diff options
author | dim <dim@FreeBSD.org> | 2011-12-30 02:58:37 +0000 |
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committer | dim <dim@FreeBSD.org> | 2011-12-30 02:58:37 +0000 |
commit | b8f81a9070810921b4d908974c477fb99ace61cb (patch) | |
tree | 2813b688cb80ad8845329c6caea0c8f8f8a256b3 | |
parent | 6e081ed8fe33bc95f21583f133b902237f803095 (diff) | |
download | FreeBSD-src-b8f81a9070810921b4d908974c477fb99ace61cb.zip FreeBSD-src-b8f81a9070810921b4d908974c477fb99ace61cb.tar.gz |
Reapply r228785 now it has been tested by Adrian. Also add comments
with the old AR_SCR_SLE_XXX values, with a short explanation why they
were changed.
Reviewed by: adrian
MFC after: 1 week
-rw-r--r-- | sys/dev/ath/ath_hal/ar5210/ar5210reg.h | 17 | ||||
-rw-r--r-- | sys/dev/ath/ath_hal/ar5211/ar5211reg.h | 17 |
2 files changed, 28 insertions, 6 deletions
diff --git a/sys/dev/ath/ath_hal/ar5210/ar5210reg.h b/sys/dev/ath/ath_hal/ar5210/ar5210reg.h index 894d9bb..7382107 100644 --- a/sys/dev/ath/ath_hal/ar5210/ar5210reg.h +++ b/sys/dev/ath/ath_hal/ar5210/ar5210reg.h @@ -245,9 +245,20 @@ #define AR_SCR_SLDUR 0x0000ffff /* sleep duration */ #define AR_SCR_SLE 0x00030000 /* sleep enable */ #define AR_SCR_SLE_S 16 -#define AR_SCR_SLE_WAKE 0x00000000 /* force wake */ -#define AR_SCR_SLE_SLP 0x00010000 /* force sleep */ -#define AR_SCR_SLE_ALLOW 0x00020000 /* allow to control sleep */ +/* + * The previous values for the following three defines were: + * + * AR_SCR_SLE_WAKE 0x00000000 + * AR_SCR_SLE_SLP 0x00010000 + * AR_SCR_SLE_ALLOW 0x00020000 + * + * However, these have been pre-shifted with AR_SCR_SLE_S. The + * OS_REG_READ() macro would attempt to shift them again, effectively + * shifting out any of the set bits completely. + */ +#define AR_SCR_SLE_WAKE 0 /* force wake */ +#define AR_SCR_SLE_SLP 1 /* force sleep */ +#define AR_SCR_SLE_ALLOW 2 /* allow to control sleep */ #define AR_SCR_BITS "\20\20SLE_SLP\21SLE_ALLOW" #define AR_INTPEND_IP 0x00000001 /* interrupt pending */ diff --git a/sys/dev/ath/ath_hal/ar5211/ar5211reg.h b/sys/dev/ath/ath_hal/ar5211/ar5211reg.h index 647f20d..93d4fc5 100644 --- a/sys/dev/ath/ath_hal/ar5211/ar5211reg.h +++ b/sys/dev/ath/ath_hal/ar5211/ar5211reg.h @@ -618,9 +618,20 @@ #define AR_SCR_SLDUR_S 0 #define AR_SCR_SLE 0x00030000 /* sleep enable mask */ #define AR_SCR_SLE_S 16 /* sleep enable bits shift */ -#define AR_SCR_SLE_WAKE 0x00000000 /* force wake */ -#define AR_SCR_SLE_SLP 0x00010000 /* force sleep */ -#define AR_SCR_SLE_NORM 0x00020000 /* sleep logic normal operation */ +/* + * The previous values for the following three defines were: + * + * AR_SCR_SLE_WAKE 0x00000000 + * AR_SCR_SLE_SLP 0x00010000 + * AR_SCR_SLE_NORM 0x00020000 + * + * However, these have been pre-shifted with AR_SCR_SLE_S. The + * OS_REG_READ() macro would attempt to shift them again, effectively + * shifting out any of the set bits completely. + */ +#define AR_SCR_SLE_WAKE 0 /* force wake */ +#define AR_SCR_SLE_SLP 1 /* force sleep */ +#define AR_SCR_SLE_NORM 2 /* sleep logic normal operation */ #define AR_SCR_SLE_UNITS 0x00000008 /* SCR units/TU */ #define AR_SCR_BITS "\20\20SLE_SLP\21SLE" |