Update the new 40G XL710 driver to Release version 1.0.0

17 files changed, 3565 insertions, 2550 deletions

diff --git a/sys/dev/i40e/i40e.h b/sys/dev/i40e/i40e.h
index 8892e09..e377c2c 100755
--- a/sys/dev/i40e/i40e.h
+++ b/sys/dev/i40e/i40e.h
@@ -92,13 +92,23 @@
 #include "i40e_prototype.h"
 
 #ifdef I40E_DEBUG
+#include <sys/sbuf.h>
+
 #define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x"
 #define MAC_FORMAT_ARGS(mac_addr) \
 	(mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \
 	(mac_addr)[4], (mac_addr)[5]
 #define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off")
 
+#define DPRINTF(...)		printf(__VA_ARGS__)
+#define DDPRINTF(dev, ...)	device_printf(dev, __VA_ARGS__)
+#define IDPRINTF(ifp, ...)	if_printf(ifp, __VA_ARGS__)
+
 // static void	i40e_dump_desc(void *, u8, u16);
+#else
+#define DPRINTF(...)
+#define DDPRINTF(...)
+#define IDPRINTF(...)
 #endif
 
 /* Tunables */
@@ -173,10 +183,21 @@
 #define I40E_ITR_NONE		3
 #define I40E_QUEUE_EOL		0x7FF
 #define I40E_MAX_FRAME		0x2600
-#define I40E_MAX_SEGS		32
-#define I40E_MAX_FILTERS	256 /* This is artificial */
+#define I40E_MAX_TX_SEGS	8 
+#define I40E_MAX_TSO_SEGS	66 
+#define I40E_SPARSE_CHAIN	6
+#define I40E_QUEUE_HUNG		0x80000000
+
+/* ERJ: hardware can support ~1.5k filters between all functions */
+#define I40E_MAX_FILTERS	256
 #define I40E_MAX_TX_BUSY	10
 
+#define I40E_NVM_VERSION_LO_SHIFT	0
+#define I40E_NVM_VERSION_LO_MASK	(0xff << I40E_NVM_VERSION_LO_SHIFT)
+#define I40E_NVM_VERSION_HI_SHIFT	12
+#define I40E_NVM_VERSION_HI_MASK	(0xf << I40E_NVM_VERSION_HI_SHIFT)
+
+
 /*
  * Interrupt Moderation parameters 
  */
@@ -200,7 +221,9 @@
 /* used in the vlan field of the filter when not a vlan */
 #define I40E_VLAN_ANY		-1
 
-#define CSUM_OFFLOAD		(CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
+#define CSUM_OFFLOAD_IPV4	(CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
+#define CSUM_OFFLOAD_IPV6	(CSUM_TCP_IPV6|CSUM_UDP_IPV6|CSUM_SCTP_IPV6)
+#define CSUM_OFFLOAD		(CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6|CSUM_TSO)
 
 /* Misc flags for i40e_vsi.flags */
 #define I40E_FLAGS_KEEP_TSO4	(1 << 0)
@@ -238,6 +261,7 @@ struct i40e_tx_buf {
 	u32		eop_index;
 	struct mbuf	*m_head;
 	bus_dmamap_t	map;
+	bus_dma_tag_t	tag;
 };
 
 struct i40e_rx_buf {
@@ -248,15 +272,6 @@ struct i40e_rx_buf {
 	bus_dmamap_t	pmap;
 };
 
-struct i40e_pkt_info {
-	u16		etype;
-	u32		elen;
-	u32		iplen;
-	struct ip	*ip;
-	struct ip6_hdr	*ip6;
-	struct tcphdr	*th;
-};
-
 /*
 ** This struct has multiple uses, multicast
 ** addresses, vlans, and mac filters all use it.
@@ -275,7 +290,7 @@ struct i40e_mac_filter {
 struct tx_ring {
         struct i40e_queue	*que;
 	struct mtx		mtx;
-	int			watchdog;
+	u32			tail;
 	struct i40e_tx_desc	*base;
 	struct i40e_dma_mem	dma;
 	u16			next_avail;
@@ -287,7 +302,8 @@ struct tx_ring {
 	struct i40e_tx_buf	*buffers;
 	volatile u16		avail;
 	u32			cmd;
-	bus_dma_tag_t		tag;
+	bus_dma_tag_t		tx_tag;
+	bus_dma_tag_t		tso_tag;
 	char			mtx_name[16];
 	struct buf_ring		*br;
 
@@ -318,6 +334,7 @@ struct rx_ring {
 	char			mtx_name[16];
 	struct i40e_rx_buf	*buffers;
 	u32			mbuf_sz;
+	u32			tail;
 	bus_dma_tag_t		htag;
 	bus_dma_tag_t		ptag;
 
@@ -407,6 +424,7 @@ struct i40e_vsi {
 	u64			hw_filters_add;
 
 	/* Misc. */
+	u64 			active_queues;
 	u64 			flags;
 };
 
@@ -433,8 +451,9 @@ i40e_get_filter(struct i40e_vsi *vsi)
 {
 	struct i40e_mac_filter  *f;
 
-	// create a new empty filter
-	f = malloc(sizeof(struct i40e_mac_filter) , M_DEVBUF, M_NOWAIT | M_ZERO);
+	/* create a new empty filter */
+	f = malloc(sizeof(struct i40e_mac_filter),
+	    M_DEVBUF, M_NOWAIT | M_ZERO);
 	SLIST_INSERT_HEAD(&vsi->ftl, f, next);
 
 	return (f);
@@ -467,6 +486,25 @@ struct i40e_sysctl_info {
 
 extern int i40e_atr_rate;
 
+/*
+** i40e_fw_version_str - format the FW and NVM version strings
+*/
+static inline char *
+i40e_fw_version_str(struct i40e_hw *hw)
+{
+	static char buf[32];
+
+	snprintf(buf, sizeof(buf),
+	    "f%d.%d a%d.%d n%02x.%02x e%08x",
+	    hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
+	    hw->aq.api_maj_ver, hw->aq.api_min_ver,
+	    (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
+	    I40E_NVM_VERSION_HI_SHIFT,
+	    (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
+	    I40E_NVM_VERSION_LO_SHIFT,
+	    hw->nvm.eetrack);
+	return buf;
+}
 
 /*********************************************************************
  *  TXRX Function prototypes
diff --git a/sys/dev/i40e/i40e_adminq.c b/sys/dev/i40e/i40e_adminq.c
index e2924f6..cca01a6 100755
--- a/sys/dev/i40e/i40e_adminq.c
+++ b/sys/dev/i40e/i40e_adminq.c
@@ -61,16 +61,37 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw)
 		hw->aq.asq.tail = I40E_VF_ATQT1;
 		hw->aq.asq.head = I40E_VF_ATQH1;
 		hw->aq.asq.len  = I40E_VF_ATQLEN1;
+		hw->aq.asq.bal  = I40E_VF_ATQBAL1;
+		hw->aq.asq.bah  = I40E_VF_ATQBAH1;
 		hw->aq.arq.tail = I40E_VF_ARQT1;
 		hw->aq.arq.head = I40E_VF_ARQH1;
 		hw->aq.arq.len  = I40E_VF_ARQLEN1;
+		hw->aq.arq.bal  = I40E_VF_ARQBAL1;
+		hw->aq.arq.bah  = I40E_VF_ARQBAH1;
+#ifdef I40E_QV
+	} else if (hw->aq_dbg_ena) {
+		hw->aq.asq.tail = I40E_GL_ATQT;
+		hw->aq.asq.head = I40E_GL_ATQH;
+		hw->aq.asq.len  = I40E_GL_ATQLEN;
+		hw->aq.asq.bal  = I40E_GL_ATQBAL;
+		hw->aq.asq.bah  = I40E_GL_ATQBAH;
+		hw->aq.arq.tail = I40E_GL_ARQT;
+		hw->aq.arq.head = I40E_GL_ARQH;
+		hw->aq.arq.len  = I40E_GL_ARQLEN;
+		hw->aq.arq.bal  = I40E_GL_ARQBAL;
+		hw->aq.arq.bah  = I40E_GL_ARQBAH;
+#endif
 	} else {
 		hw->aq.asq.tail = I40E_PF_ATQT;
 		hw->aq.asq.head = I40E_PF_ATQH;
 		hw->aq.asq.len  = I40E_PF_ATQLEN;
+		hw->aq.asq.bal  = I40E_PF_ATQBAL;
+		hw->aq.asq.bah  = I40E_PF_ATQBAH;
 		hw->aq.arq.tail = I40E_PF_ARQT;
 		hw->aq.arq.head = I40E_PF_ARQH;
 		hw->aq.arq.len  = I40E_PF_ARQLEN;
+		hw->aq.arq.bal  = I40E_PF_ARQBAL;
+		hw->aq.arq.bah  = I40E_PF_ARQBAH;
 	}
 }
 
@@ -148,6 +169,10 @@ void i40e_free_adminq_arq(struct i40e_hw *hw)
  **/
 static enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw)
 {
+#ifdef I40E_QV
+	struct i40e_aq_desc qv_desc;
+	struct i40e_aq_desc *qv_desc_on_ring;
+#endif
 	enum i40e_status_code ret_code;
 	struct i40e_aq_desc *desc;
 	struct i40e_dma_mem *bi;
@@ -176,6 +201,13 @@ static enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw)
 
 		/* now configure the descriptors for use */
 		desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
+#ifdef I40E_QV
+		/* swap the descriptor with userspace version */
+		i40e_memcpy(&qv_desc, desc, sizeof(struct i40e_aq_desc),
+			    I40E_DMA_TO_NONDMA);
+		qv_desc_on_ring = desc;
+		desc = &qv_desc;
+#endif
 
 		desc->flags = CPU_TO_LE16(I40E_AQ_FLAG_BUF);
 		if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
@@ -194,6 +226,11 @@ static enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw)
 			CPU_TO_LE32(I40E_LO_DWORD(bi->pa));
 		desc->params.external.param0 = 0;
 		desc->params.external.param1 = 0;
+#ifdef I40E_QV
+		/* put the initialized descriptor back to the ring */
+		i40e_memcpy(qv_desc_on_ring, desc, sizeof(struct i40e_aq_desc),
+			    I40E_NONDMA_TO_DMA);
+#endif
 	}
 
 alloc_arq_bufs:
@@ -306,27 +343,14 @@ static enum i40e_status_code i40e_config_asq_regs(struct i40e_hw *hw)
 	wr32(hw, hw->aq.asq.head, 0);
 	wr32(hw, hw->aq.asq.tail, 0);
 
-	if (hw->mac.type == I40E_MAC_VF) {
-		/* configure the transmit queue */
-		wr32(hw, I40E_VF_ATQBAH1,
-		    I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
-		wr32(hw, I40E_VF_ATQBAL1,
-		    I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
-		wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
-					  I40E_VF_ATQLEN1_ATQENABLE_MASK));
-		reg = rd32(hw, I40E_VF_ATQBAL1);
-	} else {
-		/* configure the transmit queue */
-		wr32(hw, I40E_PF_ATQBAH,
-		    I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
-		wr32(hw, I40E_PF_ATQBAL,
-		    I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
-		wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
-					  I40E_PF_ATQLEN_ATQENABLE_MASK));
-		reg = rd32(hw, I40E_PF_ATQBAL);
-	}
+	/* set starting point */
+	wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
+				  I40E_PF_ATQLEN_ATQENABLE_MASK));
+	wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
+	wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
 
 	/* Check one register to verify that config was applied */
+	reg = rd32(hw, hw->aq.asq.bal);
 	if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
 		ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 
@@ -348,30 +372,17 @@ static enum i40e_status_code i40e_config_arq_regs(struct i40e_hw *hw)
 	wr32(hw, hw->aq.arq.head, 0);
 	wr32(hw, hw->aq.arq.tail, 0);
 
-	if (hw->mac.type == I40E_MAC_VF) {
-		/* configure the receive queue */
-		wr32(hw, I40E_VF_ARQBAH1,
-		    I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
-		wr32(hw, I40E_VF_ARQBAL1,
-		    I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
-		wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
-					  I40E_VF_ARQLEN1_ARQENABLE_MASK));
-		reg = rd32(hw, I40E_VF_ARQBAL1);
-	} else {
-		/* configure the receive queue */
-		wr32(hw, I40E_PF_ARQBAH,
-		    I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
-		wr32(hw, I40E_PF_ARQBAL,
-		    I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
-		wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
-					  I40E_PF_ARQLEN_ARQENABLE_MASK));
-		reg = rd32(hw, I40E_PF_ARQBAL);
-	}
+	/* set starting point */
+	wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
+				  I40E_PF_ARQLEN_ARQENABLE_MASK));
+	wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
+	wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
 
 	/* Update tail in the HW to post pre-allocated buffers */
 	wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
 
 	/* Check one register to verify that config was applied */
+	reg = rd32(hw, hw->aq.arq.bal);
 	if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa))
 		ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 
@@ -510,9 +521,22 @@ enum i40e_status_code i40e_shutdown_asq(struct i40e_hw *hw)
 		return I40E_ERR_NOT_READY;
 
 	/* Stop firmware AdminQ processing */
+#ifdef I40E_QV
+	/* Do not reset registers, as Tools AQ is shared resource for QV */
+	if (!hw->aq_dbg_ena) {
+		wr32(hw, hw->aq.asq.head, 0);
+		wr32(hw, hw->aq.asq.tail, 0);
+		wr32(hw, hw->aq.asq.len, 0);
+		wr32(hw, hw->aq.asq.bal, 0);
+		wr32(hw, hw->aq.asq.bah, 0);
+	}
+#else
 	wr32(hw, hw->aq.asq.head, 0);
 	wr32(hw, hw->aq.asq.tail, 0);
 	wr32(hw, hw->aq.asq.len, 0);
+	wr32(hw, hw->aq.asq.bal, 0);
+	wr32(hw, hw->aq.asq.bah, 0);
+#endif
 
 	/* make sure spinlock is available */
 	i40e_acquire_spinlock(&hw->aq.asq_spinlock);
@@ -541,9 +565,22 @@ enum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw)
 		return I40E_ERR_NOT_READY;
 
 	/* Stop firmware AdminQ processing */
+#ifdef I40E_QV
+	/* Do not reset registers, as Tools AQ is shared resource for QV */
+	if (!hw->aq_dbg_ena) {
+		wr32(hw, hw->aq.arq.head, 0);
+		wr32(hw, hw->aq.arq.tail, 0);
+		wr32(hw, hw->aq.arq.len, 0);
+		wr32(hw, hw->aq.arq.bal, 0);
+		wr32(hw, hw->aq.arq.bah, 0);
+	}
+#else
 	wr32(hw, hw->aq.arq.head, 0);
 	wr32(hw, hw->aq.arq.tail, 0);
 	wr32(hw, hw->aq.arq.len, 0);
+	wr32(hw, hw->aq.arq.bal, 0);
+	wr32(hw, hw->aq.arq.bah, 0);
+#endif
 
 	/* make sure spinlock is available */
 	i40e_acquire_spinlock(&hw->aq.arq_spinlock);
@@ -591,6 +628,9 @@ enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
 	/* Set up register offsets */
 	i40e_adminq_init_regs(hw);
 
+	/* setup ASQ command write back timeout */
+	hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
+
 	/* allocate the ASQ */
 	ret_code = i40e_init_asq(hw);
 	if (ret_code != I40E_SUCCESS)
@@ -627,16 +667,19 @@ enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
 	i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
 	hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
 
-#ifdef FORTVILLE_A0_SUPPORT
-	if (hw->aq.api_maj_ver != I40E_FW_API_VERSION_MAJOR ||
-	    !((hw->aq.api_min_ver == I40E_FW_API_VERSION_MINOR) ||
-	      (hw->aq.api_min_ver == I40E_FW_API_VERSION_A0_MINOR))) {
+#ifdef I40E_QV
+	if (!hw->qv_force_init) {
+		if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
+			ret_code = I40E_ERR_FIRMWARE_API_VERSION;
+			goto init_adminq_free_arq;
+		}
+	}
 #else
 	if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
-#endif
 		ret_code = I40E_ERR_FIRMWARE_API_VERSION;
 		goto init_adminq_free_arq;
 	}
+#endif
 
 	/* pre-emptive resource lock release */
 	i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
@@ -671,8 +714,16 @@ enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw)
 {
 	enum i40e_status_code ret_code = I40E_SUCCESS;
 
+#ifdef I40E_QV
+	/* This command is not supported for Tools AQ */
+	if (!hw->aq_dbg_ena) {
+		if (i40e_check_asq_alive(hw))
+			i40e_aq_queue_shutdown(hw, TRUE);
+	}
+#else
 	if (i40e_check_asq_alive(hw))
 		i40e_aq_queue_shutdown(hw, TRUE);
+#endif
 
 	i40e_shutdown_asq(hw);
 	i40e_shutdown_arq(hw);
@@ -692,6 +743,10 @@ enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw)
  **/
 u16 i40e_clean_asq(struct i40e_hw *hw)
 {
+#ifdef I40E_QV
+	struct i40e_aq_desc qv_desc = {0};
+	struct i40e_aq_desc *qv_desc_on_ring;
+#endif /* I40E_QV */
 	struct i40e_adminq_ring *asq = &(hw->aq.asq);
 	struct i40e_asq_cmd_details *details;
 	u16 ntc = asq->next_to_clean;
@@ -700,6 +755,13 @@ u16 i40e_clean_asq(struct i40e_hw *hw)
 
 	desc = I40E_ADMINQ_DESC(*asq, ntc);
 	details = I40E_ADMINQ_DETAILS(*asq, ntc);
+#ifdef I40E_QV
+	/* copy the descriptor from ring to userspace buffer */
+	i40e_memcpy(&qv_desc, desc, sizeof(struct i40e_aq_desc),
+		     I40E_DMA_TO_NONDMA);
+	qv_desc_on_ring = desc;
+	desc = &qv_desc;
+#endif /* I40E_QV */
 	while (rd32(hw, hw->aq.asq.head) != ntc) {
 		i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 			   "%s: ntc %d head %d.\n", __FUNCTION__, ntc,
@@ -714,11 +776,23 @@ u16 i40e_clean_asq(struct i40e_hw *hw)
 		}
 		i40e_memset(desc, 0, sizeof(*desc), I40E_DMA_MEM);
 		i40e_memset(details, 0, sizeof(*details), I40E_NONDMA_MEM);
+#ifdef I40E_QV
+		/* copy the descriptor from userspace buffer to ring */
+		i40e_memcpy(qv_desc_on_ring, desc,
+			    sizeof(struct i40e_aq_desc), I40E_NONDMA_TO_DMA);
+#endif /* I40E_QV */
 		ntc++;
 		if (ntc == asq->count)
 			ntc = 0;
 		desc = I40E_ADMINQ_DESC(*asq, ntc);
 		details = I40E_ADMINQ_DETAILS(*asq, ntc);
+#ifdef I40E_QV
+		/* copy the descriptor from ring to userspace buffer */
+		i40e_memcpy(&qv_desc, desc, sizeof(struct i40e_aq_desc),
+			     I40E_DMA_TO_NONDMA);
+		qv_desc_on_ring = desc;
+		desc = &qv_desc;
+#endif /* I40E_QV */
 	}
 
 	asq->next_to_clean = ntc;
@@ -759,6 +833,10 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
 				u16  buff_size,
 				struct i40e_asq_cmd_details *cmd_details)
 {
+#ifdef I40E_QV
+	struct i40e_aq_desc qv_desc = {0};
+	struct i40e_aq_desc *qv_desc_on_ring;
+#endif /* I40E_QV */
 	enum i40e_status_code status = I40E_SUCCESS;
 	struct i40e_dma_mem *dma_buff = NULL;
 	struct i40e_asq_cmd_details *details;
@@ -855,6 +933,13 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
 	/* if the desc is available copy the temp desc to the right place */
 	i40e_memcpy(desc_on_ring, desc, sizeof(struct i40e_aq_desc),
 		    I40E_NONDMA_TO_DMA);
+#ifdef I40E_QV
+	/* copy the descriptor from ring to userspace buffer */
+	i40e_memcpy(&qv_desc, desc_on_ring, sizeof(struct i40e_aq_desc),
+		     I40E_DMA_TO_NONDMA);
+	qv_desc_on_ring = desc_on_ring;
+	desc_on_ring = &qv_desc;
+#endif /* I40E_QV */
 
 	/* if buff is not NULL assume indirect command */
 	if (buff != NULL) {
@@ -871,11 +956,17 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
 				CPU_TO_LE32(I40E_HI_DWORD(dma_buff->pa));
 		desc_on_ring->params.external.addr_low =
 				CPU_TO_LE32(I40E_LO_DWORD(dma_buff->pa));
+#ifdef I40E_QV
+		/* copy the descriptor from userspace buffer to ring */
+		i40e_memcpy(qv_desc_on_ring, desc_on_ring,
+			    sizeof(struct i40e_aq_desc), I40E_NONDMA_TO_DMA);
+#endif /* I40E_QV */
 	}
 
 	/* bump the tail */
 	i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
-	i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
+	i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
+		      buff, buff_size);
 	(hw->aq.asq.next_to_use)++;
 	if (hw->aq.asq.next_to_use == hw->aq.asq.count)
 		hw->aq.asq.next_to_use = 0;
@@ -890,6 +981,11 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
 		u32 delay_len = 10;
 
 		do {
+#ifdef I40E_QV
+			/* copy the descriptor from ring to user buffer */
+			i40e_memcpy(desc_on_ring, qv_desc_on_ring,
+			    sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA);
+#endif /* I40E_QV */
 			/* AQ designers suggest use of head for better
 			 * timing reliability than DD bit
 			 */
@@ -898,11 +994,15 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
 			/* ugh! delay while spin_lock */
 			i40e_usec_delay(delay_len);
 			total_delay += delay_len;
-		} while (total_delay <  I40E_ASQ_CMD_TIMEOUT);
+		} while (total_delay < hw->aq.asq_cmd_timeout);
 	}
 
 	/* if ready, copy the desc back to temp */
 	if (i40e_asq_done(hw)) {
+#ifdef I40E_QV
+		/* Swap pointer back */
+		desc_on_ring = qv_desc_on_ring;
+#endif /* I40E_QV */
 		i40e_memcpy(desc, desc_on_ring, sizeof(struct i40e_aq_desc),
 			    I40E_DMA_TO_NONDMA);
 		if (buff != NULL)
@@ -926,11 +1026,9 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
 		hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
 	}
 
-	if (desc->datalen == buff_size) {
-		i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
-			   "AQTX: desc and buffer writeback:\n");
-		i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff);
-	}
+	i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
+		   "AQTX: desc and buffer writeback:\n");
+	i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
 
 	/* update the error if time out occurred */
 	if ((!cmd_completed) &&
@@ -981,6 +1079,10 @@ enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
 					     struct i40e_arq_event_info *e,
 					     u16 *pending)
 {
+#ifdef I40E_QV
+	struct i40e_aq_desc qv_desc = {0};
+	struct i40e_aq_desc *qv_desc_on_ring;
+#endif /* I40E_QV */
 	enum i40e_status_code ret_code = I40E_SUCCESS;
 	u16 ntc = hw->aq.arq.next_to_clean;
 	struct i40e_aq_desc *desc;
@@ -1006,6 +1108,13 @@ enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
 
 	/* now clean the next descriptor */
 	desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
+#ifdef I40E_QV
+	/* copy the descriptor from ring to userspace buffer */
+	i40e_memcpy(&qv_desc, desc, sizeof(struct i40e_aq_desc),
+		     I40E_DMA_TO_NONDMA);
+	qv_desc_on_ring = desc;
+	desc = &qv_desc;
+#endif /* I40E_QV */
 	desc_idx = ntc;
 
 	flags = LE16_TO_CPU(desc->flags);
@@ -1017,19 +1126,20 @@ enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
 			   I40E_DEBUG_AQ_MESSAGE,
 			   "AQRX: Event received with error 0x%X.\n",
 			   hw->aq.arq_last_status);
-	} else {
-		i40e_memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc),
-			    I40E_DMA_TO_NONDMA);
-		datalen = LE16_TO_CPU(desc->datalen);
-		e->msg_size = min(datalen, e->msg_size);
-		if (e->msg_buf != NULL && (e->msg_size != 0))
-			i40e_memcpy(e->msg_buf,
-				    hw->aq.arq.r.arq_bi[desc_idx].va,
-				    e->msg_size, I40E_DMA_TO_NONDMA);
 	}
 
+	i40e_memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc),
+		    I40E_DMA_TO_NONDMA);
+	datalen = LE16_TO_CPU(desc->datalen);
+	e->msg_size = min(datalen, e->msg_size);
+	if (e->msg_buf != NULL && (e->msg_size != 0))
+		i40e_memcpy(e->msg_buf,
+			    hw->aq.arq.r.arq_bi[desc_idx].va,
+			    e->msg_size, I40E_DMA_TO_NONDMA);
+
 	i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
-	i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf);
+	i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
+		      hw->aq.arq_buf_size);
 
 	/* Restore the original datalen and buffer address in the desc,
 	 * FW updates datalen to indicate the event message
@@ -1044,6 +1154,11 @@ enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
 	desc->datalen = CPU_TO_LE16((u16)bi->size);
 	desc->params.external.addr_high = CPU_TO_LE32(I40E_HI_DWORD(bi->pa));
 	desc->params.external.addr_low = CPU_TO_LE32(I40E_LO_DWORD(bi->pa));
+#ifdef I40E_QV
+	/* copy the descriptor from userspace buffer to ring */
+	i40e_memcpy(qv_desc_on_ring, desc,
+		    sizeof(struct i40e_aq_desc), I40E_NONDMA_TO_DMA);
+#endif /* I40E_QV */
 
 	/* set tail = the last cleaned desc index. */
 	wr32(hw, hw->aq.arq.tail, ntc);
diff --git a/sys/dev/i40e/i40e_adminq.h b/sys/dev/i40e/i40e_adminq.h
index 1dd645e..f5a33ea 100755
--- a/sys/dev/i40e/i40e_adminq.h
+++ b/sys/dev/i40e/i40e_adminq.h
@@ -64,6 +64,8 @@ struct i40e_adminq_ring {
 	u32 head;
 	u32 tail;
 	u32 len;
+	u32 bah;
+	u32 bal;
 };
 
 /* ASQ transaction details */
@@ -90,6 +92,7 @@ struct i40e_arq_event_info {
 struct i40e_adminq_info {
 	struct i40e_adminq_ring arq;    /* receive queue */
 	struct i40e_adminq_ring asq;    /* send queue */
+	u32 asq_cmd_timeout;            /* send queue cmd write back timeout*/
 	u16 num_arq_entries;            /* receive queue depth */
 	u16 num_asq_entries;            /* send queue depth */
 	u16 arq_buf_size;               /* receive queue buffer size */
@@ -110,8 +113,8 @@ struct i40e_adminq_info {
 };
 
 /* general information */
-#define I40E_AQ_LARGE_BUF	512
-#define I40E_ASQ_CMD_TIMEOUT	100000  /* usecs */
+#define I40E_AQ_LARGE_BUF		512
+#define I40E_ASQ_CMD_TIMEOUT		100000 /* usecs */
 
 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
 				       u16 opcode);
diff --git a/sys/dev/i40e/i40e_adminq_cmd.h b/sys/dev/i40e/i40e_adminq_cmd.h
index 77a1afb..09b5887 100755
--- a/sys/dev/i40e/i40e_adminq_cmd.h
+++ b/sys/dev/i40e/i40e_adminq_cmd.h
@@ -43,9 +43,6 @@
 
 #define I40E_FW_API_VERSION_MAJOR  0x0001
 #define I40E_FW_API_VERSION_MINOR  0x0002
-#ifdef FORTVILLE_A0_SUPPORT
-#define I40E_FW_API_VERSION_A0_MINOR  0x0000
-#endif
 
 struct i40e_aq_desc {
 	__le16 flags;
@@ -698,9 +695,6 @@ struct i40e_aqc_add_get_update_vsi {
 #define I40E_AQ_VSI_TYPE_PF             0x2
 #define I40E_AQ_VSI_TYPE_EMP_MNG        0x3
 #define I40E_AQ_VSI_FLAG_CASCADED_PV    0x4
-#ifdef FORTVILLE_A0_SUPPORT
-#define I40E_AQ_VSI_FLAG_CLOUD_VSI      0x8
-#endif
 	__le32 addr_high;
 	__le32 addr_low;
 };
@@ -1223,11 +1217,6 @@ struct i40e_aqc_add_remove_cloud_filters_element_data {
 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT                 0
 #define I40E_AQC_ADD_CLOUD_FILTER_MASK                  (0x3F << \
 					I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
-#ifdef FORTVILLE_A0_SUPPORT
-#define I40E_AQC_ADD_CLOUD_FILTER_OIP_GRE               0x0002
-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_GRE        0x0004
-#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_VNL        0x0007
-#endif
 /* 0x0000 reserved */
 #define I40E_AQC_ADD_CLOUD_FILTER_OIP                   0x0001
 /* 0x0002 reserved */
@@ -2012,22 +2001,6 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
 
 /* Add Udp Tunnel command and completion (direct 0x0B00) */
 struct i40e_aqc_add_udp_tunnel {
-#ifdef FORTVILLE_A0_SUPPORT
-	__le16 udp_port;
-	u8     header_len; /* in DWords, 1 to 15 */
-	u8     protocol_type;
-#define I40E_AQC_TUNNEL_TYPE_TEREDO	0x0
-#define I40E_AQC_TUNNEL_TYPE_VXLAN	0x2
-#define I40E_AQC_TUNNEL_TYPE_NGE	0x3
-	u8     variable_udp_length;
-#define I40E_AQC_TUNNEL_FIXED_UDP_LENGTH	0x0
-#define I40E_AQC_TUNNEL_VARIABLE_UDP_LENGTH	0x1
-	u8		udp_key_index;
-#define I40E_AQC_TUNNEL_KEY_INDEX_VXLAN			0x0
-#define I40E_AQC_TUNNEL_KEY_INDEX_NGE			0x1
-#define I40E_AQC_TUNNEL_KEY_INDEX_PROPRIETARY_UDP	0x2
-	u8		reserved[10];
-#else
 	__le16 udp_port;
 	u8     reserved0[3];
 	u8     protocol_type;
@@ -2035,7 +2008,6 @@ struct i40e_aqc_add_udp_tunnel {
 #define I40E_AQC_TUNNEL_TYPE_NGE	0x01
 #define I40E_AQC_TUNNEL_TYPE_TEREDO	0x10
 	u8     reserved1[10];
-#endif
 };
 
 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
@@ -2056,13 +2028,7 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
 struct i40e_aqc_remove_udp_tunnel {
 	u8     reserved[2];
 	u8     index; /* 0 to 15 */
-#ifdef FORTVILLE_A0_SUPPORT
-	u8     pf_filters;
-	u8     total_filters;
-	u8     reserved2[11];
-#else
 	u8     reserved2[13];
-#endif
 };
 
 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
@@ -2072,37 +2038,13 @@ struct i40e_aqc_del_udp_tunnel_completion {
 	u8     index; /* 0 to 15 */
 	u8     multiple_pfs;
 	u8     total_filters_used;
-#ifdef FORTVILLE_A0_SUPPORT
-	u8     reserved;
-	u8     tunnels_free;
-	u8     reserved1[9];
-#else
 	u8     reserved1[11];
-#endif
 };
 
 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
 
 /* tunnel key structure 0x0B10 */
 
-#ifdef FORTVILLE_A0_SUPPORT
-struct i40e_aqc_tunnel_key_structure_A0 {
-	__le16     key1_off;
-	__le16     key1_len;
-	__le16     key2_off;
-	__le16     key2_len;
-	__le16     flags;
-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
-/* response flags */
-#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS    0x01
-#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED   0x02
-#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
-	u8         resreved[6];
-};
-
-I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
-
-#endif
 struct i40e_aqc_tunnel_key_structure {
 	u8	key1_off;
 	u8	key2_off;
diff --git a/sys/dev/i40e/i40e_common.c b/sys/dev/i40e/i40e_common.c
index 53a43be..ec0fd0c 100755
--- a/sys/dev/i40e/i40e_common.c
+++ b/sys/dev/i40e/i40e_common.c
@@ -52,9 +52,6 @@ static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
 
 	if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
 		switch (hw->device_id) {
-#if defined(FORTVILLE_A0_SUPPORT) || defined(I40E_FPGA_SUPPORT)
-		case I40E_DEV_ID_FPGA_A:
-#endif
 		case I40E_DEV_ID_SFP_XL710:
 		case I40E_DEV_ID_QEMU:
 		case I40E_DEV_ID_KX_A:
@@ -63,9 +60,6 @@ static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
 		case I40E_DEV_ID_QSFP_A:
 		case I40E_DEV_ID_QSFP_B:
 		case I40E_DEV_ID_QSFP_C:
-#ifdef FORTVILLE_A0_SUPPORT
-		case I40E_DEV_ID_10G_BASE_T:
-#endif
 			hw->mac.type = I40E_MAC_XL710;
 			break;
 		case I40E_DEV_ID_VF:
@@ -91,13 +85,15 @@ static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  * @mask: debug mask
  * @desc: pointer to admin queue descriptor
  * @buffer: pointer to command buffer
+ * @buf_len: max length of buffer
  *
  * Dumps debug log about adminq command with descriptor contents.
  **/
 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
-		   void *buffer)
+		   void *buffer, u16 buf_len)
 {
 	struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
+	u16 len = LE16_TO_CPU(aq_desc->datalen);
 	u8 *aq_buffer = (u8 *)buffer;
 	u32 data[4];
 	u32 i = 0;
@@ -121,7 +117,9 @@ void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 	if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 		i40e_memset(data, 0, sizeof(data), I40E_NONDMA_MEM);
 		i40e_debug(hw, mask, "AQ CMD Buffer:\n");
-		for (i = 0; i < LE16_TO_CPU(aq_desc->datalen); i++) {
+		if (buf_len < len)
+			len = buf_len;
+		for (i = 0; i < len; i++) {
 			data[((i % 16) / 4)] |=
 				((u32)aq_buffer[i]) << (8 * (i % 4));
 			if ((i % 16) == 15) {
@@ -572,7 +570,6 @@ enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 		break;
 	default:
 		return I40E_ERR_DEVICE_NOT_SUPPORTED;
-		break;
 	}
 
 	hw->phy.get_link_info = TRUE;
@@ -712,8 +709,10 @@ void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
 	u32 reg_block = 0;
 	u32 reg_val;
 
-	if (abs_queue_idx >= 128)
+	if (abs_queue_idx >= 128) {
 		reg_block = abs_queue_idx / 128;
+		abs_queue_idx %= 128;
+	}
 
 	reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
 	reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
@@ -762,6 +761,8 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
 	switch (hw->phy.link_info.phy_type) {
 	case I40E_PHY_TYPE_10GBASE_SR:
 	case I40E_PHY_TYPE_10GBASE_LR:
+	case I40E_PHY_TYPE_1000BASE_SX:
+	case I40E_PHY_TYPE_1000BASE_LX:
 	case I40E_PHY_TYPE_40GBASE_SR4:
 	case I40E_PHY_TYPE_40GBASE_LR4:
 		media = I40E_MEDIA_TYPE_FIBER;
@@ -797,11 +798,7 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
 	return media;
 }
 
-#ifndef FORTVILLE_A0_SUPPORT
 #define I40E_PF_RESET_WAIT_COUNT	100
-#else
-#define I40E_PF_RESET_WAIT_COUNT	200
-#endif
 /**
  * i40e_pf_reset - Reset the PF
  * @hw: pointer to the hardware structure
@@ -878,6 +875,99 @@ enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
 }
 
 /**
+ * i40e_clear_hw - clear out any left over hw state
+ * @hw: pointer to the hw struct
+ *
+ * Clear queues and interrupts, typically called at init time,
+ * but after the capabilities have been found so we know how many
+ * queues and msix vectors have been allocated.
+ **/
+void i40e_clear_hw(struct i40e_hw *hw)
+{
+	u32 num_queues, base_queue;
+	u32 num_pf_int;
+	u32 num_vf_int;
+	u32 num_vfs;
+	u32 i, j;
+	u32 val;
+	u32 eol = 0x7ff;
+
+	/* get number of interrupts, queues, and vfs */
+	val = rd32(hw, I40E_GLPCI_CNF2);
+	num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
+			I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
+	num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
+			I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
+
+	val = rd32(hw, I40E_PFLAN_QALLOC);
+	base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
+			I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
+	j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
+			I40E_PFLAN_QALLOC_LASTQ_SHIFT;
+	if (val & I40E_PFLAN_QALLOC_VALID_MASK)
+		num_queues = (j - base_queue) + 1;
+	else
+		num_queues = 0;
+
+	val = rd32(hw, I40E_PF_VT_PFALLOC);
+	i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
+			I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
+	j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
+			I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
+	if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
+		num_vfs = (j - i) + 1;
+	else
+		num_vfs = 0;
+
+	/* stop all the interrupts */
+	wr32(hw, I40E_PFINT_ICR0_ENA, 0);
+	val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
+	for (i = 0; i < num_pf_int - 2; i++)
+		wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
+
+	/* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
+	val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
+	wr32(hw, I40E_PFINT_LNKLST0, val);
+	for (i = 0; i < num_pf_int - 2; i++)
+		wr32(hw, I40E_PFINT_LNKLSTN(i), val);
+	val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
+	for (i = 0; i < num_vfs; i++)
+		wr32(hw, I40E_VPINT_LNKLST0(i), val);
+	for (i = 0; i < num_vf_int - 2; i++)
+		wr32(hw, I40E_VPINT_LNKLSTN(i), val);
+
+	/* warn the HW of the coming Tx disables */
+	for (i = 0; i < num_queues; i++) {
+		u32 abs_queue_idx = base_queue + i;
+		u32 reg_block = 0;
+
+		if (abs_queue_idx >= 128) {
+			reg_block = abs_queue_idx / 128;
+			abs_queue_idx %= 128;
+		}
+
+		val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
+		val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
+		val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
+		val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
+
+		wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
+	}
+	i40e_usec_delay(400);
+
+	/* stop all the queues */
+	for (i = 0; i < num_queues; i++) {
+		wr32(hw, I40E_QINT_TQCTL(i), 0);
+		wr32(hw, I40E_QTX_ENA(i), 0);
+		wr32(hw, I40E_QINT_RQCTL(i), 0);
+		wr32(hw, I40E_QRX_ENA(i), 0);
+	}
+
+	/* short wait for all queue disables to settle */
+	i40e_usec_delay(50);
+}
+
+/**
  * i40e_clear_pxe_mode - clear pxe operations mode
  * @hw: pointer to the hw struct
  *
@@ -886,16 +976,8 @@ enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
  **/
 void i40e_clear_pxe_mode(struct i40e_hw *hw)
 {
-#if defined(FORTVILLE_A0_SUPPORT) || defined(I40E_FPGA_SUPPORT)
-	u32 reg;
-
-	/* Clear single descriptor fetch/write-back mode */
-	reg = rd32(hw, I40E_GLLAN_RCTL_0);
-	wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
-#else
 	if (i40e_check_asq_alive(hw))
 		i40e_aq_clear_pxe_mode(hw, NULL);
-#endif
 }
 
 /**
@@ -1120,7 +1202,7 @@ enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
 	status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
 					      NULL);
 	if (status) {
-		*aq_failures |= I40E_SET_FC_AQ_FAIL_GET1;
+		*aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
 		return status;
 	}
 
@@ -1145,31 +1227,19 @@ enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
 
 		if (status)
 			*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
-
-		/* Get the abilities to set hw->fc.current_mode correctly */
-		status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
-						      &abilities, NULL);
-		if (status) {
-			/* Wait a little bit and try once more */
-			i40e_msec_delay(1000);
-			status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
-							      &abilities, NULL);
-		}
-		if (status) {
-			*aq_failures |= I40E_SET_FC_AQ_FAIL_GET2;
-			return status;
-		}
 	}
-	/* Copy the what was returned from get capabilities into fc */
-	if ((abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX) &&
-	    (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX))
-		hw->fc.current_mode = I40E_FC_FULL;
-	else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX)
-		hw->fc.current_mode = I40E_FC_TX_PAUSE;
-	else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX)
-		hw->fc.current_mode = I40E_FC_RX_PAUSE;
-	else
-		hw->fc.current_mode = I40E_FC_NONE;
+	/* Update the link info */
+	status = i40e_update_link_info(hw, TRUE);
+	if (status) {
+		/* Wait a little bit (on 40G cards it sometimes takes a really
+		 * long time for link to come back from the atomic reset)
+		 * and try once more
+		 */
+		i40e_msec_delay(1000);
+		status = i40e_update_link_info(hw, TRUE);
+	}
+	if (status)
+		*aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
 
 	return status;
 }
@@ -1210,7 +1280,6 @@ enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
 
 	return status;
 }
-#ifndef FORTVILLE_A0_SUPPORT
 
 /**
  * i40e_aq_clear_pxe_mode
@@ -1238,17 +1307,17 @@ enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
 
 	return status;
 }
-#endif
 
 /**
  * i40e_aq_set_link_restart_an
  * @hw: pointer to the hw struct
+ * @enable_link: if TRUE: enable link, if FALSE: disable link
  * @cmd_details: pointer to command details structure or NULL
  *
  * Sets up the link and restarts the Auto-Negotiation over the link.
  **/
 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
-				struct i40e_asq_cmd_details *cmd_details)
+		bool enable_link, struct i40e_asq_cmd_details *cmd_details)
 {
 	struct i40e_aq_desc desc;
 	struct i40e_aqc_set_link_restart_an *cmd =
@@ -1259,6 +1328,10 @@ enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
 					  i40e_aqc_opc_set_link_restart_an);
 
 	cmd->command = I40E_AQ_PHY_RESTART_AN;
+	if (enable_link)
+		cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
+	else
+		cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
 
 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
 
@@ -1859,6 +1932,14 @@ enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
 			*api_major_version = LE16_TO_CPU(resp->api_major);
 		if (api_minor_version != NULL)
 			*api_minor_version = LE16_TO_CPU(resp->api_minor);
+
+		/* A workaround to fix the API version in SW */
+		if (api_major_version && api_minor_version &&
+		    fw_major_version && fw_minor_version &&
+		    ((*api_major_version == 1) && (*api_minor_version == 1)) &&
+		    (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
+		     (*fw_major_version > 4)))
+			*api_minor_version = 2;
 	}
 
 	return status;
@@ -2271,6 +2352,35 @@ enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
 }
 
 /**
+ * i40e_aq_debug_write_register
+ * @hw: pointer to the hw struct
+ * @reg_addr: register address
+ * @reg_val: register value
+ * @cmd_details: pointer to command details structure or NULL
+ *
+ * Write to a register using the admin queue commands
+ **/
+enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
+				u32 reg_addr, u64 reg_val,
+				struct i40e_asq_cmd_details *cmd_details)
+{
+	struct i40e_aq_desc desc;
+	struct i40e_aqc_debug_reg_read_write *cmd =
+		(struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
+	enum i40e_status_code status;
+
+	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
+
+	cmd->address = CPU_TO_LE32(reg_addr);
+	cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
+	cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
+
+	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
+
+	return status;
+}
+
+/**
  * i40e_aq_get_hmc_resource_profile
  * @hw: pointer to the hw struct
  * @profile: type of profile the HMC is to be set as
@@ -3065,17 +3175,10 @@ enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
  * @filter_index: pointer to filter index
  * @cmd_details: pointer to command details structure or NULL
  **/
-#ifdef FORTVILLE_A0_SUPPORT
-enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
-				u16 udp_port, u8 header_len,
-				u8 protocol_index, u8 *filter_index,
-				struct i40e_asq_cmd_details *cmd_details)
-#else
 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
 				u16 udp_port, u8 protocol_index,
 				u8 *filter_index,
 				struct i40e_asq_cmd_details *cmd_details)
-#endif
 {
 	struct i40e_aq_desc desc;
 	struct i40e_aqc_add_udp_tunnel *cmd =
@@ -3087,9 +3190,6 @@ enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
 
 	cmd->udp_port = CPU_TO_LE16(udp_port);
-#ifdef FORTVILLE_A0_SUPPORT
-	cmd->header_len = header_len;
-#endif
 	cmd->protocol_type = protocol_index;
 
 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
@@ -3925,9 +4025,6 @@ static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
 	u32 fcoe_cntx_size, fcoe_filt_size;
 	u32 pe_cntx_size, pe_filt_size;
 	u32 fcoe_fmax;
-#ifdef FORTVILLE_A0_SUPPORT
-	u32 pe_fmax;
-#endif
 
 	u32 val;
 
@@ -4002,15 +4099,6 @@ static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
 		     >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
 	if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
 		return I40E_ERR_INVALID_SIZE;
-#ifdef FORTVILLE_A0_SUPPORT
-
-	/* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
-	val = rd32(hw, I40E_GLHMC_PEXFMAX);
-	pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
-		   >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
-	if (pe_filt_size + pe_cntx_size >  pe_fmax)
-		return I40E_ERR_INVALID_SIZE;
-#endif
 
 	return I40E_SUCCESS;
 }
@@ -4081,31 +4169,6 @@ enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
 
 	return I40E_SUCCESS;
 }
-#ifdef FORTVILLE_A0_SUPPORT
-
-/**
- * i40e_set_tag_alloc_method
- * @hw: pointer to the hardware structure
- * @debug: a bool to indicates if the debug mode tag alloc needs to be set.
- *
- * Note: Enable debug mode tag allocation method if the Extended PCIE Tags are
- * disabled as a workaround to avoid Rx stall when the device comes up on PCI
- * Gen 2 slot or if the Extended Tags are disabled on Gen 3 slot. If the
- * Extended tags are enabled this workaround should not be applied since it
- * would cause unnecessary performance degradation.
- */
-void i40e_set_tag_alloc_method(struct i40e_hw *hw, bool debug)
-{
-	u32 val;
-	val = rd32(hw, I40E_GLPCI_PCITEST2);
-
-	if (debug)
-		val |= I40E_GLPCI_PCITEST2_TAG_ALLOC_MASK;
-	else
-		val &= ~I40E_GLPCI_PCITEST2_TAG_ALLOC_MASK;
-	wr32(hw, I40E_GLPCI_PCITEST2, val);
-}
-#endif
 
 /**
  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
diff --git a/sys/dev/i40e/i40e_hmc.h b/sys/dev/i40e/i40e_hmc.h
index 6979917..cba325f 100755
--- a/sys/dev/i40e/i40e_hmc.h
+++ b/sys/dev/i40e/i40e_hmc.h
@@ -39,7 +39,6 @@
 
 /* forward-declare the HW struct for the compiler */
 struct i40e_hw;
-enum i40e_status_code;
 
 #define I40E_HMC_INFO_SIGNATURE		0x484D5347 /* HMSG */
 #define I40E_HMC_PD_CNT_IN_SD		512
@@ -136,7 +135,7 @@ struct i40e_hmc_info {
 		((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<		\
 		I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) |			\
 		(1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT);		\
-	val3 = (sd_index) | (1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);	\
+	val3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);	\
 	wr32((hw), I40E_PFHMC_SDDATAHIGH, val1);			\
 	wr32((hw), I40E_PFHMC_SDDATALOW, val2);				\
 	wr32((hw), I40E_PFHMC_SDCMD, val3);				\
@@ -155,7 +154,7 @@ struct i40e_hmc_info {
 		I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |		\
 		((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<		\
 		I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT);			\
-	val3 = (sd_index) | (1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);	\
+	val3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);	\
 	wr32((hw), I40E_PFHMC_SDDATAHIGH, 0);				\
 	wr32((hw), I40E_PFHMC_SDDATALOW, val2);				\
 	wr32((hw), I40E_PFHMC_SDCMD, val3);				\
diff --git a/sys/dev/i40e/i40e_lan_hmc.c b/sys/dev/i40e/i40e_lan_hmc.c
index 8cd27ea..91c20e8 100755
--- a/sys/dev/i40e/i40e_lan_hmc.c
+++ b/sys/dev/i40e/i40e_lan_hmc.c
@@ -425,7 +425,6 @@ enum i40e_status_code i40e_create_lan_hmc_object(struct i40e_hw *hw,
 			default:
 				ret_code = I40E_ERR_INVALID_SD_TYPE;
 				goto exit;
-				break;
 			}
 		}
 	}
@@ -510,7 +509,6 @@ try_type_paged:
 		DEBUGOUT1("i40e_configure_lan_hmc: Unknown SD type: %d\n",
 			  ret_code);
 		goto configure_lan_hmc_out;
-		break;
 	}
 
 	/* Configure and program the FPM registers so objects can be created */
@@ -755,6 +753,381 @@ static struct i40e_context_ele i40e_hmc_rxq_ce_info[] = {
 };
 
 /**
+ * i40e_write_byte - replace HMC context byte
+ * @hmc_bits: pointer to the HMC memory
+ * @ce_info: a description of the struct to be read from
+ * @src: the struct to be read from
+ **/
+static void i40e_write_byte(u8 *hmc_bits,
+			    struct i40e_context_ele *ce_info,
+			    u8 *src)
+{
+	u8 src_byte, dest_byte, mask;
+	u8 *from, *dest;
+	u16 shift_width;
+
+	/* copy from the next struct field */
+	from = src + ce_info->offset;
+
+	/* prepare the bits and mask */
+	shift_width = ce_info->lsb % 8;
+	mask = ((u8)1 << ce_info->width) - 1;
+
+	src_byte = *from;
+	src_byte &= mask;
+
+	/* shift to correct alignment */
+	mask <<= shift_width;
+	src_byte <<= shift_width;
+
+	/* get the current bits from the target bit string */
+	dest = hmc_bits + (ce_info->lsb / 8);
+
+	i40e_memcpy(&dest_byte, dest, sizeof(dest_byte), I40E_DMA_TO_NONDMA);
+
+	dest_byte &= ~mask;	/* get the bits not changing */
+	dest_byte |= src_byte;	/* add in the new bits */
+
+	/* put it all back */
+	i40e_memcpy(dest, &dest_byte, sizeof(dest_byte), I40E_NONDMA_TO_DMA);
+}
+
+/**
+ * i40e_write_word - replace HMC context word
+ * @hmc_bits: pointer to the HMC memory
+ * @ce_info: a description of the struct to be read from
+ * @src: the struct to be read from
+ **/
+static void i40e_write_word(u8 *hmc_bits,
+			    struct i40e_context_ele *ce_info,
+			    u8 *src)
+{
+	u16 src_word, mask;
+	u8 *from, *dest;
+	u16 shift_width;
+	__le16 dest_word;
+
+	/* copy from the next struct field */
+	from = src + ce_info->offset;
+
+	/* prepare the bits and mask */
+	shift_width = ce_info->lsb % 8;
+	mask = ((u16)1 << ce_info->width) - 1;
+
+	/* don't swizzle the bits until after the mask because the mask bits
+	 * will be in a different bit position on big endian machines
+	 */
+	src_word = *(u16 *)from;
+	src_word &= mask;
+
+	/* shift to correct alignment */
+	mask <<= shift_width;
+	src_word <<= shift_width;
+
+	/* get the current bits from the target bit string */
+	dest = hmc_bits + (ce_info->lsb / 8);
+
+	i40e_memcpy(&dest_word, dest, sizeof(dest_word), I40E_DMA_TO_NONDMA);
+
+	dest_word &= ~(CPU_TO_LE16(mask));	/* get the bits not changing */
+	dest_word |= CPU_TO_LE16(src_word);	/* add in the new bits */
+
+	/* put it all back */
+	i40e_memcpy(dest, &dest_word, sizeof(dest_word), I40E_NONDMA_TO_DMA);
+}
+
+/**
+ * i40e_write_dword - replace HMC context dword
+ * @hmc_bits: pointer to the HMC memory
+ * @ce_info: a description of the struct to be read from
+ * @src: the struct to be read from
+ **/
+static void i40e_write_dword(u8 *hmc_bits,
+			     struct i40e_context_ele *ce_info,
+			     u8 *src)
+{
+	u32 src_dword, mask;
+	u8 *from, *dest;
+	u16 shift_width;
+	__le32 dest_dword;
+
+	/* copy from the next struct field */
+	from = src + ce_info->offset;
+
+	/* prepare the bits and mask */
+	shift_width = ce_info->lsb % 8;
+
+	/* if the field width is exactly 32 on an x86 machine, then the shift
+	 * operation will not work because the SHL instructions count is masked
+	 * to 5 bits so the shift will do nothing
+	 */
+	if (ce_info->width < 32)
+		mask = ((u32)1 << ce_info->width) - 1;
+	else
+		mask = 0xFFFFFFFF;
+
+	/* don't swizzle the bits until after the mask because the mask bits
+	 * will be in a different bit position on big endian machines
+	 */
+	src_dword = *(u32 *)from;
+	src_dword &= mask;
+
+	/* shift to correct alignment */
+	mask <<= shift_width;
+	src_dword <<= shift_width;
+
+	/* get the current bits from the target bit string */
+	dest = hmc_bits + (ce_info->lsb / 8);
+
+	i40e_memcpy(&dest_dword, dest, sizeof(dest_dword), I40E_DMA_TO_NONDMA);
+
+	dest_dword &= ~(CPU_TO_LE32(mask));	/* get the bits not changing */
+	dest_dword |= CPU_TO_LE32(src_dword);	/* add in the new bits */
+
+	/* put it all back */
+	i40e_memcpy(dest, &dest_dword, sizeof(dest_dword), I40E_NONDMA_TO_DMA);
+}
+
+/**
+ * i40e_write_qword - replace HMC context qword
+ * @hmc_bits: pointer to the HMC memory
+ * @ce_info: a description of the struct to be read from
+ * @src: the struct to be read from
+ **/
+static void i40e_write_qword(u8 *hmc_bits,
+			     struct i40e_context_ele *ce_info,
+			     u8 *src)
+{
+	u64 src_qword, mask;
+	u8 *from, *dest;
+	u16 shift_width;
+	__le64 dest_qword;
+
+	/* copy from the next struct field */
+	from = src + ce_info->offset;
+
+	/* prepare the bits and mask */
+	shift_width = ce_info->lsb % 8;
+
+	/* if the field width is exactly 64 on an x86 machine, then the shift
+	 * operation will not work because the SHL instructions count is masked
+	 * to 6 bits so the shift will do nothing
+	 */
+	if (ce_info->width < 64)
+		mask = ((u64)1 << ce_info->width) - 1;
+	else
+		mask = 0xFFFFFFFFFFFFFFFFUL;
+
+	/* don't swizzle the bits until after the mask because the mask bits
+	 * will be in a different bit position on big endian machines
+	 */
+	src_qword = *(u64 *)from;
+	src_qword &= mask;
+
+	/* shift to correct alignment */
+	mask <<= shift_width;
+	src_qword <<= shift_width;
+
+	/* get the current bits from the target bit string */
+	dest = hmc_bits + (ce_info->lsb / 8);
+
+	i40e_memcpy(&dest_qword, dest, sizeof(dest_qword), I40E_DMA_TO_NONDMA);
+
+	dest_qword &= ~(CPU_TO_LE64(mask));	/* get the bits not changing */
+	dest_qword |= CPU_TO_LE64(src_qword);	/* add in the new bits */
+
+	/* put it all back */
+	i40e_memcpy(dest, &dest_qword, sizeof(dest_qword), I40E_NONDMA_TO_DMA);
+}
+
+/**
+ * i40e_read_byte - read HMC context byte into struct
+ * @hmc_bits: pointer to the HMC memory
+ * @ce_info: a description of the struct to be filled
+ * @dest: the struct to be filled
+ **/
+static void i40e_read_byte(u8 *hmc_bits,
+			   struct i40e_context_ele *ce_info,
+			   u8 *dest)
+{
+	u8 dest_byte, mask;
+	u8 *src, *target;
+	u16 shift_width;
+
+	/* prepare the bits and mask */
+	shift_width = ce_info->lsb % 8;
+	mask = ((u8)1 << ce_info->width) - 1;
+
+	/* shift to correct alignment */
+	mask <<= shift_width;
+
+	/* get the current bits from the src bit string */
+	src = hmc_bits + (ce_info->lsb / 8);
+
+	i40e_memcpy(&dest_byte, src, sizeof(dest_byte), I40E_DMA_TO_NONDMA);
+
+	dest_byte &= ~(mask);
+
+	dest_byte >>= shift_width;
+
+	/* get the address from the struct field */
+	target = dest + ce_info->offset;
+
+	/* put it back in the struct */
+	i40e_memcpy(target, &dest_byte, sizeof(dest_byte), I40E_NONDMA_TO_DMA);
+}
+
+/**
+ * i40e_read_word - read HMC context word into struct
+ * @hmc_bits: pointer to the HMC memory
+ * @ce_info: a description of the struct to be filled
+ * @dest: the struct to be filled
+ **/
+static void i40e_read_word(u8 *hmc_bits,
+			   struct i40e_context_ele *ce_info,
+			   u8 *dest)
+{
+	u16 dest_word, mask;
+	u8 *src, *target;
+	u16 shift_width;
+	__le16 src_word;
+
+	/* prepare the bits and mask */
+	shift_width = ce_info->lsb % 8;
+	mask = ((u16)1 << ce_info->width) - 1;
+
+	/* shift to correct alignment */
+	mask <<= shift_width;
+
+	/* get the current bits from the src bit string */
+	src = hmc_bits + (ce_info->lsb / 8);
+
+	i40e_memcpy(&src_word, src, sizeof(src_word), I40E_DMA_TO_NONDMA);
+
+	/* the data in the memory is stored as little endian so mask it
+	 * correctly
+	 */
+	src_word &= ~(CPU_TO_LE16(mask));
+
+	/* get the data back into host order before shifting */
+	dest_word = LE16_TO_CPU(src_word);
+
+	dest_word >>= shift_width;
+
+	/* get the address from the struct field */
+	target = dest + ce_info->offset;
+
+	/* put it back in the struct */
+	i40e_memcpy(target, &dest_word, sizeof(dest_word), I40E_NONDMA_TO_DMA);
+}
+
+/**
+ * i40e_read_dword - read HMC context dword into struct
+ * @hmc_bits: pointer to the HMC memory
+ * @ce_info: a description of the struct to be filled
+ * @dest: the struct to be filled
+ **/
+static void i40e_read_dword(u8 *hmc_bits,
+			    struct i40e_context_ele *ce_info,
+			    u8 *dest)
+{
+	u32 dest_dword, mask;
+	u8 *src, *target;
+	u16 shift_width;
+	__le32 src_dword;
+
+	/* prepare the bits and mask */
+	shift_width = ce_info->lsb % 8;
+
+	/* if the field width is exactly 32 on an x86 machine, then the shift
+	 * operation will not work because the SHL instructions count is masked
+	 * to 5 bits so the shift will do nothing
+	 */
+	if (ce_info->width < 32)
+		mask = ((u32)1 << ce_info->width) - 1;
+	else
+		mask = 0xFFFFFFFF;
+
+	/* shift to correct alignment */
+	mask <<= shift_width;
+
+	/* get the current bits from the src bit string */
+	src = hmc_bits + (ce_info->lsb / 8);
+
+	i40e_memcpy(&src_dword, src, sizeof(src_dword), I40E_DMA_TO_NONDMA);
+
+	/* the data in the memory is stored as little endian so mask it
+	 * correctly
+	 */
+	src_dword &= ~(CPU_TO_LE32(mask));
+
+	/* get the data back into host order before shifting */
+	dest_dword = LE32_TO_CPU(src_dword);
+
+	dest_dword >>= shift_width;
+
+	/* get the address from the struct field */
+	target = dest + ce_info->offset;
+
+	/* put it back in the struct */
+	i40e_memcpy(target, &dest_dword, sizeof(dest_dword),
+		    I40E_NONDMA_TO_DMA);
+}
+
+/**
+ * i40e_read_qword - read HMC context qword into struct
+ * @hmc_bits: pointer to the HMC memory
+ * @ce_info: a description of the struct to be filled
+ * @dest: the struct to be filled
+ **/
+static void i40e_read_qword(u8 *hmc_bits,
+			    struct i40e_context_ele *ce_info,
+			    u8 *dest)
+{
+	u64 dest_qword, mask;
+	u8 *src, *target;
+	u16 shift_width;
+	__le64 src_qword;
+
+	/* prepare the bits and mask */
+	shift_width = ce_info->lsb % 8;
+
+	/* if the field width is exactly 64 on an x86 machine, then the shift
+	 * operation will not work because the SHL instructions count is masked
+	 * to 6 bits so the shift will do nothing
+	 */
+	if (ce_info->width < 64)
+		mask = ((u64)1 << ce_info->width) - 1;
+	else
+		mask = 0xFFFFFFFFFFFFFFFFUL;
+
+	/* shift to correct alignment */
+	mask <<= shift_width;
+
+	/* get the current bits from the src bit string */
+	src = hmc_bits + (ce_info->lsb / 8);
+
+	i40e_memcpy(&src_qword, src, sizeof(src_qword), I40E_DMA_TO_NONDMA);
+
+	/* the data in the memory is stored as little endian so mask it
+	 * correctly
+	 */
+	src_qword &= ~(CPU_TO_LE64(mask));
+
+	/* get the data back into host order before shifting */
+	dest_qword = LE64_TO_CPU(src_qword);
+
+	dest_qword >>= shift_width;
+
+	/* get the address from the struct field */
+	target = dest + ce_info->offset;
+
+	/* put it back in the struct */
+	i40e_memcpy(target, &dest_qword, sizeof(dest_qword),
+		    I40E_NONDMA_TO_DMA);
+}
+
+/**
  * i40e_get_hmc_context - extract HMC context bits
  * @context_bytes: pointer to the context bit array
  * @ce_info: a description of the struct to be filled
@@ -764,55 +1137,21 @@ static enum i40e_status_code i40e_get_hmc_context(u8 *context_bytes,
 					struct i40e_context_ele *ce_info,
 					u8 *dest)
 {
-	u16 shift_width;
-	u8 bitfield[8];
-	int i, f;
-	u64 mask;
-	u8 *p;
+	int f;
 
 	for (f = 0; ce_info[f].width != 0; f++) {
-		*(u64 *)bitfield = 0;
-
-		/* copy the bytes that contain the desired bits */
-		p = context_bytes + (ce_info[f].lsb / 8);
-		for (i = 0; i < ce_info[f].size_of; i++)
-			bitfield[i] = p[i];
-
-		/* shift the bits to the right */
-		shift_width = ce_info[f].lsb % 8;
-		*(u64 *)bitfield >>= shift_width;
-
-		/* some fields might overlap into one more byte, so grab
-		 * the one more byte if needed and stick the extra bits
-		 * onto the top of the value
-		 * example: 62 bit field that starts in bit 5 of first byte
-		 *          will overlap 3 bits into byte 9
-		 */
-		if ((shift_width + ce_info[f].width) >
-		    (ce_info[f].size_of * 8)) {
-			u8 byte = p[ce_info[f].size_of];
-			byte <<= (8 - shift_width);
-			bitfield[ce_info[f].size_of - 1] |= byte;
-		}
-
-		/* mask for the target bits */
-		mask = ((u64)1 << ce_info[f].width) - 1;
-		*(u64 *)bitfield &= mask;
-
-		/* copy into the appropriate struct field */
-		p = dest + ce_info[f].offset;
 		switch (ce_info[f].size_of) {
 		case 1:
-			*p  = *(u8 *)&bitfield;
+			i40e_read_byte(context_bytes, &ce_info[f], dest);
 			break;
 		case 2:
-			*(u16 *)p = LE16_TO_CPU(*(u16 *)&bitfield);
+			i40e_read_word(context_bytes, &ce_info[f], dest);
 			break;
 		case 4:
-			*(u32 *)p = LE32_TO_CPU(*(u32 *)&bitfield);
+			i40e_read_dword(context_bytes, &ce_info[f], dest);
 			break;
 		case 8:
-			*(u64 *)p = LE64_TO_CPU(*(u64 *)&bitfield);
+			i40e_read_qword(context_bytes, &ce_info[f], dest);
 			break;
 		default:
 			/* nothing to do, just keep going */
@@ -850,71 +1189,28 @@ static enum i40e_status_code i40e_set_hmc_context(u8 *context_bytes,
 					struct i40e_context_ele *ce_info,
 					u8 *dest)
 {
-	u16 shift_width;
-	u64 bitfield;
-	u8 hi_byte;
-	u8 hi_mask;
-	u64 t_bits;
-	u64 mask;
-	u8 *p;
 	int f;
 
 	for (f = 0; ce_info[f].width != 0; f++) {
-		/* clear out the field */
-		bitfield = 0;
 
-		/* copy from the next struct field */
-		p = dest + ce_info[f].offset;
+		/* we have to deal with each element of the HMC using the
+		 * correct size so that we are correct regardless of the
+		 * endianness of the machine
+		 */
 		switch (ce_info[f].size_of) {
 		case 1:
-			bitfield = *p;
+			i40e_write_byte(context_bytes, &ce_info[f], dest);
 			break;
 		case 2:
-			bitfield = CPU_TO_LE16(*(u16 *)p);
+			i40e_write_word(context_bytes, &ce_info[f], dest);
 			break;
 		case 4:
-			bitfield = CPU_TO_LE32(*(u32 *)p);
+			i40e_write_dword(context_bytes, &ce_info[f], dest);
 			break;
 		case 8:
-			bitfield = CPU_TO_LE64(*(u64 *)p);
+			i40e_write_qword(context_bytes, &ce_info[f], dest);
 			break;
 		}
-
-		/* prepare the bits and mask */
-		shift_width = ce_info[f].lsb % 8;
-		mask = ((u64)1 << ce_info[f].width) - 1;
-
-		/* save upper bytes for special case */
-		hi_mask = (u8)((mask >> 56) & 0xff);
-		hi_byte = (u8)((bitfield >> 56) & 0xff);
-
-		/* shift to correct alignment */
-		mask <<= shift_width;
-		bitfield <<= shift_width;
-
-		/* get the current bits from the target bit string */
-		p = context_bytes + (ce_info[f].lsb / 8);
-		i40e_memcpy(&t_bits, p, sizeof(u64), I40E_DMA_TO_NONDMA);
-
-		t_bits &= ~mask;          /* get the bits not changing */
-		t_bits |= bitfield;       /* add in the new bits */
-
-		/* put it all back */
-		i40e_memcpy(p, &t_bits, sizeof(u64), I40E_NONDMA_TO_DMA);
-
-		/* deal with the special case if needed
-		 * example: 62 bit field that starts in bit 5 of first byte
-		 *          will overlap 3 bits into byte 9
-		 */
-		if ((shift_width + ce_info[f].width) > 64) {
-			u8 byte;
-
-			hi_mask >>= (8 - shift_width);
-			hi_byte >>= (8 - shift_width);
-			byte = p[8] & ~hi_mask;  /* get the bits not changing */
-			byte |= hi_byte;         /* add in the new bits */
-			p[8] = byte;             /* put it back */
-		}
 	}
 
 	return I40E_SUCCESS;
diff --git a/sys/dev/i40e/i40e_lan_hmc.h b/sys/dev/i40e/i40e_lan_hmc.h
index 686572f..8b73570 100755
--- a/sys/dev/i40e/i40e_lan_hmc.h
+++ b/sys/dev/i40e/i40e_lan_hmc.h
@@ -37,20 +37,25 @@
 
 /* forward-declare the HW struct for the compiler */
 struct i40e_hw;
-enum i40e_status_code;
 
 /* HMC element context information */
 
-/* Rx queue context data */
+/* Rx queue context data
+ *
+ * The sizes of the variables may be larger than needed due to crossing byte
+ * boundaries. If we do not have the width of the variable set to the correct
+ * size then we could end up shifting bits off the top of the variable when the
+ * variable is at the top of a byte and crosses over into the next byte.
+ */
 struct i40e_hmc_obj_rxq {
 	u16 head;
-	u8  cpuid;
+	u16 cpuid; /* bigger than needed, see above for reason */
 	u64 base;
 	u16 qlen;
 #define I40E_RXQ_CTX_DBUFF_SHIFT 7
-	u8  dbuff;
+	u16 dbuff; /* bigger than needed, see above for reason */
 #define I40E_RXQ_CTX_HBUFF_SHIFT 6
-	u8  hbuff;
+	u16 hbuff; /* bigger than needed, see above for reason */
 	u8  dtype;
 	u8  dsize;
 	u8  crcstrip;
@@ -59,16 +64,22 @@ struct i40e_hmc_obj_rxq {
 	u8  hsplit_0;
 	u8  hsplit_1;
 	u8  showiv;
-	u16 rxmax;
+	u32 rxmax; /* bigger than needed, see above for reason */
 	u8  tphrdesc_ena;
 	u8  tphwdesc_ena;
 	u8  tphdata_ena;
 	u8  tphhead_ena;
-	u8  lrxqthresh;
+	u16 lrxqthresh; /* bigger than needed, see above for reason */
 	u8  prefena;	/* NOTE: normally must be set to 1 at init */
 };
 
-/* Tx queue context data */
+/* Tx queue context data
+*
+* The sizes of the variables may be larger than needed due to crossing byte
+* boundaries. If we do not have the width of the variable set to the correct
+* size then we could end up shifting bits off the top of the variable when the
+* variable is at the top of a byte and crosses over into the next byte.
+*/
 struct i40e_hmc_obj_txq {
 	u16 head;
 	u8  new_context;
@@ -78,7 +89,7 @@ struct i40e_hmc_obj_txq {
 	u8  fd_ena;
 	u8  alt_vlan_ena;
 	u16 thead_wb;
-	u16 cpuid;
+	u8  cpuid;
 	u8  head_wb_ena;
 	u16 qlen;
 	u8  tphrdesc_ena;
@@ -122,11 +133,7 @@ enum i40e_hmc_lan_object_size {
 #define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
 #define I40E_HMC_OBJ_SIZE_TXQ         128
 #define I40E_HMC_OBJ_SIZE_RXQ         32
-#ifdef FORTVILLE_A0_SUPPORT
-#define I40E_HMC_OBJ_SIZE_FCOE_CNTX   128
-#else
 #define I40E_HMC_OBJ_SIZE_FCOE_CNTX   64
-#endif
 #define I40E_HMC_OBJ_SIZE_FCOE_FILT   64
 
 enum i40e_hmc_lan_rsrc_type {
diff --git a/sys/dev/i40e/i40e_nvm.c b/sys/dev/i40e/i40e_nvm.c
index f6ab50f..52d8602 100755
--- a/sys/dev/i40e/i40e_nvm.c
+++ b/sys/dev/i40e/i40e_nvm.c
@@ -457,13 +457,9 @@ enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
 
 	DEBUGFUNC("i40e_validate_nvm_checksum");
 
-	ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
-	if (ret_code != I40E_SUCCESS)
-		goto i40e_validate_nvm_checksum_exit;
-
 	ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
 	if (ret_code != I40E_SUCCESS)
-		goto i40e_validate_nvm_checksum_free;
+		goto i40e_validate_nvm_checksum_exit;
 
 	/* Do not use i40e_read_nvm_word() because we do not want to take
 	 * the synchronization semaphores twice here.
@@ -480,9 +476,6 @@ enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
 	if (checksum)
 		*checksum = checksum_local;
 
-i40e_validate_nvm_checksum_free:
-	i40e_release_nvm(hw);
-
 i40e_validate_nvm_checksum_exit:
 	return ret_code;
 }
diff --git a/sys/dev/i40e/i40e_osdep.c b/sys/dev/i40e/i40e_osdep.c
index 715131a..cea801c 100755
--- a/sys/dev/i40e/i40e_osdep.c
+++ b/sys/dev/i40e/i40e_osdep.c
@@ -89,7 +89,7 @@ i40e_allocate_dma(struct i40e_hw *hw, struct i40e_dma_mem *dma,
 		goto fail_0;
 	}
 	err = bus_dmamem_alloc(dma->tag, (void **)&dma->va,
-			     BUS_DMA_NOWAIT | M_ZERO, &dma->map);
+			     BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->map);
 	if (err != 0) {
 		device_printf(dev,
 		    "i40e_allocate_dma: bus_dmamem_alloc failed, "
@@ -116,6 +116,7 @@ fail_2:
 fail_1:
 	bus_dma_tag_destroy(dma->tag);
 fail_0:
+	dma->map = NULL;
 	dma->tag = NULL;
 	return (err);
 }
diff --git a/sys/dev/i40e/i40e_prototype.h b/sys/dev/i40e/i40e_prototype.h
index 3dc2f5a..9b2d7fc 100755
--- a/sys/dev/i40e/i40e_prototype.h
+++ b/sys/dev/i40e/i40e_prototype.h
@@ -70,10 +70,8 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
 bool i40e_asq_done(struct i40e_hw *hw);
 
 /* debug function for adminq */
-void i40e_debug_aq(struct i40e_hw *hw,
-		   enum i40e_debug_mask mask,
-		   void *desc,
-		   void *buffer);
+void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
+		   void *desc, void *buffer, u16 buf_len);
 
 void i40e_idle_aq(struct i40e_hw *hw);
 void i40e_resume_aq(struct i40e_hw *hw);
@@ -90,6 +88,9 @@ enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
 				u16 *fw_major_version, u16 *fw_minor_version,
 				u16 *api_major_version, u16 *api_minor_version,
 				struct i40e_asq_cmd_details *cmd_details);
+enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
+				u32 reg_addr, u64 reg_val,
+				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
@@ -116,12 +117,10 @@ enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, u16 lb_modes,
 				struct i40e_asq_cmd_details *cmd_details);
-#ifndef FORTVILLE_A0_SUPPORT
 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
 			struct i40e_asq_cmd_details *cmd_details);
-#endif
 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
-				struct i40e_asq_cmd_details *cmd_details);
+		bool enable_link, struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
 				bool enable_lse, struct i40e_link_status *link,
 				struct i40e_asq_cmd_details *cmd_details);
@@ -226,17 +225,10 @@ enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
 				struct i40e_asq_cmd_details *cmd_details);
-#ifdef FORTVILLE_A0_SUPPORT
-enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
-				u16 udp_port, u8 header_len,
-				u8 protocol_index, u8 *filter_index,
-				struct i40e_asq_cmd_details *cmd_details);
-#else
 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
 				u16 udp_port, u8 protocol_index,
 				u8 *filter_index,
 				struct i40e_asq_cmd_details *cmd_details);
-#endif
 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
@@ -361,6 +353,7 @@ enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
 /* i40e_common */
 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw);
 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw);
+void i40e_clear_hw(struct i40e_hw *hw);
 void i40e_clear_pxe_mode(struct i40e_hw *hw);
 bool i40e_get_link_status(struct i40e_hw *hw);
 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
@@ -371,9 +364,6 @@ enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable);
-#ifdef FORTVILLE_A0_SUPPORT
-void i40e_set_tag_alloc_method(struct i40e_hw *hw, bool debug);
-#endif
 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr);
 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw);
 /* prototype for functions used for NVM access */
diff --git a/sys/dev/i40e/i40e_register.h b/sys/dev/i40e/i40e_register.h
index 39d86e3..b6364a0 100755
--- a/sys/dev/i40e/i40e_register.h
+++ b/sys/dev/i40e/i40e_register.h
@@ -35,32 +35,29 @@
 #ifndef _I40E_REGISTER_H_
 #define _I40E_REGISTER_H_
 
-#if !defined(EXTERNAL_RELEASE) || defined(SV_SUPPORT) || defined(FORTVILLE_A0_SUPPORT)
-#include "i40e_register_x710_int.h"
-#endif
 
-#define I40E_GL_ARQBAH              0x000801C0
+#define I40E_GL_ARQBAH              0x000801C0 /* Reset: EMPR */
 #define I40E_GL_ARQBAH_ARQBAH_SHIFT 0
 #define I40E_GL_ARQBAH_ARQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)
-#define I40E_GL_ARQBAL              0x000800C0
+#define I40E_GL_ARQBAL              0x000800C0 /* Reset: EMPR */
 #define I40E_GL_ARQBAL_ARQBAL_SHIFT 0
 #define I40E_GL_ARQBAL_ARQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT)
-#define I40E_GL_ARQH            0x000803C0
+#define I40E_GL_ARQH            0x000803C0 /* Reset: EMPR */
 #define I40E_GL_ARQH_ARQH_SHIFT 0
 #define I40E_GL_ARQH_ARQH_MASK  I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT)
-#define I40E_GL_ARQT            0x000804C0
+#define I40E_GL_ARQT            0x000804C0 /* Reset: EMPR */
 #define I40E_GL_ARQT_ARQT_SHIFT 0
 #define I40E_GL_ARQT_ARQT_MASK  I40E_MASK(0x3FF, I40E_GL_ARQT_ARQT_SHIFT)
-#define I40E_GL_ATQBAH              0x00080140
+#define I40E_GL_ATQBAH              0x00080140 /* Reset: EMPR */
 #define I40E_GL_ATQBAH_ATQBAH_SHIFT 0
 #define I40E_GL_ATQBAH_ATQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAH_ATQBAH_SHIFT)
-#define I40E_GL_ATQBAL              0x00080040
+#define I40E_GL_ATQBAL              0x00080040 /* Reset: EMPR */
 #define I40E_GL_ATQBAL_ATQBAL_SHIFT 0
 #define I40E_GL_ATQBAL_ATQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAL_ATQBAL_SHIFT)
-#define I40E_GL_ATQH            0x00080340
+#define I40E_GL_ATQH            0x00080340 /* Reset: EMPR */
 #define I40E_GL_ATQH_ATQH_SHIFT 0
 #define I40E_GL_ATQH_ATQH_MASK  I40E_MASK(0x3FF, I40E_GL_ATQH_ATQH_SHIFT)
-#define I40E_GL_ATQLEN                 0x00080240
+#define I40E_GL_ATQLEN                 0x00080240 /* Reset: EMPR */
 #define I40E_GL_ATQLEN_ATQLEN_SHIFT    0
 #define I40E_GL_ATQLEN_ATQLEN_MASK     I40E_MASK(0x3FF, I40E_GL_ATQLEN_ATQLEN_SHIFT)
 #define I40E_GL_ATQLEN_ATQVFE_SHIFT    28
@@ -71,19 +68,19 @@
 #define I40E_GL_ATQLEN_ATQCRIT_MASK    I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
 #define I40E_GL_ATQLEN_ATQENABLE_SHIFT 31
 #define I40E_GL_ATQLEN_ATQENABLE_MASK  I40E_MASK(0x1, I40E_GL_ATQLEN_ATQENABLE_SHIFT)
-#define I40E_GL_ATQT            0x00080440
+#define I40E_GL_ATQT            0x00080440 /* Reset: EMPR */
 #define I40E_GL_ATQT_ATQT_SHIFT 0
 #define I40E_GL_ATQT_ATQT_MASK  I40E_MASK(0x3FF, I40E_GL_ATQT_ATQT_SHIFT)
-#define I40E_PF_ARQBAH              0x00080180
+#define I40E_PF_ARQBAH              0x00080180 /* Reset: EMPR */
 #define I40E_PF_ARQBAH_ARQBAH_SHIFT 0
 #define I40E_PF_ARQBAH_ARQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAH_ARQBAH_SHIFT)
-#define I40E_PF_ARQBAL              0x00080080
+#define I40E_PF_ARQBAL              0x00080080 /* Reset: EMPR */
 #define I40E_PF_ARQBAL_ARQBAL_SHIFT 0
 #define I40E_PF_ARQBAL_ARQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAL_ARQBAL_SHIFT)
-#define I40E_PF_ARQH            0x00080380
+#define I40E_PF_ARQH            0x00080380 /* Reset: EMPR */
 #define I40E_PF_ARQH_ARQH_SHIFT 0
 #define I40E_PF_ARQH_ARQH_MASK  I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)
-#define I40E_PF_ARQLEN                 0x00080280
+#define I40E_PF_ARQLEN                 0x00080280 /* Reset: EMPR */
 #define I40E_PF_ARQLEN_ARQLEN_SHIFT    0
 #define I40E_PF_ARQLEN_ARQLEN_MASK     I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT)
 #define I40E_PF_ARQLEN_ARQVFE_SHIFT    28
@@ -94,19 +91,19 @@
 #define I40E_PF_ARQLEN_ARQCRIT_MASK    I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
 #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
 #define I40E_PF_ARQLEN_ARQENABLE_MASK  I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
-#define I40E_PF_ARQT            0x00080480
+#define I40E_PF_ARQT            0x00080480 /* Reset: EMPR */
 #define I40E_PF_ARQT_ARQT_SHIFT 0
 #define I40E_PF_ARQT_ARQT_MASK  I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)
-#define I40E_PF_ATQBAH              0x00080100
+#define I40E_PF_ATQBAH              0x00080100 /* Reset: EMPR */
 #define I40E_PF_ATQBAH_ATQBAH_SHIFT 0
 #define I40E_PF_ATQBAH_ATQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT)
-#define I40E_PF_ATQBAL              0x00080000
+#define I40E_PF_ATQBAL              0x00080000 /* Reset: EMPR */
 #define I40E_PF_ATQBAL_ATQBAL_SHIFT 0
 #define I40E_PF_ATQBAL_ATQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT)
-#define I40E_PF_ATQH            0x00080300
+#define I40E_PF_ATQH            0x00080300 /* Reset: EMPR */
 #define I40E_PF_ATQH_ATQH_SHIFT 0
 #define I40E_PF_ATQH_ATQH_MASK  I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT)
-#define I40E_PF_ATQLEN                 0x00080200
+#define I40E_PF_ATQLEN                 0x00080200 /* Reset: EMPR */
 #define I40E_PF_ATQLEN_ATQLEN_SHIFT    0
 #define I40E_PF_ATQLEN_ATQLEN_MASK     I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT)
 #define I40E_PF_ATQLEN_ATQVFE_SHIFT    28
@@ -117,22 +114,22 @@
 #define I40E_PF_ATQLEN_ATQCRIT_MASK    I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
 #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
 #define I40E_PF_ATQLEN_ATQENABLE_MASK  I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
-#define I40E_PF_ATQT            0x00080400
+#define I40E_PF_ATQT            0x00080400 /* Reset: EMPR */
 #define I40E_PF_ATQT_ATQT_SHIFT 0
 #define I40E_PF_ATQT_ATQT_MASK  I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)
-#define I40E_VF_ARQBAH(_VF)         (0x00081400 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ARQBAH(_VF)         (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ARQBAH_MAX_INDEX    127
 #define I40E_VF_ARQBAH_ARQBAH_SHIFT 0
 #define I40E_VF_ARQBAH_ARQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT)
-#define I40E_VF_ARQBAL(_VF)         (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ARQBAL(_VF)         (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ARQBAL_MAX_INDEX    127
 #define I40E_VF_ARQBAL_ARQBAL_SHIFT 0
 #define I40E_VF_ARQBAL_ARQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL_ARQBAL_SHIFT)
-#define I40E_VF_ARQH(_VF)       (0x00082400 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ARQH(_VF)       (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ARQH_MAX_INDEX  127
 #define I40E_VF_ARQH_ARQH_SHIFT 0
 #define I40E_VF_ARQH_ARQH_MASK  I40E_MASK(0x3FF, I40E_VF_ARQH_ARQH_SHIFT)
-#define I40E_VF_ARQLEN(_VF)            (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ARQLEN(_VF)            (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ARQLEN_MAX_INDEX       127
 #define I40E_VF_ARQLEN_ARQLEN_SHIFT    0
 #define I40E_VF_ARQLEN_ARQLEN_MASK     I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT)
@@ -144,23 +141,23 @@
 #define I40E_VF_ARQLEN_ARQCRIT_MASK    I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)
 #define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31
 #define I40E_VF_ARQLEN_ARQENABLE_MASK  I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
-#define I40E_VF_ARQT(_VF)       (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ARQT(_VF)       (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ARQT_MAX_INDEX  127
 #define I40E_VF_ARQT_ARQT_SHIFT 0
 #define I40E_VF_ARQT_ARQT_MASK  I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT)
-#define I40E_VF_ATQBAH(_VF)         (0x00081000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ATQBAH(_VF)         (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ATQBAH_MAX_INDEX    127
 #define I40E_VF_ATQBAH_ATQBAH_SHIFT 0
 #define I40E_VF_ATQBAH_ATQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT)
-#define I40E_VF_ATQBAL(_VF)         (0x00080800 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ATQBAL(_VF)         (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ATQBAL_MAX_INDEX    127
 #define I40E_VF_ATQBAL_ATQBAL_SHIFT 0
 #define I40E_VF_ATQBAL_ATQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL_ATQBAL_SHIFT)
-#define I40E_VF_ATQH(_VF)       (0x00082000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ATQH(_VF)       (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ATQH_MAX_INDEX  127
 #define I40E_VF_ATQH_ATQH_SHIFT 0
 #define I40E_VF_ATQH_ATQH_MASK  I40E_MASK(0x3FF, I40E_VF_ATQH_ATQH_SHIFT)
-#define I40E_VF_ATQLEN(_VF)            (0x00081800 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ATQLEN(_VF)            (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ATQLEN_MAX_INDEX       127
 #define I40E_VF_ATQLEN_ATQLEN_SHIFT    0
 #define I40E_VF_ATQLEN_ATQLEN_MASK     I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT)
@@ -172,21 +169,21 @@
 #define I40E_VF_ATQLEN_ATQCRIT_MASK    I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)
 #define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31
 #define I40E_VF_ATQLEN_ATQENABLE_MASK  I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
-#define I40E_VF_ATQT(_VF)       (0x00082800 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VF_ATQT(_VF)       (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
 #define I40E_VF_ATQT_MAX_INDEX  127
 #define I40E_VF_ATQT_ATQT_SHIFT 0
 #define I40E_VF_ATQT_ATQT_MASK  I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT)
-#define I40E_PRT_L2TAGSEN              0x001C0B20
+#define I40E_PRT_L2TAGSEN              0x001C0B20 /* Reset: CORER */
 #define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0
 #define I40E_PRT_L2TAGSEN_ENABLE_MASK  I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT)
-#define I40E_PFCM_LAN_ERRDATA                  0x0010C080
+#define I40E_PFCM_LAN_ERRDATA                  0x0010C080 /* Reset: PFR */
 #define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0
 #define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK  I40E_MASK(0xF, I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT)
 #define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT     4
 #define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK      I40E_MASK(0x7, I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT)
 #define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT      8
 #define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK       I40E_MASK(0xFFF, I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT)
-#define I40E_PFCM_LAN_ERRINFO                     0x0010C000
+#define I40E_PFCM_LAN_ERRINFO                     0x0010C000 /* Reset: PFR */
 #define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT   0
 #define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK    I40E_MASK(0x1, I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT)
 #define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT    4
@@ -197,7 +194,7 @@
 #define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)
 #define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24
 #define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)
-#define I40E_PFCM_LANCTXCTL                  0x0010C300
+#define I40E_PFCM_LANCTXCTL                  0x0010C300 /* Reset: CORER */
 #define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT  0
 #define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK   I40E_MASK(0xFFF, I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)
 #define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT   12
@@ -206,16 +203,16 @@
 #define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK  I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)
 #define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT    17
 #define I40E_PFCM_LANCTXCTL_OP_CODE_MASK     I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)
-#define I40E_PFCM_LANCTXDATA(_i)        (0x0010C100 + ((_i) * 128)) /* _i=0...3 */
+#define I40E_PFCM_LANCTXDATA(_i)        (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_PFCM_LANCTXDATA_MAX_INDEX  3
 #define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0
 #define I40E_PFCM_LANCTXDATA_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFCM_LANCTXDATA_DATA_SHIFT)
-#define I40E_PFCM_LANCTXSTAT                0x0010C380
+#define I40E_PFCM_LANCTXSTAT                0x0010C380 /* Reset: CORER */
 #define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0
 #define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK  I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)
 #define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1
 #define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK  I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT)
-#define I40E_VFCM_PE_ERRDATA1(_VF)             (0x00138800 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VFCM_PE_ERRDATA1(_VF)             (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VFCM_PE_ERRDATA1_MAX_INDEX        127
 #define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0
 #define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK  I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT)
@@ -223,7 +220,7 @@
 #define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK      I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT)
 #define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT      8
 #define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK       I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT)
-#define I40E_VFCM_PE_ERRINFO1(_VF)                (0x00138400 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VFCM_PE_ERRINFO1(_VF)                (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VFCM_PE_ERRINFO1_MAX_INDEX           127
 #define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT   0
 #define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK    I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT)
@@ -235,25 +232,25 @@
 #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)
 #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24
 #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)
-#define I40E_GLDCB_GENC              0x00083044
+#define I40E_GLDCB_GENC              0x00083044 /* Reset: CORER */
 #define I40E_GLDCB_GENC_PCIRTT_SHIFT 0
 #define I40E_GLDCB_GENC_PCIRTT_MASK  I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT)
-#define I40E_GLDCB_RUPTI                     0x00122618
+#define I40E_GLDCB_RUPTI                     0x00122618 /* Reset: CORER */
 #define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0
 #define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT)
-#define I40E_PRTDCB_FCCFG            0x001E4640
+#define I40E_PRTDCB_FCCFG            0x001E4640 /* Reset: GLOBR */
 #define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3
 #define I40E_PRTDCB_FCCFG_TFCE_MASK  I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT)
-#define I40E_PRTDCB_FCRTV                     0x001E4600
+#define I40E_PRTDCB_FCRTV                     0x001E4600 /* Reset: GLOBR */
 #define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0
 #define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT)
-#define I40E_PRTDCB_FCTTVN(_i)             (0x001E4580 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRTDCB_FCTTVN(_i)             (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */
 #define I40E_PRTDCB_FCTTVN_MAX_INDEX       3
 #define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT    0
 #define I40E_PRTDCB_FCTTVN_TTV_2N_MASK     I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT)
 #define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16
 #define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)
-#define I40E_PRTDCB_GENC                    0x00083000
+#define I40E_PRTDCB_GENC                    0x00083000 /* Reset: CORER */
 #define I40E_PRTDCB_GENC_RESERVED_1_SHIFT   0
 #define I40E_PRTDCB_GENC_RESERVED_1_MASK    I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT)
 #define I40E_PRTDCB_GENC_NUMTC_SHIFT        2
@@ -264,10 +261,10 @@
 #define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK  I40E_MASK(0x1, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT)
 #define I40E_PRTDCB_GENC_PFCLDA_SHIFT       16
 #define I40E_PRTDCB_GENC_PFCLDA_MASK        I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT)
-#define I40E_PRTDCB_GENS                   0x00083020
+#define I40E_PRTDCB_GENS                   0x00083020 /* Reset: CORER */
 #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0
 #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK  I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)
-#define I40E_PRTDCB_MFLCN             0x001E2400
+#define I40E_PRTDCB_MFLCN             0x001E2400 /* Reset: GLOBR */
 #define I40E_PRTDCB_MFLCN_PMCF_SHIFT  0
 #define I40E_PRTDCB_MFLCN_PMCF_MASK   I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT)
 #define I40E_PRTDCB_MFLCN_DPF_SHIFT   1
@@ -278,7 +275,7 @@
 #define I40E_PRTDCB_MFLCN_RFCE_MASK   I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT)
 #define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4
 #define I40E_PRTDCB_MFLCN_RPFCE_MASK  I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT)
-#define I40E_PRTDCB_RETSC                    0x001223E0
+#define I40E_PRTDCB_RETSC                    0x001223E0 /* Reset: CORER */
 #define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT     0
 #define I40E_PRTDCB_RETSC_ETS_MODE_MASK      I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT)
 #define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1
@@ -287,7 +284,7 @@
 #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK   I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT)
 #define I40E_PRTDCB_RETSC_LLTC_SHIFT         8
 #define I40E_PRTDCB_RETSC_LLTC_MASK          I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)
-#define I40E_PRTDCB_RETSTCC(_i)               (0x00122180 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTDCB_RETSTCC(_i)               (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTDCB_RETSTCC_MAX_INDEX         7
 #define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT     0
 #define I40E_PRTDCB_RETSTCC_BWSHARE_MASK      I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)
@@ -295,17 +292,17 @@
 #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK  I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
 #define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT       31
 #define I40E_PRTDCB_RETSTCC_ETSTC_MASK        I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
-#define I40E_PRTDCB_RPPMC                    0x001223A0
+#define I40E_PRTDCB_RPPMC                    0x001223A0 /* Reset: CORER */
 #define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT      0
 #define I40E_PRTDCB_RPPMC_LANRPPM_MASK       I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
 #define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT     8
 #define I40E_PRTDCB_RPPMC_RDMARPPM_MASK      I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)
 #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16
 #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK  I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)
-#define I40E_PRTDCB_RUP                0x001C0B00
+#define I40E_PRTDCB_RUP                0x001C0B00 /* Reset: CORER */
 #define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0
 #define I40E_PRTDCB_RUP_NOVLANUP_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT)
-#define I40E_PRTDCB_RUP2TC             0x001C09A0
+#define I40E_PRTDCB_RUP2TC             0x001C09A0 /* Reset: CORER */
 #define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0
 #define I40E_PRTDCB_RUP2TC_UP0TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT)
 #define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3
@@ -322,36 +319,40 @@
 #define I40E_PRTDCB_RUP2TC_UP6TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
 #define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21
 #define I40E_PRTDCB_RUP2TC_UP7TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
-#define I40E_PRTDCB_TC2PFC              0x001C0980
+#define I40E_PRTDCB_TC2PFC              0x001C0980 /* Reset: CORER */
 #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0
 #define I40E_PRTDCB_TC2PFC_TC2PFC_MASK  I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
-#define I40E_PRTDCB_TCPMC                 0x000A21A0
+#define I40E_PRTDCB_TCMSTC(_i)        (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
+#define I40E_PRTDCB_TCMSTC_MAX_INDEX  7
+#define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0
+#define I40E_PRTDCB_TCMSTC_MSTC_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT)
+#define I40E_PRTDCB_TCPMC                 0x000A21A0 /* Reset: CORER */
 #define I40E_PRTDCB_TCPMC_CPM_SHIFT       0
 #define I40E_PRTDCB_TCPMC_CPM_MASK        I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT)
 #define I40E_PRTDCB_TCPMC_LLTC_SHIFT      13
 #define I40E_PRTDCB_TCPMC_LLTC_MASK       I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT)
 #define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30
 #define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK  I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT)
-#define I40E_PRTDCB_TCWSTC(_i)        (0x000A2040 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTDCB_TCWSTC(_i)        (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTDCB_TCWSTC_MAX_INDEX  7
 #define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0
 #define I40E_PRTDCB_TCWSTC_MSTC_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT)
-#define I40E_PRTDCB_TDPMC                 0x000A0180
+#define I40E_PRTDCB_TDPMC                 0x000A0180 /* Reset: CORER */
 #define I40E_PRTDCB_TDPMC_DPM_SHIFT       0
 #define I40E_PRTDCB_TDPMC_DPM_MASK        I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT)
 #define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30
 #define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK  I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT)
-#define I40E_PRTDCB_TETSC_TCB                             0x000AE060
+#define I40E_PRTDCB_TETSC_TCB                             0x000AE060 /* Reset: CORER */
 #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0
 #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK  I40E_MASK(0x1, I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT)
 #define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT                  8
 #define I40E_PRTDCB_TETSC_TCB_LLTC_MASK                   I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT)
-#define I40E_PRTDCB_TETSC_TPB                             0x00098060
+#define I40E_PRTDCB_TETSC_TPB                             0x00098060 /* Reset: CORER */
 #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0
 #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK  I40E_MASK(0x1, I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT)
 #define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT                  8
 #define I40E_PRTDCB_TETSC_TPB_LLTC_MASK                   I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT)
-#define I40E_PRTDCB_TFCS              0x001E4560
+#define I40E_PRTDCB_TFCS              0x001E4560 /* Reset: GLOBR */
 #define I40E_PRTDCB_TFCS_TXOFF_SHIFT  0
 #define I40E_PRTDCB_TFCS_TXOFF_MASK   I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT)
 #define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8
@@ -370,15 +371,11 @@
 #define I40E_PRTDCB_TFCS_TXOFF6_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT)
 #define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15
 #define I40E_PRTDCB_TFCS_TXOFF7_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT)
-#define I40E_PRTDCB_TFWSTC(_i)        (0x000A0040 + ((_i) * 32)) /* _i=0...7 */
-#define I40E_PRTDCB_TFWSTC_MAX_INDEX  7
-#define I40E_PRTDCB_TFWSTC_MSTC_SHIFT 0
-#define I40E_PRTDCB_TFWSTC_MSTC_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TFWSTC_MSTC_SHIFT)
-#define I40E_PRTDCB_TPFCTS(_i)            (0x001E4660 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTDCB_TPFCTS(_i)            (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */
 #define I40E_PRTDCB_TPFCTS_MAX_INDEX      7
 #define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0
 #define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK  I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT)
-#define I40E_GLFCOE_RCTL                0x00269B94
+#define I40E_GLFCOE_RCTL                0x00269B94 /* Reset: CORER */
 #define I40E_GLFCOE_RCTL_FCOEVER_SHIFT  0
 #define I40E_GLFCOE_RCTL_FCOEVER_MASK   I40E_MASK(0xF, I40E_GLFCOE_RCTL_FCOEVER_SHIFT)
 #define I40E_GLFCOE_RCTL_SAVBAD_SHIFT   4
@@ -387,14 +384,14 @@
 #define I40E_GLFCOE_RCTL_ICRC_MASK      I40E_MASK(0x1, I40E_GLFCOE_RCTL_ICRC_SHIFT)
 #define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16
 #define I40E_GLFCOE_RCTL_MAX_SIZE_MASK  I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)
-#define I40E_GL_FWSTS             0x00083048
+#define I40E_GL_FWSTS             0x00083048 /* Reset: POR */
 #define I40E_GL_FWSTS_FWS0B_SHIFT 0
 #define I40E_GL_FWSTS_FWS0B_MASK  I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT)
 #define I40E_GL_FWSTS_FWRI_SHIFT  9
 #define I40E_GL_FWSTS_FWRI_MASK   I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT)
 #define I40E_GL_FWSTS_FWS1B_SHIFT 16
 #define I40E_GL_FWSTS_FWS1B_MASK  I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)
-#define I40E_GLGEN_CLKSTAT                    0x000B8184
+#define I40E_GLGEN_CLKSTAT                    0x000B8184 /* Reset: POR */
 #define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT      0
 #define I40E_GLGEN_CLKSTAT_CLKMODE_MASK       I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)
 #define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT  4
@@ -407,7 +404,7 @@
 #define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK  I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT)
 #define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20
 #define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK  I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT)
-#define I40E_GLGEN_GPIO_CTL(_i)                (0x00088100 + ((_i) * 4)) /* _i=0...29 */
+#define I40E_GLGEN_GPIO_CTL(_i)                (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */
 #define I40E_GLGEN_GPIO_CTL_MAX_INDEX          29
 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT      0
 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK       I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
@@ -426,27 +423,27 @@
 #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT    11
 #define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK     I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT)
 #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT     12
-#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK      I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
+#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK      I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
 #define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT     17
 #define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK      I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT)
 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT  19
 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK   I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
 #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20
 #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK  I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
-#define I40E_GLGEN_GPIO_SET                 0x00088184
+#define I40E_GLGEN_GPIO_SET                 0x00088184 /* Reset: POR */
 #define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0
 #define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK  I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
 #define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT  5
 #define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK   I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
 #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6
 #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK  I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
-#define I40E_GLGEN_GPIO_STAT                  0x0008817C
+#define I40E_GLGEN_GPIO_STAT                  0x0008817C /* Reset: POR */
 #define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0
 #define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK  I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT)
-#define I40E_GLGEN_GPIO_TRANSIT                       0x00088180
+#define I40E_GLGEN_GPIO_TRANSIT                       0x00088180 /* Reset: POR */
 #define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0
 #define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK  I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT)
-#define I40E_GLGEN_I2CCMD(_i)          (0x000881E0 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLGEN_I2CCMD(_i)          (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_GLGEN_I2CCMD_MAX_INDEX    3
 #define I40E_GLGEN_I2CCMD_DATA_SHIFT   0
 #define I40E_GLGEN_I2CCMD_DATA_MASK    I40E_MASK(0xFFFF, I40E_GLGEN_I2CCMD_DATA_SHIFT)
@@ -462,7 +459,7 @@
 #define I40E_GLGEN_I2CCMD_R_MASK       I40E_MASK(0x1, I40E_GLGEN_I2CCMD_R_SHIFT)
 #define I40E_GLGEN_I2CCMD_E_SHIFT      31
 #define I40E_GLGEN_I2CCMD_E_MASK       I40E_MASK(0x1, I40E_GLGEN_I2CCMD_E_SHIFT)
-#define I40E_GLGEN_I2CPARAMS(_i)                   (0x000881AC + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLGEN_I2CPARAMS(_i)                   (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_GLGEN_I2CPARAMS_MAX_INDEX             3
 #define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT      0
 #define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK       I40E_MASK(0x1F, I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT)
@@ -486,10 +483,10 @@
 #define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK  I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT)
 #define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT  31
 #define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK   I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT)
-#define I40E_GLGEN_LED_CTL                          0x00088178
+#define I40E_GLGEN_LED_CTL                          0x00088178 /* Reset: POR */
 #define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT  0
 #define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK   I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT)
-#define I40E_GLGEN_MDIO_CTRL(_i)                (0x000881D0 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLGEN_MDIO_CTRL(_i)                (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_GLGEN_MDIO_CTRL_MAX_INDEX          3
 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0
 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK  I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT)
@@ -497,7 +494,7 @@
 #define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK       I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18
 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK  I40E_MASK(0x3FFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
-#define I40E_GLGEN_MDIO_I2C_SEL(_i)                (0x000881C0 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLGEN_MDIO_I2C_SEL(_i)                (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX          3
 #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0
 #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK  I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT)
@@ -515,7 +512,7 @@
 #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK  I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT)
 #define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31
 #define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK  I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT)
-#define I40E_GLGEN_MSCA(_i)               (0x0008818C + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLGEN_MSCA(_i)               (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_GLGEN_MSCA_MAX_INDEX         3
 #define I40E_GLGEN_MSCA_MDIADD_SHIFT      0
 #define I40E_GLGEN_MSCA_MDIADD_MASK       I40E_MASK(0xFFFF, I40E_GLGEN_MSCA_MDIADD_SHIFT)
@@ -531,18 +528,18 @@
 #define I40E_GLGEN_MSCA_MDICMD_MASK       I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)
 #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
 #define I40E_GLGEN_MSCA_MDIINPROGEN_MASK  I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
-#define I40E_GLGEN_MSRWD(_i)             (0x0008819C + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLGEN_MSRWD(_i)             (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_GLGEN_MSRWD_MAX_INDEX       3
 #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
 #define I40E_GLGEN_MSRWD_MDIWRDATA_MASK  I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)
 #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
 #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK  I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
-#define I40E_GLGEN_PCIFCNCNT                0x001C0AB4
+#define I40E_GLGEN_PCIFCNCNT                0x001C0AB4 /* Reset: PCIR */
 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK  I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
 #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
 #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK  I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
-#define I40E_GLGEN_RSTAT                   0x000B8188
+#define I40E_GLGEN_RSTAT                   0x000B8188 /* Reset: POR */
 #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT    0
 #define I40E_GLGEN_RSTAT_DEVSTATE_MASK     I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
 #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT  2
@@ -555,22 +552,22 @@
 #define I40E_GLGEN_RSTAT_EMPRCNT_MASK      I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT)
 #define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10
 #define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK  I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT)
-#define I40E_GLGEN_RSTCTL                   0x000B8180
+#define I40E_GLGEN_RSTCTL                   0x000B8180 /* Reset: POR */
 #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT     0
 #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK      I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
 #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8
 #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK  I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
-#define I40E_GLGEN_RSTENA_EMP                   0x000B818C
+#define I40E_GLGEN_RSTENA_EMP                   0x000B818C /* Reset: POR */
 #define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0
 #define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK  I40E_MASK(0x1, I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT)
-#define I40E_GLGEN_RTRIG              0x000B8190
+#define I40E_GLGEN_RTRIG              0x000B8190 /* Reset: CORER */
 #define I40E_GLGEN_RTRIG_CORER_SHIFT  0
 #define I40E_GLGEN_RTRIG_CORER_MASK   I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)
 #define I40E_GLGEN_RTRIG_GLOBR_SHIFT  1
 #define I40E_GLGEN_RTRIG_GLOBR_MASK   I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT)
 #define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2
 #define I40E_GLGEN_RTRIG_EMPFWR_MASK  I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT)
-#define I40E_GLGEN_STAT               0x000B612C
+#define I40E_GLGEN_STAT               0x000B612C /* Reset: POR */
 #define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0
 #define I40E_GLGEN_STAT_HWRSVD0_MASK  I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD0_SHIFT)
 #define I40E_GLGEN_STAT_DCBEN_SHIFT   2
@@ -583,23 +580,23 @@
 #define I40E_GLGEN_STAT_EVBEN_MASK    I40E_MASK(0x1, I40E_GLGEN_STAT_EVBEN_SHIFT)
 #define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6
 #define I40E_GLGEN_STAT_HWRSVD1_MASK  I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD1_SHIFT)
-#define I40E_GLGEN_VFLRSTAT(_i)         (0x00092600 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLGEN_VFLRSTAT(_i)         (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLGEN_VFLRSTAT_MAX_INDEX   3
 #define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0
 #define I40E_GLGEN_VFLRSTAT_VFLRE_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT)
-#define I40E_GLVFGEN_TIMER             0x000881BC
+#define I40E_GLVFGEN_TIMER             0x000881BC /* Reset: CORER */
 #define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0
 #define I40E_GLVFGEN_TIMER_GTIME_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVFGEN_TIMER_GTIME_SHIFT)
-#define I40E_PFGEN_CTRL             0x00092400
+#define I40E_PFGEN_CTRL             0x00092400 /* Reset: PFR */
 #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0
 #define I40E_PFGEN_CTRL_PFSWR_MASK  I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT)
-#define I40E_PFGEN_DRUN               0x00092500
+#define I40E_PFGEN_DRUN               0x00092500 /* Reset: CORER */
 #define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0
 #define I40E_PFGEN_DRUN_DRVUNLD_MASK  I40E_MASK(0x1, I40E_PFGEN_DRUN_DRVUNLD_SHIFT)
-#define I40E_PFGEN_PORTNUM                0x001C0480
+#define I40E_PFGEN_PORTNUM                0x001C0480 /* Reset: CORER */
 #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0
 #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK  I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT)
-#define I40E_PFGEN_STATE                  0x00088000
+#define I40E_PFGEN_STATE                  0x00088000 /* Reset: CORER */
 #define I40E_PFGEN_STATE_RESERVED_0_SHIFT 0
 #define I40E_PFGEN_STATE_RESERVED_0_MASK  I40E_MASK(0x1, I40E_PFGEN_STATE_RESERVED_0_SHIFT)
 #define I40E_PFGEN_STATE_PFFCEN_SHIFT     1
@@ -608,140 +605,140 @@
 #define I40E_PFGEN_STATE_PFLINKEN_MASK    I40E_MASK(0x1, I40E_PFGEN_STATE_PFLINKEN_SHIFT)
 #define I40E_PFGEN_STATE_PFSCEN_SHIFT     3
 #define I40E_PFGEN_STATE_PFSCEN_MASK      I40E_MASK(0x1, I40E_PFGEN_STATE_PFSCEN_SHIFT)
-#define I40E_PRTGEN_CNF                      0x000B8120
+#define I40E_PRTGEN_CNF                      0x000B8120 /* Reset: POR */
 #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT       0
 #define I40E_PRTGEN_CNF_PORT_DIS_MASK        I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT)
 #define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1
 #define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK  I40E_MASK(0x1, I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT)
 #define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT   2
 #define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK    I40E_MASK(0x1, I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT)
-#define I40E_PRTGEN_CNF2                          0x000B8160
+#define I40E_PRTGEN_CNF2                          0x000B8160 /* Reset: POR */
 #define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0
 #define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK  I40E_MASK(0x1, I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT)
-#define I40E_PRTGEN_STATUS                   0x000B8100
+#define I40E_PRTGEN_STATUS                   0x000B8100 /* Reset: POR */
 #define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT  0
 #define I40E_PRTGEN_STATUS_PORT_VALID_MASK   I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_VALID_SHIFT)
 #define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1
 #define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK  I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT)
-#define I40E_VFGEN_RSTAT1(_VF)            (0x00074400 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VFGEN_RSTAT1(_VF)            (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VFGEN_RSTAT1_MAX_INDEX       127
 #define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0
 #define I40E_VFGEN_RSTAT1_VFR_STATE_MASK  I40E_MASK(0x3, I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT)
-#define I40E_VPGEN_VFRSTAT(_VF)       (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPGEN_VFRSTAT(_VF)       (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VPGEN_VFRSTAT_MAX_INDEX  127
 #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0
 #define I40E_VPGEN_VFRSTAT_VFRD_MASK  I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT)
-#define I40E_VPGEN_VFRTRIG(_VF)        (0x00091800 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPGEN_VFRTRIG(_VF)        (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VPGEN_VFRTRIG_MAX_INDEX   127
 #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0
 #define I40E_VPGEN_VFRTRIG_VFSWR_MASK  I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT)
-#define I40E_VSIGEN_RSTAT(_VSI)      (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSIGEN_RSTAT(_VSI)      (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_VSIGEN_RSTAT_MAX_INDEX  383
 #define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0
 #define I40E_VSIGEN_RSTAT_VMRD_MASK  I40E_MASK(0x1, I40E_VSIGEN_RSTAT_VMRD_SHIFT)
-#define I40E_VSIGEN_RTRIG(_VSI)       (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSIGEN_RTRIG(_VSI)       (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_VSIGEN_RTRIG_MAX_INDEX   383
 #define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0
 #define I40E_VSIGEN_RTRIG_VMSWR_MASK  I40E_MASK(0x1, I40E_VSIGEN_RTRIG_VMSWR_SHIFT)
-#define I40E_GLHMC_FCOEDDPBASE(_i)                  (0x000C6600 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_FCOEDDPBASE(_i)                  (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX            15
 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0
 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT)
-#define I40E_GLHMC_FCOEDDPCNT(_i)                 (0x000C6700 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_FCOEDDPCNT(_i)                 (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX           15
 #define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0
 #define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK  I40E_MASK(0xFFFFF, I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT)
-#define I40E_GLHMC_FCOEDDPOBJSZ                      0x000C2010
+#define I40E_GLHMC_FCOEDDPOBJSZ                      0x000C2010 /* Reset: CORER */
 #define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0
 #define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT)
-#define I40E_GLHMC_FCOEFBASE(_i)                (0x000C6800 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_FCOEFBASE(_i)                (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_FCOEFBASE_MAX_INDEX          15
 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0
 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT)
-#define I40E_GLHMC_FCOEFCNT(_i)               (0x000C6900 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_FCOEFCNT(_i)               (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_FCOEFCNT_MAX_INDEX         15
 #define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0
 #define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK  I40E_MASK(0x7FFFFF, I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT)
-#define I40E_GLHMC_FCOEFMAX                  0x000C20D0
+#define I40E_GLHMC_FCOEFMAX                  0x000C20D0 /* Reset: CORER */
 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0
 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK  I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT)
-#define I40E_GLHMC_FCOEFOBJSZ                    0x000C2018
+#define I40E_GLHMC_FCOEFOBJSZ                    0x000C2018 /* Reset: CORER */
 #define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0
 #define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT)
-#define I40E_GLHMC_FCOEMAX                 0x000C2014
+#define I40E_GLHMC_FCOEMAX                 0x000C2014 /* Reset: CORER */
 #define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0
 #define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK  I40E_MASK(0x1FFF, I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT)
-#define I40E_GLHMC_FSIAVBASE(_i)                (0x000C5600 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_FSIAVBASE(_i)                (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_FSIAVBASE_MAX_INDEX          15
 #define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0
 #define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT)
-#define I40E_GLHMC_FSIAVCNT(_i)               (0x000C5700 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_FSIAVCNT(_i)               (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_FSIAVCNT_MAX_INDEX         15
 #define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0
 #define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT)
 #define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT        29
 #define I40E_GLHMC_FSIAVCNT_RSVD_MASK         I40E_MASK(0x7, I40E_GLHMC_FSIAVCNT_RSVD_SHIFT)
-#define I40E_GLHMC_FSIAVMAX                  0x000C2068
+#define I40E_GLHMC_FSIAVMAX                  0x000C2068 /* Reset: CORER */
 #define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0
 #define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK  I40E_MASK(0x1FFFF, I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT)
-#define I40E_GLHMC_FSIAVOBJSZ                    0x000C2064
+#define I40E_GLHMC_FSIAVOBJSZ                    0x000C2064 /* Reset: CORER */
 #define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0
 #define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT)
-#define I40E_GLHMC_FSIMCBASE(_i)                (0x000C6000 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_FSIMCBASE(_i)                (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_FSIMCBASE_MAX_INDEX          15
 #define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0
 #define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT)
-#define I40E_GLHMC_FSIMCCNT(_i)              (0x000C6100 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_FSIMCCNT(_i)              (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_FSIMCCNT_MAX_INDEX        15
 #define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0
 #define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT)
-#define I40E_GLHMC_FSIMCMAX                  0x000C2060
+#define I40E_GLHMC_FSIMCMAX                  0x000C2060 /* Reset: CORER */
 #define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0
 #define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK  I40E_MASK(0x3FFF, I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT)
-#define I40E_GLHMC_FSIMCOBJSZ                    0x000C205c
+#define I40E_GLHMC_FSIMCOBJSZ                    0x000C205c /* Reset: CORER */
 #define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0
 #define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT)
-#define I40E_GLHMC_LANQMAX                 0x000C2008
+#define I40E_GLHMC_LANQMAX                 0x000C2008 /* Reset: CORER */
 #define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0
 #define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK  I40E_MASK(0x7FF, I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT)
-#define I40E_GLHMC_LANRXBASE(_i)                (0x000C6400 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LANRXBASE(_i)                (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LANRXBASE_MAX_INDEX          15
 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0
 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT)
-#define I40E_GLHMC_LANRXCNT(_i)               (0x000C6500 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LANRXCNT(_i)               (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LANRXCNT_MAX_INDEX         15
 #define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0
 #define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK  I40E_MASK(0x7FF, I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT)
-#define I40E_GLHMC_LANRXOBJSZ                    0x000C200c
+#define I40E_GLHMC_LANRXOBJSZ                    0x000C200c /* Reset: CORER */
 #define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0
 #define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT)
-#define I40E_GLHMC_LANTXBASE(_i)                (0x000C6200 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LANTXBASE(_i)                (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LANTXBASE_MAX_INDEX          15
 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0
 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT)
 #define I40E_GLHMC_LANTXBASE_RSVD_SHIFT         24
 #define I40E_GLHMC_LANTXBASE_RSVD_MASK          I40E_MASK(0xFF, I40E_GLHMC_LANTXBASE_RSVD_SHIFT)
-#define I40E_GLHMC_LANTXCNT(_i)               (0x000C6300 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LANTXCNT(_i)               (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LANTXCNT_MAX_INDEX         15
 #define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0
 #define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK  I40E_MASK(0x7FF, I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT)
-#define I40E_GLHMC_LANTXOBJSZ                    0x000C2004
+#define I40E_GLHMC_LANTXOBJSZ                    0x000C2004 /* Reset: CORER */
 #define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0
 #define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT)
-#define I40E_GLHMC_PFASSIGN(_i)                 (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_PFASSIGN(_i)                 (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_PFASSIGN_MAX_INDEX           15
 #define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0
 #define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK  I40E_MASK(0xF, I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT)
-#define I40E_GLHMC_SDPART(_i)            (0x000C0800 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_SDPART(_i)            (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_SDPART_MAX_INDEX      15
 #define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0
 #define I40E_GLHMC_SDPART_PMSDBASE_MASK  I40E_MASK(0xFFF, I40E_GLHMC_SDPART_PMSDBASE_SHIFT)
 #define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16
 #define I40E_GLHMC_SDPART_PMSDSIZE_MASK  I40E_MASK(0x1FFF, I40E_GLHMC_SDPART_PMSDSIZE_SHIFT)
-#define I40E_PFHMC_ERRORDATA                      0x000C0500
+#define I40E_PFHMC_ERRORDATA                      0x000C0500 /* Reset: PFR */
 #define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0
 #define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK  I40E_MASK(0x3FFFFFFF, I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT)
-#define I40E_PFHMC_ERRORINFO                       0x000C0400
+#define I40E_PFHMC_ERRORINFO                       0x000C0400 /* Reset: PFR */
 #define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT       0
 #define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK        I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT)
 #define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT        7
@@ -752,20 +749,20 @@
 #define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK  I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT)
 #define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT  31
 #define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK   I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT)
-#define I40E_PFHMC_PDINV               0x000C0300
+#define I40E_PFHMC_PDINV               0x000C0300 /* Reset: PFR */
 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
 #define I40E_PFHMC_PDINV_PMSDIDX_MASK  I40E_MASK(0xFFF, I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
 #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16
 #define I40E_PFHMC_PDINV_PMPDIDX_MASK  I40E_MASK(0x1FF, I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
-#define I40E_PFHMC_SDCMD               0x000C0000
+#define I40E_PFHMC_SDCMD               0x000C0000 /* Reset: PFR */
 #define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0
 #define I40E_PFHMC_SDCMD_PMSDIDX_MASK  I40E_MASK(0xFFF, I40E_PFHMC_SDCMD_PMSDIDX_SHIFT)
 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT  31
 #define I40E_PFHMC_SDCMD_PMSDWR_MASK   I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
-#define I40E_PFHMC_SDDATAHIGH                    0x000C0200
+#define I40E_PFHMC_SDDATAHIGH                    0x000C0200 /* Reset: PFR */
 #define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0
 #define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT)
-#define I40E_PFHMC_SDDATALOW                   0x000C0100
+#define I40E_PFHMC_SDDATALOW                   0x000C0100 /* Reset: PFR */
 #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT   0
 #define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK    I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)
 #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT    1
@@ -774,220 +771,11 @@
 #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK  I40E_MASK(0x3FF, I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT)
 #define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12
 #define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK  I40E_MASK(0xFFFFF, I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT)
-#define I40E_GL_DBG_DATA                   0x0026998C
-#define I40E_GL_DBG_DATA_GL_DBG_DATA_SHIFT 0
-#define I40E_GL_DBG_DATA_GL_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_DBG_DATA_GL_DBG_DATA_SHIFT)
-#define I40E_GLQF_ABORT_MASK(_i)                   (0x0026CCC8 + ((_i) * 4)) /* _i=0...1 */
-#define I40E_GLQF_ABORT_MASK_MAX_INDEX             1
-#define I40E_GLQF_ABORT_MASK_GLQF_ABORT_MASK_SHIFT 0
-#define I40E_GLQF_ABORT_MASK_GLQF_ABORT_MASK_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_ABORT_MASK_GLQF_ABORT_MASK_SHIFT)
-#define I40E_GLQF_L2_MAP(_i)               (0x0026CBF8 + ((_i) * 4)) /* _i=0...1 */
-#define I40E_GLQF_L2_MAP_MAX_INDEX         1
-#define I40E_GLQF_L2_MAP_GLQF_L2_MAP_SHIFT 0
-#define I40E_GLQF_L2_MAP_GLQF_L2_MAP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_L2_MAP_GLQF_L2_MAP_SHIFT)
-#define I40E_GLQF_OPT_MAP                   0x0026CBDC
-#define I40E_GLQF_OPT_MAP_FRAG_IDX_SHIFT    0
-#define I40E_GLQF_OPT_MAP_FRAG_IDX_MASK     I40E_MASK(0x3F, I40E_GLQF_OPT_MAP_FRAG_IDX_SHIFT)
-#define I40E_GLQF_OPT_MAP_IP_OPT_IDX_SHIFT  12
-#define I40E_GLQF_OPT_MAP_IP_OPT_IDX_MASK   I40E_MASK(0x3F, I40E_GLQF_OPT_MAP_IP_OPT_IDX_SHIFT)
-#define I40E_GLQF_OPT_MAP_TCP_OPT_IDX_SHIFT 18
-#define I40E_GLQF_OPT_MAP_TCP_OPT_IDX_MASK  I40E_MASK(0x3F, I40E_GLQF_OPT_MAP_TCP_OPT_IDX_SHIFT)
-#define I40E_GLRCB_DBG_DATA0                0x00122628
-#define I40E_GLRCB_DBG_DATA0_DBG_DATA_SHIFT 0
-#define I40E_GLRCB_DBG_DATA0_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA0_DBG_DATA_SHIFT)
-#define I40E_GLRCB_DBG_DATA1                0x0012262C
-#define I40E_GLRCB_DBG_DATA1_DBG_DATA_SHIFT 0
-#define I40E_GLRCB_DBG_DATA1_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA1_DBG_DATA_SHIFT)
-#define I40E_GLRCB_DBG_DATA2                0x00122630
-#define I40E_GLRCB_DBG_DATA2_DBG_DATA_SHIFT 0
-#define I40E_GLRCB_DBG_DATA2_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA2_DBG_DATA_SHIFT)
-#define I40E_GLRCB_DBG_DATA3                0x00122634
-#define I40E_GLRCB_DBG_DATA3_DBG_DATA_SHIFT 0
-#define I40E_GLRCB_DBG_DATA3_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA3_DBG_DATA_SHIFT)
-#define I40E_GLRCB_DBG_DATA4                0x00122638
-#define I40E_GLRCB_DBG_DATA4_DBG_DATA_SHIFT 0
-#define I40E_GLRCB_DBG_DATA4_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA4_DBG_DATA_SHIFT)
-#define I40E_GLRCB_DBG_DATA5                0x0012263C
-#define I40E_GLRCB_DBG_DATA5_DBG_DATA_SHIFT 0
-#define I40E_GLRCB_DBG_DATA5_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA5_DBG_DATA_SHIFT)
-#define I40E_GLRLAN_DBG_DATA0                0x0012A598
-#define I40E_GLRLAN_DBG_DATA0_DBG_DATA_SHIFT 0
-#define I40E_GLRLAN_DBG_DATA0_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA0_DBG_DATA_SHIFT)
-#define I40E_GLRLAN_DBG_DATA1                0x0012A59C
-#define I40E_GLRLAN_DBG_DATA1_DBG_DATA_SHIFT 0
-#define I40E_GLRLAN_DBG_DATA1_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA1_DBG_DATA_SHIFT)
-#define I40E_GLRLAN_DBG_DATA2                0x0012A5A0
-#define I40E_GLRLAN_DBG_DATA2_DBG_DATA_SHIFT 0
-#define I40E_GLRLAN_DBG_DATA2_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA2_DBG_DATA_SHIFT)
-#define I40E_GLRLAN_DBG_DATA3                0x0012A5A4
-#define I40E_GLRLAN_DBG_DATA3_DBG_DATA_SHIFT 0
-#define I40E_GLRLAN_DBG_DATA3_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA3_DBG_DATA_SHIFT)
-#define I40E_GLRLAN_DBG_DATA4                0x0012A5A8
-#define I40E_GLRLAN_DBG_DATA4_DBG_DATA_SHIFT 0
-#define I40E_GLRLAN_DBG_DATA4_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA4_DBG_DATA_SHIFT)
-#define I40E_GLRLAN_DBG_DATA5                0x0012A5AC
-#define I40E_GLRLAN_DBG_DATA5_DBG_DATA_SHIFT 0
-#define I40E_GLRLAN_DBG_DATA5_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA5_DBG_DATA_SHIFT)
-#define I40E_GLRLAN_DBG_DATA6                0x0012A5B0
-#define I40E_GLRLAN_DBG_DATA6_DBG_DATA_SHIFT 0
-#define I40E_GLRLAN_DBG_DATA6_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA6_DBG_DATA_SHIFT)
-#define I40E_GLRLAN_DBG_DATA7                0x0012A5B4
-#define I40E_GLRLAN_DBG_DATA7_DBG_DATA_SHIFT 0
-#define I40E_GLRLAN_DBG_DATA7_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA7_DBG_DATA_SHIFT)
-#define I40E_GLRLAN_SPARE                  0x0012A5B8
-#define I40E_GLRLAN_SPARE_SPARE_BITS_SHIFT 0
-#define I40E_GLRLAN_SPARE_SPARE_BITS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_SPARE_SPARE_BITS_SHIFT)
-#define I40E_PRT_SWR_PM_THR                 0x0026CD00
-#define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0
-#define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK  I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT)
-#define I40E_RCU_PST_DBG_CTL                           0x0026CC24
-#define I40E_RCU_PST_DBG_CTL_IGNORE_FLR_SHIFT          0
-#define I40E_RCU_PST_DBG_CTL_IGNORE_FLR_MASK           I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_FLR_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_IGNORE_VFLR_SHIFT         1
-#define I40E_RCU_PST_DBG_CTL_IGNORE_VFLR_MASK          I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_VFLR_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_IGNORE_VMLR_SHIFT         2
-#define I40E_RCU_PST_DBG_CTL_IGNORE_VMLR_MASK          I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_VMLR_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_USE_PCTYPE_FCOE_SHIFT     3
-#define I40E_RCU_PST_DBG_CTL_USE_PCTYPE_FCOE_MASK      I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_USE_PCTYPE_FCOE_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_IGNORE_ETH_HIT_SHIFT      4
-#define I40E_RCU_PST_DBG_CTL_IGNORE_ETH_HIT_MASK       I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_ETH_HIT_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_IGNORE_MAC_VLAN_HIT_SHIFT 5
-#define I40E_RCU_PST_DBG_CTL_IGNORE_MAC_VLAN_HIT_MASK  I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_MAC_VLAN_HIT_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_IGNORE_SWR_DROP_SHIFT     6
-#define I40E_RCU_PST_DBG_CTL_IGNORE_SWR_DROP_MASK      I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_SWR_DROP_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_HOLD_FLU_JOBS_SHIFT       7
-#define I40E_RCU_PST_DBG_CTL_HOLD_FLU_JOBS_MASK        I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_HOLD_FLU_JOBS_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_FC_HASH_BASE_SHIFT        8
-#define I40E_RCU_PST_DBG_CTL_FC_HASH_BASE_MASK         I40E_MASK(0xF, I40E_RCU_PST_DBG_CTL_FC_HASH_BASE_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_PE_HASH_BASE_SHIFT        12
-#define I40E_RCU_PST_DBG_CTL_PE_HASH_BASE_MASK         I40E_MASK(0xF, I40E_RCU_PST_DBG_CTL_PE_HASH_BASE_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_FD_HASH_BASE_SHIFT        16
-#define I40E_RCU_PST_DBG_CTL_FD_HASH_BASE_MASK         I40E_MASK(0xF, I40E_RCU_PST_DBG_CTL_FD_HASH_BASE_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_FOC_CNTX_LIMIT_BASE_SHIFT 20
-#define I40E_RCU_PST_DBG_CTL_FOC_CNTX_LIMIT_BASE_MASK  I40E_MASK(0xF, I40E_RCU_PST_DBG_CTL_FOC_CNTX_LIMIT_BASE_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_ERR_COMP_DIS_SHIFT        24
-#define I40E_RCU_PST_DBG_CTL_ERR_COMP_DIS_MASK         I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_ERR_COMP_DIS_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_REM_COMP_DIS_SHIFT        25
-#define I40E_RCU_PST_DBG_CTL_REM_COMP_DIS_MASK         I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_REM_COMP_DIS_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_HOLD_PST_INPUT_SHIFT      28
-#define I40E_RCU_PST_DBG_CTL_HOLD_PST_INPUT_MASK       I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_HOLD_PST_INPUT_SHIFT)
-#define I40E_RCU_PST_DBG_CTL_INC_INPUT_CMD_SHIFT       29
-#define I40E_RCU_PST_DBG_CTL_INC_INPUT_CMD_MASK        I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_INC_INPUT_CMD_SHIFT)
-#define I40E_RCU_PST_DBG_DROP_CNT                         0x0026CBEC
-#define I40E_RCU_PST_DBG_DROP_CNT_FD_DROP_CNT_SHIFT       0
-#define I40E_RCU_PST_DBG_DROP_CNT_FD_DROP_CNT_MASK        I40E_MASK(0xFF, I40E_RCU_PST_DBG_DROP_CNT_FD_DROP_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_DROP_CNT_FLR_DROP_CNT_SHIFT      8
-#define I40E_RCU_PST_DBG_DROP_CNT_FLR_DROP_CNT_MASK       I40E_MASK(0xFF, I40E_RCU_PST_DBG_DROP_CNT_FLR_DROP_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_DROP_CNT_PF_BOUND_DROP_CNT_SHIFT 16
-#define I40E_RCU_PST_DBG_DROP_CNT_PF_BOUND_DROP_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_DBG_DROP_CNT_PF_BOUND_DROP_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_DROP_CNT_SWR_DROP_CNT_SHIFT      24
-#define I40E_RCU_PST_DBG_DROP_CNT_SWR_DROP_CNT_MASK       I40E_MASK(0xFF, I40E_RCU_PST_DBG_DROP_CNT_SWR_DROP_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_FLU_STATE(_i)             (0x0026CB80 + ((_i) * 4)) /* _i=0...15 */
-#define I40E_RCU_PST_DBG_FLU_STATE_MAX_INDEX       15
-#define I40E_RCU_PST_DBG_FLU_STATE_FLU_STATE_SHIFT 0
-#define I40E_RCU_PST_DBG_FLU_STATE_FLU_STATE_MASK  I40E_MASK(0x1F, I40E_RCU_PST_DBG_FLU_STATE_FLU_STATE_SHIFT)
-#define I40E_RCU_PST_DBG_FLU_STATE_FLU_HASH_SHIFT  5
-#define I40E_RCU_PST_DBG_FLU_STATE_FLU_HASH_MASK   I40E_MASK(0xFFFFF, I40E_RCU_PST_DBG_FLU_STATE_FLU_HASH_SHIFT)
-#define I40E_RCU_PST_DBG_FLU_STATE_FLU_OBJ_SHIFT   25
-#define I40E_RCU_PST_DBG_FLU_STATE_FLU_OBJ_MASK    I40E_MASK(0x7, I40E_RCU_PST_DBG_FLU_STATE_FLU_OBJ_SHIFT)
-#define I40E_RCU_PST_DBG_FLU_STATE_FLU_CMD_SHIFT   28
-#define I40E_RCU_PST_DBG_FLU_STATE_FLU_CMD_MASK    I40E_MASK(0xF, I40E_RCU_PST_DBG_FLU_STATE_FLU_CMD_SHIFT)
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_0                     0x0026CC14
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_CONF_FAIL_CNT_SHIFT 0
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_CONF_FAIL_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_0_CONF_FAIL_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_QUAD_HIT_CNT_SHIFT  8
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_QUAD_HIT_CNT_MASK   I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_0_QUAD_HIT_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_ETH_HIT_CNT_SHIFT   16
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_ETH_HIT_CNT_MASK    I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_0_ETH_HIT_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_FCOE_CNT_SHIFT      24
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_FCOE_CNT_MASK       I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_0_FCOE_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_1                    0x0026CC1C
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_FD_HIT_CNT_SHIFT   0
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_FD_HIT_CNT_MASK    I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_1_FD_HIT_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_MAC_VLAN_CNT_SHIFT 8
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_MAC_VLAN_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_1_MAC_VLAN_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_RSS_CNT_SHIFT      16
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_RSS_CNT_MASK       I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_1_RSS_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_DEFAULT_CNT_SHIFT  24
-#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_DEFAULT_CNT_MASK   I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_1_DEFAULT_CNT_SHIFT)
-#define I40E_RCU_PST_DBG_STATUS_0                      0x0026CC04
-#define I40E_RCU_PST_DBG_STATUS_0_PST_FLR_STAT_SHIFT   0
-#define I40E_RCU_PST_DBG_STATUS_0_PST_FLR_STAT_MASK    I40E_MASK(0xFFFF, I40E_RCU_PST_DBG_STATUS_0_PST_FLR_STAT_SHIFT)
-#define I40E_RCU_PST_DBG_STATUS_0_INPUT_FIFO_OCC_SHIFT 16
-#define I40E_RCU_PST_DBG_STATUS_0_INPUT_FIFO_OCC_MASK  I40E_MASK(0x3, I40E_RCU_PST_DBG_STATUS_0_INPUT_FIFO_OCC_SHIFT)
-#define I40E_RCU_PST_DBG_STATUS_1                      0x0026CC0C
-#define I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_START_SHIFT 0
-#define I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_START_MASK  I40E_MASK(0xFFFF, I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_START_SHIFT)
-#define I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_DONE_SHIFT  16
-#define I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_DONE_MASK   I40E_MASK(0xFFFF, I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_DONE_SHIFT)
-#define I40E_RCU_PST_FOC_ACCESS_STATUS                     0x00270110
-#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT 0
-#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT)
-#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT 8
-#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT)
-#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT       16
-#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_MASK        I40E_MASK(0xFF, I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT)
-#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT 24
-#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_MASK  I40E_MASK(0x7, I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT)
-#define I40E_RCU_PST_INPUT_ACL_STATUS(_i)                            (0x00270100 + ((_i) * 4)) /* _i=0...2 */
-#define I40E_RCU_PST_INPUT_ACL_STATUS_MAX_INDEX                      2
-#define I40E_RCU_PST_INPUT_ACL_STATUS_RCU_PST_INPUT_ACL_STATUS_SHIFT 0
-#define I40E_RCU_PST_INPUT_ACL_STATUS_RCU_PST_INPUT_ACL_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_INPUT_ACL_STATUS_RCU_PST_INPUT_ACL_STATUS_SHIFT)
-#define I40E_RCU_PST_INPUT_MTG_FIELDS(_i)                            (0x00270080 + ((_i) * 4)) /* _i=0...31 */
-#define I40E_RCU_PST_INPUT_MTG_FIELDS_MAX_INDEX                      31
-#define I40E_RCU_PST_INPUT_MTG_FIELDS_RCU_PST_INPUT_MTG_FIELDS_SHIFT 0
-#define I40E_RCU_PST_INPUT_MTG_FIELDS_RCU_PST_INPUT_MTG_FIELDS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_INPUT_MTG_FIELDS_RCU_PST_INPUT_MTG_FIELDS_SHIFT)
-#define I40E_RCU_PST_INPUT_MTG_STATUS(_i)                            (0x00270060 + ((_i) * 4)) /* _i=0...7 */
-#define I40E_RCU_PST_INPUT_MTG_STATUS_MAX_INDEX                      7
-#define I40E_RCU_PST_INPUT_MTG_STATUS_RCU_PST_INPUT_MTG_STATUS_SHIFT 0
-#define I40E_RCU_PST_INPUT_MTG_STATUS_RCU_PST_INPUT_MTG_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_INPUT_MTG_STATUS_RCU_PST_INPUT_MTG_STATUS_SHIFT)
-#define I40E_RCU_PST_OUTFIFO_OCC(_i)            (0x0026CFE0 + ((_i) * 4)) /* _i=0...7 */
-#define I40E_RCU_PST_OUTFIFO_OCC_MAX_INDEX      7
-#define I40E_RCU_PST_OUTFIFO_OCC_UP_1_OCC_SHIFT 0
-#define I40E_RCU_PST_OUTFIFO_OCC_UP_1_OCC_MASK  I40E_MASK(0xFF, I40E_RCU_PST_OUTFIFO_OCC_UP_1_OCC_SHIFT)
-#define I40E_RCU_PST_OUTFIFO_OCC_UP_2_OCC_SHIFT 8
-#define I40E_RCU_PST_OUTFIFO_OCC_UP_2_OCC_MASK  I40E_MASK(0xFF, I40E_RCU_PST_OUTFIFO_OCC_UP_2_OCC_SHIFT)
-#define I40E_RCU_PST_OUTFIFO_OCC_UP_3_OCC_SHIFT 16
-#define I40E_RCU_PST_OUTFIFO_OCC_UP_3_OCC_MASK  I40E_MASK(0xFF, I40E_RCU_PST_OUTFIFO_OCC_UP_3_OCC_SHIFT)
-#define I40E_RCU_PST_OUTFIFO_OCC_UP_4_OCC_SHIFT 24
-#define I40E_RCU_PST_OUTFIFO_OCC_UP_4_OCC_MASK  I40E_MASK(0xFF, I40E_RCU_PST_OUTFIFO_OCC_UP_4_OCC_SHIFT)
-#define I40E_RCU_PST_RCB_ACL_STATUS(_i)                          (0x00270030 + ((_i) * 4)) /* _i=0...2 */
-#define I40E_RCU_PST_RCB_ACL_STATUS_MAX_INDEX                    2
-#define I40E_RCU_PST_RCB_ACL_STATUS_RCU_PST_RCB_ACL_STATUS_SHIFT 0
-#define I40E_RCU_PST_RCB_ACL_STATUS_RCU_PST_RCB_ACL_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_RCB_ACL_STATUS_RCU_PST_RCB_ACL_STATUS_SHIFT)
-#define I40E_RCU_PST_RCB_FIFO_FIELDS(_i)                           (0x00270000 + ((_i) * 4)) /* _i=0...5 */
-#define I40E_RCU_PST_RCB_FIFO_FIELDS_MAX_INDEX                     5
-#define I40E_RCU_PST_RCB_FIFO_FIELDS_RCU_PST_RCB_FIFO_FIELDS_SHIFT 0
-#define I40E_RCU_PST_RCB_FIFO_FIELDS_RCU_PST_RCB_FIFO_FIELDS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_RCB_FIFO_FIELDS_RCU_PST_RCB_FIFO_FIELDS_SHIFT)
-#define I40E_RCU_PST_RCB_FIFO_Q_STATUS(_i)                             (0x00270020 + ((_i) * 4)) /* _i=0...3 */
-#define I40E_RCU_PST_RCB_FIFO_Q_STATUS_MAX_INDEX                       3
-#define I40E_RCU_PST_RCB_FIFO_Q_STATUS_RCU_PST_RCB_FIFO_Q_STATUS_SHIFT 0
-#define I40E_RCU_PST_RCB_FIFO_Q_STATUS_RCU_PST_RCB_FIFO_Q_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_RCB_FIFO_Q_STATUS_RCU_PST_RCB_FIFO_Q_STATUS_SHIFT)
-#define I40E_RCU_PST_RCB_MTG_STATUS(_i)                          (0x00270040 + ((_i) * 4)) /* _i=0...7 */
-#define I40E_RCU_PST_RCB_MTG_STATUS_MAX_INDEX                    7
-#define I40E_RCU_PST_RCB_MTG_STATUS_RCU_PST_RCB_MTG_STATUS_SHIFT 0
-#define I40E_RCU_PST_RCB_MTG_STATUS_RCU_PST_RCB_MTG_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_RCB_MTG_STATUS_RCU_PST_RCB_MTG_STATUS_SHIFT)
-#define I40E_RCU_PST_RCB_OUT_CTL                     0x0026CDA8
-#define I40E_RCU_PST_RCB_OUT_CTL_BLOCK_RCB_OUT_SHIFT 0
-#define I40E_RCU_PST_RCB_OUT_CTL_BLOCK_RCB_OUT_MASK  I40E_MASK(0x1, I40E_RCU_PST_RCB_OUT_CTL_BLOCK_RCB_OUT_SHIFT)
-#define I40E_RCU_PST_RCB_OUT_CTL_STEP_ONE_CMD_SHIFT  1
-#define I40E_RCU_PST_RCB_OUT_CTL_STEP_ONE_CMD_MASK   I40E_MASK(0x1, I40E_RCU_PST_RCB_OUT_CTL_STEP_ONE_CMD_SHIFT)
-#define I40E_RCU_PST_RCB_OUT_STAT                    0x0026CC18
-#define I40E_RCU_PST_RCB_OUT_STAT_RCB_FIFO_OCC_SHIFT 0
-#define I40E_RCU_PST_RCB_OUT_STAT_RCB_FIFO_OCC_MASK  I40E_MASK(0xF, I40E_RCU_PST_RCB_OUT_STAT_RCB_FIFO_OCC_SHIFT)
-#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_IPLEN_SHIFT   8
-#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_IPLEN_MASK    I40E_MASK(0xFFFF, I40E_RCU_PST_RCB_OUT_STAT_NEXT_IPLEN_SHIFT)
-#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_TYPE_SHIFT    24
-#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_TYPE_MASK     I40E_MASK(0x7, I40E_RCU_PST_RCB_OUT_STAT_NEXT_TYPE_SHIFT)
-#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_CFG_ERR_SHIFT 28
-#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_CFG_ERR_MASK  I40E_MASK(0x1, I40E_RCU_PST_RCB_OUT_STAT_NEXT_CFG_ERR_SHIFT)
-#define I40E_RCU_PST_RCB_OUT_STAT_RSV3_SHIFT         29
-#define I40E_RCU_PST_RCB_OUT_STAT_RSV3_MASK          I40E_MASK(0x7, I40E_RCU_PST_RCB_OUT_STAT_RSV3_SHIFT)
-#define I40E_GL_GP_FUSE(_i)              (0x0009400C + ((_i) * 4)) /* _i=0...28 */
+#define I40E_GL_GP_FUSE(_i)              (0x0009400C + ((_i) * 4)) /* _i=0...28 */ /* Reset: POR */
 #define I40E_GL_GP_FUSE_MAX_INDEX        28
 #define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0
 #define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT)
-#define I40E_GL_UFUSE                        0x00094008
+#define I40E_GL_UFUSE                        0x00094008 /* Reset: POR */
 #define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1
 #define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK  I40E_MASK(0x1, I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT)
 #define I40E_GL_UFUSE_NIC_ID_SHIFT           2
@@ -996,7 +784,7 @@
 #define I40E_GL_UFUSE_ULT_LOCKOUT_MASK       I40E_MASK(0x1, I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT)
 #define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT      11
 #define I40E_GL_UFUSE_CLS_LOCKOUT_MASK       I40E_MASK(0x1, I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT)
-#define I40E_EMPINT_GPIO_ENA                  0x00088188
+#define I40E_EMPINT_GPIO_ENA                  0x00088188 /* Reset: POR */
 #define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT  0
 #define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT)
 #define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT  1
@@ -1057,12 +845,12 @@
 #define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT)
 #define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
 #define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT)
-#define I40E_PFGEN_PORTMDIO_NUM                       0x0003F100
+#define I40E_PFGEN_PORTMDIO_NUM                       0x0003F100 /* Reset: CORER */
 #define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT        0
 #define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK         I40E_MASK(0x3, I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT)
 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4
 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK  I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT)
-#define I40E_PFINT_AEQCTL                  0x00038700
+#define I40E_PFINT_AEQCTL                  0x00038700 /* Reset: CORER */
 #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT  0
 #define I40E_PFINT_AEQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT)
 #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT   11
@@ -1073,7 +861,7 @@
 #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT)
 #define I40E_PFINT_AEQCTL_INTEVENT_SHIFT   31
 #define I40E_PFINT_AEQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_PFINT_AEQCTL_INTEVENT_SHIFT)
-#define I40E_PFINT_CEQCTL(_INTPF)          (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */
+#define I40E_PFINT_CEQCTL(_INTPF)          (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */
 #define I40E_PFINT_CEQCTL_MAX_INDEX        511
 #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT  0
 #define I40E_PFINT_CEQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT)
@@ -1089,7 +877,7 @@
 #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)
 #define I40E_PFINT_CEQCTL_INTEVENT_SHIFT   31
 #define I40E_PFINT_CEQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)
-#define I40E_PFINT_DYN_CTL0                       0x00038480
+#define I40E_PFINT_DYN_CTL0                       0x00038480 /* Reset: PFR */
 #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT          0
 #define I40E_PFINT_DYN_CTL0_INTENA_MASK           I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)
 #define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT        1
@@ -1106,7 +894,7 @@
 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT      31
 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT)
-#define I40E_PFINT_DYN_CTLN(_INTPF)               (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */
+#define I40E_PFINT_DYN_CTLN(_INTPF)               (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
 #define I40E_PFINT_DYN_CTLN_MAX_INDEX             511
 #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT          0
 #define I40E_PFINT_DYN_CTLN_INTENA_MASK           I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT)
@@ -1124,7 +912,7 @@
 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
 #define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT      31
 #define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT)
-#define I40E_PFINT_GPIO_ENA                  0x00088080
+#define I40E_PFINT_GPIO_ENA                  0x00088080 /* Reset: CORER */
 #define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT  0
 #define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT)
 #define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT  1
@@ -1185,7 +973,7 @@
 #define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT)
 #define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
 #define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT)
-#define I40E_PFINT_ICR0                        0x00038780
+#define I40E_PFINT_ICR0                        0x00038780 /* Reset: CORER */
 #define I40E_PFINT_ICR0_INTEVENT_SHIFT         0
 #define I40E_PFINT_ICR0_INTEVENT_MASK          I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT)
 #define I40E_PFINT_ICR0_QUEUE_0_SHIFT          1
@@ -1230,7 +1018,7 @@
 #define I40E_PFINT_ICR0_ADMINQ_MASK            I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT)
 #define I40E_PFINT_ICR0_SWINT_SHIFT            31
 #define I40E_PFINT_ICR0_SWINT_MASK             I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT)
-#define I40E_PFINT_ICR0_ENA                        0x00038800
+#define I40E_PFINT_ICR0_ENA                        0x00038800 /* Reset: CORER */
 #define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT          16
 #define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT)
 #define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT       19
@@ -1257,40 +1045,40 @@
 #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK            I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT)
 #define I40E_PFINT_ICR0_ENA_RSVD_SHIFT             31
 #define I40E_PFINT_ICR0_ENA_RSVD_MASK              I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_RSVD_SHIFT)
-#define I40E_PFINT_ITR0(_i)            (0x00038000 + ((_i) * 128)) /* _i=0...2 */
+#define I40E_PFINT_ITR0(_i)            (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */
 #define I40E_PFINT_ITR0_MAX_INDEX      2
 #define I40E_PFINT_ITR0_INTERVAL_SHIFT 0
 #define I40E_PFINT_ITR0_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_PFINT_ITR0_INTERVAL_SHIFT)
-#define I40E_PFINT_ITRN(_i, _INTPF)     (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */
+#define I40E_PFINT_ITRN(_i, _INTPF)     (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */
 #define I40E_PFINT_ITRN_MAX_INDEX      2
 #define I40E_PFINT_ITRN_INTERVAL_SHIFT 0
 #define I40E_PFINT_ITRN_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_PFINT_ITRN_INTERVAL_SHIFT)
-#define I40E_PFINT_LNKLST0                   0x00038500
+#define I40E_PFINT_LNKLST0                   0x00038500 /* Reset: PFR */
 #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
 #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT)
 #define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
 #define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK  I40E_MASK(0x3, I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
-#define I40E_PFINT_LNKLSTN(_INTPF)           (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */
+#define I40E_PFINT_LNKLSTN(_INTPF)           (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
 #define I40E_PFINT_LNKLSTN_MAX_INDEX         511
 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK  I40E_MASK(0x3, I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
-#define I40E_PFINT_RATE0                 0x00038580
+#define I40E_PFINT_RATE0                 0x00038580 /* Reset: PFR */
 #define I40E_PFINT_RATE0_INTERVAL_SHIFT  0
 #define I40E_PFINT_RATE0_INTERVAL_MASK   I40E_MASK(0x3F, I40E_PFINT_RATE0_INTERVAL_SHIFT)
 #define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6
 #define I40E_PFINT_RATE0_INTRL_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT)
-#define I40E_PFINT_RATEN(_INTPF)         (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */
+#define I40E_PFINT_RATEN(_INTPF)         (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
 #define I40E_PFINT_RATEN_MAX_INDEX       511
 #define I40E_PFINT_RATEN_INTERVAL_SHIFT  0
 #define I40E_PFINT_RATEN_INTERVAL_MASK   I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)
 #define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6
 #define I40E_PFINT_RATEN_INTRL_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
-#define I40E_PFINT_STAT_CTL0                      0x00038400
+#define I40E_PFINT_STAT_CTL0                      0x00038400 /* Reset: PFR */
 #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
 #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK  I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
-#define I40E_QINT_RQCTL(_Q)              (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */
+#define I40E_QINT_RQCTL(_Q)              (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
 #define I40E_QINT_RQCTL_MAX_INDEX        1535
 #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT  0
 #define I40E_QINT_RQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT)
@@ -1306,7 +1094,7 @@
 #define I40E_QINT_RQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT)
 #define I40E_QINT_RQCTL_INTEVENT_SHIFT   31
 #define I40E_QINT_RQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT)
-#define I40E_QINT_TQCTL(_Q)              (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */
+#define I40E_QINT_TQCTL(_Q)              (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
 #define I40E_QINT_TQCTL_MAX_INDEX        1535
 #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT  0
 #define I40E_QINT_TQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT)
@@ -1322,7 +1110,7 @@
 #define I40E_QINT_TQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT)
 #define I40E_QINT_TQCTL_INTEVENT_SHIFT   31
 #define I40E_QINT_TQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT)
-#define I40E_VFINT_DYN_CTL0(_VF)                  (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VFINT_DYN_CTL0(_VF)                  (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VFINT_DYN_CTL0_MAX_INDEX             127
 #define I40E_VFINT_DYN_CTL0_INTENA_SHIFT          0
 #define I40E_VFINT_DYN_CTL0_INTENA_MASK           I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_SHIFT)
@@ -1340,7 +1128,7 @@
 #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
 #define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT      31
 #define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT)
-#define I40E_VFINT_DYN_CTLN(_INTVF)               (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */
+#define I40E_VFINT_DYN_CTLN(_INTVF)               (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
 #define I40E_VFINT_DYN_CTLN_MAX_INDEX             511
 #define I40E_VFINT_DYN_CTLN_INTENA_SHIFT          0
 #define I40E_VFINT_DYN_CTLN_INTENA_MASK           I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_SHIFT)
@@ -1358,7 +1146,7 @@
 #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
 #define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT      31
 #define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT)
-#define I40E_VFINT_ICR0(_VF)                   (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VFINT_ICR0(_VF)                   (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VFINT_ICR0_MAX_INDEX              127
 #define I40E_VFINT_ICR0_INTEVENT_SHIFT         0
 #define I40E_VFINT_ICR0_INTEVENT_MASK          I40E_MASK(0x1, I40E_VFINT_ICR0_INTEVENT_SHIFT)
@@ -1376,7 +1164,7 @@
 #define I40E_VFINT_ICR0_ADMINQ_MASK            I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT)
 #define I40E_VFINT_ICR0_SWINT_SHIFT            31
 #define I40E_VFINT_ICR0_SWINT_MASK             I40E_MASK(0x1, I40E_VFINT_ICR0_SWINT_SHIFT)
-#define I40E_VFINT_ICR0_ENA(_VF)                   (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VFINT_ICR0_ENA(_VF)                   (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VFINT_ICR0_ENA_MAX_INDEX              127
 #define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
 #define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK  I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
@@ -1384,19 +1172,19 @@
 #define I40E_VFINT_ICR0_ENA_ADMINQ_MASK            I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT)
 #define I40E_VFINT_ICR0_ENA_RSVD_SHIFT             31
 #define I40E_VFINT_ICR0_ENA_RSVD_MASK              I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_RSVD_SHIFT)
-#define I40E_VFINT_ITR0(_i, _VF)        (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */
+#define I40E_VFINT_ITR0(_i, _VF)        (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */
 #define I40E_VFINT_ITR0_MAX_INDEX      2
 #define I40E_VFINT_ITR0_INTERVAL_SHIFT 0
 #define I40E_VFINT_ITR0_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT)
-#define I40E_VFINT_ITRN(_i, _INTVF)     (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */
+#define I40E_VFINT_ITRN(_i, _INTVF)     (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */
 #define I40E_VFINT_ITRN_MAX_INDEX      2
 #define I40E_VFINT_ITRN_INTERVAL_SHIFT 0
 #define I40E_VFINT_ITRN_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)
-#define I40E_VFINT_STAT_CTL0(_VF)                 (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VFINT_STAT_CTL0(_VF)                 (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VFINT_STAT_CTL0_MAX_INDEX            127
 #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
 #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK  I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
-#define I40E_VPINT_AEQCTL(_VF)             (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPINT_AEQCTL(_VF)             (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VPINT_AEQCTL_MAX_INDEX        127
 #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT  0
 #define I40E_VPINT_AEQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT)
@@ -1408,7 +1196,7 @@
 #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT)
 #define I40E_VPINT_AEQCTL_INTEVENT_SHIFT   31
 #define I40E_VPINT_AEQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_VPINT_AEQCTL_INTEVENT_SHIFT)
-#define I40E_VPINT_CEQCTL(_INTVF)          (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */
+#define I40E_VPINT_CEQCTL(_INTVF)          (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */
 #define I40E_VPINT_CEQCTL_MAX_INDEX        511
 #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT  0
 #define I40E_VPINT_CEQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT)
@@ -1424,48 +1212,48 @@
 #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT)
 #define I40E_VPINT_CEQCTL_INTEVENT_SHIFT   31
 #define I40E_VPINT_CEQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_VPINT_CEQCTL_INTEVENT_SHIFT)
-#define I40E_VPINT_LNKLST0(_VF)              (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPINT_LNKLST0(_VF)              (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VPINT_LNKLST0_MAX_INDEX         127
 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT)
 #define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
 #define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK  I40E_MASK(0x3, I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
-#define I40E_VPINT_LNKLSTN(_INTVF)           (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */
+#define I40E_VPINT_LNKLSTN(_INTVF)           (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
 #define I40E_VPINT_LNKLSTN_MAX_INDEX         511
 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK  I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
-#define I40E_VPINT_RATE0(_VF)            (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPINT_RATE0(_VF)            (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VPINT_RATE0_MAX_INDEX       127
 #define I40E_VPINT_RATE0_INTERVAL_SHIFT  0
 #define I40E_VPINT_RATE0_INTERVAL_MASK   I40E_MASK(0x3F, I40E_VPINT_RATE0_INTERVAL_SHIFT)
 #define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6
 #define I40E_VPINT_RATE0_INTRL_ENA_MASK  I40E_MASK(0x1, I40E_VPINT_RATE0_INTRL_ENA_SHIFT)
-#define I40E_VPINT_RATEN(_INTVF)         (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */
+#define I40E_VPINT_RATEN(_INTVF)         (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
 #define I40E_VPINT_RATEN_MAX_INDEX       511
 #define I40E_VPINT_RATEN_INTERVAL_SHIFT  0
 #define I40E_VPINT_RATEN_INTERVAL_MASK   I40E_MASK(0x3F, I40E_VPINT_RATEN_INTERVAL_SHIFT)
 #define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6
 #define I40E_VPINT_RATEN_INTRL_ENA_MASK  I40E_MASK(0x1, I40E_VPINT_RATEN_INTRL_ENA_SHIFT)
-#define I40E_GL_RDPU_CNTRL                 0x00051060
+#define I40E_GL_RDPU_CNTRL                 0x00051060 /* Reset: CORER */
 #define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0
 #define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK  I40E_MASK(0x1, I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT)
 #define I40E_GL_RDPU_CNTRL_ECO_SHIFT       1
 #define I40E_GL_RDPU_CNTRL_ECO_MASK        I40E_MASK(0x7FFFFFFF, I40E_GL_RDPU_CNTRL_ECO_SHIFT)
-#define I40E_GLLAN_RCTL_0                0x0012A500
+#define I40E_GLLAN_RCTL_0                0x0012A500 /* Reset: CORER */
 #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0
 #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK  I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT)
-#define I40E_GLLAN_TSOMSK_F               0x000442D8
+#define I40E_GLLAN_TSOMSK_F               0x000442D8 /* Reset: CORER */
 #define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0
 #define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK  I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT)
-#define I40E_GLLAN_TSOMSK_L               0x000442E0
+#define I40E_GLLAN_TSOMSK_L               0x000442E0 /* Reset: CORER */
 #define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0
 #define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK  I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT)
-#define I40E_GLLAN_TSOMSK_M               0x000442DC
+#define I40E_GLLAN_TSOMSK_M               0x000442DC /* Reset: CORER */
 #define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0
 #define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK  I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT)
-#define I40E_GLLAN_TXPRE_QDIS(_i)              (0x000e6500 + ((_i) * 4)) /* _i=0...11 */
+#define I40E_GLLAN_TXPRE_QDIS(_i)              (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */
 #define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX        11
 #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT      0
 #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK       I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)
@@ -1475,14 +1263,14 @@
 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK    I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31
 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK  I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
-#define I40E_PFLAN_QALLOC              0x001C0400
+#define I40E_PFLAN_QALLOC              0x001C0400 /* Reset: CORER */
 #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
 #define I40E_PFLAN_QALLOC_FIRSTQ_MASK  I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
 #define I40E_PFLAN_QALLOC_LASTQ_SHIFT  16
 #define I40E_PFLAN_QALLOC_LASTQ_MASK   I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
 #define I40E_PFLAN_QALLOC_VALID_SHIFT  31
 #define I40E_PFLAN_QALLOC_VALID_MASK   I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)
-#define I40E_QRX_ENA(_Q)             (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */
+#define I40E_QRX_ENA(_Q)             (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
 #define I40E_QRX_ENA_MAX_INDEX       1535
 #define I40E_QRX_ENA_QENA_REQ_SHIFT  0
 #define I40E_QRX_ENA_QENA_REQ_MASK   I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT)
@@ -1490,11 +1278,11 @@
 #define I40E_QRX_ENA_FAST_QDIS_MASK  I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT)
 #define I40E_QRX_ENA_QENA_STAT_SHIFT 2
 #define I40E_QRX_ENA_QENA_STAT_MASK  I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT)
-#define I40E_QRX_TAIL(_Q)        (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */
+#define I40E_QRX_TAIL(_Q)        (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
 #define I40E_QRX_TAIL_MAX_INDEX  1535
 #define I40E_QRX_TAIL_TAIL_SHIFT 0
 #define I40E_QRX_TAIL_TAIL_MASK  I40E_MASK(0x1FFF, I40E_QRX_TAIL_TAIL_SHIFT)
-#define I40E_QTX_CTL(_Q)             (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */
+#define I40E_QTX_CTL(_Q)             (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
 #define I40E_QTX_CTL_MAX_INDEX       1535
 #define I40E_QTX_CTL_PFVF_Q_SHIFT    0
 #define I40E_QTX_CTL_PFVF_Q_MASK     I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT)
@@ -1502,7 +1290,7 @@
 #define I40E_QTX_CTL_PF_INDX_MASK    I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT)
 #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7
 #define I40E_QTX_CTL_VFVM_INDX_MASK  I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT)
-#define I40E_QTX_ENA(_Q)             (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */
+#define I40E_QTX_ENA(_Q)             (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
 #define I40E_QTX_ENA_MAX_INDEX       1535
 #define I40E_QTX_ENA_QENA_REQ_SHIFT  0
 #define I40E_QTX_ENA_QENA_REQ_MASK   I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT)
@@ -1510,89 +1298,89 @@
 #define I40E_QTX_ENA_FAST_QDIS_MASK  I40E_MASK(0x1, I40E_QTX_ENA_FAST_QDIS_SHIFT)
 #define I40E_QTX_ENA_QENA_STAT_SHIFT 2
 #define I40E_QTX_ENA_QENA_STAT_MASK  I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT)
-#define I40E_QTX_HEAD(_Q)              (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */
+#define I40E_QTX_HEAD(_Q)              (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
 #define I40E_QTX_HEAD_MAX_INDEX        1535
 #define I40E_QTX_HEAD_HEAD_SHIFT       0
 #define I40E_QTX_HEAD_HEAD_MASK        I40E_MASK(0x1FFF, I40E_QTX_HEAD_HEAD_SHIFT)
 #define I40E_QTX_HEAD_RS_PENDING_SHIFT 16
 #define I40E_QTX_HEAD_RS_PENDING_MASK  I40E_MASK(0x1, I40E_QTX_HEAD_RS_PENDING_SHIFT)
-#define I40E_QTX_TAIL(_Q)        (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */
+#define I40E_QTX_TAIL(_Q)        (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
 #define I40E_QTX_TAIL_MAX_INDEX  1535
 #define I40E_QTX_TAIL_TAIL_SHIFT 0
 #define I40E_QTX_TAIL_TAIL_MASK  I40E_MASK(0x1FFF, I40E_QTX_TAIL_TAIL_SHIFT)
-#define I40E_VPLAN_MAPENA(_VF)           (0x00074000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPLAN_MAPENA(_VF)           (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VPLAN_MAPENA_MAX_INDEX      127
 #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0
 #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK  I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT)
-#define I40E_VPLAN_QTABLE(_i, _VF)      (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */
+#define I40E_VPLAN_QTABLE(_i, _VF)      (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */
 #define I40E_VPLAN_QTABLE_MAX_INDEX    15
 #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0
 #define I40E_VPLAN_QTABLE_QINDEX_MASK  I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT)
-#define I40E_VSILAN_QBASE(_VSI)               (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSILAN_QBASE(_VSI)               (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSILAN_QBASE_MAX_INDEX           383
 #define I40E_VSILAN_QBASE_VSIBASE_SHIFT       0
 #define I40E_VSILAN_QBASE_VSIBASE_MASK        I40E_MASK(0x7FF, I40E_VSILAN_QBASE_VSIBASE_SHIFT)
 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11
 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK  I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)
-#define I40E_VSILAN_QTABLE(_i, _VSI)       (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */
+#define I40E_VSILAN_QTABLE(_i, _VSI)       (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */
 #define I40E_VSILAN_QTABLE_MAX_INDEX      7
 #define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0
 #define I40E_VSILAN_QTABLE_QINDEX_0_MASK  I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_0_SHIFT)
 #define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16
 #define I40E_VSILAN_QTABLE_QINDEX_1_MASK  I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_1_SHIFT)
-#define I40E_PRTGL_SAH              0x001E2140
+#define I40E_PRTGL_SAH              0x001E2140 /* Reset: GLOBR */
 #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0
 #define I40E_PRTGL_SAH_FC_SAH_MASK  I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT)
 #define I40E_PRTGL_SAH_MFS_SHIFT    16
 #define I40E_PRTGL_SAH_MFS_MASK     I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT)
-#define I40E_PRTGL_SAL              0x001E2120
+#define I40E_PRTGL_SAL              0x001E2120 /* Reset: GLOBR */
 #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0
 #define I40E_PRTGL_SAL_FC_SAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP                              0x001E30E0
+#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP                              0x001E30E0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP                              0x001E3260
+#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP                              0x001E3260 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP                              0x001E32E0
+#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP                              0x001E32E0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL                                   0x001E3360
+#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL                                   0x001E3360 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1                                        0x001E3110
+#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1                                        0x001E3110 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2                                        0x001E3120
+#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2                                        0x001E3120 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE                                0x001E30C0
+#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE                                0x001E30C0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK  I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1                                  0x001E3140
+#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1                                  0x001E3140 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2                                  0x001E3150
+#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2                                  0x001E3150 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE                                0x001E30D0
+#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE                                0x001E30D0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK  I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i)                            (0x001E3370 + ((_i) * 16)) /* _i=0...8 */
+#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i)                            (0x001E3370 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX                      8
 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i)                                   (0x001E3400 + ((_i) * 16)) /* _i=0...8 */
+#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i)                                   (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX                             8
 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1                            0x001E34B0
+#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1                            0x001E34B0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT)
-#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2                            0x001E34C0
+#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2                            0x001E34C0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT)
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A                     0x0008C480
+#define I40E_PRTMAC_PCS_XAUI_SWAP_A                     0x0008C480 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0
 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT)
 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2
@@ -1609,7 +1397,7 @@
 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT)
 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14
 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT)
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B                     0x0008C484
+#define I40E_PRTMAC_PCS_XAUI_SWAP_B                     0x0008C484 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0
 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT)
 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2
@@ -1626,10 +1414,10 @@
 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT)
 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14
 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)
-#define I40E_GL_FWRESETCNT                  0x00083100
+#define I40E_GL_FWRESETCNT                  0x00083100 /* Reset: POR */
 #define I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT 0
 #define I40E_GL_FWRESETCNT_FWRESETCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT)
-#define I40E_GL_MNG_FWSM                              0x000B6134
+#define I40E_GL_MNG_FWSM                              0x000B6134 /* Reset: POR */
 #define I40E_GL_MNG_FWSM_FW_MODES_SHIFT               0
 #define I40E_GL_MNG_FWSM_FW_MODES_MASK                I40E_MASK(0x3, I40E_GL_MNG_FWSM_FW_MODES_SHIFT)
 #define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT         10
@@ -1650,21 +1438,21 @@
 #define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK  I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT)
 #define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29
 #define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK  I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT)
-#define I40E_GL_MNG_HWARB_CTRL                   0x000B6130
+#define I40E_GL_MNG_HWARB_CTRL                   0x000B6130 /* Reset: POR */
 #define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0
 #define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK  I40E_MASK(0x1, I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT)
-#define I40E_PRT_MNG_FTFT_DATA(_i)         (0x000852A0 + ((_i) * 32)) /* _i=0...31 */
+#define I40E_PRT_MNG_FTFT_DATA(_i)         (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ /* Reset: POR */
 #define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX   31
 #define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0
 #define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT)
-#define I40E_PRT_MNG_FTFT_LENGTH              0x00085260
+#define I40E_PRT_MNG_FTFT_LENGTH              0x00085260 /* Reset: POR */
 #define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0
 #define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK  I40E_MASK(0xFF, I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT)
-#define I40E_PRT_MNG_FTFT_MASK(_i)        (0x00085160 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRT_MNG_FTFT_MASK(_i)        (0x00085160 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
 #define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX  7
 #define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0
 #define I40E_PRT_MNG_FTFT_MASK_MASK_MASK  I40E_MASK(0xFFFF, I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT)
-#define I40E_PRT_MNG_MANC                            0x00256A20
+#define I40E_PRT_MNG_MANC                            0x00256A20 /* Reset: POR */
 #define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0
 #define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT)
 #define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT         1
@@ -1681,11 +1469,11 @@
 #define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK             I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT)
 #define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT           29
 #define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK            I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT)
-#define I40E_PRT_MNG_MAVTV(_i)       (0x00255900 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRT_MNG_MAVTV(_i)       (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
 #define I40E_PRT_MNG_MAVTV_MAX_INDEX 7
 #define I40E_PRT_MNG_MAVTV_VID_SHIFT 0
 #define I40E_PRT_MNG_MAVTV_VID_MASK  I40E_MASK(0xFFF, I40E_PRT_MNG_MAVTV_VID_SHIFT)
-#define I40E_PRT_MNG_MDEF(_i)                             (0x00255D00 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRT_MNG_MDEF(_i)                             (0x00255D00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
 #define I40E_PRT_MNG_MDEF_MAX_INDEX                       7
 #define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT             0
 #define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK              I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT)
@@ -1713,7 +1501,7 @@
 #define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK              I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT)
 #define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT             31
 #define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK              I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT)
-#define I40E_PRT_MNG_MDEF_EXT(_i)                             (0x00255F00 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRT_MNG_MDEF_EXT(_i)                             (0x00255F00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
 #define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX                       7
 #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT          0
 #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK           I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT)
@@ -1737,19 +1525,19 @@
 #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK   I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT)
 #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT     31
 #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK      I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT)
-#define I40E_PRT_MNG_MDEFVSI(_i)                (0x00256580 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRT_MNG_MDEFVSI(_i)                (0x00256580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_PRT_MNG_MDEFVSI_MAX_INDEX          3
 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT   0
 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK    I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT)
 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16
 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK  I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)
-#define I40E_PRT_MNG_METF(_i)            (0x00256780 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRT_MNG_METF(_i)            (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_PRT_MNG_METF_MAX_INDEX      3
 #define I40E_PRT_MNG_METF_ETYPE_SHIFT    0
 #define I40E_PRT_MNG_METF_ETYPE_MASK     I40E_MASK(0xFFFF, I40E_PRT_MNG_METF_ETYPE_SHIFT)
 #define I40E_PRT_MNG_METF_POLARITY_SHIFT 30
 #define I40E_PRT_MNG_METF_POLARITY_MASK  I40E_MASK(0x1, I40E_PRT_MNG_METF_POLARITY_SHIFT)
-#define I40E_PRT_MNG_MFUTP(_i)                      (0x00254E00 + ((_i) * 32)) /* _i=0...15 */
+#define I40E_PRT_MNG_MFUTP(_i)                      (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
 #define I40E_PRT_MNG_MFUTP_MAX_INDEX                15
 #define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT            0
 #define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK             I40E_MASK(0xFFFF, I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT)
@@ -1759,26 +1547,26 @@
 #define I40E_PRT_MNG_MFUTP_TCP_MASK                 I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_TCP_SHIFT)
 #define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18
 #define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT)
-#define I40E_PRT_MNG_MIPAF4(_i)         (0x00256280 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRT_MNG_MIPAF4(_i)         (0x00256280 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_PRT_MNG_MIPAF4_MAX_INDEX   3
 #define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0
 #define I40E_PRT_MNG_MIPAF4_MIPAF_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT)
-#define I40E_PRT_MNG_MIPAF6(_i)         (0x00254200 + ((_i) * 32)) /* _i=0...15 */
+#define I40E_PRT_MNG_MIPAF6(_i)         (0x00254200 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
 #define I40E_PRT_MNG_MIPAF6_MAX_INDEX   15
 #define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0
 #define I40E_PRT_MNG_MIPAF6_MIPAF_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT)
-#define I40E_PRT_MNG_MMAH(_i)        (0x00256380 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRT_MNG_MMAH(_i)        (0x00256380 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_PRT_MNG_MMAH_MAX_INDEX  3
 #define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0
 #define I40E_PRT_MNG_MMAH_MMAH_MASK  I40E_MASK(0xFFFF, I40E_PRT_MNG_MMAH_MMAH_SHIFT)
-#define I40E_PRT_MNG_MMAL(_i)        (0x00256480 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRT_MNG_MMAL(_i)        (0x00256480 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_PRT_MNG_MMAL_MAX_INDEX  3
 #define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0
 #define I40E_PRT_MNG_MMAL_MMAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MMAL_MMAL_SHIFT)
-#define I40E_PRT_MNG_MNGONLY                                  0x00256A60
+#define I40E_PRT_MNG_MNGONLY                                  0x00256A60 /* Reset: POR */
 #define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0
 #define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK  I40E_MASK(0xFF, I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT)
-#define I40E_PRT_MNG_MSFM                    0x00256AA0
+#define I40E_PRT_MNG_MSFM                    0x00256AA0 /* Reset: POR */
 #define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0
 #define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT)
 #define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1
@@ -1795,51 +1583,51 @@
 #define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK   I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT)
 #define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT  7
 #define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK   I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT)
-#define I40E_MSIX_PBA(_i)          (0x00001000 + ((_i) * 4)) /* _i=0...5 */
+#define I40E_MSIX_PBA(_i)          (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */
 #define I40E_MSIX_PBA_MAX_INDEX    5
 #define I40E_MSIX_PBA_PENBIT_SHIFT 0
 #define I40E_MSIX_PBA_PENBIT_MASK  I40E_MASK(0xFFFFFFFF, I40E_MSIX_PBA_PENBIT_SHIFT)
-#define I40E_MSIX_TADD(_i)              (0x00000000 + ((_i) * 16)) /* _i=0...128 */
+#define I40E_MSIX_TADD(_i)              (0x00000000 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
 #define I40E_MSIX_TADD_MAX_INDEX        128
 #define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0
 #define I40E_MSIX_TADD_MSIXTADD10_MASK  I40E_MASK(0x3, I40E_MSIX_TADD_MSIXTADD10_SHIFT)
 #define I40E_MSIX_TADD_MSIXTADD_SHIFT   2
 #define I40E_MSIX_TADD_MSIXTADD_MASK    I40E_MASK(0x3FFFFFFF, I40E_MSIX_TADD_MSIXTADD_SHIFT)
-#define I40E_MSIX_TMSG(_i)            (0x00000008 + ((_i) * 16)) /* _i=0...128 */
+#define I40E_MSIX_TMSG(_i)            (0x00000008 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
 #define I40E_MSIX_TMSG_MAX_INDEX      128
 #define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0
 #define I40E_MSIX_TMSG_MSIXTMSG_MASK  I40E_MASK(0xFFFFFFFF, I40E_MSIX_TMSG_MSIXTMSG_SHIFT)
-#define I40E_MSIX_TUADD(_i)             (0x00000004 + ((_i) * 16)) /* _i=0...128 */
+#define I40E_MSIX_TUADD(_i)             (0x00000004 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
 #define I40E_MSIX_TUADD_MAX_INDEX       128
 #define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0
 #define I40E_MSIX_TUADD_MSIXTUADD_MASK  I40E_MASK(0xFFFFFFFF, I40E_MSIX_TUADD_MSIXTUADD_SHIFT)
-#define I40E_MSIX_TVCTRL(_i)        (0x0000000C + ((_i) * 16)) /* _i=0...128 */
+#define I40E_MSIX_TVCTRL(_i)        (0x0000000C + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
 #define I40E_MSIX_TVCTRL_MAX_INDEX  128
 #define I40E_MSIX_TVCTRL_MASK_SHIFT 0
 #define I40E_MSIX_TVCTRL_MASK_MASK  I40E_MASK(0x1, I40E_MSIX_TVCTRL_MASK_SHIFT)
-#define I40E_VFMSIX_PBA1(_i)          (0x00002000 + ((_i) * 4)) /* _i=0...19 */
+#define I40E_VFMSIX_PBA1(_i)          (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
 #define I40E_VFMSIX_PBA1_MAX_INDEX    19
 #define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0
 #define I40E_VFMSIX_PBA1_PENBIT_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)
-#define I40E_VFMSIX_TADD1(_i)              (0x00002100 + ((_i) * 16)) /* _i=0...639 */
+#define I40E_VFMSIX_TADD1(_i)              (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
 #define I40E_VFMSIX_TADD1_MAX_INDEX        639
 #define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0
 #define I40E_VFMSIX_TADD1_MSIXTADD10_MASK  I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)
 #define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT   2
 #define I40E_VFMSIX_TADD1_MSIXTADD_MASK    I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)
-#define I40E_VFMSIX_TMSG1(_i)            (0x00002108 + ((_i) * 16)) /* _i=0...639 */
+#define I40E_VFMSIX_TMSG1(_i)            (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
 #define I40E_VFMSIX_TMSG1_MAX_INDEX      639
 #define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0
 #define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)
-#define I40E_VFMSIX_TUADD1(_i)             (0x00002104 + ((_i) * 16)) /* _i=0...639 */
+#define I40E_VFMSIX_TUADD1(_i)             (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
 #define I40E_VFMSIX_TUADD1_MAX_INDEX       639
 #define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0
 #define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)
-#define I40E_VFMSIX_TVCTRL1(_i)        (0x0000210C + ((_i) * 16)) /* _i=0...639 */
+#define I40E_VFMSIX_TVCTRL1(_i)        (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
 #define I40E_VFMSIX_TVCTRL1_MAX_INDEX  639
 #define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0
 #define I40E_VFMSIX_TVCTRL1_MASK_MASK  I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
-#define I40E_GLNVM_FLA                0x000B6108
+#define I40E_GLNVM_FLA                0x000B6108 /* Reset: POR */
 #define I40E_GLNVM_FLA_FL_SCK_SHIFT   0
 #define I40E_GLNVM_FLA_FL_SCK_MASK    I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SCK_SHIFT)
 #define I40E_GLNVM_FLA_FL_CE_SHIFT    1
@@ -1860,12 +1648,12 @@
 #define I40E_GLNVM_FLA_FL_BUSY_MASK   I40E_MASK(0x1, I40E_GLNVM_FLA_FL_BUSY_SHIFT)
 #define I40E_GLNVM_FLA_FL_DER_SHIFT   31
 #define I40E_GLNVM_FLA_FL_DER_MASK    I40E_MASK(0x1, I40E_GLNVM_FLA_FL_DER_SHIFT)
-#define I40E_GLNVM_FLASHID                  0x000B6104
+#define I40E_GLNVM_FLASHID                  0x000B6104 /* Reset: POR */
 #define I40E_GLNVM_FLASHID_FLASHID_SHIFT    0
 #define I40E_GLNVM_FLASHID_FLASHID_MASK     I40E_MASK(0xFFFFFF, I40E_GLNVM_FLASHID_FLASHID_SHIFT)
 #define I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT 31
 #define I40E_GLNVM_FLASHID_FLEEP_PERF_MASK  I40E_MASK(0x1, I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT)
-#define I40E_GLNVM_GENS                  0x000B6100
+#define I40E_GLNVM_GENS                  0x000B6100 /* Reset: POR */
 #define I40E_GLNVM_GENS_NVM_PRES_SHIFT   0
 #define I40E_GLNVM_GENS_NVM_PRES_MASK    I40E_MASK(0x1, I40E_GLNVM_GENS_NVM_PRES_SHIFT)
 #define I40E_GLNVM_GENS_SR_SIZE_SHIFT    5
@@ -1876,11 +1664,11 @@
 #define I40E_GLNVM_GENS_ALT_PRST_MASK    I40E_MASK(0x1, I40E_GLNVM_GENS_ALT_PRST_SHIFT)
 #define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25
 #define I40E_GLNVM_GENS_FL_AUTO_RD_MASK  I40E_MASK(0x1, I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT)
-#define I40E_GLNVM_PROTCSR(_i)              (0x000B6010 + ((_i) * 4)) /* _i=0...59 */
+#define I40E_GLNVM_PROTCSR(_i)              (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset: POR */
 #define I40E_GLNVM_PROTCSR_MAX_INDEX        59
 #define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0
 #define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK  I40E_MASK(0xFFFFFF, I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT)
-#define I40E_GLNVM_SRCTL              0x000B6110
+#define I40E_GLNVM_SRCTL              0x000B6110 /* Reset: POR */
 #define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0
 #define I40E_GLNVM_SRCTL_SRBUSY_MASK  I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT)
 #define I40E_GLNVM_SRCTL_ADDR_SHIFT   14
@@ -1891,12 +1679,12 @@
 #define I40E_GLNVM_SRCTL_START_MASK   I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)
 #define I40E_GLNVM_SRCTL_DONE_SHIFT   31
 #define I40E_GLNVM_SRCTL_DONE_MASK    I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)
-#define I40E_GLNVM_SRDATA              0x000B6114
+#define I40E_GLNVM_SRDATA              0x000B6114 /* Reset: POR */
 #define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
 #define I40E_GLNVM_SRDATA_WRDATA_MASK  I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
 #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16
 #define I40E_GLNVM_SRDATA_RDDATA_MASK  I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
-#define I40E_GLNVM_ULD                          0x000B6008
+#define I40E_GLNVM_ULD                          0x000B6008 /* Reset: POR */
 #define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT     0
 #define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK      I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)
 #define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT   1
@@ -1917,16 +1705,16 @@
 #define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK       I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT)
 #define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT   9
 #define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK    I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT)
-#define I40E_GLPCI_BYTCTH                        0x0009C484
+#define I40E_GLPCI_BYTCTH                        0x0009C484 /* Reset: PCIR */
 #define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0
 #define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT)
-#define I40E_GLPCI_BYTCTL                        0x0009C488
+#define I40E_GLPCI_BYTCTL                        0x0009C488 /* Reset: PCIR */
 #define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0
 #define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT)
-#define I40E_GLPCI_CAPCTRL              0x000BE4A4
+#define I40E_GLPCI_CAPCTRL              0x000BE4A4 /* Reset: PCIR */
 #define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0
 #define I40E_GLPCI_CAPCTRL_VPD_EN_MASK  I40E_MASK(0x1, I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT)
-#define I40E_GLPCI_CAPSUP                      0x000BE4A8
+#define I40E_GLPCI_CAPSUP                      0x000BE4A8 /* Reset: PCIR */
 #define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT       0
 #define I40E_GLPCI_CAPSUP_PCIE_VER_MASK        I40E_MASK(0x1, I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT)
 #define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT         2
@@ -1955,12 +1743,12 @@
 #define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK  I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT)
 #define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT    31
 #define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK     I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT)
-#define I40E_GLPCI_CNF                   0x000BE4C0
+#define I40E_GLPCI_CNF                   0x000BE4C0 /* Reset: POR */
 #define I40E_GLPCI_CNF_FLEX10_SHIFT      1
 #define I40E_GLPCI_CNF_FLEX10_MASK       I40E_MASK(0x1, I40E_GLPCI_CNF_FLEX10_SHIFT)
 #define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2
 #define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK  I40E_MASK(0x1, I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT)
-#define I40E_GLPCI_CNF2                      0x000BE494
+#define I40E_GLPCI_CNF2                      0x000BE494 /* Reset: PCIR */
 #define I40E_GLPCI_CNF2_RO_DIS_SHIFT         0
 #define I40E_GLPCI_CNF2_RO_DIS_MASK          I40E_MASK(0x1, I40E_GLPCI_CNF2_RO_DIS_SHIFT)
 #define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1
@@ -1969,10 +1757,10 @@
 #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK      I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT)
 #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT     13
 #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK      I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT)
-#define I40E_GLPCI_DREVID                     0x0009C480
+#define I40E_GLPCI_DREVID                     0x0009C480 /* Reset: PCIR */
 #define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0
 #define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK  I40E_MASK(0xFF, I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT)
-#define I40E_GLPCI_GSCL_1                        0x0009C48C
+#define I40E_GLPCI_GSCL_1                        0x0009C48C /* Reset: PCIR */
 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT   0
 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK    I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT)
 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT   1
@@ -2005,7 +1793,7 @@
 #define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK    I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT)
 #define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT  31
 #define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK   I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT)
-#define I40E_GLPCI_GSCL_2                       0x0009C490
+#define I40E_GLPCI_GSCL_2                       0x0009C490 /* Reset: PCIR */
 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0
 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK  I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT)
 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8
@@ -2014,20 +1802,20 @@
 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK  I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT)
 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24
 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK  I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT)
-#define I40E_GLPCI_GSCL_5_8(_i)                   (0x0009C494 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLPCI_GSCL_5_8(_i)                   (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
 #define I40E_GLPCI_GSCL_5_8_MAX_INDEX             3
 #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0
 #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT)
 #define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT     16
 #define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK      I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)
-#define I40E_GLPCI_GSCN_0_3(_i)                 (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLPCI_GSCN_0_3(_i)                 (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
 #define I40E_GLPCI_GSCN_0_3_MAX_INDEX           3
 #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0
 #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
-#define I40E_GLPCI_LATCT                        0x0009C4B4
+#define I40E_GLPCI_LATCT                        0x0009C4B4 /* Reset: PCIR */
 #define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0
 #define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT)
-#define I40E_GLPCI_LBARCTRL                    0x000BE484
+#define I40E_GLPCI_LBARCTRL                    0x000BE484 /* Reset: POR */
 #define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT      0
 #define I40E_GLPCI_LBARCTRL_PREFBAR_MASK       I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
 #define I40E_GLPCI_LBARCTRL_BAR32_SHIFT        1
@@ -2042,30 +1830,30 @@
 #define I40E_GLPCI_LBARCTRL_RSVD_10_MASK       I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT)
 #define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT   11
 #define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK    I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT)
-#define I40E_GLPCI_LINKCAP                          0x000BE4AC
+#define I40E_GLPCI_LINKCAP                          0x000BE4AC /* Reset: PCIR */
 #define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0
 #define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK  I40E_MASK(0x3F, I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT)
 #define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT        6
 #define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK         I40E_MASK(0x7, I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT)
 #define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT     9
 #define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK      I40E_MASK(0xF, I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT)
-#define I40E_GLPCI_PCIERR                    0x000BE4FC
+#define I40E_GLPCI_PCIERR                    0x000BE4FC /* Reset: PCIR */
 #define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0
 #define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)
-#define I40E_GLPCI_PKTCT                        0x0009C4BC
+#define I40E_GLPCI_PKTCT                        0x0009C4BC /* Reset: PCIR */
 #define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0
 #define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)
-#define I40E_GLPCI_PM_MUX_NPQ                        0x0009C4F4
+#define I40E_GLPCI_PM_MUX_NPQ                        0x0009C4F4 /* Reset: PCIR */
 #define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0
 #define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK  I40E_MASK(0x7, I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT)
 #define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT    16
 #define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK     I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT)
-#define I40E_GLPCI_PM_MUX_PFB                      0x0009C4F0
+#define I40E_GLPCI_PM_MUX_PFB                      0x0009C4F0 /* Reset: PCIR */
 #define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT   0
 #define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK    I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT)
 #define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16
 #define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK  I40E_MASK(0x7, I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT)
-#define I40E_GLPCI_PMSUP                    0x000BE4B0
+#define I40E_GLPCI_PMSUP                    0x000BE4B0 /* Reset: PCIR */
 #define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT     0
 #define I40E_GLPCI_PMSUP_ASPM_SUP_MASK      I40E_MASK(0x3, I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT)
 #define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2
@@ -2080,12 +1868,12 @@
 #define I40E_GLPCI_PMSUP_SLOT_CLK_MASK      I40E_MASK(0x1, I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT)
 #define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT     15
 #define I40E_GLPCI_PMSUP_OBFF_SUP_MASK      I40E_MASK(0x3, I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT)
-#define I40E_GLPCI_PQ_MAX_USED_SPC                                0x0009C4EC
+#define I40E_GLPCI_PQ_MAX_USED_SPC                                0x0009C4EC /* Reset: PCIR */
 #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0
 #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK  I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT)
 #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8
 #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK  I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT)
-#define I40E_GLPCI_PWRDATA                  0x000BE490
+#define I40E_GLPCI_PWRDATA                  0x000BE490 /* Reset: PCIR */
 #define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT   0
 #define I40E_GLPCI_PWRDATA_D0_POWER_MASK    I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D0_POWER_SHIFT)
 #define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8
@@ -2094,58 +1882,58 @@
 #define I40E_GLPCI_PWRDATA_D3_POWER_MASK    I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D3_POWER_SHIFT)
 #define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24
 #define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK  I40E_MASK(0x3, I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT)
-#define I40E_GLPCI_REVID                 0x000BE4B4
+#define I40E_GLPCI_REVID                 0x000BE4B4 /* Reset: PCIR */
 #define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0
 #define I40E_GLPCI_REVID_NVM_REVID_MASK  I40E_MASK(0xFF, I40E_GLPCI_REVID_NVM_REVID_SHIFT)
-#define I40E_GLPCI_SERH                 0x000BE49C
+#define I40E_GLPCI_SERH                 0x000BE49C /* Reset: PCIR */
 #define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0
 #define I40E_GLPCI_SERH_SER_NUM_H_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_SERH_SER_NUM_H_SHIFT)
-#define I40E_GLPCI_SERL                 0x000BE498
+#define I40E_GLPCI_SERL                 0x000BE498 /* Reset: PCIR */
 #define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0
 #define I40E_GLPCI_SERL_SER_NUM_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SERL_SER_NUM_L_SHIFT)
-#define I40E_GLPCI_SPARE_BITS_0                  0x0009C4F8
+#define I40E_GLPCI_SPARE_BITS_0                  0x0009C4F8 /* Reset: PCIR */
 #define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0
 #define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT)
-#define I40E_GLPCI_SPARE_BITS_1                  0x0009C4FC
+#define I40E_GLPCI_SPARE_BITS_1                  0x0009C4FC /* Reset: PCIR */
 #define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0
 #define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT)
-#define I40E_GLPCI_SUBVENID                  0x000BE48C
+#define I40E_GLPCI_SUBVENID                  0x000BE48C /* Reset: PCIR */
 #define I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT 0
 #define I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT)
-#define I40E_GLPCI_UPADD               0x000BE4F8
+#define I40E_GLPCI_UPADD               0x000BE4F8 /* Reset: PCIR */
 #define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1
 #define I40E_GLPCI_UPADD_ADDRESS_MASK  I40E_MASK(0x7FFFFFFF, I40E_GLPCI_UPADD_ADDRESS_SHIFT)
-#define I40E_GLPCI_VENDORID                0x000BE518
+#define I40E_GLPCI_VENDORID                0x000BE518 /* Reset: PCIR */
 #define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0
 #define I40E_GLPCI_VENDORID_VENDORID_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT)
-#define I40E_GLPCI_VFSUP                   0x000BE4B8
+#define I40E_GLPCI_VFSUP                   0x000BE4B8 /* Reset: PCIR */
 #define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0
 #define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK  I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
 #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1
 #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK  I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
-#define I40E_PF_FUNC_RID                       0x0009C000
+#define I40E_PF_FUNC_RID                       0x0009C000 /* Reset: PCIR */
 #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0
 #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK  I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
 #define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT   3
 #define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK    I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT)
 #define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT      8
 #define I40E_PF_FUNC_RID_BUS_NUMBER_MASK       I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT)
-#define I40E_PF_PCI_CIAA               0x0009C080
+#define I40E_PF_PCI_CIAA               0x0009C080 /* Reset: FLR */
 #define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0
 #define I40E_PF_PCI_CIAA_ADDRESS_MASK  I40E_MASK(0xFFF, I40E_PF_PCI_CIAA_ADDRESS_SHIFT)
 #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT  12
 #define I40E_PF_PCI_CIAA_VF_NUM_MASK   I40E_MASK(0x7F, I40E_PF_PCI_CIAA_VF_NUM_SHIFT)
-#define I40E_PF_PCI_CIAD            0x0009C100
+#define I40E_PF_PCI_CIAD            0x0009C100 /* Reset: FLR */
 #define I40E_PF_PCI_CIAD_DATA_SHIFT 0
 #define I40E_PF_PCI_CIAD_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_PCI_CIAD_DATA_SHIFT)
-#define I40E_PFPCI_CLASS                     0x000BE400
+#define I40E_PFPCI_CLASS                     0x000BE400 /* Reset: PCIR */
 #define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0
 #define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK  I40E_MASK(0x1, I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT)
 #define I40E_PFPCI_CLASS_RESERVED_1_SHIFT    1
 #define I40E_PFPCI_CLASS_RESERVED_1_MASK     I40E_MASK(0x1, I40E_PFPCI_CLASS_RESERVED_1_SHIFT)
 #define I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT     2
 #define I40E_PFPCI_CLASS_PF_IS_LAN_MASK      I40E_MASK(0x1, I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT)
-#define I40E_PFPCI_CNF                 0x000BE000
+#define I40E_PFPCI_CNF                 0x000BE000 /* Reset: PCIR */
 #define I40E_PFPCI_CNF_MSI_EN_SHIFT    2
 #define I40E_PFPCI_CNF_MSI_EN_MASK     I40E_MASK(0x1, I40E_PFPCI_CNF_MSI_EN_SHIFT)
 #define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3
@@ -2154,88 +1942,88 @@
 #define I40E_PFPCI_CNF_IO_BAR_MASK     I40E_MASK(0x1, I40E_PFPCI_CNF_IO_BAR_SHIFT)
 #define I40E_PFPCI_CNF_INT_PIN_SHIFT   5
 #define I40E_PFPCI_CNF_INT_PIN_MASK    I40E_MASK(0x3, I40E_PFPCI_CNF_INT_PIN_SHIFT)
-#define I40E_PFPCI_DEVID                 0x000BE080
+#define I40E_PFPCI_DEVID                 0x000BE080 /* Reset: PCIR */
 #define I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT 0
 #define I40E_PFPCI_DEVID_PF_DEV_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT)
 #define I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT 16
 #define I40E_PFPCI_DEVID_VF_DEV_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT)
-#define I40E_PFPCI_FACTPS                        0x0009C180
+#define I40E_PFPCI_FACTPS                        0x0009C180 /* Reset: FLR */
 #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0
 #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK  I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT)
 #define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT      3
 #define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK       I40E_MASK(0x1, I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT)
-#define I40E_PFPCI_FUNC                            0x000BE200
+#define I40E_PFPCI_FUNC                            0x000BE200 /* Reset: POR */
 #define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT             0
 #define I40E_PFPCI_FUNC_FUNC_DIS_MASK              I40E_MASK(0x1, I40E_PFPCI_FUNC_FUNC_DIS_SHIFT)
 #define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT       1
 #define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK        I40E_MASK(0x1, I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT)
 #define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2
 #define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK  I40E_MASK(0x1, I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT)
-#define I40E_PFPCI_FUNC2                    0x000BE180
+#define I40E_PFPCI_FUNC2                    0x000BE180 /* Reset: PCIR */
 #define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0
 #define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK  I40E_MASK(0x1, I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT)
-#define I40E_PFPCI_ICAUSE                      0x0009C200
+#define I40E_PFPCI_ICAUSE                      0x0009C200 /* Reset: PFR */
 #define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0
 #define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT)
-#define I40E_PFPCI_IENA                   0x0009C280
+#define I40E_PFPCI_IENA                   0x0009C280 /* Reset: PFR */
 #define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0
 #define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT)
-#define I40E_PFPCI_PF_FLUSH_DONE                  0x0009C800
+#define I40E_PFPCI_PF_FLUSH_DONE                  0x0009C800 /* Reset: PCIR */
 #define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
 #define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK  I40E_MASK(0x1, I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT)
-#define I40E_PFPCI_PM              0x000BE300
+#define I40E_PFPCI_PM              0x000BE300 /* Reset: POR */
 #define I40E_PFPCI_PM_PME_EN_SHIFT 0
 #define I40E_PFPCI_PM_PME_EN_MASK  I40E_MASK(0x1, I40E_PFPCI_PM_PME_EN_SHIFT)
-#define I40E_PFPCI_STATUS1                  0x000BE280
+#define I40E_PFPCI_STATUS1                  0x000BE280 /* Reset: POR */
 #define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0
 #define I40E_PFPCI_STATUS1_FUNC_VALID_MASK  I40E_MASK(0x1, I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT)
-#define I40E_PFPCI_SUBSYSID                    0x000BE100
+#define I40E_PFPCI_SUBSYSID                    0x000BE100 /* Reset: PCIR */
 #define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT 0
 #define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT)
 #define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT 16
 #define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT)
-#define I40E_PFPCI_VF_FLUSH_DONE                  0x0000E400
+#define I40E_PFPCI_VF_FLUSH_DONE                  0x0000E400 /* Reset: PCIR */
 #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
 #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK  I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)
-#define I40E_PFPCI_VF_FLUSH_DONE1(_VF)             (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_PFPCI_VF_FLUSH_DONE1(_VF)             (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: PCIR */
 #define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX        127
 #define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0
 #define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK  I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT)
-#define I40E_PFPCI_VM_FLUSH_DONE                  0x0009C880
+#define I40E_PFPCI_VM_FLUSH_DONE                  0x0009C880 /* Reset: PCIR */
 #define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
 #define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK  I40E_MASK(0x1, I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
-#define I40E_PFPCI_VMINDEX               0x0009C300
+#define I40E_PFPCI_VMINDEX               0x0009C300 /* Reset: PCIR */
 #define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0
 #define I40E_PFPCI_VMINDEX_VMINDEX_MASK  I40E_MASK(0x1FF, I40E_PFPCI_VMINDEX_VMINDEX_SHIFT)
-#define I40E_PFPCI_VMPEND               0x0009C380
+#define I40E_PFPCI_VMPEND               0x0009C380 /* Reset: PCIR */
 #define I40E_PFPCI_VMPEND_PENDING_SHIFT 0
 #define I40E_PFPCI_VMPEND_PENDING_MASK  I40E_MASK(0x1, I40E_PFPCI_VMPEND_PENDING_SHIFT)
-#define I40E_PRTPM_EEE_STAT                     0x001E4320
+#define I40E_PRTPM_EEE_STAT                     0x001E4320 /* Reset: GLOBR */
 #define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT       29
 #define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK        I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT)
 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30
 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK  I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)
 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31
 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK  I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT)
-#define I40E_PRTPM_EEEC                     0x001E4380
+#define I40E_PRTPM_EEEC                     0x001E4380 /* Reset: GLOBR */
 #define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT   16
 #define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK    I40E_MASK(0x3F, I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT)
 #define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24
 #define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK  I40E_MASK(0x3, I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT)
 #define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT      26
 #define I40E_PRTPM_EEEC_TEEE_DLY_MASK       I40E_MASK(0x3F, I40E_PRTPM_EEEC_TEEE_DLY_SHIFT)
-#define I40E_PRTPM_EEEFWD                          0x001E4400
+#define I40E_PRTPM_EEEFWD                          0x001E4400 /* Reset: GLOBR */
 #define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31
 #define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK  I40E_MASK(0x1, I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT)
-#define I40E_PRTPM_EEER                 0x001E4360
+#define I40E_PRTPM_EEER                 0x001E4360 /* Reset: GLOBR */
 #define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0
 #define I40E_PRTPM_EEER_TW_SYSTEM_MASK  I40E_MASK(0xFFFF, I40E_PRTPM_EEER_TW_SYSTEM_SHIFT)
 #define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16
 #define I40E_PRTPM_EEER_TX_LPI_EN_MASK  I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT)
-#define I40E_PRTPM_EEETXC              0x001E43E0
+#define I40E_PRTPM_EEETXC              0x001E43E0 /* Reset: GLOBR */
 #define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0
 #define I40E_PRTPM_EEETXC_TW_PHY_MASK  I40E_MASK(0xFFFF, I40E_PRTPM_EEETXC_TW_PHY_SHIFT)
-#define I40E_PRTPM_GC                     0x000B8140
+#define I40E_PRTPM_GC                     0x000B8140 /* Reset: POR */
 #define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT   0
 #define I40E_PRTPM_GC_EMP_LINK_ON_MASK    I40E_MASK(0x1, I40E_PRTPM_GC_EMP_LINK_ON_SHIFT)
 #define I40E_PRTPM_GC_MNG_VETO_SHIFT      1
@@ -2246,57 +2034,57 @@
 #define I40E_PRTPM_GC_LCDMP_MASK          I40E_MASK(0x1, I40E_PRTPM_GC_LCDMP_SHIFT)
 #define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31
 #define I40E_PRTPM_GC_LPLU_ASSERTED_MASK  I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)
-#define I40E_PRTPM_RLPIC              0x001E43A0
+#define I40E_PRTPM_RLPIC              0x001E43A0 /* Reset: GLOBR */
 #define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0
 #define I40E_PRTPM_RLPIC_ERLPIC_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT)
-#define I40E_PRTPM_TLPIC              0x001E43C0
+#define I40E_PRTPM_TLPIC              0x001E43C0 /* Reset: GLOBR */
 #define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0
 #define I40E_PRTPM_TLPIC_ETLPIC_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
-#define I40E_GLRPB_DPSS               0x000AC828
+#define I40E_GLRPB_DPSS               0x000AC828 /* Reset: CORER */
 #define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0
 #define I40E_GLRPB_DPSS_DPS_TCN_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)
-#define I40E_GLRPB_GHW           0x000AC830
+#define I40E_GLRPB_GHW           0x000AC830 /* Reset: CORER */
 #define I40E_GLRPB_GHW_GHW_SHIFT 0
 #define I40E_GLRPB_GHW_GHW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT)
-#define I40E_GLRPB_GLW           0x000AC834
+#define I40E_GLRPB_GLW           0x000AC834 /* Reset: CORER */
 #define I40E_GLRPB_GLW_GLW_SHIFT 0
 #define I40E_GLRPB_GLW_GLW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_GLW_GLW_SHIFT)
-#define I40E_GLRPB_PHW           0x000AC844
+#define I40E_GLRPB_PHW           0x000AC844 /* Reset: CORER */
 #define I40E_GLRPB_PHW_PHW_SHIFT 0
 #define I40E_GLRPB_PHW_PHW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_PHW_PHW_SHIFT)
-#define I40E_GLRPB_PLW           0x000AC848
+#define I40E_GLRPB_PLW           0x000AC848 /* Reset: CORER */
 #define I40E_GLRPB_PLW_PLW_SHIFT 0
 #define I40E_GLRPB_PLW_PLW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_PLW_PLW_SHIFT)
-#define I40E_PRTRPB_DHW(_i)           (0x000AC100 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTRPB_DHW(_i)           (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTRPB_DHW_MAX_INDEX     7
 #define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0
 #define I40E_PRTRPB_DHW_DHW_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT)
-#define I40E_PRTRPB_DLW(_i)           (0x000AC220 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTRPB_DLW(_i)           (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTRPB_DLW_MAX_INDEX     7
 #define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0
 #define I40E_PRTRPB_DLW_DLW_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT)
-#define I40E_PRTRPB_DPS(_i)           (0x000AC320 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTRPB_DPS(_i)           (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTRPB_DPS_MAX_INDEX     7
 #define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0
 #define I40E_PRTRPB_DPS_DPS_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT)
-#define I40E_PRTRPB_SHT(_i)           (0x000AC480 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTRPB_SHT(_i)           (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTRPB_SHT_MAX_INDEX     7
 #define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0
 #define I40E_PRTRPB_SHT_SHT_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT)
-#define I40E_PRTRPB_SHW           0x000AC580
+#define I40E_PRTRPB_SHW           0x000AC580 /* Reset: CORER */
 #define I40E_PRTRPB_SHW_SHW_SHIFT 0
 #define I40E_PRTRPB_SHW_SHW_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT)
-#define I40E_PRTRPB_SLT(_i)           (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTRPB_SLT(_i)           (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTRPB_SLT_MAX_INDEX     7
 #define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0
 #define I40E_PRTRPB_SLT_SLT_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT)
-#define I40E_PRTRPB_SLW           0x000AC6A0
+#define I40E_PRTRPB_SLW           0x000AC6A0 /* Reset: CORER */
 #define I40E_PRTRPB_SLW_SLW_SHIFT 0
 #define I40E_PRTRPB_SLW_SLW_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT)
-#define I40E_PRTRPB_SPS           0x000AC7C0
+#define I40E_PRTRPB_SPS           0x000AC7C0 /* Reset: CORER */
 #define I40E_PRTRPB_SPS_SPS_SHIFT 0
 #define I40E_PRTRPB_SPS_SPS_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT)
-#define I40E_GLQF_CTL                      0x00269BA4
+#define I40E_GLQF_CTL                      0x00269BA4 /* Reset: CORER */
 #define I40E_GLQF_CTL_HTOEP_SHIFT          1
 #define I40E_GLQF_CTL_HTOEP_MASK           I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_SHIFT)
 #define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT     2
@@ -2321,12 +2109,12 @@
 #define I40E_GLQF_CTL_INVALPRIO_MASK       I40E_MASK(0x1, I40E_GLQF_CTL_INVALPRIO_SHIFT)
 #define I40E_GLQF_CTL_IGNORE_IP_SHIFT      27
 #define I40E_GLQF_CTL_IGNORE_IP_MASK       I40E_MASK(0x1, I40E_GLQF_CTL_IGNORE_IP_SHIFT)
-#define I40E_GLQF_FDCNT_0                   0x00269BAC
+#define I40E_GLQF_FDCNT_0                   0x00269BAC /* Reset: CORER */
 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0
 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK  I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT)
 #define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT     13
 #define I40E_GLQF_FDCNT_0_BESTCNT_MASK      I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT)
-#define I40E_GLQF_HKEY(_i)         (0x00270140 + ((_i) * 4)) /* _i=0...12 */
+#define I40E_GLQF_HKEY(_i)         (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
 #define I40E_GLQF_HKEY_MAX_INDEX   12
 #define I40E_GLQF_HKEY_KEY_0_SHIFT 0
 #define I40E_GLQF_HKEY_KEY_0_MASK  I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_0_SHIFT)
@@ -2336,15 +2124,15 @@
 #define I40E_GLQF_HKEY_KEY_2_MASK  I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_2_SHIFT)
 #define I40E_GLQF_HKEY_KEY_3_SHIFT 24
 #define I40E_GLQF_HKEY_KEY_3_MASK  I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_3_SHIFT)
-#define I40E_GLQF_HSYM(_i)            (0x00269D00 + ((_i) * 4)) /* _i=0...63 */
+#define I40E_GLQF_HSYM(_i)            (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
 #define I40E_GLQF_HSYM_MAX_INDEX      63
 #define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0
 #define I40E_GLQF_HSYM_SYMH_ENA_MASK  I40E_MASK(0x1, I40E_GLQF_HSYM_SYMH_ENA_SHIFT)
-#define I40E_GLQF_PCNT(_i)        (0x00266800 + ((_i) * 4)) /* _i=0...511 */
+#define I40E_GLQF_PCNT(_i)        (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */
 #define I40E_GLQF_PCNT_MAX_INDEX  511
 #define I40E_GLQF_PCNT_PCNT_SHIFT 0
 #define I40E_GLQF_PCNT_PCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_PCNT_PCNT_SHIFT)
-#define I40E_GLQF_SWAP(_i, _j)          (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */
+#define I40E_GLQF_SWAP(_i, _j)          (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
 #define I40E_GLQF_SWAP_MAX_INDEX       1
 #define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0
 #define I40E_GLQF_SWAP_OFF0_SRC0_MASK  I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC0_SHIFT)
@@ -2358,7 +2146,7 @@
 #define I40E_GLQF_SWAP_OFF1_SRC1_MASK  I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC1_SHIFT)
 #define I40E_GLQF_SWAP_FLEN1_SHIFT     28
 #define I40E_GLQF_SWAP_FLEN1_MASK      I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN1_SHIFT)
-#define I40E_PFQF_CTL_0                   0x001C0AC0
+#define I40E_PFQF_CTL_0                   0x001C0AC0 /* Reset: CORER */
 #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT     0
 #define I40E_PFQF_CTL_0_PEHSIZE_MASK      I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT)
 #define I40E_PFQF_CTL_0_PEDSIZE_SHIFT     5
@@ -2379,24 +2167,24 @@
 #define I40E_PFQF_CTL_0_VFFCHSIZE_MASK    I40E_MASK(0xF, I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT)
 #define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT   24
 #define I40E_PFQF_CTL_0_VFFCDSIZE_MASK    I40E_MASK(0x3, I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT)
-#define I40E_PFQF_CTL_1                    0x00245D80
+#define I40E_PFQF_CTL_1                    0x00245D80 /* Reset: CORER */
 #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0
 #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK  I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT)
-#define I40E_PFQF_FDALLOC               0x00246280
+#define I40E_PFQF_FDALLOC               0x00246280 /* Reset: CORER */
 #define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0
 #define I40E_PFQF_FDALLOC_FDALLOC_MASK  I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDALLOC_SHIFT)
 #define I40E_PFQF_FDALLOC_FDBEST_SHIFT  8
 #define I40E_PFQF_FDALLOC_FDBEST_MASK   I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDBEST_SHIFT)
-#define I40E_PFQF_FDSTAT                   0x00246380
+#define I40E_PFQF_FDSTAT                   0x00246380 /* Reset: CORER */
 #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0
 #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK  I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT)
 #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT    16
 #define I40E_PFQF_FDSTAT_BEST_CNT_MASK     I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT)
-#define I40E_PFQF_HENA(_i)             (0x00245900 + ((_i) * 128)) /* _i=0...1 */
+#define I40E_PFQF_HENA(_i)             (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_PFQF_HENA_MAX_INDEX       1
 #define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0
 #define I40E_PFQF_HENA_PTYPE_ENA_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFQF_HENA_PTYPE_ENA_SHIFT)
-#define I40E_PFQF_HKEY(_i)         (0x00244800 + ((_i) * 128)) /* _i=0...12 */
+#define I40E_PFQF_HKEY(_i)         (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */
 #define I40E_PFQF_HKEY_MAX_INDEX   12
 #define I40E_PFQF_HKEY_KEY_0_SHIFT 0
 #define I40E_PFQF_HKEY_KEY_0_MASK  I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_0_SHIFT)
@@ -2406,7 +2194,7 @@
 #define I40E_PFQF_HKEY_KEY_2_MASK  I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_2_SHIFT)
 #define I40E_PFQF_HKEY_KEY_3_SHIFT 24
 #define I40E_PFQF_HKEY_KEY_3_MASK  I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_3_SHIFT)
-#define I40E_PFQF_HLUT(_i)        (0x00240000 + ((_i) * 128)) /* _i=0...127 */
+#define I40E_PFQF_HLUT(_i)        (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_PFQF_HLUT_MAX_INDEX  127
 #define I40E_PFQF_HLUT_LUT0_SHIFT 0
 #define I40E_PFQF_HLUT_LUT0_MASK  I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT0_SHIFT)
@@ -2416,54 +2204,20 @@
 #define I40E_PFQF_HLUT_LUT2_MASK  I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT2_SHIFT)
 #define I40E_PFQF_HLUT_LUT3_SHIFT 24
 #define I40E_PFQF_HLUT_LUT3_MASK  I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT)
-#define I40E_PFQF_HREGION(_i)                  (0x00245400 + ((_i) * 128)) /* _i=0...7 */
-#define I40E_PFQF_HREGION_MAX_INDEX            7
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
-#define I40E_PFQF_HREGION_REGION_0_SHIFT       1
-#define I40E_PFQF_HREGION_REGION_0_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_0_SHIFT)
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
-#define I40E_PFQF_HREGION_REGION_1_SHIFT       5
-#define I40E_PFQF_HREGION_REGION_1_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_1_SHIFT)
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
-#define I40E_PFQF_HREGION_REGION_2_SHIFT       9
-#define I40E_PFQF_HREGION_REGION_2_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_2_SHIFT)
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
-#define I40E_PFQF_HREGION_REGION_3_SHIFT       13
-#define I40E_PFQF_HREGION_REGION_3_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_3_SHIFT)
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
-#define I40E_PFQF_HREGION_REGION_4_SHIFT       17
-#define I40E_PFQF_HREGION_REGION_4_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_4_SHIFT)
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
-#define I40E_PFQF_HREGION_REGION_5_SHIFT       21
-#define I40E_PFQF_HREGION_REGION_5_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_5_SHIFT)
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
-#define I40E_PFQF_HREGION_REGION_6_SHIFT       25
-#define I40E_PFQF_HREGION_REGION_6_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_6_SHIFT)
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
-#define I40E_PFQF_HREGION_REGION_7_SHIFT       29
-#define I40E_PFQF_HREGION_REGION_7_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_7_SHIFT)
-#define I40E_PRTQF_CTL_0                0x00256E60
+#define I40E_PRTQF_CTL_0                0x00256E60 /* Reset: CORER */
 #define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0
 #define I40E_PRTQF_CTL_0_HSYM_ENA_MASK  I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT)
-#define I40E_PRTQF_FD_FLXINSET(_i)         (0x00253800 + ((_i) * 32)) /* _i=0...63 */
+#define I40E_PRTQF_FD_FLXINSET(_i)         (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */
 #define I40E_PRTQF_FD_FLXINSET_MAX_INDEX   63
 #define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0
 #define I40E_PRTQF_FD_FLXINSET_INSET_MASK  I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)
-#define I40E_PRTQF_FD_MSK(_i, _j)       (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */
+#define I40E_PRTQF_FD_MSK(_i, _j)       (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
 #define I40E_PRTQF_FD_MSK_MAX_INDEX    63
 #define I40E_PRTQF_FD_MSK_MASK_SHIFT   0
 #define I40E_PRTQF_FD_MSK_MASK_MASK    I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT)
 #define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16
 #define I40E_PRTQF_FD_MSK_OFFSET_MASK  I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT)
-#define I40E_PRTQF_FLX_PIT(_i)              (0x00255200 + ((_i) * 32)) /* _i=0...8 */
+#define I40E_PRTQF_FLX_PIT(_i)              (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */
 #define I40E_PRTQF_FLX_PIT_MAX_INDEX        8
 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0
 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK  I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
@@ -2471,11 +2225,11 @@
 #define I40E_PRTQF_FLX_PIT_FSIZE_MASK       I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
 #define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT   10
 #define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK    I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
-#define I40E_VFQF_HENA1(_i, _VF)         (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */
+#define I40E_VFQF_HENA1(_i, _VF)         (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */
 #define I40E_VFQF_HENA1_MAX_INDEX       1
 #define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0
 #define I40E_VFQF_HENA1_PTYPE_ENA_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA1_PTYPE_ENA_SHIFT)
-#define I40E_VFQF_HKEY1(_i, _VF)     (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */
+#define I40E_VFQF_HKEY1(_i, _VF)     (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */
 #define I40E_VFQF_HKEY1_MAX_INDEX   12
 #define I40E_VFQF_HKEY1_KEY_0_SHIFT 0
 #define I40E_VFQF_HKEY1_KEY_0_MASK  I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_0_SHIFT)
@@ -2485,7 +2239,7 @@
 #define I40E_VFQF_HKEY1_KEY_2_MASK  I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_2_SHIFT)
 #define I40E_VFQF_HKEY1_KEY_3_SHIFT 24
 #define I40E_VFQF_HKEY1_KEY_3_MASK  I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_3_SHIFT)
-#define I40E_VFQF_HLUT1(_i, _VF)    (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */
+#define I40E_VFQF_HLUT1(_i, _VF)    (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */
 #define I40E_VFQF_HLUT1_MAX_INDEX  15
 #define I40E_VFQF_HLUT1_LUT0_SHIFT 0
 #define I40E_VFQF_HLUT1_LUT0_MASK  I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT0_SHIFT)
@@ -2495,7 +2249,7 @@
 #define I40E_VFQF_HLUT1_LUT2_MASK  I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT2_SHIFT)
 #define I40E_VFQF_HLUT1_LUT3_SHIFT 24
 #define I40E_VFQF_HLUT1_LUT3_MASK  I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT3_SHIFT)
-#define I40E_VFQF_HREGION1(_i, _VF)              (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...7, _VF=0...127 */
+#define I40E_VFQF_HREGION1(_i, _VF)              (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...7, _VF=0...127 */ /* Reset: CORER */
 #define I40E_VFQF_HREGION1_MAX_INDEX            7
 #define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0
 #define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK  I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT)
@@ -2529,7 +2283,7 @@
 #define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK  I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT)
 #define I40E_VFQF_HREGION1_REGION_7_SHIFT       29
 #define I40E_VFQF_HREGION1_REGION_7_MASK        I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_7_SHIFT)
-#define I40E_VPQF_CTL(_VF)          (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPQF_CTL(_VF)          (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VPQF_CTL_MAX_INDEX     127
 #define I40E_VPQF_CTL_PEHSIZE_SHIFT 0
 #define I40E_VPQF_CTL_PEHSIZE_MASK  I40E_MASK(0x1F, I40E_VPQF_CTL_PEHSIZE_SHIFT)
@@ -2539,7 +2293,7 @@
 #define I40E_VPQF_CTL_FCHSIZE_MASK  I40E_MASK(0xF, I40E_VPQF_CTL_FCHSIZE_SHIFT)
 #define I40E_VPQF_CTL_FCDSIZE_SHIFT 14
 #define I40E_VPQF_CTL_FCDSIZE_MASK  I40E_MASK(0x3, I40E_VPQF_CTL_FCDSIZE_SHIFT)
-#define I40E_VSIQF_CTL(_VSI)             (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSIQF_CTL(_VSI)             (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSIQF_CTL_MAX_INDEX         383
 #define I40E_VSIQF_CTL_FCOE_ENA_SHIFT    0
 #define I40E_VSIQF_CTL_FCOE_ENA_MASK     I40E_MASK(0x1, I40E_VSIQF_CTL_FCOE_ENA_SHIFT)
@@ -2553,7 +2307,7 @@
 #define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK  I40E_MASK(0x1, I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT)
 #define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5
 #define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK  I40E_MASK(0x1, I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT)
-#define I40E_VSIQF_TCREGION(_i, _VSI)         (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...3, _VSI=0...383 */
+#define I40E_VSIQF_TCREGION(_i, _VSI)         (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...3, _VSI=0...383 */ /* Reset: PFR */
 #define I40E_VSIQF_TCREGION_MAX_INDEX        3
 #define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT  0
 #define I40E_VSIQF_TCREGION_TC_OFFSET_MASK   I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT)
@@ -2563,575 +2317,575 @@
 #define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK  I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT)
 #define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT   25
 #define I40E_VSIQF_TCREGION_TC_SIZE2_MASK    I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT)
-#define I40E_GL_FCOECRC(_i)           (0x00314d80 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOECRC(_i)           (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOECRC_MAX_INDEX     143
 #define I40E_GL_FCOECRC_FCOECRC_SHIFT 0
 #define I40E_GL_FCOECRC_FCOECRC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOECRC_FCOECRC_SHIFT)
-#define I40E_GL_FCOEDDPC(_i)            (0x00314480 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEDDPC(_i)            (0x00314480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEDDPC_MAX_INDEX      143
 #define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0
 #define I40E_GL_FCOEDDPC_FCOEDDPC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT)
-#define I40E_GL_FCOEDIFEC(_i)             (0x00318480 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEDIFEC(_i)             (0x00318480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEDIFEC_MAX_INDEX       143
 #define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0
 #define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT)
-#define I40E_GL_FCOEDIFTCL(_i)             (0x00354000 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEDIFTCL(_i)             (0x00354000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEDIFTCL_MAX_INDEX       143
 #define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0
 #define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT)
-#define I40E_GL_FCOEDIXEC(_i)             (0x0034c000 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEDIXEC(_i)             (0x0034c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEDIXEC_MAX_INDEX       143
 #define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0
 #define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT)
-#define I40E_GL_FCOEDIXVC(_i)             (0x00350000 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEDIXVC(_i)             (0x00350000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEDIXVC_MAX_INDEX       143
 #define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0
 #define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT)
-#define I40E_GL_FCOEDWRCH(_i)             (0x00320004 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEDWRCH(_i)             (0x00320004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEDWRCH_MAX_INDEX       143
 #define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0
 #define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK  I40E_MASK(0xFFFF, I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT)
-#define I40E_GL_FCOEDWRCL(_i)             (0x00320000 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEDWRCL(_i)             (0x00320000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEDWRCL_MAX_INDEX       143
 #define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0
 #define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT)
-#define I40E_GL_FCOEDWTCH(_i)             (0x00348084 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEDWTCH(_i)             (0x00348084 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEDWTCH_MAX_INDEX       143
 #define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0
 #define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK  I40E_MASK(0xFFFF, I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT)
-#define I40E_GL_FCOEDWTCL(_i)             (0x00348080 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEDWTCL(_i)             (0x00348080 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEDWTCL_MAX_INDEX       143
 #define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0
 #define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT)
-#define I40E_GL_FCOELAST(_i)            (0x00314000 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOELAST(_i)            (0x00314000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOELAST_MAX_INDEX      143
 #define I40E_GL_FCOELAST_FCOELAST_SHIFT 0
 #define I40E_GL_FCOELAST_FCOELAST_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOELAST_FCOELAST_SHIFT)
-#define I40E_GL_FCOEPRC(_i)           (0x00315200 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEPRC(_i)           (0x00315200 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEPRC_MAX_INDEX     143
 #define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0
 #define I40E_GL_FCOEPRC_FCOEPRC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPRC_FCOEPRC_SHIFT)
-#define I40E_GL_FCOEPTC(_i)           (0x00344C00 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOEPTC(_i)           (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOEPTC_MAX_INDEX     143
 #define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0
 #define I40E_GL_FCOEPTC_FCOEPTC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPTC_FCOEPTC_SHIFT)
-#define I40E_GL_FCOERPDC(_i)            (0x00324000 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_FCOERPDC(_i)            (0x00324000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_FCOERPDC_MAX_INDEX      143
 #define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0
 #define I40E_GL_FCOERPDC_FCOERPDC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FCOERPDC_FCOERPDC_SHIFT)
-#define I40E_GL_RXERR1_L(_i)             (0x00318000 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_RXERR1_L(_i)             (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_RXERR1_L_MAX_INDEX       143
 #define I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT 0
 #define I40E_GL_RXERR1_L_FCOEDIFRC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT)
-#define I40E_GL_RXERR2_L(_i)             (0x0031c000 + ((_i) * 8)) /* _i=0...143 */
+#define I40E_GL_RXERR2_L(_i)             (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
 #define I40E_GL_RXERR2_L_MAX_INDEX       143
 #define I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT 0
 #define I40E_GL_RXERR2_L_FCOEDIXAC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)
-#define I40E_GLPRT_BPRCH(_i)         (0x003005E4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_BPRCH(_i)         (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_BPRCH_MAX_INDEX   3
 #define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0
 #define I40E_GLPRT_BPRCH_UPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_UPRCH_SHIFT)
-#define I40E_GLPRT_BPRCL(_i)         (0x003005E0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_BPRCL(_i)         (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_BPRCL_MAX_INDEX   3
 #define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0
 #define I40E_GLPRT_BPRCL_UPRCH_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_UPRCH_SHIFT)
-#define I40E_GLPRT_BPTCH(_i)         (0x00300A04 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_BPTCH(_i)         (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_BPTCH_MAX_INDEX   3
 #define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0
 #define I40E_GLPRT_BPTCH_UPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_UPRCH_SHIFT)
-#define I40E_GLPRT_BPTCL(_i)         (0x00300A00 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_BPTCL(_i)         (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_BPTCL_MAX_INDEX   3
 #define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0
 #define I40E_GLPRT_BPTCL_UPRCH_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_UPRCH_SHIFT)
-#define I40E_GLPRT_CRCERRS(_i)           (0x00300080 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_CRCERRS(_i)           (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_CRCERRS_MAX_INDEX     3
 #define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0
 #define I40E_GLPRT_CRCERRS_CRCERRS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT)
-#define I40E_GLPRT_GORCH(_i)         (0x00300004 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_GORCH(_i)         (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_GORCH_MAX_INDEX   3
 #define I40E_GLPRT_GORCH_GORCH_SHIFT 0
 #define I40E_GLPRT_GORCH_GORCH_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT)
-#define I40E_GLPRT_GORCL(_i)         (0x00300000 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_GORCL(_i)         (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_GORCL_MAX_INDEX   3
 #define I40E_GLPRT_GORCL_GORCL_SHIFT 0
 #define I40E_GLPRT_GORCL_GORCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GORCL_GORCL_SHIFT)
-#define I40E_GLPRT_GOTCH(_i)         (0x00300684 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_GOTCH(_i)         (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_GOTCH_MAX_INDEX   3
 #define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0
 #define I40E_GLPRT_GOTCH_GOTCH_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_GOTCH_GOTCH_SHIFT)
-#define I40E_GLPRT_GOTCL(_i)         (0x00300680 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_GOTCL(_i)         (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_GOTCL_MAX_INDEX   3
 #define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0
 #define I40E_GLPRT_GOTCL_GOTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GOTCL_GOTCL_SHIFT)
-#define I40E_GLPRT_ILLERRC(_i)           (0x003000E0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_ILLERRC(_i)           (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_ILLERRC_MAX_INDEX     3
 #define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0
 #define I40E_GLPRT_ILLERRC_ILLERRC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ILLERRC_ILLERRC_SHIFT)
-#define I40E_GLPRT_LDPC(_i)        (0x00300620 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_LDPC(_i)        (0x00300620 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_LDPC_MAX_INDEX  3
 #define I40E_GLPRT_LDPC_LDPC_SHIFT 0
 #define I40E_GLPRT_LDPC_LDPC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LDPC_LDPC_SHIFT)
-#define I40E_GLPRT_LXOFFRXC(_i)              (0x00300160 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_LXOFFRXC(_i)              (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_LXOFFRXC_MAX_INDEX        3
 #define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0
 #define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT)
-#define I40E_GLPRT_LXOFFTXC(_i)            (0x003009A0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_LXOFFTXC(_i)            (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_LXOFFTXC_MAX_INDEX      3
 #define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0
 #define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT)
-#define I40E_GLPRT_LXONRXC(_i)             (0x00300140 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_LXONRXC(_i)             (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_LXONRXC_MAX_INDEX       3
 #define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0
 #define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT)
-#define I40E_GLPRT_LXONTXC(_i)           (0x00300980 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_LXONTXC(_i)           (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_LXONTXC_MAX_INDEX     3
 #define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0
 #define I40E_GLPRT_LXONTXC_LXONTXC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONTXC_LXONTXC_SHIFT)
-#define I40E_GLPRT_MLFC(_i)        (0x00300020 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_MLFC(_i)        (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_MLFC_MAX_INDEX  3
 #define I40E_GLPRT_MLFC_MLFC_SHIFT 0
 #define I40E_GLPRT_MLFC_MLFC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MLFC_MLFC_SHIFT)
-#define I40E_GLPRT_MPRCH(_i)         (0x003005C4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_MPRCH(_i)         (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_MPRCH_MAX_INDEX   3
 #define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0
 #define I40E_GLPRT_MPRCH_MPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_MPRCH_MPRCH_SHIFT)
-#define I40E_GLPRT_MPRCL(_i)         (0x003005C0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_MPRCL(_i)         (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_MPRCL_MAX_INDEX   3
 #define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0
 #define I40E_GLPRT_MPRCL_MPRCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPRCL_MPRCL_SHIFT)
-#define I40E_GLPRT_MPTCH(_i)         (0x003009E4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_MPTCH(_i)         (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_MPTCH_MAX_INDEX   3
 #define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0
 #define I40E_GLPRT_MPTCH_MPTCH_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_MPTCH_MPTCH_SHIFT)
-#define I40E_GLPRT_MPTCL(_i)         (0x003009E0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_MPTCL(_i)         (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_MPTCL_MAX_INDEX   3
 #define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0
 #define I40E_GLPRT_MPTCL_MPTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPTCL_MPTCL_SHIFT)
-#define I40E_GLPRT_MRFC(_i)        (0x00300040 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_MRFC(_i)        (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_MRFC_MAX_INDEX  3
 #define I40E_GLPRT_MRFC_MRFC_SHIFT 0
 #define I40E_GLPRT_MRFC_MRFC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MRFC_MRFC_SHIFT)
-#define I40E_GLPRT_PRC1023H(_i)            (0x00300504 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC1023H(_i)            (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC1023H_MAX_INDEX      3
 #define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0
 #define I40E_GLPRT_PRC1023H_PRC1023H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PRC1023H_PRC1023H_SHIFT)
-#define I40E_GLPRT_PRC1023L(_i)            (0x00300500 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC1023L(_i)            (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC1023L_MAX_INDEX      3
 #define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0
 #define I40E_GLPRT_PRC1023L_PRC1023L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1023L_PRC1023L_SHIFT)
-#define I40E_GLPRT_PRC127H(_i)           (0x003004A4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC127H(_i)           (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC127H_MAX_INDEX     3
 #define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0
 #define I40E_GLPRT_PRC127H_PRC127H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PRC127H_PRC127H_SHIFT)
-#define I40E_GLPRT_PRC127L(_i)           (0x003004A0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC127L(_i)           (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC127L_MAX_INDEX     3
 #define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0
 #define I40E_GLPRT_PRC127L_PRC127L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC127L_PRC127L_SHIFT)
-#define I40E_GLPRT_PRC1522H(_i)            (0x00300524 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC1522H(_i)            (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC1522H_MAX_INDEX      3
 #define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0
 #define I40E_GLPRT_PRC1522H_PRC1522H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PRC1522H_PRC1522H_SHIFT)
-#define I40E_GLPRT_PRC1522L(_i)            (0x00300520 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC1522L(_i)            (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC1522L_MAX_INDEX      3
 #define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0
 #define I40E_GLPRT_PRC1522L_PRC1522L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1522L_PRC1522L_SHIFT)
-#define I40E_GLPRT_PRC255H(_i)              (0x003004C4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC255H(_i)              (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC255H_MAX_INDEX        3
 #define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0
 #define I40E_GLPRT_PRC255H_PRTPRC255H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT)
-#define I40E_GLPRT_PRC255L(_i)           (0x003004C0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC255L(_i)           (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC255L_MAX_INDEX     3
 #define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0
 #define I40E_GLPRT_PRC255L_PRC255L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC255L_PRC255L_SHIFT)
-#define I40E_GLPRT_PRC511H(_i)           (0x003004E4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC511H(_i)           (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC511H_MAX_INDEX     3
 #define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0
 #define I40E_GLPRT_PRC511H_PRC511H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PRC511H_PRC511H_SHIFT)
-#define I40E_GLPRT_PRC511L(_i)           (0x003004E0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC511L(_i)           (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC511L_MAX_INDEX     3
 #define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0
 #define I40E_GLPRT_PRC511L_PRC511L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC511L_PRC511L_SHIFT)
-#define I40E_GLPRT_PRC64H(_i)          (0x00300484 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC64H(_i)          (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC64H_MAX_INDEX    3
 #define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0
 #define I40E_GLPRT_PRC64H_PRC64H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PRC64H_PRC64H_SHIFT)
-#define I40E_GLPRT_PRC64L(_i)          (0x00300480 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC64L(_i)          (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC64L_MAX_INDEX    3
 #define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0
 #define I40E_GLPRT_PRC64L_PRC64L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC64L_PRC64L_SHIFT)
-#define I40E_GLPRT_PRC9522H(_i)            (0x00300544 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC9522H(_i)            (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC9522H_MAX_INDEX      3
 #define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0
 #define I40E_GLPRT_PRC9522H_PRC1522H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PRC9522H_PRC1522H_SHIFT)
-#define I40E_GLPRT_PRC9522L(_i)            (0x00300540 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PRC9522L(_i)            (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PRC9522L_MAX_INDEX      3
 #define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0
 #define I40E_GLPRT_PRC9522L_PRC1522L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC9522L_PRC1522L_SHIFT)
-#define I40E_GLPRT_PTC1023H(_i)            (0x00300724 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC1023H(_i)            (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC1023H_MAX_INDEX      3
 #define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0
 #define I40E_GLPRT_PTC1023H_PTC1023H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PTC1023H_PTC1023H_SHIFT)
-#define I40E_GLPRT_PTC1023L(_i)            (0x00300720 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC1023L(_i)            (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC1023L_MAX_INDEX      3
 #define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0
 #define I40E_GLPRT_PTC1023L_PTC1023L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1023L_PTC1023L_SHIFT)
-#define I40E_GLPRT_PTC127H(_i)           (0x003006C4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC127H(_i)           (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC127H_MAX_INDEX     3
 #define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0
 #define I40E_GLPRT_PTC127H_PTC127H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PTC127H_PTC127H_SHIFT)
-#define I40E_GLPRT_PTC127L(_i)           (0x003006C0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC127L(_i)           (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC127L_MAX_INDEX     3
 #define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0
 #define I40E_GLPRT_PTC127L_PTC127L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC127L_PTC127L_SHIFT)
-#define I40E_GLPRT_PTC1522H(_i)            (0x00300744 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC1522H(_i)            (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC1522H_MAX_INDEX      3
 #define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0
 #define I40E_GLPRT_PTC1522H_PTC1522H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PTC1522H_PTC1522H_SHIFT)
-#define I40E_GLPRT_PTC1522L(_i)            (0x00300740 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC1522L(_i)            (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC1522L_MAX_INDEX      3
 #define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0
 #define I40E_GLPRT_PTC1522L_PTC1522L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1522L_PTC1522L_SHIFT)
-#define I40E_GLPRT_PTC255H(_i)           (0x003006E4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC255H(_i)           (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC255H_MAX_INDEX     3
 #define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0
 #define I40E_GLPRT_PTC255H_PTC255H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PTC255H_PTC255H_SHIFT)
-#define I40E_GLPRT_PTC255L(_i)           (0x003006E0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC255L(_i)           (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC255L_MAX_INDEX     3
 #define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0
 #define I40E_GLPRT_PTC255L_PTC255L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC255L_PTC255L_SHIFT)
-#define I40E_GLPRT_PTC511H(_i)           (0x00300704 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC511H(_i)           (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC511H_MAX_INDEX     3
 #define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0
 #define I40E_GLPRT_PTC511H_PTC511H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PTC511H_PTC511H_SHIFT)
-#define I40E_GLPRT_PTC511L(_i)           (0x00300700 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC511L(_i)           (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC511L_MAX_INDEX     3
 #define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0
 #define I40E_GLPRT_PTC511L_PTC511L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC511L_PTC511L_SHIFT)
-#define I40E_GLPRT_PTC64H(_i)          (0x003006A4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC64H(_i)          (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC64H_MAX_INDEX    3
 #define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0
 #define I40E_GLPRT_PTC64H_PTC64H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PTC64H_PTC64H_SHIFT)
-#define I40E_GLPRT_PTC64L(_i)          (0x003006A0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC64L(_i)          (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC64L_MAX_INDEX    3
 #define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0
 #define I40E_GLPRT_PTC64L_PTC64L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC64L_PTC64L_SHIFT)
-#define I40E_GLPRT_PTC9522H(_i)            (0x00300764 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC9522H(_i)            (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC9522H_MAX_INDEX      3
 #define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0
 #define I40E_GLPRT_PTC9522H_PTC9522H_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_PTC9522H_PTC9522H_SHIFT)
-#define I40E_GLPRT_PTC9522L(_i)            (0x00300760 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_PTC9522L(_i)            (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_PTC9522L_MAX_INDEX      3
 #define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0
 #define I40E_GLPRT_PTC9522L_PTC9522L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC9522L_PTC9522L_SHIFT)
-#define I40E_GLPRT_PXOFFRXC(_i, _j)             (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */
+#define I40E_GLPRT_PXOFFRXC(_i, _j)             (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
 #define I40E_GLPRT_PXOFFRXC_MAX_INDEX          3
 #define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0
 #define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT)
-#define I40E_GLPRT_PXOFFTXC(_i, _j)             (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */
+#define I40E_GLPRT_PXOFFTXC(_i, _j)             (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
 #define I40E_GLPRT_PXOFFTXC_MAX_INDEX          3
 #define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0
 #define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT)
-#define I40E_GLPRT_PXONRXC(_i, _j)            (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */
+#define I40E_GLPRT_PXONRXC(_i, _j)            (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
 #define I40E_GLPRT_PXONRXC_MAX_INDEX         3
 #define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0
 #define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT)
-#define I40E_GLPRT_PXONTXC(_i, _j)          (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */
+#define I40E_GLPRT_PXONTXC(_i, _j)          (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
 #define I40E_GLPRT_PXONTXC_MAX_INDEX       3
 #define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0
 #define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT)
-#define I40E_GLPRT_RDPC(_i)        (0x00300600 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_RDPC(_i)        (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_RDPC_MAX_INDEX  3
 #define I40E_GLPRT_RDPC_RDPC_SHIFT 0
 #define I40E_GLPRT_RDPC_RDPC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RDPC_RDPC_SHIFT)
-#define I40E_GLPRT_RFC(_i)       (0x00300560 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_RFC(_i)       (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_RFC_MAX_INDEX 3
 #define I40E_GLPRT_RFC_RFC_SHIFT 0
 #define I40E_GLPRT_RFC_RFC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RFC_RFC_SHIFT)
-#define I40E_GLPRT_RJC(_i)       (0x00300580 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_RJC(_i)       (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_RJC_MAX_INDEX 3
 #define I40E_GLPRT_RJC_RJC_SHIFT 0
 #define I40E_GLPRT_RJC_RJC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RJC_RJC_SHIFT)
-#define I40E_GLPRT_RLEC(_i)        (0x003000A0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_RLEC(_i)        (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_RLEC_MAX_INDEX  3
 #define I40E_GLPRT_RLEC_RLEC_SHIFT 0
 #define I40E_GLPRT_RLEC_RLEC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RLEC_RLEC_SHIFT)
-#define I40E_GLPRT_ROC(_i)       (0x00300120 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_ROC(_i)       (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_ROC_MAX_INDEX 3
 #define I40E_GLPRT_ROC_ROC_SHIFT 0
 #define I40E_GLPRT_ROC_ROC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ROC_ROC_SHIFT)
-#define I40E_GLPRT_RUC(_i)       (0x00300100 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_RUC(_i)       (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_RUC_MAX_INDEX 3
 #define I40E_GLPRT_RUC_RUC_SHIFT 0
 #define I40E_GLPRT_RUC_RUC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUC_RUC_SHIFT)
-#define I40E_GLPRT_RUPP(_i)        (0x00300660 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_RUPP(_i)        (0x00300660 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_RUPP_MAX_INDEX  3
 #define I40E_GLPRT_RUPP_RUPP_SHIFT 0
 #define I40E_GLPRT_RUPP_RUPP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUPP_RUPP_SHIFT)
-#define I40E_GLPRT_RXON2OFFCNT(_i, _j)              (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */
+#define I40E_GLPRT_RXON2OFFCNT(_i, _j)              (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
 #define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX           3
 #define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0
 #define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT)
-#define I40E_GLPRT_TDOLD(_i)               (0x00300A20 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_TDOLD(_i)               (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_TDOLD_MAX_INDEX         3
 #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0
 #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)
-#define I40E_GLPRT_TDPC(_i)        (0x00375400 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_TDPC(_i)        (0x00375400 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_TDPC_MAX_INDEX  3
 #define I40E_GLPRT_TDPC_TDPC_SHIFT 0
 #define I40E_GLPRT_TDPC_TDPC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDPC_TDPC_SHIFT)
-#define I40E_GLPRT_UPRCH(_i)         (0x003005A4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_UPRCH(_i)         (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_UPRCH_MAX_INDEX   3
 #define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0
 #define I40E_GLPRT_UPRCH_UPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT)
-#define I40E_GLPRT_UPRCL(_i)         (0x003005A0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_UPRCL(_i)         (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_UPRCL_MAX_INDEX   3
 #define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0
 #define I40E_GLPRT_UPRCL_UPRCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT)
-#define I40E_GLPRT_UPTCH(_i)         (0x003009C4 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_UPTCH(_i)         (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_UPTCH_MAX_INDEX   3
 #define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0
 #define I40E_GLPRT_UPTCH_UPTCH_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_UPTCH_UPTCH_SHIFT)
-#define I40E_GLPRT_UPTCL(_i)          (0x003009C0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_UPTCL(_i)          (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_UPTCL_MAX_INDEX    3
 #define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0
 #define I40E_GLPRT_UPTCL_VUPTCH_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPTCL_VUPTCH_SHIFT)
-#define I40E_GLSW_BPRCH(_i)         (0x00370104 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_BPRCH(_i)         (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_BPRCH_MAX_INDEX   15
 #define I40E_GLSW_BPRCH_BPRCH_SHIFT 0
 #define I40E_GLSW_BPRCH_BPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLSW_BPRCH_BPRCH_SHIFT)
-#define I40E_GLSW_BPRCL(_i)         (0x00370100 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_BPRCL(_i)         (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_BPRCL_MAX_INDEX   15
 #define I40E_GLSW_BPRCL_BPRCL_SHIFT 0
 #define I40E_GLSW_BPRCL_BPRCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPRCL_BPRCL_SHIFT)
-#define I40E_GLSW_BPTCH(_i)         (0x00340104 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_BPTCH(_i)         (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_BPTCH_MAX_INDEX   15
 #define I40E_GLSW_BPTCH_BPTCH_SHIFT 0
 #define I40E_GLSW_BPTCH_BPTCH_MASK  I40E_MASK(0xFFFF, I40E_GLSW_BPTCH_BPTCH_SHIFT)
-#define I40E_GLSW_BPTCL(_i)         (0x00340100 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_BPTCL(_i)         (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_BPTCL_MAX_INDEX   15
 #define I40E_GLSW_BPTCL_BPTCL_SHIFT 0
 #define I40E_GLSW_BPTCL_BPTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPTCL_BPTCL_SHIFT)
-#define I40E_GLSW_GORCH(_i)         (0x0035C004 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_GORCH(_i)         (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_GORCH_MAX_INDEX   15
 #define I40E_GLSW_GORCH_GORCH_SHIFT 0
 #define I40E_GLSW_GORCH_GORCH_MASK  I40E_MASK(0xFFFF, I40E_GLSW_GORCH_GORCH_SHIFT)
-#define I40E_GLSW_GORCL(_i)         (0x0035c000 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_GORCL(_i)         (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_GORCL_MAX_INDEX   15
 #define I40E_GLSW_GORCL_GORCL_SHIFT 0
 #define I40E_GLSW_GORCL_GORCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_GORCL_GORCL_SHIFT)
-#define I40E_GLSW_GOTCH(_i)         (0x0032C004 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_GOTCH(_i)         (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_GOTCH_MAX_INDEX   15
 #define I40E_GLSW_GOTCH_GOTCH_SHIFT 0
 #define I40E_GLSW_GOTCH_GOTCH_MASK  I40E_MASK(0xFFFF, I40E_GLSW_GOTCH_GOTCH_SHIFT)
-#define I40E_GLSW_GOTCL(_i)         (0x0032c000 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_GOTCL(_i)         (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_GOTCL_MAX_INDEX   15
 #define I40E_GLSW_GOTCL_GOTCL_SHIFT 0
 #define I40E_GLSW_GOTCL_GOTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_GOTCL_GOTCL_SHIFT)
-#define I40E_GLSW_MPRCH(_i)         (0x00370084 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_MPRCH(_i)         (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_MPRCH_MAX_INDEX   15
 #define I40E_GLSW_MPRCH_MPRCH_SHIFT 0
 #define I40E_GLSW_MPRCH_MPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLSW_MPRCH_MPRCH_SHIFT)
-#define I40E_GLSW_MPRCL(_i)         (0x00370080 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_MPRCL(_i)         (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_MPRCL_MAX_INDEX   15
 #define I40E_GLSW_MPRCL_MPRCL_SHIFT 0
 #define I40E_GLSW_MPRCL_MPRCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPRCL_MPRCL_SHIFT)
-#define I40E_GLSW_MPTCH(_i)         (0x00340084 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_MPTCH(_i)         (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_MPTCH_MAX_INDEX   15
 #define I40E_GLSW_MPTCH_MPTCH_SHIFT 0
 #define I40E_GLSW_MPTCH_MPTCH_MASK  I40E_MASK(0xFFFF, I40E_GLSW_MPTCH_MPTCH_SHIFT)
-#define I40E_GLSW_MPTCL(_i)         (0x00340080 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_MPTCL(_i)         (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_MPTCL_MAX_INDEX   15
 #define I40E_GLSW_MPTCL_MPTCL_SHIFT 0
 #define I40E_GLSW_MPTCL_MPTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPTCL_MPTCL_SHIFT)
-#define I40E_GLSW_RUPP(_i)        (0x00370180 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_RUPP(_i)        (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_RUPP_MAX_INDEX  15
 #define I40E_GLSW_RUPP_RUPP_SHIFT 0
 #define I40E_GLSW_RUPP_RUPP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_RUPP_RUPP_SHIFT)
-#define I40E_GLSW_TDPC(_i)        (0x00348000 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_TDPC(_i)        (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_TDPC_MAX_INDEX  15
 #define I40E_GLSW_TDPC_TDPC_SHIFT 0
 #define I40E_GLSW_TDPC_TDPC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_TDPC_TDPC_SHIFT)
-#define I40E_GLSW_UPRCH(_i)         (0x00370004 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_UPRCH(_i)         (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_UPRCH_MAX_INDEX   15
 #define I40E_GLSW_UPRCH_UPRCH_SHIFT 0
 #define I40E_GLSW_UPRCH_UPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLSW_UPRCH_UPRCH_SHIFT)
-#define I40E_GLSW_UPRCL(_i)         (0x00370000 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_UPRCL(_i)         (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_UPRCL_MAX_INDEX   15
 #define I40E_GLSW_UPRCL_UPRCL_SHIFT 0
 #define I40E_GLSW_UPRCL_UPRCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPRCL_UPRCL_SHIFT)
-#define I40E_GLSW_UPTCH(_i)         (0x00340004 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_UPTCH(_i)         (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_UPTCH_MAX_INDEX   15
 #define I40E_GLSW_UPTCH_UPTCH_SHIFT 0
 #define I40E_GLSW_UPTCH_UPTCH_MASK  I40E_MASK(0xFFFF, I40E_GLSW_UPTCH_UPTCH_SHIFT)
-#define I40E_GLSW_UPTCL(_i)         (0x00340000 + ((_i) * 8)) /* _i=0...15 */
+#define I40E_GLSW_UPTCL(_i)         (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSW_UPTCL_MAX_INDEX   15
 #define I40E_GLSW_UPTCL_UPTCL_SHIFT 0
 #define I40E_GLSW_UPTCL_UPTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPTCL_UPTCL_SHIFT)
-#define I40E_GLV_BPRCH(_i)         (0x0036D804 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_BPRCH(_i)         (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_BPRCH_MAX_INDEX   383
 #define I40E_GLV_BPRCH_BPRCH_SHIFT 0
 #define I40E_GLV_BPRCH_BPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLV_BPRCH_BPRCH_SHIFT)
-#define I40E_GLV_BPRCL(_i)         (0x0036d800 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_BPRCL(_i)         (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_BPRCL_MAX_INDEX   383
 #define I40E_GLV_BPRCL_BPRCL_SHIFT 0
 #define I40E_GLV_BPRCL_BPRCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_BPRCL_BPRCL_SHIFT)
-#define I40E_GLV_BPTCH(_i)         (0x0033D804 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_BPTCH(_i)         (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_BPTCH_MAX_INDEX   383
 #define I40E_GLV_BPTCH_BPTCH_SHIFT 0
 #define I40E_GLV_BPTCH_BPTCH_MASK  I40E_MASK(0xFFFF, I40E_GLV_BPTCH_BPTCH_SHIFT)
-#define I40E_GLV_BPTCL(_i)         (0x0033d800 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_BPTCL(_i)         (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_BPTCL_MAX_INDEX   383
 #define I40E_GLV_BPTCL_BPTCL_SHIFT 0
 #define I40E_GLV_BPTCL_BPTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_BPTCL_BPTCL_SHIFT)
-#define I40E_GLV_GORCH(_i)         (0x00358004 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_GORCH(_i)         (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_GORCH_MAX_INDEX   383
 #define I40E_GLV_GORCH_GORCH_SHIFT 0
 #define I40E_GLV_GORCH_GORCH_MASK  I40E_MASK(0xFFFF, I40E_GLV_GORCH_GORCH_SHIFT)
-#define I40E_GLV_GORCL(_i)         (0x00358000 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_GORCL(_i)         (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_GORCL_MAX_INDEX   383
 #define I40E_GLV_GORCL_GORCL_SHIFT 0
 #define I40E_GLV_GORCL_GORCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_GORCL_GORCL_SHIFT)
-#define I40E_GLV_GOTCH(_i)         (0x00328004 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_GOTCH(_i)         (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_GOTCH_MAX_INDEX   383
 #define I40E_GLV_GOTCH_GOTCH_SHIFT 0
 #define I40E_GLV_GOTCH_GOTCH_MASK  I40E_MASK(0xFFFF, I40E_GLV_GOTCH_GOTCH_SHIFT)
-#define I40E_GLV_GOTCL(_i)         (0x00328000 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_GOTCL(_i)         (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_GOTCL_MAX_INDEX   383
 #define I40E_GLV_GOTCL_GOTCL_SHIFT 0
 #define I40E_GLV_GOTCL_GOTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_GOTCL_GOTCL_SHIFT)
-#define I40E_GLV_MPRCH(_i)         (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_MPRCH(_i)         (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_MPRCH_MAX_INDEX   383
 #define I40E_GLV_MPRCH_MPRCH_SHIFT 0
 #define I40E_GLV_MPRCH_MPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLV_MPRCH_MPRCH_SHIFT)
-#define I40E_GLV_MPRCL(_i)         (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_MPRCL(_i)         (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_MPRCL_MAX_INDEX   383
 #define I40E_GLV_MPRCL_MPRCL_SHIFT 0
 #define I40E_GLV_MPRCL_MPRCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_MPRCL_MPRCL_SHIFT)
-#define I40E_GLV_MPTCH(_i)         (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_MPTCH(_i)         (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_MPTCH_MAX_INDEX   383
 #define I40E_GLV_MPTCH_MPTCH_SHIFT 0
 #define I40E_GLV_MPTCH_MPTCH_MASK  I40E_MASK(0xFFFF, I40E_GLV_MPTCH_MPTCH_SHIFT)
-#define I40E_GLV_MPTCL(_i)         (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_MPTCL(_i)         (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_MPTCL_MAX_INDEX   383
 #define I40E_GLV_MPTCL_MPTCL_SHIFT 0
 #define I40E_GLV_MPTCL_MPTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_MPTCL_MPTCL_SHIFT)
-#define I40E_GLV_RDPC(_i)        (0x00310000 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_RDPC(_i)        (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_RDPC_MAX_INDEX  383
 #define I40E_GLV_RDPC_RDPC_SHIFT 0
 #define I40E_GLV_RDPC_RDPC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT)
-#define I40E_GLV_RUPP(_i)        (0x0036E400 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_RUPP(_i)        (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_RUPP_MAX_INDEX  383
 #define I40E_GLV_RUPP_RUPP_SHIFT 0
 #define I40E_GLV_RUPP_RUPP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT)
-#define I40E_GLV_TEPC(_VSI)      (0x00344000 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_GLV_TEPC(_VSI)      (0x00344000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_TEPC_MAX_INDEX  383
 #define I40E_GLV_TEPC_TEPC_SHIFT 0
 #define I40E_GLV_TEPC_TEPC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT)
-#define I40E_GLV_UPRCH(_i)         (0x0036C004 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_UPRCH(_i)         (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_UPRCH_MAX_INDEX   383
 #define I40E_GLV_UPRCH_UPRCH_SHIFT 0
 #define I40E_GLV_UPRCH_UPRCH_MASK  I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT)
-#define I40E_GLV_UPRCL(_i)         (0x0036c000 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_UPRCL(_i)         (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_UPRCL_MAX_INDEX   383
 #define I40E_GLV_UPRCL_UPRCL_SHIFT 0
 #define I40E_GLV_UPRCL_UPRCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_UPRCL_UPRCL_SHIFT)
-#define I40E_GLV_UPTCH(_i)            (0x0033C004 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_UPTCH(_i)            (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_UPTCH_MAX_INDEX      383
 #define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0
 #define I40E_GLV_UPTCH_GLVUPTCH_MASK  I40E_MASK(0xFFFF, I40E_GLV_UPTCH_GLVUPTCH_SHIFT)
-#define I40E_GLV_UPTCL(_i)         (0x0033c000 + ((_i) * 8)) /* _i=0...383 */
+#define I40E_GLV_UPTCL(_i)         (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_GLV_UPTCL_MAX_INDEX   383
 #define I40E_GLV_UPTCL_UPTCL_SHIFT 0
 #define I40E_GLV_UPTCL_UPTCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLV_UPTCL_UPTCL_SHIFT)
-#define I40E_GLVEBTC_RBCH(_i, _j)      (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
+#define I40E_GLVEBTC_RBCH(_i, _j)      (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
 #define I40E_GLVEBTC_RBCH_MAX_INDEX   7
 #define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0
 #define I40E_GLVEBTC_RBCH_TCBCH_MASK  I40E_MASK(0xFFFF, I40E_GLVEBTC_RBCH_TCBCH_SHIFT)
-#define I40E_GLVEBTC_RBCL(_i, _j)      (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
+#define I40E_GLVEBTC_RBCL(_i, _j)      (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
 #define I40E_GLVEBTC_RBCL_MAX_INDEX   7
 #define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0
 #define I40E_GLVEBTC_RBCL_TCBCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RBCL_TCBCL_SHIFT)
-#define I40E_GLVEBTC_RPCH(_i, _j)      (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
+#define I40E_GLVEBTC_RPCH(_i, _j)      (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
 #define I40E_GLVEBTC_RPCH_MAX_INDEX   7
 #define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0
 #define I40E_GLVEBTC_RPCH_TCPCH_MASK  I40E_MASK(0xFFFF, I40E_GLVEBTC_RPCH_TCPCH_SHIFT)
-#define I40E_GLVEBTC_RPCL(_i, _j)      (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
+#define I40E_GLVEBTC_RPCL(_i, _j)      (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
 #define I40E_GLVEBTC_RPCL_MAX_INDEX   7
 #define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0
 #define I40E_GLVEBTC_RPCL_TCPCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RPCL_TCPCL_SHIFT)
-#define I40E_GLVEBTC_TBCH(_i, _j)      (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
+#define I40E_GLVEBTC_TBCH(_i, _j)      (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
 #define I40E_GLVEBTC_TBCH_MAX_INDEX   7
 #define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0
 #define I40E_GLVEBTC_TBCH_TCBCH_MASK  I40E_MASK(0xFFFF, I40E_GLVEBTC_TBCH_TCBCH_SHIFT)
-#define I40E_GLVEBTC_TBCL(_i, _j)      (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
+#define I40E_GLVEBTC_TBCL(_i, _j)      (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
 #define I40E_GLVEBTC_TBCL_MAX_INDEX   7
 #define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0
 #define I40E_GLVEBTC_TBCL_TCBCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TBCL_TCBCL_SHIFT)
-#define I40E_GLVEBTC_TPCH(_i, _j)      (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
+#define I40E_GLVEBTC_TPCH(_i, _j)      (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
 #define I40E_GLVEBTC_TPCH_MAX_INDEX   7
 #define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0
 #define I40E_GLVEBTC_TPCH_TCPCH_MASK  I40E_MASK(0xFFFF, I40E_GLVEBTC_TPCH_TCPCH_SHIFT)
-#define I40E_GLVEBTC_TPCL(_i, _j)      (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
+#define I40E_GLVEBTC_TPCL(_i, _j)      (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
 #define I40E_GLVEBTC_TPCL_MAX_INDEX   7
 #define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0
 #define I40E_GLVEBTC_TPCL_TCPCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TPCL_TCPCL_SHIFT)
-#define I40E_GLVEBVL_BPCH(_i)          (0x00374804 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_BPCH(_i)          (0x00374804 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_BPCH_MAX_INDEX    127
 #define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0
 #define I40E_GLVEBVL_BPCH_VLBPCH_MASK  I40E_MASK(0xFFFF, I40E_GLVEBVL_BPCH_VLBPCH_SHIFT)
-#define I40E_GLVEBVL_BPCL(_i)          (0x00374800 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_BPCL(_i)          (0x00374800 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_BPCL_MAX_INDEX    127
 #define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0
 #define I40E_GLVEBVL_BPCL_VLBPCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_BPCL_VLBPCL_SHIFT)
-#define I40E_GLVEBVL_GORCH(_i)         (0x00360004 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_GORCH(_i)         (0x00360004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_GORCH_MAX_INDEX   127
 #define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0
 #define I40E_GLVEBVL_GORCH_VLBCH_MASK  I40E_MASK(0xFFFF, I40E_GLVEBVL_GORCH_VLBCH_SHIFT)
-#define I40E_GLVEBVL_GORCL(_i)         (0x00360000 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_GORCL(_i)         (0x00360000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_GORCL_MAX_INDEX   127
 #define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0
 #define I40E_GLVEBVL_GORCL_VLBCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GORCL_VLBCL_SHIFT)
-#define I40E_GLVEBVL_GOTCH(_i)         (0x00330004 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_GOTCH(_i)         (0x00330004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_GOTCH_MAX_INDEX   127
 #define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0
 #define I40E_GLVEBVL_GOTCH_VLBCH_MASK  I40E_MASK(0xFFFF, I40E_GLVEBVL_GOTCH_VLBCH_SHIFT)
-#define I40E_GLVEBVL_GOTCL(_i)         (0x00330000 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_GOTCL(_i)         (0x00330000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_GOTCL_MAX_INDEX   127
 #define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0
 #define I40E_GLVEBVL_GOTCL_VLBCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GOTCL_VLBCL_SHIFT)
-#define I40E_GLVEBVL_MPCH(_i)          (0x00374404 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_MPCH(_i)          (0x00374404 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_MPCH_MAX_INDEX    127
 #define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0
 #define I40E_GLVEBVL_MPCH_VLMPCH_MASK  I40E_MASK(0xFFFF, I40E_GLVEBVL_MPCH_VLMPCH_SHIFT)
-#define I40E_GLVEBVL_MPCL(_i)          (0x00374400 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_MPCL(_i)          (0x00374400 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_MPCL_MAX_INDEX    127
 #define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0
 #define I40E_GLVEBVL_MPCL_VLMPCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_MPCL_VLMPCL_SHIFT)
-#define I40E_GLVEBVL_UPCH(_i)          (0x00374004 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_UPCH(_i)          (0x00374004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_UPCH_MAX_INDEX    127
 #define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0
 #define I40E_GLVEBVL_UPCH_VLUPCH_MASK  I40E_MASK(0xFFFF, I40E_GLVEBVL_UPCH_VLUPCH_SHIFT)
-#define I40E_GLVEBVL_UPCL(_i)          (0x00374000 + ((_i) * 8)) /* _i=0...127 */
+#define I40E_GLVEBVL_UPCL(_i)          (0x00374000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_GLVEBVL_UPCL_MAX_INDEX    127
 #define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0
 #define I40E_GLVEBVL_UPCL_VLUPCL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_UPCL_VLUPCL_SHIFT)
-#define I40E_GL_MTG_FLU_MSK_H                 0x00269F4C
+#define I40E_GL_MTG_FLU_MSK_H                 0x00269F4C /* Reset: CORER */
 #define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0
 #define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK  I40E_MASK(0xFFFF, I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT)
-#define I40E_GL_SWR_DEF_ACT(_i)              (0x00270200 + ((_i) * 4)) /* _i=0...35 */
+#define I40E_GL_SWR_DEF_ACT(_i)              (0x00270200 + ((_i) * 4)) /* _i=0...35 */ /* Reset: CORER */
 #define I40E_GL_SWR_DEF_ACT_MAX_INDEX        35
 #define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0
 #define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT)
-#define I40E_GL_SWR_DEF_ACT_EN(_i)                     (0x0026CFB8 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GL_SWR_DEF_ACT_EN(_i)                     (0x0026CFB8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GL_SWR_DEF_ACT_EN_MAX_INDEX               1
 #define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0
 #define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT)
-#define I40E_PRTTSYN_ADJ               0x001E4280
+#define I40E_PRTTSYN_ADJ               0x001E4280 /* Reset: GLOBR */
 #define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0
 #define I40E_PRTTSYN_ADJ_TSYNADJ_MASK  I40E_MASK(0x7FFFFFFF, I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT)
 #define I40E_PRTTSYN_ADJ_SIGN_SHIFT    31
 #define I40E_PRTTSYN_ADJ_SIGN_MASK     I40E_MASK(0x1, I40E_PRTTSYN_ADJ_SIGN_SHIFT)
-#define I40E_PRTTSYN_AUX_0(_i)           (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */
+#define I40E_PRTTSYN_AUX_0(_i)           (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_AUX_0_MAX_INDEX     1
 #define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0
 #define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK  I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
@@ -3143,17 +2897,17 @@
 #define I40E_PRTTSYN_AUX_0_PULSEW_MASK   I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
 #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16
 #define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK  I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
-#define I40E_PRTTSYN_AUX_1(_i)               (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */
+#define I40E_PRTTSYN_AUX_1(_i)               (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_AUX_1_MAX_INDEX         1
 #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT      0
 #define I40E_PRTTSYN_AUX_1_INSTNT_MASK       I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
 #define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1
 #define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK  I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT)
-#define I40E_PRTTSYN_CLKO(_i)            (0x001E4240 + ((_i) * 32)) /* _i=0...1 */
+#define I40E_PRTTSYN_CLKO(_i)            (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_CLKO_MAX_INDEX      1
 #define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0
 #define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT)
-#define I40E_PRTTSYN_CTL0                       0x001E4200
+#define I40E_PRTTSYN_CTL0                       0x001E4200 /* Reset: GLOBR */
 #define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0
 #define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK  I40E_MASK(0x1, I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT)
 #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT  1
@@ -3168,7 +2922,7 @@
 #define I40E_PRTTSYN_CTL0_TSYNACT_MASK          I40E_MASK(0x3, I40E_PRTTSYN_CTL0_TSYNACT_SHIFT)
 #define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT         31
 #define I40E_PRTTSYN_CTL0_TSYNENA_MASK          I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT)
-#define I40E_PRTTSYN_CTL1                   0x00085020
+#define I40E_PRTTSYN_CTL1                   0x00085020 /* Reset: CORER */
 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0
 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK  I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT)
 #define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8
@@ -3183,29 +2937,29 @@
 #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK      I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT)
 #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT     31
 #define I40E_PRTTSYN_CTL1_TSYNENA_MASK      I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT)
-#define I40E_PRTTSYN_EVNT_H(_i)              (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */
+#define I40E_PRTTSYN_EVNT_H(_i)              (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_EVNT_H_MAX_INDEX        1
 #define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0
 #define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT)
-#define I40E_PRTTSYN_EVNT_L(_i)              (0x001E4080 + ((_i) * 32)) /* _i=0...1 */
+#define I40E_PRTTSYN_EVNT_L(_i)              (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_EVNT_L_MAX_INDEX        1
 #define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0
 #define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT)
-#define I40E_PRTTSYN_INC_H                 0x001E4060
+#define I40E_PRTTSYN_INC_H                 0x001E4060 /* Reset: GLOBR */
 #define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0
 #define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK  I40E_MASK(0x3F, I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT)
-#define I40E_PRTTSYN_INC_L                 0x001E4040
+#define I40E_PRTTSYN_INC_L                 0x001E4040 /* Reset: GLOBR */
 #define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0
 #define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT)
-#define I40E_PRTTSYN_RXTIME_H(_i)            (0x00085040 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRTTSYN_RXTIME_H(_i)            (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_PRTTSYN_RXTIME_H_MAX_INDEX      3
 #define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0
 #define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT)
-#define I40E_PRTTSYN_RXTIME_L(_i)            (0x000850C0 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRTTSYN_RXTIME_L(_i)            (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_PRTTSYN_RXTIME_L_MAX_INDEX      3
 #define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0
 #define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT)
-#define I40E_PRTTSYN_STAT_0              0x001E4220
+#define I40E_PRTTSYN_STAT_0              0x001E4220 /* Reset: GLOBR */
 #define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0
 #define I40E_PRTTSYN_STAT_0_EVENT0_MASK  I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT)
 #define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1
@@ -3216,7 +2970,7 @@
 #define I40E_PRTTSYN_STAT_0_TGT1_MASK    I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT1_SHIFT)
 #define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4
 #define I40E_PRTTSYN_STAT_0_TXTIME_MASK  I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT)
-#define I40E_PRTTSYN_STAT_1            0x00085140
+#define I40E_PRTTSYN_STAT_1            0x00085140 /* Reset: CORER */
 #define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0
 #define I40E_PRTTSYN_STAT_1_RXT0_MASK  I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT0_SHIFT)
 #define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1
@@ -3225,30 +2979,30 @@
 #define I40E_PRTTSYN_STAT_1_RXT2_MASK  I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT2_SHIFT)
 #define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3
 #define I40E_PRTTSYN_STAT_1_RXT3_MASK  I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT3_SHIFT)
-#define I40E_PRTTSYN_TGT_H(_i)              (0x001E4180 + ((_i) * 32)) /* _i=0...1 */
+#define I40E_PRTTSYN_TGT_H(_i)              (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_TGT_H_MAX_INDEX        1
 #define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0
 #define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT)
-#define I40E_PRTTSYN_TGT_L(_i)              (0x001E4140 + ((_i) * 32)) /* _i=0...1 */
+#define I40E_PRTTSYN_TGT_L(_i)              (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_TGT_L_MAX_INDEX        1
 #define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0
 #define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT)
-#define I40E_PRTTSYN_TIME_H                  0x001E4120
+#define I40E_PRTTSYN_TIME_H                  0x001E4120 /* Reset: GLOBR */
 #define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0
 #define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT)
-#define I40E_PRTTSYN_TIME_L                  0x001E4100
+#define I40E_PRTTSYN_TIME_L                  0x001E4100 /* Reset: GLOBR */
 #define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0
 #define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT)
-#define I40E_PRTTSYN_TXTIME_H                0x001E41E0
+#define I40E_PRTTSYN_TXTIME_H                0x001E41E0 /* Reset: GLOBR */
 #define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0
 #define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT)
-#define I40E_PRTTSYN_TXTIME_L                0x001E41C0
+#define I40E_PRTTSYN_TXTIME_L                0x001E41C0 /* Reset: GLOBR */
 #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0
 #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)
-#define I40E_GLSCD_QUANTA                  0x000B2080
+#define I40E_GLSCD_QUANTA                  0x000B2080 /* Reset: CORER */
 #define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0
 #define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK  I40E_MASK(0x7, I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT)
-#define I40E_GL_MDET_RX                0x0012A510
+#define I40E_GL_MDET_RX                0x0012A510 /* Reset: CORER */
 #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0
 #define I40E_GL_MDET_RX_FUNCTION_MASK  I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)
 #define I40E_GL_MDET_RX_EVENT_SHIFT    8
@@ -3257,37 +3011,39 @@
 #define I40E_GL_MDET_RX_QUEUE_MASK     I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT)
 #define I40E_GL_MDET_RX_VALID_SHIFT    31
 #define I40E_GL_MDET_RX_VALID_MASK     I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT)
-#define I40E_GL_MDET_TX                0x000E6480
-#define I40E_GL_MDET_TX_FUNCTION_SHIFT 0
-#define I40E_GL_MDET_TX_FUNCTION_MASK  I40E_MASK(0xFF, I40E_GL_MDET_TX_FUNCTION_SHIFT)
-#define I40E_GL_MDET_TX_EVENT_SHIFT    8
-#define I40E_GL_MDET_TX_EVENT_MASK     I40E_MASK(0x1FF, I40E_GL_MDET_TX_EVENT_SHIFT)
-#define I40E_GL_MDET_TX_QUEUE_SHIFT    17
-#define I40E_GL_MDET_TX_QUEUE_MASK     I40E_MASK(0x3FFF, I40E_GL_MDET_TX_QUEUE_SHIFT)
-#define I40E_GL_MDET_TX_VALID_SHIFT    31
-#define I40E_GL_MDET_TX_VALID_MASK     I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT)
-#define I40E_PF_MDET_RX             0x0012A400
+#define I40E_GL_MDET_TX              0x000E6480 /* Reset: CORER */
+#define I40E_GL_MDET_TX_QUEUE_SHIFT  0
+#define I40E_GL_MDET_TX_QUEUE_MASK   I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT)
+#define I40E_GL_MDET_TX_VF_NUM_SHIFT 12
+#define I40E_GL_MDET_TX_VF_NUM_MASK  I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT)
+#define I40E_GL_MDET_TX_PF_NUM_SHIFT 21
+#define I40E_GL_MDET_TX_PF_NUM_MASK  I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT)
+#define I40E_GL_MDET_TX_EVENT_SHIFT  25
+#define I40E_GL_MDET_TX_EVENT_MASK   I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT)
+#define I40E_GL_MDET_TX_VALID_SHIFT  31
+#define I40E_GL_MDET_TX_VALID_MASK   I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT)
+#define I40E_PF_MDET_RX             0x0012A400 /* Reset: CORER */
 #define I40E_PF_MDET_RX_VALID_SHIFT 0
 #define I40E_PF_MDET_RX_VALID_MASK  I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT)
-#define I40E_PF_MDET_TX             0x000E6400
+#define I40E_PF_MDET_TX             0x000E6400 /* Reset: CORER */
 #define I40E_PF_MDET_TX_VALID_SHIFT 0
 #define I40E_PF_MDET_TX_VALID_MASK  I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT)
-#define I40E_PF_VT_PFALLOC               0x001C0500
+#define I40E_PF_VT_PFALLOC               0x001C0500 /* Reset: CORER */
 #define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0
 #define I40E_PF_VT_PFALLOC_FIRSTVF_MASK  I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT)
 #define I40E_PF_VT_PFALLOC_LASTVF_SHIFT  8
 #define I40E_PF_VT_PFALLOC_LASTVF_MASK   I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
 #define I40E_PF_VT_PFALLOC_VALID_SHIFT   31
 #define I40E_PF_VT_PFALLOC_VALID_MASK    I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT)
-#define I40E_VP_MDET_RX(_VF)        (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VP_MDET_RX(_VF)        (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VP_MDET_RX_MAX_INDEX   127
 #define I40E_VP_MDET_RX_VALID_SHIFT 0
 #define I40E_VP_MDET_RX_VALID_MASK  I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT)
-#define I40E_VP_MDET_TX(_VF)        (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VP_MDET_TX(_VF)        (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VP_MDET_TX_MAX_INDEX   127
 #define I40E_VP_MDET_TX_VALID_SHIFT 0
 #define I40E_VP_MDET_TX_VALID_MASK  I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT)
-#define I40E_GLPM_WUMC                    0x0006C800
+#define I40E_GLPM_WUMC                    0x0006C800 /* Reset: POR */
 #define I40E_GLPM_WUMC_NOTCO_SHIFT        0
 #define I40E_GLPM_WUMC_NOTCO_MASK         I40E_MASK(0x1, I40E_GLPM_WUMC_NOTCO_SHIFT)
 #define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1
@@ -3298,17 +3054,17 @@
 #define I40E_GLPM_WUMC_RESERVED_4_MASK    I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT)
 #define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT    16
 #define I40E_GLPM_WUMC_MNG_WU_PF_MASK     I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)
-#define I40E_PFPM_APM            0x000B8080
+#define I40E_PFPM_APM            0x000B8080 /* Reset: POR */
 #define I40E_PFPM_APM_APME_SHIFT 0
 #define I40E_PFPM_APM_APME_MASK  I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT)
-#define I40E_PFPM_FHFT_LENGTH(_i)          (0x0006A000 + ((_i) * 128)) /* _i=0...7 */
+#define I40E_PFPM_FHFT_LENGTH(_i)          (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */
 #define I40E_PFPM_FHFT_LENGTH_MAX_INDEX    7
 #define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0
 #define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK  I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT)
-#define I40E_PFPM_WUC                 0x0006B200
+#define I40E_PFPM_WUC                 0x0006B200 /* Reset: POR */
 #define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5
 #define I40E_PFPM_WUC_EN_APM_D0_MASK  I40E_MASK(0x1, I40E_PFPM_WUC_EN_APM_D0_SHIFT)
-#define I40E_PFPM_WUFC                 0x0006B400
+#define I40E_PFPM_WUFC                 0x0006B400 /* Reset: POR */
 #define I40E_PFPM_WUFC_LNKC_SHIFT      0
 #define I40E_PFPM_WUFC_LNKC_MASK       I40E_MASK(0x1, I40E_PFPM_WUFC_LNKC_SHIFT)
 #define I40E_PFPM_WUFC_MAG_SHIFT       1
@@ -3349,7 +3105,7 @@
 #define I40E_PFPM_WUFC_FLX7_MASK       I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_SHIFT)
 #define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31
 #define I40E_PFPM_WUFC_FW_RST_WK_MASK  I40E_MASK(0x1, I40E_PFPM_WUFC_FW_RST_WK_SHIFT)
-#define I40E_PFPM_WUS                  0x0006B600
+#define I40E_PFPM_WUS                  0x0006B600 /* Reset: POR */
 #define I40E_PFPM_WUS_LNKC_SHIFT       0
 #define I40E_PFPM_WUS_LNKC_MASK        I40E_MASK(0x1, I40E_PFPM_WUS_LNKC_SHIFT)
 #define I40E_PFPM_WUS_MAG_SHIFT        1
@@ -3376,12 +3132,12 @@
 #define I40E_PFPM_WUS_FLX7_MASK        I40E_MASK(0x1, I40E_PFPM_WUS_FLX7_SHIFT)
 #define I40E_PFPM_WUS_FW_RST_WK_SHIFT  31
 #define I40E_PFPM_WUS_FW_RST_WK_MASK   I40E_MASK(0x1, I40E_PFPM_WUS_FW_RST_WK_SHIFT)
-#define I40E_PRTPM_FHFHR                 0x0006C000
+#define I40E_PRTPM_FHFHR                 0x0006C000 /* Reset: POR */
 #define I40E_PRTPM_FHFHR_UNICAST_SHIFT   0
 #define I40E_PRTPM_FHFHR_UNICAST_MASK    I40E_MASK(0x1, I40E_PRTPM_FHFHR_UNICAST_SHIFT)
 #define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1
 #define I40E_PRTPM_FHFHR_MULTICAST_MASK  I40E_MASK(0x1, I40E_PRTPM_FHFHR_MULTICAST_SHIFT)
-#define I40E_PRTPM_SAH(_i)             (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRTPM_SAH(_i)             (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */
 #define I40E_PRTPM_SAH_MAX_INDEX       3
 #define I40E_PRTPM_SAH_PFPM_SAH_SHIFT  0
 #define I40E_PRTPM_SAH_PFPM_SAH_MASK   I40E_MASK(0xFFFF, I40E_PRTPM_SAH_PFPM_SAH_SHIFT)
@@ -3391,20 +3147,20 @@
 #define I40E_PRTPM_SAH_MC_MAG_EN_MASK  I40E_MASK(0x1, I40E_PRTPM_SAH_MC_MAG_EN_SHIFT)
 #define I40E_PRTPM_SAH_AV_SHIFT        31
 #define I40E_PRTPM_SAH_AV_MASK         I40E_MASK(0x1, I40E_PRTPM_SAH_AV_SHIFT)
-#define I40E_PRTPM_SAL(_i)            (0x001E4440 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRTPM_SAL(_i)            (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */
 #define I40E_PRTPM_SAL_MAX_INDEX      3
 #define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0
 #define I40E_PRTPM_SAL_PFPM_SAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTPM_SAL_PFPM_SAL_SHIFT)
-#define I40E_VF_ARQBAH1              0x00006000
+#define I40E_VF_ARQBAH1              0x00006000 /* Reset: EMPR */
 #define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0
 #define I40E_VF_ARQBAH1_ARQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)
-#define I40E_VF_ARQBAL1              0x00006C00
+#define I40E_VF_ARQBAL1              0x00006C00 /* Reset: EMPR */
 #define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0
 #define I40E_VF_ARQBAL1_ARQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT)
-#define I40E_VF_ARQH1            0x00007400
+#define I40E_VF_ARQH1            0x00007400 /* Reset: EMPR */
 #define I40E_VF_ARQH1_ARQH_SHIFT 0
 #define I40E_VF_ARQH1_ARQH_MASK  I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)
-#define I40E_VF_ARQLEN1                 0x00008000
+#define I40E_VF_ARQLEN1                 0x00008000 /* Reset: EMPR */
 #define I40E_VF_ARQLEN1_ARQLEN_SHIFT    0
 #define I40E_VF_ARQLEN1_ARQLEN_MASK     I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)
 #define I40E_VF_ARQLEN1_ARQVFE_SHIFT    28
@@ -3415,19 +3171,19 @@
 #define I40E_VF_ARQLEN1_ARQCRIT_MASK    I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
 #define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
 #define I40E_VF_ARQLEN1_ARQENABLE_MASK  I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
-#define I40E_VF_ARQT1            0x00007000
+#define I40E_VF_ARQT1            0x00007000 /* Reset: EMPR */
 #define I40E_VF_ARQT1_ARQT_SHIFT 0
 #define I40E_VF_ARQT1_ARQT_MASK  I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
-#define I40E_VF_ATQBAH1              0x00007800
+#define I40E_VF_ATQBAH1              0x00007800 /* Reset: EMPR */
 #define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0
 #define I40E_VF_ATQBAH1_ATQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)
-#define I40E_VF_ATQBAL1              0x00007C00
+#define I40E_VF_ATQBAL1              0x00007C00 /* Reset: EMPR */
 #define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0
 #define I40E_VF_ATQBAL1_ATQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)
-#define I40E_VF_ATQH1            0x00006400
+#define I40E_VF_ATQH1            0x00006400 /* Reset: EMPR */
 #define I40E_VF_ATQH1_ATQH_SHIFT 0
 #define I40E_VF_ATQH1_ATQH_MASK  I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)
-#define I40E_VF_ATQLEN1                 0x00006800
+#define I40E_VF_ATQLEN1                 0x00006800 /* Reset: EMPR */
 #define I40E_VF_ATQLEN1_ATQLEN_SHIFT    0
 #define I40E_VF_ATQLEN1_ATQLEN_MASK     I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)
 #define I40E_VF_ATQLEN1_ATQVFE_SHIFT    28
@@ -3438,13 +3194,13 @@
 #define I40E_VF_ATQLEN1_ATQCRIT_MASK    I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
 #define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
 #define I40E_VF_ATQLEN1_ATQENABLE_MASK  I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
-#define I40E_VF_ATQT1            0x00008400
+#define I40E_VF_ATQT1            0x00008400 /* Reset: EMPR */
 #define I40E_VF_ATQT1_ATQT_SHIFT 0
 #define I40E_VF_ATQT1_ATQT_MASK  I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
-#define I40E_VFGEN_RSTAT                 0x00008800
+#define I40E_VFGEN_RSTAT                 0x00008800 /* Reset: VFR */
 #define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0
 #define I40E_VFGEN_RSTAT_VFR_STATE_MASK  I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)
-#define I40E_VFINT_DYN_CTL01                       0x00005C00
+#define I40E_VFINT_DYN_CTL01                       0x00005C00 /* Reset: VFR */
 #define I40E_VFINT_DYN_CTL01_INTENA_SHIFT          0
 #define I40E_VFINT_DYN_CTL01_INTENA_MASK           I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)
 #define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT        1
@@ -3461,7 +3217,7 @@
 #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
 #define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT      31
 #define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)
-#define I40E_VFINT_DYN_CTLN1(_INTVF)               (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */
+#define I40E_VFINT_DYN_CTLN1(_INTVF)               (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
 #define I40E_VFINT_DYN_CTLN1_MAX_INDEX             15
 #define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT          0
 #define I40E_VFINT_DYN_CTLN1_INTENA_MASK           I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)
@@ -3479,14 +3235,14 @@
 #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
 #define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT      31
 #define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
-#define I40E_VFINT_ICR0_ENA1                        0x00005000
+#define I40E_VFINT_ICR0_ENA1                        0x00005000 /* Reset: CORER */
 #define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25
 #define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK  I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
 #define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT           30
 #define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK            I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
 #define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT             31
 #define I40E_VFINT_ICR0_ENA1_RSVD_MASK              I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)
-#define I40E_VFINT_ICR01                        0x00004800
+#define I40E_VFINT_ICR01                        0x00004800 /* Reset: CORER */
 #define I40E_VFINT_ICR01_INTEVENT_SHIFT         0
 #define I40E_VFINT_ICR01_INTEVENT_MASK          I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT)
 #define I40E_VFINT_ICR01_QUEUE_0_SHIFT          1
@@ -3503,54 +3259,54 @@
 #define I40E_VFINT_ICR01_ADMINQ_MASK            I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT)
 #define I40E_VFINT_ICR01_SWINT_SHIFT            31
 #define I40E_VFINT_ICR01_SWINT_MASK             I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT)
-#define I40E_VFINT_ITR01(_i)            (0x00004C00 + ((_i) * 4)) /* _i=0...2 */
+#define I40E_VFINT_ITR01(_i)            (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
 #define I40E_VFINT_ITR01_MAX_INDEX      2
 #define I40E_VFINT_ITR01_INTERVAL_SHIFT 0
 #define I40E_VFINT_ITR01_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT)
-#define I40E_VFINT_ITRN1(_i, _INTVF)     (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */
+#define I40E_VFINT_ITRN1(_i, _INTVF)     (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
 #define I40E_VFINT_ITRN1_MAX_INDEX      2
 #define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0
 #define I40E_VFINT_ITRN1_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)
-#define I40E_VFINT_STAT_CTL01                      0x00005400
+#define I40E_VFINT_STAT_CTL01                      0x00005400 /* Reset: VFR */
 #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
 #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK  I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
-#define I40E_QRX_TAIL1(_Q)        (0x00002000 + ((_Q) * 4)) /* _i=0...15 */
+#define I40E_QRX_TAIL1(_Q)        (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_QRX_TAIL1_MAX_INDEX  15
 #define I40E_QRX_TAIL1_TAIL_SHIFT 0
 #define I40E_QRX_TAIL1_TAIL_MASK  I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT)
-#define I40E_QTX_TAIL1(_Q)        (0x00000000 + ((_Q) * 4)) /* _i=0...15 */
+#define I40E_QTX_TAIL1(_Q)        (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
 #define I40E_QTX_TAIL1_MAX_INDEX  15
 #define I40E_QTX_TAIL1_TAIL_SHIFT 0
 #define I40E_QTX_TAIL1_TAIL_MASK  I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT)
-#define I40E_VFMSIX_PBA              0x00002000
+#define I40E_VFMSIX_PBA              0x00002000 /* Reset: VFLR */
 #define I40E_VFMSIX_PBA_PENBIT_SHIFT 0
 #define I40E_VFMSIX_PBA_PENBIT_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT)
-#define I40E_VFMSIX_TADD(_i)              (0x00000000 + ((_i) * 16)) /* _i=0...16 */
+#define I40E_VFMSIX_TADD(_i)              (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
 #define I40E_VFMSIX_TADD_MAX_INDEX        16
 #define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0
 #define I40E_VFMSIX_TADD_MSIXTADD10_MASK  I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)
 #define I40E_VFMSIX_TADD_MSIXTADD_SHIFT   2
 #define I40E_VFMSIX_TADD_MSIXTADD_MASK    I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT)
-#define I40E_VFMSIX_TMSG(_i)            (0x00000008 + ((_i) * 16)) /* _i=0...16 */
+#define I40E_VFMSIX_TMSG(_i)            (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
 #define I40E_VFMSIX_TMSG_MAX_INDEX      16
 #define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0
 #define I40E_VFMSIX_TMSG_MSIXTMSG_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)
-#define I40E_VFMSIX_TUADD(_i)             (0x00000004 + ((_i) * 16)) /* _i=0...16 */
+#define I40E_VFMSIX_TUADD(_i)             (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
 #define I40E_VFMSIX_TUADD_MAX_INDEX       16
 #define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0
 #define I40E_VFMSIX_TUADD_MSIXTUADD_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)
-#define I40E_VFMSIX_TVCTRL(_i)        (0x0000000C + ((_i) * 16)) /* _i=0...16 */
+#define I40E_VFMSIX_TVCTRL(_i)        (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
 #define I40E_VFMSIX_TVCTRL_MAX_INDEX  16
 #define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0
 #define I40E_VFMSIX_TVCTRL_MASK_MASK  I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT)
-#define I40E_VFCM_PE_ERRDATA                  0x0000DC00
+#define I40E_VFCM_PE_ERRDATA                  0x0000DC00 /* Reset: VFR */
 #define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
 #define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK  I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
 #define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT     4
 #define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK      I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)
 #define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT      8
 #define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK       I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)
-#define I40E_VFCM_PE_ERRINFO                     0x0000D800
+#define I40E_VFCM_PE_ERRINFO                     0x0000D800 /* Reset: VFR */
 #define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT   0
 #define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK    I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
 #define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT    4
@@ -3561,11 +3317,11 @@
 #define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
 #define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
 #define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
-#define I40E_VFQF_HENA(_i)             (0x0000C400 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_VFQF_HENA(_i)             (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_VFQF_HENA_MAX_INDEX       1
 #define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0
 #define I40E_VFQF_HENA_PTYPE_ENA_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT)
-#define I40E_VFQF_HKEY(_i)         (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */
+#define I40E_VFQF_HKEY(_i)         (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
 #define I40E_VFQF_HKEY_MAX_INDEX   12
 #define I40E_VFQF_HKEY_KEY_0_SHIFT 0
 #define I40E_VFQF_HKEY_KEY_0_MASK  I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT)
@@ -3575,7 +3331,7 @@
 #define I40E_VFQF_HKEY_KEY_2_MASK  I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT)
 #define I40E_VFQF_HKEY_KEY_3_SHIFT 24
 #define I40E_VFQF_HKEY_KEY_3_MASK  I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT)
-#define I40E_VFQF_HLUT(_i)        (0x0000D000 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_VFQF_HLUT(_i)        (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_VFQF_HLUT_MAX_INDEX  15
 #define I40E_VFQF_HLUT_LUT0_SHIFT 0
 #define I40E_VFQF_HLUT_LUT0_MASK  I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT)
@@ -3585,7 +3341,7 @@
 #define I40E_VFQF_HLUT_LUT2_MASK  I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT)
 #define I40E_VFQF_HLUT_LUT3_SHIFT 24
 #define I40E_VFQF_HLUT_LUT3_MASK  I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT)
-#define I40E_VFQF_HREGION(_i)                  (0x0000D400 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_VFQF_HREGION(_i)                  (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_VFQF_HREGION_MAX_INDEX            7
 #define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
 #define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK  I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
diff --git a/sys/dev/i40e/i40e_register_x710_int.h b/sys/dev/i40e/i40e_register_x710_int.h
index d227f34..2f970cd 100755
--- a/sys/dev/i40e/i40e_register_x710_int.h
+++ b/sys/dev/i40e/i40e_register_x710_int.h
@@ -37,7 +37,7 @@
 
 /* PF - Admin Queue */
 
-#define I40E_GL_ARQLEN                 0x000802C0
+#define I40E_GL_ARQLEN                 0x000802C0 /* Reset: EMPR */
 #define I40E_GL_ARQLEN_ARQLEN_SHIFT    0
 #define I40E_GL_ARQLEN_ARQLEN_MASK     I40E_MASK(0x3FF, I40E_GL_ARQLEN_ARQLEN_SHIFT)
 #define I40E_GL_ARQLEN_ARQVFE_SHIFT    28
@@ -51,7 +51,7 @@
 
 /* PF - Analyzer Registers */
 
-#define I40E_GL_RCU_PRS_L2TAG(_i)             (0x0026CFC0 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GL_RCU_PRS_L2TAG(_i)             (0x0026CFC0 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GL_RCU_PRS_L2TAG_MAX_INDEX       7
 #define I40E_GL_RCU_PRS_L2TAG_LENGTH_SHIFT    0
 #define I40E_GL_RCU_PRS_L2TAG_LENGTH_MASK     I40E_MASK(0x7F, I40E_GL_RCU_PRS_L2TAG_LENGTH_SHIFT)
@@ -70,17 +70,17 @@
 #define I40E_GL_RCU_PRS_L2TAG_ETHERTYPE_SHIFT 16
 #define I40E_GL_RCU_PRS_L2TAG_ETHERTYPE_MASK  I40E_MASK(0xFFFF, I40E_GL_RCU_PRS_L2TAG_ETHERTYPE_SHIFT)
 
-#define I40E_GL_SWT_L2TAG0(_i)        (0x00044278 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GL_SWT_L2TAG0(_i)        (0x00044278 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GL_SWT_L2TAG0_MAX_INDEX  7
 #define I40E_GL_SWT_L2TAG0_DATA_SHIFT 0
 #define I40E_GL_SWT_L2TAG0_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWT_L2TAG0_DATA_SHIFT)
 
-#define I40E_GL_SWT_L2TAG1(_i)        (0x00044298 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GL_SWT_L2TAG1(_i)        (0x00044298 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GL_SWT_L2TAG1_MAX_INDEX  7
 #define I40E_GL_SWT_L2TAG1_DATA_SHIFT 0
 #define I40E_GL_SWT_L2TAG1_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWT_L2TAG1_DATA_SHIFT)
 
-#define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GL_SWT_L2TAGCTRL_MAX_INDEX       7
 #define I40E_GL_SWT_L2TAGCTRL_LENGTH_SHIFT    0
 #define I40E_GL_SWT_L2TAGCTRL_LENGTH_MASK     I40E_MASK(0x7F, I40E_GL_SWT_L2TAGCTRL_LENGTH_SHIFT)
@@ -99,41 +99,41 @@
 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 
-#define I40E_GL_SWT_L2TAGRXEB(_i)          (0x00051000 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GL_SWT_L2TAGRXEB(_i)          (0x00051000 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GL_SWT_L2TAGRXEB_MAX_INDEX    7
 #define I40E_GL_SWT_L2TAGRXEB_OFFSET_SHIFT 0
 #define I40E_GL_SWT_L2TAGRXEB_OFFSET_MASK  I40E_MASK(0xFF, I40E_GL_SWT_L2TAGRXEB_OFFSET_SHIFT)
 #define I40E_GL_SWT_L2TAGRXEB_LENGTH_SHIFT 8
 #define I40E_GL_SWT_L2TAGRXEB_LENGTH_MASK  I40E_MASK(0x3, I40E_GL_SWT_L2TAGRXEB_LENGTH_SHIFT)
 
-#define I40E_GL_SWT_L2TAGTXIB(_i)          (0x000442B8 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GL_SWT_L2TAGTXIB(_i)          (0x000442B8 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GL_SWT_L2TAGTXIB_MAX_INDEX    7
 #define I40E_GL_SWT_L2TAGTXIB_OFFSET_SHIFT 0
 #define I40E_GL_SWT_L2TAGTXIB_OFFSET_MASK  I40E_MASK(0xFF, I40E_GL_SWT_L2TAGTXIB_OFFSET_SHIFT)
 #define I40E_GL_SWT_L2TAGTXIB_LENGTH_SHIFT 8
 #define I40E_GL_SWT_L2TAGTXIB_LENGTH_MASK  I40E_MASK(0x3, I40E_GL_SWT_L2TAGTXIB_LENGTH_SHIFT)
 
-#define I40E_GLANL_L2ULP(_i)             (0x001C0A2C + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLANL_L2ULP(_i)             (0x001C0A2C + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLANL_L2ULP_MAX_INDEX       15
 #define I40E_GLANL_L2ULP_ETHERTYPE_SHIFT 0
 #define I40E_GLANL_L2ULP_ETHERTYPE_MASK  I40E_MASK(0xFFFF, I40E_GLANL_L2ULP_ETHERTYPE_SHIFT)
 #define I40E_GLANL_L2ULP_ENABLE_SHIFT    31
 #define I40E_GLANL_L2ULP_ENABLE_MASK     I40E_MASK(0x1, I40E_GLANL_L2ULP_ENABLE_SHIFT)
 
-#define I40E_GLANL_PRE_LY2                  0x001C0A20
+#define I40E_GLANL_PRE_LY2                  0x001C0A20 /* Reset: CORER */
 #define I40E_GLANL_PRE_LY2_PRE_LY2_L2_SHIFT 0
 #define I40E_GLANL_PRE_LY2_PRE_LY2_L2_MASK  I40E_MASK(0xFFFF, I40E_GLANL_PRE_LY2_PRE_LY2_L2_SHIFT)
 
-#define I40E_GLPPRS_INDIRECT_ADDRESS            0x001C0A90
+#define I40E_GLPPRS_INDIRECT_ADDRESS            0x001C0A90 /* Reset: CORER */
 #define I40E_GLPPRS_INDIRECT_ADDRESS_ADDR_SHIFT 0
 #define I40E_GLPPRS_INDIRECT_ADDRESS_ADDR_MASK  I40E_MASK(0xFFFF, I40E_GLPPRS_INDIRECT_ADDRESS_ADDR_SHIFT)
 
-#define I40E_GLPPRS_INDIRECT_DATA(_i)        (0x001C0A94 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLPPRS_INDIRECT_DATA(_i)        (0x001C0A94 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPPRS_INDIRECT_DATA_MAX_INDEX  3
 #define I40E_GLPPRS_INDIRECT_DATA_DATA_SHIFT 0
 #define I40E_GLPPRS_INDIRECT_DATA_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPPRS_INDIRECT_DATA_DATA_SHIFT)
 
-#define I40E_GLRDPU_L2TAGCTRL(_i)             (0x00051020 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GLRDPU_L2TAGCTRL(_i)             (0x00051020 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GLRDPU_L2TAGCTRL_MAX_INDEX       7
 #define I40E_GLRDPU_L2TAGCTRL_LENGTH_SHIFT    0
 #define I40E_GLRDPU_L2TAGCTRL_LENGTH_MASK     I40E_MASK(0x7F, I40E_GLRDPU_L2TAGCTRL_LENGTH_SHIFT)
@@ -152,7 +152,7 @@
 #define I40E_GLRDPU_L2TAGCTRL_ETHERTYPE_SHIFT 16
 #define I40E_GLRDPU_L2TAGCTRL_ETHERTYPE_MASK  I40E_MASK(0xFFFF, I40E_GLRDPU_L2TAGCTRL_ETHERTYPE_SHIFT)
 
-#define I40E_GLTDPU_L2TAGCTRL(_i)             (0x00044204 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GLTDPU_L2TAGCTRL(_i)             (0x00044204 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GLTDPU_L2TAGCTRL_MAX_INDEX       7
 #define I40E_GLTDPU_L2TAGCTRL_LENGTH_SHIFT    0
 #define I40E_GLTDPU_L2TAGCTRL_LENGTH_MASK     I40E_MASK(0x7F, I40E_GLTDPU_L2TAGCTRL_LENGTH_SHIFT)
@@ -171,35 +171,35 @@
 #define I40E_GLTDPU_L2TAGCTRL_ETHERTYPE_SHIFT 16
 #define I40E_GLTDPU_L2TAGCTRL_ETHERTYPE_MASK  I40E_MASK(0xFFFF, I40E_GLTDPU_L2TAGCTRL_ETHERTYPE_SHIFT)
 
-#define I40E_GLTDPU_L2ULP(_i)             (0x00044224 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLTDPU_L2ULP(_i)             (0x00044224 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLTDPU_L2ULP_MAX_INDEX       15
 #define I40E_GLTDPU_L2ULP_ETHERTYPE_SHIFT 0
 #define I40E_GLTDPU_L2ULP_ETHERTYPE_MASK  I40E_MASK(0xFFFF, I40E_GLTDPU_L2ULP_ETHERTYPE_SHIFT)
 #define I40E_GLTDPU_L2ULP_ENABLE_SHIFT    31
 #define I40E_GLTDPU_L2ULP_ENABLE_MASK     I40E_MASK(0x1, I40E_GLTDPU_L2ULP_ENABLE_SHIFT)
 
-#define I40E_GLTDPU_PRE_LY2                  0x00044200
+#define I40E_GLTDPU_PRE_LY2                  0x00044200 /* Reset: CORER */
 #define I40E_GLTDPU_PRE_LY2_PRE_LY2_L2_SHIFT 0
 #define I40E_GLTDPU_PRE_LY2_PRE_LY2_L2_MASK  I40E_MASK(0xFFFF, I40E_GLTDPU_PRE_LY2_PRE_LY2_L2_SHIFT)
 
-#define I40E_PRT_PPRSL2TAGSEN              0x00087080
+#define I40E_PRT_PPRSL2TAGSEN              0x00087080 /* Reset: CORER */
 #define I40E_PRT_PPRSL2TAGSEN_ENABLE_SHIFT 0
 #define I40E_PRT_PPRSL2TAGSEN_ENABLE_MASK  I40E_MASK(0xFF, I40E_PRT_PPRSL2TAGSEN_ENABLE_SHIFT)
 
-#define I40E_PRT_TDPUL2TAGSEN              0x00044140
+#define I40E_PRT_TDPUL2TAGSEN              0x00044140 /* Reset: CORER */
 #define I40E_PRT_TDPUL2TAGSEN_ENABLE_SHIFT 0
 #define I40E_PRT_TDPUL2TAGSEN_ENABLE_MASK  I40E_MASK(0xFF, I40E_PRT_TDPUL2TAGSEN_ENABLE_SHIFT)
 
-#define I40E_PRTPPRS_INDIRECT_ADDRESS            0x00084320
+#define I40E_PRTPPRS_INDIRECT_ADDRESS            0x00084320 /* Reset: CORER */
 #define I40E_PRTPPRS_INDIRECT_ADDRESS_ADDR_SHIFT 0
 #define I40E_PRTPPRS_INDIRECT_ADDRESS_ADDR_MASK  I40E_MASK(0xFFFF, I40E_PRTPPRS_INDIRECT_ADDRESS_ADDR_SHIFT)
 
-#define I40E_PRTPPRS_INDIRECT_DATA(_i)        (0x00084340 + ((_i) * 32)) /* _i=0...3 */
+#define I40E_PRTPPRS_INDIRECT_DATA(_i)        (0x00084340 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_PRTPPRS_INDIRECT_DATA_MAX_INDEX  3
 #define I40E_PRTPPRS_INDIRECT_DATA_DATA_SHIFT 0
 #define I40E_PRTPPRS_INDIRECT_DATA_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTPPRS_INDIRECT_DATA_DATA_SHIFT)
 
-#define I40E_PRTPPRS_L2TAGCTRL(_i)             (0x00084020 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTPPRS_L2TAGCTRL(_i)             (0x00084020 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTPPRS_L2TAGCTRL_MAX_INDEX       7
 #define I40E_PRTPPRS_L2TAGCTRL_LENGTH_SHIFT    0
 #define I40E_PRTPPRS_L2TAGCTRL_LENGTH_MASK     I40E_MASK(0x7F, I40E_PRTPPRS_L2TAGCTRL_LENGTH_SHIFT)
@@ -218,18 +218,18 @@
 #define I40E_PRTPPRS_L2TAGCTRL_ETHERTYPE_SHIFT 16
 #define I40E_PRTPPRS_L2TAGCTRL_ETHERTYPE_MASK  I40E_MASK(0xFFFF, I40E_PRTPPRS_L2TAGCTRL_ETHERTYPE_SHIFT)
 
-#define I40E_PRTPPRS_L2ULP(_i)             (0x00084120 + ((_i) * 32)) /* _i=0...15 */
+#define I40E_PRTPPRS_L2ULP(_i)             (0x00084120 + ((_i) * 32)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_PRTPPRS_L2ULP_MAX_INDEX       15
 #define I40E_PRTPPRS_L2ULP_ETHERTYPE_SHIFT 0
 #define I40E_PRTPPRS_L2ULP_ETHERTYPE_MASK  I40E_MASK(0xFFFF, I40E_PRTPPRS_L2ULP_ETHERTYPE_SHIFT)
 #define I40E_PRTPPRS_L2ULP_ENABLE_SHIFT    31
 #define I40E_PRTPPRS_L2ULP_ENABLE_MASK     I40E_MASK(0x1, I40E_PRTPPRS_L2ULP_ENABLE_SHIFT)
 
-#define I40E_PRTPPRS_PRE_LY2                  0x00084000
+#define I40E_PRTPPRS_PRE_LY2                  0x00084000 /* Reset: CORER */
 #define I40E_PRTPPRS_PRE_LY2_PRE_LY2_L2_SHIFT 0
 #define I40E_PRTPPRS_PRE_LY2_PRE_LY2_L2_MASK  I40E_MASK(0xFFFF, I40E_PRTPPRS_PRE_LY2_PRE_LY2_L2_SHIFT)
 
-#define I40E_PRTPPRS_SIATH(_i)             (0x00085900 + ((_i) * 32)) /* _i=0...15 */
+#define I40E_PRTPPRS_SIATH(_i)             (0x00085900 + ((_i) * 32)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_PRTPPRS_SIATH_MAX_INDEX       15
 #define I40E_PRTPPRS_SIATH_ETHERTYPE_SHIFT 0
 #define I40E_PRTPPRS_SIATH_ETHERTYPE_MASK  I40E_MASK(0xFFFF, I40E_PRTPPRS_SIATH_ETHERTYPE_SHIFT)
@@ -238,7 +238,7 @@
 #define I40E_PRTPPRS_SIATH_VALID_SHIFT     31
 #define I40E_PRTPPRS_SIATH_VALID_MASK      I40E_MASK(0x1, I40E_PRTPPRS_SIATH_VALID_SHIFT)
 
-#define I40E_PRTPPRS_SIATL(_i)                (0x00085700 + ((_i) * 32)) /* _i=0...15 */
+#define I40E_PRTPPRS_SIATL(_i)                (0x00085700 + ((_i) * 32)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_PRTPPRS_SIATL_MAX_INDEX          15
 #define I40E_PRTPPRS_SIATL_GRE_PROTOCOL_SHIFT 0
 #define I40E_PRTPPRS_SIATL_GRE_PROTOCOL_MASK  I40E_MASK(0xFFFF, I40E_PRTPPRS_SIATL_GRE_PROTOCOL_SHIFT)
@@ -251,19 +251,19 @@
 
 /* PF - CM Registers */
 
-#define I40E_GLCM_LANCLSADDR                0x0010C444
+#define I40E_GLCM_LANCLSADDR                0x0010C444 /* Reset: CORER */
 #define I40E_GLCM_LANCLSADDR_CLS_ADDR_SHIFT 0
 #define I40E_GLCM_LANCLSADDR_CLS_ADDR_MASK  I40E_MASK(0x1FF, I40E_GLCM_LANCLSADDR_CLS_ADDR_SHIFT)
 
-#define I40E_GLCM_LANCLSDATAHI                   0x0010C44C
+#define I40E_GLCM_LANCLSDATAHI                   0x0010C44C /* Reset: CORER */
 #define I40E_GLCM_LANCLSDATAHI_CLS_DATA_HI_SHIFT 0
 #define I40E_GLCM_LANCLSDATAHI_CLS_DATA_HI_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLCM_LANCLSDATAHI_CLS_DATA_HI_SHIFT)
 
-#define I40E_GLCM_LANCLSDATALO                   0x0010C448
+#define I40E_GLCM_LANCLSDATALO                   0x0010C448 /* Reset: CORER */
 #define I40E_GLCM_LANCLSDATALO_CLS_DATA_LO_SHIFT 0
 #define I40E_GLCM_LANCLSDATALO_CLS_DATA_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLCM_LANCLSDATALO_CLS_DATA_LO_SHIFT)
 
-#define I40E_GLCM_LANCONFIG                            0x0010C430
+#define I40E_GLCM_LANCONFIG                            0x0010C430 /* Reset: CORER */
 #define I40E_GLCM_LANCONFIG_GLOBAL_LOCK_MODE_SHIFT     1
 #define I40E_GLCM_LANCONFIG_GLOBAL_LOCK_MODE_MASK      I40E_MASK(0x1, I40E_GLCM_LANCONFIG_GLOBAL_LOCK_MODE_SHIFT)
 #define I40E_GLCM_LANCONFIG_DISABLE_PACKET_COUNT_SHIFT 2
@@ -289,13 +289,13 @@
 #define I40E_GLCM_LANCONFIG_DBGMUX_EN_SHIFT            28
 #define I40E_GLCM_LANCONFIG_DBGMUX_EN_MASK             I40E_MASK(0x1, I40E_GLCM_LANCONFIG_DBGMUX_EN_SHIFT)
 
-#define I40E_GLCM_LANCRDTHR                   0x0010C41C
+#define I40E_GLCM_LANCRDTHR                   0x0010C41C /* Reset: CORER */
 #define I40E_GLCM_LANCRDTHR_CMLANCRDTHR_SHIFT 0
 #define I40E_GLCM_LANCRDTHR_CMLANCRDTHR_MASK  I40E_MASK(0x3FFF, I40E_GLCM_LANCRDTHR_CMLANCRDTHR_SHIFT)
 #define I40E_GLCM_LANCRDTHR_CMLANTCBTHR_SHIFT 16
 #define I40E_GLCM_LANCRDTHR_CMLANTCBTHR_MASK  I40E_MASK(0x7F, I40E_GLCM_LANCRDTHR_CMLANTCBTHR_SHIFT)
 
-#define I40E_GLCM_LANCTXDGCTL                  0x0010C410
+#define I40E_GLCM_LANCTXDGCTL                  0x0010C410 /* Reset: CORER */
 #define I40E_GLCM_LANCTXDGCTL_QUEUE_NUM_SHIFT  0
 #define I40E_GLCM_LANCTXDGCTL_QUEUE_NUM_MASK   I40E_MASK(0xFFF, I40E_GLCM_LANCTXDGCTL_QUEUE_NUM_SHIFT)
 #define I40E_GLCM_LANCTXDGCTL_SUB_LINE_SHIFT   12
@@ -313,12 +313,12 @@
 #define I40E_GLCM_LANCTXDGCTL_ALLOCATE_SHIFT   23
 #define I40E_GLCM_LANCTXDGCTL_ALLOCATE_MASK    I40E_MASK(0x1, I40E_GLCM_LANCTXDGCTL_ALLOCATE_SHIFT)
 
-#define I40E_GLCM_LANCTXDGDATA(_i)        (0x0010C400 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLCM_LANCTXDGDATA(_i)        (0x0010C400 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLCM_LANCTXDGDATA_MAX_INDEX  3
 #define I40E_GLCM_LANCTXDGDATA_DATA_SHIFT 0
 #define I40E_GLCM_LANCTXDGDATA_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLCM_LANCTXDGDATA_DATA_SHIFT)
 
-#define I40E_GLCM_LANCTXDGFN                  0x0010C418
+#define I40E_GLCM_LANCTXDGFN                  0x0010C418 /* Reset: CORER */
 #define I40E_GLCM_LANCTXDGFN_PF_NUM_SHIFT     0
 #define I40E_GLCM_LANCTXDGFN_PF_NUM_MASK      I40E_MASK(0xF, I40E_GLCM_LANCTXDGFN_PF_NUM_SHIFT)
 #define I40E_GLCM_LANCTXDGFN_VM_VF_NUM_SHIFT  4
@@ -326,39 +326,39 @@
 #define I40E_GLCM_LANCTXDGFN_VM_VF_TYPE_SHIFT 16
 #define I40E_GLCM_LANCTXDGFN_VM_VF_TYPE_MASK  I40E_MASK(0x3, I40E_GLCM_LANCTXDGFN_VM_VF_TYPE_SHIFT)
 
-#define I40E_GLCM_LANCTXDGSTAT                0x0010C414
+#define I40E_GLCM_LANCTXDGSTAT                0x0010C414 /* Reset: CORER */
 #define I40E_GLCM_LANCTXDGSTAT_CTX_DONE_SHIFT 0
 #define I40E_GLCM_LANCTXDGSTAT_CTX_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LANCTXDGSTAT_CTX_DONE_SHIFT)
 #define I40E_GLCM_LANCTXDGSTAT_CTX_MISS_SHIFT 1
 #define I40E_GLCM_LANCTXDGSTAT_CTX_MISS_MASK  I40E_MASK(0x1, I40E_GLCM_LANCTXDGSTAT_CTX_MISS_SHIFT)
 
-#define I40E_GLCM_LANDATAREQHI                      0x0010C478
+#define I40E_GLCM_LANDATAREQHI                      0x0010C478 /* Reset: CORER */
 #define I40E_GLCM_LANDATAREQHI_CMLANDATAREQHI_SHIFT 0
 #define I40E_GLCM_LANDATAREQHI_CMLANDATAREQHI_MASK  I40E_MASK(0xFFFFFF, I40E_GLCM_LANDATAREQHI_CMLANDATAREQHI_SHIFT)
 
-#define I40E_GLCM_LANDATAREQLOW                       0x0010C474
+#define I40E_GLCM_LANDATAREQLOW                       0x0010C474 /* Reset: CORER */
 #define I40E_GLCM_LANDATAREQLOW_CMLANDATAREQLOW_SHIFT 0
 #define I40E_GLCM_LANDATAREQLOW_CMLANDATAREQLOW_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLCM_LANDATAREQLOW_CMLANDATAREQLOW_SHIFT)
 
-#define I40E_GLCM_LANDATASTALLHI                        0x0010C480
+#define I40E_GLCM_LANDATASTALLHI                        0x0010C480 /* Reset: CORER */
 #define I40E_GLCM_LANDATASTALLHI_CMLANDATASTALLHI_SHIFT 0
 #define I40E_GLCM_LANDATASTALLHI_CMLANDATASTALLHI_MASK  I40E_MASK(0xFFFFFF, I40E_GLCM_LANDATASTALLHI_CMLANDATASTALLHI_SHIFT)
 
-#define I40E_GLCM_LANDATASTALLLO                         0x0010C47C
+#define I40E_GLCM_LANDATASTALLLO                         0x0010C47C /* Reset: CORER */
 #define I40E_GLCM_LANDATASTALLLO_CMLANDATASTALLLOW_SHIFT 0
 #define I40E_GLCM_LANDATASTALLLO_CMLANDATASTALLLOW_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLCM_LANDATASTALLLO_CMLANDATASTALLLOW_SHIFT)
 
-#define I40E_GLCM_LANLOCKTBLADDR                    0x0010C458
+#define I40E_GLCM_LANLOCKTBLADDR                    0x0010C458 /* Reset: CORER */
 #define I40E_GLCM_LANLOCKTBLADDR_LOCKTBL_ADDR_SHIFT 0
 #define I40E_GLCM_LANLOCKTBLADDR_LOCKTBL_ADDR_MASK  I40E_MASK(0xF, I40E_GLCM_LANLOCKTBLADDR_LOCKTBL_ADDR_SHIFT)
 
-#define I40E_GLCM_LANLOCKTBLDATAHI                 0x0010C460
+#define I40E_GLCM_LANLOCKTBLDATAHI                 0x0010C460 /* Reset: CORER */
 #define I40E_GLCM_LANLOCKTBLDATAHI_LOCKSEL_SHIFT   0
 #define I40E_GLCM_LANLOCKTBLDATAHI_LOCKSEL_MASK    I40E_MASK(0xFF, I40E_GLCM_LANLOCKTBLDATAHI_LOCKSEL_SHIFT)
 #define I40E_GLCM_LANLOCKTBLDATAHI_GPLOCKSEL_SHIFT 8
 #define I40E_GLCM_LANLOCKTBLDATAHI_GPLOCKSEL_MASK  I40E_MASK(0xF, I40E_GLCM_LANLOCKTBLDATAHI_GPLOCKSEL_SHIFT)
 
-#define I40E_GLCM_LANLOCKTBLDATALO                  0x0010C45C
+#define I40E_GLCM_LANLOCKTBLDATALO                  0x0010C45C /* Reset: CORER */
 #define I40E_GLCM_LANLOCKTBLDATALO_QNUM_SHIFT       0
 #define I40E_GLCM_LANLOCKTBLDATALO_QNUM_MASK        I40E_MASK(0xFFF, I40E_GLCM_LANLOCKTBLDATALO_QNUM_SHIFT)
 #define I40E_GLCM_LANLOCKTBLDATALO_PF_NUM_SHIFT     12
@@ -368,19 +368,19 @@
 #define I40E_GLCM_LANLOCKTBLDATALO_VM_VF_TYPE_SHIFT 25
 #define I40E_GLCM_LANLOCKTBLDATALO_VM_VF_TYPE_MASK  I40E_MASK(0x3, I40E_GLCM_LANLOCKTBLDATALO_VM_VF_TYPE_SHIFT)
 
-#define I40E_GLCM_LANMISSREQHI                      0x0010C488
+#define I40E_GLCM_LANMISSREQHI                      0x0010C488 /* Reset: CORER */
 #define I40E_GLCM_LANMISSREQHI_CMLANMISSREQHI_SHIFT 0
 #define I40E_GLCM_LANMISSREQHI_CMLANMISSREQHI_MASK  I40E_MASK(0xFFFFFF, I40E_GLCM_LANMISSREQHI_CMLANMISSREQHI_SHIFT)
 
-#define I40E_GLCM_LANMISSREQLO                       0x0010C484
+#define I40E_GLCM_LANMISSREQLO                       0x0010C484 /* Reset: CORER */
 #define I40E_GLCM_LANMISSREQLO_CMLANMISSREQLOW_SHIFT 0
 #define I40E_GLCM_LANMISSREQLO_CMLANMISSREQLOW_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLCM_LANMISSREQLO_CMLANMISSREQLOW_SHIFT)
 
-#define I40E_GLCM_LANPKTCNTADDR                   0x0010C450
+#define I40E_GLCM_LANPKTCNTADDR                   0x0010C450 /* Reset: CORER */
 #define I40E_GLCM_LANPKTCNTADDR_PKTCNT_ADDR_SHIFT 0
 #define I40E_GLCM_LANPKTCNTADDR_PKTCNT_ADDR_MASK  I40E_MASK(0x1FF, I40E_GLCM_LANPKTCNTADDR_PKTCNT_ADDR_SHIFT)
 
-#define I40E_GLCM_LANPKTCNTDATA               0x0010C454
+#define I40E_GLCM_LANPKTCNTDATA               0x0010C454 /* Reset: CORER */
 #define I40E_GLCM_LANPKTCNTDATA_DONE_SHIFT    0
 #define I40E_GLCM_LANPKTCNTDATA_DONE_MASK     I40E_MASK(0x1, I40E_GLCM_LANPKTCNTDATA_DONE_SHIFT)
 #define I40E_GLCM_LANPKTCNTDATA_PKTCNT_SHIFT  1
@@ -388,69 +388,69 @@
 #define I40E_GLCM_LANPKTCNTDATA_RLSTATE_SHIFT 12
 #define I40E_GLCM_LANPKTCNTDATA_RLSTATE_MASK  I40E_MASK(0x3, I40E_GLCM_LANPKTCNTDATA_RLSTATE_SHIFT)
 
-#define I40E_GLCM_LANRLADDR               0x0010C43C
+#define I40E_GLCM_LANRLADDR               0x0010C43C /* Reset: CORER */
 #define I40E_GLCM_LANRLADDR_RL_ADDR_SHIFT 0
 #define I40E_GLCM_LANRLADDR_RL_ADDR_MASK  I40E_MASK(0xFFF, I40E_GLCM_LANRLADDR_RL_ADDR_SHIFT)
 
-#define I40E_GLCM_LANRLDATA               0x0010C440
+#define I40E_GLCM_LANRLDATA               0x0010C440 /* Reset: CORER */
 #define I40E_GLCM_LANRLDATA_RL_DATA_SHIFT 0
 #define I40E_GLCM_LANRLDATA_RL_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLCM_LANRLDATA_RL_DATA_SHIFT)
 
-#define I40E_GLCM_LANRLQUERY(_i)           (0x0010C420 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GLCM_LANRLQUERY(_i)           (0x0010C420 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GLCM_LANRLQUERY_MAX_INDEX     1
 #define I40E_GLCM_LANRLQUERY_RLINDEX_SHIFT 0
 #define I40E_GLCM_LANRLQUERY_RLINDEX_MASK  I40E_MASK(0x3FF, I40E_GLCM_LANRLQUERY_RLINDEX_SHIFT)
 
-#define I40E_GLCM_LANRLSTAT(_i)              (0x0010C428 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GLCM_LANRLSTAT(_i)              (0x0010C428 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GLCM_LANRLSTAT_MAX_INDEX        1
 #define I40E_GLCM_LANRLSTAT_QUERY_DONE_SHIFT 0
 #define I40E_GLCM_LANRLSTAT_QUERY_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LANRLSTAT_QUERY_DONE_SHIFT)
 #define I40E_GLCM_LANRLSTAT_RL_EMPTY_SHIFT   1
 #define I40E_GLCM_LANRLSTAT_RL_EMPTY_MASK    I40E_MASK(0x1, I40E_GLCM_LANRLSTAT_RL_EMPTY_SHIFT)
 
-#define I40E_GLCM_LANSNOOPREQHI                       0x0010C468
+#define I40E_GLCM_LANSNOOPREQHI                       0x0010C468 /* Reset: CORER */
 #define I40E_GLCM_LANSNOOPREQHI_CMLANSNOOPREQHI_SHIFT 0
 #define I40E_GLCM_LANSNOOPREQHI_CMLANSNOOPREQHI_MASK  I40E_MASK(0xFFFFFF, I40E_GLCM_LANSNOOPREQHI_CMLANSNOOPREQHI_SHIFT)
 
-#define I40E_GLCM_LANSNOOPREQLO                        0x0010C464
+#define I40E_GLCM_LANSNOOPREQLO                        0x0010C464 /* Reset: CORER */
 #define I40E_GLCM_LANSNOOPREQLO_CMLANSNOOPREQLOW_SHIFT 0
 #define I40E_GLCM_LANSNOOPREQLO_CMLANSNOOPREQLOW_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLCM_LANSNOOPREQLO_CMLANSNOOPREQLOW_SHIFT)
 
-#define I40E_GLCM_LANSNOOPSTALLHI                         0x0010C470
+#define I40E_GLCM_LANSNOOPSTALLHI                         0x0010C470 /* Reset: CORER */
 #define I40E_GLCM_LANSNOOPSTALLHI_CMLANSNOOPSTALLHI_SHIFT 0
 #define I40E_GLCM_LANSNOOPSTALLHI_CMLANSNOOPSTALLHI_MASK  I40E_MASK(0xFFFFFF, I40E_GLCM_LANSNOOPSTALLHI_CMLANSNOOPSTALLHI_SHIFT)
 
-#define I40E_GLCM_LANSNOOPSTALLLO                          0x0010C46C
+#define I40E_GLCM_LANSNOOPSTALLLO                          0x0010C46C /* Reset: CORER */
 #define I40E_GLCM_LANSNOOPSTALLLO_CMLANSNOOPSTALLLOW_SHIFT 0
 #define I40E_GLCM_LANSNOOPSTALLLO_CMLANSNOOPSTALLLOW_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLCM_LANSNOOPSTALLLO_CMLANSNOOPSTALLLOW_SHIFT)
 
 /* PF - DCB Registers  */
 
-#define I40E_GLDCB_PACER                 0x000A2210
+#define I40E_GLDCB_PACER                 0x000A2210 /* Reset: CORER */
 #define I40E_GLDCB_PACER_PACER_VAL_SHIFT 0
 #define I40E_GLDCB_PACER_PACER_VAL_MASK  I40E_MASK(0x3FFFFFF, I40E_GLDCB_PACER_PACER_VAL_SHIFT)
 #define I40E_GLDCB_PACER_PACER_EN_SHIFT  31
 #define I40E_GLDCB_PACER_PACER_EN_MASK   I40E_MASK(0x1, I40E_GLDCB_PACER_PACER_EN_SHIFT)
 
-#define I40E_GLDCB_PCI_DATA                   0x000A0150
+#define I40E_GLDCB_PCI_DATA                   0x000A0150 /* Reset: CORER */
 #define I40E_GLDCB_PCI_DATA_PCI_DATA_BC_SHIFT 0
 #define I40E_GLDCB_PCI_DATA_PCI_DATA_BC_MASK  I40E_MASK(0xFFFFF, I40E_GLDCB_PCI_DATA_PCI_DATA_BC_SHIFT)
 
-#define I40E_GLDCB_RLLPC                 0x0005105C
+#define I40E_GLDCB_RLLPC                 0x0005105C /* Reset: CORER */
 #define I40E_GLDCB_RLLPC_LLMAXPCNT_SHIFT 0
 #define I40E_GLDCB_RLLPC_LLMAXPCNT_MASK  I40E_MASK(0xFFFF, I40E_GLDCB_RLLPC_LLMAXPCNT_SHIFT)
 #define I40E_GLDCB_RLLPC_BMAXPCNT_SHIFT  16
 #define I40E_GLDCB_RLLPC_BMAXPCNT_MASK   I40E_MASK(0xFFFF, I40E_GLDCB_RLLPC_BMAXPCNT_SHIFT)
 
-#define I40E_GLDCB_RLLPSB             0x00051054
+#define I40E_GLDCB_RLLPSB             0x00051054 /* Reset: CORER */
 #define I40E_GLDCB_RLLPSB_BPCNT_SHIFT 0
 #define I40E_GLDCB_RLLPSB_BPCNT_MASK  I40E_MASK(0x3FFFFFF, I40E_GLDCB_RLLPSB_BPCNT_SHIFT)
 
-#define I40E_GLDCB_RLLPSLL              0x00051058
+#define I40E_GLDCB_RLLPSLL              0x00051058 /* Reset: CORER */
 #define I40E_GLDCB_RLLPSLL_LLPCNT_SHIFT 0
 #define I40E_GLDCB_RLLPSLL_LLPCNT_MASK  I40E_MASK(0x3FFFFFF, I40E_GLDCB_RLLPSLL_LLPCNT_SHIFT)
 
-#define I40E_GLDCB_RMPMC                       0x00122610
+#define I40E_GLDCB_RMPMC                       0x00122610 /* Reset: CORER */
 #define I40E_GLDCB_RMPMC_RSPM_SHIFT            0
 #define I40E_GLDCB_RMPMC_RSPM_MASK             I40E_MASK(0x3F, I40E_GLDCB_RMPMC_RSPM_SHIFT)
 #define I40E_GLDCB_RMPMC_MIQ_NODROP_MODE_SHIFT 6
@@ -458,23 +458,23 @@
 #define I40E_GLDCB_RMPMC_RPM_DIS_SHIFT         31
 #define I40E_GLDCB_RMPMC_RPM_DIS_MASK          I40E_MASK(0x1, I40E_GLDCB_RMPMC_RPM_DIS_SHIFT)
 
-#define I40E_GLDCB_RMPMS            0x00122614
+#define I40E_GLDCB_RMPMS            0x00122614 /* Reset: CORER */
 #define I40E_GLDCB_RMPMS_RMPM_SHIFT 0
 #define I40E_GLDCB_RMPMS_RMPM_MASK  I40E_MASK(0xFFFF, I40E_GLDCB_RMPMS_RMPM_SHIFT)
 
-#define I40E_GLDCB_RPRRD0                   0x00122608
+#define I40E_GLDCB_RPRRD0                   0x00122608 /* Reset: CORER */
 #define I40E_GLDCB_RPRRD0_BWSHARE_40G_SHIFT 0
 #define I40E_GLDCB_RPRRD0_BWSHARE_40G_MASK  I40E_MASK(0x3FF, I40E_GLDCB_RPRRD0_BWSHARE_40G_SHIFT)
 #define I40E_GLDCB_RPRRD0_BWSHARE_10G_SHIFT 16
 #define I40E_GLDCB_RPRRD0_BWSHARE_10G_MASK  I40E_MASK(0x3FF, I40E_GLDCB_RPRRD0_BWSHARE_10G_SHIFT)
 
-#define I40E_GLDCB_RPRRD1                    0x0012260C
+#define I40E_GLDCB_RPRRD1                    0x0012260C /* Reset: CORER */
 #define I40E_GLDCB_RPRRD1_BWSHARE_1G_SHIFT   0
 #define I40E_GLDCB_RPRRD1_BWSHARE_1G_MASK    I40E_MASK(0x3FF, I40E_GLDCB_RPRRD1_BWSHARE_1G_SHIFT)
 #define I40E_GLDCB_RPRRD1_BWSHARE_100M_SHIFT 16
 #define I40E_GLDCB_RPRRD1_BWSHARE_100M_MASK  I40E_MASK(0x3FF, I40E_GLDCB_RPRRD1_BWSHARE_100M_SHIFT)
 
-#define I40E_GLDCB_RSPMC                   0x00122604
+#define I40E_GLDCB_RSPMC                   0x00122604 /* Reset: CORER */
 #define I40E_GLDCB_RSPMC_RSPM_SHIFT        0
 #define I40E_GLDCB_RSPMC_RSPM_MASK         I40E_MASK(0xFF, I40E_GLDCB_RSPMC_RSPM_SHIFT)
 #define I40E_GLDCB_RSPMC_RPM_MODE_SHIFT    8
@@ -486,15 +486,15 @@
 #define I40E_GLDCB_RSPMC_RPM_DIS_SHIFT     31
 #define I40E_GLDCB_RSPMC_RPM_DIS_MASK      I40E_MASK(0x1, I40E_GLDCB_RSPMC_RPM_DIS_SHIFT)
 
-#define I40E_GLDCB_RSPMS            0x00122600
+#define I40E_GLDCB_RSPMS            0x00122600 /* Reset: CORER */
 #define I40E_GLDCB_RSPMS_RSPM_SHIFT 0
 #define I40E_GLDCB_RSPMS_RSPM_MASK  I40E_MASK(0x3FFFF, I40E_GLDCB_RSPMS_RSPM_SHIFT)
 
-#define I40E_GLDCB_TFPFCI                 0x00098080
+#define I40E_GLDCB_TFPFCI                 0x00098080 /* Reset: CORER */
 #define I40E_GLDCB_TFPFCI_IGNORE_FC_SHIFT 0
 #define I40E_GLDCB_TFPFCI_IGNORE_FC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLDCB_TFPFCI_IGNORE_FC_SHIFT)
 
-#define I40E_GLDCB_TGENC_TLPM                         0x000A01C0
+#define I40E_GLDCB_TGENC_TLPM                         0x000A01C0 /* Reset: CORER */
 #define I40E_GLDCB_TGENC_TLPM_ALLOFFTH_SHIFT          0
 #define I40E_GLDCB_TGENC_TLPM_ALLOFFTH_MASK           I40E_MASK(0xFF, I40E_GLDCB_TGENC_TLPM_ALLOFFTH_SHIFT)
 #define I40E_GLDCB_TGENC_TLPM_SHARED_TDATATH_SHIFT    8
@@ -506,7 +506,7 @@
 #define I40E_GLDCB_TGENC_TLPM_FWLB_MODE_SHIFT         31
 #define I40E_GLDCB_TGENC_TLPM_FWLB_MODE_MASK          I40E_MASK(0x1, I40E_GLDCB_TGENC_TLPM_FWLB_MODE_SHIFT)
 
-#define I40E_GLDCB_TGENC_TUPM                 0x000A2200
+#define I40E_GLDCB_TGENC_TUPM                 0x000A2200 /* Reset: CORER */
 #define I40E_GLDCB_TGENC_TUPM_ALLOFFTH_SHIFT  0
 #define I40E_GLDCB_TGENC_TUPM_ALLOFFTH_MASK   I40E_MASK(0x1FFF, I40E_GLDCB_TGENC_TUPM_ALLOFFTH_SHIFT)
 #define I40E_GLDCB_TGENC_TUPM_TCPM_DIS_SHIFT  30
@@ -514,50 +514,50 @@
 #define I40E_GLDCB_TGENC_TUPM_CWLB_MODE_SHIFT 31
 #define I40E_GLDCB_TGENC_TUPM_CWLB_MODE_MASK  I40E_MASK(0x1, I40E_GLDCB_TGENC_TUPM_CWLB_MODE_SHIFT)
 
-#define I40E_PRTDCB_FCAH             0x001E24C0
+#define I40E_PRTDCB_FCAH             0x001E24C0 /* Reset: GLOBR */
 #define I40E_PRTDCB_FCAH_PFCAH_SHIFT 0
 #define I40E_PRTDCB_FCAH_PFCAH_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_FCAH_PFCAH_SHIFT)
 
-#define I40E_PRTDCB_FCAL             0x001E24A0
+#define I40E_PRTDCB_FCAL             0x001E24A0 /* Reset: GLOBR */
 #define I40E_PRTDCB_FCAL_PFCAL_SHIFT 0
 #define I40E_PRTDCB_FCAL_PFCAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTDCB_FCAL_PFCAL_SHIFT)
 
-#define I40E_PRTDCB_RETSTCS(_i)           (0x001222A0 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTDCB_RETSTCS(_i)           (0x001222A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTDCB_RETSTCS_MAX_INDEX     7
 #define I40E_PRTDCB_RETSTCS_CREDITS_SHIFT 0
 #define I40E_PRTDCB_RETSTCS_CREDITS_MASK  I40E_MASK(0x1FFFFFFF, I40E_PRTDCB_RETSTCS_CREDITS_SHIFT)
 
-#define I40E_PRTDCB_RLANPMS               0x001223C0
+#define I40E_PRTDCB_RLANPMS               0x001223C0 /* Reset: CORER */
 #define I40E_PRTDCB_RLANPMS_LANRPPM_SHIFT 0
 #define I40E_PRTDCB_RLANPMS_LANRPPM_MASK  I40E_MASK(0x3FFFF, I40E_PRTDCB_RLANPMS_LANRPPM_SHIFT)
 
-#define I40E_PRTDCB_RPFCTOP                 0x001E2480
+#define I40E_PRTDCB_RPFCTOP                 0x001E2480 /* Reset: GLOBR */
 #define I40E_PRTDCB_RPFCTOP_PFCTYPE_SHIFT   0
 #define I40E_PRTDCB_RPFCTOP_PFCTYPE_MASK    I40E_MASK(0xFFFF, I40E_PRTDCB_RPFCTOP_PFCTYPE_SHIFT)
 #define I40E_PRTDCB_RPFCTOP_PFCOPCODE_SHIFT 16
 #define I40E_PRTDCB_RPFCTOP_PFCOPCODE_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_RPFCTOP_PFCOPCODE_SHIFT)
 
-#define I40E_PRTDCB_RPRRC               0x00122100
+#define I40E_PRTDCB_RPRRC               0x00122100 /* Reset: CORER */
 #define I40E_PRTDCB_RPRRC_BWSHARE_SHIFT 0
 #define I40E_PRTDCB_RPRRC_BWSHARE_MASK  I40E_MASK(0x3FF, I40E_PRTDCB_RPRRC_BWSHARE_SHIFT)
 
-#define I40E_PRTDCB_RPRRS               0x00122120
+#define I40E_PRTDCB_RPRRS               0x00122120 /* Reset: CORER */
 #define I40E_PRTDCB_RPRRS_CREDITS_SHIFT 0
 #define I40E_PRTDCB_RPRRS_CREDITS_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTDCB_RPRRS_CREDITS_SHIFT)
 
-#define I40E_PRTDCB_RRDMAPMS                0x00122160
+#define I40E_PRTDCB_RRDMAPMS                0x00122160 /* Reset: CORER */
 #define I40E_PRTDCB_RRDMAPMS_RDMARPPM_SHIFT 0
 #define I40E_PRTDCB_RRDMAPMS_RDMARPPM_MASK  I40E_MASK(0x3FFFF, I40E_PRTDCB_RRDMAPMS_RDMARPPM_SHIFT)
 
-#define I40E_PRTDCB_RUP_PPRS                0x000844C0
+#define I40E_PRTDCB_RUP_PPRS                0x000844C0 /* Reset: CORER */
 #define I40E_PRTDCB_RUP_PPRS_NOVLANUP_SHIFT 0
 #define I40E_PRTDCB_RUP_PPRS_NOVLANUP_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP_PPRS_NOVLANUP_SHIFT)
 
-#define I40E_PRTDCB_RUP_TDPU                0x00044120
+#define I40E_PRTDCB_RUP_TDPU                0x00044120 /* Reset: CORER */
 #define I40E_PRTDCB_RUP_TDPU_NOVLANUP_SHIFT 0
 #define I40E_PRTDCB_RUP_TDPU_NOVLANUP_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP_TDPU_NOVLANUP_SHIFT)
 
-#define I40E_PRTDCB_RUP2TC_RCB             0x00122280
+#define I40E_PRTDCB_RUP2TC_RCB             0x00122280 /* Reset: CORER */
 #define I40E_PRTDCB_RUP2TC_RCB_UP0TC_SHIFT 0
 #define I40E_PRTDCB_RUP2TC_RCB_UP0TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_RCB_UP0TC_SHIFT)
 #define I40E_PRTDCB_RUP2TC_RCB_UP1TC_SHIFT 3
@@ -575,39 +575,39 @@
 #define I40E_PRTDCB_RUP2TC_RCB_UP7TC_SHIFT 21
 #define I40E_PRTDCB_RUP2TC_RCB_UP7TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_RCB_UP7TC_SHIFT)
 
-#define I40E_PRTDCB_RUPTQ(_i)          (0x00122400 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTDCB_RUPTQ(_i)          (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTDCB_RUPTQ_MAX_INDEX    7
 #define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0
 #define I40E_PRTDCB_RUPTQ_RXQNUM_MASK  I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)
 
-#define I40E_PRTDCB_RUPTS(_i)            (0x00122500 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTDCB_RUPTS(_i)            (0x00122500 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTDCB_RUPTS_MAX_INDEX      7
 #define I40E_PRTDCB_RUPTS_PFCTIMER_SHIFT 0
 #define I40E_PRTDCB_RUPTS_PFCTIMER_MASK  I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTS_PFCTIMER_SHIFT)
 
-#define I40E_PRTDCB_TC2PFC_RCB              0x00122140
+#define I40E_PRTDCB_TC2PFC_RCB              0x00122140 /* Reset: CORER */
 #define I40E_PRTDCB_TC2PFC_RCB_TC2PFC_SHIFT 0
 #define I40E_PRTDCB_TC2PFC_RCB_TC2PFC_MASK  I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_RCB_TC2PFC_SHIFT)
 
-#define I40E_PRTDCB_TCLLPC                 0x000AE000
+#define I40E_PRTDCB_TCLLPC                 0x000AE000 /* Reset: CORER */
 #define I40E_PRTDCB_TCLLPC_LLMAXPCNT_SHIFT 0
 #define I40E_PRTDCB_TCLLPC_LLMAXPCNT_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_TCLLPC_LLMAXPCNT_SHIFT)
 #define I40E_PRTDCB_TCLLPC_BMAXPCNT_SHIFT  16
 #define I40E_PRTDCB_TCLLPC_BMAXPCNT_MASK   I40E_MASK(0xFFFF, I40E_PRTDCB_TCLLPC_BMAXPCNT_SHIFT)
 
-#define I40E_PRTDCB_TCLLPSB             0x000AE020
+#define I40E_PRTDCB_TCLLPSB             0x000AE020 /* Reset: CORER */
 #define I40E_PRTDCB_TCLLPSB_BPCNT_SHIFT 0
 #define I40E_PRTDCB_TCLLPSB_BPCNT_MASK  I40E_MASK(0x3FFFFFF, I40E_PRTDCB_TCLLPSB_BPCNT_SHIFT)
 
-#define I40E_PRTDCB_TCLLPSLL              0x000AE040
+#define I40E_PRTDCB_TCLLPSLL              0x000AE040 /* Reset: CORER */
 #define I40E_PRTDCB_TCLLPSLL_LLPCNT_SHIFT 0
 #define I40E_PRTDCB_TCLLPSLL_LLPCNT_MASK  I40E_MASK(0x3FFFFFF, I40E_PRTDCB_TCLLPSLL_LLPCNT_SHIFT)
 
-#define I40E_PRTDCB_TCPFCPC                 0x000A21C0
+#define I40E_PRTDCB_TCPFCPC                 0x000A21C0 /* Reset: CORER */
 #define I40E_PRTDCB_TCPFCPC_PORTOFFTH_SHIFT 0
 #define I40E_PRTDCB_TCPFCPC_PORTOFFTH_MASK  I40E_MASK(0x1FFF, I40E_PRTDCB_TCPFCPC_PORTOFFTH_SHIFT)
 
-#define I40E_PRTDCB_TCPFCTCC                    0x000A21E0
+#define I40E_PRTDCB_TCPFCTCC                    0x000A21E0 /* Reset: CORER */
 #define I40E_PRTDCB_TCPFCTCC_TCOFFTH_SHIFT      0
 #define I40E_PRTDCB_TCPFCTCC_TCOFFTH_MASK       I40E_MASK(0x1FFF, I40E_PRTDCB_TCPFCTCC_TCOFFTH_SHIFT)
 #define I40E_PRTDCB_TCPFCTCC_LL_PRI_TRESH_SHIFT 13
@@ -615,15 +615,15 @@
 #define I40E_PRTDCB_TCPFCTCC_LL_PRI_EN_SHIFT    31
 #define I40E_PRTDCB_TCPFCTCC_LL_PRI_EN_MASK     I40E_MASK(0x1, I40E_PRTDCB_TCPFCTCC_LL_PRI_EN_SHIFT)
 
-#define I40E_PRTDCB_TCWSP              0x000A2160
+#define I40E_PRTDCB_TCWSP              0x000A2160 /* Reset: CORER */
 #define I40E_PRTDCB_TCWSP_WSPORT_SHIFT 0
 #define I40E_PRTDCB_TCWSP_WSPORT_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSP_WSPORT_SHIFT)
 
-#define I40E_PRTDCB_TDPMS           0x000A0000
+#define I40E_PRTDCB_TDPMS           0x000A0000 /* Reset: CORER */
 #define I40E_PRTDCB_TDPMS_DPM_SHIFT 0
 #define I40E_PRTDCB_TDPMS_DPM_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TDPMS_DPM_SHIFT)
 
-#define I40E_PRTDCB_TDPUC                   0x00044100
+#define I40E_PRTDCB_TDPUC                   0x00044100 /* Reset: CORER */
 #define I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT 0
 #define I40E_PRTDCB_TDPUC_MAX_TXFRAME_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT)
 #define I40E_PRTDCB_TDPUC_MAL_LENGTH_SHIFT  16
@@ -637,49 +637,49 @@
 #define I40E_PRTDCB_TDPUC_CLEAR_DROP_SHIFT  31
 #define I40E_PRTDCB_TDPUC_CLEAR_DROP_MASK   I40E_MASK(0x1, I40E_PRTDCB_TDPUC_CLEAR_DROP_SHIFT)
 
-#define I40E_PRTDCB_TFLLPC                 0x00098000
+#define I40E_PRTDCB_TFLLPC                 0x00098000 /* Reset: CORER */
 #define I40E_PRTDCB_TFLLPC_LLMAXPCNT_SHIFT 0
 #define I40E_PRTDCB_TFLLPC_LLMAXPCNT_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_TFLLPC_LLMAXPCNT_SHIFT)
 #define I40E_PRTDCB_TFLLPC_BMAXPCNT_SHIFT  16
 #define I40E_PRTDCB_TFLLPC_BMAXPCNT_MASK   I40E_MASK(0xFFFF, I40E_PRTDCB_TFLLPC_BMAXPCNT_SHIFT)
 
-#define I40E_PRTDCB_TFLLPSB             0x00098020
+#define I40E_PRTDCB_TFLLPSB             0x00098020 /* Reset: CORER */
 #define I40E_PRTDCB_TFLLPSB_BPCNT_SHIFT 0
 #define I40E_PRTDCB_TFLLPSB_BPCNT_MASK  I40E_MASK(0x3FFFFFF, I40E_PRTDCB_TFLLPSB_BPCNT_SHIFT)
 
-#define I40E_PRTDCB_TFLLPSLL              0x00098040
+#define I40E_PRTDCB_TFLLPSLL              0x00098040 /* Reset: CORER */
 #define I40E_PRTDCB_TFLLPSLL_LLPCNT_SHIFT 0
 #define I40E_PRTDCB_TFLLPSLL_LLPCNT_MASK  I40E_MASK(0x3FFFFFF, I40E_PRTDCB_TFLLPSLL_LLPCNT_SHIFT)
 
-#define I40E_PRTDCB_TFPFCC                 0x000A01A0
+#define I40E_PRTDCB_TFPFCC                 0x000A01A0 /* Reset: CORER */
 #define I40E_PRTDCB_TFPFCC_PORTOFFTH_SHIFT 0
 #define I40E_PRTDCB_TFPFCC_PORTOFFTH_MASK  I40E_MASK(0xFF, I40E_PRTDCB_TFPFCC_PORTOFFTH_SHIFT)
 #define I40E_PRTDCB_TFPFCC_TCOFFTH_SHIFT   8
 #define I40E_PRTDCB_TFPFCC_TCOFFTH_MASK    I40E_MASK(0xFF, I40E_PRTDCB_TFPFCC_TCOFFTH_SHIFT)
 
-#define I40E_PRTDCB_TFWSP              0x000A0140
+#define I40E_PRTDCB_TFWSP              0x000A0140 /* Reset: CORER */
 #define I40E_PRTDCB_TFWSP_WSPORT_SHIFT 0
 #define I40E_PRTDCB_TFWSP_WSPORT_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TFWSP_WSPORT_SHIFT)
 
-#define I40E_PRTDCB_TLANCPMS              0x000A2020
+#define I40E_PRTDCB_TLANCPMS              0x000A2020 /* Reset: CORER */
 #define I40E_PRTDCB_TLANCPMS_LANCPM_SHIFT 0
 #define I40E_PRTDCB_TLANCPMS_LANCPM_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TLANCPMS_LANCPM_SHIFT)
 
-#define I40E_PRTDCB_TLPMC              0x000A0160
+#define I40E_PRTDCB_TLPMC              0x000A0160 /* Reset: CORER */
 #define I40E_PRTDCB_TLPMC_TC2PFC_SHIFT 0
 #define I40E_PRTDCB_TLPMC_TC2PFC_MASK  I40E_MASK(0xFF, I40E_PRTDCB_TLPMC_TC2PFC_SHIFT)
 
-#define I40E_PRTDCB_TPFCTOP                 0x001E4540
+#define I40E_PRTDCB_TPFCTOP                 0x001E4540 /* Reset: GLOBR */
 #define I40E_PRTDCB_TPFCTOP_PFCTYPE_SHIFT   0
 #define I40E_PRTDCB_TPFCTOP_PFCTYPE_MASK    I40E_MASK(0xFFFF, I40E_PRTDCB_TPFCTOP_PFCTYPE_SHIFT)
 #define I40E_PRTDCB_TPFCTOP_PFCOPCODE_SHIFT 16
 #define I40E_PRTDCB_TPFCTOP_PFCOPCODE_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_TPFCTOP_PFCOPCODE_SHIFT)
 
-#define I40E_PRTDCB_TRDMACPMS               0x000A2000
+#define I40E_PRTDCB_TRDMACPMS               0x000A2000 /* Reset: CORER */
 #define I40E_PRTDCB_TRDMACPMS_RDMACPM_SHIFT 0
 #define I40E_PRTDCB_TRDMACPMS_RDMACPM_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TRDMACPMS_RDMACPM_SHIFT)
 
-#define I40E_PRTDCB_TUP2TC             0x001E4620
+#define I40E_PRTDCB_TUP2TC             0x001E4620 /* Reset: GLOBR */
 #define I40E_PRTDCB_TUP2TC_UP0TC_SHIFT 0
 #define I40E_PRTDCB_TUP2TC_UP0TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_TUP2TC_UP0TC_SHIFT)
 #define I40E_PRTDCB_TUP2TC_UP1TC_SHIFT 3
@@ -697,31 +697,31 @@
 #define I40E_PRTDCB_TUP2TC_UP7TC_SHIFT 21
 #define I40E_PRTDCB_TUP2TC_UP7TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_TUP2TC_UP7TC_SHIFT)
 
-#define I40E_PRTDCB_TUPMC              0x000A2140
+#define I40E_PRTDCB_TUPMC              0x000A2140 /* Reset: CORER */
 #define I40E_PRTDCB_TUPMC_TC2PFC_SHIFT 0
 #define I40E_PRTDCB_TUPMC_TC2PFC_MASK  I40E_MASK(0xFF, I40E_PRTDCB_TUPMC_TC2PFC_SHIFT)
 
 /* PF - FCoE Registers  */
 
-#define I40E_GLFCOE_ENA                0x001C0A28
+#define I40E_GLFCOE_ENA                0x001C0A28 /* Reset: CORER */
 #define I40E_GLFCOE_ENA_FCOE_ENA_SHIFT 0
 #define I40E_GLFCOE_ENA_FCOE_ENA_MASK  I40E_MASK(0x1, I40E_GLFCOE_ENA_FCOE_ENA_SHIFT)
 
-#define I40E_GLFCOE_ENA_TDPU                0x000442E4
+#define I40E_GLFCOE_ENA_TDPU                0x000442E4 /* Reset: CORER */
 #define I40E_GLFCOE_ENA_TDPU_FCOE_ENA_SHIFT 0
 #define I40E_GLFCOE_ENA_TDPU_FCOE_ENA_MASK  I40E_MASK(0x1, I40E_GLFCOE_ENA_TDPU_FCOE_ENA_SHIFT)
 
-#define I40E_GLFCOE_ENA_TLAN                0x000E6484
+#define I40E_GLFCOE_ENA_TLAN                0x000E6484 /* Reset: CORER */
 #define I40E_GLFCOE_ENA_TLAN_FCOE_ENA_SHIFT 0
 #define I40E_GLFCOE_ENA_TLAN_FCOE_ENA_MASK  I40E_MASK(0x1, I40E_GLFCOE_ENA_TLAN_FCOE_ENA_SHIFT)
 
-#define I40E_GLFCOE_RLANCTL                0x0012A508
+#define I40E_GLFCOE_RLANCTL                0x0012A508 /* Reset: CORER */
 #define I40E_GLFCOE_RLANCTL_FRSTDDPH_SHIFT 1
 #define I40E_GLFCOE_RLANCTL_FRSTDDPH_MASK  I40E_MASK(0x1, I40E_GLFCOE_RLANCTL_FRSTDDPH_SHIFT)
 #define I40E_GLFCOE_RLANCTL_ALLH_SHIFT     3
 #define I40E_GLFCOE_RLANCTL_ALLH_MASK      I40E_MASK(0x1, I40E_GLFCOE_RLANCTL_ALLH_SHIFT)
 
-#define I40E_GLFCOE_RSOF              0x00269B9C
+#define I40E_GLFCOE_RSOF              0x00269B9C /* Reset: CORER */
 #define I40E_GLFCOE_RSOF_SOF_I2_SHIFT 0
 #define I40E_GLFCOE_RSOF_SOF_I2_MASK  I40E_MASK(0xFF, I40E_GLFCOE_RSOF_SOF_I2_SHIFT)
 #define I40E_GLFCOE_RSOF_SOF_I3_SHIFT 8
@@ -731,7 +731,7 @@
 #define I40E_GLFCOE_RSOF_SOF_N3_SHIFT 24
 #define I40E_GLFCOE_RSOF_SOF_N3_MASK  I40E_MASK(0xFF, I40E_GLFCOE_RSOF_SOF_N3_SHIFT)
 
-#define I40E_GLFCOE_TEOF              0x000442EC
+#define I40E_GLFCOE_TEOF              0x000442EC /* Reset: CORER */
 #define I40E_GLFCOE_TEOF_EOF_N_SHIFT  0
 #define I40E_GLFCOE_TEOF_EOF_N_MASK   I40E_MASK(0xFF, I40E_GLFCOE_TEOF_EOF_N_SHIFT)
 #define I40E_GLFCOE_TEOF_EOF_T_SHIFT  8
@@ -741,7 +741,7 @@
 #define I40E_GLFCOE_TEOF_EOF_A_SHIFT  24
 #define I40E_GLFCOE_TEOF_EOF_A_MASK   I40E_MASK(0xFF, I40E_GLFCOE_TEOF_EOF_A_SHIFT)
 
-#define I40E_GLFCOE_TSOF              0x000442E8
+#define I40E_GLFCOE_TSOF              0x000442E8 /* Reset: CORER */
 #define I40E_GLFCOE_TSOF_SOF_I2_SHIFT 0
 #define I40E_GLFCOE_TSOF_SOF_I2_MASK  I40E_MASK(0xFF, I40E_GLFCOE_TSOF_SOF_I2_SHIFT)
 #define I40E_GLFCOE_TSOF_SOF_I3_SHIFT 8
@@ -751,7 +751,7 @@
 #define I40E_GLFCOE_TSOF_SOF_N3_SHIFT 24
 #define I40E_GLFCOE_TSOF_SOF_N3_MASK  I40E_MASK(0xFF, I40E_GLFCOE_TSOF_SOF_N3_SHIFT)
 
-#define I40E_PRTFCOE_REOF              0x000856A0
+#define I40E_PRTFCOE_REOF              0x000856A0 /* Reset: CORER */
 #define I40E_PRTFCOE_REOF_EOF_N_SHIFT  0
 #define I40E_PRTFCOE_REOF_EOF_N_MASK   I40E_MASK(0xFF, I40E_PRTFCOE_REOF_EOF_N_SHIFT)
 #define I40E_PRTFCOE_REOF_EOF_T_SHIFT  8
@@ -763,37 +763,37 @@
 
 /* PF - General Registers  */
 
-#define I40E_ECC_ENA               0x00092630
+#define I40E_ECC_ENA               0x00092630 /* Reset: CORER */
 #define I40E_ECC_ENA_ECC_ENA_SHIFT 0
 #define I40E_ECC_ENA_ECC_ENA_MASK  I40E_MASK(0x1, I40E_ECC_ENA_ECC_ENA_SHIFT)
 
-#define I40E_GLGEN_CSR_DEBUG_C                     0x00078E8C
+#define I40E_GLGEN_CSR_DEBUG_C                     0x00078E8C /* Reset: POR */
 #define I40E_GLGEN_CSR_DEBUG_C_CSR_ACCESS_EN_SHIFT 0
 #define I40E_GLGEN_CSR_DEBUG_C_CSR_ACCESS_EN_MASK  I40E_MASK(0x1, I40E_GLGEN_CSR_DEBUG_C_CSR_ACCESS_EN_SHIFT)
 #define I40E_GLGEN_CSR_DEBUG_C_CSR_ADDR_PROT_SHIFT 1
 #define I40E_GLGEN_CSR_DEBUG_C_CSR_ADDR_PROT_MASK  I40E_MASK(0x1, I40E_GLGEN_CSR_DEBUG_C_CSR_ADDR_PROT_SHIFT)
 
-#define I40E_GLGEN_CSR_DEBUG_F                   0x000B6138
+#define I40E_GLGEN_CSR_DEBUG_F                   0x000B6138 /* Reset: POR */
 #define I40E_GLGEN_CSR_DEBUG_F_CSR_PROT_EN_SHIFT 0
 #define I40E_GLGEN_CSR_DEBUG_F_CSR_PROT_EN_MASK  I40E_MASK(0x1, I40E_GLGEN_CSR_DEBUG_F_CSR_PROT_EN_SHIFT)
 
-#define I40E_GLGEN_DUAL40                     0x001C0A6C
+#define I40E_GLGEN_DUAL40                     0x001C0A6C /* Reset: CORER */
 #define I40E_GLGEN_DUAL40_DUAL_40G_MODE_SHIFT 0
 #define I40E_GLGEN_DUAL40_DUAL_40G_MODE_MASK  I40E_MASK(0x1, I40E_GLGEN_DUAL40_DUAL_40G_MODE_SHIFT)
 
-#define I40E_GLGEN_DUAL40_RPB                     0x000AC7E0
+#define I40E_GLGEN_DUAL40_RPB                     0x000AC7E0 /* Reset: CORER */
 #define I40E_GLGEN_DUAL40_RPB_DUAL_40G_MODE_SHIFT 0
 #define I40E_GLGEN_DUAL40_RPB_DUAL_40G_MODE_MASK  I40E_MASK(0x1, I40E_GLGEN_DUAL40_RPB_DUAL_40G_MODE_SHIFT)
 
-#define I40E_GLGEN_DUAL40_TLPM                     0x000A01C4
+#define I40E_GLGEN_DUAL40_TLPM                     0x000A01C4 /* Reset: CORER */
 #define I40E_GLGEN_DUAL40_TLPM_DUAL_40G_MODE_SHIFT 0
 #define I40E_GLGEN_DUAL40_TLPM_DUAL_40G_MODE_MASK  I40E_MASK(0x1, I40E_GLGEN_DUAL40_TLPM_DUAL_40G_MODE_SHIFT)
 
-#define I40E_GLGEN_DUAL40_TUPM                     0x000A2204
+#define I40E_GLGEN_DUAL40_TUPM                     0x000A2204 /* Reset: CORER */
 #define I40E_GLGEN_DUAL40_TUPM_DUAL_40G_MODE_SHIFT 0
 #define I40E_GLGEN_DUAL40_TUPM_DUAL_40G_MODE_MASK  I40E_MASK(0x1, I40E_GLGEN_DUAL40_TUPM_DUAL_40G_MODE_SHIFT)
 
-#define I40E_GLGEN_FWHWRCTRL                       0x00092610
+#define I40E_GLGEN_FWHWRCTRL                       0x00092610 /* Reset: CORER */
 #define I40E_GLGEN_FWHWRCTRL_PF_ENA_RST_DONE_SHIFT 0
 #define I40E_GLGEN_FWHWRCTRL_PF_ENA_RST_DONE_MASK  I40E_MASK(0x1, I40E_GLGEN_FWHWRCTRL_PF_ENA_RST_DONE_SHIFT)
 #define I40E_GLGEN_FWHWRCTRL_VF_ENA_RST_DONE_SHIFT 1
@@ -803,7 +803,7 @@
 #define I40E_GLGEN_FWHWRCTRL_PE_CPL_EN_SHIFT       31
 #define I40E_GLGEN_FWHWRCTRL_PE_CPL_EN_MASK        I40E_MASK(0x1, I40E_GLGEN_FWHWRCTRL_PE_CPL_EN_SHIFT)
 
-#define I40E_GLGEN_IMRTRIG              0x000B8194
+#define I40E_GLGEN_IMRTRIG              0x000B8194 /* Reset: CORER */
 #define I40E_GLGEN_IMRTRIG_CORER_SHIFT  0
 #define I40E_GLGEN_IMRTRIG_CORER_MASK   I40E_MASK(0x1, I40E_GLGEN_IMRTRIG_CORER_SHIFT)
 #define I40E_GLGEN_IMRTRIG_GLOBR_SHIFT  1
@@ -811,33 +811,39 @@
 #define I40E_GLGEN_IMRTRIG_EMPFWR_SHIFT 2
 #define I40E_GLGEN_IMRTRIG_EMPFWR_MASK  I40E_MASK(0x1, I40E_GLGEN_IMRTRIG_EMPFWR_SHIFT)
 
-#define I40E_GLGEN_MISC_CONFIG                              0x000B81A4
+#define I40E_GLGEN_MISC_CONFIG                              0x000B81A4 /* Reset: POR */
 #define I40E_GLGEN_MISC_CONFIG_SINGLE_10G_PORT_SELECT_SHIFT 0
 #define I40E_GLGEN_MISC_CONFIG_SINGLE_10G_PORT_SELECT_MASK  I40E_MASK(0x1, I40E_GLGEN_MISC_CONFIG_SINGLE_10G_PORT_SELECT_SHIFT)
 
-#define I40E_GLGEN_PCIFCNCNT_CSR                0x00078E84
+#define I40E_GLGEN_PCIFCNCNT_CSR                0x00078E84 /* Reset: PCIR */
 #define I40E_GLGEN_PCIFCNCNT_CSR_PCIPFCNT_SHIFT 0
 #define I40E_GLGEN_PCIFCNCNT_CSR_PCIPFCNT_MASK  I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_CSR_PCIPFCNT_SHIFT)
 #define I40E_GLGEN_PCIFCNCNT_CSR_PCIVFCNT_SHIFT 16
 #define I40E_GLGEN_PCIFCNCNT_CSR_PCIVFCNT_MASK  I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_CSR_PCIVFCNT_SHIFT)
 
-#define I40E_GLGEN_PCIFCNCNT_INT                0x0003F840
+#define I40E_GLGEN_PCIFCNCNT_INT                0x0003F840 /* Reset: CORER */
 #define I40E_GLGEN_PCIFCNCNT_INT_PCIPFCNT_SHIFT 0
 #define I40E_GLGEN_PCIFCNCNT_INT_PCIPFCNT_MASK  I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_INT_PCIPFCNT_SHIFT)
 #define I40E_GLGEN_PCIFCNCNT_INT_PCIVFCNT_SHIFT 16
 #define I40E_GLGEN_PCIFCNCNT_INT_PCIVFCNT_MASK  I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_INT_PCIVFCNT_SHIFT)
 
-#define I40E_GLGEN_PF_ACC_TO                 0x00078E88
+#define I40E_GLGEN_PE_ENA                      0x000B81A0 /* Reset: POR */
+#define I40E_GLGEN_PE_ENA_PE_ENA_SHIFT         0
+#define I40E_GLGEN_PE_ENA_PE_ENA_MASK          I40E_MASK(0x1, I40E_GLGEN_PE_ENA_PE_ENA_SHIFT)
+#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT 1
+#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_MASK  I40E_MASK(0x3, I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT)
+
+#define I40E_GLGEN_PF_ACC_TO                 0x00078E88 /* Reset: POR */
 #define I40E_GLGEN_PF_ACC_TO_PF_ACC_TO_SHIFT 0
 #define I40E_GLGEN_PF_ACC_TO_PF_ACC_TO_MASK  I40E_MASK(0xFFFF, I40E_GLGEN_PF_ACC_TO_PF_ACC_TO_SHIFT)
 
-#define I40E_GLGEN_RSTSTAT_REQ                 0x00092620
+#define I40E_GLGEN_RSTSTAT_REQ                 0x00092620 /* Reset: CORER */
 #define I40E_GLGEN_RSTSTAT_REQ_RST_INDEX_SHIFT 0
 #define I40E_GLGEN_RSTSTAT_REQ_RST_INDEX_MASK  I40E_MASK(0x1FF, I40E_GLGEN_RSTSTAT_REQ_RST_INDEX_SHIFT)
 #define I40E_GLGEN_RSTSTAT_REQ_RST_TYPE_SHIFT  16
 #define I40E_GLGEN_RSTSTAT_REQ_RST_TYPE_MASK   I40E_MASK(0x3, I40E_GLGEN_RSTSTAT_REQ_RST_TYPE_SHIFT)
 
-#define I40E_GLGEN_RSTSTATUS                   0x00092624
+#define I40E_GLGEN_RSTSTATUS                   0x00092624 /* Reset: CORER */
 #define I40E_GLGEN_RSTSTATUS_TDPU_CNT_SHIFT    0
 #define I40E_GLGEN_RSTSTATUS_TDPU_CNT_MASK     I40E_MASK(0x1F, I40E_GLGEN_RSTSTATUS_TDPU_CNT_SHIFT)
 #define I40E_GLGEN_RSTSTATUS_RDPU_CNT_SHIFT    8
@@ -869,56 +875,56 @@
 #define I40E_GLGEN_RSTSTATUS_HW_DONE_SHIFT     31
 #define I40E_GLGEN_RSTSTATUS_HW_DONE_MASK      I40E_MASK(0x1, I40E_GLGEN_RSTSTATUS_HW_DONE_SHIFT)
 
-#define I40E_GLMNG_WD_ENA                     0x000B8198
+#define I40E_GLMNG_WD_ENA                     0x000B8198 /* Reset: POR */
 #define I40E_GLMNG_WD_ENA_FW_RST_WD_ENA_SHIFT 0
 #define I40E_GLMNG_WD_ENA_FW_RST_WD_ENA_MASK  I40E_MASK(0x1, I40E_GLMNG_WD_ENA_FW_RST_WD_ENA_SHIFT)
 #define I40E_GLMNG_WD_ENA_ECC_RST_ENA_SHIFT   1
 #define I40E_GLMNG_WD_ENA_ECC_RST_ENA_MASK    I40E_MASK(0x1, I40E_GLMNG_WD_ENA_ECC_RST_ENA_SHIFT)
 
-#define I40E_GLPHY_ANA_ADD               0x000BA008
+#define I40E_GLPHY_ANA_ADD               0x000BA008 /* Reset: POR */
 #define I40E_GLPHY_ANA_ADD_ADDRESS_SHIFT 0
 #define I40E_GLPHY_ANA_ADD_ADDRESS_MASK  I40E_MASK(0xFFFF, I40E_GLPHY_ANA_ADD_ADDRESS_SHIFT)
 #define I40E_GLPHY_ANA_ADD_BYTE_EN_SHIFT 28
 #define I40E_GLPHY_ANA_ADD_BYTE_EN_MASK  I40E_MASK(0xF, I40E_GLPHY_ANA_ADD_BYTE_EN_SHIFT)
 
-#define I40E_GLPHY_ANA_DATA            0x000BA00C
+#define I40E_GLPHY_ANA_DATA            0x000BA00C /* Reset: POR */
 #define I40E_GLPHY_ANA_DATA_DATA_SHIFT 0
 #define I40E_GLPHY_ANA_DATA_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPHY_ANA_DATA_DATA_SHIFT)
 
-#define I40E_PFGEN_FWHWRSTAT                        0x00092480
+#define I40E_PFGEN_FWHWRSTAT                        0x00092480 /* Reset: CORER */
 #define I40E_PFGEN_FWHWRSTAT_FW_RST_DONE_SHIFT      0
 #define I40E_PFGEN_FWHWRSTAT_FW_RST_DONE_MASK       I40E_MASK(0x1, I40E_PFGEN_FWHWRSTAT_FW_RST_DONE_SHIFT)
 #define I40E_PFGEN_FWHWRSTAT_HW_ONLY_RST_DONE_SHIFT 31
 #define I40E_PFGEN_FWHWRSTAT_HW_ONLY_RST_DONE_MASK  I40E_MASK(0x1, I40E_PFGEN_FWHWRSTAT_HW_ONLY_RST_DONE_SHIFT)
 
-#define I40E_PFGEN_PORTNUM_CAR                0x000B8000
+#define I40E_PFGEN_PORTNUM_CAR                0x000B8000 /* Reset: POR */
 #define I40E_PFGEN_PORTNUM_CAR_PORT_NUM_SHIFT 0
 #define I40E_PFGEN_PORTNUM_CAR_PORT_NUM_MASK  I40E_MASK(0x3, I40E_PFGEN_PORTNUM_CAR_PORT_NUM_SHIFT)
 
-#define I40E_PFGEN_PORTNUM_CSR                0x00078D00
+#define I40E_PFGEN_PORTNUM_CSR                0x00078D00 /* Reset: CORER */
 #define I40E_PFGEN_PORTNUM_CSR_PORT_NUM_SHIFT 0
 #define I40E_PFGEN_PORTNUM_CSR_PORT_NUM_MASK  I40E_MASK(0x3, I40E_PFGEN_PORTNUM_CSR_PORT_NUM_SHIFT)
 
-#define I40E_PFGEN_PORTNUM_PM                0x0006B800
+#define I40E_PFGEN_PORTNUM_PM                0x0006B800 /* Reset: CORER */
 #define I40E_PFGEN_PORTNUM_PM_PORT_NUM_SHIFT 0
 #define I40E_PFGEN_PORTNUM_PM_PORT_NUM_MASK  I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PM_PORT_NUM_SHIFT)
 
-#define I40E_PFGEN_PORTNUM_RCB                0x00122000
+#define I40E_PFGEN_PORTNUM_RCB                0x00122000 /* Reset: CORER */
 #define I40E_PFGEN_PORTNUM_RCB_PORT_NUM_SHIFT 0
 #define I40E_PFGEN_PORTNUM_RCB_PORT_NUM_MASK  I40E_MASK(0x3, I40E_PFGEN_PORTNUM_RCB_PORT_NUM_SHIFT)
 
-#define I40E_PFGEN_PORTNUM_TSCD                0x000B2240
+#define I40E_PFGEN_PORTNUM_TSCD                0x000B2240 /* Reset: CORER */
 #define I40E_PFGEN_PORTNUM_TSCD_PORT_NUM_SHIFT 0
 #define I40E_PFGEN_PORTNUM_TSCD_PORT_NUM_MASK  I40E_MASK(0x3, I40E_PFGEN_PORTNUM_TSCD_PORT_NUM_SHIFT)
 
-#define I40E_VPGEN_FWHWRSTAT(_VF)                   (0x00092000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPGEN_FWHWRSTAT(_VF)                   (0x00092000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VPGEN_FWHWRSTAT_MAX_INDEX              127
 #define I40E_VPGEN_FWHWRSTAT_FW_RST_DONE_SHIFT      0
 #define I40E_VPGEN_FWHWRSTAT_FW_RST_DONE_MASK       I40E_MASK(0x1, I40E_VPGEN_FWHWRSTAT_FW_RST_DONE_SHIFT)
 #define I40E_VPGEN_FWHWRSTAT_HW_ONLY_RST_DONE_SHIFT 31
 #define I40E_VPGEN_FWHWRSTAT_HW_ONLY_RST_DONE_MASK  I40E_MASK(0x1, I40E_VPGEN_FWHWRSTAT_HW_ONLY_RST_DONE_SHIFT)
 
-#define I40E_VSIGEN_FWHWRSTAT(_VSI)                  (0x00091000 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSIGEN_FWHWRSTAT(_VSI)                  (0x00091000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
 #define I40E_VSIGEN_FWHWRSTAT_MAX_INDEX              383
 #define I40E_VSIGEN_FWHWRSTAT_FW_RST_DONE_SHIFT      0
 #define I40E_VSIGEN_FWHWRSTAT_FW_RST_DONE_MASK       I40E_MASK(0x1, I40E_VSIGEN_FWHWRSTAT_FW_RST_DONE_SHIFT)
@@ -927,13 +933,13 @@
 
 /* PF - HMC Registers */
 
-#define I40E_GLFOC_CECC_ERR                         0x000AA0D4
+#define I40E_GLFOC_CECC_ERR                         0x000AA0D4 /* Reset: POR */
 #define I40E_GLFOC_CECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT 0
 #define I40E_GLFOC_CECC_ERR_UNCOR_ECC_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_GLFOC_CECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT)
 #define I40E_GLFOC_CECC_ERR_COR_ECC_ERR_CNT_SHIFT   16
 #define I40E_GLFOC_CECC_ERR_COR_ECC_ERR_CNT_MASK    I40E_MASK(0xFFF, I40E_GLFOC_CECC_ERR_COR_ECC_ERR_CNT_SHIFT)
 
-#define I40E_GLFOC_ECC_CTL                           0x000AA0CC
+#define I40E_GLFOC_ECC_CTL                           0x000AA0CC /* Reset: POR */
 #define I40E_GLFOC_ECC_CTL_HOST_ECC_EN_SHIFT         0
 #define I40E_GLFOC_ECC_CTL_HOST_ECC_EN_MASK          I40E_MASK(0x1, I40E_GLFOC_ECC_CTL_HOST_ECC_EN_SHIFT)
 #define I40E_GLFOC_ECC_CTL_HOST_ECC_MASK_INT_SHIFT   1
@@ -951,7 +957,7 @@
 #define I40E_GLFOC_ECC_CTL_CLIENT_ECC_INVERT2_SHIFT  7
 #define I40E_GLFOC_ECC_CTL_CLIENT_ECC_INVERT2_MASK   I40E_MASK(0x1, I40E_GLFOC_ECC_CTL_CLIENT_ECC_INVERT2_SHIFT)
 
-#define I40E_GLFOC_ERRDATA0                  0x000AA0C0
+#define I40E_GLFOC_ERRDATA0                  0x000AA0C0 /* Reset: POR */
 #define I40E_GLFOC_ERRDATA0_ERROR_CODE_SHIFT 0
 #define I40E_GLFOC_ERRDATA0_ERROR_CODE_MASK  I40E_MASK(0x3F, I40E_GLFOC_ERRDATA0_ERROR_CODE_SHIFT)
 #define I40E_GLFOC_ERRDATA0_OBJ_TYPE_SHIFT   8
@@ -963,11 +969,11 @@
 #define I40E_GLFOC_ERRDATA0_PF_NUM_SHIFT     24
 #define I40E_GLFOC_ERRDATA0_PF_NUM_MASK      I40E_MASK(0xF, I40E_GLFOC_ERRDATA0_PF_NUM_SHIFT)
 
-#define I40E_GLFOC_ERRDATA1                 0x000AA0C4
+#define I40E_GLFOC_ERRDATA1                 0x000AA0C4 /* Reset: POR */
 #define I40E_GLFOC_ERRDATA1_OBJ_INDEX_SHIFT 0
 #define I40E_GLFOC_ERRDATA1_OBJ_INDEX_MASK  I40E_MASK(0xFFFFFFF, I40E_GLFOC_ERRDATA1_OBJ_INDEX_SHIFT)
 
-#define I40E_GLFOC_ERRDATA2              0x000AA0C8
+#define I40E_GLFOC_ERRDATA2              0x000AA0C8 /* Reset: POR */
 #define I40E_GLFOC_ERRDATA2_LENGTH_SHIFT 0
 #define I40E_GLFOC_ERRDATA2_LENGTH_MASK  I40E_MASK(0x7F, I40E_GLFOC_ERRDATA2_LENGTH_SHIFT)
 #define I40E_GLFOC_ERRDATA2_OFFSET_SHIFT 7
@@ -977,111 +983,111 @@
 #define I40E_GLFOC_ERRDATA2_TAG_SHIFT    23
 #define I40E_GLFOC_ERRDATA2_TAG_MASK     I40E_MASK(0x1FF, I40E_GLFOC_ERRDATA2_TAG_SHIFT)
 
-#define I40E_GLFOC_ERRINFO                   0x000AA0BC
+#define I40E_GLFOC_ERRINFO                   0x000AA0BC /* Reset: POR */
 #define I40E_GLFOC_ERRINFO_ERROR_VALID_SHIFT 0
 #define I40E_GLFOC_ERRINFO_ERROR_VALID_MASK  I40E_MASK(0x1, I40E_GLFOC_ERRINFO_ERROR_VALID_SHIFT)
 #define I40E_GLFOC_ERRINFO_ERROR_CNT_SHIFT   8
 #define I40E_GLFOC_ERRINFO_ERROR_CNT_MASK    I40E_MASK(0xFF, I40E_GLFOC_ERRINFO_ERROR_CNT_SHIFT)
 
-#define I40E_GLFOC_FCOEHTE_OBJOFST                       0x000AA050
+#define I40E_GLFOC_FCOEHTE_OBJOFST                       0x000AA050 /* Reset: CORER */
 #define I40E_GLFOC_FCOEHTE_OBJOFST_OBJ_TYPE_OFFSET_SHIFT 0
 #define I40E_GLFOC_FCOEHTE_OBJOFST_OBJ_TYPE_OFFSET_MASK  I40E_MASK(0x3FF, I40E_GLFOC_FCOEHTE_OBJOFST_OBJ_TYPE_OFFSET_SHIFT)
 
-#define I40E_GLFOC_HECC_ERR                         0x000AA0D0
+#define I40E_GLFOC_HECC_ERR                         0x000AA0D0 /* Reset: POR */
 #define I40E_GLFOC_HECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT 0
 #define I40E_GLFOC_HECC_ERR_UNCOR_ECC_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_GLFOC_HECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT)
 #define I40E_GLFOC_HECC_ERR_COR_ECC_ERR_CNT_SHIFT   16
 #define I40E_GLFOC_HECC_ERR_COR_ECC_ERR_CNT_MASK    I40E_MASK(0xFFF, I40E_GLFOC_HECC_ERR_COR_ECC_ERR_CNT_SHIFT)
 
-#define I40E_GLFOC_LAN32BRSV_OBJOFST                       0x000AA058
+#define I40E_GLFOC_LAN32BRSV_OBJOFST                       0x000AA058 /* Reset: CORER */
 #define I40E_GLFOC_LAN32BRSV_OBJOFST_OBJ_TYPE_OFFSET_SHIFT 0
 #define I40E_GLFOC_LAN32BRSV_OBJOFST_OBJ_TYPE_OFFSET_MASK  I40E_MASK(0x3FF, I40E_GLFOC_LAN32BRSV_OBJOFST_OBJ_TYPE_OFFSET_SHIFT)
 
-#define I40E_GLFOC_LAN64BRSV0_OBJOFST                       0x000AA05C
+#define I40E_GLFOC_LAN64BRSV0_OBJOFST                       0x000AA05C /* Reset: CORER */
 #define I40E_GLFOC_LAN64BRSV0_OBJOFST_OBJ_TYPE_OFFSET_SHIFT 0
 #define I40E_GLFOC_LAN64BRSV0_OBJOFST_OBJ_TYPE_OFFSET_MASK  I40E_MASK(0x3FF, I40E_GLFOC_LAN64BRSV0_OBJOFST_OBJ_TYPE_OFFSET_SHIFT)
 
-#define I40E_GLFOC_LAN64BRSV1_OBJOFST                       0x000AA060
+#define I40E_GLFOC_LAN64BRSV1_OBJOFST                       0x000AA060 /* Reset: CORER */
 #define I40E_GLFOC_LAN64BRSV1_OBJOFST_OBJ_TYPE_OFFSET_SHIFT 0
 #define I40E_GLFOC_LAN64BRSV1_OBJOFST_OBJ_TYPE_OFFSET_MASK  I40E_MASK(0x3FF, I40E_GLFOC_LAN64BRSV1_OBJOFST_OBJ_TYPE_OFFSET_SHIFT)
 
-#define I40E_GLFOC_QUADHTE_OBJOFST                       0x000AA054
+#define I40E_GLFOC_QUADHTE_OBJOFST                       0x000AA054 /* Reset: CORER */
 #define I40E_GLFOC_QUADHTE_OBJOFST_OBJ_TYPE_OFFSET_SHIFT 0
 #define I40E_GLFOC_QUADHTE_OBJOFST_OBJ_TYPE_OFFSET_MASK  I40E_MASK(0x3FF, I40E_GLFOC_QUADHTE_OBJOFST_OBJ_TYPE_OFFSET_SHIFT)
 
-#define I40E_GLFOC_STAT_CTL                   0x000AA008
+#define I40E_GLFOC_STAT_CTL                   0x000AA008 /* Reset: CORER */
 #define I40E_GLFOC_STAT_CTL_OBJECT_TYPE_SHIFT 0
 #define I40E_GLFOC_STAT_CTL_OBJECT_TYPE_MASK  I40E_MASK(0x1F, I40E_GLFOC_STAT_CTL_OBJECT_TYPE_SHIFT)
 
-#define I40E_GLFOC_STAT_OBJ_CNT                    0x000AA00C
+#define I40E_GLFOC_STAT_OBJ_CNT                    0x000AA00C /* Reset: CORER */
 #define I40E_GLFOC_STAT_OBJ_CNT_OBJECT_COUNT_SHIFT 0
 #define I40E_GLFOC_STAT_OBJ_CNT_OBJECT_COUNT_MASK  I40E_MASK(0x3FFF, I40E_GLFOC_STAT_OBJ_CNT_OBJECT_COUNT_SHIFT)
 
-#define I40E_GLFOC_STAT_RD_DATA_IDLE_HI              0x000AA034
+#define I40E_GLFOC_STAT_RD_DATA_IDLE_HI              0x000AA034 /* Reset: CORER */
 #define I40E_GLFOC_STAT_RD_DATA_IDLE_HI_CNT_HI_SHIFT 0
 #define I40E_GLFOC_STAT_RD_DATA_IDLE_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLFOC_STAT_RD_DATA_IDLE_HI_CNT_HI_SHIFT)
 
-#define I40E_GLFOC_STAT_RD_DATA_IDLE_LO              0x000AA030
+#define I40E_GLFOC_STAT_RD_DATA_IDLE_LO              0x000AA030 /* Reset: CORER */
 #define I40E_GLFOC_STAT_RD_DATA_IDLE_LO_CNT_LO_SHIFT 0
 #define I40E_GLFOC_STAT_RD_DATA_IDLE_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLFOC_STAT_RD_DATA_IDLE_LO_CNT_LO_SHIFT)
 
-#define I40E_GLFOC_STAT_RD_DATA_XFER_HI              0x000AA03C
+#define I40E_GLFOC_STAT_RD_DATA_XFER_HI              0x000AA03C /* Reset: CORER */
 #define I40E_GLFOC_STAT_RD_DATA_XFER_HI_CNT_HI_SHIFT 0
 #define I40E_GLFOC_STAT_RD_DATA_XFER_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLFOC_STAT_RD_DATA_XFER_HI_CNT_HI_SHIFT)
 
-#define I40E_GLFOC_STAT_RD_DATA_XFER_LO              0x000AA038
+#define I40E_GLFOC_STAT_RD_DATA_XFER_LO              0x000AA038 /* Reset: CORER */
 #define I40E_GLFOC_STAT_RD_DATA_XFER_LO_CNT_LO_SHIFT 0
 #define I40E_GLFOC_STAT_RD_DATA_XFER_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLFOC_STAT_RD_DATA_XFER_LO_CNT_LO_SHIFT)
 
-#define I40E_GLFOC_STAT_RD_HIT_HI              0x000AA014
+#define I40E_GLFOC_STAT_RD_HIT_HI              0x000AA014 /* Reset: CORER */
 #define I40E_GLFOC_STAT_RD_HIT_HI_CNT_HI_SHIFT 0
 #define I40E_GLFOC_STAT_RD_HIT_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLFOC_STAT_RD_HIT_HI_CNT_HI_SHIFT)
 
-#define I40E_GLFOC_STAT_RD_HIT_LO              0x000AA010
+#define I40E_GLFOC_STAT_RD_HIT_LO              0x000AA010 /* Reset: CORER */
 #define I40E_GLFOC_STAT_RD_HIT_LO_CNT_LO_SHIFT 0
 #define I40E_GLFOC_STAT_RD_HIT_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLFOC_STAT_RD_HIT_LO_CNT_LO_SHIFT)
 
-#define I40E_GLFOC_STAT_RD_MISS_HI              0x000AA01C
+#define I40E_GLFOC_STAT_RD_MISS_HI              0x000AA01C /* Reset: CORER */
 #define I40E_GLFOC_STAT_RD_MISS_HI_CNT_HI_SHIFT 0
 #define I40E_GLFOC_STAT_RD_MISS_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLFOC_STAT_RD_MISS_HI_CNT_HI_SHIFT)
 
-#define I40E_GLFOC_STAT_RD_MISS_LO              0x000AA018
+#define I40E_GLFOC_STAT_RD_MISS_LO              0x000AA018 /* Reset: CORER */
 #define I40E_GLFOC_STAT_RD_MISS_LO_CNT_LO_SHIFT 0
 #define I40E_GLFOC_STAT_RD_MISS_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLFOC_STAT_RD_MISS_LO_CNT_LO_SHIFT)
 
-#define I40E_GLFOC_STAT_WR_DATA_IDLE_HI              0x000AA044
+#define I40E_GLFOC_STAT_WR_DATA_IDLE_HI              0x000AA044 /* Reset: CORER */
 #define I40E_GLFOC_STAT_WR_DATA_IDLE_HI_CNT_HI_SHIFT 0
 #define I40E_GLFOC_STAT_WR_DATA_IDLE_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLFOC_STAT_WR_DATA_IDLE_HI_CNT_HI_SHIFT)
 
-#define I40E_GLFOC_STAT_WR_DATA_IDLE_LO              0x000AA040
+#define I40E_GLFOC_STAT_WR_DATA_IDLE_LO              0x000AA040 /* Reset: CORER */
 #define I40E_GLFOC_STAT_WR_DATA_IDLE_LO_CNT_LO_SHIFT 0
 #define I40E_GLFOC_STAT_WR_DATA_IDLE_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLFOC_STAT_WR_DATA_IDLE_LO_CNT_LO_SHIFT)
 
-#define I40E_GLFOC_STAT_WR_DATA_XFER_HI              0x000AA04C
+#define I40E_GLFOC_STAT_WR_DATA_XFER_HI              0x000AA04C /* Reset: CORER */
 #define I40E_GLFOC_STAT_WR_DATA_XFER_HI_CNT_HI_SHIFT 0
 #define I40E_GLFOC_STAT_WR_DATA_XFER_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLFOC_STAT_WR_DATA_XFER_HI_CNT_HI_SHIFT)
 
-#define I40E_GLFOC_STAT_WR_DATA_XFER_LO              0x000AA048
+#define I40E_GLFOC_STAT_WR_DATA_XFER_LO              0x000AA048 /* Reset: CORER */
 #define I40E_GLFOC_STAT_WR_DATA_XFER_LO_CNT_LO_SHIFT 0
 #define I40E_GLFOC_STAT_WR_DATA_XFER_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLFOC_STAT_WR_DATA_XFER_LO_CNT_LO_SHIFT)
 
-#define I40E_GLFOC_STAT_WR_HIT_HI              0x000AA024
+#define I40E_GLFOC_STAT_WR_HIT_HI              0x000AA024 /* Reset: CORER */
 #define I40E_GLFOC_STAT_WR_HIT_HI_CNT_HI_SHIFT 0
 #define I40E_GLFOC_STAT_WR_HIT_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLFOC_STAT_WR_HIT_HI_CNT_HI_SHIFT)
 
-#define I40E_GLFOC_STAT_WR_HIT_LO              0x000AA020
+#define I40E_GLFOC_STAT_WR_HIT_LO              0x000AA020 /* Reset: CORER */
 #define I40E_GLFOC_STAT_WR_HIT_LO_CNT_LO_SHIFT 0
 #define I40E_GLFOC_STAT_WR_HIT_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLFOC_STAT_WR_HIT_LO_CNT_LO_SHIFT)
 
-#define I40E_GLFOC_STAT_WR_MISS_HI              0x000AA02C
+#define I40E_GLFOC_STAT_WR_MISS_HI              0x000AA02C /* Reset: CORER */
 #define I40E_GLFOC_STAT_WR_MISS_HI_CNT_HI_SHIFT 0
 #define I40E_GLFOC_STAT_WR_MISS_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLFOC_STAT_WR_MISS_HI_CNT_HI_SHIFT)
 
-#define I40E_GLFOC_STAT_WR_MISS_LO              0x000AA028
+#define I40E_GLFOC_STAT_WR_MISS_LO              0x000AA028 /* Reset: CORER */
 #define I40E_GLFOC_STAT_WR_MISS_LO_CNT_LO_SHIFT 0
 #define I40E_GLFOC_STAT_WR_MISS_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLFOC_STAT_WR_MISS_LO_CNT_LO_SHIFT)
 
-#define I40E_GLHMC_EMPOBJCACHECTL0                      0x000C20dc
+#define I40E_GLHMC_EMPOBJCACHECTL0                      0x000C20dc /* Reset: CORER */
 #define I40E_GLHMC_EMPOBJCACHECTL0_OBJ_PF_NUM_SHIFT     0
 #define I40E_GLHMC_EMPOBJCACHECTL0_OBJ_PF_NUM_MASK      I40E_MASK(0xF, I40E_GLHMC_EMPOBJCACHECTL0_OBJ_PF_NUM_SHIFT)
 #define I40E_GLHMC_EMPOBJCACHECTL0_OBJ_TYPE_SHIFT       8
@@ -1097,17 +1103,17 @@
 #define I40E_GLHMC_EMPOBJCACHECTL0_CMD_DONE_SHIFT       31
 #define I40E_GLHMC_EMPOBJCACHECTL0_CMD_DONE_MASK        I40E_MASK(0x1, I40E_GLHMC_EMPOBJCACHECTL0_CMD_DONE_SHIFT)
 
-#define I40E_GLHMC_EMPOBJCACHECTL1                 0x000C20e0
+#define I40E_GLHMC_EMPOBJCACHECTL1                 0x000C20e0 /* Reset: CORER */
 #define I40E_GLHMC_EMPOBJCACHECTL1_OBJ_INDEX_SHIFT 0
 #define I40E_GLHMC_EMPOBJCACHECTL1_OBJ_INDEX_MASK  I40E_MASK(0xFFFFFFF, I40E_GLHMC_EMPOBJCACHECTL1_OBJ_INDEX_SHIFT)
 
-#define I40E_GLHMC_FWPDINV               0x000C207c
+#define I40E_GLHMC_FWPDINV               0x000C207c /* Reset: CORER */
 #define I40E_GLHMC_FWPDINV_PMSDIDX_SHIFT 0
 #define I40E_GLHMC_FWPDINV_PMSDIDX_MASK  I40E_MASK(0xFFF, I40E_GLHMC_FWPDINV_PMSDIDX_SHIFT)
 #define I40E_GLHMC_FWPDINV_PMPDIDX_SHIFT 16
 #define I40E_GLHMC_FWPDINV_PMPDIDX_MASK  I40E_MASK(0x1FF, I40E_GLHMC_FWPDINV_PMPDIDX_SHIFT)
 
-#define I40E_GLHMC_FWSDCMD                0x000C2070
+#define I40E_GLHMC_FWSDCMD                0x000C2070 /* Reset: CORER */
 #define I40E_GLHMC_FWSDCMD_PMSDIDX_SHIFT  0
 #define I40E_GLHMC_FWSDCMD_PMSDIDX_MASK   I40E_MASK(0xFFF, I40E_GLHMC_FWSDCMD_PMSDIDX_SHIFT)
 #define I40E_GLHMC_FWSDCMD_PF_SHIFT       16
@@ -1119,11 +1125,11 @@
 #define I40E_GLHMC_FWSDCMD_PMSDWR_SHIFT   31
 #define I40E_GLHMC_FWSDCMD_PMSDWR_MASK    I40E_MASK(0x1, I40E_GLHMC_FWSDCMD_PMSDWR_SHIFT)
 
-#define I40E_GLHMC_FWSDDATAHIGH                    0x000C2078
+#define I40E_GLHMC_FWSDDATAHIGH                    0x000C2078 /* Reset: CORER */
 #define I40E_GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_SHIFT 0
 #define I40E_GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_SHIFT)
 
-#define I40E_GLHMC_FWSDDATALOW                   0x000C2074
+#define I40E_GLHMC_FWSDDATALOW                   0x000C2074 /* Reset: CORER */
 #define I40E_GLHMC_FWSDDATALOW_PMSDVALID_SHIFT   0
 #define I40E_GLHMC_FWSDDATALOW_PMSDVALID_MASK    I40E_MASK(0x1, I40E_GLHMC_FWSDDATALOW_PMSDVALID_SHIFT)
 #define I40E_GLHMC_FWSDDATALOW_PMSDTYPE_SHIFT    1
@@ -1133,61 +1139,61 @@
 #define I40E_GLHMC_FWSDDATALOW_PMSDDATALOW_SHIFT 12
 #define I40E_GLHMC_FWSDDATALOW_PMSDDATALOW_MASK  I40E_MASK(0xFFFFF, I40E_GLHMC_FWSDDATALOW_PMSDDATALOW_SHIFT)
 
-#define I40E_GLHMC_LAN32BRSVDBASE(_i)                     (0x000C6a00 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LAN32BRSVDBASE(_i)                     (0x000C6a00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LAN32BRSVDBASE_MAX_INDEX               15
 #define I40E_GLHMC_LAN32BRSVDBASE_FPMLAN32BRSVDBASE_SHIFT 0
 #define I40E_GLHMC_LAN32BRSVDBASE_FPMLAN32BRSVDBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_LAN32BRSVDBASE_FPMLAN32BRSVDBASE_SHIFT)
 
-#define I40E_GLHMC_LAN32BRSVDCNT(_i)                    (0x000C6b00 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LAN32BRSVDCNT(_i)                    (0x000C6b00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LAN32BRSVDCNT_MAX_INDEX              15
 #define I40E_GLHMC_LAN32BRSVDCNT_FPMLAN32BRSVDCNT_SHIFT 0
 #define I40E_GLHMC_LAN32BRSVDCNT_FPMLAN32BRSVDCNT_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_LAN32BRSVDCNT_FPMLAN32BRSVDCNT_SHIFT)
 
-#define I40E_GLHMC_LAN32BRSVDMAX                       0x000C209C
+#define I40E_GLHMC_LAN32BRSVDMAX                       0x000C209C /* Reset: CORER */
 #define I40E_GLHMC_LAN32BRSVDMAX_PMLAN32BRSVDMAX_SHIFT 0
 #define I40E_GLHMC_LAN32BRSVDMAX_PMLAN32BRSVDMAX_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_LAN32BRSVDMAX_PMLAN32BRSVDMAX_SHIFT)
 
-#define I40E_GLHMC_LAN32BRSVDOBJSZ                         0x000C2098
+#define I40E_GLHMC_LAN32BRSVDOBJSZ                         0x000C2098 /* Reset: CORER */
 #define I40E_GLHMC_LAN32BRSVDOBJSZ_PMLAN32BRSVDOBJSZ_SHIFT 0
 #define I40E_GLHMC_LAN32BRSVDOBJSZ_PMLAN32BRSVDOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_LAN32BRSVDOBJSZ_PMLAN32BRSVDOBJSZ_SHIFT)
 
-#define I40E_GLHMC_LAN64BRSVD0BASE(_i)                      (0x000C6c00 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LAN64BRSVD0BASE(_i)                      (0x000C6c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LAN64BRSVD0BASE_MAX_INDEX                15
 #define I40E_GLHMC_LAN64BRSVD0BASE_FPMLAN64BRSVD0BASE_SHIFT 0
 #define I40E_GLHMC_LAN64BRSVD0BASE_FPMLAN64BRSVD0BASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_LAN64BRSVD0BASE_FPMLAN64BRSVD0BASE_SHIFT)
 
-#define I40E_GLHMC_LAN64BRSVD0CNT(_i)                     (0x000C6d00 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LAN64BRSVD0CNT(_i)                     (0x000C6d00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LAN64BRSVD0CNT_MAX_INDEX               15
 #define I40E_GLHMC_LAN64BRSVD0CNT_FPMLAN64BRSVD0CNT_SHIFT 0
 #define I40E_GLHMC_LAN64BRSVD0CNT_FPMLAN64BRSVD0CNT_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_LAN64BRSVD0CNT_FPMLAN64BRSVD0CNT_SHIFT)
 
-#define I40E_GLHMC_LAN64BRSVD0MAX                        0x000C20a4
+#define I40E_GLHMC_LAN64BRSVD0MAX                        0x000C20a4 /* Reset: CORER */
 #define I40E_GLHMC_LAN64BRSVD0MAX_PMLAN64BRSVD0MAX_SHIFT 0
 #define I40E_GLHMC_LAN64BRSVD0MAX_PMLAN64BRSVD0MAX_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_LAN64BRSVD0MAX_PMLAN64BRSVD0MAX_SHIFT)
 
-#define I40E_GLHMC_LAN64BRSVD0OBJSZ                          0x000C20a0
+#define I40E_GLHMC_LAN64BRSVD0OBJSZ                          0x000C20a0 /* Reset: CORER */
 #define I40E_GLHMC_LAN64BRSVD0OBJSZ_PMLAN64BRSVD0OBJSZ_SHIFT 0
 #define I40E_GLHMC_LAN64BRSVD0OBJSZ_PMLAN64BRSVD0OBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_LAN64BRSVD0OBJSZ_PMLAN64BRSVD0OBJSZ_SHIFT)
 
-#define I40E_GLHMC_LAN64BRSVD1BASE(_i)                      (0x000C6e00 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LAN64BRSVD1BASE(_i)                      (0x000C6e00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LAN64BRSVD1BASE_MAX_INDEX                15
 #define I40E_GLHMC_LAN64BRSVD1BASE_FPMLAN64BRSVD1BASE_SHIFT 0
 #define I40E_GLHMC_LAN64BRSVD1BASE_FPMLAN64BRSVD1BASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_LAN64BRSVD1BASE_FPMLAN64BRSVD1BASE_SHIFT)
 
-#define I40E_GLHMC_LAN64BRSVD1CNT(_i)                     (0x000C6f00 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_LAN64BRSVD1CNT(_i)                     (0x000C6f00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_LAN64BRSVD1CNT_MAX_INDEX               15
 #define I40E_GLHMC_LAN64BRSVD1CNT_FPMLAN64BRSVD1CNT_SHIFT 0
 #define I40E_GLHMC_LAN64BRSVD1CNT_FPMLAN64BRSVD1CNT_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_LAN64BRSVD1CNT_FPMLAN64BRSVD1CNT_SHIFT)
 
-#define I40E_GLHMC_LAN64BRSVD1MAX                        0x000C20ac
+#define I40E_GLHMC_LAN64BRSVD1MAX                        0x000C20ac /* Reset: CORER */
 #define I40E_GLHMC_LAN64BRSVD1MAX_PMLAN64BRSVD1MAX_SHIFT 0
 #define I40E_GLHMC_LAN64BRSVD1MAX_PMLAN64BRSVD1MAX_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_LAN64BRSVD1MAX_PMLAN64BRSVD1MAX_SHIFT)
 
-#define I40E_GLHMC_LAN64BRSVD1OBJSZ                          0x000C20a8
+#define I40E_GLHMC_LAN64BRSVD1OBJSZ                          0x000C20a8 /* Reset: CORER */
 #define I40E_GLHMC_LAN64BRSVD1OBJSZ_PMLAN64BRSVD1OBJSZ_SHIFT 0
 #define I40E_GLHMC_LAN64BRSVD1OBJSZ_PMLAN64BRSVD1OBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_LAN64BRSVD1OBJSZ_PMLAN64BRSVD1OBJSZ_SHIFT)
 
-#define I40E_GLHMC_OBJECTCACHECTL0(_i)                  (0x000C0900 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_OBJECTCACHECTL0(_i)                  (0x000C0900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_OBJECTCACHECTL0_MAX_INDEX            15
 #define I40E_GLHMC_OBJECTCACHECTL0_OBJ_PF_NUM_SHIFT     0
 #define I40E_GLHMC_OBJECTCACHECTL0_OBJ_PF_NUM_MASK      I40E_MASK(0xF, I40E_GLHMC_OBJECTCACHECTL0_OBJ_PF_NUM_SHIFT)
@@ -1204,23 +1210,23 @@
 #define I40E_GLHMC_OBJECTCACHECTL0_CMD_DONE_SHIFT       31
 #define I40E_GLHMC_OBJECTCACHECTL0_CMD_DONE_MASK        I40E_MASK(0x1, I40E_GLHMC_OBJECTCACHECTL0_CMD_DONE_SHIFT)
 
-#define I40E_GLHMC_OBJECTCACHECTL1(_i)             (0x000C0a00 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_OBJECTCACHECTL1(_i)             (0x000C0a00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_OBJECTCACHECTL1_MAX_INDEX       15
 #define I40E_GLHMC_OBJECTCACHECTL1_OBJ_INDEX_SHIFT 0
 #define I40E_GLHMC_OBJECTCACHECTL1_OBJ_INDEX_MASK  I40E_MASK(0xFFFFFFF, I40E_GLHMC_OBJECTCACHECTL1_OBJ_INDEX_SHIFT)
 
-#define I40E_GLHMC_PMATCFG                     0x000C2000
+#define I40E_GLHMC_PMATCFG                     0x000C2000 /* Reset: CORER */
 #define I40E_GLHMC_PMATCFG_CM_PE_WEIGHT_SHIFT  0
 #define I40E_GLHMC_PMATCFG_CM_PE_WEIGHT_MASK   I40E_MASK(0x1, I40E_GLHMC_PMATCFG_CM_PE_WEIGHT_SHIFT)
 #define I40E_GLHMC_PMATCFG_CM_LAN_WEIGHT_SHIFT 1
 #define I40E_GLHMC_PMATCFG_CM_LAN_WEIGHT_MASK  I40E_MASK(0x1, I40E_GLHMC_PMATCFG_CM_LAN_WEIGHT_SHIFT)
 
-#define I40E_GLHMC_PMFTABLE(_i)                        (0x000C0b00 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLHMC_PMFTABLE(_i)                        (0x000C0b00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLHMC_PMFTABLE_MAX_INDEX                  15
 #define I40E_GLHMC_PMFTABLE_PM_FCN_TBL_ENTRY_VLD_SHIFT 31
 #define I40E_GLHMC_PMFTABLE_PM_FCN_TBL_ENTRY_VLD_MASK  I40E_MASK(0x1, I40E_GLHMC_PMFTABLE_PM_FCN_TBL_ENTRY_VLD_SHIFT)
 
-#define I40E_GLPBLOC_CACHE_CTRL                     0x000A8000
+#define I40E_GLPBLOC_CACHE_CTRL                     0x000A8000 /* Reset: CORER */
 #define I40E_GLPBLOC_CACHE_CTRL_SCALE_FACTOR_SHIFT  0
 #define I40E_GLPBLOC_CACHE_CTRL_SCALE_FACTOR_MASK   I40E_MASK(0x3, I40E_GLPBLOC_CACHE_CTRL_SCALE_FACTOR_SHIFT)
 #define I40E_GLPBLOC_CACHE_CTRL_DBGMUX_EN_SHIFT     4
@@ -1230,13 +1236,13 @@
 #define I40E_GLPBLOC_CACHE_CTRL_DBGMUX_SEL_HI_SHIFT 16
 #define I40E_GLPBLOC_CACHE_CTRL_DBGMUX_SEL_HI_MASK  I40E_MASK(0x1F, I40E_GLPBLOC_CACHE_CTRL_DBGMUX_SEL_HI_SHIFT)
 
-#define I40E_GLPBLOC_CECC_ERR                         0x000A80B4
+#define I40E_GLPBLOC_CECC_ERR                         0x000A80B4 /* Reset: POR */
 #define I40E_GLPBLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT 0
 #define I40E_GLPBLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_GLPBLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT)
 #define I40E_GLPBLOC_CECC_ERR_COR_ECC_ERR_CNT_SHIFT   16
 #define I40E_GLPBLOC_CECC_ERR_COR_ECC_ERR_CNT_MASK    I40E_MASK(0xFFF, I40E_GLPBLOC_CECC_ERR_COR_ECC_ERR_CNT_SHIFT)
 
-#define I40E_GLPBLOC_ECC_CTL                           0x000A80AC
+#define I40E_GLPBLOC_ECC_CTL                           0x000A80AC /* Reset: POR */
 #define I40E_GLPBLOC_ECC_CTL_HOST_ECC_EN_SHIFT         0
 #define I40E_GLPBLOC_ECC_CTL_HOST_ECC_EN_MASK          I40E_MASK(0x1, I40E_GLPBLOC_ECC_CTL_HOST_ECC_EN_SHIFT)
 #define I40E_GLPBLOC_ECC_CTL_HOST_ECC_MASK_INT_SHIFT   1
@@ -1254,7 +1260,7 @@
 #define I40E_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT2_SHIFT  7
 #define I40E_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT2_MASK   I40E_MASK(0x1, I40E_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT2_SHIFT)
 
-#define I40E_GLPBLOC_ERRDATA0                  0x000A80A0
+#define I40E_GLPBLOC_ERRDATA0                  0x000A80A0 /* Reset: POR */
 #define I40E_GLPBLOC_ERRDATA0_ERROR_CODE_SHIFT 0
 #define I40E_GLPBLOC_ERRDATA0_ERROR_CODE_MASK  I40E_MASK(0x3F, I40E_GLPBLOC_ERRDATA0_ERROR_CODE_SHIFT)
 #define I40E_GLPBLOC_ERRDATA0_OBJ_TYPE_SHIFT   8
@@ -1266,11 +1272,11 @@
 #define I40E_GLPBLOC_ERRDATA0_PF_NUM_SHIFT     24
 #define I40E_GLPBLOC_ERRDATA0_PF_NUM_MASK      I40E_MASK(0xF, I40E_GLPBLOC_ERRDATA0_PF_NUM_SHIFT)
 
-#define I40E_GLPBLOC_ERRDATA1                 0x000A80A4
+#define I40E_GLPBLOC_ERRDATA1                 0x000A80A4 /* Reset: POR */
 #define I40E_GLPBLOC_ERRDATA1_OBJ_INDEX_SHIFT 0
 #define I40E_GLPBLOC_ERRDATA1_OBJ_INDEX_MASK  I40E_MASK(0xFFFFFFF, I40E_GLPBLOC_ERRDATA1_OBJ_INDEX_SHIFT)
 
-#define I40E_GLPBLOC_ERRDATA2              0x000A80A8
+#define I40E_GLPBLOC_ERRDATA2              0x000A80A8 /* Reset: POR */
 #define I40E_GLPBLOC_ERRDATA2_LENGTH_SHIFT 0
 #define I40E_GLPBLOC_ERRDATA2_LENGTH_MASK  I40E_MASK(0x7F, I40E_GLPBLOC_ERRDATA2_LENGTH_SHIFT)
 #define I40E_GLPBLOC_ERRDATA2_OFFSET_SHIFT 7
@@ -1280,99 +1286,99 @@
 #define I40E_GLPBLOC_ERRDATA2_TAG_SHIFT    23
 #define I40E_GLPBLOC_ERRDATA2_TAG_MASK     I40E_MASK(0x1FF, I40E_GLPBLOC_ERRDATA2_TAG_SHIFT)
 
-#define I40E_GLPBLOC_ERRINFO                   0x000A809C
+#define I40E_GLPBLOC_ERRINFO                   0x000A809C /* Reset: POR */
 #define I40E_GLPBLOC_ERRINFO_ERROR_VALID_SHIFT 0
 #define I40E_GLPBLOC_ERRINFO_ERROR_VALID_MASK  I40E_MASK(0x1, I40E_GLPBLOC_ERRINFO_ERROR_VALID_SHIFT)
 #define I40E_GLPBLOC_ERRINFO_ERROR_CNT_SHIFT   8
 #define I40E_GLPBLOC_ERRINFO_ERROR_CNT_MASK    I40E_MASK(0xFF, I40E_GLPBLOC_ERRINFO_ERROR_CNT_SHIFT)
 
-#define I40E_GLPBLOC_HECC_ERR                         0x000A80B0
+#define I40E_GLPBLOC_HECC_ERR                         0x000A80B0 /* Reset: POR */
 #define I40E_GLPBLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT 0
 #define I40E_GLPBLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_GLPBLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT)
 #define I40E_GLPBLOC_HECC_ERR_COR_ECC_ERR_CNT_SHIFT   16
 #define I40E_GLPBLOC_HECC_ERR_COR_ECC_ERR_CNT_MASK    I40E_MASK(0xFFF, I40E_GLPBLOC_HECC_ERR_COR_ECC_ERR_CNT_SHIFT)
 
-#define I40E_GLPBLOC_MRTE_OBJOFST                       0x000A8050
+#define I40E_GLPBLOC_MRTE_OBJOFST                       0x000A8050 /* Reset: CORER */
 #define I40E_GLPBLOC_MRTE_OBJOFST_OBJ_TYPE_OFFSET_SHIFT 0
 #define I40E_GLPBLOC_MRTE_OBJOFST_OBJ_TYPE_OFFSET_MASK  I40E_MASK(0x3FF, I40E_GLPBLOC_MRTE_OBJOFST_OBJ_TYPE_OFFSET_SHIFT)
 
-#define I40E_GLPBLOC_PBLE_OBJOFST                       0x000A804C
+#define I40E_GLPBLOC_PBLE_OBJOFST                       0x000A804C /* Reset: CORER */
 #define I40E_GLPBLOC_PBLE_OBJOFST_OBJ_TYPE_OFFSET_SHIFT 0
 #define I40E_GLPBLOC_PBLE_OBJOFST_OBJ_TYPE_OFFSET_MASK  I40E_MASK(0x3FF, I40E_GLPBLOC_PBLE_OBJOFST_OBJ_TYPE_OFFSET_SHIFT)
 
-#define I40E_GLPBLOC_STAT_CTL                   0x000A8004
+#define I40E_GLPBLOC_STAT_CTL                   0x000A8004 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_CTL_OBJECT_TYPE_SHIFT 0
 #define I40E_GLPBLOC_STAT_CTL_OBJECT_TYPE_MASK  I40E_MASK(0x1F, I40E_GLPBLOC_STAT_CTL_OBJECT_TYPE_SHIFT)
 
-#define I40E_GLPBLOC_STAT_OBJ_CNT                    0x000A8008
+#define I40E_GLPBLOC_STAT_OBJ_CNT                    0x000A8008 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_OBJ_CNT_OBJECT_COUNT_SHIFT 0
 #define I40E_GLPBLOC_STAT_OBJ_CNT_OBJECT_COUNT_MASK  I40E_MASK(0x3FFF, I40E_GLPBLOC_STAT_OBJ_CNT_OBJECT_COUNT_SHIFT)
 
-#define I40E_GLPBLOC_STAT_RD_DATA_IDLE_HI              0x000A8030
+#define I40E_GLPBLOC_STAT_RD_DATA_IDLE_HI              0x000A8030 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_SHIFT 0
 #define I40E_GLPBLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPBLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPBLOC_STAT_RD_DATA_IDLE_LO              0x000A802C
+#define I40E_GLPBLOC_STAT_RD_DATA_IDLE_LO              0x000A802C /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_SHIFT 0
 #define I40E_GLPBLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPBLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPBLOC_STAT_RD_DATA_XFER_HI              0x000A8038
+#define I40E_GLPBLOC_STAT_RD_DATA_XFER_HI              0x000A8038 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_RD_DATA_XFER_HI_CNT_HI_SHIFT 0
 #define I40E_GLPBLOC_STAT_RD_DATA_XFER_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPBLOC_STAT_RD_DATA_XFER_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPBLOC_STAT_RD_DATA_XFER_LO              0x000A8034
+#define I40E_GLPBLOC_STAT_RD_DATA_XFER_LO              0x000A8034 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_RD_DATA_XFER_LO_CNT_LO_SHIFT 0
 #define I40E_GLPBLOC_STAT_RD_DATA_XFER_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPBLOC_STAT_RD_DATA_XFER_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPBLOC_STAT_RD_HIT_HI              0x000A8010
+#define I40E_GLPBLOC_STAT_RD_HIT_HI              0x000A8010 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_RD_HIT_HI_CNT_HI_SHIFT 0
 #define I40E_GLPBLOC_STAT_RD_HIT_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPBLOC_STAT_RD_HIT_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPBLOC_STAT_RD_HIT_LO              0x000A800C
+#define I40E_GLPBLOC_STAT_RD_HIT_LO              0x000A800C /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_RD_HIT_LO_CNT_LO_SHIFT 0
 #define I40E_GLPBLOC_STAT_RD_HIT_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPBLOC_STAT_RD_HIT_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPBLOC_STAT_RD_MISS_HI              0x000A8018
+#define I40E_GLPBLOC_STAT_RD_MISS_HI              0x000A8018 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_RD_MISS_HI_CNT_HI_SHIFT 0
 #define I40E_GLPBLOC_STAT_RD_MISS_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPBLOC_STAT_RD_MISS_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPBLOC_STAT_RD_MISS_LO              0x000A8014
+#define I40E_GLPBLOC_STAT_RD_MISS_LO              0x000A8014 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_RD_MISS_LO_CNT_LO_SHIFT 0
 #define I40E_GLPBLOC_STAT_RD_MISS_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPBLOC_STAT_RD_MISS_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPBLOC_STAT_WR_DATA_IDLE_HI              0x000A8040
+#define I40E_GLPBLOC_STAT_WR_DATA_IDLE_HI              0x000A8040 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_SHIFT 0
 #define I40E_GLPBLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPBLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPBLOC_STAT_WR_DATA_IDLE_LO              0x000A803C
+#define I40E_GLPBLOC_STAT_WR_DATA_IDLE_LO              0x000A803C /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_SHIFT 0
 #define I40E_GLPBLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPBLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPBLOC_STAT_WR_DATA_XFER_HI              0x000A8048
+#define I40E_GLPBLOC_STAT_WR_DATA_XFER_HI              0x000A8048 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_WR_DATA_XFER_HI_CNT_HI_SHIFT 0
 #define I40E_GLPBLOC_STAT_WR_DATA_XFER_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPBLOC_STAT_WR_DATA_XFER_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPBLOC_STAT_WR_DATA_XFER_LO              0x000A8044
+#define I40E_GLPBLOC_STAT_WR_DATA_XFER_LO              0x000A8044 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_WR_DATA_XFER_LO_CNT_LO_SHIFT 0
 #define I40E_GLPBLOC_STAT_WR_DATA_XFER_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPBLOC_STAT_WR_DATA_XFER_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPBLOC_STAT_WR_HIT_HI              0x000A8020
+#define I40E_GLPBLOC_STAT_WR_HIT_HI              0x000A8020 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_WR_HIT_HI_CNT_HI_SHIFT 0
 #define I40E_GLPBLOC_STAT_WR_HIT_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPBLOC_STAT_WR_HIT_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPBLOC_STAT_WR_HIT_LO              0x000A801C
+#define I40E_GLPBLOC_STAT_WR_HIT_LO              0x000A801C /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_WR_HIT_LO_CNT_LO_SHIFT 0
 #define I40E_GLPBLOC_STAT_WR_HIT_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPBLOC_STAT_WR_HIT_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPBLOC_STAT_WR_MISS_HI              0x000A8028
+#define I40E_GLPBLOC_STAT_WR_MISS_HI              0x000A8028 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_WR_MISS_HI_CNT_HI_SHIFT 0
 #define I40E_GLPBLOC_STAT_WR_MISS_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPBLOC_STAT_WR_MISS_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPBLOC_STAT_WR_MISS_LO              0x000A8024
+#define I40E_GLPBLOC_STAT_WR_MISS_LO              0x000A8024 /* Reset: CORER */
 #define I40E_GLPBLOC_STAT_WR_MISS_LO_CNT_LO_SHIFT 0
 #define I40E_GLPBLOC_STAT_WR_MISS_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPBLOC_STAT_WR_MISS_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPDOC_CACHE_CTRL                     0x000D0000
+#define I40E_GLPDOC_CACHE_CTRL                     0x000D0000 /* Reset: CORER */
 #define I40E_GLPDOC_CACHE_CTRL_SCALE_FACTOR_SHIFT  0
 #define I40E_GLPDOC_CACHE_CTRL_SCALE_FACTOR_MASK   I40E_MASK(0x3, I40E_GLPDOC_CACHE_CTRL_SCALE_FACTOR_SHIFT)
 #define I40E_GLPDOC_CACHE_CTRL_DBGMUX_EN_SHIFT     4
@@ -1382,13 +1388,13 @@
 #define I40E_GLPDOC_CACHE_CTRL_DBGMUX_SEL_HI_SHIFT 16
 #define I40E_GLPDOC_CACHE_CTRL_DBGMUX_SEL_HI_MASK  I40E_MASK(0x1F, I40E_GLPDOC_CACHE_CTRL_DBGMUX_SEL_HI_SHIFT)
 
-#define I40E_GLPDOC_CECC_ERR                         0x000D0080
+#define I40E_GLPDOC_CECC_ERR                         0x000D0080 /* Reset: POR */
 #define I40E_GLPDOC_CECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT 0
 #define I40E_GLPDOC_CECC_ERR_UNCOR_ECC_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_GLPDOC_CECC_ERR_UNCOR_ECC_ERR_CNT_SHIFT)
 #define I40E_GLPDOC_CECC_ERR_COR_ECC_ERR_CNT_SHIFT   16
 #define I40E_GLPDOC_CECC_ERR_COR_ECC_ERR_CNT_MASK    I40E_MASK(0xFFF, I40E_GLPDOC_CECC_ERR_COR_ECC_ERR_CNT_SHIFT)
 
-#define I40E_GLPDOC_ECC_CTL                           0x000D007c
+#define I40E_GLPDOC_ECC_CTL                           0x000D007c /* Reset: POR */
 #define I40E_GLPDOC_ECC_CTL_HOST_ECC_EN_SHIFT         0
 #define I40E_GLPDOC_ECC_CTL_HOST_ECC_EN_MASK          I40E_MASK(0x1, I40E_GLPDOC_ECC_CTL_HOST_ECC_EN_SHIFT)
 #define I40E_GLPDOC_ECC_CTL_HOST_ECC_MASK_INT_SHIFT   1
@@ -1406,7 +1412,7 @@
 #define I40E_GLPDOC_ECC_CTL_CLIENT_ECC_INVERT2_SHIFT  7
 #define I40E_GLPDOC_ECC_CTL_CLIENT_ECC_INVERT2_MASK   I40E_MASK(0x1, I40E_GLPDOC_ECC_CTL_CLIENT_ECC_INVERT2_SHIFT)
 
-#define I40E_GLPDOC_ERRDATA0                  0x000D0070
+#define I40E_GLPDOC_ERRDATA0                  0x000D0070 /* Reset: POR */
 #define I40E_GLPDOC_ERRDATA0_ERROR_CODE_SHIFT 0
 #define I40E_GLPDOC_ERRDATA0_ERROR_CODE_MASK  I40E_MASK(0x3F, I40E_GLPDOC_ERRDATA0_ERROR_CODE_SHIFT)
 #define I40E_GLPDOC_ERRDATA0_OBJ_TYPE_SHIFT   8
@@ -1418,11 +1424,11 @@
 #define I40E_GLPDOC_ERRDATA0_PF_NUM_SHIFT     24
 #define I40E_GLPDOC_ERRDATA0_PF_NUM_MASK      I40E_MASK(0xF, I40E_GLPDOC_ERRDATA0_PF_NUM_SHIFT)
 
-#define I40E_GLPDOC_ERRDATA1                 0x000D0074
+#define I40E_GLPDOC_ERRDATA1                 0x000D0074 /* Reset: POR */
 #define I40E_GLPDOC_ERRDATA1_OBJ_INDEX_SHIFT 0
 #define I40E_GLPDOC_ERRDATA1_OBJ_INDEX_MASK  I40E_MASK(0xFFFFFFF, I40E_GLPDOC_ERRDATA1_OBJ_INDEX_SHIFT)
 
-#define I40E_GLPDOC_ERRDATA2              0x000D0078
+#define I40E_GLPDOC_ERRDATA2              0x000D0078 /* Reset: POR */
 #define I40E_GLPDOC_ERRDATA2_LENGTH_SHIFT 0
 #define I40E_GLPDOC_ERRDATA2_LENGTH_MASK  I40E_MASK(0x7F, I40E_GLPDOC_ERRDATA2_LENGTH_SHIFT)
 #define I40E_GLPDOC_ERRDATA2_OFFSET_SHIFT 7
@@ -1432,55 +1438,55 @@
 #define I40E_GLPDOC_ERRDATA2_TAG_SHIFT    23
 #define I40E_GLPDOC_ERRDATA2_TAG_MASK     I40E_MASK(0x1FF, I40E_GLPDOC_ERRDATA2_TAG_SHIFT)
 
-#define I40E_GLPDOC_ERRINFO                   0x000D006C
+#define I40E_GLPDOC_ERRINFO                   0x000D006C /* Reset: POR */
 #define I40E_GLPDOC_ERRINFO_ERROR_VALID_SHIFT 0
 #define I40E_GLPDOC_ERRINFO_ERROR_VALID_MASK  I40E_MASK(0x1, I40E_GLPDOC_ERRINFO_ERROR_VALID_SHIFT)
 #define I40E_GLPDOC_ERRINFO_ERROR_CNT_SHIFT   8
 #define I40E_GLPDOC_ERRINFO_ERROR_CNT_MASK    I40E_MASK(0xFF, I40E_GLPDOC_ERRINFO_ERROR_CNT_SHIFT)
 
-#define I40E_GLPDOC_STAT_CTL                   0x000D0004
+#define I40E_GLPDOC_STAT_CTL                   0x000D0004 /* Reset: CORER */
 #define I40E_GLPDOC_STAT_CTL_OBJECT_TYPE_SHIFT 0
 #define I40E_GLPDOC_STAT_CTL_OBJECT_TYPE_MASK  I40E_MASK(0x1F, I40E_GLPDOC_STAT_CTL_OBJECT_TYPE_SHIFT)
 
-#define I40E_GLPDOC_STAT_OBJ_CNT                    0x000D0008
+#define I40E_GLPDOC_STAT_OBJ_CNT                    0x000D0008 /* Reset: CORER */
 #define I40E_GLPDOC_STAT_OBJ_CNT_OBJECT_COUNT_SHIFT 0
 #define I40E_GLPDOC_STAT_OBJ_CNT_OBJECT_COUNT_MASK  I40E_MASK(0x3FFF, I40E_GLPDOC_STAT_OBJ_CNT_OBJECT_COUNT_SHIFT)
 
-#define I40E_GLPDOC_STAT_RD_DATA_IDLE_HI              0x000D0020
+#define I40E_GLPDOC_STAT_RD_DATA_IDLE_HI              0x000D0020 /* Reset: CORER */
 #define I40E_GLPDOC_STAT_RD_DATA_IDLE_HI_CNT_HI_SHIFT 0
 #define I40E_GLPDOC_STAT_RD_DATA_IDLE_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPDOC_STAT_RD_DATA_IDLE_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPDOC_STAT_RD_DATA_IDLE_LO              0x000D001C
+#define I40E_GLPDOC_STAT_RD_DATA_IDLE_LO              0x000D001C /* Reset: CORER */
 #define I40E_GLPDOC_STAT_RD_DATA_IDLE_LO_CNT_LO_SHIFT 0
 #define I40E_GLPDOC_STAT_RD_DATA_IDLE_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPDOC_STAT_RD_DATA_IDLE_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPDOC_STAT_RD_DATA_XFER_HI              0x000D0028
+#define I40E_GLPDOC_STAT_RD_DATA_XFER_HI              0x000D0028 /* Reset: CORER */
 #define I40E_GLPDOC_STAT_RD_DATA_XFER_HI_CNT_HI_SHIFT 0
 #define I40E_GLPDOC_STAT_RD_DATA_XFER_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPDOC_STAT_RD_DATA_XFER_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPDOC_STAT_RD_DATA_XFER_LO              0x000D0024
+#define I40E_GLPDOC_STAT_RD_DATA_XFER_LO              0x000D0024 /* Reset: CORER */
 #define I40E_GLPDOC_STAT_RD_DATA_XFER_LO_CNT_LO_SHIFT 0
 #define I40E_GLPDOC_STAT_RD_DATA_XFER_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPDOC_STAT_RD_DATA_XFER_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPDOC_STAT_RD_HIT_HI              0x000D0010
+#define I40E_GLPDOC_STAT_RD_HIT_HI              0x000D0010 /* Reset: CORER */
 #define I40E_GLPDOC_STAT_RD_HIT_HI_CNT_HI_SHIFT 0
 #define I40E_GLPDOC_STAT_RD_HIT_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPDOC_STAT_RD_HIT_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPDOC_STAT_RD_HIT_LO              0x000D000C
+#define I40E_GLPDOC_STAT_RD_HIT_LO              0x000D000C /* Reset: CORER */
 #define I40E_GLPDOC_STAT_RD_HIT_LO_CNT_LO_SHIFT 0
 #define I40E_GLPDOC_STAT_RD_HIT_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPDOC_STAT_RD_HIT_LO_CNT_LO_SHIFT)
 
-#define I40E_GLPDOC_STAT_RD_MISS_HI              0x000D0018
+#define I40E_GLPDOC_STAT_RD_MISS_HI              0x000D0018 /* Reset: CORER */
 #define I40E_GLPDOC_STAT_RD_MISS_HI_CNT_HI_SHIFT 0
 #define I40E_GLPDOC_STAT_RD_MISS_HI_CNT_HI_MASK  I40E_MASK(0xFFFFFF, I40E_GLPDOC_STAT_RD_MISS_HI_CNT_HI_SHIFT)
 
-#define I40E_GLPDOC_STAT_RD_MISS_LO              0x000D0014
+#define I40E_GLPDOC_STAT_RD_MISS_LO              0x000D0014 /* Reset: CORER */
 #define I40E_GLPDOC_STAT_RD_MISS_LO_CNT_LO_SHIFT 0
 #define I40E_GLPDOC_STAT_RD_MISS_LO_CNT_LO_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPDOC_STAT_RD_MISS_LO_CNT_LO_SHIFT)
 
 /* PF - Intel Internal Registers */
 
-#define I40E_DPU_IMEM_CFG                    0x00051064
+#define I40E_DPU_IMEM_CFG                    0x00051064 /* Reset: POR */
 #define I40E_DPU_IMEM_CFG_ECC_EN_SHIFT       0
 #define I40E_DPU_IMEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_DPU_IMEM_CFG_ECC_EN_SHIFT)
 #define I40E_DPU_IMEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -1502,7 +1508,7 @@
 #define I40E_DPU_IMEM_CFG_RM_SHIFT           16
 #define I40E_DPU_IMEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_DPU_IMEM_CFG_RM_SHIFT)
 
-#define I40E_DPU_IMEM_STATUS                        0x00051068
+#define I40E_DPU_IMEM_STATUS                        0x00051068 /* Reset: POR */
 #define I40E_DPU_IMEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_DPU_IMEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_DPU_IMEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_DPU_IMEM_STATUS_ECC_FIX_SHIFT          1
@@ -1512,7 +1518,7 @@
 #define I40E_DPU_IMEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_DPU_IMEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_DPU_IMEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_DPU_RECIPE_ADDR_CFG                    0x0005106C
+#define I40E_DPU_RECIPE_ADDR_CFG                    0x0005106C /* Reset: POR */
 #define I40E_DPU_RECIPE_ADDR_CFG_ECC_EN_SHIFT       0
 #define I40E_DPU_RECIPE_ADDR_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_DPU_RECIPE_ADDR_CFG_ECC_EN_SHIFT)
 #define I40E_DPU_RECIPE_ADDR_CFG_ECC_INVERT_1_SHIFT 1
@@ -1534,7 +1540,7 @@
 #define I40E_DPU_RECIPE_ADDR_CFG_RM_SHIFT           16
 #define I40E_DPU_RECIPE_ADDR_CFG_RM_MASK            I40E_MASK(0xF, I40E_DPU_RECIPE_ADDR_CFG_RM_SHIFT)
 
-#define I40E_DPU_RECIPE_ADDR_STATUS                        0x00051070
+#define I40E_DPU_RECIPE_ADDR_STATUS                        0x00051070 /* Reset: POR */
 #define I40E_DPU_RECIPE_ADDR_STATUS_ECC_ERR_SHIFT          0
 #define I40E_DPU_RECIPE_ADDR_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_DPU_RECIPE_ADDR_STATUS_ECC_ERR_SHIFT)
 #define I40E_DPU_RECIPE_ADDR_STATUS_ECC_FIX_SHIFT          1
@@ -1544,15 +1550,15 @@
 #define I40E_DPU_RECIPE_ADDR_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_DPU_RECIPE_ADDR_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_DPU_RECIPE_ADDR_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_FLEEP_ECC_COR_ERR           0x000B6150
+#define I40E_FLEEP_ECC_COR_ERR           0x000B6150 /* Reset: POR */
 #define I40E_FLEEP_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_FLEEP_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_FLEEP_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_FLEEP_ECC_UNCOR_ERR           0x000B614C
+#define I40E_FLEEP_ECC_UNCOR_ERR           0x000B614C /* Reset: POR */
 #define I40E_FLEEP_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_FLEEP_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_FLEEP_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_FLEEP_MEM_CFG                    0x000B6144
+#define I40E_FLEEP_MEM_CFG                    0x000B6144 /* Reset: POR */
 #define I40E_FLEEP_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_FLEEP_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_FLEEP_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_FLEEP_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -1574,7 +1580,7 @@
 #define I40E_FLEEP_MEM_CFG_RM_SHIFT           16
 #define I40E_FLEEP_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_FLEEP_MEM_CFG_RM_SHIFT)
 
-#define I40E_FLEEP_MEM_STATUS                        0x000B6148
+#define I40E_FLEEP_MEM_STATUS                        0x000B6148 /* Reset: POR */
 #define I40E_FLEEP_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_FLEEP_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_FLEEP_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_FLEEP_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -1584,7 +1590,7 @@
 #define I40E_FLEEP_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_FLEEP_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_FLEEP_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_FOC_CACHE_DBG_CTL              0x000AA0A4
+#define I40E_FOC_CACHE_DBG_CTL              0x000AA0A4 /* Reset: CORER */
 #define I40E_FOC_CACHE_DBG_CTL_ADR_SHIFT    0
 #define I40E_FOC_CACHE_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_FOC_CACHE_DBG_CTL_ADR_SHIFT)
 #define I40E_FOC_CACHE_DBG_CTL_DW_SEL_SHIFT 18
@@ -1594,11 +1600,11 @@
 #define I40E_FOC_CACHE_DBG_CTL_DONE_SHIFT   31
 #define I40E_FOC_CACHE_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_FOC_CACHE_DBG_CTL_DONE_SHIFT)
 
-#define I40E_FOC_CACHE_DBG_DATA             0x000AA0A8
+#define I40E_FOC_CACHE_DBG_DATA             0x000AA0A8 /* Reset: CORER */
 #define I40E_FOC_CACHE_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_FOC_CACHE_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_FOC_CACHE_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_FOC_CACHE_MEM_CFG                    0x000AA064
+#define I40E_FOC_CACHE_MEM_CFG                    0x000AA064 /* Reset: POR */
 #define I40E_FOC_CACHE_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_FOC_CACHE_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_FOC_CACHE_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_FOC_CACHE_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -1620,7 +1626,7 @@
 #define I40E_FOC_CACHE_MEM_CFG_RM_SHIFT           16
 #define I40E_FOC_CACHE_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_FOC_CACHE_MEM_CFG_RM_SHIFT)
 
-#define I40E_FOC_CAHCE_MEM_STATUS                        0x000AA068
+#define I40E_FOC_CAHCE_MEM_STATUS                        0x000AA068 /* Reset: POR */
 #define I40E_FOC_CAHCE_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_FOC_CAHCE_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_FOC_CAHCE_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_FOC_CAHCE_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -1630,15 +1636,15 @@
 #define I40E_FOC_CAHCE_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_FOC_CAHCE_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_FOC_CAHCE_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_FOC_ECC_COR_ERR           0x000AA098
+#define I40E_FOC_ECC_COR_ERR           0x000AA098 /* Reset: POR */
 #define I40E_FOC_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_FOC_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_FOC_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_FOC_ECC_UNCOR_ERR           0x000AA094
+#define I40E_FOC_ECC_UNCOR_ERR           0x000AA094 /* Reset: POR */
 #define I40E_FOC_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_FOC_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_FOC_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_FOC_EVICT_MEM_CFG                    0x000AA084
+#define I40E_FOC_EVICT_MEM_CFG                    0x000AA084 /* Reset: POR */
 #define I40E_FOC_EVICT_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_FOC_EVICT_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_FOC_EVICT_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_FOC_EVICT_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -1660,7 +1666,7 @@
 #define I40E_FOC_EVICT_MEM_CFG_RM_SHIFT           16
 #define I40E_FOC_EVICT_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_FOC_EVICT_MEM_CFG_RM_SHIFT)
 
-#define I40E_FOC_EVICT_MEM_STATUS                        0x000AA088
+#define I40E_FOC_EVICT_MEM_STATUS                        0x000AA088 /* Reset: POR */
 #define I40E_FOC_EVICT_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_FOC_EVICT_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_FOC_EVICT_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_FOC_EVICT_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -1670,7 +1676,7 @@
 #define I40E_FOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_FOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_FOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_FOC_FD_DBG_CTL              0x000AA0B4
+#define I40E_FOC_FD_DBG_CTL              0x000AA0B4 /* Reset: CORER */
 #define I40E_FOC_FD_DBG_CTL_ADR_SHIFT    0
 #define I40E_FOC_FD_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_FOC_FD_DBG_CTL_ADR_SHIFT)
 #define I40E_FOC_FD_DBG_CTL_DW_SEL_SHIFT 18
@@ -1680,11 +1686,11 @@
 #define I40E_FOC_FD_DBG_CTL_DONE_SHIFT   31
 #define I40E_FOC_FD_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_FOC_FD_DBG_CTL_DONE_SHIFT)
 
-#define I40E_FOC_FD_DBG_DATA             0x000AA0B8
+#define I40E_FOC_FD_DBG_DATA             0x000AA0B8 /* Reset: CORER */
 #define I40E_FOC_FD_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_FOC_FD_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_FOC_FD_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_FOC_FD_MEM_CFG                    0x000AA08C
+#define I40E_FOC_FD_MEM_CFG                    0x000AA08C /* Reset: POR */
 #define I40E_FOC_FD_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_FOC_FD_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_FOC_FD_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_FOC_FD_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -1706,7 +1712,7 @@
 #define I40E_FOC_FD_MEM_CFG_RM_SHIFT           16
 #define I40E_FOC_FD_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_FOC_FD_MEM_CFG_RM_SHIFT)
 
-#define I40E_FOC_FD_MEM_STATUS                        0x000AA090
+#define I40E_FOC_FD_MEM_STATUS                        0x000AA090 /* Reset: POR */
 #define I40E_FOC_FD_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_FOC_FD_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_FOC_FD_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_FOC_FD_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -1716,7 +1722,7 @@
 #define I40E_FOC_FD_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_FOC_FD_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_FOC_FD_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_FOC_FILL_MEM_CFG                    0x000AA074
+#define I40E_FOC_FILL_MEM_CFG                    0x000AA074 /* Reset: POR */
 #define I40E_FOC_FILL_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_FOC_FILL_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_FOC_FILL_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_FOC_FILL_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -1738,7 +1744,7 @@
 #define I40E_FOC_FILL_MEM_CFG_RM_SHIFT           16
 #define I40E_FOC_FILL_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_FOC_FILL_MEM_CFG_RM_SHIFT)
 
-#define I40E_FOC_FILL_MEM_STATUS                        0x000AA078
+#define I40E_FOC_FILL_MEM_STATUS                        0x000AA078 /* Reset: POR */
 #define I40E_FOC_FILL_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_FOC_FILL_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_FOC_FILL_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_FOC_FILL_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -1748,7 +1754,7 @@
 #define I40E_FOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_FOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_FOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_FOC_TAG_DBG_CTL              0x000AA09C
+#define I40E_FOC_TAG_DBG_CTL              0x000AA09C /* Reset: CORER */
 #define I40E_FOC_TAG_DBG_CTL_ADR_SHIFT    0
 #define I40E_FOC_TAG_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_FOC_TAG_DBG_CTL_ADR_SHIFT)
 #define I40E_FOC_TAG_DBG_CTL_DW_SEL_SHIFT 18
@@ -1758,11 +1764,11 @@
 #define I40E_FOC_TAG_DBG_CTL_DONE_SHIFT   31
 #define I40E_FOC_TAG_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_FOC_TAG_DBG_CTL_DONE_SHIFT)
 
-#define I40E_FOC_TAG_DBG_DATA             0x000AA0A0
+#define I40E_FOC_TAG_DBG_DATA             0x000AA0A0 /* Reset: CORER */
 #define I40E_FOC_TAG_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_FOC_TAG_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_FOC_TAG_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_FOC_TAG_MEM_CFG                    0x000AA06C
+#define I40E_FOC_TAG_MEM_CFG                    0x000AA06C /* Reset: POR */
 #define I40E_FOC_TAG_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_FOC_TAG_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_FOC_TAG_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_FOC_TAG_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -1784,7 +1790,7 @@
 #define I40E_FOC_TAG_MEM_CFG_RM_SHIFT           16
 #define I40E_FOC_TAG_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_FOC_TAG_MEM_CFG_RM_SHIFT)
 
-#define I40E_FOC_TAG_MEM_STATUS                        0x000AA070
+#define I40E_FOC_TAG_MEM_STATUS                        0x000AA070 /* Reset: POR */
 #define I40E_FOC_TAG_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_FOC_TAG_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_FOC_TAG_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_FOC_TAG_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -1794,15 +1800,15 @@
 #define I40E_FOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_FOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_FOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_FVL_STAT_ECC_COR_ERR           0x003800F4
+#define I40E_FVL_STAT_ECC_COR_ERR           0x003800F4 /* Reset: POR */
 #define I40E_FVL_STAT_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_FVL_STAT_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_FVL_STAT_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_FVL_STAT_ECC_UNCOR_ERR           0x003800F0
+#define I40E_FVL_STAT_ECC_UNCOR_ERR           0x003800F0 /* Reset: POR */
 #define I40E_FVL_STAT_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_FVL_STAT_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_FVL_STAT_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_FVL_STAT_MEM_CFG(_i)                (0x00380000 + ((_i) * 4)) /* _i=0...29 */
+#define I40E_FVL_STAT_MEM_CFG(_i)                (0x00380000 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */
 #define I40E_FVL_STAT_MEM_CFG_MAX_INDEX          29
 #define I40E_FVL_STAT_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_FVL_STAT_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_FVL_STAT_MEM_CFG_ECC_EN_SHIFT)
@@ -1825,7 +1831,7 @@
 #define I40E_FVL_STAT_MEM_CFG_RM_SHIFT           16
 #define I40E_FVL_STAT_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_FVL_STAT_MEM_CFG_RM_SHIFT)
 
-#define I40E_FVL_STAT_MEM_STATUS(_i)                    (0x00380078 + ((_i) * 4)) /* _i=0...29 */
+#define I40E_FVL_STAT_MEM_STATUS(_i)                    (0x00380078 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */
 #define I40E_FVL_STAT_MEM_STATUS_MAX_INDEX              29
 #define I40E_FVL_STAT_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_FVL_STAT_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_FVL_STAT_MEM_STATUS_ECC_ERR_SHIFT)
@@ -1836,23 +1842,23 @@
 #define I40E_FVL_STAT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_FVL_STAT_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_FVL_STAT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_GL_CRITERRMODMASK0                    0x000B4020
+#define I40E_GL_CRITERRMODMASK0                    0x000B4020 /* Reset: CORER */
 #define I40E_GL_CRITERRMODMASK0_MODULE_MASK0_SHIFT 1
 #define I40E_GL_CRITERRMODMASK0_MODULE_MASK0_MASK  I40E_MASK(0x7FFFFFFF, I40E_GL_CRITERRMODMASK0_MODULE_MASK0_SHIFT)
 
-#define I40E_GL_CRITERRMODMASK1                    0x000B4024
+#define I40E_GL_CRITERRMODMASK1                    0x000B4024 /* Reset: CORER */
 #define I40E_GL_CRITERRMODMASK1_MODULE_MASK1_SHIFT 1
 #define I40E_GL_CRITERRMODMASK1_MODULE_MASK1_MASK  I40E_MASK(0x7FFFFFFF, I40E_GL_CRITERRMODMASK1_MODULE_MASK1_SHIFT)
 
-#define I40E_GL_CRITERRMODMASK2                    0x000B4028
+#define I40E_GL_CRITERRMODMASK2                    0x000B4028 /* Reset: CORER */
 #define I40E_GL_CRITERRMODMASK2_MODULE_MASK2_SHIFT 1
 #define I40E_GL_CRITERRMODMASK2_MODULE_MASK2_MASK  I40E_MASK(0x7FFFFFFF, I40E_GL_CRITERRMODMASK2_MODULE_MASK2_SHIFT)
 
-#define I40E_GL_CRITERRMODMASK3                    0x000B402C
+#define I40E_GL_CRITERRMODMASK3                    0x000B402C /* Reset: CORER */
 #define I40E_GL_CRITERRMODMASK3_MODULE_MASK3_SHIFT 1
 #define I40E_GL_CRITERRMODMASK3_MODULE_MASK3_MASK  I40E_MASK(0x7FFFFFFF, I40E_GL_CRITERRMODMASK3_MODULE_MASK3_SHIFT)
 
-#define I40E_GL_CRITERRTRGTMASK0                           0x000B4040
+#define I40E_GL_CRITERRTRGTMASK0                           0x000B4040 /* Reset: CORER */
 #define I40E_GL_CRITERRTRGTMASK0_TRGT_MATCH_0_INST_SHIFT   0
 #define I40E_GL_CRITERRTRGTMASK0_TRGT_MATCH_0_INST_MASK    I40E_MASK(0x3F, I40E_GL_CRITERRTRGTMASK0_TRGT_MATCH_0_INST_SHIFT)
 #define I40E_GL_CRITERRTRGTMASK0_TRGT_MATCH_0_TYPE_SHIFT   6
@@ -1866,7 +1872,7 @@
 #define I40E_GL_CRITERRTRGTMASK0_TRGT_MATCH_1_MODULE_SHIFT 24
 #define I40E_GL_CRITERRTRGTMASK0_TRGT_MATCH_1_MODULE_MASK  I40E_MASK(0xFF, I40E_GL_CRITERRTRGTMASK0_TRGT_MATCH_1_MODULE_SHIFT)
 
-#define I40E_GL_CRITERRTRGTMASK1                           0x000B4044
+#define I40E_GL_CRITERRTRGTMASK1                           0x000B4044 /* Reset: CORER */
 #define I40E_GL_CRITERRTRGTMASK1_TRGT_MATCH_2_INST_SHIFT   0
 #define I40E_GL_CRITERRTRGTMASK1_TRGT_MATCH_2_INST_MASK    I40E_MASK(0x3F, I40E_GL_CRITERRTRGTMASK1_TRGT_MATCH_2_INST_SHIFT)
 #define I40E_GL_CRITERRTRGTMASK1_TRGT_MATCH_2_TYPE_SHIFT   6
@@ -1880,7 +1886,7 @@
 #define I40E_GL_CRITERRTRGTMASK1_TRGT_MATCH_3_MODULE_SHIFT 24
 #define I40E_GL_CRITERRTRGTMASK1_TRGT_MATCH_3_MODULE_MASK  I40E_MASK(0xFF, I40E_GL_CRITERRTRGTMASK1_TRGT_MATCH_3_MODULE_SHIFT)
 
-#define I40E_GL_CRITERRTRGTMASK2                           0x000B4048
+#define I40E_GL_CRITERRTRGTMASK2                           0x000B4048 /* Reset: CORER */
 #define I40E_GL_CRITERRTRGTMASK2_TRGT_MATCH_4_INST_SHIFT   0
 #define I40E_GL_CRITERRTRGTMASK2_TRGT_MATCH_4_INST_MASK    I40E_MASK(0x3F, I40E_GL_CRITERRTRGTMASK2_TRGT_MATCH_4_INST_SHIFT)
 #define I40E_GL_CRITERRTRGTMASK2_TRGT_MATCH_4_TYPE_SHIFT   6
@@ -1894,7 +1900,7 @@
 #define I40E_GL_CRITERRTRGTMASK2_TRGT_MATCH_5_MODULE_SHIFT 24
 #define I40E_GL_CRITERRTRGTMASK2_TRGT_MATCH_5_MODULE_MASK  I40E_MASK(0xFF, I40E_GL_CRITERRTRGTMASK2_TRGT_MATCH_5_MODULE_SHIFT)
 
-#define I40E_GL_CRITERRTRGTMASK3                           0x000B404C
+#define I40E_GL_CRITERRTRGTMASK3                           0x000B404C /* Reset: CORER */
 #define I40E_GL_CRITERRTRGTMASK3_TRGT_MATCH_6_INST_SHIFT   0
 #define I40E_GL_CRITERRTRGTMASK3_TRGT_MATCH_6_INST_MASK    I40E_MASK(0x3F, I40E_GL_CRITERRTRGTMASK3_TRGT_MATCH_6_INST_SHIFT)
 #define I40E_GL_CRITERRTRGTMASK3_TRGT_MATCH_6_TYPE_SHIFT   6
@@ -1908,7 +1914,7 @@
 #define I40E_GL_CRITERRTRGTMASK3_TRGT_MATCH_7_MODULE_SHIFT 24
 #define I40E_GL_CRITERRTRGTMASK3_TRGT_MATCH_7_MODULE_MASK  I40E_MASK(0xFF, I40E_GL_CRITERRTRGTMASK3_TRGT_MATCH_7_MODULE_SHIFT)
 
-#define I40E_GL_CRITERRTRGTMASK4                           0x000B4050
+#define I40E_GL_CRITERRTRGTMASK4                           0x000B4050 /* Reset: CORER */
 #define I40E_GL_CRITERRTRGTMASK4_TRGT_MATCH_8_INST_SHIFT   0
 #define I40E_GL_CRITERRTRGTMASK4_TRGT_MATCH_8_INST_MASK    I40E_MASK(0x3F, I40E_GL_CRITERRTRGTMASK4_TRGT_MATCH_8_INST_SHIFT)
 #define I40E_GL_CRITERRTRGTMASK4_TRGT_MATCH_8_TYPE_SHIFT   6
@@ -1922,7 +1928,7 @@
 #define I40E_GL_CRITERRTRGTMASK4_TRGT_MATCH_9_MODULE_SHIFT 24
 #define I40E_GL_CRITERRTRGTMASK4_TRGT_MATCH_9_MODULE_MASK  I40E_MASK(0xFF, I40E_GL_CRITERRTRGTMASK4_TRGT_MATCH_9_MODULE_SHIFT)
 
-#define I40E_GL_CRITERRTRGTMASK5                            0x000B4054
+#define I40E_GL_CRITERRTRGTMASK5                            0x000B4054 /* Reset: CORER */
 #define I40E_GL_CRITERRTRGTMASK5_TRGT_MATCH_10_INST_SHIFT   0
 #define I40E_GL_CRITERRTRGTMASK5_TRGT_MATCH_10_INST_MASK    I40E_MASK(0x3F, I40E_GL_CRITERRTRGTMASK5_TRGT_MATCH_10_INST_SHIFT)
 #define I40E_GL_CRITERRTRGTMASK5_TRGT_MATCH_10_TYPE_SHIFT   6
@@ -1936,7 +1942,7 @@
 #define I40E_GL_CRITERRTRGTMASK5_TRGT_MATCH_11_MODULE_SHIFT 24
 #define I40E_GL_CRITERRTRGTMASK5_TRGT_MATCH_11_MODULE_MASK  I40E_MASK(0xFF, I40E_GL_CRITERRTRGTMASK5_TRGT_MATCH_11_MODULE_SHIFT)
 
-#define I40E_GL_CRITERRTRGTMASK6                            0x000B4058
+#define I40E_GL_CRITERRTRGTMASK6                            0x000B4058 /* Reset: CORER */
 #define I40E_GL_CRITERRTRGTMASK6_TRGT_MATCH_12_INST_SHIFT   0
 #define I40E_GL_CRITERRTRGTMASK6_TRGT_MATCH_12_INST_MASK    I40E_MASK(0x3F, I40E_GL_CRITERRTRGTMASK6_TRGT_MATCH_12_INST_SHIFT)
 #define I40E_GL_CRITERRTRGTMASK6_TRGT_MATCH_12_TYPE_SHIFT   6
@@ -1950,7 +1956,7 @@
 #define I40E_GL_CRITERRTRGTMASK6_TRGT_MATCH_13_MODULE_SHIFT 24
 #define I40E_GL_CRITERRTRGTMASK6_TRGT_MATCH_13_MODULE_MASK  I40E_MASK(0xFF, I40E_GL_CRITERRTRGTMASK6_TRGT_MATCH_13_MODULE_SHIFT)
 
-#define I40E_GL_CRITERRTRGTMASK7                            0x000B405C
+#define I40E_GL_CRITERRTRGTMASK7                            0x000B405C /* Reset: CORER */
 #define I40E_GL_CRITERRTRGTMASK7_TRGT_MATCH_14_INST_SHIFT   0
 #define I40E_GL_CRITERRTRGTMASK7_TRGT_MATCH_14_INST_MASK    I40E_MASK(0x3F, I40E_GL_CRITERRTRGTMASK7_TRGT_MATCH_14_INST_SHIFT)
 #define I40E_GL_CRITERRTRGTMASK7_TRGT_MATCH_14_TYPE_SHIFT   6
@@ -1964,17 +1970,21 @@
 #define I40E_GL_CRITERRTRGTMASK7_TRGT_MATCH_15_MODULE_SHIFT 24
 #define I40E_GL_CRITERRTRGTMASK7_TRGT_MATCH_15_MODULE_MASK  I40E_MASK(0xFF, I40E_GL_CRITERRTRGTMASK7_TRGT_MATCH_15_MODULE_SHIFT)
 
-#define I40E_GL_DBGEMPR                0x00083108
+#define I40E_GL_DBG_DATA                   0x0026998C /* Reset: CORER */
+#define I40E_GL_DBG_DATA_GL_DBG_DATA_SHIFT 0
+#define I40E_GL_DBG_DATA_GL_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_DBG_DATA_GL_DBG_DATA_SHIFT)
+
+#define I40E_GL_DBGEMPR                0x00083108 /* Reset: EMPR */
 #define I40E_GL_DBGEMPR_RSV_DATA_SHIFT 0
 #define I40E_GL_DBGEMPR_RSV_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_DBGEMPR_RSV_DATA_SHIFT)
 
-#define I40E_GL_DBGPOR                        0x00083104
+#define I40E_GL_DBGPOR                        0x00083104 /* Reset: POR */
 #define I40E_GL_DBGPOR_ROM_EMPR_TRIGGER_SHIFT 0
 #define I40E_GL_DBGPOR_ROM_EMPR_TRIGGER_MASK  I40E_MASK(0x1, I40E_GL_DBGPOR_ROM_EMPR_TRIGGER_SHIFT)
 #define I40E_GL_DBGPOR_RSV_DATA_SHIFT         1
 #define I40E_GL_DBGPOR_RSV_DATA_MASK          I40E_MASK(0x7FFFFFFF, I40E_GL_DBGPOR_RSV_DATA_SHIFT)
 
-#define I40E_GL_DBGRST                      0x0008310C
+#define I40E_GL_DBGRST                      0x0008310C /* Reset: POR */
 #define I40E_GL_DBGRST_PRST_RSV_DATA_SHIFT  0
 #define I40E_GL_DBGRST_PRST_RSV_DATA_MASK   I40E_MASK(0xFF, I40E_GL_DBGRST_PRST_RSV_DATA_SHIFT)
 #define I40E_GL_DBGRST_IBR_RSV_DATA_SHIFT   8
@@ -1984,7 +1994,7 @@
 #define I40E_GL_DBGRST_CORER_RSV_DATA_SHIFT 24
 #define I40E_GL_DBGRST_CORER_RSV_DATA_MASK  I40E_MASK(0xFF, I40E_GL_DBGRST_CORER_RSV_DATA_SHIFT)
 
-#define I40E_GL_MDEF_TR_CFG                   0x00269A5C
+#define I40E_GL_MDEF_TR_CFG                   0x00269A5C /* Reset: CORER */
 #define I40E_GL_MDEF_TR_CFG_TCP_TR_IDX_SHIFT  0
 #define I40E_GL_MDEF_TR_CFG_TCP_TR_IDX_MASK   I40E_MASK(0x3F, I40E_GL_MDEF_TR_CFG_TCP_TR_IDX_SHIFT)
 #define I40E_GL_MDEF_TR_CFG_UDP_TR_IDX_SHIFT  6
@@ -1996,15 +2006,15 @@
 #define I40E_GL_MDEF_TR_CFG_VLAN_TR_IDX_SHIFT 24
 #define I40E_GL_MDEF_TR_CFG_VLAN_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_MDEF_TR_CFG_VLAN_TR_IDX_SHIFT)
 
-#define I40E_GL_MDEF_TR_EXT_CFG                    0x00269A64
+#define I40E_GL_MDEF_TR_EXT_CFG                    0x00269A64 /* Reset: CORER */
 #define I40E_GL_MDEF_TR_EXT_CFG_FCTRL_TR_IDX_SHIFT 0
 #define I40E_GL_MDEF_TR_EXT_CFG_FCTRL_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_MDEF_TR_EXT_CFG_FCTRL_TR_IDX_SHIFT)
 
-#define I40E_GL_MTG_HSH_CTL                 0x00269984
+#define I40E_GL_MTG_HSH_CTL                 0x00269984 /* Reset: CORER */
 #define I40E_GL_MTG_HSH_CTL_HASH_MODE_SHIFT 0
 #define I40E_GL_MTG_HSH_CTL_HASH_MODE_MASK  I40E_MASK(0x3, I40E_GL_MTG_HSH_CTL_HASH_MODE_SHIFT)
 
-#define I40E_GL_MTG_MAP                      0x0026994C
+#define I40E_GL_MTG_MAP                      0x0026994C /* Reset: CORER */
 #define I40E_GL_MTG_MAP_ETAG_FV_IDX_SHIFT    0
 #define I40E_GL_MTG_MAP_ETAG_FV_IDX_MASK     I40E_MASK(0x3F, I40E_GL_MTG_MAP_ETAG_FV_IDX_SHIFT)
 #define I40E_GL_MTG_MAP_ETAG_TR_IDX_SHIFT    6
@@ -2016,54 +2026,54 @@
 #define I40E_GL_MTG_MAP_STAG_TR_IDX_SHIFT    24
 #define I40E_GL_MTG_MAP_STAG_TR_IDX_MASK     I40E_MASK(0x3F, I40E_GL_MTG_MAP_STAG_TR_IDX_SHIFT)
 
-#define I40E_GL_MTG_MAP_EXT                     0x00269954
+#define I40E_GL_MTG_MAP_EXT                     0x00269954 /* Reset: CORER */
 #define I40E_GL_MTG_MAP_EXT_O_VLAN_FV_IDX_SHIFT 0
 #define I40E_GL_MTG_MAP_EXT_O_VLAN_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_MTG_MAP_EXT_O_VLAN_FV_IDX_SHIFT)
 #define I40E_GL_MTG_MAP_EXT_O_VLAN_TR_IDX_SHIFT 6
 #define I40E_GL_MTG_MAP_EXT_O_VLAN_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_MTG_MAP_EXT_O_VLAN_TR_IDX_SHIFT)
 
-#define I40E_GL_MTG_REP_FLU_CTL                0x00269964
+#define I40E_GL_MTG_REP_FLU_CTL                0x00269964 /* Reset: CORER */
 #define I40E_GL_MTG_REP_FLU_CTL_FLU_MODE_SHIFT 0
 #define I40E_GL_MTG_REP_FLU_CTL_FLU_MODE_MASK  I40E_MASK(0xF, I40E_GL_MTG_REP_FLU_CTL_FLU_MODE_SHIFT)
 #define I40E_GL_MTG_REP_FLU_CTL_FLU_OVTH_SHIFT 8
 #define I40E_GL_MTG_REP_FLU_CTL_FLU_OVTH_MASK  I40E_MASK(0xFF, I40E_GL_MTG_REP_FLU_CTL_FLU_OVTH_SHIFT)
 
-#define I40E_GL_MTG_REP_MFIFO_CTL                     0x0026999C
+#define I40E_GL_MTG_REP_MFIFO_CTL                     0x0026999C /* Reset: CORER */
 #define I40E_GL_MTG_REP_MFIFO_CTL_UP_STRICT_PR_SHIFT  0
 #define I40E_GL_MTG_REP_MFIFO_CTL_UP_STRICT_PR_MASK   I40E_MASK(0xF, I40E_GL_MTG_REP_MFIFO_CTL_UP_STRICT_PR_SHIFT)
 #define I40E_GL_MTG_REP_MFIFO_CTL_PRT_STRICT_PR_SHIFT 4
 #define I40E_GL_MTG_REP_MFIFO_CTL_PRT_STRICT_PR_MASK  I40E_MASK(0x1, I40E_GL_MTG_REP_MFIFO_CTL_PRT_STRICT_PR_SHIFT)
 
-#define I40E_GL_MTG_TBL_CTL                0x0026997C
+#define I40E_GL_MTG_TBL_CTL                0x0026997C /* Reset: CORER */
 #define I40E_GL_MTG_TBL_CTL_FLU_MODE_SHIFT 0
 #define I40E_GL_MTG_TBL_CTL_FLU_MODE_MASK  I40E_MASK(0xF, I40E_GL_MTG_TBL_CTL_FLU_MODE_SHIFT)
 #define I40E_GL_MTG_TBL_CTL_FLU_OVTH_SHIFT 8
 #define I40E_GL_MTG_TBL_CTL_FLU_OVTH_MASK  I40E_MASK(0xFF, I40E_GL_MTG_TBL_CTL_FLU_OVTH_SHIFT)
 
-#define I40E_GL_PRE_FLU_CTL(_i)            (0x00269240 + ((_i) * 4)) /* _i=0...9 */
+#define I40E_GL_PRE_FLU_CTL(_i)            (0x00269240 + ((_i) * 4)) /* _i=0...9 */ /* Reset: CORER */
 #define I40E_GL_PRE_FLU_CTL_MAX_INDEX      9
 #define I40E_GL_PRE_FLU_CTL_FLU_MODE_SHIFT 0
 #define I40E_GL_PRE_FLU_CTL_FLU_MODE_MASK  I40E_MASK(0xF, I40E_GL_PRE_FLU_CTL_FLU_MODE_SHIFT)
 #define I40E_GL_PRE_FLU_CTL_FLU_OVTH_SHIFT 8
 #define I40E_GL_PRE_FLU_CTL_FLU_OVTH_MASK  I40E_MASK(0xFF, I40E_GL_PRE_FLU_CTL_FLU_OVTH_SHIFT)
 
-#define I40E_GL_PRE_HSH_KEY_D0                0x00269810
+#define I40E_GL_PRE_HSH_KEY_D0                0x00269810 /* Reset: CORER */
 #define I40E_GL_PRE_HSH_KEY_D0_HASH_KEY_SHIFT 0
 #define I40E_GL_PRE_HSH_KEY_D0_HASH_KEY_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_HSH_KEY_D0_HASH_KEY_SHIFT)
 
-#define I40E_GL_PRE_HSH_KEY_D1                0x00269814
+#define I40E_GL_PRE_HSH_KEY_D1                0x00269814 /* Reset: CORER */
 #define I40E_GL_PRE_HSH_KEY_D1_HASH_KEY_SHIFT 0
 #define I40E_GL_PRE_HSH_KEY_D1_HASH_KEY_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_HSH_KEY_D1_HASH_KEY_SHIFT)
 
-#define I40E_GL_PRE_HSH_KEY_D2                0x00269818
+#define I40E_GL_PRE_HSH_KEY_D2                0x00269818 /* Reset: CORER */
 #define I40E_GL_PRE_HSH_KEY_D2_HASH_KEY_SHIFT 0
 #define I40E_GL_PRE_HSH_KEY_D2_HASH_KEY_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_HSH_KEY_D2_HASH_KEY_SHIFT)
 
-#define I40E_GL_PRE_HSH_KEY_D3                0x0026981C
+#define I40E_GL_PRE_HSH_KEY_D3                0x0026981C /* Reset: CORER */
 #define I40E_GL_PRE_HSH_KEY_D3_HASH_KEY_SHIFT 0
 #define I40E_GL_PRE_HSH_KEY_D3_HASH_KEY_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_HSH_KEY_D3_HASH_KEY_SHIFT)
 
-#define I40E_GL_PRE_MNG_ARP_FLD_CFG                         0x00269A94
+#define I40E_GL_PRE_MNG_ARP_FLD_CFG                         0x00269A94 /* Reset: CORER */
 #define I40E_GL_PRE_MNG_ARP_FLD_CFG_FV_IDX_SHIFT            0
 #define I40E_GL_PRE_MNG_ARP_FLD_CFG_FV_IDX_MASK             I40E_MASK(0x3F, I40E_GL_PRE_MNG_ARP_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_ARP_FLD_CFG_TR_IDX_SHIFT            13
@@ -2071,71 +2081,71 @@
 #define I40E_GL_PRE_MNG_ARP_FLD_CFG_ARP_TAR_IP_FV_IDX_SHIFT 24
 #define I40E_GL_PRE_MNG_ARP_FLD_CFG_ARP_TAR_IP_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_ARP_FLD_CFG_ARP_TAR_IP_FV_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_ETH_FLD_CFG              0x00269ABC
+#define I40E_GL_PRE_MNG_ETH_FLD_CFG              0x00269ABC /* Reset: CORER */
 #define I40E_GL_PRE_MNG_ETH_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_ETH_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_ETH_FLD_CFG_FV_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_ICMP_FLD_CFG              0x00269A9C
+#define I40E_GL_PRE_MNG_ICMP_FLD_CFG              0x00269A9C /* Reset: CORER */
 #define I40E_GL_PRE_MNG_ICMP_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_ICMP_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_ICMP_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_ICMP_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_ICMP_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_ICMP_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_IP4_FLD_CFG              0x00269AB4
+#define I40E_GL_PRE_MNG_IP4_FLD_CFG              0x00269AB4 /* Reset: CORER */
 #define I40E_GL_PRE_MNG_IP4_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_IP4_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_IP4_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_IP4_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_IP4_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_IP4_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_IP6_FLD_CFG              0x00269A7C
+#define I40E_GL_PRE_MNG_IP6_FLD_CFG              0x00269A7C /* Reset: CORER */
 #define I40E_GL_PRE_MNG_IP6_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_IP6_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_IP6_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_IP6_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_IP6_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_IP6_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_MAC_FLD_CFG              0x00269A8C
+#define I40E_GL_PRE_MNG_MAC_FLD_CFG              0x00269A8C /* Reset: CORER */
 #define I40E_GL_PRE_MNG_MAC_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_MAC_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_MAC_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_MAC_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_MAC_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_MAC_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_MLD_FLD_CFG              0x00269A6C
+#define I40E_GL_PRE_MNG_MLD_FLD_CFG              0x00269A6C /* Reset: CORER */
 #define I40E_GL_PRE_MNG_MLD_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_MLD_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_MLD_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_MLD_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_MLD_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_MLD_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_TCPDP_FLD_CFG              0x00269A74
+#define I40E_GL_PRE_MNG_TCPDP_FLD_CFG              0x00269A74 /* Reset: CORER */
 #define I40E_GL_PRE_MNG_TCPDP_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_TCPDP_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_TCPDP_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_TCPDP_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_TCPDP_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_TCPDP_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_TCPSP_FLD_CFG              0x00269AA4
+#define I40E_GL_PRE_MNG_TCPSP_FLD_CFG              0x00269AA4 /* Reset: CORER */
 #define I40E_GL_PRE_MNG_TCPSP_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_TCPSP_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_TCPSP_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_TCPSP_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_TCPSP_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_TCPSP_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_UDPDP_FLD_CFG              0x00269AAC
+#define I40E_GL_PRE_MNG_UDPDP_FLD_CFG              0x00269AAC /* Reset: CORER */
 #define I40E_GL_PRE_MNG_UDPDP_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_UDPDP_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_UDPDP_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_UDPDP_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_UDPDP_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_UDPDP_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_UDPSP_FLD_CFG              0x00269AC4
+#define I40E_GL_PRE_MNG_UDPSP_FLD_CFG              0x00269AC4 /* Reset: CORER */
 #define I40E_GL_PRE_MNG_UDPSP_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_UDPSP_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_UDPSP_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_UDPSP_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_UDPSP_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_UDPSP_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_MNG_VLAN_FLD_CFG              0x00269A84
+#define I40E_GL_PRE_MNG_VLAN_FLD_CFG              0x00269A84 /* Reset: CORER */
 #define I40E_GL_PRE_MNG_VLAN_FLD_CFG_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_MNG_VLAN_FLD_CFG_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_VLAN_FLD_CFG_FV_IDX_SHIFT)
 #define I40E_GL_PRE_MNG_VLAN_FLD_CFG_TR_IDX_SHIFT 13
 #define I40E_GL_PRE_MNG_VLAN_FLD_CFG_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_MNG_VLAN_FLD_CFG_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_PRX_BIG_ENT_D2                 0x002699EC
+#define I40E_GL_PRE_PRX_BIG_ENT_D2                 0x002699EC /* Reset: CORER */
 #define I40E_GL_PRE_PRX_BIG_ENT_D2_USE_PORT_SHIFT  7
 #define I40E_GL_PRE_PRX_BIG_ENT_D2_USE_PORT_MASK   I40E_MASK(0x1, I40E_GL_PRE_PRX_BIG_ENT_D2_USE_PORT_SHIFT)
 #define I40E_GL_PRE_PRX_BIG_ENT_D2_TR_EN_SHIFT     8
@@ -2147,39 +2157,39 @@
 #define I40E_GL_PRE_PRX_BIG_ENT_D2_BIT_MSK0_SHIFT  24
 #define I40E_GL_PRE_PRX_BIG_ENT_D2_BIT_MSK0_MASK   I40E_MASK(0xFF, I40E_GL_PRE_PRX_BIG_ENT_D2_BIT_MSK0_SHIFT)
 
-#define I40E_GL_PRE_PRX_BIG_HSH_KEY_D0          0x00269A1C
+#define I40E_GL_PRE_PRX_BIG_HSH_KEY_D0          0x00269A1C /* Reset: CORER */
 #define I40E_GL_PRE_PRX_BIG_HSH_KEY_D0_H0_SHIFT 0
 #define I40E_GL_PRE_PRX_BIG_HSH_KEY_D0_H0_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_PRX_BIG_HSH_KEY_D0_H0_SHIFT)
 
-#define I40E_GL_PRE_PRX_BIG_HSH_KEY_D2          0x00269A3C
+#define I40E_GL_PRE_PRX_BIG_HSH_KEY_D2          0x00269A3C /* Reset: CORER */
 #define I40E_GL_PRE_PRX_BIG_HSH_KEY_D2_H2_SHIFT 0
 #define I40E_GL_PRE_PRX_BIG_HSH_KEY_D2_H2_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_PRX_BIG_HSH_KEY_D2_H2_SHIFT)
 
-#define I40E_GL_PRE_PRX_FLU_CTL                0x00269974
+#define I40E_GL_PRE_PRX_FLU_CTL                0x00269974 /* Reset: CORER */
 #define I40E_GL_PRE_PRX_FLU_CTL_FLU_MODE_SHIFT 0
 #define I40E_GL_PRE_PRX_FLU_CTL_FLU_MODE_MASK  I40E_MASK(0xF, I40E_GL_PRE_PRX_FLU_CTL_FLU_MODE_SHIFT)
 #define I40E_GL_PRE_PRX_FLU_CTL_FLU_OVTH_SHIFT 8
 #define I40E_GL_PRE_PRX_FLU_CTL_FLU_OVTH_MASK  I40E_MASK(0xFF, I40E_GL_PRE_PRX_FLU_CTL_FLU_OVTH_SHIFT)
 
-#define I40E_GL_PRE_PRX_GEN_CFG                     0x002699AC
+#define I40E_GL_PRE_PRX_GEN_CFG                     0x002699AC /* Reset: CORER */
 #define I40E_GL_PRE_PRX_GEN_CFG_FILTER_ENABLE_SHIFT 0
 #define I40E_GL_PRE_PRX_GEN_CFG_FILTER_ENABLE_MASK  I40E_MASK(0x1, I40E_GL_PRE_PRX_GEN_CFG_FILTER_ENABLE_SHIFT)
 #define I40E_GL_PRE_PRX_GEN_CFG_HASH_MODE_SHIFT     6
 #define I40E_GL_PRE_PRX_GEN_CFG_HASH_MODE_MASK      I40E_MASK(0x3, I40E_GL_PRE_PRX_GEN_CFG_HASH_MODE_SHIFT)
 
-#define I40E_GL_PRE_PRX_HSH_KEY_D1          0x00269A2C
+#define I40E_GL_PRE_PRX_HSH_KEY_D1          0x00269A2C /* Reset: CORER */
 #define I40E_GL_PRE_PRX_HSH_KEY_D1_H1_SHIFT 0
 #define I40E_GL_PRE_PRX_HSH_KEY_D1_H1_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_PRX_HSH_KEY_D1_H1_SHIFT)
 
-#define I40E_GL_PRE_PRX_HSH_KEY_D2          0x00269A44
+#define I40E_GL_PRE_PRX_HSH_KEY_D2          0x00269A44 /* Reset: CORER */
 #define I40E_GL_PRE_PRX_HSH_KEY_D2_H2_SHIFT 0
 #define I40E_GL_PRE_PRX_HSH_KEY_D2_H2_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_PRX_HSH_KEY_D2_H2_SHIFT)
 
-#define I40E_GL_PRE_PRX_HSH_KEY_D3          0x00269A4C
+#define I40E_GL_PRE_PRX_HSH_KEY_D3          0x00269A4C /* Reset: CORER */
 #define I40E_GL_PRE_PRX_HSH_KEY_D3_H3_SHIFT 0
 #define I40E_GL_PRE_PRX_HSH_KEY_D3_H3_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_PRX_HSH_KEY_D3_H3_SHIFT)
 
-#define I40E_GL_PRE_RDMABM_FLD_CFG                     0x002699B4
+#define I40E_GL_PRE_RDMABM_FLD_CFG                     0x002699B4 /* Reset: CORER */
 #define I40E_GL_PRE_RDMABM_FLD_CFG_TCP_DP_FV_IDX_SHIFT 0
 #define I40E_GL_PRE_RDMABM_FLD_CFG_TCP_DP_FV_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_RDMABM_FLD_CFG_TCP_DP_FV_IDX_SHIFT)
 #define I40E_GL_PRE_RDMABM_FLD_CFG_TCP_DP_TR_IDX_SHIFT 6
@@ -2189,7 +2199,7 @@
 #define I40E_GL_PRE_RDMABM_FLD_CFG_UDP_DP_TR_IDX_SHIFT 22
 #define I40E_GL_PRE_RDMABM_FLD_CFG_UDP_DP_TR_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_RDMABM_FLD_CFG_UDP_DP_TR_IDX_SHIFT)
 
-#define I40E_GL_PRE_TR_MAN(_i)               (0x00269F80 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GL_PRE_TR_MAN(_i)               (0x00269F80 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GL_PRE_TR_MAN_MAX_INDEX         7
 #define I40E_GL_PRE_TR_MAN_SRC_TR_IDX0_SHIFT 0
 #define I40E_GL_PRE_TR_MAN_SRC_TR_IDX0_MASK  I40E_MASK(0x3F, I40E_GL_PRE_TR_MAN_SRC_TR_IDX0_SHIFT)
@@ -2200,18 +2210,18 @@
 #define I40E_GL_PRE_TR_MAN_TR_MAN_NEG_SHIFT  18
 #define I40E_GL_PRE_TR_MAN_TR_MAN_NEG_MASK   I40E_MASK(0x1, I40E_GL_PRE_TR_MAN_TR_MAN_NEG_SHIFT)
 
-#define I40E_GL_PRS_FRT(_i)            (0x00269750 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GL_PRS_FRT(_i)            (0x00269750 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GL_PRS_FRT_MAX_INDEX      3
 #define I40E_GL_PRS_FRT_FV_IDX_0_SHIFT 0
 #define I40E_GL_PRS_FRT_FV_IDX_0_MASK  I40E_MASK(0x3FF, I40E_GL_PRS_FRT_FV_IDX_0_SHIFT)
 #define I40E_GL_PRS_FRT_FV_IDX_1_SHIFT 16
 #define I40E_GL_PRS_FRT_FV_IDX_1_MASK  I40E_MASK(0x3FF, I40E_GL_PRS_FRT_FV_IDX_1_SHIFT)
 
-#define I40E_GL_PRS_L2LEN               0x0026996C
+#define I40E_GL_PRS_L2LEN               0x0026996C /* Reset: CORER */
 #define I40E_GL_PRS_L2LEN_MAC_LEN_SHIFT 8
 #define I40E_GL_PRS_L2LEN_MAC_LEN_MASK  I40E_MASK(0xFF, I40E_GL_PRS_L2LEN_MAC_LEN_SHIFT)
 
-#define I40E_GL_PRS_PL_THR                     0x00269FE4
+#define I40E_GL_PRS_PL_THR                     0x00269FE4 /* Reset: CORER */
 #define I40E_GL_PRS_PL_THR_PIPE_LIMIT_P0_SHIFT 0
 #define I40E_GL_PRS_PL_THR_PIPE_LIMIT_P0_MASK  I40E_MASK(0xFF, I40E_GL_PRS_PL_THR_PIPE_LIMIT_P0_SHIFT)
 #define I40E_GL_PRS_PL_THR_PIPE_LIMIT_P1_SHIFT 8
@@ -2221,7 +2231,7 @@
 #define I40E_GL_PRS_PL_THR_PIPE_LIMIT_P3_SHIFT 24
 #define I40E_GL_PRS_PL_THR_PIPE_LIMIT_P3_MASK  I40E_MASK(0xFF, I40E_GL_PRS_PL_THR_PIPE_LIMIT_P3_SHIFT)
 
-#define I40E_GL_PRS_PM_PORT_THR                  0x00269FC4
+#define I40E_GL_PRS_PM_PORT_THR                  0x00269FC4 /* Reset: CORER */
 #define I40E_GL_PRS_PM_PORT_THR_THR_PORT_0_SHIFT 0
 #define I40E_GL_PRS_PM_PORT_THR_THR_PORT_0_MASK  I40E_MASK(0xFF, I40E_GL_PRS_PM_PORT_THR_THR_PORT_0_SHIFT)
 #define I40E_GL_PRS_PM_PORT_THR_THR_PORT_1_SHIFT 8
@@ -2231,7 +2241,7 @@
 #define I40E_GL_PRS_PM_PORT_THR_THR_PORT_3_SHIFT 24
 #define I40E_GL_PRS_PM_PORT_THR_THR_PORT_3_MASK  I40E_MASK(0xFF, I40E_GL_PRS_PM_PORT_THR_THR_PORT_3_SHIFT)
 
-#define I40E_GL_PRS_PM_UP_THR                 0x00269FCC
+#define I40E_GL_PRS_PM_UP_THR                 0x00269FCC /* Reset: CORER */
 #define I40E_GL_PRS_PM_UP_THR_UP_PORT_0_SHIFT 0
 #define I40E_GL_PRS_PM_UP_THR_UP_PORT_0_MASK  I40E_MASK(0xFF, I40E_GL_PRS_PM_UP_THR_UP_PORT_0_SHIFT)
 #define I40E_GL_PRS_PM_UP_THR_UP_PORT_1_SHIFT 8
@@ -2241,7 +2251,7 @@
 #define I40E_GL_PRS_PM_UP_THR_UP_PORT_3_SHIFT 24
 #define I40E_GL_PRS_PM_UP_THR_UP_PORT_3_MASK  I40E_MASK(0xFF, I40E_GL_PRS_PM_UP_THR_UP_PORT_3_SHIFT)
 
-#define I40E_GL_RXA_CFG                     0x00269944
+#define I40E_GL_RXA_CFG                     0x00269944 /* Reset: CORER */
 #define I40E_GL_RXA_CFG_UP_STRICT_PR_SHIFT  0
 #define I40E_GL_RXA_CFG_UP_STRICT_PR_MASK   I40E_MASK(0xF, I40E_GL_RXA_CFG_UP_STRICT_PR_SHIFT)
 #define I40E_GL_RXA_CFG_PRT_STRICT_PR_SHIFT 4
@@ -2251,16 +2261,16 @@
 #define I40E_GL_RXA_CFG_MAX_HDR_LEN_SHIFT   15
 #define I40E_GL_RXA_CFG_MAX_HDR_LEN_MASK    I40E_MASK(0x7F, I40E_GL_RXA_CFG_MAX_HDR_LEN_SHIFT)
 
-#define I40E_GL_SWR_DP                 0x00269998
+#define I40E_GL_SWR_DP                 0x00269998 /* Reset: CORER */
 #define I40E_GL_SWR_DP_DUAL_PORT_SHIFT 0
 #define I40E_GL_SWR_DP_DUAL_PORT_MASK  I40E_MASK(0x1, I40E_GL_SWR_DP_DUAL_PORT_SHIFT)
 
-#define I40E_GL_SWR_MAC_AS_FLU_ID(_i)               (0x00269BE8 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GL_SWR_MAC_AS_FLU_ID(_i)               (0x00269BE8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GL_SWR_MAC_AS_FLU_ID_MAX_INDEX         1
 #define I40E_GL_SWR_MAC_AS_FLU_ID_FLU_INDEXES_SHIFT 0
 #define I40E_GL_SWR_MAC_AS_FLU_ID_FLU_INDEXES_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_MAC_AS_FLU_ID_FLU_INDEXES_SHIFT)
 
-#define I40E_GL_SWR_MIM_DBG_CTL                  0x00269FE8
+#define I40E_GL_SWR_MIM_DBG_CTL                  0x00269FE8 /* Reset: CORER */
 #define I40E_GL_SWR_MIM_DBG_CTL_ADDR_SHIFT       0
 #define I40E_GL_SWR_MIM_DBG_CTL_ADDR_MASK        I40E_MASK(0x1FF, I40E_GL_SWR_MIM_DBG_CTL_ADDR_SHIFT)
 #define I40E_GL_SWR_MIM_DBG_CTL_DW_SEL_SHIFT     16
@@ -2270,11 +2280,11 @@
 #define I40E_GL_SWR_MIM_DBG_CTL_BLOCK_PRSR_SHIFT 31
 #define I40E_GL_SWR_MIM_DBG_CTL_BLOCK_PRSR_MASK  I40E_MASK(0x1, I40E_GL_SWR_MIM_DBG_CTL_BLOCK_PRSR_SHIFT)
 
-#define I40E_GL_SWR_MIM_DBG_STS                          0x00269FEC
+#define I40E_GL_SWR_MIM_DBG_STS                          0x00269FEC /* Reset: CORER */
 #define I40E_GL_SWR_MIM_DBG_STS_GL_SWR_MIM_DBG_STS_SHIFT 0
 #define I40E_GL_SWR_MIM_DBG_STS_GL_SWR_MIM_DBG_STS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_MIM_DBG_STS_GL_SWR_MIM_DBG_STS_SHIFT)
 
-#define I40E_GL_SWR_PM_PORT_THR                  0x00269FB4
+#define I40E_GL_SWR_PM_PORT_THR                  0x00269FB4 /* Reset: CORER */
 #define I40E_GL_SWR_PM_PORT_THR_THR_PORT_0_SHIFT 0
 #define I40E_GL_SWR_PM_PORT_THR_THR_PORT_0_MASK  I40E_MASK(0xFF, I40E_GL_SWR_PM_PORT_THR_THR_PORT_0_SHIFT)
 #define I40E_GL_SWR_PM_PORT_THR_THR_PORT_1_SHIFT 8
@@ -2284,13 +2294,13 @@
 #define I40E_GL_SWR_PM_PORT_THR_THR_PORT_3_SHIFT 24
 #define I40E_GL_SWR_PM_PORT_THR_THR_PORT_3_MASK  I40E_MASK(0xFF, I40E_GL_SWR_PM_PORT_THR_THR_PORT_3_SHIFT)
 
-#define I40E_GL_SWR_REP_FLU_CTL                0x0026995C
+#define I40E_GL_SWR_REP_FLU_CTL                0x0026995C /* Reset: CORER */
 #define I40E_GL_SWR_REP_FLU_CTL_FLU_MODE_SHIFT 0
 #define I40E_GL_SWR_REP_FLU_CTL_FLU_MODE_MASK  I40E_MASK(0xF, I40E_GL_SWR_REP_FLU_CTL_FLU_MODE_SHIFT)
 #define I40E_GL_SWR_REP_FLU_CTL_FLU_OVTH_SHIFT 8
 #define I40E_GL_SWR_REP_FLU_CTL_FLU_OVTH_MASK  I40E_MASK(0xFF, I40E_GL_SWR_REP_FLU_CTL_FLU_OVTH_SHIFT)
 
-#define I40E_GL_SWR_REP_MFIFO_CTL                     0x00269994
+#define I40E_GL_SWR_REP_MFIFO_CTL                     0x00269994 /* Reset: CORER */
 #define I40E_GL_SWR_REP_MFIFO_CTL_UP_STRICT_PR_SHIFT  0
 #define I40E_GL_SWR_REP_MFIFO_CTL_UP_STRICT_PR_MASK   I40E_MASK(0xF, I40E_GL_SWR_REP_MFIFO_CTL_UP_STRICT_PR_SHIFT)
 #define I40E_GL_SWR_REP_MFIFO_CTL_PRT_STRICT_PR_SHIFT 4
@@ -2298,7 +2308,7 @@
 #define I40E_GL_SWR_REP_MFIFO_CTL_SPARE27B_SHIFT      5
 #define I40E_GL_SWR_REP_MFIFO_CTL_SPARE27B_MASK       I40E_MASK(0x7FFFFFF, I40E_GL_SWR_REP_MFIFO_CTL_SPARE27B_SHIFT)
 
-#define I40E_GLCM_LAN_CACHE0_MEM_CFG                    0x0010C48C
+#define I40E_GLCM_LAN_CACHE0_MEM_CFG                    0x0010C48C /* Reset: POR */
 #define I40E_GLCM_LAN_CACHE0_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_GLCM_LAN_CACHE0_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_GLCM_LAN_CACHE0_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_GLCM_LAN_CACHE0_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -2324,7 +2334,7 @@
 #define I40E_GLCM_LAN_CACHE0_MEM_CFG_RM_B_SHIFT         20
 #define I40E_GLCM_LAN_CACHE0_MEM_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_GLCM_LAN_CACHE0_MEM_CFG_RM_B_SHIFT)
 
-#define I40E_GLCM_LAN_CACHE0_MEM_STATUS                        0x0010C490
+#define I40E_GLCM_LAN_CACHE0_MEM_STATUS                        0x0010C490 /* Reset: POR */
 #define I40E_GLCM_LAN_CACHE0_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_GLCM_LAN_CACHE0_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_GLCM_LAN_CACHE0_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_GLCM_LAN_CACHE0_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -2334,7 +2344,7 @@
 #define I40E_GLCM_LAN_CACHE0_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_GLCM_LAN_CACHE0_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LAN_CACHE0_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_GLCM_LAN_CACHE1_MEM_CFG                    0x0010C494
+#define I40E_GLCM_LAN_CACHE1_MEM_CFG                    0x0010C494 /* Reset: POR */
 #define I40E_GLCM_LAN_CACHE1_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_GLCM_LAN_CACHE1_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_GLCM_LAN_CACHE1_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_GLCM_LAN_CACHE1_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -2360,7 +2370,7 @@
 #define I40E_GLCM_LAN_CACHE1_MEM_CFG_RM_B_SHIFT         20
 #define I40E_GLCM_LAN_CACHE1_MEM_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_GLCM_LAN_CACHE1_MEM_CFG_RM_B_SHIFT)
 
-#define I40E_GLCM_LAN_CACHE1_MEM_STATUS                        0x0010C498
+#define I40E_GLCM_LAN_CACHE1_MEM_STATUS                        0x0010C498 /* Reset: POR */
 #define I40E_GLCM_LAN_CACHE1_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_GLCM_LAN_CACHE1_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_GLCM_LAN_CACHE1_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_GLCM_LAN_CACHE1_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -2370,7 +2380,7 @@
 #define I40E_GLCM_LAN_CACHE1_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_GLCM_LAN_CACHE1_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LAN_CACHE1_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_GLCM_LAN_DBELL_MEM_CFG                    0x0010C49C
+#define I40E_GLCM_LAN_DBELL_MEM_CFG                    0x0010C49C /* Reset: POR */
 #define I40E_GLCM_LAN_DBELL_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_GLCM_LAN_DBELL_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_GLCM_LAN_DBELL_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_GLCM_LAN_DBELL_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -2396,7 +2406,7 @@
 #define I40E_GLCM_LAN_DBELL_MEM_CFG_RM_B_SHIFT         20
 #define I40E_GLCM_LAN_DBELL_MEM_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_GLCM_LAN_DBELL_MEM_CFG_RM_B_SHIFT)
 
-#define I40E_GLCM_LAN_DBELL_MEM_STATUS                        0x0010C4A0
+#define I40E_GLCM_LAN_DBELL_MEM_STATUS                        0x0010C4A0 /* Reset: POR */
 #define I40E_GLCM_LAN_DBELL_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_GLCM_LAN_DBELL_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_GLCM_LAN_DBELL_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_GLCM_LAN_DBELL_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -2406,15 +2416,15 @@
 #define I40E_GLCM_LAN_DBELL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_GLCM_LAN_DBELL_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LAN_DBELL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_GLCM_LAN_ECC_COR_ERR           0x0010C4D0
+#define I40E_GLCM_LAN_ECC_COR_ERR           0x0010C4D0 /* Reset: POR */
 #define I40E_GLCM_LAN_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_GLCM_LAN_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_GLCM_LAN_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_GLCM_LAN_ECC_UNCOR_ERR           0x0010C4CC
+#define I40E_GLCM_LAN_ECC_UNCOR_ERR           0x0010C4CC /* Reset: POR */
 #define I40E_GLCM_LAN_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_GLCM_LAN_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_GLCM_LAN_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_GLCM_LAN_EVICTBUF_MEM_CFG                    0x0010C4A4
+#define I40E_GLCM_LAN_EVICTBUF_MEM_CFG                    0x0010C4A4 /* Reset: POR */
 #define I40E_GLCM_LAN_EVICTBUF_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_GLCM_LAN_EVICTBUF_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_GLCM_LAN_EVICTBUF_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_GLCM_LAN_EVICTBUF_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -2436,7 +2446,7 @@
 #define I40E_GLCM_LAN_EVICTBUF_MEM_CFG_RM_SHIFT           16
 #define I40E_GLCM_LAN_EVICTBUF_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_GLCM_LAN_EVICTBUF_MEM_CFG_RM_SHIFT)
 
-#define I40E_GLCM_LAN_EVICTBUF_MEM_STATUS                        0x0010C4A8
+#define I40E_GLCM_LAN_EVICTBUF_MEM_STATUS                        0x0010C4A8 /* Reset: POR */
 #define I40E_GLCM_LAN_EVICTBUF_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_GLCM_LAN_EVICTBUF_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_GLCM_LAN_EVICTBUF_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_GLCM_LAN_EVICTBUF_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -2446,7 +2456,7 @@
 #define I40E_GLCM_LAN_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_GLCM_LAN_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LAN_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_GLCM_LAN_FILLBUF_MEM_CFG                    0x0010C4AC
+#define I40E_GLCM_LAN_FILLBUF_MEM_CFG                    0x0010C4AC /* Reset: POR */
 #define I40E_GLCM_LAN_FILLBUF_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_GLCM_LAN_FILLBUF_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_GLCM_LAN_FILLBUF_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_GLCM_LAN_FILLBUF_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -2468,7 +2478,7 @@
 #define I40E_GLCM_LAN_FILLBUF_MEM_CFG_RM_SHIFT           16
 #define I40E_GLCM_LAN_FILLBUF_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_GLCM_LAN_FILLBUF_MEM_CFG_RM_SHIFT)
 
-#define I40E_GLCM_LAN_FILLBUF_MEM_STATUS                        0x0010C4B0
+#define I40E_GLCM_LAN_FILLBUF_MEM_STATUS                        0x0010C4B0 /* Reset: POR */
 #define I40E_GLCM_LAN_FILLBUF_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_GLCM_LAN_FILLBUF_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_GLCM_LAN_FILLBUF_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_GLCM_LAN_FILLBUF_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -2478,7 +2488,7 @@
 #define I40E_GLCM_LAN_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_GLCM_LAN_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LAN_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_GLCM_LAN_QTXCTL_MEM_CFG                    0x0010C4BC
+#define I40E_GLCM_LAN_QTXCTL_MEM_CFG                    0x0010C4BC /* Reset: POR */
 #define I40E_GLCM_LAN_QTXCTL_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_GLCM_LAN_QTXCTL_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_GLCM_LAN_QTXCTL_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_GLCM_LAN_QTXCTL_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -2500,7 +2510,7 @@
 #define I40E_GLCM_LAN_QTXCTL_MEM_CFG_RM_SHIFT           16
 #define I40E_GLCM_LAN_QTXCTL_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_GLCM_LAN_QTXCTL_MEM_CFG_RM_SHIFT)
 
-#define I40E_GLCM_LAN_QTXCTL_MEM_STATUS                        0x0010C4C0
+#define I40E_GLCM_LAN_QTXCTL_MEM_STATUS                        0x0010C4C0 /* Reset: POR */
 #define I40E_GLCM_LAN_QTXCTL_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_GLCM_LAN_QTXCTL_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_GLCM_LAN_QTXCTL_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_GLCM_LAN_QTXCTL_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -2510,7 +2520,7 @@
 #define I40E_GLCM_LAN_QTXCTL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_GLCM_LAN_QTXCTL_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LAN_QTXCTL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_GLCM_LAN_RDYLIST_MEM_CFG                    0x0010C4B4
+#define I40E_GLCM_LAN_RDYLIST_MEM_CFG                    0x0010C4B4 /* Reset: POR */
 #define I40E_GLCM_LAN_RDYLIST_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_GLCM_LAN_RDYLIST_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_GLCM_LAN_RDYLIST_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_GLCM_LAN_RDYLIST_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -2532,7 +2542,7 @@
 #define I40E_GLCM_LAN_RDYLIST_MEM_CFG_RM_SHIFT           16
 #define I40E_GLCM_LAN_RDYLIST_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_GLCM_LAN_RDYLIST_MEM_CFG_RM_SHIFT)
 
-#define I40E_GLCM_LAN_RDYLIST_MEM_STATUS                        0x0010C4B8
+#define I40E_GLCM_LAN_RDYLIST_MEM_STATUS                        0x0010C4B8 /* Reset: POR */
 #define I40E_GLCM_LAN_RDYLIST_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_GLCM_LAN_RDYLIST_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_GLCM_LAN_RDYLIST_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_GLCM_LAN_RDYLIST_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -2542,7 +2552,7 @@
 #define I40E_GLCM_LAN_RDYLIST_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_GLCM_LAN_RDYLIST_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LAN_RDYLIST_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_GLCM_LAN_TAILPTR_MEM_CFG                    0x0010C4C4
+#define I40E_GLCM_LAN_TAILPTR_MEM_CFG                    0x0010C4C4 /* Reset: POR */
 #define I40E_GLCM_LAN_TAILPTR_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_GLCM_LAN_TAILPTR_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_GLCM_LAN_TAILPTR_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_GLCM_LAN_TAILPTR_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -2568,7 +2578,7 @@
 #define I40E_GLCM_LAN_TAILPTR_MEM_CFG_RM_B_SHIFT         20
 #define I40E_GLCM_LAN_TAILPTR_MEM_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_GLCM_LAN_TAILPTR_MEM_CFG_RM_B_SHIFT)
 
-#define I40E_GLCM_LAN_TAILPTR_MEM_STATUS                        0x0010C4C8
+#define I40E_GLCM_LAN_TAILPTR_MEM_STATUS                        0x0010C4C8 /* Reset: POR */
 #define I40E_GLCM_LAN_TAILPTR_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_GLCM_LAN_TAILPTR_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_GLCM_LAN_TAILPTR_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_GLCM_LAN_TAILPTR_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -2578,11 +2588,11 @@
 #define I40E_GLCM_LAN_TAILPTR_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_GLCM_LAN_TAILPTR_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_GLCM_LAN_TAILPTR_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_GLDFT_NCSI_PADS_CFG                       0x0009408C
+#define I40E_GLDFT_NCSI_PADS_CFG                       0x0009408C /* Reset: POR */
 #define I40E_GLDFT_NCSI_PADS_CFG_GLNCSI_PADS_CFG_SHIFT 0
 #define I40E_GLDFT_NCSI_PADS_CFG_GLNCSI_PADS_CFG_MASK  I40E_MASK(0x1, I40E_GLDFT_NCSI_PADS_CFG_GLNCSI_PADS_CFG_SHIFT)
 
-#define I40E_GLDFT_TS_STAT                       0x00094080
+#define I40E_GLDFT_TS_STAT                       0x00094080 /* Reset: POR */
 #define I40E_GLDFT_TS_STAT_SBL_THERM_IND_SHIFT   0
 #define I40E_GLDFT_TS_STAT_SBL_THERM_IND_MASK    I40E_MASK(0x7, I40E_GLDFT_TS_STAT_SBL_THERM_IND_SHIFT)
 #define I40E_GLDFT_TS_STAT_SBT_THERM_VAL_SHIFT   3
@@ -2590,7 +2600,7 @@
 #define I40E_GLDFT_TS_STAT_SBT_THERM_VALID_SHIFT 31
 #define I40E_GLDFT_TS_STAT_SBT_THERM_VALID_MASK  I40E_MASK(0x1, I40E_GLDFT_TS_STAT_SBT_THERM_VALID_SHIFT)
 
-#define I40E_GLDFT_VISA_CTRL                    0x00094084
+#define I40E_GLDFT_VISA_CTRL                    0x00094084 /* Reset: POR */
 #define I40E_GLDFT_VISA_CTRL_VISA_INDEX_SHIFT   0
 #define I40E_GLDFT_VISA_CTRL_VISA_INDEX_MASK    I40E_MASK(0x1F, I40E_GLDFT_VISA_CTRL_VISA_INDEX_SHIFT)
 #define I40E_GLDFT_VISA_CTRL_VISA_UNIT_ID_SHIFT 5
@@ -2598,95 +2608,95 @@
 #define I40E_GLDFT_VISA_CTRL_VISA_OPCODE_SHIFT  31
 #define I40E_GLDFT_VISA_CTRL_VISA_OPCODE_MASK   I40E_MASK(0x1, I40E_GLDFT_VISA_CTRL_VISA_OPCODE_SHIFT)
 
-#define I40E_GLDFT_VISA_DATA                       0x00094088
+#define I40E_GLDFT_VISA_DATA                       0x00094088 /* Reset: POR */
 #define I40E_GLDFT_VISA_DATA_GLDFT_VISA_DATA_SHIFT 0
 #define I40E_GLDFT_VISA_DATA_GLDFT_VISA_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLDFT_VISA_DATA_GLDFT_VISA_DATA_SHIFT)
 
-#define I40E_GLDFT_VISA_DISABLE                             0x00094098
+#define I40E_GLDFT_VISA_DISABLE                             0x00094098 /* Reset: POR */
 #define I40E_GLDFT_VISA_DISABLE_VISA_CUSTOMER_DISABLE_SHIFT 0
 #define I40E_GLDFT_VISA_DISABLE_VISA_CUSTOMER_DISABLE_MASK  I40E_MASK(0x1, I40E_GLDFT_VISA_DISABLE_VISA_CUSTOMER_DISABLE_SHIFT)
 #define I40E_GLDFT_VISA_DISABLE_VISA_ALL_DISABLE_SHIFT      1
 #define I40E_GLDFT_VISA_DISABLE_VISA_ALL_DISABLE_MASK       I40E_MASK(0x1, I40E_GLDFT_VISA_DISABLE_VISA_ALL_DISABLE_SHIFT)
 
-#define I40E_GLDFT_VISA_LANE_LSB                           0x00094090
+#define I40E_GLDFT_VISA_LANE_LSB                           0x00094090 /* Reset: POR */
 #define I40E_GLDFT_VISA_LANE_LSB_GLDFT_VISA_LANE_LSB_SHIFT 0
 #define I40E_GLDFT_VISA_LANE_LSB_GLDFT_VISA_LANE_LSB_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLDFT_VISA_LANE_LSB_GLDFT_VISA_LANE_LSB_SHIFT)
 
-#define I40E_GLDFT_VISA_LANE_MSB                           0x00094094
+#define I40E_GLDFT_VISA_LANE_MSB                           0x00094094 /* Reset: POR */
 #define I40E_GLDFT_VISA_LANE_MSB_GLDFT_VISA_LANE_MSB_SHIFT 0
 #define I40E_GLDFT_VISA_LANE_MSB_GLDFT_VISA_LANE_MSB_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLDFT_VISA_LANE_MSB_GLDFT_VISA_LANE_MSB_SHIFT)
 
-#define I40E_GLLAN_TCB_STAT               0x000AE0D0
+#define I40E_GLLAN_TCB_STAT               0x000AE0D0 /* Reset: CORER */
 #define I40E_GLLAN_TCB_STAT_LL_STAT_SHIFT 0
 #define I40E_GLLAN_TCB_STAT_LL_STAT_MASK  I40E_MASK(0xFFFF, I40E_GLLAN_TCB_STAT_LL_STAT_SHIFT)
 #define I40E_GLLAN_TCB_STAT_RSV_SHIFT     16
 #define I40E_GLLAN_TCB_STAT_RSV_MASK      I40E_MASK(0xFFFF, I40E_GLLAN_TCB_STAT_RSV_SHIFT)
 
-#define I40E_GLPCI_CLKCTL                      0x000B819C
+#define I40E_GLPCI_CLKCTL                      0x000B819C /* Reset: POR */
 #define I40E_GLPCI_CLKCTL_PCI_CLK_DYN_SHIFT    0
 #define I40E_GLPCI_CLKCTL_PCI_CLK_DYN_MASK     I40E_MASK(0x1, I40E_GLPCI_CLKCTL_PCI_CLK_DYN_SHIFT)
 #define I40E_GLPCI_CLKCTL_PCI_CLK_STABLE_SHIFT 1
 #define I40E_GLPCI_CLKCTL_PCI_CLK_STABLE_MASK  I40E_MASK(0x1, I40E_GLPCI_CLKCTL_PCI_CLK_STABLE_SHIFT)
 
-#define I40E_GLPCI_MCTP_CREDIT              0x000BE4EC
+#define I40E_GLPCI_MCTP_CREDIT              0x000BE4EC /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_CREDIT_HEADER_SHIFT 0
 #define I40E_GLPCI_MCTP_CREDIT_HEADER_MASK  I40E_MASK(0xFF, I40E_GLPCI_MCTP_CREDIT_HEADER_SHIFT)
 #define I40E_GLPCI_MCTP_CREDIT_DATA_SHIFT   8
 #define I40E_GLPCI_MCTP_CREDIT_DATA_MASK    I40E_MASK(0xFFF, I40E_GLPCI_MCTP_CREDIT_DATA_SHIFT)
 
-#define I40E_GLPCI_MCTP_MASK_0                         0x000BE4C4
+#define I40E_GLPCI_MCTP_MASK_0                         0x000BE4C4 /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_MASK_0_GLPCI_MCTP_MASK_0_SHIFT 0
 #define I40E_GLPCI_MCTP_MASK_0_GLPCI_MCTP_MASK_0_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_MCTP_MASK_0_GLPCI_MCTP_MASK_0_SHIFT)
 
-#define I40E_GLPCI_MCTP_MASK_1                         0x000BE4C8
+#define I40E_GLPCI_MCTP_MASK_1                         0x000BE4C8 /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_MASK_1_GLPCI_MCTP_MASK_1_SHIFT 0
 #define I40E_GLPCI_MCTP_MASK_1_GLPCI_MCTP_MASK_1_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_MCTP_MASK_1_GLPCI_MCTP_MASK_1_SHIFT)
 
-#define I40E_GLPCI_MCTP_MASK_2                         0x000BE4CC
+#define I40E_GLPCI_MCTP_MASK_2                         0x000BE4CC /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_MASK_2_GLPCI_MCTP_MASK_2_SHIFT 0
 #define I40E_GLPCI_MCTP_MASK_2_GLPCI_MCTP_MASK_2_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_MCTP_MASK_2_GLPCI_MCTP_MASK_2_SHIFT)
 
-#define I40E_GLPCI_MCTP_MASK_3                         0x000BE4D0
+#define I40E_GLPCI_MCTP_MASK_3                         0x000BE4D0 /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_MASK_3_GLPCI_MCTP_MASK_3_SHIFT 0
 #define I40E_GLPCI_MCTP_MASK_3_GLPCI_MCTP_MASK_3_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_MCTP_MASK_3_GLPCI_MCTP_MASK_3_SHIFT)
 
-#define I40E_GLPCI_MCTP_MAX_PAY                          0x000BE4E8
+#define I40E_GLPCI_MCTP_MAX_PAY                          0x000BE4E8 /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_MAX_PAY_GLPCI_MCTP_MAX_PAY_SHIFT 0
 #define I40E_GLPCI_MCTP_MAX_PAY_GLPCI_MCTP_MAX_PAY_MASK  I40E_MASK(0x7FF, I40E_GLPCI_MCTP_MAX_PAY_GLPCI_MCTP_MAX_PAY_SHIFT)
 
-#define I40E_GLPCI_MCTP_VAL_0                        0x000BE4D4
+#define I40E_GLPCI_MCTP_VAL_0                        0x000BE4D4 /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_VAL_0_GLPCI_MCTP_VAL_0_SHIFT 0
 #define I40E_GLPCI_MCTP_VAL_0_GLPCI_MCTP_VAL_0_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_MCTP_VAL_0_GLPCI_MCTP_VAL_0_SHIFT)
 
-#define I40E_GLPCI_MCTP_VAL_1                        0x000BE4D8
+#define I40E_GLPCI_MCTP_VAL_1                        0x000BE4D8 /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_VAL_1_GLPCI_MCTP_VAL_1_SHIFT 0
 #define I40E_GLPCI_MCTP_VAL_1_GLPCI_MCTP_VAL_1_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_MCTP_VAL_1_GLPCI_MCTP_VAL_1_SHIFT)
 
-#define I40E_GLPCI_MCTP_VAL_2                        0x000BE4DC
+#define I40E_GLPCI_MCTP_VAL_2                        0x000BE4DC /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_VAL_2_GLPCI_MCTP_VAL_2_SHIFT 0
 #define I40E_GLPCI_MCTP_VAL_2_GLPCI_MCTP_VAL_2_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_MCTP_VAL_2_GLPCI_MCTP_VAL_2_SHIFT)
 
-#define I40E_GLPCI_MCTP_VAL_3                        0x000BE4E0
+#define I40E_GLPCI_MCTP_VAL_3                        0x000BE4E0 /* Reset: PCIR */
 #define I40E_GLPCI_MCTP_VAL_3_GLPCI_MCTP_VAL_3_SHIFT 0
 #define I40E_GLPCI_MCTP_VAL_3_GLPCI_MCTP_VAL_3_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_MCTP_VAL_3_GLPCI_MCTP_VAL_3_SHIFT)
 
-#define I40E_GLPCI_OSR_LIMIT                 0x000BE504
+#define I40E_GLPCI_OSR_LIMIT                 0x000BE504 /* Reset: PCIR */
 #define I40E_GLPCI_OSR_LIMIT_OSR_LIMIT_SHIFT 0
 #define I40E_GLPCI_OSR_LIMIT_OSR_LIMIT_MASK  I40E_MASK(0xFF, I40E_GLPCI_OSR_LIMIT_OSR_LIMIT_SHIFT)
 
-#define I40E_GLPCI_PHY_SPARE_IN                    0x000BE508
+#define I40E_GLPCI_PHY_SPARE_IN                    0x000BE508 /* Reset: POR */
 #define I40E_GLPCI_PHY_SPARE_IN_DIG_IN_SPARE_SHIFT 0
 #define I40E_GLPCI_PHY_SPARE_IN_DIG_IN_SPARE_MASK  I40E_MASK(0x3FF, I40E_GLPCI_PHY_SPARE_IN_DIG_IN_SPARE_SHIFT)
 
-#define I40E_GLPCI_PHY_SPARE_OUT                           0x000BE50C
+#define I40E_GLPCI_PHY_SPARE_OUT                           0x000BE50C /* Reset: POR */
 #define I40E_GLPCI_PHY_SPARE_OUT_TAMAR_DIG_OUT_SPARE_SHIFT 0
 #define I40E_GLPCI_PHY_SPARE_OUT_TAMAR_DIG_OUT_SPARE_MASK  I40E_MASK(0x3FF, I40E_GLPCI_PHY_SPARE_OUT_TAMAR_DIG_OUT_SPARE_SHIFT)
 
-#define I40E_GLPCI_SHUTDOWN_DIS                    0x000BE4F0
+#define I40E_GLPCI_SHUTDOWN_DIS                    0x000BE4F0 /* Reset: PCIR */
 #define I40E_GLPCI_SHUTDOWN_DIS_SHUTDOWN_DIS_SHIFT 0
 #define I40E_GLPCI_SHUTDOWN_DIS_SHUTDOWN_DIS_MASK  I40E_MASK(0x1, I40E_GLPCI_SHUTDOWN_DIS_SHUTDOWN_DIS_SHIFT)
 
-#define I40E_GLPCI_SPARE1                               0x000BE510
+#define I40E_GLPCI_SPARE1                               0x000BE510 /* Reset: POR */
 #define I40E_GLPCI_SPARE1_WU_COMPLIANT_CB_SHIFT         0
 #define I40E_GLPCI_SPARE1_WU_COMPLIANT_CB_MASK          I40E_MASK(0x1, I40E_GLPCI_SPARE1_WU_COMPLIANT_CB_SHIFT)
 #define I40E_GLPCI_SPARE1_BYPASS_SIDEBAND_SHIFT         1
@@ -2708,11 +2718,21 @@
 #define I40E_GLPCI_SPARE1_SPARE_SHIFT                   25
 #define I40E_GLPCI_SPARE1_SPARE_MASK                    I40E_MASK(0x7F, I40E_GLPCI_SPARE1_SPARE_SHIFT)
 
-#define I40E_GLPCI_SPARE2             0x000BE514
+#define I40E_GLPCI_SPARE2             0x000BE514 /* Reset: POR */
 #define I40E_GLPCI_SPARE2_SPARE_SHIFT 0
 #define I40E_GLPCI_SPARE2_SPARE_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE2_SPARE_SHIFT)
 
-#define I40E_GLQF_L3_MAP(_i)                (0x0026C700 + ((_i) * 4)) /* _i=0...63 */
+#define I40E_GLQF_ABORT_MASK(_i)                   (0x0026CCC8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
+#define I40E_GLQF_ABORT_MASK_MAX_INDEX             1
+#define I40E_GLQF_ABORT_MASK_GLQF_ABORT_MASK_SHIFT 0
+#define I40E_GLQF_ABORT_MASK_GLQF_ABORT_MASK_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_ABORT_MASK_GLQF_ABORT_MASK_SHIFT)
+
+#define I40E_GLQF_L2_MAP(_i)               (0x0026CBF8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
+#define I40E_GLQF_L2_MAP_MAX_INDEX         1
+#define I40E_GLQF_L2_MAP_GLQF_L2_MAP_SHIFT 0
+#define I40E_GLQF_L2_MAP_GLQF_L2_MAP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_L2_MAP_GLQF_L2_MAP_SHIFT)
+
+#define I40E_GLQF_L3_MAP(_i)                (0x0026C700 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
 #define I40E_GLQF_L3_MAP_MAX_INDEX          63
 #define I40E_GLQF_L3_MAP_TR_IDX_CODE_SHIFT  0
 #define I40E_GLQF_L3_MAP_TR_IDX_CODE_MASK   I40E_MASK(0x3F, I40E_GLQF_L3_MAP_TR_IDX_CODE_SHIFT)
@@ -2723,115 +2743,191 @@
 #define I40E_GLQF_L3_MAP_MIN_SKIP_ENA_SHIFT 15
 #define I40E_GLQF_L3_MAP_MIN_SKIP_ENA_MASK  I40E_MASK(0x1, I40E_GLQF_L3_MAP_MIN_SKIP_ENA_SHIFT)
 
-#define I40E_GLRCB_DBG_CTL                0x00122620
+#define I40E_GLQF_OPT_MAP                   0x0026CBDC /* Reset: CORER */
+#define I40E_GLQF_OPT_MAP_FRAG_IDX_SHIFT    0
+#define I40E_GLQF_OPT_MAP_FRAG_IDX_MASK     I40E_MASK(0x3F, I40E_GLQF_OPT_MAP_FRAG_IDX_SHIFT)
+#define I40E_GLQF_OPT_MAP_IP_OPT_IDX_SHIFT  12
+#define I40E_GLQF_OPT_MAP_IP_OPT_IDX_MASK   I40E_MASK(0x3F, I40E_GLQF_OPT_MAP_IP_OPT_IDX_SHIFT)
+#define I40E_GLQF_OPT_MAP_TCP_OPT_IDX_SHIFT 18
+#define I40E_GLQF_OPT_MAP_TCP_OPT_IDX_MASK  I40E_MASK(0x3F, I40E_GLQF_OPT_MAP_TCP_OPT_IDX_SHIFT)
+
+#define I40E_GLRCB_DBG_CTL                0x00122620 /* Reset: CORER */
 #define I40E_GLRCB_DBG_CTL_MEM_ADDR_SHIFT 0
 #define I40E_GLRCB_DBG_CTL_MEM_ADDR_MASK  I40E_MASK(0xFFFF, I40E_GLRCB_DBG_CTL_MEM_ADDR_SHIFT)
 #define I40E_GLRCB_DBG_CTL_MEM_SEL_SHIFT  16
 #define I40E_GLRCB_DBG_CTL_MEM_SEL_MASK   I40E_MASK(0x1F, I40E_GLRCB_DBG_CTL_MEM_SEL_SHIFT)
 
-#define I40E_GLRCB_DBG_FEAT                0x0012266C
+#define I40E_GLRCB_DBG_DATA0                0x00122628 /* Reset: CORER */
+#define I40E_GLRCB_DBG_DATA0_DBG_DATA_SHIFT 0
+#define I40E_GLRCB_DBG_DATA0_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA0_DBG_DATA_SHIFT)
+
+#define I40E_GLRCB_DBG_DATA1                0x0012262C /* Reset: CORER */
+#define I40E_GLRCB_DBG_DATA1_DBG_DATA_SHIFT 0
+#define I40E_GLRCB_DBG_DATA1_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA1_DBG_DATA_SHIFT)
+
+#define I40E_GLRCB_DBG_DATA2                0x00122630 /* Reset: CORER */
+#define I40E_GLRCB_DBG_DATA2_DBG_DATA_SHIFT 0
+#define I40E_GLRCB_DBG_DATA2_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA2_DBG_DATA_SHIFT)
+
+#define I40E_GLRCB_DBG_DATA3                0x00122634 /* Reset: CORER */
+#define I40E_GLRCB_DBG_DATA3_DBG_DATA_SHIFT 0
+#define I40E_GLRCB_DBG_DATA3_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA3_DBG_DATA_SHIFT)
+
+#define I40E_GLRCB_DBG_DATA4                0x00122638 /* Reset: CORER */
+#define I40E_GLRCB_DBG_DATA4_DBG_DATA_SHIFT 0
+#define I40E_GLRCB_DBG_DATA4_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA4_DBG_DATA_SHIFT)
+
+#define I40E_GLRCB_DBG_DATA5                0x0012263C /* Reset: CORER */
+#define I40E_GLRCB_DBG_DATA5_DBG_DATA_SHIFT 0
+#define I40E_GLRCB_DBG_DATA5_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCB_DBG_DATA5_DBG_DATA_SHIFT)
+
+#define I40E_GLRCB_DBG_FEAT                0x0012266C /* Reset: CORER */
 #define I40E_GLRCB_DBG_FEAT_SET_DROP_SHIFT 0
 #define I40E_GLRCB_DBG_FEAT_SET_DROP_MASK  I40E_MASK(0xF, I40E_GLRCB_DBG_FEAT_SET_DROP_SHIFT)
 
-#define I40E_GLRCB_DBG_RD_STOP           0x00122640
+#define I40E_GLRCB_DBG_RD_STOP           0x00122640 /* Reset: CORER */
 #define I40E_GLRCB_DBG_RD_STOP_ENA_SHIFT 0
 #define I40E_GLRCB_DBG_RD_STOP_ENA_MASK  I40E_MASK(0x1, I40E_GLRCB_DBG_RD_STOP_ENA_SHIFT)
 
-#define I40E_GLRCB_LL_BP_CFG                0x0012261C
+#define I40E_GLRCB_LL_BP_CFG                0x0012261C /* Reset: CORER */
 #define I40E_GLRCB_LL_BP_CFG_MIN_THRS_SHIFT 0
 #define I40E_GLRCB_LL_BP_CFG_MIN_THRS_MASK  I40E_MASK(0xFFFF, I40E_GLRCB_LL_BP_CFG_MIN_THRS_SHIFT)
 #define I40E_GLRCB_LL_BP_CFG_MAX_THRS_SHIFT 16
 #define I40E_GLRCB_LL_BP_CFG_MAX_THRS_MASK  I40E_MASK(0xFFFF, I40E_GLRCB_LL_BP_CFG_MAX_THRS_SHIFT)
 
-#define I40E_GLRCB_TO_1MS_TICK_CFG                    0x00122624
+#define I40E_GLRCB_TO_1MS_TICK_CFG                    0x00122624 /* Reset: CORER */
 #define I40E_GLRCB_TO_1MS_TICK_CFG_UC_DIV_RATIO_SHIFT 0
 #define I40E_GLRCB_TO_1MS_TICK_CFG_UC_DIV_RATIO_MASK  I40E_MASK(0xFFFFF, I40E_GLRCB_TO_1MS_TICK_CFG_UC_DIV_RATIO_SHIFT)
 
-#define I40E_GLRLAN_COMPLETION_FIFO_CTL                  0x0012A574
+#define I40E_GLRLAN_COMPLETION_FIFO_CTL                  0x0012A574 /* Reset: CORER */
 #define I40E_GLRLAN_COMPLETION_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_COMPLETION_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_COMPLETION_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_DATA_FLUSH_REQ_FIFO_CTL                  0x0012A58C
+#define I40E_GLRLAN_DATA_FLUSH_REQ_FIFO_CTL                  0x0012A58C /* Reset: CORER */
 #define I40E_GLRLAN_DATA_FLUSH_REQ_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_DATA_FLUSH_REQ_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_DATA_FLUSH_REQ_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_DBG_CTL                0x0012A594
+#define I40E_GLRLAN_DBG_CTL                0x0012A594 /* Reset: CORER */
 #define I40E_GLRLAN_DBG_CTL_MEM_ADDR_SHIFT 0
 #define I40E_GLRLAN_DBG_CTL_MEM_ADDR_MASK  I40E_MASK(0xFFFF, I40E_GLRLAN_DBG_CTL_MEM_ADDR_SHIFT)
 #define I40E_GLRLAN_DBG_CTL_MEM_SEL_SHIFT  16
 #define I40E_GLRLAN_DBG_CTL_MEM_SEL_MASK   I40E_MASK(0x1F, I40E_GLRLAN_DBG_CTL_MEM_SEL_SHIFT)
 
-#define I40E_GLRLAN_DIX_WB_FIFO_CTL                  0x0012A590
+#define I40E_GLRLAN_DBG_DATA0                0x0012A598 /* Reset: CORER */
+#define I40E_GLRLAN_DBG_DATA0_DBG_DATA_SHIFT 0
+#define I40E_GLRLAN_DBG_DATA0_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA0_DBG_DATA_SHIFT)
+
+#define I40E_GLRLAN_DBG_DATA1                0x0012A59C /* Reset: CORER */
+#define I40E_GLRLAN_DBG_DATA1_DBG_DATA_SHIFT 0
+#define I40E_GLRLAN_DBG_DATA1_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA1_DBG_DATA_SHIFT)
+
+#define I40E_GLRLAN_DBG_DATA2                0x0012A5A0 /* Reset: CORER */
+#define I40E_GLRLAN_DBG_DATA2_DBG_DATA_SHIFT 0
+#define I40E_GLRLAN_DBG_DATA2_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA2_DBG_DATA_SHIFT)
+
+#define I40E_GLRLAN_DBG_DATA3                0x0012A5A4 /* Reset: CORER */
+#define I40E_GLRLAN_DBG_DATA3_DBG_DATA_SHIFT 0
+#define I40E_GLRLAN_DBG_DATA3_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA3_DBG_DATA_SHIFT)
+
+#define I40E_GLRLAN_DBG_DATA4                0x0012A5A8 /* Reset: CORER */
+#define I40E_GLRLAN_DBG_DATA4_DBG_DATA_SHIFT 0
+#define I40E_GLRLAN_DBG_DATA4_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA4_DBG_DATA_SHIFT)
+
+#define I40E_GLRLAN_DBG_DATA5                0x0012A5AC /* Reset: CORER */
+#define I40E_GLRLAN_DBG_DATA5_DBG_DATA_SHIFT 0
+#define I40E_GLRLAN_DBG_DATA5_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA5_DBG_DATA_SHIFT)
+
+#define I40E_GLRLAN_DBG_DATA6                0x0012A5B0 /* Reset: CORER */
+#define I40E_GLRLAN_DBG_DATA6_DBG_DATA_SHIFT 0
+#define I40E_GLRLAN_DBG_DATA6_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA6_DBG_DATA_SHIFT)
+
+#define I40E_GLRLAN_DBG_DATA7                0x0012A5B4 /* Reset: CORER */
+#define I40E_GLRLAN_DBG_DATA7_DBG_DATA_SHIFT 0
+#define I40E_GLRLAN_DBG_DATA7_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DBG_DATA7_DBG_DATA_SHIFT)
+
+#define I40E_GLRLAN_DIX_WB_FIFO_CTL                  0x0012A590 /* Reset: CORER */
 #define I40E_GLRLAN_DIX_WB_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_DIX_WB_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_DIX_WB_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_DSCR_FETCH_FIFO_CTL                  0x0012A584
+#define I40E_GLRLAN_DSCR_FETCH_FIFO_CTL                  0x0012A584 /* Reset: CORER */
 #define I40E_GLRLAN_DSCR_FETCH_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_DSCR_FETCH_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_DSCR_FETCH_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_DSCR_REQ_FIFO_CTL                  0x0012A554
+#define I40E_GLRLAN_DSCR_REQ_FIFO_CTL                  0x0012A554 /* Reset: CORER */
 #define I40E_GLRLAN_DSCR_REQ_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_DSCR_REQ_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_DSCR_REQ_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_DSCR_WR_REQ_FIFO_CTL                  0x0012A57C
+#define I40E_GLRLAN_DSCR_WR_REQ_FIFO_CTL                  0x0012A57C /* Reset: CORER */
 #define I40E_GLRLAN_DSCR_WR_REQ_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_DSCR_WR_REQ_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_DSCR_WR_REQ_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_DUMMY_CNTX_0(_i)              (0x0012A5BC + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLRLAN_DUMMY_CNTX_0(_i)              (0x0012A5BC + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLRLAN_DUMMY_CNTX_0_MAX_INDEX        3
 #define I40E_GLRLAN_DUMMY_CNTX_0_DUMMY_CNTX_SHIFT 0
 #define I40E_GLRLAN_DUMMY_CNTX_0_DUMMY_CNTX_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DUMMY_CNTX_0_DUMMY_CNTX_SHIFT)
 
-#define I40E_GLRLAN_DUMMY_CNTX_1(_i)              (0x0012A5CC + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLRLAN_DUMMY_CNTX_1(_i)              (0x0012A5CC + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLRLAN_DUMMY_CNTX_1_MAX_INDEX        3
 #define I40E_GLRLAN_DUMMY_CNTX_1_DUMMY_CNTX_SHIFT 0
 #define I40E_GLRLAN_DUMMY_CNTX_1_DUMMY_CNTX_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_DUMMY_CNTX_1_DUMMY_CNTX_SHIFT)
 
-#define I40E_GLRLAN_DUMMY_CNTX_ENA                      0x0012A5DC
+#define I40E_GLRLAN_DUMMY_CNTX_ENA                      0x0012A5DC /* Reset: CORER */
 #define I40E_GLRLAN_DUMMY_CNTX_ENA_DUMMY_CNTX_ENA_SHIFT 0
 #define I40E_GLRLAN_DUMMY_CNTX_ENA_DUMMY_CNTX_ENA_MASK  I40E_MASK(0x1, I40E_GLRLAN_DUMMY_CNTX_ENA_DUMMY_CNTX_ENA_SHIFT)
 
-#define I40E_GLRLAN_ITR_NOTIFICATION_FIFO_CTL                  0x0012A578
+#define I40E_GLRLAN_ITR_NOTIFICATION_FIFO_CTL                  0x0012A578 /* Reset: CORER */
 #define I40E_GLRLAN_ITR_NOTIFICATION_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_ITR_NOTIFICATION_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_ITR_NOTIFICATION_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_ITR_WR_DONE_FIFO_CTL                  0x0012A580
+#define I40E_GLRLAN_ITR_WR_DONE_FIFO_CTL                  0x0012A580 /* Reset: CORER */
 #define I40E_GLRLAN_ITR_WR_DONE_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_ITR_WR_DONE_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_ITR_WR_DONE_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_PIM_REQ_FIFO_CTL                  0x0012A570
+#define I40E_GLRLAN_PIM_REQ_FIFO_CTL                  0x0012A570 /* Reset: CORER */
 #define I40E_GLRLAN_PIM_REQ_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_PIM_REQ_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_PIM_REQ_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_QCNTX_DATA_WB_FIFO_CTL                  0x0012A568
+#define I40E_GLRLAN_QCNTX_DATA_WB_FIFO_CTL                  0x0012A568 /* Reset: CORER */
 #define I40E_GLRLAN_QCNTX_DATA_WB_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_QCNTX_DATA_WB_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_QCNTX_DATA_WB_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_QCNTX_MT2L_WB_FIFO_CTL                  0x0012A56C
+#define I40E_GLRLAN_QCNTX_MT2L_WB_FIFO_CTL                  0x0012A56C /* Reset: CORER */
 #define I40E_GLRLAN_QCNTX_MT2L_WB_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_QCNTX_MT2L_WB_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_QCNTX_MT2L_WB_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_QCNTX_NUM_WB_FIFO_CTL                  0x0012A564
+#define I40E_GLRLAN_QCNTX_NUM_WB_FIFO_CTL                  0x0012A564 /* Reset: CORER */
 #define I40E_GLRLAN_QCNTX_NUM_WB_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_QCNTX_NUM_WB_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_QCNTX_NUM_WB_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_RDPU_ATTR_FIFO_CTL                  0x0012A55C
+#define I40E_GLRLAN_RDPU_ATTR_FIFO_CTL                  0x0012A55C /* Reset: CORER */
 #define I40E_GLRLAN_RDPU_ATTR_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_RDPU_ATTR_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_RDPU_ATTR_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_RDPU_CMD_FIFO_CTL                  0x0012A558
+#define I40E_GLRLAN_RDPU_CMD_FIFO_CTL                  0x0012A558 /* Reset: CORER */
 #define I40E_GLRLAN_RDPU_CMD_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_RDPU_CMD_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_RDPU_CMD_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_RDPU_WB_FIFO_CTL                  0x0012A560
+#define I40E_GLRLAN_RDPU_WB_FIFO_CTL                  0x0012A560 /* Reset: CORER */
 #define I40E_GLRLAN_RDPU_WB_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_RDPU_WB_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_RDPU_WB_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_GLRLAN_REQ_INFO_FIFO_CTL                  0x0012A588
+#define I40E_GLRLAN_REQ_INFO_FIFO_CTL                  0x0012A588 /* Reset: CORER */
 #define I40E_GLRLAN_REQ_INFO_FIFO_CTL_BP_THRSHLD_SHIFT 0
 #define I40E_GLRLAN_REQ_INFO_FIFO_CTL_BP_THRSHLD_MASK  I40E_MASK(0x3FF, I40E_GLRLAN_REQ_INFO_FIFO_CTL_BP_THRSHLD_SHIFT)
 
-#define I40E_ITR_CAUSE_MEM_0_CFG                    0x0003FC00
+#define I40E_GLRLAN_SPARE                  0x0012A5B8 /* Reset: CORER */
+#define I40E_GLRLAN_SPARE_SPARE_BITS_SHIFT 0
+#define I40E_GLRLAN_SPARE_SPARE_BITS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRLAN_SPARE_SPARE_BITS_SHIFT)
+
+#define I40E_GLTLAN_MAX_TCBCMD                      0x000E64D4 /* Reset: CORER */
+#define I40E_GLTLAN_MAX_TCBCMD_MAX_TCBCMD_SHIFT     0
+#define I40E_GLTLAN_MAX_TCBCMD_MAX_TCBCMD_MASK      I40E_MASK(0xF, I40E_GLTLAN_MAX_TCBCMD_MAX_TCBCMD_SHIFT)
+#define I40E_GLTLAN_MAX_TCBCMD_RSVD1_SHIFT          8
+#define I40E_GLTLAN_MAX_TCBCMD_RSVD1_MASK           I40E_MASK(0x3, I40E_GLTLAN_MAX_TCBCMD_RSVD1_SHIFT)
+#define I40E_GLTLAN_MAX_TCBCMD_MULTPL_REQ_DIS_SHIFT 31
+#define I40E_GLTLAN_MAX_TCBCMD_MULTPL_REQ_DIS_MASK  I40E_MASK(0x1, I40E_GLTLAN_MAX_TCBCMD_MULTPL_REQ_DIS_SHIFT)
+
+#define I40E_ITR_CAUSE_MEM_0_CFG                    0x0003FC00 /* Reset: POR */
 #define I40E_ITR_CAUSE_MEM_0_CFG_ECC_EN_SHIFT       0
 #define I40E_ITR_CAUSE_MEM_0_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_ITR_CAUSE_MEM_0_CFG_ECC_EN_SHIFT)
 #define I40E_ITR_CAUSE_MEM_0_CFG_ECC_INVERT_1_SHIFT 1
@@ -2853,7 +2949,7 @@
 #define I40E_ITR_CAUSE_MEM_0_CFG_RM_SHIFT           16
 #define I40E_ITR_CAUSE_MEM_0_CFG_RM_MASK            I40E_MASK(0xF, I40E_ITR_CAUSE_MEM_0_CFG_RM_SHIFT)
 
-#define I40E_ITR_CAUSE_MEM_0_STATUS                        0x0003FC04
+#define I40E_ITR_CAUSE_MEM_0_STATUS                        0x0003FC04 /* Reset: POR */
 #define I40E_ITR_CAUSE_MEM_0_STATUS_ECC_ERR_SHIFT          0
 #define I40E_ITR_CAUSE_MEM_0_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_ITR_CAUSE_MEM_0_STATUS_ECC_ERR_SHIFT)
 #define I40E_ITR_CAUSE_MEM_0_STATUS_ECC_FIX_SHIFT          1
@@ -2863,7 +2959,7 @@
 #define I40E_ITR_CAUSE_MEM_0_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_ITR_CAUSE_MEM_0_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_ITR_CAUSE_MEM_0_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_ITR_CAUSE_MEM_1_CFG                    0x0003FC08
+#define I40E_ITR_CAUSE_MEM_1_CFG                    0x0003FC08 /* Reset: POR */
 #define I40E_ITR_CAUSE_MEM_1_CFG_ECC_EN_SHIFT       0
 #define I40E_ITR_CAUSE_MEM_1_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_ITR_CAUSE_MEM_1_CFG_ECC_EN_SHIFT)
 #define I40E_ITR_CAUSE_MEM_1_CFG_ECC_INVERT_1_SHIFT 1
@@ -2885,7 +2981,7 @@
 #define I40E_ITR_CAUSE_MEM_1_CFG_RM_SHIFT           16
 #define I40E_ITR_CAUSE_MEM_1_CFG_RM_MASK            I40E_MASK(0xF, I40E_ITR_CAUSE_MEM_1_CFG_RM_SHIFT)
 
-#define I40E_ITR_CAUSE_MEM_1_STATUS                        0x0003FC0C
+#define I40E_ITR_CAUSE_MEM_1_STATUS                        0x0003FC0C /* Reset: POR */
 #define I40E_ITR_CAUSE_MEM_1_STATUS_ECC_ERR_SHIFT          0
 #define I40E_ITR_CAUSE_MEM_1_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_ITR_CAUSE_MEM_1_STATUS_ECC_ERR_SHIFT)
 #define I40E_ITR_CAUSE_MEM_1_STATUS_ECC_FIX_SHIFT          1
@@ -2895,15 +2991,15 @@
 #define I40E_ITR_CAUSE_MEM_1_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_ITR_CAUSE_MEM_1_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_ITR_CAUSE_MEM_1_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_ITR_ECC_COR_ERR           0x0003FC24
+#define I40E_ITR_ECC_COR_ERR           0x0003FC24 /* Reset: POR */
 #define I40E_ITR_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_ITR_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_ITR_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_ITR_ECC_UNCOR_ERR           0x0003FC20
+#define I40E_ITR_ECC_UNCOR_ERR           0x0003FC20 /* Reset: POR */
 #define I40E_ITR_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_ITR_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_ITR_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_ITR_MSIX_MEM_0_CFG                    0x0003FC10
+#define I40E_ITR_MSIX_MEM_0_CFG                    0x0003FC10 /* Reset: POR */
 #define I40E_ITR_MSIX_MEM_0_CFG_ECC_EN_SHIFT       0
 #define I40E_ITR_MSIX_MEM_0_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_ITR_MSIX_MEM_0_CFG_ECC_EN_SHIFT)
 #define I40E_ITR_MSIX_MEM_0_CFG_ECC_INVERT_1_SHIFT 1
@@ -2925,7 +3021,7 @@
 #define I40E_ITR_MSIX_MEM_0_CFG_RM_SHIFT           16
 #define I40E_ITR_MSIX_MEM_0_CFG_RM_MASK            I40E_MASK(0xF, I40E_ITR_MSIX_MEM_0_CFG_RM_SHIFT)
 
-#define I40E_ITR_MSIX_MEM_0_STATUS                        0x0003FC14
+#define I40E_ITR_MSIX_MEM_0_STATUS                        0x0003FC14 /* Reset: POR */
 #define I40E_ITR_MSIX_MEM_0_STATUS_ECC_ERR_SHIFT          0
 #define I40E_ITR_MSIX_MEM_0_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_ITR_MSIX_MEM_0_STATUS_ECC_ERR_SHIFT)
 #define I40E_ITR_MSIX_MEM_0_STATUS_ECC_FIX_SHIFT          1
@@ -2935,7 +3031,7 @@
 #define I40E_ITR_MSIX_MEM_0_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_ITR_MSIX_MEM_0_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_ITR_MSIX_MEM_0_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_ITR_MSIX_MEM_1_CFG                    0x0003FC18
+#define I40E_ITR_MSIX_MEM_1_CFG                    0x0003FC18 /* Reset: POR */
 #define I40E_ITR_MSIX_MEM_1_CFG_ECC_EN_SHIFT       0
 #define I40E_ITR_MSIX_MEM_1_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_ITR_MSIX_MEM_1_CFG_ECC_EN_SHIFT)
 #define I40E_ITR_MSIX_MEM_1_CFG_ECC_INVERT_1_SHIFT 1
@@ -2957,7 +3053,7 @@
 #define I40E_ITR_MSIX_MEM_1_CFG_RM_SHIFT           16
 #define I40E_ITR_MSIX_MEM_1_CFG_RM_MASK            I40E_MASK(0xF, I40E_ITR_MSIX_MEM_1_CFG_RM_SHIFT)
 
-#define I40E_ITR_MSIX_MEM_1_STATUS                        0x0003FC1C
+#define I40E_ITR_MSIX_MEM_1_STATUS                        0x0003FC1C /* Reset: POR */
 #define I40E_ITR_MSIX_MEM_1_STATUS_ECC_ERR_SHIFT          0
 #define I40E_ITR_MSIX_MEM_1_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_ITR_MSIX_MEM_1_STATUS_ECC_ERR_SHIFT)
 #define I40E_ITR_MSIX_MEM_1_STATUS_ECC_FIX_SHIFT          1
@@ -2967,7 +3063,7 @@
 #define I40E_ITR_MSIX_MEM_1_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_ITR_MSIX_MEM_1_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_ITR_MSIX_MEM_1_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_ADMIN_Q_CFG                    0x0008304C
+#define I40E_MNG_ADMIN_Q_CFG                    0x0008304C /* Reset: POR */
 #define I40E_MNG_ADMIN_Q_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_ADMIN_Q_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_ADMIN_Q_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_ADMIN_Q_CFG_ECC_INVERT_1_SHIFT 1
@@ -2989,7 +3085,7 @@
 #define I40E_MNG_ADMIN_Q_CFG_RM_SHIFT           16
 #define I40E_MNG_ADMIN_Q_CFG_RM_MASK            I40E_MASK(0xF, I40E_MNG_ADMIN_Q_CFG_RM_SHIFT)
 
-#define I40E_MNG_ADMIN_Q_STATUS                        0x00083050
+#define I40E_MNG_ADMIN_Q_STATUS                        0x00083050 /* Reset: POR */
 #define I40E_MNG_ADMIN_Q_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_ADMIN_Q_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_ADMIN_Q_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_ADMIN_Q_STATUS_ECC_FIX_SHIFT          1
@@ -2999,7 +3095,7 @@
 #define I40E_MNG_ADMIN_Q_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_ADMIN_Q_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_ADMIN_Q_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_ALTERNATE_CFG                    0x000830A4
+#define I40E_MNG_ALTERNATE_CFG                    0x000830A4 /* Reset: POR */
 #define I40E_MNG_ALTERNATE_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_ALTERNATE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_ALTERNATE_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_ALTERNATE_CFG_ECC_INVERT_1_SHIFT 1
@@ -3021,7 +3117,7 @@
 #define I40E_MNG_ALTERNATE_CFG_RM_SHIFT           16
 #define I40E_MNG_ALTERNATE_CFG_RM_MASK            I40E_MASK(0xF, I40E_MNG_ALTERNATE_CFG_RM_SHIFT)
 
-#define I40E_MNG_ALTERNATE_STATUS                        0x000830A8
+#define I40E_MNG_ALTERNATE_STATUS                        0x000830A8 /* Reset: POR */
 #define I40E_MNG_ALTERNATE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_ALTERNATE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_ALTERNATE_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_ALTERNATE_STATUS_ECC_FIX_SHIFT          1
@@ -3031,7 +3127,7 @@
 #define I40E_MNG_ALTERNATE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_ALTERNATE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_ALTERNATE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_CODE_BANK_CFG                    0x00083054
+#define I40E_MNG_CODE_BANK_CFG                    0x00083054 /* Reset: POR */
 #define I40E_MNG_CODE_BANK_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_CODE_BANK_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_CODE_BANK_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_CODE_BANK_CFG_ECC_INVERT_1_SHIFT 1
@@ -3053,7 +3149,7 @@
 #define I40E_MNG_CODE_BANK_CFG_RM_SHIFT           16
 #define I40E_MNG_CODE_BANK_CFG_RM_MASK            I40E_MASK(0xF, I40E_MNG_CODE_BANK_CFG_RM_SHIFT)
 
-#define I40E_MNG_CODE_BANK_STATUS                        0x00083058
+#define I40E_MNG_CODE_BANK_STATUS                        0x00083058 /* Reset: POR */
 #define I40E_MNG_CODE_BANK_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_CODE_BANK_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_CODE_BANK_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_CODE_BANK_STATUS_ECC_FIX_SHIFT          1
@@ -3063,15 +3159,15 @@
 #define I40E_MNG_CODE_BANK_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_CODE_BANK_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_CODE_BANK_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_ECC_COR_ERR           0x000830B8
+#define I40E_MNG_ECC_COR_ERR           0x000830B8 /* Reset: POR */
 #define I40E_MNG_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_MNG_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_MNG_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_MNG_ECC_UNCOR_ERR           0x000830B4
+#define I40E_MNG_ECC_UNCOR_ERR           0x000830B4 /* Reset: POR */
 #define I40E_MNG_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_MNG_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_MNG_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_MNG_POPULATED_DATA_CFG                    0x00083064
+#define I40E_MNG_POPULATED_DATA_CFG                    0x00083064 /* Reset: POR */
 #define I40E_MNG_POPULATED_DATA_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_POPULATED_DATA_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_POPULATED_DATA_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_POPULATED_DATA_CFG_ECC_INVERT_1_SHIFT 1
@@ -3093,7 +3189,7 @@
 #define I40E_MNG_POPULATED_DATA_CFG_RM_SHIFT           16
 #define I40E_MNG_POPULATED_DATA_CFG_RM_MASK            I40E_MASK(0xF, I40E_MNG_POPULATED_DATA_CFG_RM_SHIFT)
 
-#define I40E_MNG_POPULATED_DATA_STATUS                        0x00083068
+#define I40E_MNG_POPULATED_DATA_STATUS                        0x00083068 /* Reset: POR */
 #define I40E_MNG_POPULATED_DATA_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_POPULATED_DATA_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_POPULATED_DATA_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_POPULATED_DATA_STATUS_ECC_FIX_SHIFT          1
@@ -3103,7 +3199,7 @@
 #define I40E_MNG_POPULATED_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_POPULATED_DATA_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_POPULATED_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_POPULATED_DATA0_CFG                    0x0008305C
+#define I40E_MNG_POPULATED_DATA0_CFG                    0x0008305C /* Reset: POR */
 #define I40E_MNG_POPULATED_DATA0_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_POPULATED_DATA0_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_POPULATED_DATA0_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_POPULATED_DATA0_CFG_ECC_INVERT_1_SHIFT 1
@@ -3125,7 +3221,7 @@
 #define I40E_MNG_POPULATED_DATA0_CFG_RM_SHIFT           16
 #define I40E_MNG_POPULATED_DATA0_CFG_RM_MASK            I40E_MASK(0xF, I40E_MNG_POPULATED_DATA0_CFG_RM_SHIFT)
 
-#define I40E_MNG_POPULATED_DATA0_STATUS                        0x00083060
+#define I40E_MNG_POPULATED_DATA0_STATUS                        0x00083060 /* Reset: POR */
 #define I40E_MNG_POPULATED_DATA0_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_POPULATED_DATA0_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_POPULATED_DATA0_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_POPULATED_DATA0_STATUS_ECC_FIX_SHIFT          1
@@ -3135,7 +3231,7 @@
 #define I40E_MNG_POPULATED_DATA0_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_POPULATED_DATA0_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_POPULATED_DATA0_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_ROM_CFG                    0x000830AC
+#define I40E_MNG_ROM_CFG                    0x000830AC /* Reset: POR */
 #define I40E_MNG_ROM_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_ROM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_ROM_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_ROM_CFG_ECC_INVERT_1_SHIFT 1
@@ -3157,7 +3253,7 @@
 #define I40E_MNG_ROM_CFG_RM_SHIFT           16
 #define I40E_MNG_ROM_CFG_RM_MASK            I40E_MASK(0xF, I40E_MNG_ROM_CFG_RM_SHIFT)
 
-#define I40E_MNG_ROM_STATUS                        0x000830B0
+#define I40E_MNG_ROM_STATUS                        0x000830B0 /* Reset: POR */
 #define I40E_MNG_ROM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_ROM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_ROM_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_ROM_STATUS_ECC_FIX_SHIFT          1
@@ -3167,7 +3263,7 @@
 #define I40E_MNG_ROM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_ROM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_ROM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_RX_BANK_CFG                    0x0008306C
+#define I40E_MNG_RX_BANK_CFG                    0x0008306C /* Reset: POR */
 #define I40E_MNG_RX_BANK_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_RX_BANK_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_RX_BANK_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_RX_BANK_CFG_ECC_INVERT_1_SHIFT 1
@@ -3189,7 +3285,7 @@
 #define I40E_MNG_RX_BANK_CFG_RM_SHIFT           16
 #define I40E_MNG_RX_BANK_CFG_RM_MASK            I40E_MASK(0xF, I40E_MNG_RX_BANK_CFG_RM_SHIFT)
 
-#define I40E_MNG_RX_BANK_STATUS                        0x00083070
+#define I40E_MNG_RX_BANK_STATUS                        0x00083070 /* Reset: POR */
 #define I40E_MNG_RX_BANK_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_RX_BANK_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_RX_BANK_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_RX_BANK_STATUS_ECC_FIX_SHIFT          1
@@ -3199,7 +3295,7 @@
 #define I40E_MNG_RX_BANK_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_RX_BANK_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_RX_BANK_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_RXF_CFG                    0x00083074
+#define I40E_MNG_RXF_CFG                    0x00083074 /* Reset: POR */
 #define I40E_MNG_RXF_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_RXF_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_RXF_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_RXF_CFG_ECC_INVERT_1_SHIFT 1
@@ -3225,7 +3321,7 @@
 #define I40E_MNG_RXF_CFG_RM_B_SHIFT         20
 #define I40E_MNG_RXF_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_MNG_RXF_CFG_RM_B_SHIFT)
 
-#define I40E_MNG_RXF_STATUS                        0x00083078
+#define I40E_MNG_RXF_STATUS                        0x00083078 /* Reset: POR */
 #define I40E_MNG_RXF_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_RXF_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_RXF_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_RXF_STATUS_ECC_FIX_SHIFT          1
@@ -3235,7 +3331,7 @@
 #define I40E_MNG_RXF_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_RXF_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_RXF_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_TX0_GLUE_CFG                    0x0008307C
+#define I40E_MNG_TX0_GLUE_CFG                    0x0008307C /* Reset: POR */
 #define I40E_MNG_TX0_GLUE_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_TX0_GLUE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_TX0_GLUE_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_TX0_GLUE_CFG_ECC_INVERT_1_SHIFT 1
@@ -3261,7 +3357,7 @@
 #define I40E_MNG_TX0_GLUE_CFG_RM_B_SHIFT         20
 #define I40E_MNG_TX0_GLUE_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_MNG_TX0_GLUE_CFG_RM_B_SHIFT)
 
-#define I40E_MNG_TX0_GLUE_STATUS                        0x00083080
+#define I40E_MNG_TX0_GLUE_STATUS                        0x00083080 /* Reset: POR */
 #define I40E_MNG_TX0_GLUE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_TX0_GLUE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_TX0_GLUE_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_TX0_GLUE_STATUS_ECC_FIX_SHIFT          1
@@ -3271,7 +3367,7 @@
 #define I40E_MNG_TX0_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_TX0_GLUE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_TX0_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_TX1_GLUE_CFG                    0x00083084
+#define I40E_MNG_TX1_GLUE_CFG                    0x00083084 /* Reset: POR */
 #define I40E_MNG_TX1_GLUE_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_TX1_GLUE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_TX1_GLUE_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_TX1_GLUE_CFG_ECC_INVERT_1_SHIFT 1
@@ -3297,7 +3393,7 @@
 #define I40E_MNG_TX1_GLUE_CFG_RM_B_SHIFT         20
 #define I40E_MNG_TX1_GLUE_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_MNG_TX1_GLUE_CFG_RM_B_SHIFT)
 
-#define I40E_MNG_TX1_GLUE_STATUS                        0x00083088
+#define I40E_MNG_TX1_GLUE_STATUS                        0x00083088 /* Reset: POR */
 #define I40E_MNG_TX1_GLUE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_TX1_GLUE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_TX1_GLUE_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_TX1_GLUE_STATUS_ECC_FIX_SHIFT          1
@@ -3307,7 +3403,7 @@
 #define I40E_MNG_TX1_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_TX1_GLUE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_TX1_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_TX2_GLUE_CFG                    0x0008308C
+#define I40E_MNG_TX2_GLUE_CFG                    0x0008308C /* Reset: POR */
 #define I40E_MNG_TX2_GLUE_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_TX2_GLUE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_TX2_GLUE_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_TX2_GLUE_CFG_ECC_INVERT_1_SHIFT 1
@@ -3333,7 +3429,7 @@
 #define I40E_MNG_TX2_GLUE_CFG_RM_B_SHIFT         20
 #define I40E_MNG_TX2_GLUE_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_MNG_TX2_GLUE_CFG_RM_B_SHIFT)
 
-#define I40E_MNG_TX2_GLUE_STATUS                        0x00083090
+#define I40E_MNG_TX2_GLUE_STATUS                        0x00083090 /* Reset: POR */
 #define I40E_MNG_TX2_GLUE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_TX2_GLUE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_TX2_GLUE_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_TX2_GLUE_STATUS_ECC_FIX_SHIFT          1
@@ -3343,7 +3439,7 @@
 #define I40E_MNG_TX2_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_TX2_GLUE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_TX2_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_TX3_GLUE_CFG                    0x00083094
+#define I40E_MNG_TX3_GLUE_CFG                    0x00083094 /* Reset: POR */
 #define I40E_MNG_TX3_GLUE_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_TX3_GLUE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_TX3_GLUE_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_TX3_GLUE_CFG_ECC_INVERT_1_SHIFT 1
@@ -3369,7 +3465,7 @@
 #define I40E_MNG_TX3_GLUE_CFG_RM_B_SHIFT         20
 #define I40E_MNG_TX3_GLUE_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_MNG_TX3_GLUE_CFG_RM_B_SHIFT)
 
-#define I40E_MNG_TX3_GLUE_STATUS                        0x00083098
+#define I40E_MNG_TX3_GLUE_STATUS                        0x00083098 /* Reset: POR */
 #define I40E_MNG_TX3_GLUE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_TX3_GLUE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_TX3_GLUE_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_TX3_GLUE_STATUS_ECC_FIX_SHIFT          1
@@ -3379,7 +3475,7 @@
 #define I40E_MNG_TX3_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_TX3_GLUE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_TX3_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_MNG_TX4_GLUE_CFG                    0x0008309C
+#define I40E_MNG_TX4_GLUE_CFG                    0x0008309C /* Reset: POR */
 #define I40E_MNG_TX4_GLUE_CFG_ECC_EN_SHIFT       0
 #define I40E_MNG_TX4_GLUE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_MNG_TX4_GLUE_CFG_ECC_EN_SHIFT)
 #define I40E_MNG_TX4_GLUE_CFG_ECC_INVERT_1_SHIFT 1
@@ -3405,7 +3501,7 @@
 #define I40E_MNG_TX4_GLUE_CFG_RM_B_SHIFT         20
 #define I40E_MNG_TX4_GLUE_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_MNG_TX4_GLUE_CFG_RM_B_SHIFT)
 
-#define I40E_MNG_TX4_GLUE_STATUS                        0x000830A0
+#define I40E_MNG_TX4_GLUE_STATUS                        0x000830A0 /* Reset: POR */
 #define I40E_MNG_TX4_GLUE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_MNG_TX4_GLUE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_MNG_TX4_GLUE_STATUS_ECC_ERR_SHIFT)
 #define I40E_MNG_TX4_GLUE_STATUS_ECC_FIX_SHIFT          1
@@ -3415,7 +3511,7 @@
 #define I40E_MNG_TX4_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_MNG_TX4_GLUE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_MNG_TX4_GLUE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PBLOC_CACHE_DBG_CTL              0x000A808C
+#define I40E_PBLOC_CACHE_DBG_CTL              0x000A808C /* Reset: CORER */
 #define I40E_PBLOC_CACHE_DBG_CTL_ADR_SHIFT    0
 #define I40E_PBLOC_CACHE_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_PBLOC_CACHE_DBG_CTL_ADR_SHIFT)
 #define I40E_PBLOC_CACHE_DBG_CTL_DW_SEL_SHIFT 18
@@ -3425,11 +3521,11 @@
 #define I40E_PBLOC_CACHE_DBG_CTL_DONE_SHIFT   31
 #define I40E_PBLOC_CACHE_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_PBLOC_CACHE_DBG_CTL_DONE_SHIFT)
 
-#define I40E_PBLOC_CACHE_DBG_DATA             0x000A8090
+#define I40E_PBLOC_CACHE_DBG_DATA             0x000A8090 /* Reset: CORER */
 #define I40E_PBLOC_CACHE_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_PBLOC_CACHE_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_PBLOC_CACHE_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_PBLOC_CACHE_MEM_CFG                    0x000A8054
+#define I40E_PBLOC_CACHE_MEM_CFG                    0x000A8054 /* Reset: POR */
 #define I40E_PBLOC_CACHE_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PBLOC_CACHE_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PBLOC_CACHE_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PBLOC_CACHE_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -3451,7 +3547,7 @@
 #define I40E_PBLOC_CACHE_MEM_CFG_RM_SHIFT           16
 #define I40E_PBLOC_CACHE_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PBLOC_CACHE_MEM_CFG_RM_SHIFT)
 
-#define I40E_PBLOC_CACHE_MEM_STATUS                        0x000A8058
+#define I40E_PBLOC_CACHE_MEM_STATUS                        0x000A8058 /* Reset: POR */
 #define I40E_PBLOC_CACHE_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PBLOC_CACHE_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PBLOC_CACHE_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PBLOC_CACHE_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -3461,15 +3557,15 @@
 #define I40E_PBLOC_CACHE_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PBLOC_CACHE_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PBLOC_CACHE_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PBLOC_ECC_COR_ERR           0x000A8080
+#define I40E_PBLOC_ECC_COR_ERR           0x000A8080 /* Reset: POR */
 #define I40E_PBLOC_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_PBLOC_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_PBLOC_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_PBLOC_ECC_UNCOR_ERR           0x000A807C
+#define I40E_PBLOC_ECC_UNCOR_ERR           0x000A807C /* Reset: POR */
 #define I40E_PBLOC_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_PBLOC_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_PBLOC_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_PBLOC_EVICT_MEM_CFG                    0x000A8074
+#define I40E_PBLOC_EVICT_MEM_CFG                    0x000A8074 /* Reset: POR */
 #define I40E_PBLOC_EVICT_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PBLOC_EVICT_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PBLOC_EVICT_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PBLOC_EVICT_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -3495,7 +3591,7 @@
 #define I40E_PBLOC_EVICT_MEM_CFG_RM_B_SHIFT         20
 #define I40E_PBLOC_EVICT_MEM_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_PBLOC_EVICT_MEM_CFG_RM_B_SHIFT)
 
-#define I40E_PBLOC_EVICT_MEM_STATUS                        0x000A8078
+#define I40E_PBLOC_EVICT_MEM_STATUS                        0x000A8078 /* Reset: POR */
 #define I40E_PBLOC_EVICT_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PBLOC_EVICT_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PBLOC_EVICT_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PBLOC_EVICT_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -3505,7 +3601,7 @@
 #define I40E_PBLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PBLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PBLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PBLOC_FILL_MEM_CFG                    0x000A8064
+#define I40E_PBLOC_FILL_MEM_CFG                    0x000A8064 /* Reset: POR */
 #define I40E_PBLOC_FILL_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PBLOC_FILL_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PBLOC_FILL_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PBLOC_FILL_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -3531,7 +3627,7 @@
 #define I40E_PBLOC_FILL_MEM_CFG_RM_B_SHIFT         20
 #define I40E_PBLOC_FILL_MEM_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_PBLOC_FILL_MEM_CFG_RM_B_SHIFT)
 
-#define I40E_PBLOC_FILL_MEM_STATUS                        0x000A8068
+#define I40E_PBLOC_FILL_MEM_STATUS                        0x000A8068 /* Reset: POR */
 #define I40E_PBLOC_FILL_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PBLOC_FILL_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PBLOC_FILL_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PBLOC_FILL_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -3541,7 +3637,7 @@
 #define I40E_PBLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PBLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PBLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PBLOC_PLIST_DBG_CTL              0x000A8094
+#define I40E_PBLOC_PLIST_DBG_CTL              0x000A8094 /* Reset: CORER */
 #define I40E_PBLOC_PLIST_DBG_CTL_ADR_SHIFT    0
 #define I40E_PBLOC_PLIST_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_PBLOC_PLIST_DBG_CTL_ADR_SHIFT)
 #define I40E_PBLOC_PLIST_DBG_CTL_DW_SEL_SHIFT 18
@@ -3551,11 +3647,11 @@
 #define I40E_PBLOC_PLIST_DBG_CTL_DONE_SHIFT   31
 #define I40E_PBLOC_PLIST_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_PBLOC_PLIST_DBG_CTL_DONE_SHIFT)
 
-#define I40E_PBLOC_PLIST_DBG_DATA             0x000A8098
+#define I40E_PBLOC_PLIST_DBG_DATA             0x000A8098 /* Reset: CORER */
 #define I40E_PBLOC_PLIST_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_PBLOC_PLIST_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_PBLOC_PLIST_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_PBLOC_PLIST_MEM_CFG                    0x000A806C
+#define I40E_PBLOC_PLIST_MEM_CFG                    0x000A806C /* Reset: POR */
 #define I40E_PBLOC_PLIST_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PBLOC_PLIST_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PBLOC_PLIST_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PBLOC_PLIST_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -3577,7 +3673,7 @@
 #define I40E_PBLOC_PLIST_MEM_CFG_RM_SHIFT           16
 #define I40E_PBLOC_PLIST_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PBLOC_PLIST_MEM_CFG_RM_SHIFT)
 
-#define I40E_PBLOC_PLIST_MEM_STATUS                        0x000A8070
+#define I40E_PBLOC_PLIST_MEM_STATUS                        0x000A8070 /* Reset: POR */
 #define I40E_PBLOC_PLIST_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PBLOC_PLIST_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PBLOC_PLIST_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PBLOC_PLIST_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -3587,7 +3683,7 @@
 #define I40E_PBLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PBLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PBLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PBLOC_TAG_DBG_CTL              0x000A8084
+#define I40E_PBLOC_TAG_DBG_CTL              0x000A8084 /* Reset: CORER */
 #define I40E_PBLOC_TAG_DBG_CTL_ADR_SHIFT    0
 #define I40E_PBLOC_TAG_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_PBLOC_TAG_DBG_CTL_ADR_SHIFT)
 #define I40E_PBLOC_TAG_DBG_CTL_DW_SEL_SHIFT 18
@@ -3597,11 +3693,11 @@
 #define I40E_PBLOC_TAG_DBG_CTL_DONE_SHIFT   31
 #define I40E_PBLOC_TAG_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_PBLOC_TAG_DBG_CTL_DONE_SHIFT)
 
-#define I40E_PBLOC_TAG_DBG_DATA             0x000A8088
+#define I40E_PBLOC_TAG_DBG_DATA             0x000A8088 /* Reset: CORER */
 #define I40E_PBLOC_TAG_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_PBLOC_TAG_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_PBLOC_TAG_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_PBLOC_TAG_MEM_CFG                    0x000A805C
+#define I40E_PBLOC_TAG_MEM_CFG                    0x000A805C /* Reset: POR */
 #define I40E_PBLOC_TAG_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PBLOC_TAG_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PBLOC_TAG_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PBLOC_TAG_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -3623,7 +3719,7 @@
 #define I40E_PBLOC_TAG_MEM_CFG_RM_SHIFT           16
 #define I40E_PBLOC_TAG_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PBLOC_TAG_MEM_CFG_RM_SHIFT)
 
-#define I40E_PBLOC_TAG_MEM_STATUS                        0x000A8060
+#define I40E_PBLOC_TAG_MEM_STATUS                        0x000A8060 /* Reset: POR */
 #define I40E_PBLOC_TAG_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PBLOC_TAG_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PBLOC_TAG_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PBLOC_TAG_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -3633,15 +3729,15 @@
 #define I40E_PBLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PBLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PBLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_ECC_COR_ERR           0x0009D080
+#define I40E_PCIE_ECC_COR_ERR           0x0009D080 /* Reset: POR */
 #define I40E_PCIE_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_PCIE_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_PCIE_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_PCIE_ECC_UNCOR_ERR           0x0009D07C
+#define I40E_PCIE_ECC_UNCOR_ERR           0x0009D07C /* Reset: POR */
 #define I40E_PCIE_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_PCIE_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_PCIE_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_PCIE_IOSF_RX_DATA_CFG                    0x0009D010
+#define I40E_PCIE_IOSF_RX_DATA_CFG                    0x0009D010 /* Reset: POR */
 #define I40E_PCIE_IOSF_RX_DATA_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_IOSF_RX_DATA_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_IOSF_RX_DATA_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_IOSF_RX_DATA_CFG_ECC_INVERT_1_SHIFT 1
@@ -3667,7 +3763,7 @@
 #define I40E_PCIE_IOSF_RX_DATA_CFG_RM_B_SHIFT         20
 #define I40E_PCIE_IOSF_RX_DATA_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_PCIE_IOSF_RX_DATA_CFG_RM_B_SHIFT)
 
-#define I40E_PCIE_IOSF_RX_DATA_STATUS                        0x0009D068
+#define I40E_PCIE_IOSF_RX_DATA_STATUS                        0x0009D068 /* Reset: POR */
 #define I40E_PCIE_IOSF_RX_DATA_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_IOSF_RX_DATA_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_IOSF_RX_DATA_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_IOSF_RX_DATA_STATUS_ECC_FIX_SHIFT          1
@@ -3677,7 +3773,7 @@
 #define I40E_PCIE_IOSF_RX_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_IOSF_RX_DATA_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_IOSF_RX_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_IOSF_RX_HDR_CFG                    0x0009D028
+#define I40E_PCIE_IOSF_RX_HDR_CFG                    0x0009D028 /* Reset: POR */
 #define I40E_PCIE_IOSF_RX_HDR_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_IOSF_RX_HDR_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_IOSF_RX_HDR_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_IOSF_RX_HDR_CFG_ECC_INVERT_1_SHIFT 1
@@ -3703,7 +3799,7 @@
 #define I40E_PCIE_IOSF_RX_HDR_CFG_RM_B_SHIFT         20
 #define I40E_PCIE_IOSF_RX_HDR_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_PCIE_IOSF_RX_HDR_CFG_RM_B_SHIFT)
 
-#define I40E_PCIE_IOSF_RX_HDR_STATUS                        0x0009D05C
+#define I40E_PCIE_IOSF_RX_HDR_STATUS                        0x0009D05C /* Reset: POR */
 #define I40E_PCIE_IOSF_RX_HDR_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_IOSF_RX_HDR_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_IOSF_RX_HDR_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_IOSF_RX_HDR_STATUS_ECC_FIX_SHIFT          1
@@ -3713,7 +3809,7 @@
 #define I40E_PCIE_IOSF_RX_HDR_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_IOSF_RX_HDR_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_IOSF_RX_HDR_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_IOSF_TX_DATA_CFG                    0x0009D020
+#define I40E_PCIE_IOSF_TX_DATA_CFG                    0x0009D020 /* Reset: POR */
 #define I40E_PCIE_IOSF_TX_DATA_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_IOSF_TX_DATA_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_IOSF_TX_DATA_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_IOSF_TX_DATA_CFG_ECC_INVERT_1_SHIFT 1
@@ -3739,7 +3835,7 @@
 #define I40E_PCIE_IOSF_TX_DATA_CFG_RM_B_SHIFT         20
 #define I40E_PCIE_IOSF_TX_DATA_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_PCIE_IOSF_TX_DATA_CFG_RM_B_SHIFT)
 
-#define I40E_PCIE_IOSF_TX_DATA_STATUS                        0x0009D050
+#define I40E_PCIE_IOSF_TX_DATA_STATUS                        0x0009D050 /* Reset: POR */
 #define I40E_PCIE_IOSF_TX_DATA_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_IOSF_TX_DATA_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_IOSF_TX_DATA_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_IOSF_TX_DATA_STATUS_ECC_FIX_SHIFT          1
@@ -3749,7 +3845,7 @@
 #define I40E_PCIE_IOSF_TX_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_IOSF_TX_DATA_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_IOSF_TX_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_IOSF_TX_HDR_CFG                    0x0009D034
+#define I40E_PCIE_IOSF_TX_HDR_CFG                    0x0009D034 /* Reset: POR */
 #define I40E_PCIE_IOSF_TX_HDR_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_IOSF_TX_HDR_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_IOSF_TX_HDR_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_IOSF_TX_HDR_CFG_ECC_INVERT_1_SHIFT 1
@@ -3775,7 +3871,7 @@
 #define I40E_PCIE_IOSF_TX_HDR_CFG_RM_B_SHIFT         20
 #define I40E_PCIE_IOSF_TX_HDR_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_PCIE_IOSF_TX_HDR_CFG_RM_B_SHIFT)
 
-#define I40E_PCIE_IOSF_TX_HDR_STATUS                        0x0009D03C
+#define I40E_PCIE_IOSF_TX_HDR_STATUS                        0x0009D03C /* Reset: POR */
 #define I40E_PCIE_IOSF_TX_HDR_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_IOSF_TX_HDR_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_IOSF_TX_HDR_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_IOSF_TX_HDR_STATUS_ECC_FIX_SHIFT          1
@@ -3785,7 +3881,7 @@
 #define I40E_PCIE_IOSF_TX_HDR_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_IOSF_TX_HDR_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_IOSF_TX_HDR_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_MCTP_DATA_CFG                    0x0009D01C
+#define I40E_PCIE_MCTP_DATA_CFG                    0x0009D01C /* Reset: POR */
 #define I40E_PCIE_MCTP_DATA_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_MCTP_DATA_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_MCTP_DATA_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_MCTP_DATA_CFG_ECC_INVERT_1_SHIFT 1
@@ -3807,7 +3903,7 @@
 #define I40E_PCIE_MCTP_DATA_CFG_RM_SHIFT           16
 #define I40E_PCIE_MCTP_DATA_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_MCTP_DATA_CFG_RM_SHIFT)
 
-#define I40E_PCIE_MCTP_DATA_STATUS                        0x0009D04C
+#define I40E_PCIE_MCTP_DATA_STATUS                        0x0009D04C /* Reset: POR */
 #define I40E_PCIE_MCTP_DATA_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_MCTP_DATA_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_MCTP_DATA_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_MCTP_DATA_STATUS_ECC_FIX_SHIFT          1
@@ -3817,7 +3913,7 @@
 #define I40E_PCIE_MCTP_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_MCTP_DATA_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_MCTP_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_MCTP_HDR_CFG                    0x0009D004
+#define I40E_PCIE_MCTP_HDR_CFG                    0x0009D004 /* Reset: POR */
 #define I40E_PCIE_MCTP_HDR_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_MCTP_HDR_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_MCTP_HDR_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_MCTP_HDR_CFG_ECC_INVERT_1_SHIFT 1
@@ -3839,7 +3935,7 @@
 #define I40E_PCIE_MCTP_HDR_CFG_RM_SHIFT           16
 #define I40E_PCIE_MCTP_HDR_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_MCTP_HDR_CFG_RM_SHIFT)
 
-#define I40E_PCIE_MCTP_HDR_STATUS                        0x0009D040
+#define I40E_PCIE_MCTP_HDR_STATUS                        0x0009D040 /* Reset: POR */
 #define I40E_PCIE_MCTP_HDR_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_MCTP_HDR_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_MCTP_HDR_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_MCTP_HDR_STATUS_ECC_FIX_SHIFT          1
@@ -3849,7 +3945,7 @@
 #define I40E_PCIE_MCTP_HDR_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_MCTP_HDR_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_MCTP_HDR_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_MSIX_VEC_CFG                    0x0009D030
+#define I40E_PCIE_MSIX_VEC_CFG                    0x0009D030 /* Reset: POR */
 #define I40E_PCIE_MSIX_VEC_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_MSIX_VEC_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_MSIX_VEC_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_MSIX_VEC_CFG_ECC_INVERT_1_SHIFT 1
@@ -3871,7 +3967,7 @@
 #define I40E_PCIE_MSIX_VEC_CFG_RM_SHIFT           16
 #define I40E_PCIE_MSIX_VEC_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_MSIX_VEC_CFG_RM_SHIFT)
 
-#define I40E_PCIE_MSIX_VEC_STATUS                        0x0009D060
+#define I40E_PCIE_MSIX_VEC_STATUS                        0x0009D060 /* Reset: POR */
 #define I40E_PCIE_MSIX_VEC_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_MSIX_VEC_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_MSIX_VEC_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_MSIX_VEC_STATUS_ECC_FIX_SHIFT          1
@@ -3881,7 +3977,7 @@
 #define I40E_PCIE_MSIX_VEC_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_MSIX_VEC_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_MSIX_VEC_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_LAN_DESC_CFG                    0x0009D06C
+#define I40E_PCIE_NPQ_CPL_LAN_DESC_CFG                    0x0009D06C /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_LAN_DESC_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_CFG_ECC_INVERT_1_SHIFT 1
@@ -3903,7 +3999,7 @@
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_CFG_RM_SHIFT           16
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_NPQ_CPL_LAN_DESC_CFG_RM_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_LAN_DESC_STATUS                        0x0009D074
+#define I40E_PCIE_NPQ_CPL_LAN_DESC_STATUS                        0x0009D074 /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_LAN_DESC_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_STATUS_ECC_FIX_SHIFT          1
@@ -3913,7 +4009,7 @@
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_NPQ_CPL_LAN_DESC_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_LAN_DESC_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_MNG_CFG                    0x0009D008
+#define I40E_PCIE_NPQ_CPL_MNG_CFG                    0x0009D008 /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_MNG_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_NPQ_CPL_MNG_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_MNG_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_NPQ_CPL_MNG_CFG_ECC_INVERT_1_SHIFT 1
@@ -3935,7 +4031,7 @@
 #define I40E_PCIE_NPQ_CPL_MNG_CFG_RM_SHIFT           16
 #define I40E_PCIE_NPQ_CPL_MNG_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_NPQ_CPL_MNG_CFG_RM_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_MNG_STATUS                        0x0009D054
+#define I40E_PCIE_NPQ_CPL_MNG_STATUS                        0x0009D054 /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_MNG_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_NPQ_CPL_MNG_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_MNG_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_NPQ_CPL_MNG_STATUS_ECC_FIX_SHIFT          1
@@ -3945,7 +4041,7 @@
 #define I40E_PCIE_NPQ_CPL_MNG_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_NPQ_CPL_MNG_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_MNG_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_PE_DESC_CFG                    0x0009D078
+#define I40E_PCIE_NPQ_CPL_PE_DESC_CFG                    0x0009D078 /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_PE_DESC_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_NPQ_CPL_PE_DESC_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_PE_DESC_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_NPQ_CPL_PE_DESC_CFG_ECC_INVERT_1_SHIFT 1
@@ -3967,7 +4063,7 @@
 #define I40E_PCIE_NPQ_CPL_PE_DESC_CFG_RM_SHIFT           16
 #define I40E_PCIE_NPQ_CPL_PE_DESC_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_NPQ_CPL_PE_DESC_CFG_RM_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_PE_DESC_STATUS                        0x0009D070
+#define I40E_PCIE_NPQ_CPL_PE_DESC_STATUS                        0x0009D070 /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_PE_DESC_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_NPQ_CPL_PE_DESC_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_PE_DESC_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_NPQ_CPL_PE_DESC_STATUS_ECC_FIX_SHIFT          1
@@ -3977,7 +4073,7 @@
 #define I40E_PCIE_NPQ_CPL_PE_DESC_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_NPQ_CPL_PE_DESC_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_PE_DESC_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_PMAT_CFG                    0x0009D000
+#define I40E_PCIE_NPQ_CPL_PMAT_CFG                    0x0009D000 /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_PMAT_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_NPQ_CPL_PMAT_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_PMAT_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_NPQ_CPL_PMAT_CFG_ECC_INVERT_1_SHIFT 1
@@ -3999,7 +4095,7 @@
 #define I40E_PCIE_NPQ_CPL_PMAT_CFG_RM_SHIFT           16
 #define I40E_PCIE_NPQ_CPL_PMAT_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_NPQ_CPL_PMAT_CFG_RM_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_PMAT_STATUS                        0x0009D048
+#define I40E_PCIE_NPQ_CPL_PMAT_STATUS                        0x0009D048 /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_PMAT_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_NPQ_CPL_PMAT_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_PMAT_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_NPQ_CPL_PMAT_STATUS_ECC_FIX_SHIFT          1
@@ -4009,7 +4105,7 @@
 #define I40E_PCIE_NPQ_CPL_PMAT_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_NPQ_CPL_PMAT_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_PMAT_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_TDPU_CFG                    0x0009D014
+#define I40E_PCIE_NPQ_CPL_TDPU_CFG                    0x0009D014 /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_TDPU_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_NPQ_CPL_TDPU_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_TDPU_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_NPQ_CPL_TDPU_CFG_ECC_INVERT_1_SHIFT 1
@@ -4031,7 +4127,7 @@
 #define I40E_PCIE_NPQ_CPL_TDPU_CFG_RM_SHIFT           16
 #define I40E_PCIE_NPQ_CPL_TDPU_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_NPQ_CPL_TDPU_CFG_RM_SHIFT)
 
-#define I40E_PCIE_NPQ_CPL_TDPU_STATUS                        0x0009D064
+#define I40E_PCIE_NPQ_CPL_TDPU_STATUS                        0x0009D064 /* Reset: POR */
 #define I40E_PCIE_NPQ_CPL_TDPU_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_NPQ_CPL_TDPU_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_TDPU_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_NPQ_CPL_TDPU_STATUS_ECC_FIX_SHIFT          1
@@ -4041,7 +4137,7 @@
 #define I40E_PCIE_NPQ_CPL_TDPU_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_NPQ_CPL_TDPU_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_NPQ_CPL_TDPU_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_PQ_C125_CFG                    0x0009D018
+#define I40E_PCIE_PQ_C125_CFG                    0x0009D018 /* Reset: POR */
 #define I40E_PCIE_PQ_C125_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_PQ_C125_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_PQ_C125_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_PQ_C125_CFG_ECC_INVERT_1_SHIFT 1
@@ -4063,7 +4159,7 @@
 #define I40E_PCIE_PQ_C125_CFG_RM_SHIFT           16
 #define I40E_PCIE_PQ_C125_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_PQ_C125_CFG_RM_SHIFT)
 
-#define I40E_PCIE_PQ_C125_STATUS                        0x0009D038
+#define I40E_PCIE_PQ_C125_STATUS                        0x0009D038 /* Reset: POR */
 #define I40E_PCIE_PQ_C125_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_PQ_C125_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_PQ_C125_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_PQ_C125_STATUS_ECC_FIX_SHIFT          1
@@ -4073,7 +4169,7 @@
 #define I40E_PCIE_PQ_C125_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_PQ_C125_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_PQ_C125_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_PQ_C400_CFG                    0x0009D024
+#define I40E_PCIE_PQ_C400_CFG                    0x0009D024 /* Reset: POR */
 #define I40E_PCIE_PQ_C400_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_PQ_C400_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_PQ_C400_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_PQ_C400_CFG_ECC_INVERT_1_SHIFT 1
@@ -4095,7 +4191,7 @@
 #define I40E_PCIE_PQ_C400_CFG_RM_SHIFT           16
 #define I40E_PCIE_PQ_C400_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_PQ_C400_CFG_RM_SHIFT)
 
-#define I40E_PCIE_PQ_C400_STATUS                        0x0009D044
+#define I40E_PCIE_PQ_C400_STATUS                        0x0009D044 /* Reset: POR */
 #define I40E_PCIE_PQ_C400_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_PQ_C400_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_PQ_C400_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_PQ_C400_STATUS_ECC_FIX_SHIFT          1
@@ -4105,7 +4201,7 @@
 #define I40E_PCIE_PQ_C400_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_PQ_C400_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_PQ_C400_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PCIE_RETRY_BUF_CFG                    0x0009D02C
+#define I40E_PCIE_RETRY_BUF_CFG                    0x0009D02C /* Reset: POR */
 #define I40E_PCIE_RETRY_BUF_CFG_ECC_EN_SHIFT       0
 #define I40E_PCIE_RETRY_BUF_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PCIE_RETRY_BUF_CFG_ECC_EN_SHIFT)
 #define I40E_PCIE_RETRY_BUF_CFG_ECC_INVERT_1_SHIFT 1
@@ -4127,7 +4223,7 @@
 #define I40E_PCIE_RETRY_BUF_CFG_RM_SHIFT           16
 #define I40E_PCIE_RETRY_BUF_CFG_RM_MASK            I40E_MASK(0xF, I40E_PCIE_RETRY_BUF_CFG_RM_SHIFT)
 
-#define I40E_PCIE_RETRY_BUF_STATUS                        0x0009D058
+#define I40E_PCIE_RETRY_BUF_STATUS                        0x0009D058 /* Reset: POR */
 #define I40E_PCIE_RETRY_BUF_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PCIE_RETRY_BUF_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PCIE_RETRY_BUF_STATUS_ECC_ERR_SHIFT)
 #define I40E_PCIE_RETRY_BUF_STATUS_ECC_FIX_SHIFT          1
@@ -4137,7 +4233,7 @@
 #define I40E_PCIE_RETRY_BUF_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PCIE_RETRY_BUF_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PCIE_RETRY_BUF_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PDOC_CACHE_DBG_CTL              0x000D005C
+#define I40E_PDOC_CACHE_DBG_CTL              0x000D005C /* Reset: CORER */
 #define I40E_PDOC_CACHE_DBG_CTL_ADR_SHIFT    0
 #define I40E_PDOC_CACHE_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_PDOC_CACHE_DBG_CTL_ADR_SHIFT)
 #define I40E_PDOC_CACHE_DBG_CTL_DW_SEL_SHIFT 18
@@ -4147,11 +4243,11 @@
 #define I40E_PDOC_CACHE_DBG_CTL_DONE_SHIFT   31
 #define I40E_PDOC_CACHE_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_PDOC_CACHE_DBG_CTL_DONE_SHIFT)
 
-#define I40E_PDOC_CACHE_DBG_DATA             0x000D0060
+#define I40E_PDOC_CACHE_DBG_DATA             0x000D0060 /* Reset: CORER */
 #define I40E_PDOC_CACHE_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_PDOC_CACHE_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_PDOC_CACHE_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_PDOC_CACHE_MEM_CFG                    0x000D002C
+#define I40E_PDOC_CACHE_MEM_CFG                    0x000D002C /* Reset: POR */
 #define I40E_PDOC_CACHE_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PDOC_CACHE_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PDOC_CACHE_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PDOC_CACHE_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -4173,7 +4269,7 @@
 #define I40E_PDOC_CACHE_MEM_CFG_RM_SHIFT           16
 #define I40E_PDOC_CACHE_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PDOC_CACHE_MEM_CFG_RM_SHIFT)
 
-#define I40E_PDOC_CACHE_MEM_STATUS                        0x000D0030
+#define I40E_PDOC_CACHE_MEM_STATUS                        0x000D0030 /* Reset: POR */
 #define I40E_PDOC_CACHE_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PDOC_CACHE_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PDOC_CACHE_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PDOC_CACHE_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -4183,15 +4279,15 @@
 #define I40E_PDOC_CACHE_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PDOC_CACHE_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PDOC_CACHE_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PDOC_ECC_COR_ERR_CNT           0x000D0050
+#define I40E_PDOC_ECC_COR_ERR_CNT           0x000D0050 /* Reset: POR */
 #define I40E_PDOC_ECC_COR_ERR_CNT_CNT_SHIFT 0
 #define I40E_PDOC_ECC_COR_ERR_CNT_CNT_MASK  I40E_MASK(0xFFF, I40E_PDOC_ECC_COR_ERR_CNT_CNT_SHIFT)
 
-#define I40E_PDOC_ECC_UNCOR_ERR_CNT           0x000D004C
+#define I40E_PDOC_ECC_UNCOR_ERR_CNT           0x000D004C /* Reset: POR */
 #define I40E_PDOC_ECC_UNCOR_ERR_CNT_CNT_SHIFT 0
 #define I40E_PDOC_ECC_UNCOR_ERR_CNT_CNT_MASK  I40E_MASK(0xFFF, I40E_PDOC_ECC_UNCOR_ERR_CNT_CNT_SHIFT)
 
-#define I40E_PDOC_FILL_MEM_CFG                    0x000D003C
+#define I40E_PDOC_FILL_MEM_CFG                    0x000D003C /* Reset: POR */
 #define I40E_PDOC_FILL_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PDOC_FILL_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PDOC_FILL_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PDOC_FILL_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -4213,7 +4309,7 @@
 #define I40E_PDOC_FILL_MEM_CFG_RM_SHIFT           16
 #define I40E_PDOC_FILL_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PDOC_FILL_MEM_CFG_RM_SHIFT)
 
-#define I40E_PDOC_FILL_MEM_STATUS                        0x000D0040
+#define I40E_PDOC_FILL_MEM_STATUS                        0x000D0040 /* Reset: POR */
 #define I40E_PDOC_FILL_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PDOC_FILL_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PDOC_FILL_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PDOC_FILL_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -4223,7 +4319,7 @@
 #define I40E_PDOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PDOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PDOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PDOC_PLIST_DBG_CTL              0x000D0064
+#define I40E_PDOC_PLIST_DBG_CTL              0x000D0064 /* Reset: CORER */
 #define I40E_PDOC_PLIST_DBG_CTL_ADR_SHIFT    0
 #define I40E_PDOC_PLIST_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_PDOC_PLIST_DBG_CTL_ADR_SHIFT)
 #define I40E_PDOC_PLIST_DBG_CTL_DW_SEL_SHIFT 18
@@ -4233,11 +4329,11 @@
 #define I40E_PDOC_PLIST_DBG_CTL_DONE_SHIFT   31
 #define I40E_PDOC_PLIST_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_PDOC_PLIST_DBG_CTL_DONE_SHIFT)
 
-#define I40E_PDOC_PLIST_DBG_DATA             0x000D0068
+#define I40E_PDOC_PLIST_DBG_DATA             0x000D0068 /* Reset: CORER */
 #define I40E_PDOC_PLIST_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_PDOC_PLIST_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_PDOC_PLIST_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_PDOC_PLIST_MEM_CFG                    0x000D0044
+#define I40E_PDOC_PLIST_MEM_CFG                    0x000D0044 /* Reset: POR */
 #define I40E_PDOC_PLIST_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PDOC_PLIST_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PDOC_PLIST_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PDOC_PLIST_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -4259,7 +4355,7 @@
 #define I40E_PDOC_PLIST_MEM_CFG_RM_SHIFT           16
 #define I40E_PDOC_PLIST_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PDOC_PLIST_MEM_CFG_RM_SHIFT)
 
-#define I40E_PDOC_PLIST_MEM_STATUS                        0x000D0048
+#define I40E_PDOC_PLIST_MEM_STATUS                        0x000D0048 /* Reset: POR */
 #define I40E_PDOC_PLIST_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PDOC_PLIST_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PDOC_PLIST_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PDOC_PLIST_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -4269,7 +4365,7 @@
 #define I40E_PDOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PDOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PDOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PDOC_TAG_DBG_CTL              0x000D0054
+#define I40E_PDOC_TAG_DBG_CTL              0x000D0054 /* Reset: CORER */
 #define I40E_PDOC_TAG_DBG_CTL_ADR_SHIFT    0
 #define I40E_PDOC_TAG_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_PDOC_TAG_DBG_CTL_ADR_SHIFT)
 #define I40E_PDOC_TAG_DBG_CTL_DW_SEL_SHIFT 18
@@ -4279,11 +4375,11 @@
 #define I40E_PDOC_TAG_DBG_CTL_DONE_SHIFT   31
 #define I40E_PDOC_TAG_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_PDOC_TAG_DBG_CTL_DONE_SHIFT)
 
-#define I40E_PDOC_TAG_DBG_DATA             0x000D0058
+#define I40E_PDOC_TAG_DBG_DATA             0x000D0058 /* Reset: CORER */
 #define I40E_PDOC_TAG_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_PDOC_TAG_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_PDOC_TAG_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_PDOC_TAG_MEM_CFG                    0x000D0038
+#define I40E_PDOC_TAG_MEM_CFG                    0x000D0038 /* Reset: POR */
 #define I40E_PDOC_TAG_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PDOC_TAG_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PDOC_TAG_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PDOC_TAG_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -4305,7 +4401,7 @@
 #define I40E_PDOC_TAG_MEM_CFG_RM_SHIFT           16
 #define I40E_PDOC_TAG_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PDOC_TAG_MEM_CFG_RM_SHIFT)
 
-#define I40E_PDOC_TAG_MEM_STATUS                        0x000D0034
+#define I40E_PDOC_TAG_MEM_STATUS                        0x000D0034 /* Reset: POR */
 #define I40E_PDOC_TAG_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PDOC_TAG_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PDOC_TAG_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PDOC_TAG_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -4315,7 +4411,7 @@
 #define I40E_PDOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PDOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PDOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PKT_INDICATIONS(_i)              (0x000AC920 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_PKT_INDICATIONS(_i)              (0x000AC920 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PKT_INDICATIONS_MAX_INDEX        7
 #define I40E_PKT_INDICATIONS_START_CNT_SHIFT  0
 #define I40E_PKT_INDICATIONS_START_CNT_MASK   I40E_MASK(0xFF, I40E_PKT_INDICATIONS_START_CNT_SHIFT)
@@ -4326,15 +4422,15 @@
 #define I40E_PKT_INDICATIONS_DROP_CNT_SHIFT   24
 #define I40E_PKT_INDICATIONS_DROP_CNT_MASK    I40E_MASK(0xFF, I40E_PKT_INDICATIONS_DROP_CNT_SHIFT)
 
-#define I40E_PMAT_ECC_COR_ERR           0x000C20CC
+#define I40E_PMAT_ECC_COR_ERR           0x000C20CC /* Reset: POR */
 #define I40E_PMAT_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_PMAT_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_PMAT_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_PMAT_ECC_UNCOR_ERR_CNT           0x000C20C8
+#define I40E_PMAT_ECC_UNCOR_ERR_CNT           0x000C20C8 /* Reset: POR */
 #define I40E_PMAT_ECC_UNCOR_ERR_CNT_CNT_SHIFT 0
 #define I40E_PMAT_ECC_UNCOR_ERR_CNT_CNT_MASK  I40E_MASK(0xFFF, I40E_PMAT_ECC_UNCOR_ERR_CNT_CNT_SHIFT)
 
-#define I40E_PMAT_OBJ_BASE_RAM_CFG                    0x000C20B8
+#define I40E_PMAT_OBJ_BASE_RAM_CFG                    0x000C20B8 /* Reset: POR */
 #define I40E_PMAT_OBJ_BASE_RAM_CFG_ECC_EN_SHIFT       0
 #define I40E_PMAT_OBJ_BASE_RAM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PMAT_OBJ_BASE_RAM_CFG_ECC_EN_SHIFT)
 #define I40E_PMAT_OBJ_BASE_RAM_CFG_ECC_INVERT_1_SHIFT 1
@@ -4356,7 +4452,7 @@
 #define I40E_PMAT_OBJ_BASE_RAM_CFG_RM_SHIFT           16
 #define I40E_PMAT_OBJ_BASE_RAM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PMAT_OBJ_BASE_RAM_CFG_RM_SHIFT)
 
-#define I40E_PMAT_OBJ_BASE_RAM_STATUS                        0x000C20BC
+#define I40E_PMAT_OBJ_BASE_RAM_STATUS                        0x000C20BC /* Reset: POR */
 #define I40E_PMAT_OBJ_BASE_RAM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PMAT_OBJ_BASE_RAM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PMAT_OBJ_BASE_RAM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PMAT_OBJ_BASE_RAM_STATUS_ECC_FIX_SHIFT          1
@@ -4366,7 +4462,7 @@
 #define I40E_PMAT_OBJ_BASE_RAM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PMAT_OBJ_BASE_RAM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PMAT_OBJ_BASE_RAM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PMAT_OBJ_BNDS_RAM_CFG                    0x000C20C0
+#define I40E_PMAT_OBJ_BNDS_RAM_CFG                    0x000C20C0 /* Reset: POR */
 #define I40E_PMAT_OBJ_BNDS_RAM_CFG_ECC_EN_SHIFT       0
 #define I40E_PMAT_OBJ_BNDS_RAM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PMAT_OBJ_BNDS_RAM_CFG_ECC_EN_SHIFT)
 #define I40E_PMAT_OBJ_BNDS_RAM_CFG_ECC_INVERT_1_SHIFT 1
@@ -4388,7 +4484,7 @@
 #define I40E_PMAT_OBJ_BNDS_RAM_CFG_RM_SHIFT           16
 #define I40E_PMAT_OBJ_BNDS_RAM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PMAT_OBJ_BNDS_RAM_CFG_RM_SHIFT)
 
-#define I40E_PMAT_OBJ_BNDS_RAM_STATUS                        0x000C20C4
+#define I40E_PMAT_OBJ_BNDS_RAM_STATUS                        0x000C20C4 /* Reset: POR */
 #define I40E_PMAT_OBJ_BNDS_RAM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PMAT_OBJ_BNDS_RAM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PMAT_OBJ_BNDS_RAM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PMAT_OBJ_BNDS_RAM_STATUS_ECC_FIX_SHIFT          1
@@ -4398,7 +4494,7 @@
 #define I40E_PMAT_OBJ_BNDS_RAM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PMAT_OBJ_BNDS_RAM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PMAT_OBJ_BNDS_RAM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PMAT_ST_RAM_CFG                    0x000C20B0
+#define I40E_PMAT_ST_RAM_CFG                    0x000C20B0 /* Reset: POR */
 #define I40E_PMAT_ST_RAM_CFG_ECC_EN_SHIFT       0
 #define I40E_PMAT_ST_RAM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PMAT_ST_RAM_CFG_ECC_EN_SHIFT)
 #define I40E_PMAT_ST_RAM_CFG_ECC_INVERT_1_SHIFT 1
@@ -4420,7 +4516,7 @@
 #define I40E_PMAT_ST_RAM_CFG_RM_SHIFT           16
 #define I40E_PMAT_ST_RAM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PMAT_ST_RAM_CFG_RM_SHIFT)
 
-#define I40E_PMAT_ST_RAM_STATUS                        0x000C20B4
+#define I40E_PMAT_ST_RAM_STATUS                        0x000C20B4 /* Reset: POR */
 #define I40E_PMAT_ST_RAM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PMAT_ST_RAM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PMAT_ST_RAM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PMAT_ST_RAM_STATUS_ECC_FIX_SHIFT          1
@@ -4430,7 +4526,7 @@
 #define I40E_PMAT_ST_RAM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PMAT_ST_RAM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PMAT_ST_RAM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PORT_CMD_BUF_MEM_CFG                    0x000AE094
+#define I40E_PORT_CMD_BUF_MEM_CFG                    0x000AE094 /* Reset: POR */
 #define I40E_PORT_CMD_BUF_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PORT_CMD_BUF_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PORT_CMD_BUF_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PORT_CMD_BUF_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -4452,7 +4548,7 @@
 #define I40E_PORT_CMD_BUF_MEM_CFG_RM_SHIFT           16
 #define I40E_PORT_CMD_BUF_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PORT_CMD_BUF_MEM_CFG_RM_SHIFT)
 
-#define I40E_PORT_CMD_BUF_MEM_STATUS                        0x000AE098
+#define I40E_PORT_CMD_BUF_MEM_STATUS                        0x000AE098 /* Reset: POR */
 #define I40E_PORT_CMD_BUF_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PORT_CMD_BUF_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PORT_CMD_BUF_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PORT_CMD_BUF_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -4462,7 +4558,7 @@
 #define I40E_PORT_CMD_BUF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PORT_CMD_BUF_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PORT_CMD_BUF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PORT_CMD_MNG_MEM_CFG                    0x000AE09C
+#define I40E_PORT_CMD_MNG_MEM_CFG                    0x000AE09C /* Reset: POR */
 #define I40E_PORT_CMD_MNG_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_PORT_CMD_MNG_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PORT_CMD_MNG_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_PORT_CMD_MNG_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -4484,7 +4580,7 @@
 #define I40E_PORT_CMD_MNG_MEM_CFG_RM_SHIFT           16
 #define I40E_PORT_CMD_MNG_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_PORT_CMD_MNG_MEM_CFG_RM_SHIFT)
 
-#define I40E_PORT_CMD_MNG_MEM_STATUS                        0x000AE0A0
+#define I40E_PORT_CMD_MNG_MEM_STATUS                        0x000AE0A0 /* Reset: POR */
 #define I40E_PORT_CMD_MNG_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PORT_CMD_MNG_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PORT_CMD_MNG_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_PORT_CMD_MNG_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -4494,15 +4590,15 @@
 #define I40E_PORT_CMD_MNG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PORT_CMD_MNG_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PORT_CMD_MNG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PPRS_ECC_COR_ERR           0x00085BA0
+#define I40E_PPRS_ECC_COR_ERR           0x00085BA0 /* Reset: POR */
 #define I40E_PPRS_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_PPRS_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_PPRS_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_PPRS_ECC_UNCOR_ERR           0x00085B80
+#define I40E_PPRS_ECC_UNCOR_ERR           0x00085B80 /* Reset: POR */
 #define I40E_PPRS_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_PPRS_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_PPRS_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_PPRS_PCKT_CFG                    0x00085B00
+#define I40E_PPRS_PCKT_CFG                    0x00085B00 /* Reset: POR */
 #define I40E_PPRS_PCKT_CFG_ECC_EN_SHIFT       0
 #define I40E_PPRS_PCKT_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PPRS_PCKT_CFG_ECC_EN_SHIFT)
 #define I40E_PPRS_PCKT_CFG_ECC_INVERT_1_SHIFT 1
@@ -4524,7 +4620,7 @@
 #define I40E_PPRS_PCKT_CFG_RM_SHIFT           16
 #define I40E_PPRS_PCKT_CFG_RM_MASK            I40E_MASK(0xF, I40E_PPRS_PCKT_CFG_RM_SHIFT)
 
-#define I40E_PPRS_PCKT_STATUS                        0x00085B20
+#define I40E_PPRS_PCKT_STATUS                        0x00085B20 /* Reset: POR */
 #define I40E_PPRS_PCKT_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PPRS_PCKT_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PPRS_PCKT_STATUS_ECC_ERR_SHIFT)
 #define I40E_PPRS_PCKT_STATUS_ECC_FIX_SHIFT          1
@@ -4534,7 +4630,7 @@
 #define I40E_PPRS_PCKT_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PPRS_PCKT_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PPRS_PCKT_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PPRS_RECIPE_CFG                    0x00085B40
+#define I40E_PPRS_RECIPE_CFG                    0x00085B40 /* Reset: POR */
 #define I40E_PPRS_RECIPE_CFG_ECC_EN_SHIFT       0
 #define I40E_PPRS_RECIPE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_PPRS_RECIPE_CFG_ECC_EN_SHIFT)
 #define I40E_PPRS_RECIPE_CFG_ECC_INVERT_1_SHIFT 1
@@ -4556,7 +4652,7 @@
 #define I40E_PPRS_RECIPE_CFG_RM_SHIFT           16
 #define I40E_PPRS_RECIPE_CFG_RM_MASK            I40E_MASK(0xF, I40E_PPRS_RECIPE_CFG_RM_SHIFT)
 
-#define I40E_PPRS_RECIPE_STATUS                        0x00085B60
+#define I40E_PPRS_RECIPE_STATUS                        0x00085B60 /* Reset: POR */
 #define I40E_PPRS_RECIPE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_PPRS_RECIPE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PPRS_RECIPE_STATUS_ECC_ERR_SHIFT)
 #define I40E_PPRS_RECIPE_STATUS_ECC_FIX_SHIFT          1
@@ -4566,7 +4662,7 @@
 #define I40E_PPRS_RECIPE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_PPRS_RECIPE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_PPRS_RECIPE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_PRT_PPRS_CTRL                     0x00086000
+#define I40E_PRT_PPRS_CTRL                     0x00086000 /* Reset: CORER */
 #define I40E_PRT_PPRS_CTRL_HDR_VLD_SEL_SHIFT   0
 #define I40E_PRT_PPRS_CTRL_HDR_VLD_SEL_MASK    I40E_MASK(0x3, I40E_PRT_PPRS_CTRL_HDR_VLD_SEL_SHIFT)
 #define I40E_PRT_PPRS_CTRL_STOP_ANA_DIS_SHIFT  2
@@ -4578,43 +4674,47 @@
 #define I40E_PRT_PPRS_CTRL_SPARE_27B_SHIFT     5
 #define I40E_PRT_PPRS_CTRL_SPARE_27B_MASK      I40E_MASK(0x7FFFFFF, I40E_PRT_PPRS_CTRL_SPARE_27B_SHIFT)
 
-#define I40E_PRT_PPRS_DEFUALT_RECIPE_PTR                          0x00086040
+#define I40E_PRT_PPRS_DEFUALT_RECIPE_PTR                          0x00086040 /* Reset: CORER */
 #define I40E_PRT_PPRS_DEFUALT_RECIPE_PTR_DEFUALT_RECIPE_PTR_SHIFT 0
 #define I40E_PRT_PPRS_DEFUALT_RECIPE_PTR_DEFUALT_RECIPE_PTR_MASK  I40E_MASK(0x3FFFFF, I40E_PRT_PPRS_DEFUALT_RECIPE_PTR_DEFUALT_RECIPE_PTR_SHIFT)
 
-#define I40E_PRT_PPRS_DONE_CNT                    0x00087020
+#define I40E_PRT_PPRS_DONE_CNT                    0x00087020 /* Reset: CORER */
 #define I40E_PRT_PPRS_DONE_CNT_LY3_DONE_CNT_SHIFT 0
 #define I40E_PRT_PPRS_DONE_CNT_LY3_DONE_CNT_MASK  I40E_MASK(0xFFFF, I40E_PRT_PPRS_DONE_CNT_LY3_DONE_CNT_SHIFT)
 #define I40E_PRT_PPRS_DONE_CNT_LY2_DONE_CNT_SHIFT 16
 #define I40E_PRT_PPRS_DONE_CNT_LY2_DONE_CNT_MASK  I40E_MASK(0xFFFF, I40E_PRT_PPRS_DONE_CNT_LY2_DONE_CNT_SHIFT)
 
-#define I40E_PRT_PPRS_DROP_CNT                         0x00087000
+#define I40E_PRT_PPRS_DROP_CNT                         0x00087000 /* Reset: CORER */
 #define I40E_PRT_PPRS_DROP_CNT_PRT_PPRS_DROP_CNT_SHIFT 0
 #define I40E_PRT_PPRS_DROP_CNT_PRT_PPRS_DROP_CNT_MASK  I40E_MASK(0xFFFF, I40E_PRT_PPRS_DROP_CNT_PRT_PPRS_DROP_CNT_SHIFT)
 
-#define I40E_PRT_PPRS_HDR_VLD_PCTYPE_EN                         0x00086060
+#define I40E_PRT_PPRS_HDR_VLD_PCTYPE_EN                         0x00086060 /* Reset: CORER */
 #define I40E_PRT_PPRS_HDR_VLD_PCTYPE_EN_HDR_VLD_PCTYPE_EN_SHIFT 0
 #define I40E_PRT_PPRS_HDR_VLD_PCTYPE_EN_HDR_VLD_PCTYPE_EN_MASK  I40E_MASK(0xFFFF, I40E_PRT_PPRS_HDR_VLD_PCTYPE_EN_HDR_VLD_PCTYPE_EN_SHIFT)
 
-#define I40E_PRT_PPRS_NOT_PARSE_CNT                    0x00087040
+#define I40E_PRT_PPRS_NOT_PARSE_CNT                    0x00087040 /* Reset: CORER */
 #define I40E_PRT_PPRS_NOT_PARSE_CNT_STOP_ANA_CNT_SHIFT 0
 #define I40E_PRT_PPRS_NOT_PARSE_CNT_STOP_ANA_CNT_MASK  I40E_MASK(0xFFFF, I40E_PRT_PPRS_NOT_PARSE_CNT_STOP_ANA_CNT_SHIFT)
 #define I40E_PRT_PPRS_NOT_PARSE_CNT_ABORT_CNT_SHIFT    16
 #define I40E_PRT_PPRS_NOT_PARSE_CNT_ABORT_CNT_MASK     I40E_MASK(0xFFFF, I40E_PRT_PPRS_NOT_PARSE_CNT_ABORT_CNT_SHIFT)
 
-#define I40E_PRT_PPRS_PERF_BUF                 0x00086020
+#define I40E_PRT_PPRS_PERF_BUF                 0x00086020 /* Reset: CORER */
 #define I40E_PRT_PPRS_PERF_BUF_HI_TRESH_SHIFT  0
 #define I40E_PRT_PPRS_PERF_BUF_HI_TRESH_MASK   I40E_MASK(0x3F, I40E_PRT_PPRS_PERF_BUF_HI_TRESH_SHIFT)
 #define I40E_PRT_PPRS_PERF_BUF_LOW_TRESH_SHIFT 16
 #define I40E_PRT_PPRS_PERF_BUF_LOW_TRESH_MASK  I40E_MASK(0x3F, I40E_PRT_PPRS_PERF_BUF_LOW_TRESH_SHIFT)
 
-#define I40E_PRT_PPRS_PKTS_CNT                  0x00087060
+#define I40E_PRT_PPRS_PKTS_CNT                  0x00087060 /* Reset: CORER */
 #define I40E_PRT_PPRS_PKTS_CNT_RPB_IF_CNT_SHIFT 0
 #define I40E_PRT_PPRS_PKTS_CNT_RPB_IF_CNT_MASK  I40E_MASK(0xFFFF, I40E_PRT_PPRS_PKTS_CNT_RPB_IF_CNT_SHIFT)
 #define I40E_PRT_PPRS_PKTS_CNT_MAC_IF_CNT_SHIFT 16
 #define I40E_PRT_PPRS_PKTS_CNT_MAC_IF_CNT_MASK  I40E_MASK(0xFFFF, I40E_PRT_PPRS_PKTS_CNT_MAC_IF_CNT_SHIFT)
 
-#define I40E_RCB_CHUNK_DATA_CFG                    0x00122644
+#define I40E_PRT_SWR_PM_THR                 0x0026CD00 /* Reset: CORER */
+#define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0
+#define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK  I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT)
+
+#define I40E_RCB_CHUNK_DATA_CFG                    0x00122644 /* Reset: POR */
 #define I40E_RCB_CHUNK_DATA_CFG_ECC_EN_SHIFT       0
 #define I40E_RCB_CHUNK_DATA_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCB_CHUNK_DATA_CFG_ECC_EN_SHIFT)
 #define I40E_RCB_CHUNK_DATA_CFG_ECC_INVERT_1_SHIFT 1
@@ -4636,7 +4736,7 @@
 #define I40E_RCB_CHUNK_DATA_CFG_RM_SHIFT           16
 #define I40E_RCB_CHUNK_DATA_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCB_CHUNK_DATA_CFG_RM_SHIFT)
 
-#define I40E_RCB_CHUNK_DATA_STATUS                        0x00122648
+#define I40E_RCB_CHUNK_DATA_STATUS                        0x00122648 /* Reset: POR */
 #define I40E_RCB_CHUNK_DATA_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCB_CHUNK_DATA_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCB_CHUNK_DATA_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCB_CHUNK_DATA_STATUS_ECC_FIX_SHIFT          1
@@ -4646,15 +4746,15 @@
 #define I40E_RCB_CHUNK_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCB_CHUNK_DATA_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCB_CHUNK_DATA_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCB_ECC_COR_ERR           0x00122668
+#define I40E_RCB_ECC_COR_ERR           0x00122668 /* Reset: POR */
 #define I40E_RCB_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_RCB_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RCB_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_RCB_ECC_UNCOR_ERR           0x00122664
+#define I40E_RCB_ECC_UNCOR_ERR           0x00122664 /* Reset: POR */
 #define I40E_RCB_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_RCB_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RCB_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_RCB_HEAD_CACHE_CFG                    0x0012264C
+#define I40E_RCB_HEAD_CACHE_CFG                    0x0012264C /* Reset: POR */
 #define I40E_RCB_HEAD_CACHE_CFG_ECC_EN_SHIFT       0
 #define I40E_RCB_HEAD_CACHE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCB_HEAD_CACHE_CFG_ECC_EN_SHIFT)
 #define I40E_RCB_HEAD_CACHE_CFG_ECC_INVERT_1_SHIFT 1
@@ -4676,7 +4776,7 @@
 #define I40E_RCB_HEAD_CACHE_CFG_RM_SHIFT           16
 #define I40E_RCB_HEAD_CACHE_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCB_HEAD_CACHE_CFG_RM_SHIFT)
 
-#define I40E_RCB_HEAD_CACHE_STATUS                        0x00122650
+#define I40E_RCB_HEAD_CACHE_STATUS                        0x00122650 /* Reset: POR */
 #define I40E_RCB_HEAD_CACHE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCB_HEAD_CACHE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCB_HEAD_CACHE_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCB_HEAD_CACHE_STATUS_ECC_FIX_SHIFT          1
@@ -4686,7 +4786,7 @@
 #define I40E_RCB_HEAD_CACHE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCB_HEAD_CACHE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCB_HEAD_CACHE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCB_INPUT_FIFO_CFG                    0x0012265C
+#define I40E_RCB_INPUT_FIFO_CFG                    0x0012265C /* Reset: POR */
 #define I40E_RCB_INPUT_FIFO_CFG_ECC_EN_SHIFT       0
 #define I40E_RCB_INPUT_FIFO_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCB_INPUT_FIFO_CFG_ECC_EN_SHIFT)
 #define I40E_RCB_INPUT_FIFO_CFG_ECC_INVERT_1_SHIFT 1
@@ -4708,7 +4808,7 @@
 #define I40E_RCB_INPUT_FIFO_CFG_RM_SHIFT           16
 #define I40E_RCB_INPUT_FIFO_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCB_INPUT_FIFO_CFG_RM_SHIFT)
 
-#define I40E_RCB_INPUT_FIFO_STATUS                        0x00122660
+#define I40E_RCB_INPUT_FIFO_STATUS                        0x00122660 /* Reset: POR */
 #define I40E_RCB_INPUT_FIFO_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCB_INPUT_FIFO_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCB_INPUT_FIFO_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCB_INPUT_FIFO_STATUS_ECC_FIX_SHIFT          1
@@ -4718,7 +4818,7 @@
 #define I40E_RCB_INPUT_FIFO_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCB_INPUT_FIFO_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCB_INPUT_FIFO_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCB_LL_CFG                    0x00122654
+#define I40E_RCB_LL_CFG                    0x00122654 /* Reset: POR */
 #define I40E_RCB_LL_CFG_ECC_EN_SHIFT       0
 #define I40E_RCB_LL_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCB_LL_CFG_ECC_EN_SHIFT)
 #define I40E_RCB_LL_CFG_ECC_INVERT_1_SHIFT 1
@@ -4740,7 +4840,7 @@
 #define I40E_RCB_LL_CFG_RM_SHIFT           16
 #define I40E_RCB_LL_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCB_LL_CFG_RM_SHIFT)
 
-#define I40E_RCB_LL_STATUS                        0x00122658
+#define I40E_RCB_LL_STATUS                        0x00122658 /* Reset: POR */
 #define I40E_RCB_LL_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCB_LL_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCB_LL_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCB_LL_STATUS_ECC_FIX_SHIFT          1
@@ -4750,7 +4850,7 @@
 #define I40E_RCB_LL_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCB_LL_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCB_LL_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_DP_MTG_MFIFO_CFG                    0x00269B34
+#define I40E_RCU_DP_MTG_MFIFO_CFG                    0x00269B34 /* Reset: POR */
 #define I40E_RCU_DP_MTG_MFIFO_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_DP_MTG_MFIFO_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_DP_MTG_MFIFO_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_DP_MTG_MFIFO_CFG_ECC_INVERT_1_SHIFT 1
@@ -4772,7 +4872,7 @@
 #define I40E_RCU_DP_MTG_MFIFO_CFG_RM_SHIFT           16
 #define I40E_RCU_DP_MTG_MFIFO_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_DP_MTG_MFIFO_CFG_RM_SHIFT)
 
-#define I40E_RCU_DP_MTG_MFIFO_STATUS                        0x00269B3C
+#define I40E_RCU_DP_MTG_MFIFO_STATUS                        0x00269B3C /* Reset: POR */
 #define I40E_RCU_DP_MTG_MFIFO_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_DP_MTG_MFIFO_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_DP_MTG_MFIFO_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_DP_MTG_MFIFO_STATUS_ECC_FIX_SHIFT          1
@@ -4782,7 +4882,7 @@
 #define I40E_RCU_DP_MTG_MFIFO_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_DP_MTG_MFIFO_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_DP_MTG_MFIFO_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_DP_SWR_REP_MFIFO_CFG                    0x00269B44
+#define I40E_RCU_DP_SWR_REP_MFIFO_CFG                    0x00269B44 /* Reset: POR */
 #define I40E_RCU_DP_SWR_REP_MFIFO_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_DP_SWR_REP_MFIFO_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_DP_SWR_REP_MFIFO_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_DP_SWR_REP_MFIFO_CFG_ECC_INVERT_1_SHIFT 1
@@ -4804,7 +4904,7 @@
 #define I40E_RCU_DP_SWR_REP_MFIFO_CFG_RM_SHIFT           16
 #define I40E_RCU_DP_SWR_REP_MFIFO_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_DP_SWR_REP_MFIFO_CFG_RM_SHIFT)
 
-#define I40E_RCU_DP_SWR_REP_MFIFO_STATUS                        0x00269B4C
+#define I40E_RCU_DP_SWR_REP_MFIFO_STATUS                        0x00269B4C /* Reset: POR */
 #define I40E_RCU_DP_SWR_REP_MFIFO_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_DP_SWR_REP_MFIFO_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_DP_SWR_REP_MFIFO_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_DP_SWR_REP_MFIFO_STATUS_ECC_FIX_SHIFT          1
@@ -4814,7 +4914,7 @@
 #define I40E_RCU_DP_SWR_REP_MFIFO_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_DP_SWR_REP_MFIFO_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_DP_SWR_REP_MFIFO_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_DP_SWR_UP_STATUS_CFG                    0x00269AFC
+#define I40E_RCU_DP_SWR_UP_STATUS_CFG                    0x00269AFC /* Reset: POR */
 #define I40E_RCU_DP_SWR_UP_STATUS_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_DP_SWR_UP_STATUS_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_DP_SWR_UP_STATUS_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_DP_SWR_UP_STATUS_CFG_ECC_INVERT_1_SHIFT 1
@@ -4836,7 +4936,7 @@
 #define I40E_RCU_DP_SWR_UP_STATUS_CFG_RM_SHIFT           16
 #define I40E_RCU_DP_SWR_UP_STATUS_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_DP_SWR_UP_STATUS_CFG_RM_SHIFT)
 
-#define I40E_RCU_DP_SWR_UP_STATUS_STATUS                        0x00269B0C
+#define I40E_RCU_DP_SWR_UP_STATUS_STATUS                        0x00269B0C /* Reset: POR */
 #define I40E_RCU_DP_SWR_UP_STATUS_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_DP_SWR_UP_STATUS_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_DP_SWR_UP_STATUS_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_DP_SWR_UP_STATUS_STATUS_ECC_FIX_SHIFT          1
@@ -4846,7 +4946,7 @@
 #define I40E_RCU_DP_SWR_UP_STATUS_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_DP_SWR_UP_STATUS_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_DP_SWR_UP_STATUS_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_DP_TFIFO_CFG                    0x0026CBD4
+#define I40E_RCU_DP_TFIFO_CFG                    0x0026CBD4 /* Reset: POR */
 #define I40E_RCU_DP_TFIFO_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_DP_TFIFO_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_DP_TFIFO_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_DP_TFIFO_CFG_ECC_INVERT_1_SHIFT 1
@@ -4868,7 +4968,7 @@
 #define I40E_RCU_DP_TFIFO_CFG_RM_SHIFT           16
 #define I40E_RCU_DP_TFIFO_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_DP_TFIFO_CFG_RM_SHIFT)
 
-#define I40E_RCU_DP_TFIFO_STATUS                        0x0026CBE4
+#define I40E_RCU_DP_TFIFO_STATUS                        0x0026CBE4 /* Reset: POR */
 #define I40E_RCU_DP_TFIFO_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_DP_TFIFO_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_DP_TFIFO_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_DP_TFIFO_STATUS_ECC_FIX_SHIFT          1
@@ -4878,7 +4978,7 @@
 #define I40E_RCU_DP_TFIFO_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_DP_TFIFO_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_DP_TFIFO_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_FCOE_PCTYPE_OVR_CTL                                     0x0026CC28
+#define I40E_RCU_FCOE_PCTYPE_OVR_CTL                                     0x0026CC28 /* Reset: CORER */
 #define I40E_RCU_FCOE_PCTYPE_OVR_CTL_OVERRIDE_METHOD_SHIFT               0
 #define I40E_RCU_FCOE_PCTYPE_OVR_CTL_OVERRIDE_METHOD_MASK                I40E_MASK(0xF, I40E_RCU_FCOE_PCTYPE_OVR_CTL_OVERRIDE_METHOD_SHIFT)
 #define I40E_RCU_FCOE_PCTYPE_OVR_CTL_ACTIVE_EXCHANGE_CONTEXT_IDX_SHIFT   4
@@ -4892,7 +4992,7 @@
 #define I40E_RCU_FCOE_PCTYPE_OVR_CTL_MANUAL_IDX_SHIFT                    20
 #define I40E_RCU_FCOE_PCTYPE_OVR_CTL_MANUAL_IDX_MASK                     I40E_MASK(0x7, I40E_RCU_FCOE_PCTYPE_OVR_CTL_MANUAL_IDX_SHIFT)
 
-#define I40E_RCU_FD_CNT_CFG                    0x0026CB04
+#define I40E_RCU_FD_CNT_CFG                    0x0026CB04 /* Reset: POR */
 #define I40E_RCU_FD_CNT_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_FD_CNT_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_FD_CNT_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_FD_CNT_CFG_ECC_INVERT_1_SHIFT 1
@@ -4914,7 +5014,7 @@
 #define I40E_RCU_FD_CNT_CFG_RM_SHIFT           16
 #define I40E_RCU_FD_CNT_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_FD_CNT_CFG_RM_SHIFT)
 
-#define I40E_RCU_FD_CNT_STATUS                        0x0026CB0C
+#define I40E_RCU_FD_CNT_STATUS                        0x0026CB0C /* Reset: POR */
 #define I40E_RCU_FD_CNT_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_FD_CNT_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_FD_CNT_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_FD_CNT_STATUS_ECC_FIX_SHIFT          1
@@ -4924,7 +5024,7 @@
 #define I40E_RCU_FD_CNT_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_FD_CNT_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_FD_CNT_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_FD_FLU_LUT_CFG                    0x0026CB14
+#define I40E_RCU_FD_FLU_LUT_CFG                    0x0026CB14 /* Reset: POR */
 #define I40E_RCU_FD_FLU_LUT_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_FD_FLU_LUT_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_FD_FLU_LUT_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_FD_FLU_LUT_CFG_ECC_INVERT_1_SHIFT 1
@@ -4946,7 +5046,7 @@
 #define I40E_RCU_FD_FLU_LUT_CFG_RM_SHIFT           16
 #define I40E_RCU_FD_FLU_LUT_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_FD_FLU_LUT_CFG_RM_SHIFT)
 
-#define I40E_RCU_FD_FLU_LUT_STATUS                        0x0026CB1C
+#define I40E_RCU_FD_FLU_LUT_STATUS                        0x0026CB1C /* Reset: POR */
 #define I40E_RCU_FD_FLU_LUT_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_FD_FLU_LUT_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_FD_FLU_LUT_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_FD_FLU_LUT_STATUS_ECC_FIX_SHIFT          1
@@ -4956,7 +5056,7 @@
 #define I40E_RCU_FD_FLU_LUT_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_FD_FLU_LUT_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_FD_FLU_LUT_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_FOC_TAILS_CFG                    0x00269ADC
+#define I40E_RCU_FOC_TAILS_CFG                    0x00269ADC /* Reset: POR */
 #define I40E_RCU_FOC_TAILS_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_FOC_TAILS_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_FOC_TAILS_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_FOC_TAILS_CFG_ECC_INVERT_1_SHIFT 1
@@ -4978,7 +5078,7 @@
 #define I40E_RCU_FOC_TAILS_CFG_RM_SHIFT           16
 #define I40E_RCU_FOC_TAILS_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_FOC_TAILS_CFG_RM_SHIFT)
 
-#define I40E_RCU_FOC_TAILS_STATUS                        0x00269B2C
+#define I40E_RCU_FOC_TAILS_STATUS                        0x00269B2C /* Reset: POR */
 #define I40E_RCU_FOC_TAILS_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_FOC_TAILS_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_FOC_TAILS_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_FOC_TAILS_STATUS_ECC_FIX_SHIFT          1
@@ -4988,15 +5088,264 @@
 #define I40E_RCU_FOC_TAILS_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_FOC_TAILS_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_FOC_TAILS_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_PST_ECC_COR_ERR           0x0026CBC4
+#define I40E_RCU_PST_DBG_CTL                           0x0026CC24 /* Reset: CORER */
+#define I40E_RCU_PST_DBG_CTL_IGNORE_FLR_SHIFT          0
+#define I40E_RCU_PST_DBG_CTL_IGNORE_FLR_MASK           I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_FLR_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_IGNORE_VFLR_SHIFT         1
+#define I40E_RCU_PST_DBG_CTL_IGNORE_VFLR_MASK          I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_VFLR_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_IGNORE_VMLR_SHIFT         2
+#define I40E_RCU_PST_DBG_CTL_IGNORE_VMLR_MASK          I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_VMLR_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_USE_PCTYPE_FCOE_SHIFT     3
+#define I40E_RCU_PST_DBG_CTL_USE_PCTYPE_FCOE_MASK      I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_USE_PCTYPE_FCOE_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_IGNORE_ETH_HIT_SHIFT      4
+#define I40E_RCU_PST_DBG_CTL_IGNORE_ETH_HIT_MASK       I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_ETH_HIT_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_IGNORE_MAC_VLAN_HIT_SHIFT 5
+#define I40E_RCU_PST_DBG_CTL_IGNORE_MAC_VLAN_HIT_MASK  I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_MAC_VLAN_HIT_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_IGNORE_SWR_DROP_SHIFT     6
+#define I40E_RCU_PST_DBG_CTL_IGNORE_SWR_DROP_MASK      I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_IGNORE_SWR_DROP_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_HOLD_FLU_JOBS_SHIFT       7
+#define I40E_RCU_PST_DBG_CTL_HOLD_FLU_JOBS_MASK        I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_HOLD_FLU_JOBS_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_FC_HASH_BASE_SHIFT        8
+#define I40E_RCU_PST_DBG_CTL_FC_HASH_BASE_MASK         I40E_MASK(0xF, I40E_RCU_PST_DBG_CTL_FC_HASH_BASE_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_PE_HASH_BASE_SHIFT        12
+#define I40E_RCU_PST_DBG_CTL_PE_HASH_BASE_MASK         I40E_MASK(0xF, I40E_RCU_PST_DBG_CTL_PE_HASH_BASE_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_FD_HASH_BASE_SHIFT        16
+#define I40E_RCU_PST_DBG_CTL_FD_HASH_BASE_MASK         I40E_MASK(0xF, I40E_RCU_PST_DBG_CTL_FD_HASH_BASE_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_FOC_CNTX_LIMIT_BASE_SHIFT 20
+#define I40E_RCU_PST_DBG_CTL_FOC_CNTX_LIMIT_BASE_MASK  I40E_MASK(0xF, I40E_RCU_PST_DBG_CTL_FOC_CNTX_LIMIT_BASE_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_ERR_COMP_DIS_SHIFT        24
+#define I40E_RCU_PST_DBG_CTL_ERR_COMP_DIS_MASK         I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_ERR_COMP_DIS_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_REM_COMP_DIS_SHIFT        25
+#define I40E_RCU_PST_DBG_CTL_REM_COMP_DIS_MASK         I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_REM_COMP_DIS_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_HOLD_PST_INPUT_SHIFT      28
+#define I40E_RCU_PST_DBG_CTL_HOLD_PST_INPUT_MASK       I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_HOLD_PST_INPUT_SHIFT)
+#define I40E_RCU_PST_DBG_CTL_INC_INPUT_CMD_SHIFT       29
+#define I40E_RCU_PST_DBG_CTL_INC_INPUT_CMD_MASK        I40E_MASK(0x1, I40E_RCU_PST_DBG_CTL_INC_INPUT_CMD_SHIFT)
+
+#define I40E_RCU_PST_DBG_DROP_CNT                         0x0026CBEC /* Reset: CORER */
+#define I40E_RCU_PST_DBG_DROP_CNT_FD_DROP_CNT_SHIFT       0
+#define I40E_RCU_PST_DBG_DROP_CNT_FD_DROP_CNT_MASK        I40E_MASK(0xFF, I40E_RCU_PST_DBG_DROP_CNT_FD_DROP_CNT_SHIFT)
+#define I40E_RCU_PST_DBG_DROP_CNT_FLR_DROP_CNT_SHIFT      8
+#define I40E_RCU_PST_DBG_DROP_CNT_FLR_DROP_CNT_MASK       I40E_MASK(0xFF, I40E_RCU_PST_DBG_DROP_CNT_FLR_DROP_CNT_SHIFT)
+#define I40E_RCU_PST_DBG_DROP_CNT_PF_BOUND_DROP_CNT_SHIFT 16
+#define I40E_RCU_PST_DBG_DROP_CNT_PF_BOUND_DROP_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_DBG_DROP_CNT_PF_BOUND_DROP_CNT_SHIFT)
+#define I40E_RCU_PST_DBG_DROP_CNT_SWR_DROP_CNT_SHIFT      24
+#define I40E_RCU_PST_DBG_DROP_CNT_SWR_DROP_CNT_MASK       I40E_MASK(0xFF, I40E_RCU_PST_DBG_DROP_CNT_SWR_DROP_CNT_SHIFT)
+
+#define I40E_RCU_PST_DBG_FLU_STATE(_i)             (0x0026CB80 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
+#define I40E_RCU_PST_DBG_FLU_STATE_MAX_INDEX       15
+#define I40E_RCU_PST_DBG_FLU_STATE_FLU_STATE_SHIFT 0
+#define I40E_RCU_PST_DBG_FLU_STATE_FLU_STATE_MASK  I40E_MASK(0x1F, I40E_RCU_PST_DBG_FLU_STATE_FLU_STATE_SHIFT)
+#define I40E_RCU_PST_DBG_FLU_STATE_FLU_HASH_SHIFT  5
+#define I40E_RCU_PST_DBG_FLU_STATE_FLU_HASH_MASK   I40E_MASK(0xFFFFF, I40E_RCU_PST_DBG_FLU_STATE_FLU_HASH_SHIFT)
+#define I40E_RCU_PST_DBG_FLU_STATE_FLU_OBJ_SHIFT   25
+#define I40E_RCU_PST_DBG_FLU_STATE_FLU_OBJ_MASK    I40E_MASK(0x7, I40E_RCU_PST_DBG_FLU_STATE_FLU_OBJ_SHIFT)
+#define I40E_RCU_PST_DBG_FLU_STATE_FLU_CMD_SHIFT   28
+#define I40E_RCU_PST_DBG_FLU_STATE_FLU_CMD_MASK    I40E_MASK(0xF, I40E_RCU_PST_DBG_FLU_STATE_FLU_CMD_SHIFT)
+
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_0                     0x0026CC14 /* Reset: CORER */
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_CONF_FAIL_CNT_SHIFT 0
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_CONF_FAIL_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_0_CONF_FAIL_CNT_SHIFT)
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_QUAD_HIT_CNT_SHIFT  8
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_QUAD_HIT_CNT_MASK   I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_0_QUAD_HIT_CNT_SHIFT)
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_ETH_HIT_CNT_SHIFT   16
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_ETH_HIT_CNT_MASK    I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_0_ETH_HIT_CNT_SHIFT)
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_FCOE_CNT_SHIFT      24
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_0_FCOE_CNT_MASK       I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_0_FCOE_CNT_SHIFT)
+
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_1                    0x0026CC1C /* Reset: CORER */
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_FD_HIT_CNT_SHIFT   0
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_FD_HIT_CNT_MASK    I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_1_FD_HIT_CNT_SHIFT)
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_MAC_VLAN_CNT_SHIFT 8
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_MAC_VLAN_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_1_MAC_VLAN_CNT_SHIFT)
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_RSS_CNT_SHIFT      16
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_RSS_CNT_MASK       I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_1_RSS_CNT_SHIFT)
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_DEFAULT_CNT_SHIFT  24
+#define I40E_RCU_PST_DBG_Q_SRC_CNT_1_DEFAULT_CNT_MASK   I40E_MASK(0xFF, I40E_RCU_PST_DBG_Q_SRC_CNT_1_DEFAULT_CNT_SHIFT)
+
+#define I40E_RCU_PST_DBG_STATUS_0                      0x0026CC04 /* Reset: CORER */
+#define I40E_RCU_PST_DBG_STATUS_0_PST_FLR_STAT_SHIFT   0
+#define I40E_RCU_PST_DBG_STATUS_0_PST_FLR_STAT_MASK    I40E_MASK(0xFFFF, I40E_RCU_PST_DBG_STATUS_0_PST_FLR_STAT_SHIFT)
+#define I40E_RCU_PST_DBG_STATUS_0_INPUT_FIFO_OCC_SHIFT 16
+#define I40E_RCU_PST_DBG_STATUS_0_INPUT_FIFO_OCC_MASK  I40E_MASK(0x3, I40E_RCU_PST_DBG_STATUS_0_INPUT_FIFO_OCC_SHIFT)
+
+#define I40E_RCU_PST_DBG_STATUS_1                      0x0026CC0C /* Reset: CORER */
+#define I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_START_SHIFT 0
+#define I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_START_MASK  I40E_MASK(0xFFFF, I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_START_SHIFT)
+#define I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_DONE_SHIFT  16
+#define I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_DONE_MASK   I40E_MASK(0xFFFF, I40E_RCU_PST_DBG_STATUS_1_FLR_FLOW_DONE_SHIFT)
+
+#define I40E_RCU_PST_ECC_COR_ERR           0x0026CBC4 /* Reset: POR */
 #define I40E_RCU_PST_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_RCU_PST_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RCU_PST_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_RCU_PST_ECC_UNCOR_ERR           0x0026CBCC
+#define I40E_RCU_PST_ECC_UNCOR_ERR           0x0026CBCC /* Reset: POR */
 #define I40E_RCU_PST_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_RCU_PST_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RCU_PST_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_RCU_PST_TFIFO_CFG                    0x00269B54
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN                          0x0026CC08 /* Reset: CORER */
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_FILTER_EN_SHIFT      0
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_FILTER_EN_MASK       I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_FILTER_EN_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_SOF2_CLASS_SHIFT     1
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_SOF2_CLASS_MASK      I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_SOF2_CLASS_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_SOF3_CLASS_SHIFT     2
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_SOF3_CLASS_MASK      I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_SOF3_CLASS_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_EOFA_EOFI_SHIFT      3
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_EOFA_EOFI_MASK       I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_EOFA_EOFI_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_FIRST_NO_SOFI_SHIFT  4
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_FIRST_NO_SOFI_MASK   I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_FIRST_NO_SOFI_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_MID_SOFI_SHIFT       5
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_MID_SOFI_MASK        I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_MID_SOFI_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_NOT_NEW_SEQ_ID_SHIFT 6
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_NOT_NEW_SEQ_ID_MASK  I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_NOT_NEW_SEQ_ID_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_NEW_SEQ_ID_SHIFT     7
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_NEW_SEQ_ID_MASK      I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_NEW_SEQ_ID_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_NEW_SEQ_CNT_SHIFT    8
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_NEW_SEQ_CNT_MASK     I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_NEW_SEQ_CNT_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_DIFF_SEQ_CNT_SHIFT   9
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_DIFF_SEQ_CNT_MASK    I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_GEN_DIFF_SEQ_CNT_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SOF_CLASS_SHIFT      11
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SOF_CLASS_MASK       I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SOF_CLASS_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_INITIATOR_SHIFT      12
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_INITIATOR_MASK       I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_INITIATOR_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_LAST_PKT_SHIFT       13
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_LAST_PKT_MASK        I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_LAST_PKT_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_EOFT_SHIFT           14
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_EOFT_MASK            I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_EOFT_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SEQ_ID_SHIFT         15
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SEQ_ID_MASK          I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SEQ_ID_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_EX_CNTX_SHIFT        16
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_EX_CNTX_MASK         I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_EX_CNTX_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SEQ_CNTX_SHIFT       17
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SEQ_CNTX_MASK        I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SEQ_CNTX_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SEQ_INITIATIVE_SHIFT 18
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SEQ_INITIATIVE_MASK  I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_SEQ_INITIATIVE_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_RLT_OFFSET_SHIFT     19
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_RLT_OFFSET_MASK      I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_RLT_OFFSET_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_FIRST_SEQ_SHIFT      20
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_FIRST_SEQ_MASK       I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_FIRST_SEQ_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_ABORT_SEQ_SHIFT      21
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_ABORT_SEQ_MASK       I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_ABORT_SEQ_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_LAST_SEQ_SHIFT       22
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_LAST_SEQ_MASK        I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_RSP_LAST_SEQ_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_NEW_SEQ_ID_SHIFT    23
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_NEW_SEQ_ID_MASK     I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_NEW_SEQ_ID_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_DIFF_SEQ_ID_SHIFT   24
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_DIFF_SEQ_ID_MASK    I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_DIFF_SEQ_ID_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_EOFT_SHIFT          25
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_EOFT_MASK           I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_EOFT_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_EOFN_SHIFT          26
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_EOFN_MASK           I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_EOFN_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_EX_CNTX_SHIFT       27
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_EX_CNTX_MASK        I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_EX_CNTX_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_SEQ_CNTX_SHIFT      28
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_SEQ_CNTX_MASK       I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_SEQ_CNTX_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_PARAM_SHIFT         29
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_PARAM_MASK          I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_PARAM_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_FIRST_SEQ_SHIFT     30
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_FIRST_SEQ_MASK      I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_FIRST_SEQ_SHIFT)
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_ABORT_SEQ_SHIFT     31
+#define I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_ABORT_SEQ_MASK      I40E_MASK(0x1, I40E_RCU_PST_FCOE_CNTX_CHK_EN_DATA_ABORT_SEQ_SHIFT)
+
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN                          0x0026CC10 /* Reset: CORER */
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_FCOE_VER_SHIFT           0
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_FCOE_VER_MASK            I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_FCOE_VER_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_SOF_VALUE_SHIFT          1
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_SOF_VALUE_MASK           I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_SOF_VALUE_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_EOF_VALUE_SHIFT          2
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_EOF_VALUE_MASK           I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_EOF_VALUE_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_END_SEQ_EOFT_SHIFT       3
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_END_SEQ_EOFT_MASK        I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_END_SEQ_EOFT_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_NO_END_SEQ_NO_EOFT_SHIFT 4
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_NO_END_SEQ_NO_EOFT_MASK  I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_NO_END_SEQ_NO_EOFT_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_OBSOLETE_FLAGS_SHIFT     5
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_OBSOLETE_FLAGS_MASK      I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_OBSOLETE_FLAGS_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_NOT_FCP_SHIFT            6
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_NOT_FCP_MASK             I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_NOT_FCP_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_CRC_ERROR_SHIFT          7
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_CRC_ERROR_MASK           I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_CRC_ERROR_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_PKT_SIZE_SHIFT           8
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_PKT_SIZE_MASK            I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_PKT_SIZE_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_SEQ_INIT_LAST_SHIFT      9
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_SEQ_INIT_LAST_MASK       I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_SEQ_INIT_LAST_SHIFT)
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_OPTIONAL_HEADERS_SHIFT   10
+#define I40E_RCU_PST_FCOE_PROT_CHK_EN_OPTIONAL_HEADERS_MASK    I40E_MASK(0x1, I40E_RCU_PST_FCOE_PROT_CHK_EN_OPTIONAL_HEADERS_SHIFT)
+
+#define I40E_RCU_PST_FOC_ACCESS_STATUS                     0x00270110 /* Reset: CORER */
+#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT 0
+#define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT)
+#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT 8
+#define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_MASK  I40E_MASK(0xFF, I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT)
+#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT       16
+#define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_MASK        I40E_MASK(0xFF, I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT)
+#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT 24
+#define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_MASK  I40E_MASK(0x7, I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT)
+
+#define I40E_RCU_PST_INPUT_ACL_STATUS(_i)                            (0x00270100 + ((_i) * 4)) /* _i=0...2 */ /* Reset: CORER */
+#define I40E_RCU_PST_INPUT_ACL_STATUS_MAX_INDEX                      2
+#define I40E_RCU_PST_INPUT_ACL_STATUS_RCU_PST_INPUT_ACL_STATUS_SHIFT 0
+#define I40E_RCU_PST_INPUT_ACL_STATUS_RCU_PST_INPUT_ACL_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_INPUT_ACL_STATUS_RCU_PST_INPUT_ACL_STATUS_SHIFT)
+
+#define I40E_RCU_PST_INPUT_MTG_FIELDS(_i)                            (0x00270080 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
+#define I40E_RCU_PST_INPUT_MTG_FIELDS_MAX_INDEX                      31
+#define I40E_RCU_PST_INPUT_MTG_FIELDS_RCU_PST_INPUT_MTG_FIELDS_SHIFT 0
+#define I40E_RCU_PST_INPUT_MTG_FIELDS_RCU_PST_INPUT_MTG_FIELDS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_INPUT_MTG_FIELDS_RCU_PST_INPUT_MTG_FIELDS_SHIFT)
+
+#define I40E_RCU_PST_INPUT_MTG_STATUS(_i)                            (0x00270060 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
+#define I40E_RCU_PST_INPUT_MTG_STATUS_MAX_INDEX                      7
+#define I40E_RCU_PST_INPUT_MTG_STATUS_RCU_PST_INPUT_MTG_STATUS_SHIFT 0
+#define I40E_RCU_PST_INPUT_MTG_STATUS_RCU_PST_INPUT_MTG_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_INPUT_MTG_STATUS_RCU_PST_INPUT_MTG_STATUS_SHIFT)
+
+#define I40E_RCU_PST_OUTFIFO_OCC(_i)            (0x0026CFE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
+#define I40E_RCU_PST_OUTFIFO_OCC_MAX_INDEX      7
+#define I40E_RCU_PST_OUTFIFO_OCC_UP_1_OCC_SHIFT 0
+#define I40E_RCU_PST_OUTFIFO_OCC_UP_1_OCC_MASK  I40E_MASK(0xFF, I40E_RCU_PST_OUTFIFO_OCC_UP_1_OCC_SHIFT)
+#define I40E_RCU_PST_OUTFIFO_OCC_UP_2_OCC_SHIFT 8
+#define I40E_RCU_PST_OUTFIFO_OCC_UP_2_OCC_MASK  I40E_MASK(0xFF, I40E_RCU_PST_OUTFIFO_OCC_UP_2_OCC_SHIFT)
+#define I40E_RCU_PST_OUTFIFO_OCC_UP_3_OCC_SHIFT 16
+#define I40E_RCU_PST_OUTFIFO_OCC_UP_3_OCC_MASK  I40E_MASK(0xFF, I40E_RCU_PST_OUTFIFO_OCC_UP_3_OCC_SHIFT)
+#define I40E_RCU_PST_OUTFIFO_OCC_UP_4_OCC_SHIFT 24
+#define I40E_RCU_PST_OUTFIFO_OCC_UP_4_OCC_MASK  I40E_MASK(0xFF, I40E_RCU_PST_OUTFIFO_OCC_UP_4_OCC_SHIFT)
+
+#define I40E_RCU_PST_RCB_ACL_STATUS(_i)                          (0x00270030 + ((_i) * 4)) /* _i=0...2 */ /* Reset: CORER */
+#define I40E_RCU_PST_RCB_ACL_STATUS_MAX_INDEX                    2
+#define I40E_RCU_PST_RCB_ACL_STATUS_RCU_PST_RCB_ACL_STATUS_SHIFT 0
+#define I40E_RCU_PST_RCB_ACL_STATUS_RCU_PST_RCB_ACL_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_RCB_ACL_STATUS_RCU_PST_RCB_ACL_STATUS_SHIFT)
+
+#define I40E_RCU_PST_RCB_FIFO_FIELDS(_i)                           (0x00270000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: CORER */
+#define I40E_RCU_PST_RCB_FIFO_FIELDS_MAX_INDEX                     5
+#define I40E_RCU_PST_RCB_FIFO_FIELDS_RCU_PST_RCB_FIFO_FIELDS_SHIFT 0
+#define I40E_RCU_PST_RCB_FIFO_FIELDS_RCU_PST_RCB_FIFO_FIELDS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_RCB_FIFO_FIELDS_RCU_PST_RCB_FIFO_FIELDS_SHIFT)
+
+#define I40E_RCU_PST_RCB_FIFO_Q_STATUS(_i)                             (0x00270020 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
+#define I40E_RCU_PST_RCB_FIFO_Q_STATUS_MAX_INDEX                       3
+#define I40E_RCU_PST_RCB_FIFO_Q_STATUS_RCU_PST_RCB_FIFO_Q_STATUS_SHIFT 0
+#define I40E_RCU_PST_RCB_FIFO_Q_STATUS_RCU_PST_RCB_FIFO_Q_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_RCB_FIFO_Q_STATUS_RCU_PST_RCB_FIFO_Q_STATUS_SHIFT)
+
+#define I40E_RCU_PST_RCB_MTG_STATUS(_i)                          (0x00270040 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
+#define I40E_RCU_PST_RCB_MTG_STATUS_MAX_INDEX                    7
+#define I40E_RCU_PST_RCB_MTG_STATUS_RCU_PST_RCB_MTG_STATUS_SHIFT 0
+#define I40E_RCU_PST_RCB_MTG_STATUS_RCU_PST_RCB_MTG_STATUS_MASK  I40E_MASK(0xFFFFFFFF, I40E_RCU_PST_RCB_MTG_STATUS_RCU_PST_RCB_MTG_STATUS_SHIFT)
+
+#define I40E_RCU_PST_RCB_OUT_CTL                     0x0026CDA8 /* Reset: CORER */
+#define I40E_RCU_PST_RCB_OUT_CTL_BLOCK_RCB_OUT_SHIFT 0
+#define I40E_RCU_PST_RCB_OUT_CTL_BLOCK_RCB_OUT_MASK  I40E_MASK(0x1, I40E_RCU_PST_RCB_OUT_CTL_BLOCK_RCB_OUT_SHIFT)
+#define I40E_RCU_PST_RCB_OUT_CTL_STEP_ONE_CMD_SHIFT  1
+#define I40E_RCU_PST_RCB_OUT_CTL_STEP_ONE_CMD_MASK   I40E_MASK(0x1, I40E_RCU_PST_RCB_OUT_CTL_STEP_ONE_CMD_SHIFT)
+
+#define I40E_RCU_PST_RCB_OUT_STAT                    0x0026CC18 /* Reset: CORER */
+#define I40E_RCU_PST_RCB_OUT_STAT_RCB_FIFO_OCC_SHIFT 0
+#define I40E_RCU_PST_RCB_OUT_STAT_RCB_FIFO_OCC_MASK  I40E_MASK(0xF, I40E_RCU_PST_RCB_OUT_STAT_RCB_FIFO_OCC_SHIFT)
+#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_IPLEN_SHIFT   8
+#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_IPLEN_MASK    I40E_MASK(0xFFFF, I40E_RCU_PST_RCB_OUT_STAT_NEXT_IPLEN_SHIFT)
+#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_TYPE_SHIFT    24
+#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_TYPE_MASK     I40E_MASK(0x7, I40E_RCU_PST_RCB_OUT_STAT_NEXT_TYPE_SHIFT)
+#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_CFG_ERR_SHIFT 28
+#define I40E_RCU_PST_RCB_OUT_STAT_NEXT_CFG_ERR_MASK  I40E_MASK(0x1, I40E_RCU_PST_RCB_OUT_STAT_NEXT_CFG_ERR_SHIFT)
+#define I40E_RCU_PST_RCB_OUT_STAT_RSV3_SHIFT         29
+#define I40E_RCU_PST_RCB_OUT_STAT_RSV3_MASK          I40E_MASK(0x7, I40E_RCU_PST_RCB_OUT_STAT_RSV3_SHIFT)
+
+#define I40E_RCU_PST_TFIFO_CFG                    0x00269B54 /* Reset: POR */
 #define I40E_RCU_PST_TFIFO_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_PST_TFIFO_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_PST_TFIFO_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_PST_TFIFO_CFG_ECC_INVERT_1_SHIFT 1
@@ -5018,7 +5367,7 @@
 #define I40E_RCU_PST_TFIFO_CFG_RM_SHIFT           16
 #define I40E_RCU_PST_TFIFO_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_PST_TFIFO_CFG_RM_SHIFT)
 
-#define I40E_RCU_PST_TFIFO_STATUS                        0x00269B5C
+#define I40E_RCU_PST_TFIFO_STATUS                        0x00269B5C /* Reset: POR */
 #define I40E_RCU_PST_TFIFO_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_PST_TFIFO_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_PST_TFIFO_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_PST_TFIFO_STATUS_ECC_FIX_SHIFT          1
@@ -5028,7 +5377,7 @@
 #define I40E_RCU_PST_TFIFO_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_PST_TFIFO_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_PST_TFIFO_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP_BIG_FLU_CFG                    0x0026CDA4
+#define I40E_RCU_SP_BIG_FLU_CFG                    0x0026CDA4 /* Reset: POR */
 #define I40E_RCU_SP_BIG_FLU_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP_BIG_FLU_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP_BIG_FLU_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP_BIG_FLU_CFG_ECC_INVERT_1_SHIFT 1
@@ -5050,7 +5399,7 @@
 #define I40E_RCU_SP_BIG_FLU_CFG_RM_SHIFT           16
 #define I40E_RCU_SP_BIG_FLU_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP_BIG_FLU_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP_BIG_FLU_STATUS                        0x0026CDAC
+#define I40E_RCU_SP_BIG_FLU_STATUS                        0x0026CDAC /* Reset: POR */
 #define I40E_RCU_SP_BIG_FLU_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP_BIG_FLU_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP_BIG_FLU_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP_BIG_FLU_STATUS_ECC_FIX_SHIFT          1
@@ -5060,7 +5409,7 @@
 #define I40E_RCU_SP_BIG_FLU_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP_BIG_FLU_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP_BIG_FLU_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP_MTG_VSI_CNTXT_CFG                    0x002698B4
+#define I40E_RCU_SP_MTG_VSI_CNTXT_CFG                    0x002698B4 /* Reset: POR */
 #define I40E_RCU_SP_MTG_VSI_CNTXT_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP_MTG_VSI_CNTXT_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP_MTG_VSI_CNTXT_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP_MTG_VSI_CNTXT_CFG_ECC_INVERT_1_SHIFT 1
@@ -5082,7 +5431,7 @@
 #define I40E_RCU_SP_MTG_VSI_CNTXT_CFG_RM_SHIFT           16
 #define I40E_RCU_SP_MTG_VSI_CNTXT_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP_MTG_VSI_CNTXT_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP_MTG_VSI_CNTXT_STATUS                        0x002698BC
+#define I40E_RCU_SP_MTG_VSI_CNTXT_STATUS                        0x002698BC /* Reset: POR */
 #define I40E_RCU_SP_MTG_VSI_CNTXT_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP_MTG_VSI_CNTXT_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP_MTG_VSI_CNTXT_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP_MTG_VSI_CNTXT_STATUS_ECC_FIX_SHIFT          1
@@ -5092,7 +5441,7 @@
 #define I40E_RCU_SP_MTG_VSI_CNTXT_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP_MTG_VSI_CNTXT_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP_MTG_VSI_CNTXT_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP_PST_CONFIG_CFG                    0x00269AD4
+#define I40E_RCU_SP_PST_CONFIG_CFG                    0x00269AD4 /* Reset: POR */
 #define I40E_RCU_SP_PST_CONFIG_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP_PST_CONFIG_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP_PST_CONFIG_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP_PST_CONFIG_CFG_ECC_INVERT_1_SHIFT 1
@@ -5114,7 +5463,7 @@
 #define I40E_RCU_SP_PST_CONFIG_CFG_RM_SHIFT           16
 #define I40E_RCU_SP_PST_CONFIG_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP_PST_CONFIG_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP_PST_CONFIG_STATUS                        0x00269B04
+#define I40E_RCU_SP_PST_CONFIG_STATUS                        0x00269B04 /* Reset: POR */
 #define I40E_RCU_SP_PST_CONFIG_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP_PST_CONFIG_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP_PST_CONFIG_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP_PST_CONFIG_STATUS_ECC_FIX_SHIFT          1
@@ -5124,7 +5473,7 @@
 #define I40E_RCU_SP_PST_CONFIG_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP_PST_CONFIG_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP_PST_CONFIG_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP_PST_RSC_HASH_CFG                    0x00269AEC
+#define I40E_RCU_SP_PST_RSC_HASH_CFG                    0x00269AEC /* Reset: POR */
 #define I40E_RCU_SP_PST_RSC_HASH_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP_PST_RSC_HASH_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP_PST_RSC_HASH_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP_PST_RSC_HASH_CFG_ECC_INVERT_1_SHIFT 1
@@ -5146,7 +5495,7 @@
 #define I40E_RCU_SP_PST_RSC_HASH_CFG_RM_SHIFT           16
 #define I40E_RCU_SP_PST_RSC_HASH_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP_PST_RSC_HASH_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP_PST_RSC_HASH_STATUS                        0x00269B14
+#define I40E_RCU_SP_PST_RSC_HASH_STATUS                        0x00269B14 /* Reset: POR */
 #define I40E_RCU_SP_PST_RSC_HASH_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP_PST_RSC_HASH_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP_PST_RSC_HASH_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP_PST_RSC_HASH_STATUS_ECC_FIX_SHIFT          1
@@ -5156,7 +5505,7 @@
 #define I40E_RCU_SP_PST_RSC_HASH_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP_PST_RSC_HASH_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP_PST_RSC_HASH_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP_SWR_VSI_CNTXT_CFG                    0x002698C4
+#define I40E_RCU_SP_SWR_VSI_CNTXT_CFG                    0x002698C4 /* Reset: POR */
 #define I40E_RCU_SP_SWR_VSI_CNTXT_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP_SWR_VSI_CNTXT_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP_SWR_VSI_CNTXT_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP_SWR_VSI_CNTXT_CFG_ECC_INVERT_1_SHIFT 1
@@ -5178,7 +5527,7 @@
 #define I40E_RCU_SP_SWR_VSI_CNTXT_CFG_RM_SHIFT           16
 #define I40E_RCU_SP_SWR_VSI_CNTXT_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP_SWR_VSI_CNTXT_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP_SWR_VSI_CNTXT_STATUS                        0x002698CC
+#define I40E_RCU_SP_SWR_VSI_CNTXT_STATUS                        0x002698CC /* Reset: POR */
 #define I40E_RCU_SP_SWR_VSI_CNTXT_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP_SWR_VSI_CNTXT_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP_SWR_VSI_CNTXT_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP_SWR_VSI_CNTXT_STATUS_ECC_FIX_SHIFT          1
@@ -5188,7 +5537,7 @@
 #define I40E_RCU_SP_SWR_VSI_CNTXT_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP_SWR_VSI_CNTXT_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP_SWR_VSI_CNTXT_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP16KB_CFG                    0x002698D4
+#define I40E_RCU_SP16KB_CFG                    0x002698D4 /* Reset: POR */
 #define I40E_RCU_SP16KB_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP16KB_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP16KB_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP16KB_CFG_ECC_INVERT_1_SHIFT 1
@@ -5210,7 +5559,7 @@
 #define I40E_RCU_SP16KB_CFG_RM_SHIFT           16
 #define I40E_RCU_SP16KB_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP16KB_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP16KB_REP_CFG                    0x00269AF4
+#define I40E_RCU_SP16KB_REP_CFG                    0x00269AF4 /* Reset: POR */
 #define I40E_RCU_SP16KB_REP_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP16KB_REP_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP16KB_REP_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP16KB_REP_CFG_ECC_INVERT_1_SHIFT 1
@@ -5232,7 +5581,7 @@
 #define I40E_RCU_SP16KB_REP_CFG_RM_SHIFT           16
 #define I40E_RCU_SP16KB_REP_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP16KB_REP_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP16KB_REP_STATUS                        0x00269B24
+#define I40E_RCU_SP16KB_REP_STATUS                        0x00269B24 /* Reset: POR */
 #define I40E_RCU_SP16KB_REP_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP16KB_REP_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP16KB_REP_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP16KB_REP_STATUS_ECC_FIX_SHIFT          1
@@ -5242,7 +5591,7 @@
 #define I40E_RCU_SP16KB_REP_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP16KB_REP_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP16KB_REP_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP16KB_STATUS                        0x002698DC
+#define I40E_RCU_SP16KB_STATUS                        0x002698DC /* Reset: POR */
 #define I40E_RCU_SP16KB_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP16KB_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP16KB_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP16KB_STATUS_ECC_FIX_SHIFT          1
@@ -5252,7 +5601,7 @@
 #define I40E_RCU_SP16KB_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP16KB_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP16KB_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP1KB_CFG                    0x002698E4
+#define I40E_RCU_SP1KB_CFG                    0x002698E4 /* Reset: POR */
 #define I40E_RCU_SP1KB_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP1KB_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP1KB_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP1KB_CFG_ECC_INVERT_1_SHIFT 1
@@ -5274,7 +5623,7 @@
 #define I40E_RCU_SP1KB_CFG_RM_SHIFT           16
 #define I40E_RCU_SP1KB_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP1KB_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP1KB_STATUS                        0x002698EC
+#define I40E_RCU_SP1KB_STATUS                        0x002698EC /* Reset: POR */
 #define I40E_RCU_SP1KB_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP1KB_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP1KB_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP1KB_STATUS_ECC_FIX_SHIFT          1
@@ -5284,7 +5633,7 @@
 #define I40E_RCU_SP1KB_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP1KB_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP1KB_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP256B_CFG                    0x002698F4
+#define I40E_RCU_SP256B_CFG                    0x002698F4 /* Reset: POR */
 #define I40E_RCU_SP256B_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP256B_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP256B_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP256B_CFG_ECC_INVERT_1_SHIFT 1
@@ -5306,7 +5655,7 @@
 #define I40E_RCU_SP256B_CFG_RM_SHIFT           16
 #define I40E_RCU_SP256B_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP256B_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP256B_STATUS                        0x002698FC
+#define I40E_RCU_SP256B_STATUS                        0x002698FC /* Reset: POR */
 #define I40E_RCU_SP256B_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP256B_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP256B_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP256B_STATUS_ECC_FIX_SHIFT          1
@@ -5316,7 +5665,7 @@
 #define I40E_RCU_SP256B_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP256B_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP256B_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP2KB_CFG                    0x00269904
+#define I40E_RCU_SP2KB_CFG                    0x00269904 /* Reset: POR */
 #define I40E_RCU_SP2KB_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP2KB_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP2KB_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP2KB_CFG_ECC_INVERT_1_SHIFT 1
@@ -5338,7 +5687,7 @@
 #define I40E_RCU_SP2KB_CFG_RM_SHIFT           16
 #define I40E_RCU_SP2KB_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP2KB_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP2KB_STATUS                        0x0026990C
+#define I40E_RCU_SP2KB_STATUS                        0x0026990C /* Reset: POR */
 #define I40E_RCU_SP2KB_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP2KB_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP2KB_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP2KB_STATUS_ECC_FIX_SHIFT          1
@@ -5348,7 +5697,7 @@
 #define I40E_RCU_SP2KB_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP2KB_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP2KB_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP4KB_CFG                    0x00269914
+#define I40E_RCU_SP4KB_CFG                    0x00269914 /* Reset: POR */
 #define I40E_RCU_SP4KB_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP4KB_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP4KB_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP4KB_CFG_ECC_INVERT_1_SHIFT 1
@@ -5370,7 +5719,7 @@
 #define I40E_RCU_SP4KB_CFG_RM_SHIFT           16
 #define I40E_RCU_SP4KB_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP4KB_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP4KB_STATUS                        0x0026991C
+#define I40E_RCU_SP4KB_STATUS                        0x0026991C /* Reset: POR */
 #define I40E_RCU_SP4KB_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP4KB_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP4KB_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP4KB_STATUS_ECC_FIX_SHIFT          1
@@ -5380,7 +5729,7 @@
 #define I40E_RCU_SP4KB_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP4KB_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP4KB_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SP8KB_CFG                    0x00269924
+#define I40E_RCU_SP8KB_CFG                    0x00269924 /* Reset: POR */
 #define I40E_RCU_SP8KB_CFG_ECC_EN_SHIFT       0
 #define I40E_RCU_SP8KB_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RCU_SP8KB_CFG_ECC_EN_SHIFT)
 #define I40E_RCU_SP8KB_CFG_ECC_INVERT_1_SHIFT 1
@@ -5402,7 +5751,7 @@
 #define I40E_RCU_SP8KB_CFG_RM_SHIFT           16
 #define I40E_RCU_SP8KB_CFG_RM_MASK            I40E_MASK(0xF, I40E_RCU_SP8KB_CFG_RM_SHIFT)
 
-#define I40E_RCU_SP8KB_STATUS                        0x0026992C
+#define I40E_RCU_SP8KB_STATUS                        0x0026992C /* Reset: POR */
 #define I40E_RCU_SP8KB_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RCU_SP8KB_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RCU_SP8KB_STATUS_ECC_ERR_SHIFT)
 #define I40E_RCU_SP8KB_STATUS_ECC_FIX_SHIFT          1
@@ -5412,23 +5761,23 @@
 #define I40E_RCU_SP8KB_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RCU_SP8KB_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RCU_SP8KB_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RCU_SWR_ECC_COR_ERR           0x00269934
+#define I40E_RCU_SWR_ECC_COR_ERR           0x00269934 /* Reset: POR */
 #define I40E_RCU_SWR_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_RCU_SWR_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RCU_SWR_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_RCU_SWR_ECC_UNCOR_ERR           0x0026993C
+#define I40E_RCU_SWR_ECC_UNCOR_ERR           0x0026993C /* Reset: POR */
 #define I40E_RCU_SWR_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_RCU_SWR_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RCU_SWR_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_RDPU_ECC_COR_ERR           0x00051080
+#define I40E_RDPU_ECC_COR_ERR           0x00051080 /* Reset: POR */
 #define I40E_RDPU_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_RDPU_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RDPU_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_RDPU_ECC_UNCOR_ERR           0x0005107C
+#define I40E_RDPU_ECC_UNCOR_ERR           0x0005107C /* Reset: POR */
 #define I40E_RDPU_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_RDPU_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RDPU_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_RDPU_VSI_LY2_STRIP_CFG                    0x00051074
+#define I40E_RDPU_VSI_LY2_STRIP_CFG                    0x00051074 /* Reset: POR */
 #define I40E_RDPU_VSI_LY2_STRIP_CFG_ECC_EN_SHIFT       0
 #define I40E_RDPU_VSI_LY2_STRIP_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RDPU_VSI_LY2_STRIP_CFG_ECC_EN_SHIFT)
 #define I40E_RDPU_VSI_LY2_STRIP_CFG_ECC_INVERT_1_SHIFT 1
@@ -5450,7 +5799,7 @@
 #define I40E_RDPU_VSI_LY2_STRIP_CFG_RM_SHIFT           16
 #define I40E_RDPU_VSI_LY2_STRIP_CFG_RM_MASK            I40E_MASK(0xF, I40E_RDPU_VSI_LY2_STRIP_CFG_RM_SHIFT)
 
-#define I40E_RDPU_VSI_LY2_STRIP_STATUS                        0x00051078
+#define I40E_RDPU_VSI_LY2_STRIP_STATUS                        0x00051078 /* Reset: POR */
 #define I40E_RDPU_VSI_LY2_STRIP_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RDPU_VSI_LY2_STRIP_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RDPU_VSI_LY2_STRIP_STATUS_ECC_ERR_SHIFT)
 #define I40E_RDPU_VSI_LY2_STRIP_STATUS_ECC_FIX_SHIFT          1
@@ -5460,7 +5809,7 @@
 #define I40E_RDPU_VSI_LY2_STRIP_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RDPU_VSI_LY2_STRIP_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RDPU_VSI_LY2_STRIP_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RLAN_ATTR_FIFO_CFG                    0x0012A52C
+#define I40E_RLAN_ATTR_FIFO_CFG                    0x0012A52C /* Reset: POR */
 #define I40E_RLAN_ATTR_FIFO_CFG_ECC_EN_SHIFT       0
 #define I40E_RLAN_ATTR_FIFO_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RLAN_ATTR_FIFO_CFG_ECC_EN_SHIFT)
 #define I40E_RLAN_ATTR_FIFO_CFG_ECC_INVERT_1_SHIFT 1
@@ -5482,7 +5831,7 @@
 #define I40E_RLAN_ATTR_FIFO_CFG_RM_SHIFT           16
 #define I40E_RLAN_ATTR_FIFO_CFG_RM_MASK            I40E_MASK(0xF, I40E_RLAN_ATTR_FIFO_CFG_RM_SHIFT)
 
-#define I40E_RLAN_ATTR_FIFO_STATUS                        0x0012A530
+#define I40E_RLAN_ATTR_FIFO_STATUS                        0x0012A530 /* Reset: POR */
 #define I40E_RLAN_ATTR_FIFO_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RLAN_ATTR_FIFO_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RLAN_ATTR_FIFO_STATUS_ECC_ERR_SHIFT)
 #define I40E_RLAN_ATTR_FIFO_STATUS_ECC_FIX_SHIFT          1
@@ -5492,7 +5841,7 @@
 #define I40E_RLAN_ATTR_FIFO_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RLAN_ATTR_FIFO_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RLAN_ATTR_FIFO_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RLAN_CCH_CFG                    0x0012A514
+#define I40E_RLAN_CCH_CFG                    0x0012A514 /* Reset: POR */
 #define I40E_RLAN_CCH_CFG_ECC_EN_SHIFT       0
 #define I40E_RLAN_CCH_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RLAN_CCH_CFG_ECC_EN_SHIFT)
 #define I40E_RLAN_CCH_CFG_ECC_INVERT_1_SHIFT 1
@@ -5514,7 +5863,7 @@
 #define I40E_RLAN_CCH_CFG_RM_SHIFT           16
 #define I40E_RLAN_CCH_CFG_RM_MASK            I40E_MASK(0xF, I40E_RLAN_CCH_CFG_RM_SHIFT)
 
-#define I40E_RLAN_CCH_STATUS                        0x0012A518
+#define I40E_RLAN_CCH_STATUS                        0x0012A518 /* Reset: POR */
 #define I40E_RLAN_CCH_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RLAN_CCH_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RLAN_CCH_STATUS_ECC_ERR_SHIFT)
 #define I40E_RLAN_CCH_STATUS_ECC_FIX_SHIFT          1
@@ -5524,7 +5873,7 @@
 #define I40E_RLAN_CCH_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RLAN_CCH_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RLAN_CCH_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RLAN_CMD_FIFO_CFG                    0x0012A534
+#define I40E_RLAN_CMD_FIFO_CFG                    0x0012A534 /* Reset: POR */
 #define I40E_RLAN_CMD_FIFO_CFG_ECC_EN_SHIFT       0
 #define I40E_RLAN_CMD_FIFO_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RLAN_CMD_FIFO_CFG_ECC_EN_SHIFT)
 #define I40E_RLAN_CMD_FIFO_CFG_ECC_INVERT_1_SHIFT 1
@@ -5546,7 +5895,7 @@
 #define I40E_RLAN_CMD_FIFO_CFG_RM_SHIFT           16
 #define I40E_RLAN_CMD_FIFO_CFG_RM_MASK            I40E_MASK(0xF, I40E_RLAN_CMD_FIFO_CFG_RM_SHIFT)
 
-#define I40E_RLAN_CMD_FIFO_STATUS                        0x0012A538
+#define I40E_RLAN_CMD_FIFO_STATUS                        0x0012A538 /* Reset: POR */
 #define I40E_RLAN_CMD_FIFO_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RLAN_CMD_FIFO_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RLAN_CMD_FIFO_STATUS_ECC_ERR_SHIFT)
 #define I40E_RLAN_CMD_FIFO_STATUS_ECC_FIX_SHIFT          1
@@ -5556,7 +5905,7 @@
 #define I40E_RLAN_CMD_FIFO_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RLAN_CMD_FIFO_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RLAN_CMD_FIFO_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RLAN_DCH_LINE_ATTR_CFG                    0x0012A51C
+#define I40E_RLAN_DCH_LINE_ATTR_CFG                    0x0012A51C /* Reset: POR */
 #define I40E_RLAN_DCH_LINE_ATTR_CFG_ECC_EN_SHIFT       0
 #define I40E_RLAN_DCH_LINE_ATTR_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RLAN_DCH_LINE_ATTR_CFG_ECC_EN_SHIFT)
 #define I40E_RLAN_DCH_LINE_ATTR_CFG_ECC_INVERT_1_SHIFT 1
@@ -5578,7 +5927,7 @@
 #define I40E_RLAN_DCH_LINE_ATTR_CFG_RM_SHIFT           16
 #define I40E_RLAN_DCH_LINE_ATTR_CFG_RM_MASK            I40E_MASK(0xF, I40E_RLAN_DCH_LINE_ATTR_CFG_RM_SHIFT)
 
-#define I40E_RLAN_DCH_LINE_ATTR_STATUS                        0x0012A520
+#define I40E_RLAN_DCH_LINE_ATTR_STATUS                        0x0012A520 /* Reset: POR */
 #define I40E_RLAN_DCH_LINE_ATTR_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RLAN_DCH_LINE_ATTR_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RLAN_DCH_LINE_ATTR_STATUS_ECC_ERR_SHIFT)
 #define I40E_RLAN_DCH_LINE_ATTR_STATUS_ECC_FIX_SHIFT          1
@@ -5588,7 +5937,7 @@
 #define I40E_RLAN_DCH_LINE_ATTR_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RLAN_DCH_LINE_ATTR_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RLAN_DCH_LINE_ATTR_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RLAN_DSCR_CH_BNK_CFG                    0x0012A544
+#define I40E_RLAN_DSCR_CH_BNK_CFG                    0x0012A544 /* Reset: POR */
 #define I40E_RLAN_DSCR_CH_BNK_CFG_ECC_EN_SHIFT       0
 #define I40E_RLAN_DSCR_CH_BNK_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RLAN_DSCR_CH_BNK_CFG_ECC_EN_SHIFT)
 #define I40E_RLAN_DSCR_CH_BNK_CFG_ECC_INVERT_1_SHIFT 1
@@ -5610,7 +5959,7 @@
 #define I40E_RLAN_DSCR_CH_BNK_CFG_RM_SHIFT           16
 #define I40E_RLAN_DSCR_CH_BNK_CFG_RM_MASK            I40E_MASK(0xF, I40E_RLAN_DSCR_CH_BNK_CFG_RM_SHIFT)
 
-#define I40E_RLAN_DSCR_CH_BNK_STATUS                        0x0012A548
+#define I40E_RLAN_DSCR_CH_BNK_STATUS                        0x0012A548 /* Reset: POR */
 #define I40E_RLAN_DSCR_CH_BNK_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RLAN_DSCR_CH_BNK_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RLAN_DSCR_CH_BNK_STATUS_ECC_ERR_SHIFT)
 #define I40E_RLAN_DSCR_CH_BNK_STATUS_ECC_FIX_SHIFT          1
@@ -5620,7 +5969,7 @@
 #define I40E_RLAN_DSCR_CH_BNK_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RLAN_DSCR_CH_BNK_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RLAN_DSCR_CH_BNK_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RLAN_DSCR_REQ_FIFO_CFG                    0x0012A524
+#define I40E_RLAN_DSCR_REQ_FIFO_CFG                    0x0012A524 /* Reset: POR */
 #define I40E_RLAN_DSCR_REQ_FIFO_CFG_ECC_EN_SHIFT       0
 #define I40E_RLAN_DSCR_REQ_FIFO_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RLAN_DSCR_REQ_FIFO_CFG_ECC_EN_SHIFT)
 #define I40E_RLAN_DSCR_REQ_FIFO_CFG_ECC_INVERT_1_SHIFT 1
@@ -5642,7 +5991,7 @@
 #define I40E_RLAN_DSCR_REQ_FIFO_CFG_RM_SHIFT           16
 #define I40E_RLAN_DSCR_REQ_FIFO_CFG_RM_MASK            I40E_MASK(0xF, I40E_RLAN_DSCR_REQ_FIFO_CFG_RM_SHIFT)
 
-#define I40E_RLAN_DSCR_REQ_FIFO_STATUS                        0x0012A528
+#define I40E_RLAN_DSCR_REQ_FIFO_STATUS                        0x0012A528 /* Reset: POR */
 #define I40E_RLAN_DSCR_REQ_FIFO_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RLAN_DSCR_REQ_FIFO_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RLAN_DSCR_REQ_FIFO_STATUS_ECC_ERR_SHIFT)
 #define I40E_RLAN_DSCR_REQ_FIFO_STATUS_ECC_FIX_SHIFT          1
@@ -5652,15 +6001,15 @@
 #define I40E_RLAN_DSCR_REQ_FIFO_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RLAN_DSCR_REQ_FIFO_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RLAN_DSCR_REQ_FIFO_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RLAN_ECC_COR_ERR           0x0012A550
+#define I40E_RLAN_ECC_COR_ERR           0x0012A550 /* Reset: POR */
 #define I40E_RLAN_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_RLAN_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RLAN_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_RLAN_ECC_UNCOR_ERR           0x0012A54C
+#define I40E_RLAN_ECC_UNCOR_ERR           0x0012A54C /* Reset: POR */
 #define I40E_RLAN_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_RLAN_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RLAN_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_RLAN_TAILS_CFG                    0x0012A53C
+#define I40E_RLAN_TAILS_CFG                    0x0012A53C /* Reset: POR */
 #define I40E_RLAN_TAILS_CFG_ECC_EN_SHIFT       0
 #define I40E_RLAN_TAILS_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RLAN_TAILS_CFG_ECC_EN_SHIFT)
 #define I40E_RLAN_TAILS_CFG_ECC_INVERT_1_SHIFT 1
@@ -5682,7 +6031,7 @@
 #define I40E_RLAN_TAILS_CFG_RM_SHIFT           16
 #define I40E_RLAN_TAILS_CFG_RM_MASK            I40E_MASK(0xF, I40E_RLAN_TAILS_CFG_RM_SHIFT)
 
-#define I40E_RLAN_TAILS_STATUS                        0x0012A540
+#define I40E_RLAN_TAILS_STATUS                        0x0012A540 /* Reset: POR */
 #define I40E_RLAN_TAILS_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RLAN_TAILS_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RLAN_TAILS_STATUS_ECC_ERR_SHIFT)
 #define I40E_RLAN_TAILS_STATUS_ECC_FIX_SHIFT          1
@@ -5692,7 +6041,7 @@
 #define I40E_RLAN_TAILS_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RLAN_TAILS_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RLAN_TAILS_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RPB_BACK_PRS_STAT                 0x000AC948
+#define I40E_RPB_BACK_PRS_STAT                 0x000AC948 /* Reset: CORER */
 #define I40E_RPB_BACK_PRS_STAT_PPRS_0_BP_SHIFT 0
 #define I40E_RPB_BACK_PRS_STAT_PPRS_0_BP_MASK  I40E_MASK(0x1, I40E_RPB_BACK_PRS_STAT_PPRS_0_BP_SHIFT)
 #define I40E_RPB_BACK_PRS_STAT_PPRS_1_BP_SHIFT 1
@@ -5720,7 +6069,7 @@
 #define I40E_RPB_BACK_PRS_STAT_PORT_3_FC_SHIFT 15
 #define I40E_RPB_BACK_PRS_STAT_PORT_3_FC_MASK  I40E_MASK(0x1, I40E_RPB_BACK_PRS_STAT_PORT_3_FC_SHIFT)
 
-#define I40E_RPB_CC_CNT_MEM_CFG                    0x000AC860
+#define I40E_RPB_CC_CNT_MEM_CFG                    0x000AC860 /* Reset: POR */
 #define I40E_RPB_CC_CNT_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_RPB_CC_CNT_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RPB_CC_CNT_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_RPB_CC_CNT_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -5742,7 +6091,7 @@
 #define I40E_RPB_CC_CNT_MEM_CFG_RM_SHIFT           16
 #define I40E_RPB_CC_CNT_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_RPB_CC_CNT_MEM_CFG_RM_SHIFT)
 
-#define I40E_RPB_CC_CNT_MEM_STATUS                        0x000AC864
+#define I40E_RPB_CC_CNT_MEM_STATUS                        0x000AC864 /* Reset: POR */
 #define I40E_RPB_CC_CNT_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RPB_CC_CNT_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RPB_CC_CNT_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_RPB_CC_CNT_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -5752,7 +6101,7 @@
 #define I40E_RPB_CC_CNT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RPB_CC_CNT_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RPB_CC_CNT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RPB_CC_MEM_CFG                    0x000AC890
+#define I40E_RPB_CC_MEM_CFG                    0x000AC890 /* Reset: POR */
 #define I40E_RPB_CC_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_RPB_CC_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RPB_CC_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_RPB_CC_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -5774,7 +6123,7 @@
 #define I40E_RPB_CC_MEM_CFG_RM_SHIFT           16
 #define I40E_RPB_CC_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_RPB_CC_MEM_CFG_RM_SHIFT)
 
-#define I40E_RPB_CC_MEM_STATUS                        0x000AC894
+#define I40E_RPB_CC_MEM_STATUS                        0x000AC894 /* Reset: POR */
 #define I40E_RPB_CC_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RPB_CC_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RPB_CC_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_RPB_CC_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -5784,7 +6133,7 @@
 #define I40E_RPB_CC_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RPB_CC_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RPB_CC_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RPB_CLID_MEM_CFG                    0x000AC870
+#define I40E_RPB_CLID_MEM_CFG                    0x000AC870 /* Reset: POR */
 #define I40E_RPB_CLID_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_RPB_CLID_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RPB_CLID_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_RPB_CLID_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -5806,7 +6155,7 @@
 #define I40E_RPB_CLID_MEM_CFG_RM_SHIFT           16
 #define I40E_RPB_CLID_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_RPB_CLID_MEM_CFG_RM_SHIFT)
 
-#define I40E_RPB_CLID_MEM_STATUS                        0x000AC874
+#define I40E_RPB_CLID_MEM_STATUS                        0x000AC874 /* Reset: POR */
 #define I40E_RPB_CLID_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RPB_CLID_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RPB_CLID_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_RPB_CLID_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -5816,7 +6165,7 @@
 #define I40E_RPB_CLID_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RPB_CLID_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RPB_CLID_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RPB_DATA_PIPE_MEM_CFG(_i)                (0x000AC898 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_RPB_DATA_PIPE_MEM_CFG(_i)                (0x000AC898 + ((_i) * 4)) /* _i=0...7 */ /* Reset: POR */
 #define I40E_RPB_DATA_PIPE_MEM_CFG_MAX_INDEX          7
 #define I40E_RPB_DATA_PIPE_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_RPB_DATA_PIPE_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RPB_DATA_PIPE_MEM_CFG_ECC_EN_SHIFT)
@@ -5839,7 +6188,7 @@
 #define I40E_RPB_DATA_PIPE_MEM_CFG_RM_SHIFT           16
 #define I40E_RPB_DATA_PIPE_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_RPB_DATA_PIPE_MEM_CFG_RM_SHIFT)
 
-#define I40E_RPB_DATA_PIPE_MEM_STATUS(_i)                    (0x000AC8B8 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_RPB_DATA_PIPE_MEM_STATUS(_i)                    (0x000AC8B8 + ((_i) * 4)) /* _i=0...7 */ /* Reset: POR */
 #define I40E_RPB_DATA_PIPE_MEM_STATUS_MAX_INDEX              7
 #define I40E_RPB_DATA_PIPE_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RPB_DATA_PIPE_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RPB_DATA_PIPE_MEM_STATUS_ECC_ERR_SHIFT)
@@ -5850,11 +6199,11 @@
 #define I40E_RPB_DATA_PIPE_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RPB_DATA_PIPE_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RPB_DATA_PIPE_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RPB_DBG_ACC_CNT                       0x000AC8E0
+#define I40E_RPB_DBG_ACC_CNT                       0x000AC8E0 /* Reset: CORER */
 #define I40E_RPB_DBG_ACC_CNT_RPB_DBG_ACC_CNT_SHIFT 0
 #define I40E_RPB_DBG_ACC_CNT_RPB_DBG_ACC_CNT_MASK  I40E_MASK(0xFFFF, I40E_RPB_DBG_ACC_CNT_RPB_DBG_ACC_CNT_SHIFT)
 
-#define I40E_RPB_DBG_ACC_CTL               0x000AC8E4
+#define I40E_RPB_DBG_ACC_CTL               0x000AC8E4 /* Reset: CORER */
 #define I40E_RPB_DBG_ACC_CTL_ADDR_SHIFT    0
 #define I40E_RPB_DBG_ACC_CTL_ADDR_MASK     I40E_MASK(0xFFFF, I40E_RPB_DBG_ACC_CTL_ADDR_SHIFT)
 #define I40E_RPB_DBG_ACC_CTL_MEM_SEL_SHIFT 16
@@ -5862,12 +6211,12 @@
 #define I40E_RPB_DBG_ACC_CTL_EXECUTE_SHIFT 20
 #define I40E_RPB_DBG_ACC_CTL_EXECUTE_MASK  I40E_MASK(0x1, I40E_RPB_DBG_ACC_CTL_EXECUTE_SHIFT)
 
-#define I40E_RPB_DBG_ACC_DATA(_i)                     (0x000AC8EC + ((_i) * 4)) /* _i=0...7 */
+#define I40E_RPB_DBG_ACC_DATA(_i)                     (0x000AC8EC + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_RPB_DBG_ACC_DATA_MAX_INDEX               7
 #define I40E_RPB_DBG_ACC_DATA_RPB_DBG_READ_DATA_SHIFT 0
 #define I40E_RPB_DBG_ACC_DATA_RPB_DBG_READ_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_RPB_DBG_ACC_DATA_RPB_DBG_READ_DATA_SHIFT)
 
-#define I40E_RPB_DBG_ACC_STAT                0x000AC8E8
+#define I40E_RPB_DBG_ACC_STAT                0x000AC8E8 /* Reset: CORER */
 #define I40E_RPB_DBG_ACC_STAT_READY_SHIFT    0
 #define I40E_RPB_DBG_ACC_STAT_READY_MASK     I40E_MASK(0x1, I40E_RPB_DBG_ACC_STAT_READY_SHIFT)
 #define I40E_RPB_DBG_ACC_STAT_BUSY_SHIFT     1
@@ -5879,7 +6228,7 @@
 #define I40E_RPB_DBG_ACC_STAT_WD_ERR_SHIFT   6
 #define I40E_RPB_DBG_ACC_STAT_WD_ERR_MASK    I40E_MASK(0x1, I40E_RPB_DBG_ACC_STAT_WD_ERR_SHIFT)
 
-#define I40E_RPB_DBG_FEAT                         0x000AC940
+#define I40E_RPB_DBG_FEAT                         0x000AC940 /* Reset: CORER */
 #define I40E_RPB_DBG_FEAT_DISABLE_REPORTS_SHIFT   0
 #define I40E_RPB_DBG_FEAT_DISABLE_REPORTS_MASK    I40E_MASK(0x1, I40E_RPB_DBG_FEAT_DISABLE_REPORTS_SHIFT)
 #define I40E_RPB_DBG_FEAT_DISABLE_RELEASE_SHIFT   1
@@ -5907,15 +6256,15 @@
 #define I40E_RPB_DBG_FEAT_LTR_CLK_GEN_VAL_SHIFT   20
 #define I40E_RPB_DBG_FEAT_LTR_CLK_GEN_VAL_MASK    I40E_MASK(0xFFF, I40E_RPB_DBG_FEAT_LTR_CLK_GEN_VAL_SHIFT)
 
-#define I40E_RPB_ECC_COR_ERR           0x000AC8DC
+#define I40E_RPB_ECC_COR_ERR           0x000AC8DC /* Reset: POR */
 #define I40E_RPB_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_RPB_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RPB_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_RPB_ECC_UNCOR_ERR           0x000AC8D8
+#define I40E_RPB_ECC_UNCOR_ERR           0x000AC8D8 /* Reset: POR */
 #define I40E_RPB_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_RPB_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_RPB_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_RPB_EGR_CNT                0x000AC94C
+#define I40E_RPB_EGR_CNT                0x000AC94C /* Reset: CORER */
 #define I40E_RPB_EGR_CNT_RCU_REQ_SHIFT  0
 #define I40E_RPB_EGR_CNT_RCU_REQ_MASK   I40E_MASK(0xFF, I40E_RPB_EGR_CNT_RCU_REQ_SHIFT)
 #define I40E_RPB_EGR_CNT_PE_0_REQ_SHIFT 8
@@ -5925,13 +6274,13 @@
 #define I40E_RPB_EGR_CNT_RDPU_REQ_SHIFT 24
 #define I40E_RPB_EGR_CNT_RDPU_REQ_MASK  I40E_MASK(0xFF, I40E_RPB_EGR_CNT_RDPU_REQ_SHIFT)
 
-#define I40E_RPB_GEN_DBG_CNT                  0x000AC944
+#define I40E_RPB_GEN_DBG_CNT                  0x000AC944 /* Reset: CORER */
 #define I40E_RPB_GEN_DBG_CNT_FREE_CC_SHIFT    0
 #define I40E_RPB_GEN_DBG_CNT_FREE_CC_MASK     I40E_MASK(0x1FF, I40E_RPB_GEN_DBG_CNT_FREE_CC_SHIFT)
 #define I40E_RPB_GEN_DBG_CNT_FREE_CLIDS_SHIFT 16
 #define I40E_RPB_GEN_DBG_CNT_FREE_CLIDS_MASK  I40E_MASK(0x3FFF, I40E_RPB_GEN_DBG_CNT_FREE_CLIDS_SHIFT)
 
-#define I40E_RPB_PKT_MEM_CFG                    0x000AC868
+#define I40E_RPB_PKT_MEM_CFG                    0x000AC868 /* Reset: POR */
 #define I40E_RPB_PKT_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_RPB_PKT_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RPB_PKT_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_RPB_PKT_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -5953,7 +6302,7 @@
 #define I40E_RPB_PKT_MEM_CFG_RM_SHIFT           16
 #define I40E_RPB_PKT_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_RPB_PKT_MEM_CFG_RM_SHIFT)
 
-#define I40E_RPB_PKT_MEM_STATUS                        0x000AC86C
+#define I40E_RPB_PKT_MEM_STATUS                        0x000AC86C /* Reset: POR */
 #define I40E_RPB_PKT_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RPB_PKT_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RPB_PKT_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_RPB_PKT_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -5963,7 +6312,7 @@
 #define I40E_RPB_PKT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RPB_PKT_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RPB_PKT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RPB_PPDB_MEM_CFG                    0x000AC878
+#define I40E_RPB_PPDB_MEM_CFG                    0x000AC878 /* Reset: POR */
 #define I40E_RPB_PPDB_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_RPB_PPDB_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RPB_PPDB_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_RPB_PPDB_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -5989,7 +6338,7 @@
 #define I40E_RPB_PPDB_MEM_CFG_RM_B_SHIFT         20
 #define I40E_RPB_PPDB_MEM_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_RPB_PPDB_MEM_CFG_RM_B_SHIFT)
 
-#define I40E_RPB_PPDB_MEM_STATUS                        0x000AC87C
+#define I40E_RPB_PPDB_MEM_STATUS                        0x000AC87C /* Reset: POR */
 #define I40E_RPB_PPDB_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RPB_PPDB_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RPB_PPDB_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_RPB_PPDB_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -5999,14 +6348,14 @@
 #define I40E_RPB_PPDB_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RPB_PPDB_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RPB_PPDB_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RPB_PPRS_ERR_CNT(_i)                 (0x000AC910 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_RPB_PPRS_ERR_CNT(_i)                 (0x000AC910 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_RPB_PPRS_ERR_CNT_MAX_INDEX           3
 #define I40E_RPB_PPRS_ERR_CNT_PKT_SIZE_ERR_SHIFT  0
 #define I40E_RPB_PPRS_ERR_CNT_PKT_SIZE_ERR_MASK   I40E_MASK(0xFF, I40E_RPB_PPRS_ERR_CNT_PKT_SIZE_ERR_SHIFT)
 #define I40E_RPB_PPRS_ERR_CNT_VALID_BTW_PKT_SHIFT 8
 #define I40E_RPB_PPRS_ERR_CNT_VALID_BTW_PKT_MASK  I40E_MASK(0xFF, I40E_RPB_PPRS_ERR_CNT_VALID_BTW_PKT_SHIFT)
 
-#define I40E_RPB_REPORT_LL_MEM_CFG                    0x000AC880
+#define I40E_RPB_REPORT_LL_MEM_CFG                    0x000AC880 /* Reset: POR */
 #define I40E_RPB_REPORT_LL_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_RPB_REPORT_LL_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RPB_REPORT_LL_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_RPB_REPORT_LL_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6028,7 +6377,7 @@
 #define I40E_RPB_REPORT_LL_MEM_CFG_RM_SHIFT           16
 #define I40E_RPB_REPORT_LL_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_RPB_REPORT_LL_MEM_CFG_RM_SHIFT)
 
-#define I40E_RPB_REPORT_LL_MEM_STATUS                        0x000AC884
+#define I40E_RPB_REPORT_LL_MEM_STATUS                        0x000AC884 /* Reset: POR */
 #define I40E_RPB_REPORT_LL_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RPB_REPORT_LL_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RPB_REPORT_LL_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_RPB_REPORT_LL_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6038,7 +6387,7 @@
 #define I40E_RPB_REPORT_LL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RPB_REPORT_LL_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RPB_REPORT_LL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RPB_REPORT_MEM_CFG                    0x000AC888
+#define I40E_RPB_REPORT_MEM_CFG                    0x000AC888 /* Reset: POR */
 #define I40E_RPB_REPORT_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_RPB_REPORT_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_RPB_REPORT_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_RPB_REPORT_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6060,7 +6409,7 @@
 #define I40E_RPB_REPORT_MEM_CFG_RM_SHIFT           16
 #define I40E_RPB_REPORT_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_RPB_REPORT_MEM_CFG_RM_SHIFT)
 
-#define I40E_RPB_REPORT_MEM_STATUS                        0x000AC88C
+#define I40E_RPB_REPORT_MEM_STATUS                        0x000AC88C /* Reset: POR */
 #define I40E_RPB_REPORT_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_RPB_REPORT_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_RPB_REPORT_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_RPB_REPORT_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6070,27 +6419,27 @@
 #define I40E_RPB_REPORT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_RPB_REPORT_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_RPB_REPORT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_RPB_RPT_CNT                   0x000AC950
+#define I40E_RPB_RPT_CNT                   0x000AC950 /* Reset: CORER */
 #define I40E_RPB_RPT_CNT_RPB_RPT_CNT_SHIFT 0
 #define I40E_RPB_RPT_CNT_RPB_RPT_CNT_MASK  I40E_MASK(0xFFFF, I40E_RPB_RPT_CNT_RPB_RPT_CNT_SHIFT)
 
-#define I40E_RPB_RPT_STAT                    0x000AC954
+#define I40E_RPB_RPT_STAT                    0x000AC954 /* Reset: CORER */
 #define I40E_RPB_RPT_STAT_RPB_RPT_STAT_SHIFT 0
 #define I40E_RPB_RPT_STAT_RPB_RPT_STAT_MASK  I40E_MASK(0xFFFFFFFF, I40E_RPB_RPT_STAT_RPB_RPT_STAT_SHIFT)
 
-#define I40E_RPB_SHR_MOD_CNT                       0x000AC90C
+#define I40E_RPB_SHR_MOD_CNT                       0x000AC90C /* Reset: CORER */
 #define I40E_RPB_SHR_MOD_CNT_RPB_SHR_MOD_CNT_SHIFT 0
 #define I40E_RPB_SHR_MOD_CNT_RPB_SHR_MOD_CNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_RPB_SHR_MOD_CNT_RPB_SHR_MOD_CNT_SHIFT)
 
-#define I40E_TCB_ECC_COR_ERR           0x000AE0A8
+#define I40E_TCB_ECC_COR_ERR           0x000AE0A8 /* Reset: POR */
 #define I40E_TCB_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_TCB_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TCB_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_TCB_ECC_UNCOR_ERR           0x000AE0A4
+#define I40E_TCB_ECC_UNCOR_ERR           0x000AE0A4 /* Reset: POR */
 #define I40E_TCB_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_TCB_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TCB_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_TCB_PORT_CMD_BUF_DBG_CTL              0x000AE0B4
+#define I40E_TCB_PORT_CMD_BUF_DBG_CTL              0x000AE0B4 /* Reset: CORER */
 #define I40E_TCB_PORT_CMD_BUF_DBG_CTL_ADR_SHIFT    0
 #define I40E_TCB_PORT_CMD_BUF_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_TCB_PORT_CMD_BUF_DBG_CTL_ADR_SHIFT)
 #define I40E_TCB_PORT_CMD_BUF_DBG_CTL_DW_SEL_SHIFT 18
@@ -6100,11 +6449,11 @@
 #define I40E_TCB_PORT_CMD_BUF_DBG_CTL_DONE_SHIFT   31
 #define I40E_TCB_PORT_CMD_BUF_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_TCB_PORT_CMD_BUF_DBG_CTL_DONE_SHIFT)
 
-#define I40E_TCB_PORT_CMD_BUF_DBG_DATA             0x000AE0CC
+#define I40E_TCB_PORT_CMD_BUF_DBG_DATA             0x000AE0CC /* Reset: CORER */
 #define I40E_TCB_PORT_CMD_BUF_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_TCB_PORT_CMD_BUF_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_TCB_PORT_CMD_BUF_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_TCB_PORT_CMD_MNG_DBG_CTL              0x000AE0B8
+#define I40E_TCB_PORT_CMD_MNG_DBG_CTL              0x000AE0B8 /* Reset: CORER */
 #define I40E_TCB_PORT_CMD_MNG_DBG_CTL_ADR_SHIFT    0
 #define I40E_TCB_PORT_CMD_MNG_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_TCB_PORT_CMD_MNG_DBG_CTL_ADR_SHIFT)
 #define I40E_TCB_PORT_CMD_MNG_DBG_CTL_DW_SEL_SHIFT 18
@@ -6114,11 +6463,11 @@
 #define I40E_TCB_PORT_CMD_MNG_DBG_CTL_DONE_SHIFT   31
 #define I40E_TCB_PORT_CMD_MNG_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_TCB_PORT_CMD_MNG_DBG_CTL_DONE_SHIFT)
 
-#define I40E_TCB_PORT_CMD_MNG_DBG_DATA             0x000AE0C0
+#define I40E_TCB_PORT_CMD_MNG_DBG_DATA             0x000AE0C0 /* Reset: CORER */
 #define I40E_TCB_PORT_CMD_MNG_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_TCB_PORT_CMD_MNG_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_TCB_PORT_CMD_MNG_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_TCB_WAIT_CMD_BUF_DBG_CTL              0x000AE0BC
+#define I40E_TCB_WAIT_CMD_BUF_DBG_CTL              0x000AE0BC /* Reset: CORER */
 #define I40E_TCB_WAIT_CMD_BUF_DBG_CTL_ADR_SHIFT    0
 #define I40E_TCB_WAIT_CMD_BUF_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_TCB_WAIT_CMD_BUF_DBG_CTL_ADR_SHIFT)
 #define I40E_TCB_WAIT_CMD_BUF_DBG_CTL_DW_SEL_SHIFT 18
@@ -6128,11 +6477,11 @@
 #define I40E_TCB_WAIT_CMD_BUF_DBG_CTL_DONE_SHIFT   31
 #define I40E_TCB_WAIT_CMD_BUF_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_TCB_WAIT_CMD_BUF_DBG_CTL_DONE_SHIFT)
 
-#define I40E_TCB_WAIT_CMD_BUF_DBG_DATA             0x000AE0C4
+#define I40E_TCB_WAIT_CMD_BUF_DBG_DATA             0x000AE0C4 /* Reset: CORER */
 #define I40E_TCB_WAIT_CMD_BUF_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_TCB_WAIT_CMD_BUF_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_TCB_WAIT_CMD_BUF_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_TCB_WAIT_CMD_MNG_DBG_CTL              0x000AE0B0
+#define I40E_TCB_WAIT_CMD_MNG_DBG_CTL              0x000AE0B0 /* Reset: CORER */
 #define I40E_TCB_WAIT_CMD_MNG_DBG_CTL_ADR_SHIFT    0
 #define I40E_TCB_WAIT_CMD_MNG_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_TCB_WAIT_CMD_MNG_DBG_CTL_ADR_SHIFT)
 #define I40E_TCB_WAIT_CMD_MNG_DBG_CTL_DW_SEL_SHIFT 18
@@ -6142,11 +6491,11 @@
 #define I40E_TCB_WAIT_CMD_MNG_DBG_CTL_DONE_SHIFT   31
 #define I40E_TCB_WAIT_CMD_MNG_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_TCB_WAIT_CMD_MNG_DBG_CTL_DONE_SHIFT)
 
-#define I40E_TCB_WAIT_CMD_MNG_DBG_DATA             0x000AE0C8
+#define I40E_TCB_WAIT_CMD_MNG_DBG_DATA             0x000AE0C8 /* Reset: CORER */
 #define I40E_TCB_WAIT_CMD_MNG_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_TCB_WAIT_CMD_MNG_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_TCB_WAIT_CMD_MNG_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_TDPU_CMD_MUX_MEM_CFG                    0x00044304
+#define I40E_TDPU_CMD_MUX_MEM_CFG                    0x00044304 /* Reset: POR */
 #define I40E_TDPU_CMD_MUX_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TDPU_CMD_MUX_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TDPU_CMD_MUX_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TDPU_CMD_MUX_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6168,7 +6517,7 @@
 #define I40E_TDPU_CMD_MUX_MEM_CFG_RM_SHIFT           16
 #define I40E_TDPU_CMD_MUX_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TDPU_CMD_MUX_MEM_CFG_RM_SHIFT)
 
-#define I40E_TDPU_CMD_MUX_MEM_STATUS                        0x00044330
+#define I40E_TDPU_CMD_MUX_MEM_STATUS                        0x00044330 /* Reset: POR */
 #define I40E_TDPU_CMD_MUX_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TDPU_CMD_MUX_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TDPU_CMD_MUX_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TDPU_CMD_MUX_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6178,7 +6527,7 @@
 #define I40E_TDPU_CMD_MUX_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TDPU_CMD_MUX_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TDPU_CMD_MUX_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TDPU_DAC_MEM_CFG                    0x00044310
+#define I40E_TDPU_DAC_MEM_CFG                    0x00044310 /* Reset: POR */
 #define I40E_TDPU_DAC_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TDPU_DAC_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TDPU_DAC_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TDPU_DAC_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6200,7 +6549,7 @@
 #define I40E_TDPU_DAC_MEM_CFG_RM_SHIFT           16
 #define I40E_TDPU_DAC_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TDPU_DAC_MEM_CFG_RM_SHIFT)
 
-#define I40E_TDPU_DAC_MEM_STATUS                        0x00044328
+#define I40E_TDPU_DAC_MEM_STATUS                        0x00044328 /* Reset: POR */
 #define I40E_TDPU_DAC_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TDPU_DAC_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TDPU_DAC_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TDPU_DAC_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6210,7 +6559,7 @@
 #define I40E_TDPU_DAC_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TDPU_DAC_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TDPU_DAC_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TDPU_DAC_MNG_MEM_CFG                    0x0004430C
+#define I40E_TDPU_DAC_MNG_MEM_CFG                    0x0004430C /* Reset: POR */
 #define I40E_TDPU_DAC_MNG_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TDPU_DAC_MNG_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TDPU_DAC_MNG_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TDPU_DAC_MNG_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6232,7 +6581,7 @@
 #define I40E_TDPU_DAC_MNG_MEM_CFG_RM_SHIFT           16
 #define I40E_TDPU_DAC_MNG_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TDPU_DAC_MNG_MEM_CFG_RM_SHIFT)
 
-#define I40E_TDPU_DAC_MNG_MEM_STATUS                        0x0004432C
+#define I40E_TDPU_DAC_MNG_MEM_STATUS                        0x0004432C /* Reset: POR */
 #define I40E_TDPU_DAC_MNG_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TDPU_DAC_MNG_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TDPU_DAC_MNG_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TDPU_DAC_MNG_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6242,15 +6591,15 @@
 #define I40E_TDPU_DAC_MNG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TDPU_DAC_MNG_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TDPU_DAC_MNG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TDPU_ECC_COR_ERR           0x0004433C
+#define I40E_TDPU_ECC_COR_ERR           0x0004433C /* Reset: POR */
 #define I40E_TDPU_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_TDPU_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TDPU_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_TDPU_ECC_UNCOR_ERR           0x00044338
+#define I40E_TDPU_ECC_UNCOR_ERR           0x00044338 /* Reset: POR */
 #define I40E_TDPU_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_TDPU_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TDPU_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_TDPU_IMEM_CFG                    0x000442F8
+#define I40E_TDPU_IMEM_CFG                    0x000442F8 /* Reset: POR */
 #define I40E_TDPU_IMEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TDPU_IMEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TDPU_IMEM_CFG_ECC_EN_SHIFT)
 #define I40E_TDPU_IMEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6272,7 +6621,7 @@
 #define I40E_TDPU_IMEM_CFG_RM_SHIFT           16
 #define I40E_TDPU_IMEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TDPU_IMEM_CFG_RM_SHIFT)
 
-#define I40E_TDPU_IMEM_STATUS                        0x00044318
+#define I40E_TDPU_IMEM_STATUS                        0x00044318 /* Reset: POR */
 #define I40E_TDPU_IMEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TDPU_IMEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TDPU_IMEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TDPU_IMEM_STATUS_ECC_FIX_SHIFT          1
@@ -6282,7 +6631,7 @@
 #define I40E_TDPU_IMEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TDPU_IMEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TDPU_IMEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TDPU_RECIPE_ADDR_CFG                    0x000442FC
+#define I40E_TDPU_RECIPE_ADDR_CFG                    0x000442FC /* Reset: POR */
 #define I40E_TDPU_RECIPE_ADDR_CFG_ECC_EN_SHIFT       0
 #define I40E_TDPU_RECIPE_ADDR_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TDPU_RECIPE_ADDR_CFG_ECC_EN_SHIFT)
 #define I40E_TDPU_RECIPE_ADDR_CFG_ECC_INVERT_1_SHIFT 1
@@ -6304,7 +6653,7 @@
 #define I40E_TDPU_RECIPE_ADDR_CFG_RM_SHIFT           16
 #define I40E_TDPU_RECIPE_ADDR_CFG_RM_MASK            I40E_MASK(0xF, I40E_TDPU_RECIPE_ADDR_CFG_RM_SHIFT)
 
-#define I40E_TDPU_RECIPE_ADDR_STATUS                        0x0004431C
+#define I40E_TDPU_RECIPE_ADDR_STATUS                        0x0004431C /* Reset: POR */
 #define I40E_TDPU_RECIPE_ADDR_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TDPU_RECIPE_ADDR_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TDPU_RECIPE_ADDR_STATUS_ECC_ERR_SHIFT)
 #define I40E_TDPU_RECIPE_ADDR_STATUS_ECC_FIX_SHIFT          1
@@ -6314,7 +6663,7 @@
 #define I40E_TDPU_RECIPE_ADDR_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TDPU_RECIPE_ADDR_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TDPU_RECIPE_ADDR_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TDPU_TDRD_MEM_CFG                    0x00044314
+#define I40E_TDPU_TDRD_MEM_CFG                    0x00044314 /* Reset: POR */
 #define I40E_TDPU_TDRD_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TDPU_TDRD_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TDPU_TDRD_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TDPU_TDRD_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6336,7 +6685,7 @@
 #define I40E_TDPU_TDRD_MEM_CFG_RM_SHIFT           16
 #define I40E_TDPU_TDRD_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TDPU_TDRD_MEM_CFG_RM_SHIFT)
 
-#define I40E_TDPU_TDRD_MEM_STATUS                        0x00044324
+#define I40E_TDPU_TDRD_MEM_STATUS                        0x00044324 /* Reset: POR */
 #define I40E_TDPU_TDRD_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TDPU_TDRD_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TDPU_TDRD_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TDPU_TDRD_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6346,7 +6695,7 @@
 #define I40E_TDPU_TDRD_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TDPU_TDRD_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TDPU_TDRD_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TDPU_TDWR_MEM_CFG                    0x00044308
+#define I40E_TDPU_TDWR_MEM_CFG                    0x00044308 /* Reset: POR */
 #define I40E_TDPU_TDWR_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TDPU_TDWR_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TDPU_TDWR_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TDPU_TDWR_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6368,7 +6717,7 @@
 #define I40E_TDPU_TDWR_MEM_CFG_RM_SHIFT           16
 #define I40E_TDPU_TDWR_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TDPU_TDWR_MEM_CFG_RM_SHIFT)
 
-#define I40E_TDPU_TDWR_MEM_STATUS                        0x00044334
+#define I40E_TDPU_TDWR_MEM_STATUS                        0x00044334 /* Reset: POR */
 #define I40E_TDPU_TDWR_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TDPU_TDWR_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TDPU_TDWR_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TDPU_TDWR_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6378,7 +6727,7 @@
 #define I40E_TDPU_TDWR_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TDPU_TDWR_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TDPU_TDWR_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TDPU_VSI_LY2_INSERT_MEM_CFG                    0x00044300
+#define I40E_TDPU_VSI_LY2_INSERT_MEM_CFG                    0x00044300 /* Reset: POR */
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TDPU_VSI_LY2_INSERT_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6400,7 +6749,7 @@
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_CFG_RM_SHIFT           16
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TDPU_VSI_LY2_INSERT_MEM_CFG_RM_SHIFT)
 
-#define I40E_TDPU_VSI_LY2_INSERT_MEM_STATUS                        0x00044320
+#define I40E_TDPU_VSI_LY2_INSERT_MEM_STATUS                        0x00044320 /* Reset: POR */
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TDPU_VSI_LY2_INSERT_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6410,7 +6759,7 @@
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TDPU_VSI_LY2_INSERT_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TDPU_VSI_LY2_INSERT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TLAN_DEC_MEM_CFG                    0x000E6490
+#define I40E_TLAN_DEC_MEM_CFG                    0x000E6490 /* Reset: POR */
 #define I40E_TLAN_DEC_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TLAN_DEC_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TLAN_DEC_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TLAN_DEC_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6432,7 +6781,7 @@
 #define I40E_TLAN_DEC_MEM_CFG_RM_SHIFT           16
 #define I40E_TLAN_DEC_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TLAN_DEC_MEM_CFG_RM_SHIFT)
 
-#define I40E_TLAN_DEC_MEM_STATUS                        0x000E6494
+#define I40E_TLAN_DEC_MEM_STATUS                        0x000E6494 /* Reset: POR */
 #define I40E_TLAN_DEC_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TLAN_DEC_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TLAN_DEC_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TLAN_DEC_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6442,7 +6791,7 @@
 #define I40E_TLAN_DEC_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TLAN_DEC_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TLAN_DEC_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TLAN_DEC_MNG_MEM_CFG                    0x000E64A0
+#define I40E_TLAN_DEC_MNG_MEM_CFG                    0x000E64A0 /* Reset: POR */
 #define I40E_TLAN_DEC_MNG_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TLAN_DEC_MNG_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TLAN_DEC_MNG_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TLAN_DEC_MNG_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6464,7 +6813,7 @@
 #define I40E_TLAN_DEC_MNG_MEM_CFG_RM_SHIFT           16
 #define I40E_TLAN_DEC_MNG_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TLAN_DEC_MNG_MEM_CFG_RM_SHIFT)
 
-#define I40E_TLAN_DEC_MNG_MEM_STATUS                        0x000E64A4
+#define I40E_TLAN_DEC_MNG_MEM_STATUS                        0x000E64A4 /* Reset: POR */
 #define I40E_TLAN_DEC_MNG_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TLAN_DEC_MNG_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TLAN_DEC_MNG_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TLAN_DEC_MNG_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6474,7 +6823,7 @@
 #define I40E_TLAN_DEC_MNG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TLAN_DEC_MNG_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TLAN_DEC_MNG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TLAN_DEC_PTRS_MEM_CFG                    0x000E6498
+#define I40E_TLAN_DEC_PTRS_MEM_CFG                    0x000E6498 /* Reset: POR */
 #define I40E_TLAN_DEC_PTRS_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TLAN_DEC_PTRS_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TLAN_DEC_PTRS_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TLAN_DEC_PTRS_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6496,7 +6845,7 @@
 #define I40E_TLAN_DEC_PTRS_MEM_CFG_RM_SHIFT           16
 #define I40E_TLAN_DEC_PTRS_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TLAN_DEC_PTRS_MEM_CFG_RM_SHIFT)
 
-#define I40E_TLAN_DEC_PTRS_MEM_STATUS                        0x000E649C
+#define I40E_TLAN_DEC_PTRS_MEM_STATUS                        0x000E649C /* Reset: POR */
 #define I40E_TLAN_DEC_PTRS_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TLAN_DEC_PTRS_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TLAN_DEC_PTRS_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TLAN_DEC_PTRS_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6506,15 +6855,15 @@
 #define I40E_TLAN_DEC_PTRS_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TLAN_DEC_PTRS_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TLAN_DEC_PTRS_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TLAN_ECC_COR_ERR           0x000E64B4
+#define I40E_TLAN_ECC_COR_ERR           0x000E64B4 /* Reset: POR */
 #define I40E_TLAN_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_TLAN_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TLAN_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_TLAN_ECC_UNCOR_ERR           0x000E64B0
+#define I40E_TLAN_ECC_UNCOR_ERR           0x000E64B0 /* Reset: POR */
 #define I40E_TLAN_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_TLAN_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TLAN_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_TLAN_HEAD_WB_CFG                    0x000E64A8
+#define I40E_TLAN_HEAD_WB_CFG                    0x000E64A8 /* Reset: POR */
 #define I40E_TLAN_HEAD_WB_CFG_ECC_EN_SHIFT       0
 #define I40E_TLAN_HEAD_WB_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TLAN_HEAD_WB_CFG_ECC_EN_SHIFT)
 #define I40E_TLAN_HEAD_WB_CFG_ECC_INVERT_1_SHIFT 1
@@ -6536,7 +6885,7 @@
 #define I40E_TLAN_HEAD_WB_CFG_RM_SHIFT           16
 #define I40E_TLAN_HEAD_WB_CFG_RM_MASK            I40E_MASK(0xF, I40E_TLAN_HEAD_WB_CFG_RM_SHIFT)
 
-#define I40E_TLAN_HEAD_WB_STATUS                        0x000E64AC
+#define I40E_TLAN_HEAD_WB_STATUS                        0x000E64AC /* Reset: POR */
 #define I40E_TLAN_HEAD_WB_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TLAN_HEAD_WB_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TLAN_HEAD_WB_STATUS_ECC_ERR_SHIFT)
 #define I40E_TLAN_HEAD_WB_STATUS_ECC_FIX_SHIFT          1
@@ -6546,7 +6895,7 @@
 #define I40E_TLAN_HEAD_WB_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TLAN_HEAD_WB_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TLAN_HEAD_WB_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TPB_CLID_MEM_CFG                    0x0009808C
+#define I40E_TPB_CLID_MEM_CFG                    0x0009808C /* Reset: POR */
 #define I40E_TPB_CLID_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TPB_CLID_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TPB_CLID_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TPB_CLID_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6568,7 +6917,7 @@
 #define I40E_TPB_CLID_MEM_CFG_RM_SHIFT           16
 #define I40E_TPB_CLID_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TPB_CLID_MEM_CFG_RM_SHIFT)
 
-#define I40E_TPB_CLID_MEM_DBG_CTL              0x000980C8
+#define I40E_TPB_CLID_MEM_DBG_CTL              0x000980C8 /* Reset: CORER */
 #define I40E_TPB_CLID_MEM_DBG_CTL_ADR_SHIFT    0
 #define I40E_TPB_CLID_MEM_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_TPB_CLID_MEM_DBG_CTL_ADR_SHIFT)
 #define I40E_TPB_CLID_MEM_DBG_CTL_DW_SEL_SHIFT 18
@@ -6578,11 +6927,11 @@
 #define I40E_TPB_CLID_MEM_DBG_CTL_DONE_SHIFT   31
 #define I40E_TPB_CLID_MEM_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_TPB_CLID_MEM_DBG_CTL_DONE_SHIFT)
 
-#define I40E_TPB_CLID_MEM_DBG_DATA             0x000980D4
+#define I40E_TPB_CLID_MEM_DBG_DATA             0x000980D4 /* Reset: CORER */
 #define I40E_TPB_CLID_MEM_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_TPB_CLID_MEM_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_TPB_CLID_MEM_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_TPB_CLID_MEM_STATUS                        0x00098090
+#define I40E_TPB_CLID_MEM_STATUS                        0x00098090 /* Reset: POR */
 #define I40E_TPB_CLID_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TPB_CLID_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TPB_CLID_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TPB_CLID_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6592,7 +6941,7 @@
 #define I40E_TPB_CLID_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TPB_CLID_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TPB_CLID_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TPB_DBG_FEAT                     0x00098084
+#define I40E_TPB_DBG_FEAT                     0x00098084 /* Reset: CORER */
 #define I40E_TPB_DBG_FEAT_DIS_MIB_SHIFT       0
 #define I40E_TPB_DBG_FEAT_DIS_MIB_MASK        I40E_MASK(0xF, I40E_TPB_DBG_FEAT_DIS_MIB_SHIFT)
 #define I40E_TPB_DBG_FEAT_FORCE_FC_IND_SHIFT  4
@@ -6602,19 +6951,19 @@
 #define I40E_TPB_DBG_FEAT_DIS_BURST_CTL_SHIFT 12
 #define I40E_TPB_DBG_FEAT_DIS_BURST_CTL_MASK  I40E_MASK(0xF, I40E_TPB_DBG_FEAT_DIS_BURST_CTL_SHIFT)
 
-#define I40E_TPB_ECC_COR_ERR           0x000980B8
+#define I40E_TPB_ECC_COR_ERR           0x000980B8 /* Reset: POR */
 #define I40E_TPB_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_TPB_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TPB_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_TPB_ECC_UNCOR_ERR           0x000980B4
+#define I40E_TPB_ECC_UNCOR_ERR           0x000980B4 /* Reset: POR */
 #define I40E_TPB_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_TPB_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TPB_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_TPB_FC_OVR                  0x00098088
+#define I40E_TPB_FC_OVR                  0x00098088 /* Reset: CORER */
 #define I40E_TPB_FC_OVR_TPB_FC_OVR_SHIFT 0
 #define I40E_TPB_FC_OVR_TPB_FC_OVR_MASK  I40E_MASK(0xFFFFFFFF, I40E_TPB_FC_OVR_TPB_FC_OVR_SHIFT)
 
-#define I40E_TPB_PKT_MEM_CFG                    0x00098094
+#define I40E_TPB_PKT_MEM_CFG                    0x00098094 /* Reset: POR */
 #define I40E_TPB_PKT_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TPB_PKT_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TPB_PKT_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TPB_PKT_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6636,7 +6985,7 @@
 #define I40E_TPB_PKT_MEM_CFG_RM_SHIFT           16
 #define I40E_TPB_PKT_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TPB_PKT_MEM_CFG_RM_SHIFT)
 
-#define I40E_TPB_PKT_MEM_DBG_CTL              0x000980CC
+#define I40E_TPB_PKT_MEM_DBG_CTL              0x000980CC /* Reset: CORER */
 #define I40E_TPB_PKT_MEM_DBG_CTL_ADR_SHIFT    0
 #define I40E_TPB_PKT_MEM_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_TPB_PKT_MEM_DBG_CTL_ADR_SHIFT)
 #define I40E_TPB_PKT_MEM_DBG_CTL_DW_SEL_SHIFT 18
@@ -6646,11 +6995,11 @@
 #define I40E_TPB_PKT_MEM_DBG_CTL_DONE_SHIFT   31
 #define I40E_TPB_PKT_MEM_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_TPB_PKT_MEM_DBG_CTL_DONE_SHIFT)
 
-#define I40E_TPB_PKT_MEM_DBG_DATA             0x000980E0
+#define I40E_TPB_PKT_MEM_DBG_DATA             0x000980E0 /* Reset: CORER */
 #define I40E_TPB_PKT_MEM_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_TPB_PKT_MEM_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_TPB_PKT_MEM_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_TPB_PKT_MEM_STATUS                        0x00098098
+#define I40E_TPB_PKT_MEM_STATUS                        0x00098098 /* Reset: POR */
 #define I40E_TPB_PKT_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TPB_PKT_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TPB_PKT_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TPB_PKT_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6660,7 +7009,7 @@
 #define I40E_TPB_PKT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TPB_PKT_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TPB_PKT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TPB_REPORT_LL_MEM_CFG                    0x0009809C
+#define I40E_TPB_REPORT_LL_MEM_CFG                    0x0009809C /* Reset: POR */
 #define I40E_TPB_REPORT_LL_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TPB_REPORT_LL_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TPB_REPORT_LL_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TPB_REPORT_LL_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6682,7 +7031,7 @@
 #define I40E_TPB_REPORT_LL_MEM_CFG_RM_SHIFT           16
 #define I40E_TPB_REPORT_LL_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TPB_REPORT_LL_MEM_CFG_RM_SHIFT)
 
-#define I40E_TPB_REPORT_LL_MEM_DBG_CTL              0x000980C0
+#define I40E_TPB_REPORT_LL_MEM_DBG_CTL              0x000980C0 /* Reset: CORER */
 #define I40E_TPB_REPORT_LL_MEM_DBG_CTL_ADR_SHIFT    0
 #define I40E_TPB_REPORT_LL_MEM_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_TPB_REPORT_LL_MEM_DBG_CTL_ADR_SHIFT)
 #define I40E_TPB_REPORT_LL_MEM_DBG_CTL_DW_SEL_SHIFT 18
@@ -6692,11 +7041,11 @@
 #define I40E_TPB_REPORT_LL_MEM_DBG_CTL_DONE_SHIFT   31
 #define I40E_TPB_REPORT_LL_MEM_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_TPB_REPORT_LL_MEM_DBG_CTL_DONE_SHIFT)
 
-#define I40E_TPB_REPORT_LL_MEM_DBG_DATA             0x000980D8
+#define I40E_TPB_REPORT_LL_MEM_DBG_DATA             0x000980D8 /* Reset: CORER */
 #define I40E_TPB_REPORT_LL_MEM_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_TPB_REPORT_LL_MEM_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_TPB_REPORT_LL_MEM_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_TPB_REPORT_LL_MEM_STATUS                        0x000980A0
+#define I40E_TPB_REPORT_LL_MEM_STATUS                        0x000980A0 /* Reset: POR */
 #define I40E_TPB_REPORT_LL_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TPB_REPORT_LL_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TPB_REPORT_LL_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TPB_REPORT_LL_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6706,7 +7055,7 @@
 #define I40E_TPB_REPORT_LL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TPB_REPORT_LL_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TPB_REPORT_LL_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TPB_REPORT_MEM_CFG                    0x000980A4
+#define I40E_TPB_REPORT_MEM_CFG                    0x000980A4 /* Reset: POR */
 #define I40E_TPB_REPORT_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TPB_REPORT_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TPB_REPORT_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TPB_REPORT_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6728,7 +7077,7 @@
 #define I40E_TPB_REPORT_MEM_CFG_RM_SHIFT           16
 #define I40E_TPB_REPORT_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TPB_REPORT_MEM_CFG_RM_SHIFT)
 
-#define I40E_TPB_REPORT_MEM_DBG_CTL              0x000980C4
+#define I40E_TPB_REPORT_MEM_DBG_CTL              0x000980C4 /* Reset: CORER */
 #define I40E_TPB_REPORT_MEM_DBG_CTL_ADR_SHIFT    0
 #define I40E_TPB_REPORT_MEM_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_TPB_REPORT_MEM_DBG_CTL_ADR_SHIFT)
 #define I40E_TPB_REPORT_MEM_DBG_CTL_DW_SEL_SHIFT 18
@@ -6738,11 +7087,11 @@
 #define I40E_TPB_REPORT_MEM_DBG_CTL_DONE_SHIFT   31
 #define I40E_TPB_REPORT_MEM_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_TPB_REPORT_MEM_DBG_CTL_DONE_SHIFT)
 
-#define I40E_TPB_REPORT_MEM_DBG_DATA             0x000980DC
+#define I40E_TPB_REPORT_MEM_DBG_DATA             0x000980DC /* Reset: CORER */
 #define I40E_TPB_REPORT_MEM_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_TPB_REPORT_MEM_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_TPB_REPORT_MEM_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_TPB_REPORT_MEM_STATUS                        0x000980A8
+#define I40E_TPB_REPORT_MEM_STATUS                        0x000980A8 /* Reset: POR */
 #define I40E_TPB_REPORT_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TPB_REPORT_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TPB_REPORT_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TPB_REPORT_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6752,7 +7101,7 @@
 #define I40E_TPB_REPORT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TPB_REPORT_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TPB_REPORT_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TPB_RPB_BUFF_MEM_CFG                    0x000980AC
+#define I40E_TPB_RPB_BUFF_MEM_CFG                    0x000980AC /* Reset: POR */
 #define I40E_TPB_RPB_BUFF_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_TPB_RPB_BUFF_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TPB_RPB_BUFF_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_TPB_RPB_BUFF_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -6774,7 +7123,7 @@
 #define I40E_TPB_RPB_BUFF_MEM_CFG_RM_SHIFT           16
 #define I40E_TPB_RPB_BUFF_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_TPB_RPB_BUFF_MEM_CFG_RM_SHIFT)
 
-#define I40E_TPB_RPB_BUFF_MEM_DBG_CTL              0x000980BC
+#define I40E_TPB_RPB_BUFF_MEM_DBG_CTL              0x000980BC /* Reset: CORER */
 #define I40E_TPB_RPB_BUFF_MEM_DBG_CTL_ADR_SHIFT    0
 #define I40E_TPB_RPB_BUFF_MEM_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_TPB_RPB_BUFF_MEM_DBG_CTL_ADR_SHIFT)
 #define I40E_TPB_RPB_BUFF_MEM_DBG_CTL_DW_SEL_SHIFT 18
@@ -6784,11 +7133,11 @@
 #define I40E_TPB_RPB_BUFF_MEM_DBG_CTL_DONE_SHIFT   31
 #define I40E_TPB_RPB_BUFF_MEM_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_TPB_RPB_BUFF_MEM_DBG_CTL_DONE_SHIFT)
 
-#define I40E_TPB_RPB_BUFF_MEM_DBG_DATA             0x000980D0
+#define I40E_TPB_RPB_BUFF_MEM_DBG_DATA             0x000980D0 /* Reset: CORER */
 #define I40E_TPB_RPB_BUFF_MEM_DBG_DATA_RD_DW_SHIFT 0
 #define I40E_TPB_RPB_BUFF_MEM_DBG_DATA_RD_DW_MASK  I40E_MASK(0xFFFFFFFF, I40E_TPB_RPB_BUFF_MEM_DBG_DATA_RD_DW_SHIFT)
 
-#define I40E_TPB_RPB_BUFF_MEM_STATUS                        0x000980B0
+#define I40E_TPB_RPB_BUFF_MEM_STATUS                        0x000980B0 /* Reset: POR */
 #define I40E_TPB_RPB_BUFF_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TPB_RPB_BUFF_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TPB_RPB_BUFF_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_TPB_RPB_BUFF_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -6798,7 +7147,7 @@
 #define I40E_TPB_RPB_BUFF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TPB_RPB_BUFF_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TPB_RPB_BUFF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TSCD_BRANCH_TABLE_CFG                    0x000B2218
+#define I40E_TSCD_BRANCH_TABLE_CFG                    0x000B2218 /* Reset: POR */
 #define I40E_TSCD_BRANCH_TABLE_CFG_ECC_EN_SHIFT       0
 #define I40E_TSCD_BRANCH_TABLE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TSCD_BRANCH_TABLE_CFG_ECC_EN_SHIFT)
 #define I40E_TSCD_BRANCH_TABLE_CFG_ECC_INVERT_1_SHIFT 1
@@ -6820,7 +7169,7 @@
 #define I40E_TSCD_BRANCH_TABLE_CFG_RM_SHIFT           16
 #define I40E_TSCD_BRANCH_TABLE_CFG_RM_MASK            I40E_MASK(0xF, I40E_TSCD_BRANCH_TABLE_CFG_RM_SHIFT)
 
-#define I40E_TSCD_BRANCH_TABLE_STATUS                        0x000B2230
+#define I40E_TSCD_BRANCH_TABLE_STATUS                        0x000B2230 /* Reset: POR */
 #define I40E_TSCD_BRANCH_TABLE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TSCD_BRANCH_TABLE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TSCD_BRANCH_TABLE_STATUS_ECC_ERR_SHIFT)
 #define I40E_TSCD_BRANCH_TABLE_STATUS_ECC_FIX_SHIFT          1
@@ -6830,7 +7179,7 @@
 #define I40E_TSCD_BRANCH_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TSCD_BRANCH_TABLE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TSCD_BRANCH_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TSCD_BW_LIMIT_TABLE_CFG                    0x000B2204
+#define I40E_TSCD_BW_LIMIT_TABLE_CFG                    0x000B2204 /* Reset: POR */
 #define I40E_TSCD_BW_LIMIT_TABLE_CFG_ECC_EN_SHIFT       0
 #define I40E_TSCD_BW_LIMIT_TABLE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TSCD_BW_LIMIT_TABLE_CFG_ECC_EN_SHIFT)
 #define I40E_TSCD_BW_LIMIT_TABLE_CFG_ECC_INVERT_1_SHIFT 1
@@ -6856,7 +7205,7 @@
 #define I40E_TSCD_BW_LIMIT_TABLE_CFG_RM_B_SHIFT         20
 #define I40E_TSCD_BW_LIMIT_TABLE_CFG_RM_B_MASK          I40E_MASK(0xF, I40E_TSCD_BW_LIMIT_TABLE_CFG_RM_B_SHIFT)
 
-#define I40E_TSCD_BW_LIMIT_TABLE_STATUS                        0x000B2228
+#define I40E_TSCD_BW_LIMIT_TABLE_STATUS                        0x000B2228 /* Reset: POR */
 #define I40E_TSCD_BW_LIMIT_TABLE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TSCD_BW_LIMIT_TABLE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TSCD_BW_LIMIT_TABLE_STATUS_ECC_ERR_SHIFT)
 #define I40E_TSCD_BW_LIMIT_TABLE_STATUS_ECC_FIX_SHIFT          1
@@ -6866,15 +7215,15 @@
 #define I40E_TSCD_BW_LIMIT_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TSCD_BW_LIMIT_TABLE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TSCD_BW_LIMIT_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TSCD_ECC_COR_ERR           0x000B223c
+#define I40E_TSCD_ECC_COR_ERR           0x000B223c /* Reset: POR */
 #define I40E_TSCD_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_TSCD_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TSCD_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_TSCD_ECC_UNCOR_ERR           0x000B2238
+#define I40E_TSCD_ECC_UNCOR_ERR           0x000B2238 /* Reset: POR */
 #define I40E_TSCD_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_TSCD_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_TSCD_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_TSCD_NEXT_NODE_TABLE_CFG                    0x000B220C
+#define I40E_TSCD_NEXT_NODE_TABLE_CFG                    0x000B220C /* Reset: POR */
 #define I40E_TSCD_NEXT_NODE_TABLE_CFG_ECC_EN_SHIFT       0
 #define I40E_TSCD_NEXT_NODE_TABLE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TSCD_NEXT_NODE_TABLE_CFG_ECC_EN_SHIFT)
 #define I40E_TSCD_NEXT_NODE_TABLE_CFG_ECC_INVERT_1_SHIFT 1
@@ -6896,7 +7245,7 @@
 #define I40E_TSCD_NEXT_NODE_TABLE_CFG_RM_SHIFT           16
 #define I40E_TSCD_NEXT_NODE_TABLE_CFG_RM_MASK            I40E_MASK(0xF, I40E_TSCD_NEXT_NODE_TABLE_CFG_RM_SHIFT)
 
-#define I40E_TSCD_NEXT_NODE_TABLE_STATUS                        0x000B222c
+#define I40E_TSCD_NEXT_NODE_TABLE_STATUS                        0x000B222c /* Reset: POR */
 #define I40E_TSCD_NEXT_NODE_TABLE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TSCD_NEXT_NODE_TABLE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TSCD_NEXT_NODE_TABLE_STATUS_ECC_ERR_SHIFT)
 #define I40E_TSCD_NEXT_NODE_TABLE_STATUS_ECC_FIX_SHIFT          1
@@ -6906,7 +7255,7 @@
 #define I40E_TSCD_NEXT_NODE_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TSCD_NEXT_NODE_TABLE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TSCD_NEXT_NODE_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TSCD_NODE_TABLE_CFG                    0x000B2210
+#define I40E_TSCD_NODE_TABLE_CFG                    0x000B2210 /* Reset: POR */
 #define I40E_TSCD_NODE_TABLE_CFG_ECC_EN_SHIFT       0
 #define I40E_TSCD_NODE_TABLE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TSCD_NODE_TABLE_CFG_ECC_EN_SHIFT)
 #define I40E_TSCD_NODE_TABLE_CFG_ECC_INVERT_1_SHIFT 1
@@ -6928,7 +7277,7 @@
 #define I40E_TSCD_NODE_TABLE_CFG_RM_SHIFT           16
 #define I40E_TSCD_NODE_TABLE_CFG_RM_MASK            I40E_MASK(0xF, I40E_TSCD_NODE_TABLE_CFG_RM_SHIFT)
 
-#define I40E_TSCD_NODE_TABLE_STATUS                        0x000B2220
+#define I40E_TSCD_NODE_TABLE_STATUS                        0x000B2220 /* Reset: POR */
 #define I40E_TSCD_NODE_TABLE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TSCD_NODE_TABLE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TSCD_NODE_TABLE_STATUS_ECC_ERR_SHIFT)
 #define I40E_TSCD_NODE_TABLE_STATUS_ECC_FIX_SHIFT          1
@@ -6938,7 +7287,7 @@
 #define I40E_TSCD_NODE_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TSCD_NODE_TABLE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TSCD_NODE_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TSCD_RL_MAP_TABLE_CFG                    0x000B2214
+#define I40E_TSCD_RL_MAP_TABLE_CFG                    0x000B2214 /* Reset: POR */
 #define I40E_TSCD_RL_MAP_TABLE_CFG_ECC_EN_SHIFT       0
 #define I40E_TSCD_RL_MAP_TABLE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TSCD_RL_MAP_TABLE_CFG_ECC_EN_SHIFT)
 #define I40E_TSCD_RL_MAP_TABLE_CFG_ECC_INVERT_1_SHIFT 1
@@ -6960,7 +7309,7 @@
 #define I40E_TSCD_RL_MAP_TABLE_CFG_RM_SHIFT           16
 #define I40E_TSCD_RL_MAP_TABLE_CFG_RM_MASK            I40E_MASK(0xF, I40E_TSCD_RL_MAP_TABLE_CFG_RM_SHIFT)
 
-#define I40E_TSCD_RL_MAP_TABLE_STATUS                        0x000B2224
+#define I40E_TSCD_RL_MAP_TABLE_STATUS                        0x000B2224 /* Reset: POR */
 #define I40E_TSCD_RL_MAP_TABLE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TSCD_RL_MAP_TABLE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TSCD_RL_MAP_TABLE_STATUS_ECC_ERR_SHIFT)
 #define I40E_TSCD_RL_MAP_TABLE_STATUS_ECC_FIX_SHIFT          1
@@ -6970,7 +7319,7 @@
 #define I40E_TSCD_RL_MAP_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TSCD_RL_MAP_TABLE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TSCD_RL_MAP_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TSCD_SHARED_BW_LIMIT_TABLE_CFG                    0x000B2200
+#define I40E_TSCD_SHARED_BW_LIMIT_TABLE_CFG                    0x000B2200 /* Reset: POR */
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_CFG_ECC_EN_SHIFT       0
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_TSCD_SHARED_BW_LIMIT_TABLE_CFG_ECC_EN_SHIFT)
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_CFG_ECC_INVERT_1_SHIFT 1
@@ -6992,7 +7341,7 @@
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_CFG_RM_SHIFT           16
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_CFG_RM_MASK            I40E_MASK(0xF, I40E_TSCD_SHARED_BW_LIMIT_TABLE_CFG_RM_SHIFT)
 
-#define I40E_TSCD_SHARED_BW_LIMIT_TABLE_STATUS                        0x000B2234
+#define I40E_TSCD_SHARED_BW_LIMIT_TABLE_STATUS                        0x000B2234 /* Reset: POR */
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_STATUS_ECC_ERR_SHIFT          0
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_TSCD_SHARED_BW_LIMIT_TABLE_STATUS_ECC_ERR_SHIFT)
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_STATUS_ECC_FIX_SHIFT          1
@@ -7002,19 +7351,19 @@
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_TSCD_SHARED_BW_LIMIT_TABLE_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_TSCD_SHARED_BW_LIMIT_TABLE_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_TXDBG_GL_CNTRL                  0x000BC000
+#define I40E_TXDBG_GL_CNTRL                  0x000BC000 /* Reset: CORER */
 #define I40E_TXDBG_GL_CNTRL_TXDBG_MODE_SHIFT 0
 #define I40E_TXDBG_GL_CNTRL_TXDBG_MODE_MASK  I40E_MASK(0x7, I40E_TXDBG_GL_CNTRL_TXDBG_MODE_SHIFT)
 
-#define I40E_TXDBG_RD_ENTITY              0x000BC004
+#define I40E_TXDBG_RD_ENTITY              0x000BC004 /* Reset: CORER */
 #define I40E_TXDBG_RD_ENTITY_RD_LOG_SHIFT 0
 #define I40E_TXDBG_RD_ENTITY_RD_LOG_MASK  I40E_MASK(0xFFFFFFFF, I40E_TXDBG_RD_ENTITY_RD_LOG_SHIFT)
 
-#define I40E_TXDBG_RD_ENTITY_CNTRL                     0x000BC008
+#define I40E_TXDBG_RD_ENTITY_CNTRL                     0x000BC008 /* Reset: CORER */
 #define I40E_TXDBG_RD_ENTITY_CNTRL_RD_ENTITY_NUM_SHIFT 0
 #define I40E_TXDBG_RD_ENTITY_CNTRL_RD_ENTITY_NUM_MASK  I40E_MASK(0xFFF, I40E_TXDBG_RD_ENTITY_CNTRL_RD_ENTITY_NUM_SHIFT)
 
-#define I40E_TXUPDBG_ITR_CAUSE_CTL                      0x000E0018
+#define I40E_TXUPDBG_ITR_CAUSE_CTL                      0x000E0018 /* Reset: CORER */
 #define I40E_TXUPDBG_ITR_CAUSE_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_ITR_CAUSE_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_ITR_CAUSE_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_ITR_CAUSE_CTL_FLOW_ID_SHIFT        1
@@ -7022,7 +7371,7 @@
 #define I40E_TXUPDBG_ITR_CAUSE_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_ITR_CAUSE_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_ITR_CAUSE_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_ITR_DONE_CTL                      0x000E0020
+#define I40E_TXUPDBG_ITR_DONE_CTL                      0x000E0020 /* Reset: CORER */
 #define I40E_TXUPDBG_ITR_DONE_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_ITR_DONE_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_ITR_DONE_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_ITR_DONE_CTL_FLOW_ID_SHIFT        1
@@ -7030,7 +7379,7 @@
 #define I40E_TXUPDBG_ITR_DONE_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_ITR_DONE_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_ITR_DONE_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_ITR_EXP_CTL                      0x000E001C
+#define I40E_TXUPDBG_ITR_EXP_CTL                      0x000E001C /* Reset: CORER */
 #define I40E_TXUPDBG_ITR_EXP_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_ITR_EXP_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_ITR_EXP_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_ITR_EXP_CTL_FLOW_ID_SHIFT        1
@@ -7038,7 +7387,7 @@
 #define I40E_TXUPDBG_ITR_EXP_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_ITR_EXP_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_ITR_EXP_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_MAC0IN_CTL                      0x000E2008
+#define I40E_TXUPDBG_MAC0IN_CTL                      0x000E2008 /* Reset: CORER */
 #define I40E_TXUPDBG_MAC0IN_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_MAC0IN_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_MAC0IN_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_MAC0IN_CTL_FLOW_ID_SHIFT        1
@@ -7046,7 +7395,7 @@
 #define I40E_TXUPDBG_MAC0IN_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_MAC0IN_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_MAC0IN_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_MAC1IN_CTL                      0x000E200C
+#define I40E_TXUPDBG_MAC1IN_CTL                      0x000E200C /* Reset: CORER */
 #define I40E_TXUPDBG_MAC1IN_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_MAC1IN_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_MAC1IN_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_MAC1IN_CTL_FLOW_ID_SHIFT        1
@@ -7054,7 +7403,7 @@
 #define I40E_TXUPDBG_MAC1IN_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_MAC1IN_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_MAC1IN_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_MAC2IN_CTL                      0x000E2010
+#define I40E_TXUPDBG_MAC2IN_CTL                      0x000E2010 /* Reset: CORER */
 #define I40E_TXUPDBG_MAC2IN_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_MAC2IN_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_MAC2IN_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_MAC2IN_CTL_FLOW_ID_SHIFT        1
@@ -7062,7 +7411,7 @@
 #define I40E_TXUPDBG_MAC2IN_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_MAC2IN_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_MAC2IN_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_MAC3IN_CTL                      0x000E2014
+#define I40E_TXUPDBG_MAC3IN_CTL                      0x000E2014 /* Reset: CORER */
 #define I40E_TXUPDBG_MAC3IN_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_MAC3IN_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_MAC3IN_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_MAC3IN_CTL_FLOW_ID_SHIFT        1
@@ -7070,7 +7419,7 @@
 #define I40E_TXUPDBG_MAC3IN_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_MAC3IN_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_MAC3IN_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_MSIX_CTL                      0x000BC00C
+#define I40E_TXUPDBG_MSIX_CTL                      0x000BC00C /* Reset: CORER */
 #define I40E_TXUPDBG_MSIX_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_MSIX_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_MSIX_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_MSIX_CTL_FLOW_ID_SHIFT        1
@@ -7078,7 +7427,7 @@
 #define I40E_TXUPDBG_MSIX_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_MSIX_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_MSIX_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_Q_SCHED_CTL                      0x000E000C
+#define I40E_TXUPDBG_Q_SCHED_CTL                      0x000E000C /* Reset: CORER */
 #define I40E_TXUPDBG_Q_SCHED_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_Q_SCHED_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_Q_SCHED_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_Q_SCHED_CTL_FLOW_ID_SHIFT        1
@@ -7088,7 +7437,7 @@
 #define I40E_TXUPDBG_Q_SCHED_CTL_EVENT_ID_SHIFT       15
 #define I40E_TXUPDBG_Q_SCHED_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_Q_SCHED_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_QG_SCHED_CTL                      0x000E0008
+#define I40E_TXUPDBG_QG_SCHED_CTL                      0x000E0008 /* Reset: CORER */
 #define I40E_TXUPDBG_QG_SCHED_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_QG_SCHED_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_QG_SCHED_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_QG_SCHED_CTL_FLOW_ID_SHIFT        1
@@ -7096,7 +7445,7 @@
 #define I40E_TXUPDBG_QG_SCHED_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_QG_SCHED_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_QG_SCHED_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_TAIL_BUMP_CTL                      0x000E0000
+#define I40E_TXUPDBG_TAIL_BUMP_CTL                      0x000E0000 /* Reset: CORER */
 #define I40E_TXUPDBG_TAIL_BUMP_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_TAIL_BUMP_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_TAIL_BUMP_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_TAIL_BUMP_CTL_FLOW_ID_SHIFT        1
@@ -7104,7 +7453,7 @@
 #define I40E_TXUPDBG_TAIL_BUMP_CTL_EVENT_ID_SHIFT       13
 #define I40E_TXUPDBG_TAIL_BUMP_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_TAIL_BUMP_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_TCBIN_CTL                      0x000E0010
+#define I40E_TXUPDBG_TCBIN_CTL                      0x000E0010 /* Reset: CORER */
 #define I40E_TXUPDBG_TCBIN_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_TCBIN_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_TCBIN_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_TCBIN_CTL_FLOW_ID_SHIFT        1
@@ -7114,7 +7463,7 @@
 #define I40E_TXUPDBG_TCBIN_CTL_EVENT_ID_SHIFT       15
 #define I40E_TXUPDBG_TCBIN_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_TCBIN_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_TDPUIN_CTL                      0x000E2000
+#define I40E_TXUPDBG_TDPUIN_CTL                      0x000E2000 /* Reset: CORER */
 #define I40E_TXUPDBG_TDPUIN_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_TDPUIN_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_TDPUIN_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_TDPUIN_CTL_FLOW_ID_SHIFT        1
@@ -7124,7 +7473,7 @@
 #define I40E_TXUPDBG_TDPUIN_CTL_EVENT_ID_SHIFT       15
 #define I40E_TXUPDBG_TDPUIN_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_TDPUIN_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_TLAN2_CTL                      0x000E0014
+#define I40E_TXUPDBG_TLAN2_CTL                      0x000E0014 /* Reset: CORER */
 #define I40E_TXUPDBG_TLAN2_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_TLAN2_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_TLAN2_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_TLAN2_CTL_FLOW_ID_SHIFT        1
@@ -7136,7 +7485,7 @@
 #define I40E_TXUPDBG_TLAN2_CTL_EVENT_ID_B_SHIFT     18
 #define I40E_TXUPDBG_TLAN2_CTL_EVENT_ID_B_MASK      I40E_MASK(0x7, I40E_TXUPDBG_TLAN2_CTL_EVENT_ID_B_SHIFT)
 
-#define I40E_TXUPDBG_TPBIN_CTL                      0x000E2004
+#define I40E_TXUPDBG_TPBIN_CTL                      0x000E2004 /* Reset: CORER */
 #define I40E_TXUPDBG_TPBIN_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_TPBIN_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_TPBIN_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_TPBIN_CTL_FLOW_ID_SHIFT        1
@@ -7146,7 +7495,7 @@
 #define I40E_TXUPDBG_TPBIN_CTL_EVENT_ID_SHIFT       15
 #define I40E_TXUPDBG_TPBIN_CTL_EVENT_ID_MASK        I40E_MASK(0x7, I40E_TXUPDBG_TPBIN_CTL_EVENT_ID_SHIFT)
 
-#define I40E_TXUPDBG_WA_CTL                      0x000E0004
+#define I40E_TXUPDBG_WA_CTL                      0x000E0004 /* Reset: CORER */
 #define I40E_TXUPDBG_WA_CTL_FILTER_FLOW_EN_SHIFT 0
 #define I40E_TXUPDBG_WA_CTL_FILTER_FLOW_EN_MASK  I40E_MASK(0x1, I40E_TXUPDBG_WA_CTL_FILTER_FLOW_EN_SHIFT)
 #define I40E_TXUPDBG_WA_CTL_FLOW_ID_SHIFT        1
@@ -7156,7 +7505,7 @@
 #define I40E_TXUPDBG_WA_CTL_EVENT_ID_B_SHIFT     16
 #define I40E_TXUPDBG_WA_CTL_EVENT_ID_B_MASK      I40E_MASK(0x7, I40E_TXUPDBG_WA_CTL_EVENT_ID_B_SHIFT)
 
-#define I40E_WAIT_CMD_BUF_MEM_CFG                    0x000AE088
+#define I40E_WAIT_CMD_BUF_MEM_CFG                    0x000AE088 /* Reset: POR */
 #define I40E_WAIT_CMD_BUF_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_WAIT_CMD_BUF_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_WAIT_CMD_BUF_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_WAIT_CMD_BUF_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -7178,7 +7527,7 @@
 #define I40E_WAIT_CMD_BUF_MEM_CFG_RM_SHIFT           16
 #define I40E_WAIT_CMD_BUF_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_WAIT_CMD_BUF_MEM_CFG_RM_SHIFT)
 
-#define I40E_WAIT_CMD_BUF_MEM_STATUS                        0x000AE08C
+#define I40E_WAIT_CMD_BUF_MEM_STATUS                        0x000AE08C /* Reset: POR */
 #define I40E_WAIT_CMD_BUF_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_WAIT_CMD_BUF_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_WAIT_CMD_BUF_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_WAIT_CMD_BUF_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -7188,7 +7537,7 @@
 #define I40E_WAIT_CMD_BUF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_WAIT_CMD_BUF_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_WAIT_CMD_BUF_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_WAIT_CMD_MNG_MEM_CFG                    0x000AE084
+#define I40E_WAIT_CMD_MNG_MEM_CFG                    0x000AE084 /* Reset: POR */
 #define I40E_WAIT_CMD_MNG_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_WAIT_CMD_MNG_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_WAIT_CMD_MNG_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_WAIT_CMD_MNG_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -7210,7 +7559,7 @@
 #define I40E_WAIT_CMD_MNG_MEM_CFG_RM_SHIFT           16
 #define I40E_WAIT_CMD_MNG_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_WAIT_CMD_MNG_MEM_CFG_RM_SHIFT)
 
-#define I40E_WAIT_CMD_MNG_MEM_STATUS                        0x000AE090
+#define I40E_WAIT_CMD_MNG_MEM_STATUS                        0x000AE090 /* Reset: POR */
 #define I40E_WAIT_CMD_MNG_MEM_STATUS_ECC_ERR_SHIFT          0
 #define I40E_WAIT_CMD_MNG_MEM_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_WAIT_CMD_MNG_MEM_STATUS_ECC_ERR_SHIFT)
 #define I40E_WAIT_CMD_MNG_MEM_STATUS_ECC_FIX_SHIFT          1
@@ -7220,15 +7569,15 @@
 #define I40E_WAIT_CMD_MNG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_WAIT_CMD_MNG_MEM_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_WAIT_CMD_MNG_MEM_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_WUC_ECC_COR_ERR           0x0006E8AC
+#define I40E_WUC_ECC_COR_ERR           0x0006E8AC /* Reset: POR */
 #define I40E_WUC_ECC_COR_ERR_CNT_SHIFT 0
 #define I40E_WUC_ECC_COR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_WUC_ECC_COR_ERR_CNT_SHIFT)
 
-#define I40E_WUC_ECC_UNCOR_ERR           0x0006E8A8
+#define I40E_WUC_ECC_UNCOR_ERR           0x0006E8A8 /* Reset: POR */
 #define I40E_WUC_ECC_UNCOR_ERR_CNT_SHIFT 0
 #define I40E_WUC_ECC_UNCOR_ERR_CNT_MASK  I40E_MASK(0xFFF, I40E_WUC_ECC_UNCOR_ERR_CNT_SHIFT)
 
-#define I40E_WUC_SP_FLEX_CFG                    0x0006E898
+#define I40E_WUC_SP_FLEX_CFG                    0x0006E898 /* Reset: POR */
 #define I40E_WUC_SP_FLEX_CFG_ECC_EN_SHIFT       0
 #define I40E_WUC_SP_FLEX_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_WUC_SP_FLEX_CFG_ECC_EN_SHIFT)
 #define I40E_WUC_SP_FLEX_CFG_ECC_INVERT_1_SHIFT 1
@@ -7250,7 +7599,7 @@
 #define I40E_WUC_SP_FLEX_CFG_RM_SHIFT           16
 #define I40E_WUC_SP_FLEX_CFG_RM_MASK            I40E_MASK(0xF, I40E_WUC_SP_FLEX_CFG_RM_SHIFT)
 
-#define I40E_WUC_SP_FLEX_MASK_MEM_CFG                    0x0006E890
+#define I40E_WUC_SP_FLEX_MASK_MEM_CFG                    0x0006E890 /* Reset: POR */
 #define I40E_WUC_SP_FLEX_MASK_MEM_CFG_ECC_EN_SHIFT       0
 #define I40E_WUC_SP_FLEX_MASK_MEM_CFG_ECC_EN_MASK        I40E_MASK(0x1, I40E_WUC_SP_FLEX_MASK_MEM_CFG_ECC_EN_SHIFT)
 #define I40E_WUC_SP_FLEX_MASK_MEM_CFG_ECC_INVERT_1_SHIFT 1
@@ -7272,7 +7621,7 @@
 #define I40E_WUC_SP_FLEX_MASK_MEM_CFG_RM_SHIFT           16
 #define I40E_WUC_SP_FLEX_MASK_MEM_CFG_RM_MASK            I40E_MASK(0xF, I40E_WUC_SP_FLEX_MASK_MEM_CFG_RM_SHIFT)
 
-#define I40E_WUC_SP_FLEX_MASK_STATUS                        0x0006E894
+#define I40E_WUC_SP_FLEX_MASK_STATUS                        0x0006E894 /* Reset: POR */
 #define I40E_WUC_SP_FLEX_MASK_STATUS_ECC_ERR_SHIFT          0
 #define I40E_WUC_SP_FLEX_MASK_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_WUC_SP_FLEX_MASK_STATUS_ECC_ERR_SHIFT)
 #define I40E_WUC_SP_FLEX_MASK_STATUS_ECC_FIX_SHIFT          1
@@ -7282,7 +7631,7 @@
 #define I40E_WUC_SP_FLEX_MASK_STATUS_GLOBAL_INIT_DONE_SHIFT 3
 #define I40E_WUC_SP_FLEX_MASK_STATUS_GLOBAL_INIT_DONE_MASK  I40E_MASK(0x1, I40E_WUC_SP_FLEX_MASK_STATUS_GLOBAL_INIT_DONE_SHIFT)
 
-#define I40E_WUC_SP_FLEX_STATUS                        0x0006E89C
+#define I40E_WUC_SP_FLEX_STATUS                        0x0006E89C /* Reset: POR */
 #define I40E_WUC_SP_FLEX_STATUS_ECC_ERR_SHIFT          0
 #define I40E_WUC_SP_FLEX_STATUS_ECC_ERR_MASK           I40E_MASK(0x1, I40E_WUC_SP_FLEX_STATUS_ECC_ERR_SHIFT)
 #define I40E_WUC_SP_FLEX_STATUS_ECC_FIX_SHIFT          1
@@ -7296,7 +7645,7 @@
 
 /* PF - Interrupt Registers */
 
-#define I40E_GLINT_CTL                        0x0003F800
+#define I40E_GLINT_CTL                        0x0003F800 /* Reset: CORER */
 #define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT 0
 #define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK  I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT)
 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1
@@ -7304,7 +7653,7 @@
 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT   2
 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK    I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT)
 
-#define I40E_PFINT_ITR0_STAT(_i)              (0x00038200 + ((_i) * 128)) /* _i=0...2 */
+#define I40E_PFINT_ITR0_STAT(_i)              (0x00038200 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */
 #define I40E_PFINT_ITR0_STAT_MAX_INDEX        2
 #define I40E_PFINT_ITR0_STAT_ITR_EXPIRE_SHIFT 0
 #define I40E_PFINT_ITR0_STAT_ITR_EXPIRE_MASK  I40E_MASK(0x1, I40E_PFINT_ITR0_STAT_ITR_EXPIRE_SHIFT)
@@ -7313,7 +7662,7 @@
 #define I40E_PFINT_ITR0_STAT_ITR_TIME_SHIFT   2
 #define I40E_PFINT_ITR0_STAT_ITR_TIME_MASK    I40E_MASK(0xFFF, I40E_PFINT_ITR0_STAT_ITR_TIME_SHIFT)
 
-#define I40E_PFINT_ITRN_STAT(_i, _INTPF)       (0x00032000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */
+#define I40E_PFINT_ITRN_STAT(_i, _INTPF)       (0x00032000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */
 #define I40E_PFINT_ITRN_STAT_MAX_INDEX        2
 #define I40E_PFINT_ITRN_STAT_ITR_EXPIRE_SHIFT 0
 #define I40E_PFINT_ITRN_STAT_ITR_EXPIRE_MASK  I40E_MASK(0x1, I40E_PFINT_ITRN_STAT_ITR_EXPIRE_SHIFT)
@@ -7322,20 +7671,20 @@
 #define I40E_PFINT_ITRN_STAT_ITR_TIME_SHIFT   2
 #define I40E_PFINT_ITRN_STAT_ITR_TIME_MASK    I40E_MASK(0xFFF, I40E_PFINT_ITRN_STAT_ITR_TIME_SHIFT)
 
-#define I40E_PFINT_RATE0_STAT                  0x00038600
+#define I40E_PFINT_RATE0_STAT                  0x00038600 /* Reset: PFR */
 #define I40E_PFINT_RATE0_STAT_CREDIT_SHIFT     0
 #define I40E_PFINT_RATE0_STAT_CREDIT_MASK      I40E_MASK(0xF, I40E_PFINT_RATE0_STAT_CREDIT_SHIFT)
 #define I40E_PFINT_RATE0_STAT_INTRL_TIME_SHIFT 4
 #define I40E_PFINT_RATE0_STAT_INTRL_TIME_MASK  I40E_MASK(0x3F, I40E_PFINT_RATE0_STAT_INTRL_TIME_SHIFT)
 
-#define I40E_PFINT_RATEN_STAT(_INTPF)          (0x00036000 + ((_INTPF) * 4)) /* _i=0...511 */
+#define I40E_PFINT_RATEN_STAT(_INTPF)          (0x00036000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
 #define I40E_PFINT_RATEN_STAT_MAX_INDEX        511
 #define I40E_PFINT_RATEN_STAT_CREDIT_SHIFT     0
 #define I40E_PFINT_RATEN_STAT_CREDIT_MASK      I40E_MASK(0xF, I40E_PFINT_RATEN_STAT_CREDIT_SHIFT)
 #define I40E_PFINT_RATEN_STAT_INTRL_TIME_SHIFT 4
 #define I40E_PFINT_RATEN_STAT_INTRL_TIME_MASK  I40E_MASK(0x3F, I40E_PFINT_RATEN_STAT_INTRL_TIME_SHIFT)
 
-#define I40E_VFINT_ITR0_STAT(_i, _VF)          (0x00029000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */
+#define I40E_VFINT_ITR0_STAT(_i, _VF)          (0x00029000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */
 #define I40E_VFINT_ITR0_STAT_MAX_INDEX        2
 #define I40E_VFINT_ITR0_STAT_ITR_EXPIRE_SHIFT 0
 #define I40E_VFINT_ITR0_STAT_ITR_EXPIRE_MASK  I40E_MASK(0x1, I40E_VFINT_ITR0_STAT_ITR_EXPIRE_SHIFT)
@@ -7344,7 +7693,7 @@
 #define I40E_VFINT_ITR0_STAT_ITR_TIME_SHIFT   2
 #define I40E_VFINT_ITR0_STAT_ITR_TIME_MASK    I40E_MASK(0xFFF, I40E_VFINT_ITR0_STAT_ITR_TIME_SHIFT)
 
-#define I40E_VFINT_ITRN_STAT(_i, _INTVF)       (0x00022000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */
+#define I40E_VFINT_ITRN_STAT(_i, _INTVF)       (0x00022000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */
 #define I40E_VFINT_ITRN_STAT_MAX_INDEX        2
 #define I40E_VFINT_ITRN_STAT_ITR_EXPIRE_SHIFT 0
 #define I40E_VFINT_ITRN_STAT_ITR_EXPIRE_MASK  I40E_MASK(0x1, I40E_VFINT_ITRN_STAT_ITR_EXPIRE_SHIFT)
@@ -7353,14 +7702,14 @@
 #define I40E_VFINT_ITRN_STAT_ITR_TIME_SHIFT   2
 #define I40E_VFINT_ITRN_STAT_ITR_TIME_MASK    I40E_MASK(0xFFF, I40E_VFINT_ITRN_STAT_ITR_TIME_SHIFT)
 
-#define I40E_VFINT_RATE0_STAT(_VF)             (0x0002B000 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VFINT_RATE0_STAT(_VF)             (0x0002B000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
 #define I40E_VFINT_RATE0_STAT_MAX_INDEX        127
 #define I40E_VFINT_RATE0_STAT_CREDIT_SHIFT     0
 #define I40E_VFINT_RATE0_STAT_CREDIT_MASK      I40E_MASK(0xF, I40E_VFINT_RATE0_STAT_CREDIT_SHIFT)
 #define I40E_VFINT_RATE0_STAT_INTRL_TIME_SHIFT 4
 #define I40E_VFINT_RATE0_STAT_INTRL_TIME_MASK  I40E_MASK(0x3F, I40E_VFINT_RATE0_STAT_INTRL_TIME_SHIFT)
 
-#define I40E_VFINT_RATEN_STAT(_INTVF)          (0x00026000 + ((_INTVF) * 4)) /* _i=0...511 */
+#define I40E_VFINT_RATEN_STAT(_INTVF)          (0x00026000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
 #define I40E_VFINT_RATEN_STAT_MAX_INDEX        511
 #define I40E_VFINT_RATEN_STAT_CREDIT_SHIFT     0
 #define I40E_VFINT_RATEN_STAT_CREDIT_MASK      I40E_MASK(0xF, I40E_VFINT_RATEN_STAT_CREDIT_SHIFT)
@@ -7369,12 +7718,12 @@
 
 /* PF - LAN Transmit Receive Registers */
 
-#define I40E_GLLAN_PF_RECIPE(_i)          (0x0012A5E0 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLLAN_PF_RECIPE(_i)          (0x0012A5E0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLLAN_PF_RECIPE_MAX_INDEX    15
 #define I40E_GLLAN_PF_RECIPE_RECIPE_SHIFT 0
 #define I40E_GLLAN_PF_RECIPE_RECIPE_MASK  I40E_MASK(0x3, I40E_GLLAN_PF_RECIPE_RECIPE_SHIFT)
 
-#define I40E_GLLAN_RCTL_1                       0x0012A504
+#define I40E_GLLAN_RCTL_1                       0x0012A504 /* Reset: CORER */
 #define I40E_GLLAN_RCTL_1_RXMAX_EXPANSION_SHIFT 12
 #define I40E_GLLAN_RCTL_1_RXMAX_EXPANSION_MASK  I40E_MASK(0xF, I40E_GLLAN_RCTL_1_RXMAX_EXPANSION_SHIFT)
 #define I40E_GLLAN_RCTL_1_RXDWBCTL_SHIFT        16
@@ -7386,13 +7735,13 @@
 #define I40E_GLLAN_RCTL_1_RXDATAWRROEN_SHIFT    19
 #define I40E_GLLAN_RCTL_1_RXDATAWRROEN_MASK     I40E_MASK(0x1, I40E_GLLAN_RCTL_1_RXDATAWRROEN_SHIFT)
 
-#define I40E_GLLAN_TCTL_0                    0x000E6488
+#define I40E_GLLAN_TCTL_0                    0x000E6488 /* Reset: CORER */
 #define I40E_GLLAN_TCTL_0_TXLANTH_SHIFT      0
 #define I40E_GLLAN_TCTL_0_TXLANTH_MASK       I40E_MASK(0x3F, I40E_GLLAN_TCTL_0_TXLANTH_SHIFT)
 #define I40E_GLLAN_TCTL_0_TXDESCRDROEN_SHIFT 6
 #define I40E_GLLAN_TCTL_0_TXDESCRDROEN_MASK  I40E_MASK(0x1, I40E_GLLAN_TCTL_0_TXDESCRDROEN_SHIFT)
 
-#define I40E_GLLAN_TCTL_1                        0x000442F0
+#define I40E_GLLAN_TCTL_1                        0x000442F0 /* Reset: CORER */
 #define I40E_GLLAN_TCTL_1_TXMAX_EXPANSION_SHIFT  0
 #define I40E_GLLAN_TCTL_1_TXMAX_EXPANSION_MASK   I40E_MASK(0xF, I40E_GLLAN_TCTL_1_TXMAX_EXPANSION_SHIFT)
 #define I40E_GLLAN_TCTL_1_TXDATARDROEN_SHIFT     4
@@ -7414,7 +7763,7 @@
 #define I40E_GLLAN_TCTL_1_DBG_ECO_SHIFT          24
 #define I40E_GLLAN_TCTL_1_DBG_ECO_MASK           I40E_MASK(0xFF, I40E_GLLAN_TCTL_1_DBG_ECO_SHIFT)
 
-#define I40E_GLLAN_TCTL_2                       0x000AE080
+#define I40E_GLLAN_TCTL_2                       0x000AE080 /* Reset: CORER */
 #define I40E_GLLAN_TCTL_2_TXMAX_EXPANSION_SHIFT 0
 #define I40E_GLLAN_TCTL_2_TXMAX_EXPANSION_MASK  I40E_MASK(0xF, I40E_GLLAN_TCTL_2_TXMAX_EXPANSION_SHIFT)
 #define I40E_GLLAN_TCTL_2_STAT_DBG_ADDR_SHIFT   4
@@ -7424,60 +7773,60 @@
 #define I40E_GLLAN_TCTL_2_ECO_SHIFT             12
 #define I40E_GLLAN_TCTL_2_ECO_MASK              I40E_MASK(0xFFFFF, I40E_GLLAN_TCTL_2_ECO_SHIFT)
 
-#define I40E_GLLAN_TXEMP_EN                 0x000AE0AC
+#define I40E_GLLAN_TXEMP_EN                 0x000AE0AC /* Reset: CORER */
 #define I40E_GLLAN_TXEMP_EN_TXHOST_EN_SHIFT 0
 #define I40E_GLLAN_TXEMP_EN_TXHOST_EN_MASK  I40E_MASK(0x1, I40E_GLLAN_TXEMP_EN_TXHOST_EN_SHIFT)
 
-#define I40E_GLLAN_TXHOST_EN                 0x000A2208
+#define I40E_GLLAN_TXHOST_EN                 0x000A2208 /* Reset: CORER */
 #define I40E_GLLAN_TXHOST_EN_TXHOST_EN_SHIFT 0
 #define I40E_GLLAN_TXHOST_EN_TXHOST_EN_MASK  I40E_MASK(0x1, I40E_GLLAN_TXHOST_EN_TXHOST_EN_SHIFT)
 
-#define I40E_GLRCU_INDIRECT_ADDRESS                              0x001C0AA4
+#define I40E_GLRCU_INDIRECT_ADDRESS                              0x001C0AA4 /* Reset: CORER */
 #define I40E_GLRCU_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT 0
 #define I40E_GLRCU_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_MASK  I40E_MASK(0xFFFF, I40E_GLRCU_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT)
 
-#define I40E_GLRCU_INDIRECT_DATA(_i)                       (0x001C0AA8 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GLRCU_INDIRECT_DATA(_i)                       (0x001C0AA8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GLRCU_INDIRECT_DATA_MAX_INDEX                 1
 #define I40E_GLRCU_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT 0
 #define I40E_GLRCU_INDIRECT_DATA_GLRCU_INDIRECT_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCU_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT)
 
-#define I40E_GLRCU_LB_INDIRECT_ADDRESS                              0x00269BD4
+#define I40E_GLRCU_LB_INDIRECT_ADDRESS                              0x00269BD4 /* Reset: CORER */
 #define I40E_GLRCU_LB_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT 0
 #define I40E_GLRCU_LB_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_MASK  I40E_MASK(0xFFFF, I40E_GLRCU_LB_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT)
 
-#define I40E_GLRCU_LB_INDIRECT_DATA(_i)                       (0x00269898 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLRCU_LB_INDIRECT_DATA(_i)                       (0x00269898 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLRCU_LB_INDIRECT_DATA_MAX_INDEX                 3
 #define I40E_GLRCU_LB_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT 0
 #define I40E_GLRCU_LB_INDIRECT_DATA_GLRCU_INDIRECT_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCU_LB_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT)
 
-#define I40E_GLRCU_RX_INDIRECT_ADDRESS                              0x00269BCC
+#define I40E_GLRCU_RX_INDIRECT_ADDRESS                              0x00269BCC /* Reset: CORER */
 #define I40E_GLRCU_RX_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT 0
 #define I40E_GLRCU_RX_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_MASK  I40E_MASK(0xFFFF, I40E_GLRCU_RX_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT)
 
-#define I40E_GLRCU_RX_INDIRECT_DATA(_i)                       (0x00269888 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLRCU_RX_INDIRECT_DATA(_i)                       (0x00269888 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLRCU_RX_INDIRECT_DATA_MAX_INDEX                 3
 #define I40E_GLRCU_RX_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT 0
 #define I40E_GLRCU_RX_INDIRECT_DATA_GLRCU_INDIRECT_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRCU_RX_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT)
 
-#define I40E_GLRDPU_INDIRECT_ADDRESS                              0x00051040
+#define I40E_GLRDPU_INDIRECT_ADDRESS                              0x00051040 /* Reset: CORER */
 #define I40E_GLRDPU_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT 0
 #define I40E_GLRDPU_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_MASK  I40E_MASK(0xFFFF, I40E_GLRDPU_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT)
 
-#define I40E_GLRDPU_INDIRECT_DATA(_i)                       (0x00051044 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLRDPU_INDIRECT_DATA(_i)                       (0x00051044 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLRDPU_INDIRECT_DATA_MAX_INDEX                 3
 #define I40E_GLRDPU_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT 0
 #define I40E_GLRDPU_INDIRECT_DATA_GLRCU_INDIRECT_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLRDPU_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT)
 
-#define I40E_GLTDPU_INDIRECT_ADDRESS                              0x00044264
+#define I40E_GLTDPU_INDIRECT_ADDRESS                              0x00044264 /* Reset: CORER */
 #define I40E_GLTDPU_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT 0
 #define I40E_GLTDPU_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_MASK  I40E_MASK(0xFFFF, I40E_GLTDPU_INDIRECT_ADDRESS_GLRCU_INDIRECT_ADDRESS_SHIFT)
 
-#define I40E_GLTDPU_INDIRECT_DATA(_i)                       (0x00044268 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLTDPU_INDIRECT_DATA(_i)                       (0x00044268 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLTDPU_INDIRECT_DATA_MAX_INDEX                 3
 #define I40E_GLTDPU_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT 0
 #define I40E_GLTDPU_INDIRECT_DATA_GLRCU_INDIRECT_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLTDPU_INDIRECT_DATA_GLRCU_INDIRECT_DATA_SHIFT)
 
-#define I40E_GLTLAN_MIN_MAX_MSS             0x000E64dC
+#define I40E_GLTLAN_MIN_MAX_MSS             0x000E64dC /* Reset: CORER */
 #define I40E_GLTLAN_MIN_MAX_MSS_MAHDL_SHIFT 0
 #define I40E_GLTLAN_MIN_MAX_MSS_MAHDL_MASK  I40E_MASK(0x3FFF, I40E_GLTLAN_MIN_MAX_MSS_MAHDL_SHIFT)
 #define I40E_GLTLAN_MIN_MAX_MSS_MIHDL_SHIFT 16
@@ -7485,7 +7834,7 @@
 #define I40E_GLTLAN_MIN_MAX_MSS_RSV_SHIFT   26
 #define I40E_GLTLAN_MIN_MAX_MSS_RSV_MASK    I40E_MASK(0x3F, I40E_GLTLAN_MIN_MAX_MSS_RSV_SHIFT)
 
-#define I40E_GLTLAN_MIN_MAX_PKT             0x000E64d8
+#define I40E_GLTLAN_MIN_MAX_PKT             0x000E64DC /* Reset: CORER */
 #define I40E_GLTLAN_MIN_MAX_PKT_MAHDL_SHIFT 0
 #define I40E_GLTLAN_MIN_MAX_PKT_MAHDL_MASK  I40E_MASK(0x3FFF, I40E_GLTLAN_MIN_MAX_PKT_MAHDL_SHIFT)
 #define I40E_GLTLAN_MIN_MAX_PKT_MIHDL_SHIFT 16
@@ -7493,7 +7842,7 @@
 #define I40E_GLTLAN_MIN_MAX_PKT_RSV_SHIFT   22
 #define I40E_GLTLAN_MIN_MAX_PKT_RSV_MASK    I40E_MASK(0x3FF, I40E_GLTLAN_MIN_MAX_PKT_RSV_SHIFT)
 
-#define I40E_PF_VT_PFALLOC_RLAN               0x0012A480
+#define I40E_PF_VT_PFALLOC_RLAN               0x0012A480 /* Reset: CORER */
 #define I40E_PF_VT_PFALLOC_RLAN_FIRSTVF_SHIFT 0
 #define I40E_PF_VT_PFALLOC_RLAN_FIRSTVF_MASK  I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_RLAN_FIRSTVF_SHIFT)
 #define I40E_PF_VT_PFALLOC_RLAN_LASTVF_SHIFT  8
@@ -7501,7 +7850,7 @@
 #define I40E_PF_VT_PFALLOC_RLAN_VALID_SHIFT   31
 #define I40E_PF_VT_PFALLOC_RLAN_VALID_MASK    I40E_MASK(0x1, I40E_PF_VT_PFALLOC_RLAN_VALID_SHIFT)
 
-#define I40E_PFLAN_QALLOC_CSR              0x00078E00
+#define I40E_PFLAN_QALLOC_CSR              0x00078E00 /* Reset: CORER */
 #define I40E_PFLAN_QALLOC_CSR_FIRSTQ_SHIFT 0
 #define I40E_PFLAN_QALLOC_CSR_FIRSTQ_MASK  I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_CSR_FIRSTQ_SHIFT)
 #define I40E_PFLAN_QALLOC_CSR_LASTQ_SHIFT  16
@@ -7509,7 +7858,7 @@
 #define I40E_PFLAN_QALLOC_CSR_VALID_SHIFT  31
 #define I40E_PFLAN_QALLOC_CSR_VALID_MASK   I40E_MASK(0x1, I40E_PFLAN_QALLOC_CSR_VALID_SHIFT)
 
-#define I40E_PFLAN_QALLOC_INT              0x0003F000
+#define I40E_PFLAN_QALLOC_INT              0x0003F000 /* Reset: CORER */
 #define I40E_PFLAN_QALLOC_INT_FIRSTQ_SHIFT 0
 #define I40E_PFLAN_QALLOC_INT_FIRSTQ_MASK  I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_INT_FIRSTQ_SHIFT)
 #define I40E_PFLAN_QALLOC_INT_LASTQ_SHIFT  16
@@ -7517,7 +7866,7 @@
 #define I40E_PFLAN_QALLOC_INT_VALID_SHIFT  31
 #define I40E_PFLAN_QALLOC_INT_VALID_MASK   I40E_MASK(0x1, I40E_PFLAN_QALLOC_INT_VALID_SHIFT)
 
-#define I40E_PFLAN_QALLOC_PMAT              0x000C0600
+#define I40E_PFLAN_QALLOC_PMAT              0x000C0600 /* Reset: CORER */
 #define I40E_PFLAN_QALLOC_PMAT_FIRSTQ_SHIFT 0
 #define I40E_PFLAN_QALLOC_PMAT_FIRSTQ_MASK  I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_PMAT_FIRSTQ_SHIFT)
 #define I40E_PFLAN_QALLOC_PMAT_LASTQ_SHIFT  16
@@ -7525,7 +7874,7 @@
 #define I40E_PFLAN_QALLOC_PMAT_VALID_SHIFT  31
 #define I40E_PFLAN_QALLOC_PMAT_VALID_MASK   I40E_MASK(0x1, I40E_PFLAN_QALLOC_PMAT_VALID_SHIFT)
 
-#define I40E_PFLAN_QALLOC_RCB              0x00122080
+#define I40E_PFLAN_QALLOC_RCB              0x00122080 /* Reset: CORER */
 #define I40E_PFLAN_QALLOC_RCB_FIRSTQ_SHIFT 0
 #define I40E_PFLAN_QALLOC_RCB_FIRSTQ_MASK  I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_RCB_FIRSTQ_SHIFT)
 #define I40E_PFLAN_QALLOC_RCB_LASTQ_SHIFT  16
@@ -7533,7 +7882,7 @@
 #define I40E_PFLAN_QALLOC_RCB_VALID_SHIFT  31
 #define I40E_PFLAN_QALLOC_RCB_VALID_MASK   I40E_MASK(0x1, I40E_PFLAN_QALLOC_RCB_VALID_SHIFT)
 
-#define I40E_PFLAN_QALLOC_RCU              0x00246780
+#define I40E_PFLAN_QALLOC_RCU              0x00246780 /* Reset: CORER */
 #define I40E_PFLAN_QALLOC_RCU_FIRSTQ_SHIFT 0
 #define I40E_PFLAN_QALLOC_RCU_FIRSTQ_MASK  I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_RCU_FIRSTQ_SHIFT)
 #define I40E_PFLAN_QALLOC_RCU_LASTQ_SHIFT  16
@@ -7541,19 +7890,27 @@
 #define I40E_PFLAN_QALLOC_RCU_VALID_SHIFT  31
 #define I40E_PFLAN_QALLOC_RCU_VALID_MASK   I40E_MASK(0x1, I40E_PFLAN_QALLOC_RCU_VALID_SHIFT)
 
-#define I40E_PRTLAN_RXEMP_EN                 0x001E4780
+#define I40E_PRTLAN_RXEMP_EN                 0x001E4780 /* Reset: GLOBR */
 #define I40E_PRTLAN_RXEMP_EN_RXHOST_EN_SHIFT 0
 #define I40E_PRTLAN_RXEMP_EN_RXHOST_EN_MASK  I40E_MASK(0x1, I40E_PRTLAN_RXEMP_EN_RXHOST_EN_SHIFT)
 
 /* PF - MAC Registers  */
 
-#define I40E_PRTDCB_MPVCTL            0x001E2460
+#define I40E_PRTDCB_MPVCTL            0x001E2460 /* Reset: GLOBR */
 #define I40E_PRTDCB_MPVCTL_PFCV_SHIFT 0
 #define I40E_PRTDCB_MPVCTL_PFCV_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_MPVCTL_PFCV_SHIFT)
 #define I40E_PRTDCB_MPVCTL_RFCV_SHIFT 16
 #define I40E_PRTDCB_MPVCTL_RFCV_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_MPVCTL_RFCV_SHIFT)
 
-#define I40E_PRTMAC_HLCTL                     0x001E2000
+#define I40E_PRTMAC_AN_LP_STATUS1                      0x0008C680 /* Reset: GLOBR */
+#define I40E_PRTMAC_AN_LP_STATUS1_LP_AN_PAGE_LOW_SHIFT 0
+#define I40E_PRTMAC_AN_LP_STATUS1_LP_AN_PAGE_LOW_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_AN_LP_STATUS1_LP_AN_PAGE_LOW_SHIFT)
+#define I40E_PRTMAC_AN_LP_STATUS1_AN_ARB_STATE_SHIFT   16
+#define I40E_PRTMAC_AN_LP_STATUS1_AN_ARB_STATE_MASK    I40E_MASK(0xF, I40E_PRTMAC_AN_LP_STATUS1_AN_ARB_STATE_SHIFT)
+#define I40E_PRTMAC_AN_LP_STATUS1_RSVD_SHIFT           20
+#define I40E_PRTMAC_AN_LP_STATUS1_RSVD_MASK            I40E_MASK(0xFFF, I40E_PRTMAC_AN_LP_STATUS1_RSVD_SHIFT)
+
+#define I40E_PRTMAC_HLCTL                     0x001E2000 /* Reset: GLOBR */
 #define I40E_PRTMAC_HLCTL_APPEND_CRC_SHIFT    0
 #define I40E_PRTMAC_HLCTL_APPEND_CRC_MASK     I40E_MASK(0x1, I40E_PRTMAC_HLCTL_APPEND_CRC_SHIFT)
 #define I40E_PRTMAC_HLCTL_RXCRCSTRP_SHIFT     1
@@ -7601,7 +7958,7 @@
 #define I40E_PRTMAC_HLCTL_RXPADSTRIPEN_SHIFT  28
 #define I40E_PRTMAC_HLCTL_RXPADSTRIPEN_MASK   I40E_MASK(0x1, I40E_PRTMAC_HLCTL_RXPADSTRIPEN_SHIFT)
 
-#define I40E_PRTMAC_HLCTLA                     0x001E4760
+#define I40E_PRTMAC_HLCTLA                     0x001E4760 /* Reset: GLOBR */
 #define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT  0
 #define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_MASK   I40E_MASK(0x1, I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT)
 #define I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_SHIFT  1
@@ -7613,7 +7970,7 @@
 #define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT 7
 #define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_MASK  I40E_MASK(0x1, I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT)
 
-#define I40E_PRTMAC_HLSTA                    0x001E2020
+#define I40E_PRTMAC_HLSTA                    0x001E2020 /* Reset: GLOBR */
 #define I40E_PRTMAC_HLSTA_REVID_SHIFT        0
 #define I40E_PRTMAC_HLSTA_REVID_MASK         I40E_MASK(0xF, I40E_PRTMAC_HLSTA_REVID_SHIFT)
 #define I40E_PRTMAC_HLSTA_RESERVED_2_SHIFT   4
@@ -7629,7 +7986,7 @@
 #define I40E_PRTMAC_HLSTA_LEGACY_RSVD2_SHIFT 9
 #define I40E_PRTMAC_HLSTA_LEGACY_RSVD2_MASK  I40E_MASK(0x1, I40E_PRTMAC_HLSTA_LEGACY_RSVD2_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_INTERNAL                             0x001E3530
+#define I40E_PRTMAC_HSEC_CTL_INTERNAL                             0x001E3530 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_INTERNAL_HSEC_RX_SWZL_SHIFT          0
 #define I40E_PRTMAC_HSEC_CTL_INTERNAL_HSEC_RX_SWZL_MASK           I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_INTERNAL_HSEC_RX_SWZL_SHIFT)
 #define I40E_PRTMAC_HSEC_CTL_INTERNAL_HSEC_TX_SWZL_SHIFT          1
@@ -7637,219 +7994,219 @@
 #define I40E_PRTMAC_HSEC_CTL_INTERNAL_HSEC_CTL_RX_CHECK_ACK_SHIFT 2
 #define I40E_PRTMAC_HSEC_CTL_INTERNAL_HSEC_CTL_RX_CHECK_ACK_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_INTERNAL_HSEC_CTL_RX_CHECK_ACK_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GCP                                   0x001E3160
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GCP                                   0x001E3160 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GCP_HSEC_CTL_RX_CHECK_ETYPE_GCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GCP_HSEC_CTL_RX_CHECK_ETYPE_GCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GCP_HSEC_CTL_RX_CHECK_ETYPE_GCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GPP                                   0x001E32A0
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GPP                                   0x001E32A0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GPP_HSEC_CTL_RX_CHECK_ETYPE_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GPP_HSEC_CTL_RX_CHECK_ETYPE_GPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_GPP_HSEC_CTL_RX_CHECK_ETYPE_GPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PCP                                   0x001E3210
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PCP                                   0x001E3210 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PCP_HSEC_CTL_RX_CHECK_ETYPE_PCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PCP_HSEC_CTL_RX_CHECK_ETYPE_PCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PCP_HSEC_CTL_RX_CHECK_ETYPE_PCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PPP                                   0x001E3320
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PPP                                   0x001E3320 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PPP_HSEC_CTL_RX_CHECK_ETYPE_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PPP_HSEC_CTL_RX_CHECK_ETYPE_PPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_ETYPE_PPP_HSEC_CTL_RX_CHECK_ETYPE_PPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GCP                                   0x001E30F0
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GCP                                   0x001E30F0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GCP_HSEC_CTL_RX_CHECK_MCAST_GCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GCP_HSEC_CTL_RX_CHECK_MCAST_GCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GCP_HSEC_CTL_RX_CHECK_MCAST_GCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GPP                                   0x001E3270
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GPP                                   0x001E3270 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GPP_HSEC_CTL_RX_CHECK_MCAST_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GPP_HSEC_CTL_RX_CHECK_MCAST_GPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_GPP_HSEC_CTL_RX_CHECK_MCAST_GPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PCP                                   0x001E31C0
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PCP                                   0x001E31C0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PCP_HSEC_CTL_RX_CHECK_MCAST_PCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PCP_HSEC_CTL_RX_CHECK_MCAST_PCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PCP_HSEC_CTL_RX_CHECK_MCAST_PCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PPP                                   0x001E32F0
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PPP                                   0x001E32F0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PPP_HSEC_CTL_RX_CHECK_MCAST_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PPP_HSEC_CTL_RX_CHECK_MCAST_PPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_MCAST_PPP_HSEC_CTL_RX_CHECK_MCAST_PPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GCP                                    0x001E3170
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GCP                                    0x001E3170 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GCP_HSEC_CTL_RX_CHECK_OPCODE_GCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GCP_HSEC_CTL_RX_CHECK_OPCODE_GCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GCP_HSEC_CTL_RX_CHECK_OPCODE_GCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GPP                                    0x001E32C0
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GPP                                    0x001E32C0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GPP_HSEC_CTL_RX_CHECK_OPCODE_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GPP_HSEC_CTL_RX_CHECK_OPCODE_GPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_GPP_HSEC_CTL_RX_CHECK_OPCODE_GPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PCP                                    0x001E3230
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PCP                                    0x001E3230 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PCP_HSEC_CTL_RX_CHECK_OPCODE_PCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PCP_HSEC_CTL_RX_CHECK_OPCODE_PCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PCP_HSEC_CTL_RX_CHECK_OPCODE_PCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PPP                                    0x001E3340
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PPP                                    0x001E3340 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PPP_HSEC_CTL_RX_CHECK_OPCODE_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PPP_HSEC_CTL_RX_CHECK_OPCODE_PPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_OPCODE_PPP_HSEC_CTL_RX_CHECK_OPCODE_PPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP                                0x001E3130
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP                                0x001E3130 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP                                0x001E3290
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP                                0x001E3290 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PCP                                0x001E3200
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PCP                                0x001E3200 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PCP_HSEC_CTL_RX_CHECK_SA_PCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PCP_HSEC_CTL_RX_CHECK_SA_PCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PCP_HSEC_CTL_RX_CHECK_SA_PCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP                                0x001E3310
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP                                0x001E3310 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP                                   0x001E3100
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP                                   0x001E3100 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP                                   0x001E3280
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP                                   0x001E3280 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PCP                                   0x001E31D0
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PCP                                   0x001E31D0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PCP_HSEC_CTL_RX_CHECK_UCAST_PCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PCP_HSEC_CTL_RX_CHECK_UCAST_PCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PCP_HSEC_CTL_RX_CHECK_UCAST_PCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP                                   0x001E3300
+#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP                                   0x001E3300 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_DELETE_FCS                              0x001E3080
+#define I40E_PRTMAC_HSEC_CTL_RX_DELETE_FCS                              0x001E3080 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_DELETE_FCS_HSEC_CTL_RX_DELETE_FCS_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_DELETE_FCS_HSEC_CTL_RX_DELETE_FCS_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_DELETE_FCS_HSEC_CTL_RX_DELETE_FCS_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE                          0x001E3070
+#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE                          0x001E3070 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_HSEC_CTL_RX_ENABLE_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_HSEC_CTL_RX_ENABLE_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_HSEC_CTL_RX_ENABLE_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PCP                              0x001E31B0
+#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PCP                              0x001E31B0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PCP_HSEC_CTL_RX_ENABLE_PCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PCP_HSEC_CTL_RX_ENABLE_PCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PCP_HSEC_CTL_RX_ENABLE_PCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GCP                             0x001E31A0
+#define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GCP                             0x001E31A0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GCP_HSEC_CTL_RX_ETYPE_GCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GCP_HSEC_CTL_RX_ETYPE_GCP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GCP_HSEC_CTL_RX_ETYPE_GCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GPP                             0x001E32B0
+#define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GPP                             0x001E32B0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GPP_HSEC_CTL_RX_ETYPE_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GPP_HSEC_CTL_RX_ETYPE_GPP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_ETYPE_GPP_HSEC_CTL_RX_ETYPE_GPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PCP                             0x001E3220
+#define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PCP                             0x001E3220 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PCP_HSEC_CTL_RX_ETYPE_PCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PCP_HSEC_CTL_RX_ETYPE_PCP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PCP_HSEC_CTL_RX_ETYPE_PCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PPP                             0x001E3330
+#define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PPP                             0x001E3330 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PPP_HSEC_CTL_RX_ETYPE_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PPP_HSEC_CTL_RX_ETYPE_PPP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_ETYPE_PPP_HSEC_CTL_RX_ETYPE_PPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_IGNORE_FCS                              0x001E3090
+#define I40E_PRTMAC_HSEC_CTL_RX_IGNORE_FCS                              0x001E3090 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_IGNORE_FCS_HSEC_CTL_RX_IGNORE_FCS_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_IGNORE_FCS_HSEC_CTL_RX_IGNORE_FCS_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_IGNORE_FCS_HSEC_CTL_RX_IGNORE_FCS_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_MAX_PACKET_LEN                                  0x001E30A0
+#define I40E_PRTMAC_HSEC_CTL_RX_MAX_PACKET_LEN                                  0x001E30A0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_MAX_PACKET_LEN_HSEC_CTL_RX_MAX_PACKET_LEN_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_MAX_PACKET_LEN_HSEC_CTL_RX_MAX_PACKET_LEN_MASK  I40E_MASK(0x7FFF, I40E_PRTMAC_HSEC_CTL_RX_MAX_PACKET_LEN_HSEC_CTL_RX_MAX_PACKET_LEN_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_MIN_PACKET_LEN                                  0x001E30B0
+#define I40E_PRTMAC_HSEC_CTL_RX_MIN_PACKET_LEN                                  0x001E30B0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_MIN_PACKET_LEN_HSEC_CTL_RX_MIN_PACKET_LEN_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_MIN_PACKET_LEN_HSEC_CTL_RX_MIN_PACKET_LEN_MASK  I40E_MASK(0xFF, I40E_PRTMAC_HSEC_CTL_RX_MIN_PACKET_LEN_HSEC_CTL_RX_MIN_PACKET_LEN_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_GPP                              0x001E32D0
+#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_GPP                              0x001E32D0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_GPP_HSEC_CTL_RX_OPCODE_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_GPP_HSEC_CTL_RX_OPCODE_GPP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_OPCODE_GPP_HSEC_CTL_RX_OPCODE_GPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_GCP                                  0x001E3190
+#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_GCP                                  0x001E3190 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_GCP_HSEC_CTL_RX_OPCODE_MAX_GCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_GCP_HSEC_CTL_RX_OPCODE_MAX_GCP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_GCP_HSEC_CTL_RX_OPCODE_MAX_GCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_PCP                                  0x001E3250
+#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_PCP                                  0x001E3250 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_PCP_HSEC_CTL_RX_OPCODE_MAX_PCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_PCP_HSEC_CTL_RX_OPCODE_MAX_PCP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MAX_PCP_HSEC_CTL_RX_OPCODE_MAX_PCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_GCP                                  0x001E3180
+#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_GCP                                  0x001E3180 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_GCP_HSEC_CTL_RX_OPCODE_MIN_GCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_GCP_HSEC_CTL_RX_OPCODE_MIN_GCP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_GCP_HSEC_CTL_RX_OPCODE_MIN_GCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_PCP                                  0x001E3240
+#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_PCP                                  0x001E3240 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_PCP_HSEC_CTL_RX_OPCODE_MIN_PCP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_PCP_HSEC_CTL_RX_OPCODE_MIN_PCP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_OPCODE_MIN_PCP_HSEC_CTL_RX_OPCODE_MIN_PCP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_PPP                              0x001E3350
+#define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_PPP                              0x001E3350 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_PPP_HSEC_CTL_RX_OPCODE_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_OPCODE_PPP_HSEC_CTL_RX_OPCODE_PPP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_OPCODE_PPP_HSEC_CTL_RX_OPCODE_PPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART1                                        0x001E31E0
+#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART1                                        0x001E31E0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART1_HSEC_CTL_RX_PAUSE_DA_MCAST_PART1_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART1_HSEC_CTL_RX_PAUSE_DA_MCAST_PART1_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART1_HSEC_CTL_RX_PAUSE_DA_MCAST_PART1_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART2                                        0x001E31F0
+#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART2                                        0x001E31F0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART2_HSEC_CTL_RX_PAUSE_DA_MCAST_PART2_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART2_HSEC_CTL_RX_PAUSE_DA_MCAST_PART2_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_MCAST_PART2_HSEC_CTL_RX_PAUSE_DA_MCAST_PART2_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART1                                0x001E3490
+#define I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART1                                0x001E3490 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART1_HSEC_CTL_TX_DA_GPP_PART1_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART1_HSEC_CTL_TX_DA_GPP_PART1_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART1_HSEC_CTL_TX_DA_GPP_PART1_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART2                                0x001E34A0
+#define I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART2                                0x001E34A0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART2_HSEC_CTL_TX_DA_GPP_PART2_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART2_HSEC_CTL_TX_DA_GPP_PART2_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_DA_GPP_PART2_HSEC_CTL_TX_DA_GPP_PART2_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART1                                0x001E34F0
+#define I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART1                                0x001E34F0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART1_HSEC_CTL_TX_DA_PPP_PART1_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART1_HSEC_CTL_TX_DA_PPP_PART1_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART1_HSEC_CTL_TX_DA_PPP_PART1_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART2                                0x001E3500
+#define I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART2                                0x001E3500 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART2_HSEC_CTL_TX_DA_PPP_PART2_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART2_HSEC_CTL_TX_DA_PPP_PART2_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_DA_PPP_PART2_HSEC_CTL_TX_DA_PPP_PART2_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE                          0x001E3000
+#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE                          0x001E3000 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_ERR_PKT_MODE                                0x001E3060
+#define I40E_PRTMAC_HSEC_CTL_TX_ERR_PKT_MODE                                0x001E3060 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_ERR_PKT_MODE_HSEC_CTL_TX_ERR_PKT_MODE_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_ERR_PKT_MODE_HSEC_CTL_TX_ERR_PKT_MODE_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_TX_ERR_PKT_MODE_HSEC_CTL_TX_ERR_PKT_MODE_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_GPP                                 0x001E34D0
+#define I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_GPP                                 0x001E34D0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_GPP_HSEC_CTL_TX_ETHERTYPE_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_GPP_HSEC_CTL_TX_ETHERTYPE_GPP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_GPP_HSEC_CTL_TX_ETHERTYPE_GPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_PPP                                 0x001E3510
+#define I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_PPP                                 0x001E3510 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_PPP_HSEC_CTL_TX_ETHERTYPE_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_PPP_HSEC_CTL_TX_ETHERTYPE_PPP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_ETHERTYPE_PPP_HSEC_CTL_TX_ETHERTYPE_PPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_FCS_INS_ENABLE                     0x001E3020
+#define I40E_PRTMAC_HSEC_CTL_TX_FCS_INS_ENABLE                     0x001E3020 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_FCS_INS_ENABLE_TX_FCS_INS_EN_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_FCS_INS_ENABLE_TX_FCS_INS_EN_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_TX_FCS_INS_ENABLE_TX_FCS_INS_EN_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_FCS_STOMP                             0x001E3030
+#define I40E_PRTMAC_HSEC_CTL_TX_FCS_STOMP                             0x001E3030 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_FCS_STOMP_HSEC_CTL_TX_FCS_STOMP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_FCS_STOMP_HSEC_CTL_TX_FCS_STOMP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_TX_FCS_STOMP_HSEC_CTL_TX_FCS_STOMP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_IGNORE_FCS                              0x001E3040
+#define I40E_PRTMAC_HSEC_CTL_TX_IGNORE_FCS                              0x001E3040 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_IGNORE_FCS_HSEC_CTL_TX_IGNORE_FCS_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_IGNORE_FCS_HSEC_CTL_TX_IGNORE_FCS_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_TX_IGNORE_FCS_HSEC_CTL_TX_IGNORE_FCS_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_OPCODE_GPP                              0x001E34E0
+#define I40E_PRTMAC_HSEC_CTL_TX_OPCODE_GPP                              0x001E34E0 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_OPCODE_GPP_HSEC_CTL_TX_OPCODE_GPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_OPCODE_GPP_HSEC_CTL_TX_OPCODE_GPP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_OPCODE_GPP_HSEC_CTL_TX_OPCODE_GPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_OPCODE_PPP                              0x001E3520
+#define I40E_PRTMAC_HSEC_CTL_TX_OPCODE_PPP                              0x001E3520 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_OPCODE_PPP_HSEC_CTL_TX_OPCODE_PPP_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_OPCODE_PPP_HSEC_CTL_TX_OPCODE_PPP_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_OPCODE_PPP_HSEC_CTL_TX_OPCODE_PPP_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_RDYOUT_THRESH                                 0x001E3010
+#define I40E_PRTMAC_HSEC_CTL_TX_RDYOUT_THRESH                                 0x001E3010 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_RDYOUT_THRESH_HSEC_CTL_TX_RDYOUT_THRESH_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_RDYOUT_THRESH_HSEC_CTL_TX_RDYOUT_THRESH_MASK  I40E_MASK(0xF, I40E_PRTMAC_HSEC_CTL_TX_RDYOUT_THRESH_HSEC_CTL_TX_RDYOUT_THRESH_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_TX_TO_RX_LOOPBACK                                  0x001E3050
+#define I40E_PRTMAC_HSEC_CTL_TX_TO_RX_LOOPBACK                                  0x001E3050 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_TX_TO_RX_LOOPBACK_HSEC_CTL_TX_TO_RX_LOOPBACK_SHIFT 0
 #define I40E_PRTMAC_HSEC_CTL_TX_TO_RX_LOOPBACK_HSEC_CTL_TX_TO_RX_LOOPBACK_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_TX_TO_RX_LOOPBACK_HSEC_CTL_TX_TO_RX_LOOPBACK_SHIFT)
 
-#define I40E_PRTMAC_HSEC_CTL_XLGMII                   0x001E3550
+#define I40E_PRTMAC_HSEC_CTL_XLGMII                   0x001E3550 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_CTL_XLGMII_LB_PHY_SHIFT      0
 #define I40E_PRTMAC_HSEC_CTL_XLGMII_LB_PHY_MASK       I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_XLGMII_LB_PHY_SHIFT)
 #define I40E_PRTMAC_HSEC_CTL_XLGMII_HI_TH_SHIFT       1
@@ -7873,11 +8230,11 @@
 #define I40E_PRTMAC_HSEC_CTL_XLGMII_LB2TX_SHIFT       17
 #define I40E_PRTMAC_HSEC_CTL_XLGMII_LB2TX_MASK        I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_XLGMII_LB2TX_SHIFT)
 
-#define I40E_PRTMAC_HSEC_SINGLE_40G_PORT_SELECT                                  0x001E3540
+#define I40E_PRTMAC_HSEC_SINGLE_40G_PORT_SELECT                                  0x001E3540 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSEC_SINGLE_40G_PORT_SELECT_MAC_SINGLE_40G_PORT_SELECT_SHIFT 0
 #define I40E_PRTMAC_HSEC_SINGLE_40G_PORT_SELECT_MAC_SINGLE_40G_PORT_SELECT_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_SINGLE_40G_PORT_SELECT_MAC_SINGLE_40G_PORT_SELECT_SHIFT)
 
-#define I40E_PRTMAC_HSECTL1                         0x001E3560
+#define I40E_PRTMAC_HSECTL1                         0x001E3560 /* Reset: GLOBR */
 #define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT      0
 #define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_MASK       I40E_MASK(0x1, I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT)
 #define I40E_PRTMAC_HSECTL1_PAD_US_PKT_SHIFT        3
@@ -7891,7 +8248,7 @@
 #define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT 31
 #define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT)
 
-#define I40E_PRTMAC_LINKSTA                              0x001E2420
+#define I40E_PRTMAC_LINKSTA                              0x001E2420 /* Reset: GLOBR */
 #define I40E_PRTMAC_LINKSTA_FIFO_MTAR_STS_RX_EMPTY_SHIFT 0
 #define I40E_PRTMAC_LINKSTA_FIFO_MTAR_STS_RX_EMPTY_MASK  I40E_MASK(0x1, I40E_PRTMAC_LINKSTA_FIFO_MTAR_STS_RX_EMPTY_SHIFT)
 #define I40E_PRTMAC_LINKSTA_FIFO_MTAR_STS_RX_FULL_SHIFT  1
@@ -7907,7 +8264,7 @@
 #define I40E_PRTMAC_LINKSTA_MAC_LINK_UP_SHIFT            30
 #define I40E_PRTMAC_LINKSTA_MAC_LINK_UP_MASK             I40E_MASK(0x1, I40E_PRTMAC_LINKSTA_MAC_LINK_UP_SHIFT)
 
-#define I40E_PRTMAC_MACC                         0x001E24E0
+#define I40E_PRTMAC_MACC                         0x001E24E0 /* Reset: GLOBR */
 #define I40E_PRTMAC_MACC_FORCE_LINK_SHIFT        0
 #define I40E_PRTMAC_MACC_FORCE_LINK_MASK         I40E_MASK(0x1, I40E_PRTMAC_MACC_FORCE_LINK_SHIFT)
 #define I40E_PRTMAC_MACC_PHY_LOOP_BACK_SHIFT     1
@@ -7941,13 +8298,13 @@
 #define I40E_PRTMAC_MACC_FORCE_SPEED_EN_SHIFT    26
 #define I40E_PRTMAC_MACC_FORCE_SPEED_EN_MASK     I40E_MASK(0x1, I40E_PRTMAC_MACC_FORCE_SPEED_EN_SHIFT)
 
-#define I40E_PRTMAC_PAP                  0x001E2040
+#define I40E_PRTMAC_PAP                  0x001E2040 /* Reset: GLOBR */
 #define I40E_PRTMAC_PAP_TXPAUSECNT_SHIFT 0
 #define I40E_PRTMAC_PAP_TXPAUSECNT_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_PAP_TXPAUSECNT_SHIFT)
 #define I40E_PRTMAC_PAP_PACE_SHIFT       16
 #define I40E_PRTMAC_PAP_PACE_MASK        I40E_MASK(0xF, I40E_PRTMAC_PAP_PACE_SHIFT)
 
-#define I40E_PRTMAC_PCS_AN_CONTROL1              0x0008C600
+#define I40E_PRTMAC_PCS_AN_CONTROL1              0x0008C600 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_AN_CONTROL1_ANACK2_SHIFT 1
 #define I40E_PRTMAC_PCS_AN_CONTROL1_ANACK2_MASK  I40E_MASK(0x1, I40E_PRTMAC_PCS_AN_CONTROL1_ANACK2_SHIFT)
 #define I40E_PRTMAC_PCS_AN_CONTROL1_ANSF_SHIFT   2
@@ -7969,7 +8326,7 @@
 #define I40E_PRTMAC_PCS_AN_CONTROL1_PB_SHIFT     28
 #define I40E_PRTMAC_PCS_AN_CONTROL1_PB_MASK      I40E_MASK(0x3, I40E_PRTMAC_PCS_AN_CONTROL1_PB_SHIFT)
 
-#define I40E_PRTMAC_PCS_AN_CONTROL2                          0x0008C620
+#define I40E_PRTMAC_PCS_AN_CONTROL2                          0x0008C620 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_AN_CONTROL2_AN_PAGE_D_LOW_OVRD_SHIFT 0
 #define I40E_PRTMAC_PCS_AN_CONTROL2_AN_PAGE_D_LOW_OVRD_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_PCS_AN_CONTROL2_AN_PAGE_D_LOW_OVRD_SHIFT)
 #define I40E_PRTMAC_PCS_AN_CONTROL2_RSVD_SHIFT               16
@@ -7993,7 +8350,7 @@
 #define I40E_PRTMAC_PCS_AN_CONTROL2_FEC_FORCE_SHIFT          31
 #define I40E_PRTMAC_PCS_AN_CONTROL2_FEC_FORCE_MASK           I40E_MASK(0x1, I40E_PRTMAC_PCS_AN_CONTROL2_FEC_FORCE_SHIFT)
 
-#define I40E_PRTMAC_PCS_AN_CONTROL4                                 0x0008C660
+#define I40E_PRTMAC_PCS_AN_CONTROL4                                 0x0008C660 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_AN_CONTROL4_RESERVED0_SHIFT                 0
 #define I40E_PRTMAC_PCS_AN_CONTROL4_RESERVED0_MASK                  I40E_MASK(0x1FFF, I40E_PRTMAC_PCS_AN_CONTROL4_RESERVED0_SHIFT)
 #define I40E_PRTMAC_PCS_AN_CONTROL4_FORCE_KR_EEE_AN_VALUE_SHIFT     13
@@ -8015,7 +8372,7 @@
 #define I40E_PRTMAC_PCS_AN_CONTROL4_RESERVED1_SHIFT                 21
 #define I40E_PRTMAC_PCS_AN_CONTROL4_RESERVED1_MASK                  I40E_MASK(0x7FF, I40E_PRTMAC_PCS_AN_CONTROL4_RESERVED1_SHIFT)
 
-#define I40E_PRTMAC_PCS_LINK_CTRL                                0x0008C260
+#define I40E_PRTMAC_PCS_LINK_CTRL                                0x0008C260 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_LINK_CTRL_PMD_40G_R_TYPE_SELECTION_SHIFT 0
 #define I40E_PRTMAC_PCS_LINK_CTRL_PMD_40G_R_TYPE_SELECTION_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_LINK_CTRL_PMD_40G_R_TYPE_SELECTION_SHIFT)
 #define I40E_PRTMAC_PCS_LINK_CTRL_PMD_10G_R_TYPE_SELECTION_SHIFT 2
@@ -8059,7 +8416,7 @@
 #define I40E_PRTMAC_PCS_LINK_CTRL_RESTART_AUTO_NEG_SHIFT         31
 #define I40E_PRTMAC_PCS_LINK_CTRL_RESTART_AUTO_NEG_MASK          I40E_MASK(0x1, I40E_PRTMAC_PCS_LINK_CTRL_RESTART_AUTO_NEG_SHIFT)
 
-#define I40E_PRTMAC_PCS_LINK_STATUS1                                 0x0008C200
+#define I40E_PRTMAC_PCS_LINK_STATUS1                                 0x0008C200 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_LINK_STATUS1_SIGNAL_DETECTED_1G_MODE_SHIFT   5
 #define I40E_PRTMAC_PCS_LINK_STATUS1_SIGNAL_DETECTED_1G_MODE_MASK    I40E_MASK(0x1, I40E_PRTMAC_PCS_LINK_STATUS1_SIGNAL_DETECTED_1G_MODE_SHIFT)
 #define I40E_PRTMAC_PCS_LINK_STATUS1_SIGNAL_DETECTED_LANE_0_SHIFT    6
@@ -8107,7 +8464,7 @@
 #define I40E_PRTMAC_PCS_LINK_STATUS1_MAC_READY_SHIFT                 30
 #define I40E_PRTMAC_PCS_LINK_STATUS1_MAC_READY_MASK                  I40E_MASK(0x1, I40E_PRTMAC_PCS_LINK_STATUS1_MAC_READY_SHIFT)
 
-#define I40E_PRTMAC_PCS_LINK_STATUS2                             0x0008C220
+#define I40E_PRTMAC_PCS_LINK_STATUS2                             0x0008C220 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_LINK_STATUS2_SIGNAL_DETECTED_FEC_SHIFT   1
 #define I40E_PRTMAC_PCS_LINK_STATUS2_SIGNAL_DETECTED_FEC_MASK    I40E_MASK(0x1, I40E_PRTMAC_PCS_LINK_STATUS2_SIGNAL_DETECTED_FEC_SHIFT)
 #define I40E_PRTMAC_PCS_LINK_STATUS2_FEC_BLOCK_LOCK_SHIFT        2
@@ -8129,33 +8486,33 @@
 #define I40E_PRTMAC_PCS_LINK_STATUS2_BP_AN_RECEIVER_IDLE_SHIFT   19
 #define I40E_PRTMAC_PCS_LINK_STATUS2_BP_AN_RECEIVER_IDLE_MASK    I40E_MASK(0x1, I40E_PRTMAC_PCS_LINK_STATUS2_BP_AN_RECEIVER_IDLE_SHIFT)
 
-#define I40E_PRTMAC_PCS_MUX_KR                  0x0008C000
+#define I40E_PRTMAC_PCS_MUX_KR                  0x0008C000 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_MUX_KR_PCS_MUX_KR_SHIFT 0
 #define I40E_PRTMAC_PCS_MUX_KR_PCS_MUX_KR_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_PCS_MUX_KR_PCS_MUX_KR_SHIFT)
 
-#define I40E_PRTMAC_PCS_MUX_KX                  0x0008C008
+#define I40E_PRTMAC_PCS_MUX_KX                  0x0008C008 /* Reset: GLOBR */
 #define I40E_PRTMAC_PCS_MUX_KX_PCS_MUX_KX_SHIFT 0
 #define I40E_PRTMAC_PCS_MUX_KX_PCS_MUX_KX_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_PCS_MUX_KX_PCS_MUX_KX_SHIFT)
 
-#define I40E_PRTMAC_PHY_ANA_ADD               0x000A4038
+#define I40E_PRTMAC_PHY_ANA_ADD               0x000A4038 /* Reset: GLOBR */
 #define I40E_PRTMAC_PHY_ANA_ADD_ADDRESS_SHIFT 0
 #define I40E_PRTMAC_PHY_ANA_ADD_ADDRESS_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_PHY_ANA_ADD_ADDRESS_SHIFT)
 #define I40E_PRTMAC_PHY_ANA_ADD_BYTE_EN_SHIFT 28
 #define I40E_PRTMAC_PHY_ANA_ADD_BYTE_EN_MASK  I40E_MASK(0xF, I40E_PRTMAC_PHY_ANA_ADD_BYTE_EN_SHIFT)
 
-#define I40E_PRTMAC_PHY_ANA_DATA            0x000A403c
+#define I40E_PRTMAC_PHY_ANA_DATA            0x000A403c /* Reset: GLOBR */
 #define I40E_PRTMAC_PHY_ANA_DATA_DATA_SHIFT 0
 #define I40E_PRTMAC_PHY_ANA_DATA_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_PHY_ANA_DATA_DATA_SHIFT)
 
-#define I40E_PRTMAC_PMD_MUX_KR                  0x0008C004
+#define I40E_PRTMAC_PMD_MUX_KR                  0x0008C004 /* Reset: GLOBR */
 #define I40E_PRTMAC_PMD_MUX_KR_PMD_MUX_KR_SHIFT 0
 #define I40E_PRTMAC_PMD_MUX_KR_PMD_MUX_KR_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_PMD_MUX_KR_PMD_MUX_KR_SHIFT)
 
-#define I40E_PRTMAC_PMD_MUX_KX                  0x0008C00C
+#define I40E_PRTMAC_PMD_MUX_KX                  0x0008C00C /* Reset: GLOBR */
 #define I40E_PRTMAC_PMD_MUX_KX_PMD_MUX_KX_SHIFT 0
 #define I40E_PRTMAC_PMD_MUX_KX_PMD_MUX_KX_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_PMD_MUX_KX_PMD_MUX_KX_SHIFT)
 
-#define I40E_PRTMAC_TREG                        0x001E2160
+#define I40E_PRTMAC_TREG                        0x001E2160 /* Reset: GLOBR */
 #define I40E_PRTMAC_TREG_ILGLCODETXERRTST_SHIFT 0
 #define I40E_PRTMAC_TREG_ILGLCODETXERRTST_MASK  I40E_MASK(0xFF, I40E_PRTMAC_TREG_ILGLCODETXERRTST_SHIFT)
 #define I40E_PRTMAC_TREG_CTRLTXERRTST_SHIFT     8
@@ -8169,11 +8526,11 @@
 
 /* PF - Manageability  Registers  */
 
-#define I40E_EMP_TCO_ISOLATE                       0x00078E80
+#define I40E_EMP_TCO_ISOLATE                       0x00078E80 /* Reset: POR */
 #define I40E_EMP_TCO_ISOLATE_EMP_TCO_ISOLATE_SHIFT 0
 #define I40E_EMP_TCO_ISOLATE_EMP_TCO_ISOLATE_MASK  I40E_MASK(0xFFFF, I40E_EMP_TCO_ISOLATE_EMP_TCO_ISOLATE_SHIFT)
 
-#define I40E_GL_MNG_FRIACR            0x00083240
+#define I40E_GL_MNG_FRIACR            0x00083240 /* Reset: EMPR */
 #define I40E_GL_MNG_FRIACR_ADDR_SHIFT 0
 #define I40E_GL_MNG_FRIACR_ADDR_MASK  I40E_MASK(0x1FFFFF, I40E_GL_MNG_FRIACR_ADDR_SHIFT)
 #define I40E_GL_MNG_FRIACR_WR_SHIFT   24
@@ -8181,21 +8538,21 @@
 #define I40E_GL_MNG_FRIACR_RD_SHIFT   25
 #define I40E_GL_MNG_FRIACR_RD_MASK    I40E_MASK(0x1, I40E_GL_MNG_FRIACR_RD_SHIFT)
 
-#define I40E_GL_MNG_FRIARDR             0x00083248
+#define I40E_GL_MNG_FRIARDR             0x00083248 /* Reset: EMPR */
 #define I40E_GL_MNG_FRIARDR_RDATA_SHIFT 0
 #define I40E_GL_MNG_FRIARDR_RDATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_MNG_FRIARDR_RDATA_SHIFT)
 
-#define I40E_GL_MNG_FRIARR              0x0008324C
+#define I40E_GL_MNG_FRIARR              0x0008324C /* Reset: EMPR */
 #define I40E_GL_MNG_FRIARR_HALT_SHIFT   0
 #define I40E_GL_MNG_FRIARR_HALT_MASK    I40E_MASK(0x1, I40E_GL_MNG_FRIARR_HALT_SHIFT)
 #define I40E_GL_MNG_FRIARR_RST_EN_SHIFT 1
 #define I40E_GL_MNG_FRIARR_RST_EN_MASK  I40E_MASK(0x1, I40E_GL_MNG_FRIARR_RST_EN_SHIFT)
 
-#define I40E_GL_MNG_FRIAWDR             0x00083244
+#define I40E_GL_MNG_FRIAWDR             0x00083244 /* Reset: EMPR */
 #define I40E_GL_MNG_FRIAWDR_WDATA_SHIFT 0
 #define I40E_GL_MNG_FRIAWDR_WDATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_MNG_FRIAWDR_WDATA_SHIFT)
 
-#define I40E_GL_MNG_RRDFM                      0x00083040
+#define I40E_GL_MNG_RRDFM                      0x00083040 /* Reset: EMPR */
 #define I40E_GL_MNG_RRDFM_RMII_DBG_FIL_0_SHIFT 0
 #define I40E_GL_MNG_RRDFM_RMII_DBG_FIL_0_MASK  I40E_MASK(0x1, I40E_GL_MNG_RRDFM_RMII_DBG_FIL_0_SHIFT)
 #define I40E_GL_MNG_RRDFM_RMII_DBG_FIL_1_SHIFT 1
@@ -8205,11 +8562,11 @@
 #define I40E_GL_MNG_RRDFM_RMII_DBG_FIL_3_SHIFT 3
 #define I40E_GL_MNG_RRDFM_RMII_DBG_FIL_3_MASK  I40E_MASK(0x1, I40E_GL_MNG_RRDFM_RMII_DBG_FIL_3_SHIFT)
 
-#define I40E_GL_SWR_PL_THR                  0x00269FDC
+#define I40E_GL_SWR_PL_THR                  0x00269FDC /* Reset: CORER */
 #define I40E_GL_SWR_PL_THR_PIPE_LIMIT_SHIFT 0
 #define I40E_GL_SWR_PL_THR_PIPE_LIMIT_MASK  I40E_MASK(0xFF, I40E_GL_SWR_PL_THR_PIPE_LIMIT_SHIFT)
 
-#define I40E_GL_SWR_PM_UP_THR                 0x00269FBC
+#define I40E_GL_SWR_PM_UP_THR                 0x00269FBC /* Reset: CORER */
 #define I40E_GL_SWR_PM_UP_THR_UP_PORT_0_SHIFT 0
 #define I40E_GL_SWR_PM_UP_THR_UP_PORT_0_MASK  I40E_MASK(0xFF, I40E_GL_SWR_PM_UP_THR_UP_PORT_0_SHIFT)
 #define I40E_GL_SWR_PM_UP_THR_UP_PORT_1_SHIFT 8
@@ -8219,7 +8576,7 @@
 #define I40E_GL_SWR_PM_UP_THR_UP_PORT_3_SHIFT 24
 #define I40E_GL_SWR_PM_UP_THR_UP_PORT_3_MASK  I40E_MASK(0xFF, I40E_GL_SWR_PM_UP_THR_UP_PORT_3_SHIFT)
 
-#define I40E_PRT_MNG_FTFT_IGNORETAGS                                 0x00085280
+#define I40E_PRT_MNG_FTFT_IGNORETAGS                                 0x00085280 /* Reset: POR */
 #define I40E_PRT_MNG_FTFT_IGNORETAGS_PRT_MNG_FTFT_IGNORETAGS_0_SHIFT 0
 #define I40E_PRT_MNG_FTFT_IGNORETAGS_PRT_MNG_FTFT_IGNORETAGS_0_MASK  I40E_MASK(0x1, I40E_PRT_MNG_FTFT_IGNORETAGS_PRT_MNG_FTFT_IGNORETAGS_0_SHIFT)
 #define I40E_PRT_MNG_FTFT_IGNORETAGS_PRT_MNG_FTFT_IGNORETAGS_SHIFT   2
@@ -8229,13 +8586,13 @@
 
 /* PF - NVM Registers  */
 
-#define I40E_EMPNVM_FLCNT             0x000B6128
+#define I40E_EMPNVM_FLCNT             0x000B6128 /* Reset: POR */
 #define I40E_EMPNVM_FLCNT_RDCNT_SHIFT 0
 #define I40E_EMPNVM_FLCNT_RDCNT_MASK  I40E_MASK(0x1FFFFFF, I40E_EMPNVM_FLCNT_RDCNT_SHIFT)
 #define I40E_EMPNVM_FLCNT_ABORT_SHIFT 31
 #define I40E_EMPNVM_FLCNT_ABORT_MASK  I40E_MASK(0x1, I40E_EMPNVM_FLCNT_ABORT_SHIFT)
 
-#define I40E_EMPNVM_FLCTL              0x000B6120
+#define I40E_EMPNVM_FLCTL              0x000B6120 /* Reset: POR */
 #define I40E_EMPNVM_FLCTL_ADDR_SHIFT   0
 #define I40E_EMPNVM_FLCTL_ADDR_MASK    I40E_MASK(0xFFFFFF, I40E_EMPNVM_FLCTL_ADDR_SHIFT)
 #define I40E_EMPNVM_FLCTL_CMD_SHIFT    24
@@ -8249,11 +8606,11 @@
 #define I40E_EMPNVM_FLCTL_GLDONE_SHIFT 31
 #define I40E_EMPNVM_FLCTL_GLDONE_MASK  I40E_MASK(0x1, I40E_EMPNVM_FLCTL_GLDONE_SHIFT)
 
-#define I40E_EMPNVM_FLDATA                 0x000B6124
+#define I40E_EMPNVM_FLDATA                 0x000B6124 /* Reset: POR */
 #define I40E_EMPNVM_FLDATA_FLMNGDATA_SHIFT 0
 #define I40E_EMPNVM_FLDATA_FLMNGDATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_EMPNVM_FLDATA_FLMNGDATA_SHIFT)
 
-#define I40E_EMPNVM_SRCTL                     0x000B6118
+#define I40E_EMPNVM_SRCTL                     0x000B6118 /* Reset: POR */
 #define I40E_EMPNVM_SRCTL_ADDR_SHIFT          0
 #define I40E_EMPNVM_SRCTL_ADDR_MASK           I40E_MASK(0x7FFF, I40E_EMPNVM_SRCTL_ADDR_SHIFT)
 #define I40E_EMPNVM_SRCTL_START_SHIFT         15
@@ -8271,31 +8628,31 @@
 #define I40E_EMPNVM_SRCTL_DONE_SHIFT          31
 #define I40E_EMPNVM_SRCTL_DONE_MASK           I40E_MASK(0x1, I40E_EMPNVM_SRCTL_DONE_SHIFT)
 
-#define I40E_EMPNVM_SRDATA              0x000B611C
+#define I40E_EMPNVM_SRDATA              0x000B611C /* Reset: POR */
 #define I40E_EMPNVM_SRDATA_WRDATA_SHIFT 0
 #define I40E_EMPNVM_SRDATA_WRDATA_MASK  I40E_MASK(0xFFFF, I40E_EMPNVM_SRDATA_WRDATA_SHIFT)
 #define I40E_EMPNVM_SRDATA_RDDATA_SHIFT 16
 #define I40E_EMPNVM_SRDATA_RDDATA_MASK  I40E_MASK(0xFFFF, I40E_EMPNVM_SRDATA_RDDATA_SHIFT)
 
-#define I40E_GLNVM_ALTIMERS                   0x000B6140
+#define I40E_GLNVM_ALTIMERS                   0x000B6140 /* Reset: POR */
 #define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT 0
 #define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_MASK  I40E_MASK(0xFFF, I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT)
 #define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT 12
 #define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_MASK  I40E_MASK(0xFFFFF, I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT)
 
-#define I40E_GLNVM_EMPLD                       0x000B610C
+#define I40E_GLNVM_EMPLD                       0x000B610C /* Reset: POR */
 #define I40E_GLNVM_EMPLD_EMP_CORE_DONE_SHIFT   3
 #define I40E_GLNVM_EMPLD_EMP_CORE_DONE_MASK    I40E_MASK(0x1, I40E_GLNVM_EMPLD_EMP_CORE_DONE_SHIFT)
 #define I40E_GLNVM_EMPLD_EMP_GLOBAL_DONE_SHIFT 4
 #define I40E_GLNVM_EMPLD_EMP_GLOBAL_DONE_MASK  I40E_MASK(0x1, I40E_GLNVM_EMPLD_EMP_GLOBAL_DONE_SHIFT)
 
-#define I40E_GLNVM_EMPRQ                       0x000B613C
+#define I40E_GLNVM_EMPRQ                       0x000B613C /* Reset: POR */
 #define I40E_GLNVM_EMPRQ_EMP_CORE_REQD_SHIFT   3
 #define I40E_GLNVM_EMPRQ_EMP_CORE_REQD_MASK    I40E_MASK(0x1, I40E_GLNVM_EMPRQ_EMP_CORE_REQD_SHIFT)
 #define I40E_GLNVM_EMPRQ_EMP_GLOBAL_REQD_SHIFT 4
 #define I40E_GLNVM_EMPRQ_EMP_GLOBAL_REQD_MASK  I40E_MASK(0x1, I40E_GLNVM_EMPRQ_EMP_GLOBAL_REQD_SHIFT)
 
-#define I40E_GLNVM_SRLD                        0x000B600C
+#define I40E_GLNVM_SRLD                        0x000B600C /* Reset: POR */
 #define I40E_GLNVM_SRLD_HW_PCIR_DONE_SHIFT     0
 #define I40E_GLNVM_SRLD_HW_PCIR_DONE_MASK      I40E_MASK(0x1, I40E_GLNVM_SRLD_HW_PCIR_DONE_SHIFT)
 #define I40E_GLNVM_SRLD_HW_PCIRTL_DONE_SHIFT   1
@@ -8317,7 +8674,7 @@
 #define I40E_GLNVM_SRLD_HW_PCIALT_DONE_SHIFT   9
 #define I40E_GLNVM_SRLD_HW_PCIALT_DONE_MASK    I40E_MASK(0x1, I40E_GLNVM_SRLD_HW_PCIALT_DONE_SHIFT)
 
-#define I40E_GLNVM_ULT                      0x000B6154
+#define I40E_GLNVM_ULT                      0x000B6154 /* Reset: POR */
 #define I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT   0
 #define I40E_GLNVM_ULT_CONF_PCIR_AE_MASK    I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT)
 #define I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT 1
@@ -8335,7 +8692,7 @@
 #define I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT 9
 #define I40E_GLNVM_ULT_CONF_PCIALT_AE_MASK  I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT)
 
-#define I40E_MEM_INIT_GATE_AL_DONE                                    0x000B6004
+#define I40E_MEM_INIT_GATE_AL_DONE                                    0x000B6004 /* Reset: POR */
 #define I40E_MEM_INIT_GATE_AL_DONE_CMLAN_INIT_DONE_GATE_AL_DONE_SHIFT 0
 #define I40E_MEM_INIT_GATE_AL_DONE_CMLAN_INIT_DONE_GATE_AL_DONE_MASK  I40E_MASK(0x1, I40E_MEM_INIT_GATE_AL_DONE_CMLAN_INIT_DONE_GATE_AL_DONE_SHIFT)
 #define I40E_MEM_INIT_GATE_AL_DONE_PMAT_INIT_DONE_GATE_AL_DONE_SHIFT  1
@@ -8371,7 +8728,7 @@
 #define I40E_MEM_INIT_GATE_AL_DONE_ITR_INIT_DONE_GATE_AL_DONE_SHIFT   16
 #define I40E_MEM_INIT_GATE_AL_DONE_ITR_INIT_DONE_GATE_AL_DONE_MASK    I40E_MASK(0x1, I40E_MEM_INIT_GATE_AL_DONE_ITR_INIT_DONE_GATE_AL_DONE_SHIFT)
 
-#define I40E_MEM_INIT_GATE_AL_STR                                    0x000B6000
+#define I40E_MEM_INIT_GATE_AL_STR                                    0x000B6000 /* Reset: POR */
 #define I40E_MEM_INIT_GATE_AL_STR_CMLAN_INIT_DONE_GATE_AL_STRT_SHIFT 0
 #define I40E_MEM_INIT_GATE_AL_STR_CMLAN_INIT_DONE_GATE_AL_STRT_MASK  I40E_MASK(0x1, I40E_MEM_INIT_GATE_AL_STR_CMLAN_INIT_DONE_GATE_AL_STRT_SHIFT)
 #define I40E_MEM_INIT_GATE_AL_STR_PMAT_INIT_DONE_GATE_AL_STRT_SHIFT  1
@@ -8409,7 +8766,7 @@
 
 /* PF - PCIe Registers  */
 
-#define I40E_EMP_PCI_CIAA               0x0009C4D0
+#define I40E_EMP_PCI_CIAA               0x0009C4D0 /* Reset: PCIR */
 #define I40E_EMP_PCI_CIAA_ADDRESS_SHIFT 0
 #define I40E_EMP_PCI_CIAA_ADDRESS_MASK  I40E_MASK(0xFFF, I40E_EMP_PCI_CIAA_ADDRESS_SHIFT)
 #define I40E_EMP_PCI_CIAA_FNUM_SHIFT    12
@@ -8417,40 +8774,40 @@
 #define I40E_EMP_PCI_CIAA_PF_SHIFT      19
 #define I40E_EMP_PCI_CIAA_PF_MASK       I40E_MASK(0x1, I40E_EMP_PCI_CIAA_PF_SHIFT)
 
-#define I40E_EMP_PCI_CIAD            0x0009C4D4
+#define I40E_EMP_PCI_CIAD            0x0009C4D4 /* Reset: PCIR */
 #define I40E_EMP_PCI_CIAD_DATA_SHIFT 0
 #define I40E_EMP_PCI_CIAD_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_EMP_PCI_CIAD_DATA_SHIFT)
 
-#define I40E_GL_PCI_DBGCTL                            0x000BE4F4
+#define I40E_GL_PCI_DBGCTL                            0x000BE4F4 /* Reset: PCIR */
 #define I40E_GL_PCI_DBGCTL_CONFIG_ACCESS_ENABLE_SHIFT 0
 #define I40E_GL_PCI_DBGCTL_CONFIG_ACCESS_ENABLE_MASK  I40E_MASK(0x1, I40E_GL_PCI_DBGCTL_CONFIG_ACCESS_ENABLE_SHIFT)
 
-#define I40E_GLGEN_FWPFRSTAT              0x0009C4E8
+#define I40E_GLGEN_FWPFRSTAT              0x0009C4E8 /* Reset: PCIR */
 #define I40E_GLGEN_FWPFRSTAT_PF_FLR_SHIFT 0
 #define I40E_GLGEN_FWPFRSTAT_PF_FLR_MASK  I40E_MASK(0xFFFF, I40E_GLGEN_FWPFRSTAT_PF_FLR_SHIFT)
 
-#define I40E_GLGEN_FWVFRSTAT(_i)          (0x0009C4D8 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLGEN_FWVFRSTAT(_i)          (0x0009C4D8 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
 #define I40E_GLGEN_FWVFRSTAT_MAX_INDEX    3
 #define I40E_GLGEN_FWVFRSTAT_VF_FLR_SHIFT 0
 #define I40E_GLGEN_FWVFRSTAT_VF_FLR_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLGEN_FWVFRSTAT_VF_FLR_SHIFT)
 
-#define I40E_GLGEN_PCIFCNCNT_PCI                0x000BE4A0
+#define I40E_GLGEN_PCIFCNCNT_PCI                0x000BE4A0 /* Reset: PCIR */
 #define I40E_GLGEN_PCIFCNCNT_PCI_PCIPFCNT_SHIFT 0
 #define I40E_GLGEN_PCIFCNCNT_PCI_PCIPFCNT_MASK  I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCI_PCIPFCNT_SHIFT)
 #define I40E_GLGEN_PCIFCNCNT_PCI_PCIVFCNT_SHIFT 16
 #define I40E_GLGEN_PCIFCNCNT_PCI_PCIVFCNT_MASK  I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCI_PCIVFCNT_SHIFT)
 
-#define I40E_GLPCI_ANA_ADD               0x000BA000
+#define I40E_GLPCI_ANA_ADD               0x000BA000 /* Reset: POR */
 #define I40E_GLPCI_ANA_ADD_ADDRESS_SHIFT 0
 #define I40E_GLPCI_ANA_ADD_ADDRESS_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_ANA_ADD_ADDRESS_SHIFT)
 #define I40E_GLPCI_ANA_ADD_BYTE_EN_SHIFT 28
 #define I40E_GLPCI_ANA_ADD_BYTE_EN_MASK  I40E_MASK(0xF, I40E_GLPCI_ANA_ADD_BYTE_EN_SHIFT)
 
-#define I40E_GLPCI_ANA_DATA            0x000BA004
+#define I40E_GLPCI_ANA_DATA            0x000BA004 /* Reset: POR */
 #define I40E_GLPCI_ANA_DATA_DATA_SHIFT 0
 #define I40E_GLPCI_ANA_DATA_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_ANA_DATA_DATA_SHIFT)
 
-#define I40E_GLPCI_LCBADD                0x0009C4C0
+#define I40E_GLPCI_LCBADD                0x0009C4C0 /* Reset: PCIR */
 #define I40E_GLPCI_LCBADD_ADDRESS_SHIFT  0
 #define I40E_GLPCI_LCBADD_ADDRESS_MASK   I40E_MASK(0x3FFFF, I40E_GLPCI_LCBADD_ADDRESS_SHIFT)
 #define I40E_GLPCI_LCBADD_BLOCK_ID_SHIFT 20
@@ -8458,23 +8815,23 @@
 #define I40E_GLPCI_LCBADD_LOCK_SHIFT     31
 #define I40E_GLPCI_LCBADD_LOCK_MASK      I40E_MASK(0x1, I40E_GLPCI_LCBADD_LOCK_SHIFT)
 
-#define I40E_GLPCI_LCBDATA                0x0009C4C4
+#define I40E_GLPCI_LCBDATA                0x0009C4C4 /* Reset: PCIR */
 #define I40E_GLPCI_LCBDATA_LCB_DATA_SHIFT 0
 #define I40E_GLPCI_LCBDATA_LCB_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_LCBDATA_LCB_DATA_SHIFT)
 
-#define I40E_GLPCI_PCITEST1                  0x000BE488
+#define I40E_GLPCI_PCITEST1                  0x000BE488 /* Reset: PCIR */
 #define I40E_GLPCI_PCITEST1_IGNORE_RID_SHIFT 0
 #define I40E_GLPCI_PCITEST1_IGNORE_RID_MASK  I40E_MASK(0x1, I40E_GLPCI_PCITEST1_IGNORE_RID_SHIFT)
 #define I40E_GLPCI_PCITEST1_V_MSIX_EN_SHIFT  2
 #define I40E_GLPCI_PCITEST1_V_MSIX_EN_MASK   I40E_MASK(0x1, I40E_GLPCI_PCITEST1_V_MSIX_EN_SHIFT)
 
-#define I40E_GLPCI_PCITEST2                     0x000BE4BC
+#define I40E_GLPCI_PCITEST2                     0x000BE4BC /* Reset: PCIR */
 #define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT 0
 #define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_MASK  I40E_MASK(0x1, I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT)
 #define I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT     1
 #define I40E_GLPCI_PCITEST2_TAG_ALLOC_MASK      I40E_MASK(0x1, I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT)
 
-#define I40E_GLTPH_CTRL                         0x000BE480
+#define I40E_GLTPH_CTRL                         0x000BE480 /* Reset: PCIR */
 #define I40E_GLTPH_CTRL_DISABLE_READ_HINT_SHIFT 8
 #define I40E_GLTPH_CTRL_DISABLE_READ_HINT_MASK  I40E_MASK(0x1, I40E_GLTPH_CTRL_DISABLE_READ_HINT_SHIFT)
 #define I40E_GLTPH_CTRL_DESC_PH_SHIFT           9
@@ -8484,7 +8841,7 @@
 #define I40E_GLTPH_CTRL_TPH_AUTOLEARN_SHIFT     13
 #define I40E_GLTPH_CTRL_TPH_AUTOLEARN_MASK      I40E_MASK(0x1, I40E_GLTPH_CTRL_TPH_AUTOLEARN_SHIFT)
 
-#define I40E_PF_VT_PFALLOC_PCIE               0x000BE380
+#define I40E_PF_VT_PFALLOC_PCIE               0x000BE380 /* Reset: PCIR */
 #define I40E_PF_VT_PFALLOC_PCIE_FIRSTVF_SHIFT 0
 #define I40E_PF_VT_PFALLOC_PCIE_FIRSTVF_MASK  I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_PCIE_FIRSTVF_SHIFT)
 #define I40E_PF_VT_PFALLOC_PCIE_LASTVF_SHIFT  8
@@ -8494,7 +8851,7 @@
 
 /* PF - Power Management Registers */
 
-#define I40E_GLPCI_PM_EN_STAT                        0x000BE4E4
+#define I40E_GLPCI_PM_EN_STAT                        0x000BE4E4 /* Reset: POR */
 #define I40E_GLPCI_PM_EN_STAT_PCIE_PME_EN_PF0_SHIFT  0
 #define I40E_GLPCI_PM_EN_STAT_PCIE_PME_EN_PF0_MASK   I40E_MASK(0x1, I40E_GLPCI_PM_EN_STAT_PCIE_PME_EN_PF0_SHIFT)
 #define I40E_GLPCI_PM_EN_STAT_PCIE_PME_EN_PF1_SHIFT  1
@@ -8528,17 +8885,17 @@
 #define I40E_GLPCI_PM_EN_STAT_PCIE_PME_EN_PF15_SHIFT 15
 #define I40E_GLPCI_PM_EN_STAT_PCIE_PME_EN_PF15_MASK  I40E_MASK(0x1, I40E_GLPCI_PM_EN_STAT_PCIE_PME_EN_PF15_SHIFT)
 
-#define I40E_GLPM_DMAC_ENC                 0x000881F0
+#define I40E_GLPM_DMAC_ENC                 0x000881F0 /* Reset: CORER */
 #define I40E_GLPM_DMAC_ENC_DMACENTRY_SHIFT 0
 #define I40E_GLPM_DMAC_ENC_DMACENTRY_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPM_DMAC_ENC_DMACENTRY_SHIFT)
 
-#define I40E_GLPM_DMAC_EXC                     0x000881FC
+#define I40E_GLPM_DMAC_EXC                     0x000881FC /* Reset: CORER */
 #define I40E_GLPM_DMAC_EXC_DMACTIMEREXIT_SHIFT 0
 #define I40E_GLPM_DMAC_EXC_DMACTIMEREXIT_MASK  I40E_MASK(0xFFFF, I40E_GLPM_DMAC_EXC_DMACTIMEREXIT_SHIFT)
 #define I40E_GLPM_DMAC_EXC_DMAIMMEXIT_SHIFT    16
 #define I40E_GLPM_DMAC_EXC_DMAIMMEXIT_MASK     I40E_MASK(0xFFFF, I40E_GLPM_DMAC_EXC_DMAIMMEXIT_SHIFT)
 
-#define I40E_GLPM_DMACR                                0x000881F4
+#define I40E_GLPM_DMACR                                0x000881F4 /* Reset: CORER */
 #define I40E_GLPM_DMACR_DMACWT_SHIFT                   0
 #define I40E_GLPM_DMACR_DMACWT_MASK                    I40E_MASK(0xFFFF, I40E_GLPM_DMACR_DMACWT_SHIFT)
 #define I40E_GLPM_DMACR_EXIT_DC_SHIFT                  29
@@ -8548,21 +8905,21 @@
 #define I40E_GLPM_DMACR_DMAC_EN_SHIFT                  31
 #define I40E_GLPM_DMACR_DMAC_EN_MASK                   I40E_MASK(0x1, I40E_GLPM_DMACR_DMAC_EN_SHIFT)
 
-#define I40E_GLPM_DMCTH               0x000AC7E4
+#define I40E_GLPM_DMCTH               0x000AC7E4 /* Reset: CORER */
 #define I40E_GLPM_DMCTH_DMACRXT_SHIFT 0
 #define I40E_GLPM_DMCTH_DMACRXT_MASK  I40E_MASK(0x3FF, I40E_GLPM_DMCTH_DMACRXT_SHIFT)
 
-#define I40E_GLPM_DMCTLX            0x000881F8
+#define I40E_GLPM_DMCTLX            0x000881F8 /* Reset: CORER */
 #define I40E_GLPM_DMCTLX_TTLX_SHIFT 0
 #define I40E_GLPM_DMCTLX_TTLX_MASK  I40E_MASK(0xFFF, I40E_GLPM_DMCTLX_TTLX_SHIFT)
 
-#define I40E_GLPM_EEE_SU                           0x001E4340
+#define I40E_GLPM_EEE_SU                           0x001E4340 /* Reset: GLOBR */
 #define I40E_GLPM_EEE_SU_DTW_MIN_1000_BASE_T_SHIFT 0
 #define I40E_GLPM_EEE_SU_DTW_MIN_1000_BASE_T_MASK  I40E_MASK(0xFF, I40E_GLPM_EEE_SU_DTW_MIN_1000_BASE_T_SHIFT)
 #define I40E_GLPM_EEE_SU_DTW_MIN_100_BASE_TX_SHIFT 8
 #define I40E_GLPM_EEE_SU_DTW_MIN_100_BASE_TX_MASK  I40E_MASK(0xFF, I40E_GLPM_EEE_SU_DTW_MIN_100_BASE_TX_SHIFT)
 
-#define I40E_GLPM_EEE_SU_EXT                            0x001E4344
+#define I40E_GLPM_EEE_SU_EXT                            0x001E4344 /* Reset: GLOBR */
 #define I40E_GLPM_EEE_SU_EXT_DTW_MIN_1000_BASE_KX_SHIFT 0
 #define I40E_GLPM_EEE_SU_EXT_DTW_MIN_1000_BASE_KX_MASK  I40E_MASK(0xFF, I40E_GLPM_EEE_SU_EXT_DTW_MIN_1000_BASE_KX_SHIFT)
 #define I40E_GLPM_EEE_SU_EXT_DTW_MIN_10GBASE_KX4_SHIFT  8
@@ -8572,7 +8929,7 @@
 #define I40E_GLPM_EEE_SU_EXT_DTW_MIN_10GBASE_T_SHIFT    24
 #define I40E_GLPM_EEE_SU_EXT_DTW_MIN_10GBASE_T_MASK     I40E_MASK(0xFF, I40E_GLPM_EEE_SU_EXT_DTW_MIN_10GBASE_T_SHIFT)
 
-#define I40E_GLPM_LTRC                         0x000BE500
+#define I40E_GLPM_LTRC                         0x000BE500 /* Reset: PCIR */
 #define I40E_GLPM_LTRC_SLTRV_SHIFT             0
 #define I40E_GLPM_LTRC_SLTRV_MASK              I40E_MASK(0x3FF, I40E_GLPM_LTRC_SLTRV_SHIFT)
 #define I40E_GLPM_LTRC_SSCALE_SHIFT            10
@@ -8588,70 +8945,70 @@
 #define I40E_GLPM_LTRC_LTRNS_REQUIREMENT_SHIFT 31
 #define I40E_GLPM_LTRC_LTRNS_REQUIREMENT_MASK  I40E_MASK(0x1, I40E_GLPM_LTRC_LTRNS_REQUIREMENT_SHIFT)
 
-#define I40E_PRTPM_EEEDBG                  0x001E4420
+#define I40E_PRTPM_EEEDBG                  0x001E4420 /* Reset: GLOBR */
 #define I40E_PRTPM_EEEDBG_FORCE_TLPI_SHIFT 0
 #define I40E_PRTPM_EEEDBG_FORCE_TLPI_MASK  I40E_MASK(0x1, I40E_PRTPM_EEEDBG_FORCE_TLPI_SHIFT)
 
-#define I40E_PRTPM_HPTC                   0x000AC800
+#define I40E_PRTPM_HPTC                   0x000AC800 /* Reset: CORER */
 #define I40E_PRTPM_HPTC_HIGH_PRI_TC_SHIFT 0
 #define I40E_PRTPM_HPTC_HIGH_PRI_TC_MASK  I40E_MASK(0xFF, I40E_PRTPM_HPTC_HIGH_PRI_TC_SHIFT)
 
 /* PF - Receive Packet Buffer Registers */
 
-#define I40E_GLRPB_DHWS               0x000AC820
+#define I40E_GLRPB_DHWS               0x000AC820 /* Reset: CORER */
 #define I40E_GLRPB_DHWS_DHW_TCN_SHIFT 0
 #define I40E_GLRPB_DHWS_DHW_TCN_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_DHWS_DHW_TCN_SHIFT)
 
-#define I40E_GLRPB_DLWS               0x000AC824
+#define I40E_GLRPB_DLWS               0x000AC824 /* Reset: CORER */
 #define I40E_GLRPB_DLWS_DLW_TCN_SHIFT 0
 #define I40E_GLRPB_DLWS_DLW_TCN_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_DLWS_DLW_TCN_SHIFT)
 
-#define I40E_GLRPB_GFC           0x000AC82C
+#define I40E_GLRPB_GFC           0x000AC82C /* Reset: CORER */
 #define I40E_GLRPB_GFC_GFC_SHIFT 0
 #define I40E_GLRPB_GFC_GFC_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_GFC_GFC_SHIFT)
 
-#define I40E_GLRPB_GPC           0x000AC838
+#define I40E_GLRPB_GPC           0x000AC838 /* Reset: CORER */
 #define I40E_GLRPB_GPC_GPC_SHIFT 0
 #define I40E_GLRPB_GPC_GPC_MASK  I40E_MASK(0x3FFF, I40E_GLRPB_GPC_GPC_SHIFT)
 
-#define I40E_GLRPB_LTRTL             0x000AC83C
+#define I40E_GLRPB_LTRTL             0x000AC83C /* Reset: CORER */
 #define I40E_GLRPB_LTRTL_LTRTL_SHIFT 0
 #define I40E_GLRPB_LTRTL_LTRTL_MASK  I40E_MASK(0x3FF, I40E_GLRPB_LTRTL_LTRTL_SHIFT)
 
-#define I40E_GLRPB_LTRTV             0x000AC840
+#define I40E_GLRPB_LTRTV             0x000AC840 /* Reset: CORER */
 #define I40E_GLRPB_LTRTV_LTRTV_SHIFT 0
 #define I40E_GLRPB_LTRTV_LTRTV_MASK  I40E_MASK(0x3FF, I40E_GLRPB_LTRTV_LTRTV_SHIFT)
 
-#define I40E_GLRPB_SHTS               0x000AC84C
+#define I40E_GLRPB_SHTS               0x000AC84C /* Reset: CORER */
 #define I40E_GLRPB_SHTS_SHT_TCN_SHIFT 0
 #define I40E_GLRPB_SHTS_SHT_TCN_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_SHTS_SHT_TCN_SHIFT)
 
-#define I40E_GLRPB_SHWS           0x000AC850
+#define I40E_GLRPB_SHWS           0x000AC850 /* Reset: CORER */
 #define I40E_GLRPB_SHWS_SHW_SHIFT 0
 #define I40E_GLRPB_SHWS_SHW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_SHWS_SHW_SHIFT)
 
-#define I40E_GLRPB_SLTS               0x000AC854
+#define I40E_GLRPB_SLTS               0x000AC854 /* Reset: CORER */
 #define I40E_GLRPB_SLTS_SLT_TCN_SHIFT 0
 #define I40E_GLRPB_SLTS_SLT_TCN_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_SLTS_SLT_TCN_SHIFT)
 
-#define I40E_GLRPB_SLWS           0x000AC858
+#define I40E_GLRPB_SLWS           0x000AC858 /* Reset: CORER */
 #define I40E_GLRPB_SLWS_SLW_SHIFT 0
 #define I40E_GLRPB_SLWS_SLW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_SLWS_SLW_SHIFT)
 
-#define I40E_GLRPB_SPSS           0x000AC85C
+#define I40E_GLRPB_SPSS           0x000AC85C /* Reset: CORER */
 #define I40E_GLRPB_SPSS_SPS_SHIFT 0
 #define I40E_GLRPB_SPSS_SPS_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_SPSS_SPS_SHIFT)
 
-#define I40E_PRTRPB_DFC(_i)           (0x000AC000 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTRPB_DFC(_i)           (0x000AC000 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTRPB_DFC_MAX_INDEX     7
 #define I40E_PRTRPB_DFC_DFC_TCN_SHIFT 0
 #define I40E_PRTRPB_DFC_DFC_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_DFC_DFC_TCN_SHIFT)
 
-#define I40E_PRTRPB_PFC           0x000AC420
+#define I40E_PRTRPB_PFC           0x000AC420 /* Reset: CORER */
 #define I40E_PRTRPB_PFC_PFC_SHIFT 0
 #define I40E_PRTRPB_PFC_PFC_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_PFC_PFC_SHIFT)
 
-#define I40E_PRTRPB_RUP2TC             0x000AC440
+#define I40E_PRTRPB_RUP2TC             0x000AC440 /* Reset: CORER */
 #define I40E_PRTRPB_RUP2TC_UP0TC_SHIFT 0
 #define I40E_PRTRPB_RUP2TC_UP0TC_MASK  I40E_MASK(0x7, I40E_PRTRPB_RUP2TC_UP0TC_SHIFT)
 #define I40E_PRTRPB_RUP2TC_UP1TC_SHIFT 3
@@ -8669,22 +9026,22 @@
 #define I40E_PRTRPB_RUP2TC_UP7TC_SHIFT 21
 #define I40E_PRTRPB_RUP2TC_UP7TC_MASK  I40E_MASK(0x7, I40E_PRTRPB_RUP2TC_UP7TC_SHIFT)
 
-#define I40E_PRTRPB_SFC           0x000AC460
+#define I40E_PRTRPB_SFC           0x000AC460 /* Reset: CORER */
 #define I40E_PRTRPB_SFC_SFC_SHIFT 0
 #define I40E_PRTRPB_SFC_SFC_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SFC_SFC_SHIFT)
 
-#define I40E_PRTRPB_SOC(_i)           (0x000AC6C0 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRTRPB_SOC(_i)           (0x000AC6C0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRTRPB_SOC_MAX_INDEX     7
 #define I40E_PRTRPB_SOC_SOC_TCN_SHIFT 0
 #define I40E_PRTRPB_SOC_SOC_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SOC_SOC_TCN_SHIFT)
 
-#define I40E_PRTRPB_TC2PFC              0x000AC200
+#define I40E_PRTRPB_TC2PFC              0x000AC200 /* Reset: CORER */
 #define I40E_PRTRPB_TC2PFC_TC2PFC_SHIFT 0
 #define I40E_PRTRPB_TC2PFC_TC2PFC_MASK  I40E_MASK(0xFF, I40E_PRTRPB_TC2PFC_TC2PFC_SHIFT)
 
 /* PF - Rx Filters Registers */
 
-#define I40E_GL_PRS_FVBM(_i)                 (0x00269760 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GL_PRS_FVBM(_i)                 (0x00269760 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GL_PRS_FVBM_MAX_INDEX           3
 #define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT  0
 #define I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK   I40E_MASK(0x7F, I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT)
@@ -8693,17 +9050,17 @@
 #define I40E_GL_PRS_FVBM_MSK_ENA_SHIFT       31
 #define I40E_GL_PRS_FVBM_MSK_ENA_MASK        I40E_MASK(0x1, I40E_GL_PRS_FVBM_MSK_ENA_SHIFT)
 
-#define I40E_GLCM_LAN_FCOEQCNT                    0x0010C438
+#define I40E_GLCM_LAN_FCOEQCNT                    0x0010C438 /* Reset: CORER */
 #define I40E_GLCM_LAN_FCOEQCNT_FCOE_DDP_CNT_SHIFT 10
 #define I40E_GLCM_LAN_FCOEQCNT_FCOE_DDP_CNT_MASK  I40E_MASK(0x3FF, I40E_GLCM_LAN_FCOEQCNT_FCOE_DDP_CNT_SHIFT)
 
-#define I40E_GLCM_LAN_LANQCNT                 0x0010C434
+#define I40E_GLCM_LAN_LANQCNT                 0x0010C434 /* Reset: CORER */
 #define I40E_GLCM_LAN_LANQCNT_LANTX_CNT_SHIFT 0
 #define I40E_GLCM_LAN_LANQCNT_LANTX_CNT_MASK  I40E_MASK(0x3FF, I40E_GLCM_LAN_LANQCNT_LANTX_CNT_SHIFT)
 #define I40E_GLCM_LAN_LANQCNT_LANRX_CNT_SHIFT 10
 #define I40E_GLCM_LAN_LANQCNT_LANRX_CNT_MASK  I40E_MASK(0x3FF, I40E_GLCM_LAN_LANQCNT_LANRX_CNT_SHIFT)
 
-#define I40E_GLFOC_CACHE_CTL                     0x000AA000
+#define I40E_GLFOC_CACHE_CTL                     0x000AA000 /* Reset: CORER */
 #define I40E_GLFOC_CACHE_CTL_FD_ALLOCATION_SHIFT 0
 #define I40E_GLFOC_CACHE_CTL_FD_ALLOCATION_MASK  I40E_MASK(0x3, I40E_GLFOC_CACHE_CTL_FD_ALLOCATION_SHIFT)
 #define I40E_GLFOC_CACHE_CTL_SCALE_FACTOR_SHIFT  2
@@ -8715,68 +9072,68 @@
 #define I40E_GLFOC_CACHE_CTL_DBGMUX_SEL_HI_SHIFT 16
 #define I40E_GLFOC_CACHE_CTL_DBGMUX_SEL_HI_MASK  I40E_MASK(0x1F, I40E_GLFOC_CACHE_CTL_DBGMUX_SEL_HI_SHIFT)
 
-#define I40E_GLFOC_FSTAT              0x000AA004
+#define I40E_GLFOC_FSTAT              0x000AA004 /* Reset: CORER */
 #define I40E_GLFOC_FSTAT_PE_CNT_SHIFT 0
 #define I40E_GLFOC_FSTAT_PE_CNT_MASK  I40E_MASK(0x7FF, I40E_GLFOC_FSTAT_PE_CNT_SHIFT)
 #define I40E_GLFOC_FSTAT_FC_CNT_SHIFT 16
 #define I40E_GLFOC_FSTAT_FC_CNT_MASK  I40E_MASK(0x7FF, I40E_GLFOC_FSTAT_FC_CNT_SHIFT)
 
-#define I40E_GLQF_FC_INSET(_i, _j)      (0x002695A0 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...3 */
+#define I40E_GLQF_FC_INSET(_i, _j)      (0x002695A0 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...3 */ /* Reset: CORER */
 #define I40E_GLQF_FC_INSET_MAX_INDEX   1
 #define I40E_GLQF_FC_INSET_INSET_SHIFT 0
 #define I40E_GLQF_FC_INSET_INSET_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_FC_INSET_INSET_SHIFT)
 
-#define I40E_GLQF_FC_MSK(_i, _j)       (0x002690C0 + ((_i) * 4 + (_j) * 16)) /* _i=0...3, _j=0...3 */
+#define I40E_GLQF_FC_MSK(_i, _j)       (0x002690C0 + ((_i) * 4 + (_j) * 16)) /* _i=0...3, _j=0...3 */ /* Reset: CORER */
 #define I40E_GLQF_FC_MSK_MAX_INDEX    3
 #define I40E_GLQF_FC_MSK_MASK_SHIFT   0
 #define I40E_GLQF_FC_MSK_MASK_MASK    I40E_MASK(0xFFFF, I40E_GLQF_FC_MSK_MASK_SHIFT)
 #define I40E_GLQF_FC_MSK_OFFSET_SHIFT 16
 #define I40E_GLQF_FC_MSK_OFFSET_MASK  I40E_MASK(0x3F, I40E_GLQF_FC_MSK_OFFSET_SHIFT)
 
-#define I40E_GLQF_FCTYPE(_i)                (0x00269520 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLQF_FCTYPE(_i)                (0x00269520 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLQF_FCTYPE_MAX_INDEX          3
 #define I40E_GLQF_FCTYPE_PCTYPE_INDEX_SHIFT 0
 #define I40E_GLQF_FCTYPE_PCTYPE_INDEX_MASK  I40E_MASK(0x3F, I40E_GLQF_FCTYPE_PCTYPE_INDEX_SHIFT)
 #define I40E_GLQF_FCTYPE_PCTYPE_ENA_SHIFT   7
 #define I40E_GLQF_FCTYPE_PCTYPE_ENA_MASK    I40E_MASK(0x1, I40E_GLQF_FCTYPE_PCTYPE_ENA_SHIFT)
 
-#define I40E_GLQF_FD_MSK(_i, _j)       (0x00267200 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */
+#define I40E_GLQF_FD_MSK(_i, _j)       (0x00267200 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
 #define I40E_GLQF_FD_MSK_MAX_INDEX    1
 #define I40E_GLQF_FD_MSK_MASK_SHIFT   0
 #define I40E_GLQF_FD_MSK_MASK_MASK    I40E_MASK(0xFFFF, I40E_GLQF_FD_MSK_MASK_SHIFT)
 #define I40E_GLQF_FD_MSK_OFFSET_SHIFT 16
 #define I40E_GLQF_FD_MSK_OFFSET_MASK  I40E_MASK(0x3F, I40E_GLQF_FD_MSK_OFFSET_SHIFT)
 
-#define I40E_GLQF_FDCNT_1                 0x00269BB4
+#define I40E_GLQF_FDCNT_1                 0x00269BB4 /* Reset: CORER */
 #define I40E_GLQF_FDCNT_1_BUCKETCNT_SHIFT 0
 #define I40E_GLQF_FDCNT_1_BUCKETCNT_MASK  I40E_MASK(0x3FFF, I40E_GLQF_FDCNT_1_BUCKETCNT_SHIFT)
 
-#define I40E_GLQF_FDCNT_2                0x00269BBC
+#define I40E_GLQF_FDCNT_2                0x00269BBC /* Reset: CORER */
 #define I40E_GLQF_FDCNT_2_HITSBCNT_SHIFT 0
 #define I40E_GLQF_FDCNT_2_HITSBCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_FDCNT_2_HITSBCNT_SHIFT)
 
-#define I40E_GLQF_FDCNT_3                0x00269BC4
+#define I40E_GLQF_FDCNT_3                0x00269BC4 /* Reset: CORER */
 #define I40E_GLQF_FDCNT_3_HITLBCNT_SHIFT 0
 #define I40E_GLQF_FDCNT_3_HITLBCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_FDCNT_3_HITLBCNT_SHIFT)
 
-#define I40E_GLQF_FDENA(_i)          (0x002698A8 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GLQF_FDENA(_i)          (0x002698A8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GLQF_FDENA_MAX_INDEX    1
 #define I40E_GLQF_FDENA_FD_ENA_SHIFT 0
 #define I40E_GLQF_FDENA_FD_ENA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_FDENA_FD_ENA_SHIFT)
 
-#define I40E_GLQF_HASH_INSET(_i, _j)      (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */
+#define I40E_GLQF_HASH_INSET(_i, _j)      (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
 #define I40E_GLQF_HASH_INSET_MAX_INDEX   1
 #define I40E_GLQF_HASH_INSET_INSET_SHIFT 0
 #define I40E_GLQF_HASH_INSET_INSET_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_HASH_INSET_INSET_SHIFT)
 
-#define I40E_GLQF_HASH_MSK(_i, _j)       (0x00267A00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */
+#define I40E_GLQF_HASH_MSK(_i, _j)       (0x00267A00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
 #define I40E_GLQF_HASH_MSK_MAX_INDEX    1
 #define I40E_GLQF_HASH_MSK_MASK_SHIFT   0
 #define I40E_GLQF_HASH_MSK_MASK_MASK    I40E_MASK(0xFFFF, I40E_GLQF_HASH_MSK_MASK_SHIFT)
 #define I40E_GLQF_HASH_MSK_OFFSET_SHIFT 16
 #define I40E_GLQF_HASH_MSK_OFFSET_MASK  I40E_MASK(0x3F, I40E_GLQF_HASH_MSK_OFFSET_SHIFT)
 
-#define I40E_GLQF_ORT(_i)               (0x00268900 + ((_i) * 4)) /* _i=0...63 */
+#define I40E_GLQF_ORT(_i)               (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
 #define I40E_GLQF_ORT_MAX_INDEX         63
 #define I40E_GLQF_ORT_PIT_INDX_SHIFT    0
 #define I40E_GLQF_ORT_PIT_INDX_MASK     I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT)
@@ -8785,23 +9142,23 @@
 #define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7
 #define I40E_GLQF_ORT_FLX_PAYLOAD_MASK  I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT)
 
-#define I40E_GLQF_PE_INSET(_i, _j)      (0x00269140 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...7 */
+#define I40E_GLQF_PE_INSET(_i, _j)      (0x00269140 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...7 */ /* Reset: CORER */
 #define I40E_GLQF_PE_INSET_MAX_INDEX   1
 #define I40E_GLQF_PE_INSET_INSET_SHIFT 0
 #define I40E_GLQF_PE_INSET_INSET_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_PE_INSET_INSET_SHIFT)
 
-#define I40E_GLQF_PE_MSK(_i, _j)       (0x002691C0 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...7 */
+#define I40E_GLQF_PE_MSK(_i, _j)       (0x002691C0 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...7 */ /* Reset: CORER */
 #define I40E_GLQF_PE_MSK_MAX_INDEX    1
 #define I40E_GLQF_PE_MSK_MASK_SHIFT   0
 #define I40E_GLQF_PE_MSK_MASK_MASK    I40E_MASK(0xFFFF, I40E_GLQF_PE_MSK_MASK_SHIFT)
 #define I40E_GLQF_PE_MSK_OFFSET_SHIFT 16
 #define I40E_GLQF_PE_MSK_OFFSET_MASK  I40E_MASK(0x3F, I40E_GLQF_PE_MSK_OFFSET_SHIFT)
 
-#define I40E_GLQF_PECNT_0                0x00269FA4
+#define I40E_GLQF_PECNT_0                0x00269FA4 /* Reset: CORER */
 #define I40E_GLQF_PECNT_0_PROG_CNT_SHIFT 0
 #define I40E_GLQF_PECNT_0_PROG_CNT_MASK  I40E_MASK(0x1F, I40E_GLQF_PECNT_0_PROG_CNT_SHIFT)
 
-#define I40E_GLQF_PECNT_1                   0x00269FAC
+#define I40E_GLQF_PECNT_1                   0x00269FAC /* Reset: CORER */
 #define I40E_GLQF_PECNT_1_ADD_OK_SHIFT      0
 #define I40E_GLQF_PECNT_1_ADD_OK_MASK       I40E_MASK(0x1F, I40E_GLQF_PECNT_1_ADD_OK_SHIFT)
 #define I40E_GLQF_PECNT_1_ADD_FAIL_SHIFT    8
@@ -8811,14 +9168,14 @@
 #define I40E_GLQF_PECNT_1_REMOVE_FAIL_SHIFT 24
 #define I40E_GLQF_PECNT_1_REMOVE_FAIL_MASK  I40E_MASK(0x1F, I40E_GLQF_PECNT_1_REMOVE_FAIL_SHIFT)
 
-#define I40E_GLQF_PETYPE(_i)                (0x00269560 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GLQF_PETYPE(_i)                (0x00269560 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GLQF_PETYPE_MAX_INDEX          7
 #define I40E_GLQF_PETYPE_PCTYPE_INDEX_SHIFT 0
 #define I40E_GLQF_PETYPE_PCTYPE_INDEX_MASK  I40E_MASK(0x3F, I40E_GLQF_PETYPE_PCTYPE_INDEX_SHIFT)
 #define I40E_GLQF_PETYPE_PCTYPE_ENA_SHIFT   7
 #define I40E_GLQF_PETYPE_PCTYPE_ENA_MASK    I40E_MASK(0x1, I40E_GLQF_PETYPE_PCTYPE_ENA_SHIFT)
 
-#define I40E_GLQF_PIT(_i)              (0x00268C80 + ((_i) * 4)) /* _i=0...23 */
+#define I40E_GLQF_PIT(_i)              (0x00268C80 + ((_i) * 4)) /* _i=0...23 */ /* Reset: CORER */
 #define I40E_GLQF_PIT_MAX_INDEX        23
 #define I40E_GLQF_PIT_SOURCE_OFF_SHIFT 0
 #define I40E_GLQF_PIT_SOURCE_OFF_MASK  I40E_MASK(0x1F, I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
@@ -8827,17 +9184,17 @@
 #define I40E_GLQF_PIT_DEST_OFF_SHIFT   10
 #define I40E_GLQF_PIT_DEST_OFF_MASK    I40E_MASK(0x3F, I40E_GLQF_PIT_DEST_OFF_SHIFT)
 
-#define I40E_GLQF_PTYPE(_i, _j)           (0x00268200 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */
+#define I40E_GLQF_PTYPE(_i, _j)           (0x00268200 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
 #define I40E_GLQF_PTYPE_MAX_INDEX        1
 #define I40E_GLQF_PTYPE_PROT_LAYER_SHIFT 0
 #define I40E_GLQF_PTYPE_PROT_LAYER_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_PTYPE_PROT_LAYER_SHIFT)
 
-#define I40E_GLQF_PTYPE_ENA(_i, _j)           (0x00268600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */
+#define I40E_GLQF_PTYPE_ENA(_i, _j)           (0x00268600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
 #define I40E_GLQF_PTYPE_ENA_MAX_INDEX        1
 #define I40E_GLQF_PTYPE_ENA_PROT_LAYER_SHIFT 0
 #define I40E_GLQF_PTYPE_ENA_PROT_LAYER_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_PTYPE_ENA_PROT_LAYER_SHIFT)
 
-#define I40E_PFQF_CTL_0_PMAT                   0x000C0700
+#define I40E_PFQF_CTL_0_PMAT                   0x000C0700 /* Reset: CORER */
 #define I40E_PFQF_CTL_0_PMAT_PEHSIZE_SHIFT     0
 #define I40E_PFQF_CTL_0_PMAT_PEHSIZE_MASK      I40E_MASK(0x1F, I40E_PFQF_CTL_0_PMAT_PEHSIZE_SHIFT)
 #define I40E_PFQF_CTL_0_PMAT_PEDSIZE_SHIFT     5
@@ -8859,7 +9216,7 @@
 #define I40E_PFQF_CTL_0_PMAT_VFFCDSIZE_SHIFT   24
 #define I40E_PFQF_CTL_0_PMAT_VFFCDSIZE_MASK    I40E_MASK(0x3, I40E_PFQF_CTL_0_PMAT_VFFCDSIZE_SHIFT)
 
-#define I40E_PFQF_CTL_0_RCU                   0x00245C80
+#define I40E_PFQF_CTL_0_RCU                   0x00245C80 /* Reset: CORER */
 #define I40E_PFQF_CTL_0_RCU_PEHSIZE_SHIFT     0
 #define I40E_PFQF_CTL_0_RCU_PEHSIZE_MASK      I40E_MASK(0x1F, I40E_PFQF_CTL_0_RCU_PEHSIZE_SHIFT)
 #define I40E_PFQF_CTL_0_RCU_PEDSIZE_SHIFT     5
@@ -8881,44 +9238,79 @@
 #define I40E_PFQF_CTL_0_RCU_VFFCDSIZE_SHIFT   24
 #define I40E_PFQF_CTL_0_RCU_VFFCDSIZE_MASK    I40E_MASK(0x3, I40E_PFQF_CTL_0_RCU_VFFCDSIZE_SHIFT)
 
-#define I40E_PFQF_DDPCNT               0x00246180
+#define I40E_PFQF_DDPCNT               0x00246180 /* Reset: CORER */
 #define I40E_PFQF_DDPCNT_DDP_CNT_SHIFT 0
 #define I40E_PFQF_DDPCNT_DDP_CNT_MASK  I40E_MASK(0x1FFF, I40E_PFQF_DDPCNT_DDP_CNT_SHIFT)
 
-#define I40E_PFQF_FCCNT_0                 0x00245E80
+#define I40E_PFQF_FCCNT_0                 0x00245E80 /* Reset: CORER */
 #define I40E_PFQF_FCCNT_0_BUCKETCNT_SHIFT 0
 #define I40E_PFQF_FCCNT_0_BUCKETCNT_MASK  I40E_MASK(0x1FFF, I40E_PFQF_FCCNT_0_BUCKETCNT_SHIFT)
 
-#define I40E_PFQF_FCCNT_1                0x00245F80
+#define I40E_PFQF_FCCNT_1                0x00245F80 /* Reset: PFR */
 #define I40E_PFQF_FCCNT_1_HITSBCNT_SHIFT 0
 #define I40E_PFQF_FCCNT_1_HITSBCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFQF_FCCNT_1_HITSBCNT_SHIFT)
 
-#define I40E_PFQF_FCCNT_2                0x00246080
+#define I40E_PFQF_FCCNT_2                0x00246080 /* Reset: PFR */
 #define I40E_PFQF_FCCNT_2_HITLBCNT_SHIFT 0
 #define I40E_PFQF_FCCNT_2_HITLBCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFQF_FCCNT_2_HITLBCNT_SHIFT)
 
-#define I40E_PFQF_PECNT_0                 0x00246480
+#define I40E_PFQF_HREGION(_i)                  (0x00245400 + ((_i) * 128)) /* _i=0...7 */ /* Reset: CORER */
+#define I40E_PFQF_HREGION_MAX_INDEX            7
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
+#define I40E_PFQF_HREGION_REGION_0_SHIFT       1
+#define I40E_PFQF_HREGION_REGION_0_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_0_SHIFT)
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
+#define I40E_PFQF_HREGION_REGION_1_SHIFT       5
+#define I40E_PFQF_HREGION_REGION_1_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_1_SHIFT)
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
+#define I40E_PFQF_HREGION_REGION_2_SHIFT       9
+#define I40E_PFQF_HREGION_REGION_2_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_2_SHIFT)
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
+#define I40E_PFQF_HREGION_REGION_3_SHIFT       13
+#define I40E_PFQF_HREGION_REGION_3_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_3_SHIFT)
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
+#define I40E_PFQF_HREGION_REGION_4_SHIFT       17
+#define I40E_PFQF_HREGION_REGION_4_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_4_SHIFT)
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
+#define I40E_PFQF_HREGION_REGION_5_SHIFT       21
+#define I40E_PFQF_HREGION_REGION_5_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_5_SHIFT)
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
+#define I40E_PFQF_HREGION_REGION_6_SHIFT       25
+#define I40E_PFQF_HREGION_REGION_6_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_6_SHIFT)
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
+#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK  I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
+#define I40E_PFQF_HREGION_REGION_7_SHIFT       29
+#define I40E_PFQF_HREGION_REGION_7_MASK        I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_7_SHIFT)
+
+#define I40E_PFQF_PECNT_0                 0x00246480 /* Reset: CORER */
 #define I40E_PFQF_PECNT_0_BUCKETCNT_SHIFT 0
 #define I40E_PFQF_PECNT_0_BUCKETCNT_MASK  I40E_MASK(0x7FFFF, I40E_PFQF_PECNT_0_BUCKETCNT_SHIFT)
 
-#define I40E_PFQF_PECNT_1                0x00246580
+#define I40E_PFQF_PECNT_1                0x00246580 /* Reset: PFR */
 #define I40E_PFQF_PECNT_1_HITSBCNT_SHIFT 0
 #define I40E_PFQF_PECNT_1_HITSBCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFQF_PECNT_1_HITSBCNT_SHIFT)
 
-#define I40E_PFQF_PECNT_2                0x00246680
+#define I40E_PFQF_PECNT_2                0x00246680 /* Reset: PFR */
 #define I40E_PFQF_PECNT_2_HITLBCNT_SHIFT 0
 #define I40E_PFQF_PECNT_2_HITLBCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFQF_PECNT_2_HITLBCNT_SHIFT)
 
-#define I40E_PFQF_PECNT_CNTX              0x0026CA80
+#define I40E_PFQF_PECNT_CNTX              0x0026CA80 /* Reset: CORER */
 #define I40E_PFQF_PECNT_CNTX_FLTCNT_SHIFT 0
 #define I40E_PFQF_PECNT_CNTX_FLTCNT_MASK  I40E_MASK(0x7FFFF, I40E_PFQF_PECNT_CNTX_FLTCNT_SHIFT)
 
-#define I40E_PRTQF_FD_INSET(_i, _j)      (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */
+#define I40E_PRTQF_FD_INSET(_i, _j)      (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
 #define I40E_PRTQF_FD_INSET_MAX_INDEX   63
 #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0
 #define I40E_PRTQF_FD_INSET_INSET_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)
 
-#define I40E_VPQF_CTL_RCU(_VF)          (0x00231C00 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPQF_CTL_RCU(_VF)          (0x00231C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VPQF_CTL_RCU_MAX_INDEX     127
 #define I40E_VPQF_CTL_RCU_PEHSIZE_SHIFT 0
 #define I40E_VPQF_CTL_RCU_PEHSIZE_MASK  I40E_MASK(0x1F, I40E_VPQF_CTL_RCU_PEHSIZE_SHIFT)
@@ -8929,56 +9321,56 @@
 #define I40E_VPQF_CTL_RCU_FCDSIZE_SHIFT 14
 #define I40E_VPQF_CTL_RCU_FCDSIZE_MASK  I40E_MASK(0x3, I40E_VPQF_CTL_RCU_FCDSIZE_SHIFT)
 
-#define I40E_VPQF_DDPCNT1(_VF)          (0x00231400 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPQF_DDPCNT1(_VF)          (0x00231400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VPQF_DDPCNT1_MAX_INDEX     127
 #define I40E_VPQF_DDPCNT1_DDP_CNT_SHIFT 0
 #define I40E_VPQF_DDPCNT1_DDP_CNT_MASK  I40E_MASK(0x1FFF, I40E_VPQF_DDPCNT1_DDP_CNT_SHIFT)
 
-#define I40E_VPQF_FCCNT_0(_VF)            (0x0026A400 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPQF_FCCNT_0(_VF)            (0x0026A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VPQF_FCCNT_0_MAX_INDEX       127
 #define I40E_VPQF_FCCNT_0_BUCKETCNT_SHIFT 0
 #define I40E_VPQF_FCCNT_0_BUCKETCNT_MASK  I40E_MASK(0x1FFF, I40E_VPQF_FCCNT_0_BUCKETCNT_SHIFT)
 
-#define I40E_VPQF_PECNT_0(_VF)            (0x0026B400 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPQF_PECNT_0(_VF)            (0x0026B400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VPQF_PECNT_0_MAX_INDEX       127
 #define I40E_VPQF_PECNT_0_BUCKETCNT_SHIFT 0
 #define I40E_VPQF_PECNT_0_BUCKETCNT_MASK  I40E_MASK(0x7FFFF, I40E_VPQF_PECNT_0_BUCKETCNT_SHIFT)
 
-#define I40E_VPQF_PECNT_1(_VF)         (0x0026BC00 + ((_VF) * 4)) /* _i=0...127 */
+#define I40E_VPQF_PECNT_1(_VF)         (0x0026BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
 #define I40E_VPQF_PECNT_1_MAX_INDEX    127
 #define I40E_VPQF_PECNT_1_FLTCNT_SHIFT 0
 #define I40E_VPQF_PECNT_1_FLTCNT_MASK  I40E_MASK(0x7FFFF, I40E_VPQF_PECNT_1_FLTCNT_SHIFT)
 
 /* PF - Statistics Registers  */
 
-#define I40E_GLPRT_AORCH(_i)         (0x00300A44 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_AORCH(_i)         (0x00300A44 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_AORCH_MAX_INDEX   3
 #define I40E_GLPRT_AORCH_AORCH_SHIFT 0
 #define I40E_GLPRT_AORCH_AORCH_MASK  I40E_MASK(0xFFFF, I40E_GLPRT_AORCH_AORCH_SHIFT)
 
-#define I40E_GLPRT_AORCL(_i)         (0x00300A40 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_AORCL(_i)         (0x00300A40 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_AORCL_MAX_INDEX   3
 #define I40E_GLPRT_AORCL_VGORC_SHIFT 0
 #define I40E_GLPRT_AORCL_VGORC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_AORCL_VGORC_SHIFT)
 
-#define I40E_GLPRT_ERRBC(_i)         (0x003000C0 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_ERRBC(_i)         (0x003000C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_ERRBC_MAX_INDEX   3
 #define I40E_GLPRT_ERRBC_ERRBC_SHIFT 0
 #define I40E_GLPRT_ERRBC_ERRBC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ERRBC_ERRBC_SHIFT)
 
-#define I40E_GLPRT_MSPDC(_i)         (0x00300060 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_MSPDC(_i)         (0x00300060 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_MSPDC_MAX_INDEX   3
 #define I40E_GLPRT_MSPDC_MSPDC_SHIFT 0
 #define I40E_GLPRT_MSPDC_MSPDC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MSPDC_MSPDC_SHIFT)
 
-#define I40E_GLPRT_STDC(_i)        (0x00300640 + ((_i) * 8)) /* _i=0...3 */
+#define I40E_GLPRT_STDC(_i)        (0x00300640 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLPRT_STDC_MAX_INDEX  3
 #define I40E_GLPRT_STDC_STDC_SHIFT 0
 #define I40E_GLPRT_STDC_STDC_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPRT_STDC_STDC_SHIFT)
 
 /* PF - Switch Registers */
 
-#define I40E_EMP_MTG_FLU_ICH                       0x00269BE4
+#define I40E_EMP_MTG_FLU_ICH                       0x00269BE4 /* Reset: CORER */
 #define I40E_EMP_MTG_FLU_ICH_PROTOCOL_ID_SHIFT     0
 #define I40E_EMP_MTG_FLU_ICH_PROTOCOL_ID_MASK      I40E_MASK(0x3F, I40E_EMP_MTG_FLU_ICH_PROTOCOL_ID_SHIFT)
 #define I40E_EMP_MTG_FLU_ICH_IGNORE_PROTOCOL_SHIFT 6
@@ -8986,7 +9378,7 @@
 #define I40E_EMP_MTG_FLU_ICH_USE_MAN_SHIFT         7
 #define I40E_EMP_MTG_FLU_ICH_USE_MAN_MASK          I40E_MASK(0x1, I40E_EMP_MTG_FLU_ICH_USE_MAN_SHIFT)
 
-#define I40E_EMP_MTG_FLU_ICL                    0x00269BDC
+#define I40E_EMP_MTG_FLU_ICL                    0x00269BDC /* Reset: CORER */
 #define I40E_EMP_MTG_FLU_ICL_W0_OFFSET_SHIFT    0
 #define I40E_EMP_MTG_FLU_ICL_W0_OFFSET_MASK     I40E_MASK(0x3F, I40E_EMP_MTG_FLU_ICL_W0_OFFSET_SHIFT)
 #define I40E_EMP_MTG_FLU_ICL_W0_STATUS_SHIFT    6
@@ -9008,17 +9400,17 @@
 #define I40E_EMP_MTG_FLU_ICL_PORT_ENABLE_SHIFT  31
 #define I40E_EMP_MTG_FLU_ICL_PORT_ENABLE_MASK   I40E_MASK(0x1, I40E_EMP_MTG_FLU_ICL_PORT_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_CCTRL                0x00269770
+#define I40E_EMP_SWT_CCTRL                0x00269770 /* Reset: POR */
 #define I40E_EMP_SWT_CCTRL_LLVSI_SHIFT    10
 #define I40E_EMP_SWT_CCTRL_LLVSI_MASK     I40E_MASK(0x3FF, I40E_EMP_SWT_CCTRL_LLVSI_SHIFT)
 #define I40E_EMP_SWT_CCTRL_PROXYVSI_SHIFT 20
 #define I40E_EMP_SWT_CCTRL_PROXYVSI_MASK  I40E_MASK(0x3FF, I40E_EMP_SWT_CCTRL_PROXYVSI_SHIFT)
 
-#define I40E_EMP_SWT_CGEN            0x0006D000
+#define I40E_EMP_SWT_CGEN            0x0006D000 /* Reset: POR */
 #define I40E_EMP_SWT_CGEN_GLEN_SHIFT 0
 #define I40E_EMP_SWT_CGEN_GLEN_MASK  I40E_MASK(0x1, I40E_EMP_SWT_CGEN_GLEN_SHIFT)
 
-#define I40E_EMP_SWT_CLLE(_i)               (0x00269790 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_EMP_SWT_CLLE(_i)               (0x00269790 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_EMP_SWT_CLLE_MAX_INDEX         3
 #define I40E_EMP_SWT_CLLE_TAG_SHIFT         0
 #define I40E_EMP_SWT_CLLE_TAG_MASK          I40E_MASK(0xFFFF, I40E_EMP_SWT_CLLE_TAG_SHIFT)
@@ -9029,18 +9421,18 @@
 #define I40E_EMP_SWT_CLLE_ENABLE_SHIFT      31
 #define I40E_EMP_SWT_CLLE_ENABLE_MASK       I40E_MASK(0x1, I40E_EMP_SWT_CLLE_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_CMASK                        0x0006D180
+#define I40E_EMP_SWT_CMASK                        0x0006D180 /* Reset: POR */
 #define I40E_EMP_SWT_CMASK_UNICASTTAGMASK_SHIFT   0
 #define I40E_EMP_SWT_CMASK_UNICASTTAGMASK_MASK    I40E_MASK(0xFFFF, I40E_EMP_SWT_CMASK_UNICASTTAGMASK_SHIFT)
 #define I40E_EMP_SWT_CMASK_MULTICASTTAGMASK_SHIFT 16
 #define I40E_EMP_SWT_CMASK_MULTICASTTAGMASK_MASK  I40E_MASK(0xFFFF, I40E_EMP_SWT_CMASK_MULTICASTTAGMASK_SHIFT)
 
-#define I40E_EMP_SWT_CMTTD(_i)          (0x0006E000 + ((_i) * 4)) /* _i=0...511 */
+#define I40E_EMP_SWT_CMTTD(_i)          (0x0006E000 + ((_i) * 4)) /* _i=0...511 */ /* Reset: POR */
 #define I40E_EMP_SWT_CMTTD_MAX_INDEX    511
 #define I40E_EMP_SWT_CMTTD_PFLIST_SHIFT 0
 #define I40E_EMP_SWT_CMTTD_PFLIST_MASK  I40E_MASK(0xFFFF, I40E_EMP_SWT_CMTTD_PFLIST_SHIFT)
 
-#define I40E_EMP_SWT_CMTTL(_i)          (0x0006D800 + ((_i) * 4)) /* _i=0...511 */
+#define I40E_EMP_SWT_CMTTL(_i)          (0x0006D800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: POR */
 #define I40E_EMP_SWT_CMTTL_MAX_INDEX    511
 #define I40E_EMP_SWT_CMTTL_MTAG_SHIFT   0
 #define I40E_EMP_SWT_CMTTL_MTAG_MASK    I40E_MASK(0xFFFF, I40E_EMP_SWT_CMTTL_MTAG_SHIFT)
@@ -9049,7 +9441,7 @@
 #define I40E_EMP_SWT_CMTTL_ENABLE_SHIFT 18
 #define I40E_EMP_SWT_CMTTL_ENABLE_MASK  I40E_MASK(0x1, I40E_EMP_SWT_CMTTL_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_COFFSET                          0x0006D200
+#define I40E_EMP_SWT_COFFSET                          0x0006D200 /* Reset: POR */
 #define I40E_EMP_SWT_COFFSET_UNICASTTAGOFFSET_SHIFT   0
 #define I40E_EMP_SWT_COFFSET_UNICASTTAGOFFSET_MASK    I40E_MASK(0x1F, I40E_EMP_SWT_COFFSET_UNICASTTAGOFFSET_SHIFT)
 #define I40E_EMP_SWT_COFFSET_RESERVED_2_SHIFT         5
@@ -9057,7 +9449,7 @@
 #define I40E_EMP_SWT_COFFSET_MULTICASTTAGOFFSET_SHIFT 8
 #define I40E_EMP_SWT_COFFSET_MULTICASTTAGOFFSET_MASK  I40E_MASK(0x1F, I40E_EMP_SWT_COFFSET_MULTICASTTAGOFFSET_SHIFT)
 
-#define I40E_EMP_SWT_CPFE(_i)               (0x001C09E0 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_EMP_SWT_CPFE(_i)               (0x001C09E0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: POR */
 #define I40E_EMP_SWT_CPFE_MAX_INDEX         15
 #define I40E_EMP_SWT_CPFE_TAG_SHIFT         0
 #define I40E_EMP_SWT_CPFE_TAG_MASK          I40E_MASK(0xFFFF, I40E_EMP_SWT_CPFE_TAG_SHIFT)
@@ -9068,7 +9460,7 @@
 #define I40E_EMP_SWT_CPFE_ENABLE_SHIFT      31
 #define I40E_EMP_SWT_CPFE_ENABLE_MASK       I40E_MASK(0x1, I40E_EMP_SWT_CPFE_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_CPFE_RCU(_i)               (0x00269040 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_EMP_SWT_CPFE_RCU(_i)               (0x00269040 + ((_i) * 4)) /* _i=0...15 */ /* Reset: POR */
 #define I40E_EMP_SWT_CPFE_RCU_MAX_INDEX         15
 #define I40E_EMP_SWT_CPFE_RCU_TAG_SHIFT         0
 #define I40E_EMP_SWT_CPFE_RCU_TAG_MASK          I40E_MASK(0xFFFF, I40E_EMP_SWT_CPFE_RCU_TAG_SHIFT)
@@ -9079,7 +9471,7 @@
 #define I40E_EMP_SWT_CPFE_RCU_ENABLE_SHIFT      31
 #define I40E_EMP_SWT_CPFE_RCU_ENABLE_MASK       I40E_MASK(0x1, I40E_EMP_SWT_CPFE_RCU_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_CPFE_WUC(_i)               (0x0006D080 + ((_i) * 4)) /* _i=0...15 */
+#define I40E_EMP_SWT_CPFE_WUC(_i)               (0x0006D080 + ((_i) * 4)) /* _i=0...15 */ /* Reset: POR */
 #define I40E_EMP_SWT_CPFE_WUC_MAX_INDEX         15
 #define I40E_EMP_SWT_CPFE_WUC_TAG_SHIFT         0
 #define I40E_EMP_SWT_CPFE_WUC_TAG_MASK          I40E_MASK(0xFFFF, I40E_EMP_SWT_CPFE_WUC_TAG_SHIFT)
@@ -9090,7 +9482,7 @@
 #define I40E_EMP_SWT_CPFE_WUC_ENABLE_SHIFT      31
 #define I40E_EMP_SWT_CPFE_WUC_ENABLE_MASK       I40E_MASK(0x1, I40E_EMP_SWT_CPFE_WUC_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_CPTE(_i)               (0x002697B0 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_EMP_SWT_CPTE(_i)               (0x002697B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_EMP_SWT_CPTE_MAX_INDEX         3
 #define I40E_EMP_SWT_CPTE_TAG_SHIFT         0
 #define I40E_EMP_SWT_CPTE_TAG_MASK          I40E_MASK(0xFFFF, I40E_EMP_SWT_CPTE_TAG_SHIFT)
@@ -9101,7 +9493,7 @@
 #define I40E_EMP_SWT_CPTE_ENABLE_SHIFT      31
 #define I40E_EMP_SWT_CPTE_ENABLE_MASK       I40E_MASK(0x1, I40E_EMP_SWT_CPTE_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_CPTE2(_i)               (0x002697D0 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_EMP_SWT_CPTE2(_i)               (0x002697D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
 #define I40E_EMP_SWT_CPTE2_MAX_INDEX         3
 #define I40E_EMP_SWT_CPTE2_TAG_SHIFT         0
 #define I40E_EMP_SWT_CPTE2_TAG_MASK          I40E_MASK(0xFFFF, I40E_EMP_SWT_CPTE2_TAG_SHIFT)
@@ -9112,13 +9504,13 @@
 #define I40E_EMP_SWT_CPTE2_ENABLE_SHIFT      31
 #define I40E_EMP_SWT_CPTE2_ENABLE_MASK       I40E_MASK(0x1, I40E_EMP_SWT_CPTE2_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_CTAG                 0x00269B64
+#define I40E_EMP_SWT_CTAG                 0x00269B64 /* Reset: POR */
 #define I40E_EMP_SWT_CTAG_TAG_INDEX_SHIFT 0
 #define I40E_EMP_SWT_CTAG_TAG_INDEX_MASK  I40E_MASK(0x3F, I40E_EMP_SWT_CTAG_TAG_INDEX_SHIFT)
 #define I40E_EMP_SWT_CTAG_TAG_MASK_SHIFT  10
 #define I40E_EMP_SWT_CTAG_TAG_MASK_MASK   I40E_MASK(0xFFFF, I40E_EMP_SWT_CTAG_TAG_MASK_SHIFT)
 
-#define I40E_EMP_SWT_CUPD                            0x0006D100
+#define I40E_EMP_SWT_CUPD                            0x0006D100 /* Reset: POR */
 #define I40E_EMP_SWT_CUPD_UNTAGGED_PORT0_PF_SHIFT    0
 #define I40E_EMP_SWT_CUPD_UNTAGGED_PORT0_PF_MASK     I40E_MASK(0xF, I40E_EMP_SWT_CUPD_UNTAGGED_PORT0_PF_SHIFT)
 #define I40E_EMP_SWT_CUPD_UNTAGGED_PORT1_PF_SHIFT    4
@@ -9140,11 +9532,11 @@
 #define I40E_EMP_SWT_CUPD_ACCEPTUNMATCHEDMCTST_SHIFT 31
 #define I40E_EMP_SWT_CUPD_ACCEPTUNMATCHEDMCTST_MASK  I40E_MASK(0x1, I40E_EMP_SWT_CUPD_ACCEPTUNMATCHEDMCTST_SHIFT)
 
-#define I40E_EMP_SWT_ETHMATCH                0x00269B6C
+#define I40E_EMP_SWT_ETHMATCH                0x00269B6C /* Reset: POR */
 #define I40E_EMP_SWT_ETHMATCH_ETHMATCH_SHIFT 0
 #define I40E_EMP_SWT_ETHMATCH_ETHMATCH_MASK  I40E_MASK(0xFFFF, I40E_EMP_SWT_ETHMATCH_ETHMATCH_SHIFT)
 
-#define I40E_EMP_SWT_FLU_L1_ICH_PHASE0(_i)                   (0x002695E0 + ((_i) * 4)) /* _i=0...4 */
+#define I40E_EMP_SWT_FLU_L1_ICH_PHASE0(_i)                   (0x002695E0 + ((_i) * 4)) /* _i=0...4 */ /* Reset: CORER */
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE0_MAX_INDEX             4
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE0_PROTOCOL_ID_SHIFT     0
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE0_PROTOCOL_ID_MASK      I40E_MASK(0x3F, I40E_EMP_SWT_FLU_L1_ICH_PHASE0_PROTOCOL_ID_SHIFT)
@@ -9153,7 +9545,7 @@
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE0_USE_MAN_SHIFT         7
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE0_USE_MAN_MASK          I40E_MASK(0x1, I40E_EMP_SWT_FLU_L1_ICH_PHASE0_USE_MAN_SHIFT)
 
-#define I40E_EMP_SWT_FLU_L1_ICH_PHASE1(_i)                   (0x00269660 + ((_i) * 4)) /* _i=0...4 */
+#define I40E_EMP_SWT_FLU_L1_ICH_PHASE1(_i)                   (0x00269660 + ((_i) * 4)) /* _i=0...4 */ /* Reset: CORER */
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE1_MAX_INDEX             4
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE1_PROTOCOL_ID_SHIFT     0
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE1_PROTOCOL_ID_MASK      I40E_MASK(0x3F, I40E_EMP_SWT_FLU_L1_ICH_PHASE1_PROTOCOL_ID_SHIFT)
@@ -9162,7 +9554,7 @@
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE1_USE_MAN_SHIFT         7
 #define I40E_EMP_SWT_FLU_L1_ICH_PHASE1_USE_MAN_MASK          I40E_MASK(0x1, I40E_EMP_SWT_FLU_L1_ICH_PHASE1_USE_MAN_SHIFT)
 
-#define I40E_EMP_SWT_FLU_L1_ICL_PHASE0(_i)                (0x00269620 + ((_i) * 4)) /* _i=0...6 */
+#define I40E_EMP_SWT_FLU_L1_ICL_PHASE0(_i)                (0x00269620 + ((_i) * 4)) /* _i=0...6 */ /* Reset: CORER */
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE0_MAX_INDEX          6
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE0_W0_OFFSET_SHIFT    0
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE0_W0_OFFSET_MASK     I40E_MASK(0x3F, I40E_EMP_SWT_FLU_L1_ICL_PHASE0_W0_OFFSET_SHIFT)
@@ -9185,7 +9577,7 @@
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE0_PORT_ENABLE_SHIFT  31
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE0_PORT_ENABLE_MASK   I40E_MASK(0x1, I40E_EMP_SWT_FLU_L1_ICL_PHASE0_PORT_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_FLU_L1_ICL_PHASE1(_i)                (0x002696A0 + ((_i) * 4)) /* _i=0...6 */
+#define I40E_EMP_SWT_FLU_L1_ICL_PHASE1(_i)                (0x002696A0 + ((_i) * 4)) /* _i=0...6 */ /* Reset: CORER */
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE1_MAX_INDEX          6
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE1_W0_OFFSET_SHIFT    0
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE1_W0_OFFSET_MASK     I40E_MASK(0x3F, I40E_EMP_SWT_FLU_L1_ICL_PHASE1_W0_OFFSET_SHIFT)
@@ -9208,7 +9600,7 @@
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE1_PORT_ENABLE_SHIFT  31
 #define I40E_EMP_SWT_FLU_L1_ICL_PHASE1_PORT_ENABLE_MASK   I40E_MASK(0x1, I40E_EMP_SWT_FLU_L1_ICL_PHASE1_PORT_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_FLU_L2_IC_PHASE0(_i)                         (0x002696E0 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_EMP_SWT_FLU_L2_IC_PHASE0(_i)                         (0x002696E0 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE0_MAX_INDEX                   7
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE0_FIELD0_L1_OBJECT_TYPE_SHIFT 0
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE0_FIELD0_L1_OBJECT_TYPE_MASK  I40E_MASK(0xF, I40E_EMP_SWT_FLU_L2_IC_PHASE0_FIELD0_L1_OBJECT_TYPE_SHIFT)
@@ -9231,7 +9623,7 @@
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE0_PORT_ENABLE_SHIFT           31
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE0_PORT_ENABLE_MASK            I40E_MASK(0x1, I40E_EMP_SWT_FLU_L2_IC_PHASE0_PORT_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_FLU_L2_IC_PHASE1(_i)                         (0x00269720 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_EMP_SWT_FLU_L2_IC_PHASE1(_i)                         (0x00269720 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE1_MAX_INDEX                   7
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE1_FIELD0_L1_OBJECT_TYPE_SHIFT 0
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE1_FIELD0_L1_OBJECT_TYPE_MASK  I40E_MASK(0xF, I40E_EMP_SWT_FLU_L2_IC_PHASE1_FIELD0_L1_OBJECT_TYPE_SHIFT)
@@ -9254,27 +9646,27 @@
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE1_PORT_ENABLE_SHIFT           31
 #define I40E_EMP_SWT_FLU_L2_IC_PHASE1_PORT_ENABLE_MASK            I40E_MASK(0x1, I40E_EMP_SWT_FLU_L2_IC_PHASE1_PORT_ENABLE_SHIFT)
 
-#define I40E_EMP_SWT_LOCMD(_i)           (0x00269460 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_EMP_SWT_LOCMD(_i)           (0x00269460 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_EMP_SWT_LOCMD_MAX_INDEX     7
 #define I40E_EMP_SWT_LOCMD_COMMAND_SHIFT 0
 #define I40E_EMP_SWT_LOCMD_COMMAND_MASK  I40E_MASK(0xFFFFFFFF, I40E_EMP_SWT_LOCMD_COMMAND_SHIFT)
 
-#define I40E_EMP_SWT_LOFV(_i)               (0x00268D80 + ((_i) * 4)) /* _i=0...31 */
+#define I40E_EMP_SWT_LOFV(_i)               (0x00268D80 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
 #define I40E_EMP_SWT_LOFV_MAX_INDEX         31
 #define I40E_EMP_SWT_LOFV_FIELDVECTOR_SHIFT 0
 #define I40E_EMP_SWT_LOFV_FIELDVECTOR_MASK  I40E_MASK(0xFFFFFFFF, I40E_EMP_SWT_LOFV_FIELDVECTOR_SHIFT)
 
-#define I40E_EMP_SWT_MIREGVSI(_i, _j)             (0x00263000 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...383 */
+#define I40E_EMP_SWT_MIREGVSI(_i, _j)             (0x00263000 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...383 */ /* Reset: CORER */
 #define I40E_EMP_SWT_MIREGVSI_MAX_INDEX          1
 #define I40E_EMP_SWT_MIREGVSI_ENABLEDRULES_SHIFT 0
 #define I40E_EMP_SWT_MIREGVSI_ENABLEDRULES_MASK  I40E_MASK(0xFFFFFFFF, I40E_EMP_SWT_MIREGVSI_ENABLEDRULES_SHIFT)
 
-#define I40E_EMP_SWT_MIRIGVSI(_i, _j)             (0x00265000 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...383 */
+#define I40E_EMP_SWT_MIRIGVSI(_i, _j)             (0x00265000 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...383 */ /* Reset: CORER */
 #define I40E_EMP_SWT_MIRIGVSI_MAX_INDEX          1
 #define I40E_EMP_SWT_MIRIGVSI_ENABLEDRULES_SHIFT 0
 #define I40E_EMP_SWT_MIRIGVSI_ENABLEDRULES_MASK  I40E_MASK(0xFFFFFFFF, I40E_EMP_SWT_MIRIGVSI_ENABLEDRULES_SHIFT)
 
-#define I40E_EMP_SWT_MIRTARVSI(_i)                (0x00268B00 + ((_i) * 4)) /* _i=0...63 */
+#define I40E_EMP_SWT_MIRTARVSI(_i)                (0x00268B00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
 #define I40E_EMP_SWT_MIRTARVSI_MAX_INDEX          63
 #define I40E_EMP_SWT_MIRTARVSI_TARGETVSI_SHIFT    0
 #define I40E_EMP_SWT_MIRTARVSI_TARGETVSI_MASK     I40E_MASK(0x1FF, I40E_EMP_SWT_MIRTARVSI_TARGETVSI_SHIFT)
@@ -9287,42 +9679,42 @@
 #define I40E_EMP_SWT_MIRTARVSI_RULEENABLE_SHIFT   31
 #define I40E_EMP_SWT_MIRTARVSI_RULEENABLE_MASK    I40E_MASK(0x1, I40E_EMP_SWT_MIRTARVSI_RULEENABLE_SHIFT)
 
-#define I40E_EMP_SWT_STS(_i)               (0x002692C0 + ((_i) * 4)) /* _i=0...9 */
+#define I40E_EMP_SWT_STS(_i)               (0x002692C0 + ((_i) * 4)) /* _i=0...9 */ /* Reset: CORER */
 #define I40E_EMP_SWT_STS_MAX_INDEX         9
 #define I40E_EMP_SWT_STS_EMP_SWT_STS_SHIFT 0
 #define I40E_EMP_SWT_STS_EMP_SWT_STS_MASK  I40E_MASK(0xFFFFFFFF, I40E_EMP_SWT_STS_EMP_SWT_STS_SHIFT)
 
-#define I40E_GL_MTG_FLU_MSK_L                0x00269F44
+#define I40E_GL_MTG_FLU_MSK_L                0x00269F44 /* Reset: CORER */
 #define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT 0
 #define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT)
 
-#define I40E_GL_PRE_FLU_MSK_PH0_H(_i)             (0x00269EA0 + ((_i) * 4)) /* _i=0...6 */
+#define I40E_GL_PRE_FLU_MSK_PH0_H(_i)             (0x00269EA0 + ((_i) * 4)) /* _i=0...6 */ /* Reset: CORER */
 #define I40E_GL_PRE_FLU_MSK_PH0_H_MAX_INDEX       6
 #define I40E_GL_PRE_FLU_MSK_PH0_H_MASK_HIGH_SHIFT 0
 #define I40E_GL_PRE_FLU_MSK_PH0_H_MASK_HIGH_MASK  I40E_MASK(0xFFFF, I40E_GL_PRE_FLU_MSK_PH0_H_MASK_HIGH_SHIFT)
 
-#define I40E_GL_PRE_FLU_MSK_PH0_L(_i)            (0x00269E60 + ((_i) * 4)) /* _i=0...6 */
+#define I40E_GL_PRE_FLU_MSK_PH0_L(_i)            (0x00269E60 + ((_i) * 4)) /* _i=0...6 */ /* Reset: CORER */
 #define I40E_GL_PRE_FLU_MSK_PH0_L_MAX_INDEX      6
 #define I40E_GL_PRE_FLU_MSK_PH0_L_MASK_LOW_SHIFT 0
 #define I40E_GL_PRE_FLU_MSK_PH0_L_MASK_LOW_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_FLU_MSK_PH0_L_MASK_LOW_SHIFT)
 
-#define I40E_GL_PRE_FLU_MSK_PH1_H(_i)             (0x00269F20 + ((_i) * 4)) /* _i=0...6 */
+#define I40E_GL_PRE_FLU_MSK_PH1_H(_i)             (0x00269F20 + ((_i) * 4)) /* _i=0...6 */ /* Reset: CORER */
 #define I40E_GL_PRE_FLU_MSK_PH1_H_MAX_INDEX       6
 #define I40E_GL_PRE_FLU_MSK_PH1_H_MASK_HIGH_SHIFT 0
 #define I40E_GL_PRE_FLU_MSK_PH1_H_MASK_HIGH_MASK  I40E_MASK(0xFFFF, I40E_GL_PRE_FLU_MSK_PH1_H_MASK_HIGH_SHIFT)
 
-#define I40E_GL_PRE_FLU_MSK_PH1_L(_i)            (0x00269EE0 + ((_i) * 4)) /* _i=0...6 */
+#define I40E_GL_PRE_FLU_MSK_PH1_L(_i)            (0x00269EE0 + ((_i) * 4)) /* _i=0...6 */ /* Reset: CORER */
 #define I40E_GL_PRE_FLU_MSK_PH1_L_MAX_INDEX      6
 #define I40E_GL_PRE_FLU_MSK_PH1_L_MASK_LOW_SHIFT 0
 #define I40E_GL_PRE_FLU_MSK_PH1_L_MASK_LOW_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_FLU_MSK_PH1_L_MASK_LOW_SHIFT)
 
-#define I40E_GL_PRE_GEN_CFG                     0x002699A4
+#define I40E_GL_PRE_GEN_CFG                     0x002699A4 /* Reset: CORER */
 #define I40E_GL_PRE_GEN_CFG_FILTER_ENABLE_SHIFT 0
 #define I40E_GL_PRE_GEN_CFG_FILTER_ENABLE_MASK  I40E_MASK(0x1, I40E_GL_PRE_GEN_CFG_FILTER_ENABLE_SHIFT)
 #define I40E_GL_PRE_GEN_CFG_HASH_MODE_SHIFT     6
 #define I40E_GL_PRE_GEN_CFG_HASH_MODE_MASK      I40E_MASK(0x3, I40E_GL_PRE_GEN_CFG_HASH_MODE_SHIFT)
 
-#define I40E_GL_PRE_PRX_BIG_ENT_D0                  0x002699C4
+#define I40E_GL_PRE_PRX_BIG_ENT_D0                  0x002699C4 /* Reset: CORER */
 #define I40E_GL_PRE_PRX_BIG_ENT_D0_F0_SRC_IDX_SHIFT 0
 #define I40E_GL_PRE_PRX_BIG_ENT_D0_F0_SRC_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_PRX_BIG_ENT_D0_F0_SRC_IDX_SHIFT)
 #define I40E_GL_PRE_PRX_BIG_ENT_D0_F0_SRC_SEL_SHIFT 6
@@ -9346,7 +9738,7 @@
 #define I40E_GL_PRE_PRX_BIG_ENT_D0_F3_SRC_IDX_SHIFT 31
 #define I40E_GL_PRE_PRX_BIG_ENT_D0_F3_SRC_IDX_MASK  I40E_MASK(0x1, I40E_GL_PRE_PRX_BIG_ENT_D0_F3_SRC_IDX_SHIFT)
 
-#define I40E_GL_PRE_PRX_BIG_ENT_D1                  0x002699D4
+#define I40E_GL_PRE_PRX_BIG_ENT_D1                  0x002699D4 /* Reset: CORER */
 #define I40E_GL_PRE_PRX_BIG_ENT_D1_F4_SRC_IDX_SHIFT 0
 #define I40E_GL_PRE_PRX_BIG_ENT_D1_F4_SRC_IDX_MASK  I40E_MASK(0x3F, I40E_GL_PRE_PRX_BIG_ENT_D1_F4_SRC_IDX_SHIFT)
 #define I40E_GL_PRE_PRX_BIG_ENT_D1_F4_SRC_SEL_SHIFT 6
@@ -9370,19 +9762,19 @@
 #define I40E_GL_PRE_PRX_BIG_ENT_D1_F7_SRC_IDX_SHIFT 31
 #define I40E_GL_PRE_PRX_BIG_ENT_D1_F7_SRC_IDX_MASK  I40E_MASK(0x1, I40E_GL_PRE_PRX_BIG_ENT_D1_F7_SRC_IDX_SHIFT)
 
-#define I40E_GL_PRE_PRX_BIG_ENT_D3                0x00269A0C
+#define I40E_GL_PRE_PRX_BIG_ENT_D3                0x00269A0C /* Reset: CORER */
 #define I40E_GL_PRE_PRX_BIG_ENT_D3_BIT_MSK0_SHIFT 0
 #define I40E_GL_PRE_PRX_BIG_ENT_D3_BIT_MSK0_MASK  I40E_MASK(0xFF, I40E_GL_PRE_PRX_BIG_ENT_D3_BIT_MSK0_SHIFT)
 
-#define I40E_GL_PRE_PRX_BIG_HSH_KEY_D1          0x00269A34
+#define I40E_GL_PRE_PRX_BIG_HSH_KEY_D1          0x00269A34 /* Reset: CORER */
 #define I40E_GL_PRE_PRX_BIG_HSH_KEY_D1_H1_SHIFT 0
 #define I40E_GL_PRE_PRX_BIG_HSH_KEY_D1_H1_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_PRX_BIG_HSH_KEY_D1_H1_SHIFT)
 
-#define I40E_GL_PRE_PRX_BIG_HSH_KEY_D3          0x00269A54
+#define I40E_GL_PRE_PRX_BIG_HSH_KEY_D3          0x00269A54 /* Reset: CORER */
 #define I40E_GL_PRE_PRX_BIG_HSH_KEY_D3_H3_SHIFT 0
 #define I40E_GL_PRE_PRX_BIG_HSH_KEY_D3_H3_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_PRX_BIG_HSH_KEY_D3_H3_SHIFT)
 
-#define I40E_GL_PRE_PRX_H_PHASE0                       0x00269B74
+#define I40E_GL_PRE_PRX_H_PHASE0                       0x00269B74 /* Reset: CORER */
 #define I40E_GL_PRE_PRX_H_PHASE0_PROTOCOL_ID_SHIFT     0
 #define I40E_GL_PRE_PRX_H_PHASE0_PROTOCOL_ID_MASK      I40E_MASK(0x3F, I40E_GL_PRE_PRX_H_PHASE0_PROTOCOL_ID_SHIFT)
 #define I40E_GL_PRE_PRX_H_PHASE0_IGNORE_PROTOCOL_SHIFT 6
@@ -9396,7 +9788,7 @@
 #define I40E_GL_PRE_PRX_H_PHASE0_MASK1_BITS_SHIFT      24
 #define I40E_GL_PRE_PRX_H_PHASE0_MASK1_BITS_MASK       I40E_MASK(0xFF, I40E_GL_PRE_PRX_H_PHASE0_MASK1_BITS_SHIFT)
 
-#define I40E_GL_PRE_PRX_H_PHASE1                       0x00269B7C
+#define I40E_GL_PRE_PRX_H_PHASE1                       0x00269B7C /* Reset: CORER */
 #define I40E_GL_PRE_PRX_H_PHASE1_PROTOCOL_ID_SHIFT     0
 #define I40E_GL_PRE_PRX_H_PHASE1_PROTOCOL_ID_MASK      I40E_MASK(0x3F, I40E_GL_PRE_PRX_H_PHASE1_PROTOCOL_ID_SHIFT)
 #define I40E_GL_PRE_PRX_H_PHASE1_IGNORE_PROTOCOL_SHIFT 6
@@ -9410,11 +9802,11 @@
 #define I40E_GL_PRE_PRX_H_PHASE1_MASK1_BITS_SHIFT      24
 #define I40E_GL_PRE_PRX_H_PHASE1_MASK1_BITS_MASK       I40E_MASK(0xFF, I40E_GL_PRE_PRX_H_PHASE1_MASK1_BITS_SHIFT)
 
-#define I40E_GL_PRE_PRX_HSH_KEY_D0          0x00269A24
+#define I40E_GL_PRE_PRX_HSH_KEY_D0          0x00269A24 /* Reset: CORER */
 #define I40E_GL_PRE_PRX_HSH_KEY_D0_H0_SHIFT 0
 #define I40E_GL_PRE_PRX_HSH_KEY_D0_H0_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_PRX_HSH_KEY_D0_H0_SHIFT)
 
-#define I40E_GL_PRE_PRX_L_PHASE0                    0x00269B8C
+#define I40E_GL_PRE_PRX_L_PHASE0                    0x00269B8C /* Reset: CORER */
 #define I40E_GL_PRE_PRX_L_PHASE0_W0_OFFSET_SHIFT    0
 #define I40E_GL_PRE_PRX_L_PHASE0_W0_OFFSET_MASK     I40E_MASK(0x3F, I40E_GL_PRE_PRX_L_PHASE0_W0_OFFSET_SHIFT)
 #define I40E_GL_PRE_PRX_L_PHASE0_W0_STATUS_SHIFT    6
@@ -9442,7 +9834,7 @@
 #define I40E_GL_PRE_PRX_L_PHASE0_PORT_ENABLE_SHIFT  31
 #define I40E_GL_PRE_PRX_L_PHASE0_PORT_ENABLE_MASK   I40E_MASK(0x1, I40E_GL_PRE_PRX_L_PHASE0_PORT_ENABLE_SHIFT)
 
-#define I40E_GL_PRE_PRX_L_PHASE1                    0x00269B84
+#define I40E_GL_PRE_PRX_L_PHASE1                    0x00269B84 /* Reset: CORER */
 #define I40E_GL_PRE_PRX_L_PHASE1_W0_OFFSET_SHIFT    0
 #define I40E_GL_PRE_PRX_L_PHASE1_W0_OFFSET_MASK     I40E_MASK(0x3F, I40E_GL_PRE_PRX_L_PHASE1_W0_OFFSET_SHIFT)
 #define I40E_GL_PRE_PRX_L_PHASE1_W0_STATUS_SHIFT    6
@@ -9470,42 +9862,42 @@
 #define I40E_GL_PRE_PRX_L_PHASE1_PORT_ENABLE_SHIFT  31
 #define I40E_GL_PRE_PRX_L_PHASE1_PORT_ENABLE_MASK   I40E_MASK(0x1, I40E_GL_PRE_PRX_L_PHASE1_PORT_ENABLE_SHIFT)
 
-#define I40E_GL_SW_SWT_STS(_i)               (0x00269340 + ((_i) * 4)) /* _i=0...9 */
+#define I40E_GL_SW_SWT_STS(_i)               (0x00269340 + ((_i) * 4)) /* _i=0...9 */ /* Reset: CORER */
 #define I40E_GL_SW_SWT_STS_MAX_INDEX         9
 #define I40E_GL_SW_SWT_STS_EMP_SWT_STS_SHIFT 0
 #define I40E_GL_SW_SWT_STS_EMP_SWT_STS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SW_SWT_STS_EMP_SWT_STS_SHIFT)
 
-#define I40E_GL_SWR_FILTERS_NEED_HIT(_i)                    (0x0026CF00 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GL_SWR_FILTERS_NEED_HIT(_i)                    (0x0026CF00 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GL_SWR_FILTERS_NEED_HIT_MAX_INDEX              1
 #define I40E_GL_SWR_FILTERS_NEED_HIT_FILTERS_NEED_HIT_SHIFT 0
 #define I40E_GL_SWR_FILTERS_NEED_HIT_FILTERS_NEED_HIT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_FILTERS_NEED_HIT_FILTERS_NEED_HIT_SHIFT)
 
-#define I40E_GL_SWR_FILTERS_NEED_MISS(_i)                     (0x0026CF10 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GL_SWR_FILTERS_NEED_MISS(_i)                     (0x0026CF10 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GL_SWR_FILTERS_NEED_MISS_MAX_INDEX               1
 #define I40E_GL_SWR_FILTERS_NEED_MISS_FILTERS_NEED_MISS_SHIFT 0
 #define I40E_GL_SWR_FILTERS_NEED_MISS_FILTERS_NEED_MISS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_FILTERS_NEED_MISS_FILTERS_NEED_MISS_SHIFT)
 
-#define I40E_GL_SWR_HIT_FILTERS(_i)               (0x0026CF08 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GL_SWR_HIT_FILTERS(_i)               (0x0026CF08 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GL_SWR_HIT_FILTERS_MAX_INDEX         1
 #define I40E_GL_SWR_HIT_FILTERS_HIT_FILTERS_SHIFT 0
 #define I40E_GL_SWR_HIT_FILTERS_HIT_FILTERS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_HIT_FILTERS_HIT_FILTERS_SHIFT)
 
-#define I40E_GL_SWR_MISS_FILTERS(_i)                (0x0026CF18 + ((_i) * 4)) /* _i=0...1 */
+#define I40E_GL_SWR_MISS_FILTERS(_i)                (0x0026CF18 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
 #define I40E_GL_SWR_MISS_FILTERS_MAX_INDEX          1
 #define I40E_GL_SWR_MISS_FILTERS_MISS_FILTERS_SHIFT 0
 #define I40E_GL_SWR_MISS_FILTERS_MISS_FILTERS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_MISS_FILTERS_MISS_FILTERS_SHIFT)
 
-#define I40E_GL_SWR_PRI_JOIN_MAP(_i)                  (0x0026CE20 + ((_i) * 4)) /* _i=0...8 */
+#define I40E_GL_SWR_PRI_JOIN_MAP(_i)                  (0x0026CE20 + ((_i) * 4)) /* _i=0...8 */ /* Reset: CORER */
 #define I40E_GL_SWR_PRI_JOIN_MAP_MAX_INDEX            8
 #define I40E_GL_SWR_PRI_JOIN_MAP_GL_SWR_PRI_MAP_SHIFT 0
 #define I40E_GL_SWR_PRI_JOIN_MAP_GL_SWR_PRI_MAP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_PRI_JOIN_MAP_GL_SWR_PRI_MAP_SHIFT)
 
-#define I40E_GL_SWR_PRI_MAP(_i)                  (0x0026CDE0 + ((_i) * 4)) /* _i=0...8 */
+#define I40E_GL_SWR_PRI_MAP(_i)                  (0x0026CDE0 + ((_i) * 4)) /* _i=0...8 */ /* Reset: CORER */
 #define I40E_GL_SWR_PRI_MAP_MAX_INDEX            8
 #define I40E_GL_SWR_PRI_MAP_GL_SWR_PRI_MAP_SHIFT 0
 #define I40E_GL_SWR_PRI_MAP_GL_SWR_PRI_MAP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_PRI_MAP_GL_SWR_PRI_MAP_SHIFT)
 
-#define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D0                  0x002699BC
+#define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D0                  0x002699BC /* Reset: CORER */
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D0_F0_SRC_IDX_SHIFT 0
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D0_F0_SRC_IDX_MASK  I40E_MASK(0x3F, I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D0_F0_SRC_IDX_SHIFT)
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D0_F0_SRC_SEL_SHIFT 6
@@ -9529,7 +9921,7 @@
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D0_F3_SRC_IDX_SHIFT 31
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D0_F3_SRC_IDX_MASK  I40E_MASK(0x1, I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D0_F3_SRC_IDX_SHIFT)
 
-#define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D1                  0x002699CC
+#define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D1                  0x002699CC /* Reset: CORER */
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D1_F4_SRC_IDX_SHIFT 0
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D1_F4_SRC_IDX_MASK  I40E_MASK(0x3F, I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D1_F4_SRC_IDX_SHIFT)
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D1_F4_SRC_SEL_SHIFT 6
@@ -9553,7 +9945,7 @@
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D1_F7_SRC_IDX_SHIFT 31
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D1_F7_SRC_IDX_MASK  I40E_MASK(0x1, I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D1_F7_SRC_IDX_SHIFT)
 
-#define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D2                 0x002699FC
+#define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D2                 0x002699FC /* Reset: CORER */
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D2_USE_PHASE_SHIFT 0
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D2_USE_PHASE_MASK  I40E_MASK(0x1, I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D2_USE_PHASE_SHIFT)
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D2_USE_INGR_SHIFT  1
@@ -9573,11 +9965,11 @@
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D2_BIT_MSK0_SHIFT  24
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D2_BIT_MSK0_MASK   I40E_MASK(0xFF, I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D2_BIT_MSK0_SHIFT)
 
-#define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D3                0x00269A14
+#define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D3                0x00269A14 /* Reset: CORER */
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D3_BIT_MSK0_SHIFT 0
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D3_BIT_MSK0_MASK  I40E_MASK(0xFF, I40E_GL_SWT_FLU_BIG_ENT_PHASE0_D3_BIT_MSK0_SHIFT)
 
-#define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D0                  0x002699DC
+#define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D0                  0x002699DC /* Reset: CORER */
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D0_F0_SRC_IDX_SHIFT 0
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D0_F0_SRC_IDX_MASK  I40E_MASK(0x3F, I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D0_F0_SRC_IDX_SHIFT)
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D0_F0_SRC_SEL_SHIFT 6
@@ -9601,7 +9993,7 @@
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D0_F3_SRC_IDX_SHIFT 31
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D0_F3_SRC_IDX_MASK  I40E_MASK(0x1, I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D0_F3_SRC_IDX_SHIFT)
 
-#define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D1                  0x002699E4
+#define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D1                  0x002699E4 /* Reset: CORER */
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D1_F4_SRC_IDX_SHIFT 0
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D1_F4_SRC_IDX_MASK  I40E_MASK(0x3F, I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D1_F4_SRC_IDX_SHIFT)
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D1_F4_SRC_SEL_SHIFT 6
@@ -9625,7 +10017,7 @@
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D1_F7_SRC_IDX_SHIFT 31
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D1_F7_SRC_IDX_MASK  I40E_MASK(0x1, I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D1_F7_SRC_IDX_SHIFT)
 
-#define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D2                 0x002699F4
+#define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D2                 0x002699F4 /* Reset: CORER */
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D2_USE_PHASE_SHIFT 0
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D2_USE_PHASE_MASK  I40E_MASK(0x1, I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D2_USE_PHASE_SHIFT)
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D2_USE_INGR_SHIFT  1
@@ -9645,41 +10037,41 @@
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D2_BIT_MSK0_SHIFT  24
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D2_BIT_MSK0_MASK   I40E_MASK(0xFF, I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D2_BIT_MSK0_SHIFT)
 
-#define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D3                0x00269A04
+#define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D3                0x00269A04 /* Reset: CORER */
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D3_BIT_MSK0_SHIFT 0
 #define I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D3_BIT_MSK0_MASK  I40E_MASK(0xFF, I40E_GL_SWT_FLU_BIG_ENT_PHASE1_D3_BIT_MSK0_SHIFT)
 
-#define I40E_GL_SWT_LOCMD_PE(_i)           (0x002694A0 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GL_SWT_LOCMD_PE(_i)           (0x002694A0 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GL_SWT_LOCMD_PE_MAX_INDEX     7
 #define I40E_GL_SWT_LOCMD_PE_COMMAND_SHIFT 0
 #define I40E_GL_SWT_LOCMD_PE_COMMAND_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWT_LOCMD_PE_COMMAND_SHIFT)
 
-#define I40E_GL_SWT_LOCMD_SW(_i)           (0x002694E0 + ((_i) * 4)) /* _i=0...7 */
+#define I40E_GL_SWT_LOCMD_SW(_i)           (0x002694E0 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_GL_SWT_LOCMD_SW_MAX_INDEX     7
 #define I40E_GL_SWT_LOCMD_SW_COMMAND_SHIFT 0
 #define I40E_GL_SWT_LOCMD_SW_COMMAND_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWT_LOCMD_SW_COMMAND_SHIFT)
 
-#define I40E_GL_SWT_LOFV_PE(_i)               (0x00268E80 + ((_i) * 4)) /* _i=0...31 */
+#define I40E_GL_SWT_LOFV_PE(_i)               (0x00268E80 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
 #define I40E_GL_SWT_LOFV_PE_MAX_INDEX         31
 #define I40E_GL_SWT_LOFV_PE_FIELDVECTOR_SHIFT 0
 #define I40E_GL_SWT_LOFV_PE_FIELDVECTOR_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWT_LOFV_PE_FIELDVECTOR_SHIFT)
 
-#define I40E_GL_SWT_LOFV_SW(_i)               (0x00268F80 + ((_i) * 4)) /* _i=0...31 */
+#define I40E_GL_SWT_LOFV_SW(_i)               (0x00268F80 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
 #define I40E_GL_SWT_LOFV_SW_MAX_INDEX         31
 #define I40E_GL_SWT_LOFV_SW_FIELDVECTOR_SHIFT 0
 #define I40E_GL_SWT_LOFV_SW_FIELDVECTOR_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_SWT_LOFV_SW_FIELDVECTOR_SHIFT)
 
-#define I40E_PRT_MSCCNT              0x00256BA0
+#define I40E_PRT_MSCCNT              0x00256BA0 /* Reset: CORER */
 #define I40E_PRT_MSCCNT_CCOUNT_SHIFT 0
 #define I40E_PRT_MSCCNT_CCOUNT_MASK  I40E_MASK(0x1FFFFFF, I40E_PRT_MSCCNT_CCOUNT_SHIFT)
 
-#define I40E_PRT_SBPVSI                      0x00256BE0
+#define I40E_PRT_SBPVSI                      0x00256BE0 /* Reset: CORER */
 #define I40E_PRT_SBPVSI_BAD_FRAMES_VSI_SHIFT 0
 #define I40E_PRT_SBPVSI_BAD_FRAMES_VSI_MASK  I40E_MASK(0x1FF, I40E_PRT_SBPVSI_BAD_FRAMES_VSI_SHIFT)
 #define I40E_PRT_SBPVSI_SBP_SHIFT            31
 #define I40E_PRT_SBPVSI_SBP_MASK             I40E_MASK(0x1, I40E_PRT_SBPVSI_SBP_SHIFT)
 
-#define I40E_PRT_SCSTS             0x00256C20
+#define I40E_PRT_SCSTS             0x00256C20 /* Reset: CORER */
 #define I40E_PRT_SCSTS_BSCA_SHIFT  0
 #define I40E_PRT_SCSTS_BSCA_MASK   I40E_MASK(0x1, I40E_PRT_SCSTS_BSCA_SHIFT)
 #define I40E_PRT_SCSTS_BSCAP_SHIFT 1
@@ -9689,29 +10081,29 @@
 #define I40E_PRT_SCSTS_MSCAP_SHIFT 3
 #define I40E_PRT_SCSTS_MSCAP_MASK  I40E_MASK(0x1, I40E_PRT_SCSTS_MSCAP_SHIFT)
 
-#define I40E_PRT_SWT_BSCCNT              0x00256C60
+#define I40E_PRT_SWT_BSCCNT              0x00256C60 /* Reset: CORER */
 #define I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT 0
 #define I40E_PRT_SWT_BSCCNT_CCOUNT_MASK  I40E_MASK(0x1FFFFFF, I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT)
 
-#define I40E_PRT_SWT_BSCTRH              0x00256CA0
+#define I40E_PRT_SWT_BSCTRH              0x00256CA0 /* Reset: CORER */
 #define I40E_PRT_SWT_BSCTRH_UTRESH_SHIFT 0
 #define I40E_PRT_SWT_BSCTRH_UTRESH_MASK  I40E_MASK(0x7FFFF, I40E_PRT_SWT_BSCTRH_UTRESH_SHIFT)
 
-#define I40E_PRT_SWT_DEFPORTS                         0x00256CE0
+#define I40E_PRT_SWT_DEFPORTS                         0x00256CE0 /* Reset: CORER */
 #define I40E_PRT_SWT_DEFPORTS_DEFAULT_VSI_SHIFT       0
 #define I40E_PRT_SWT_DEFPORTS_DEFAULT_VSI_MASK        I40E_MASK(0x1FF, I40E_PRT_SWT_DEFPORTS_DEFAULT_VSI_SHIFT)
 #define I40E_PRT_SWT_DEFPORTS_DEFAULT_VSI_VALID_SHIFT 31
 #define I40E_PRT_SWT_DEFPORTS_DEFAULT_VSI_VALID_MASK  I40E_MASK(0x1, I40E_PRT_SWT_DEFPORTS_DEFAULT_VSI_VALID_SHIFT)
 
-#define I40E_PRT_SWT_MSCTRH              0x00256D20
+#define I40E_PRT_SWT_MSCTRH              0x00256D20 /* Reset: CORER */
 #define I40E_PRT_SWT_MSCTRH_UTRESH_SHIFT 0
 #define I40E_PRT_SWT_MSCTRH_UTRESH_MASK  I40E_MASK(0x7FFFF, I40E_PRT_SWT_MSCTRH_UTRESH_SHIFT)
 
-#define I40E_PRT_SWT_SCBI          0x00256D60
+#define I40E_PRT_SWT_SCBI          0x00256D60 /* Reset: CORER */
 #define I40E_PRT_SWT_SCBI_BI_SHIFT 0
 #define I40E_PRT_SWT_SCBI_BI_MASK  I40E_MASK(0x1FFFFFF, I40E_PRT_SWT_SCBI_BI_SHIFT)
 
-#define I40E_PRT_SWT_SCCRL                0x00256DA0
+#define I40E_PRT_SWT_SCCRL                0x00256DA0 /* Reset: CORER */
 #define I40E_PRT_SWT_SCCRL_MDIPW_SHIFT    0
 #define I40E_PRT_SWT_SCCRL_MDIPW_MASK     I40E_MASK(0x1, I40E_PRT_SWT_SCCRL_MDIPW_SHIFT)
 #define I40E_PRT_SWT_SCCRL_MDICW_SHIFT    1
@@ -9725,11 +10117,11 @@
 #define I40E_PRT_SWT_SCCRL_INTERVAL_SHIFT 8
 #define I40E_PRT_SWT_SCCRL_INTERVAL_MASK  I40E_MASK(0x3FF, I40E_PRT_SWT_SCCRL_INTERVAL_SHIFT)
 
-#define I40E_PRT_SWT_SCTC             0x00256DE0
+#define I40E_PRT_SWT_SCTC             0x00256DE0 /* Reset: CORER */
 #define I40E_PRT_SWT_SCTC_COUNT_SHIFT 0
 #define I40E_PRT_SWT_SCTC_COUNT_MASK  I40E_MASK(0x3FF, I40E_PRT_SWT_SCTC_COUNT_SHIFT)
 
-#define I40E_PRT_SWT_SWITCHID                             0x00256E20
+#define I40E_PRT_SWT_SWITCHID                             0x00256E20 /* Reset: CORER */
 #define I40E_PRT_SWT_SWITCHID_SWID_SHIFT                  0
 #define I40E_PRT_SWT_SWITCHID_SWID_MASK                   I40E_MASK(0xFFF, I40E_PRT_SWT_SWITCHID_SWID_SHIFT)
 #define I40E_PRT_SWT_SWITCHID_ISNSTAG_SHIFT               12
@@ -9739,7 +10131,7 @@
 #define I40E_PRT_SWT_SWITCHID_FORWARD_MUTICAST_ETAG_SHIFT 31
 #define I40E_PRT_SWT_SWITCHID_FORWARD_MUTICAST_ETAG_MASK  I40E_MASK(0x1, I40E_PRT_SWT_SWITCHID_FORWARD_MUTICAST_ETAG_SHIFT)
 
-#define I40E_PRT_TCTUPR(_i)       (0x00044000 + ((_i) * 32)) /* _i=0...7 */
+#define I40E_PRT_TCTUPR(_i)       (0x00044000 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
 #define I40E_PRT_TCTUPR_MAX_INDEX 7
 #define I40E_PRT_TCTUPR_UP0_SHIFT 0
 #define I40E_PRT_TCTUPR_UP0_MASK  I40E_MASK(0x7, I40E_PRT_TCTUPR_UP0_SHIFT)
@@ -9760,35 +10152,35 @@
 
 /* PF - TimeSync (IEEE 1588) Registers  */
 
-#define I40E_PRTTSYN_VFTIME_H                  0x001E4020
+#define I40E_PRTTSYN_VFTIME_H                  0x001E4020 /* Reset: GLOBR */
 #define I40E_PRTTSYN_VFTIME_H_TSYNTIME_H_SHIFT 0
 #define I40E_PRTTSYN_VFTIME_H_TSYNTIME_H_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_VFTIME_H_TSYNTIME_H_SHIFT)
 
-#define I40E_PRTTSYN_VFTIME_L                  0x001E4000
+#define I40E_PRTTSYN_VFTIME_L                  0x001E4000 /* Reset: GLOBR */
 #define I40E_PRTTSYN_VFTIME_L_TSYNTIME_L_SHIFT 0
 #define I40E_PRTTSYN_VFTIME_L_TSYNTIME_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_VFTIME_L_TSYNTIME_L_SHIFT)
 
 /* PF - Transmit Scheduler Registers */
 
-#define I40E_GLSCD_BWLCREDUPDATE                     0x000B2148
+#define I40E_GLSCD_BWLCREDUPDATE                     0x000B2148 /* Reset: CORER */
 #define I40E_GLSCD_BWLCREDUPDATE_BWLCREDUPDATE_SHIFT 0
 #define I40E_GLSCD_BWLCREDUPDATE_BWLCREDUPDATE_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSCD_BWLCREDUPDATE_BWLCREDUPDATE_SHIFT)
 
-#define I40E_GLSCD_BWLLINESPERARB                      0x000B214C
+#define I40E_GLSCD_BWLLINESPERARB                      0x000B214C /* Reset: CORER */
 #define I40E_GLSCD_BWLLINESPERARB_BWLLINESPERARB_SHIFT 0
 #define I40E_GLSCD_BWLLINESPERARB_BWLLINESPERARB_MASK  I40E_MASK(0x7FF, I40E_GLSCD_BWLLINESPERARB_BWLLINESPERARB_SHIFT)
 
-#define I40E_GLSCD_CREDITSPERQUANTA                            0x000B2144
+#define I40E_GLSCD_CREDITSPERQUANTA                            0x000B2144 /* Reset: CORER */
 #define I40E_GLSCD_CREDITSPERQUANTA_TSCDCREDITSPERQUANTA_SHIFT 0
 #define I40E_GLSCD_CREDITSPERQUANTA_TSCDCREDITSPERQUANTA_MASK  I40E_MASK(0xFFFF, I40E_GLSCD_CREDITSPERQUANTA_TSCDCREDITSPERQUANTA_SHIFT)
 
-#define I40E_GLSCD_ERRSTATREG                          0x000B2150
+#define I40E_GLSCD_ERRSTATREG                          0x000B2150 /* Reset: CORER */
 #define I40E_GLSCD_ERRSTATREG_LOOP_DETECTED_SHIFT      0
 #define I40E_GLSCD_ERRSTATREG_LOOP_DETECTED_MASK       I40E_MASK(0x1, I40E_GLSCD_ERRSTATREG_LOOP_DETECTED_SHIFT)
 #define I40E_GLSCD_ERRSTATREG_SHRTBWLIMUPDATEPER_SHIFT 1
 #define I40E_GLSCD_ERRSTATREG_SHRTBWLIMUPDATEPER_MASK  I40E_MASK(0x1, I40E_GLSCD_ERRSTATREG_SHRTBWLIMUPDATEPER_SHIFT)
 
-#define I40E_GLSCD_IFBCMDH                       0x000B20A0
+#define I40E_GLSCD_IFBCMDH                       0x000B20A0 /* Reset: CORER */
 #define I40E_GLSCD_IFBCMDH_FLDOFFS_NUMENTS_SHIFT 0
 #define I40E_GLSCD_IFBCMDH_FLDOFFS_NUMENTS_MASK  I40E_MASK(0x7F, I40E_GLSCD_IFBCMDH_FLDOFFS_NUMENTS_SHIFT)
 #define I40E_GLSCD_IFBCMDH_FLDSZ_SHIFT           7
@@ -9798,7 +10190,7 @@
 #define I40E_GLSCD_IFBCMDH_RSVD_SHIFT            31
 #define I40E_GLSCD_IFBCMDH_RSVD_MASK             I40E_MASK(0x1, I40E_GLSCD_IFBCMDH_RSVD_SHIFT)
 
-#define I40E_GLSCD_IFBCMDL                   0x000B209c
+#define I40E_GLSCD_IFBCMDL                   0x000B209c /* Reset: CORER */
 #define I40E_GLSCD_IFBCMDL_OPCODE_SHIFT      0
 #define I40E_GLSCD_IFBCMDL_OPCODE_MASK       I40E_MASK(0xF, I40E_GLSCD_IFBCMDL_OPCODE_SHIFT)
 #define I40E_GLSCD_IFBCMDL_TBLTYPE_SHIFT     4
@@ -9810,7 +10202,7 @@
 #define I40E_GLSCD_IFBCMDL_RSVD_SHIFT        22
 #define I40E_GLSCD_IFBCMDL_RSVD_MASK         I40E_MASK(0x3FF, I40E_GLSCD_IFBCMDL_RSVD_SHIFT)
 
-#define I40E_GLSCD_IFCTRL                          0x000B20A8
+#define I40E_GLSCD_IFCTRL                          0x000B20A8 /* Reset: CORER */
 #define I40E_GLSCD_IFCTRL_BCMDDB_SHIFT             0
 #define I40E_GLSCD_IFCTRL_BCMDDB_MASK              I40E_MASK(0x1, I40E_GLSCD_IFCTRL_BCMDDB_SHIFT)
 #define I40E_GLSCD_IFCTRL_ICMDCLRERR_SHIFT         1
@@ -9822,12 +10214,12 @@
 #define I40E_GLSCD_IFCTRL_SMALL_CRED_DISABLE_SHIFT 4
 #define I40E_GLSCD_IFCTRL_SMALL_CRED_DISABLE_MASK  I40E_MASK(0x1, I40E_GLSCD_IFCTRL_SMALL_CRED_DISABLE_SHIFT)
 
-#define I40E_GLSCD_IFDATA(_i)              (0x000B2084 + ((_i) * 4)) /* _i=0...3 */
+#define I40E_GLSCD_IFDATA(_i)              (0x000B2084 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GLSCD_IFDATA_MAX_INDEX        3
 #define I40E_GLSCD_IFDATA_TSCDIFDATA_SHIFT 0
 #define I40E_GLSCD_IFDATA_TSCDIFDATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSCD_IFDATA_TSCDIFDATA_SHIFT)
 
-#define I40E_GLSCD_IFICMDH                       0x000B2098
+#define I40E_GLSCD_IFICMDH                       0x000B2098 /* Reset: CORER */
 #define I40E_GLSCD_IFICMDH_FLDOFFS_NUMENTS_SHIFT 0
 #define I40E_GLSCD_IFICMDH_FLDOFFS_NUMENTS_MASK  I40E_MASK(0x7F, I40E_GLSCD_IFICMDH_FLDOFFS_NUMENTS_SHIFT)
 #define I40E_GLSCD_IFICMDH_FLDSZ_SHIFT           7
@@ -9837,7 +10229,7 @@
 #define I40E_GLSCD_IFICMDH_RSVD_SHIFT            31
 #define I40E_GLSCD_IFICMDH_RSVD_MASK             I40E_MASK(0x1, I40E_GLSCD_IFICMDH_RSVD_SHIFT)
 
-#define I40E_GLSCD_IFICMDL                   0x000B2094
+#define I40E_GLSCD_IFICMDL                   0x000B2094 /* Reset: CORER */
 #define I40E_GLSCD_IFICMDL_OPCODE_SHIFT      0
 #define I40E_GLSCD_IFICMDL_OPCODE_MASK       I40E_MASK(0xF, I40E_GLSCD_IFICMDL_OPCODE_SHIFT)
 #define I40E_GLSCD_IFICMDL_TBLTYPE_SHIFT     4
@@ -9849,7 +10241,7 @@
 #define I40E_GLSCD_IFICMDL_RSVD_SHIFT        22
 #define I40E_GLSCD_IFICMDL_RSVD_MASK         I40E_MASK(0x3FF, I40E_GLSCD_IFICMDL_RSVD_SHIFT)
 
-#define I40E_GLSCD_IFSTATUS                 0x000B20A4
+#define I40E_GLSCD_IFSTATUS                 0x000B20A4 /* Reset: CORER */
 #define I40E_GLSCD_IFSTATUS_ENTRAVAIL_SHIFT 0
 #define I40E_GLSCD_IFSTATUS_ENTRAVAIL_MASK  I40E_MASK(0x3F, I40E_GLSCD_IFSTATUS_ENTRAVAIL_SHIFT)
 #define I40E_GLSCD_IFSTATUS_ICMDBZ_SHIFT    6
@@ -9863,19 +10255,19 @@
 #define I40E_GLSCD_IFSTATUS_RSVD_SHIFT      10
 #define I40E_GLSCD_IFSTATUS_RSVD_MASK       I40E_MASK(0x3FFFFF, I40E_GLSCD_IFSTATUS_RSVD_SHIFT)
 
-#define I40E_GLSCD_INCSCHEDCFGCOUNT                        0x000B2140
+#define I40E_GLSCD_INCSCHEDCFGCOUNT                        0x000B2140 /* Reset: CORER */
 #define I40E_GLSCD_INCSCHEDCFGCOUNT_INCSCHEDCFGCOUNT_SHIFT 0
 #define I40E_GLSCD_INCSCHEDCFGCOUNT_INCSCHEDCFGCOUNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSCD_INCSCHEDCFGCOUNT_INCSCHEDCFGCOUNT_SHIFT)
 
-#define I40E_GLSCD_LANTCBCMDS                     0x000B2154
+#define I40E_GLSCD_LANTCBCMDS                     0x000B2154 /* Reset: CORER */
 #define I40E_GLSCD_LANTCBCMDS_NUMLANTCBCMDS_SHIFT 0
 #define I40E_GLSCD_LANTCBCMDS_NUMLANTCBCMDS_MASK  I40E_MASK(0x7F, I40E_GLSCD_LANTCBCMDS_NUMLANTCBCMDS_SHIFT)
 
-#define I40E_GLSCD_LLPREALTHRESH                     0x000B213C
+#define I40E_GLSCD_LLPREALTHRESH                     0x000B213C /* Reset: CORER */
 #define I40E_GLSCD_LLPREALTHRESH_LLPREALTHRESH_SHIFT 0
 #define I40E_GLSCD_LLPREALTHRESH_LLPREALTHRESH_MASK  I40E_MASK(0xF, I40E_GLSCD_LLPREALTHRESH_LLPREALTHRESH_SHIFT)
 
-#define I40E_GLSCD_PRGPERFCONTROL(_i)                  (0x000B20FC + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLSCD_PRGPERFCONTROL(_i)                  (0x000B20FC + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSCD_PRGPERFCONTROL_MAX_INDEX            15
 #define I40E_GLSCD_PRGPERFCONTROL_COUNTERTYPE_SHIFT    0
 #define I40E_GLSCD_PRGPERFCONTROL_COUNTERTYPE_MASK     I40E_MASK(0x7, I40E_GLSCD_PRGPERFCONTROL_COUNTERTYPE_SHIFT)
@@ -9888,12 +10280,12 @@
 #define I40E_GLSCD_PRGPERFCONTROL_QSINDEX_SHIFT        16
 #define I40E_GLSCD_PRGPERFCONTROL_QSINDEX_MASK         I40E_MASK(0x3FF, I40E_GLSCD_PRGPERFCONTROL_QSINDEX_SHIFT)
 
-#define I40E_GLSCD_PRGPERFCOUNT(_i)                (0x000B20BC + ((_i) * 4)) /* _i=0...15 */
+#define I40E_GLSCD_PRGPERFCOUNT(_i)                (0x000B20BC + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
 #define I40E_GLSCD_PRGPERFCOUNT_MAX_INDEX          15
 #define I40E_GLSCD_PRGPERFCOUNT_PRGPERFCOUNT_SHIFT 0
 #define I40E_GLSCD_PRGPERFCOUNT_PRGPERFCOUNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSCD_PRGPERFCOUNT_PRGPERFCOUNT_SHIFT)
 
-#define I40E_GLSCD_RAM_DBG_CTL(_i)          (0x000B28c0 + ((_i) * 4)) /* _i=0...9 */
+#define I40E_GLSCD_RAM_DBG_CTL(_i)          (0x000B28c0 + ((_i) * 4)) /* _i=0...9 */ /* Reset: POR */
 #define I40E_GLSCD_RAM_DBG_CTL_MAX_INDEX    9
 #define I40E_GLSCD_RAM_DBG_CTL_ADR_SHIFT    0
 #define I40E_GLSCD_RAM_DBG_CTL_ADR_MASK     I40E_MASK(0x3FFFF, I40E_GLSCD_RAM_DBG_CTL_ADR_SHIFT)
@@ -9904,58 +10296,58 @@
 #define I40E_GLSCD_RAM_DBG_CTL_DONE_SHIFT   31
 #define I40E_GLSCD_RAM_DBG_CTL_DONE_MASK    I40E_MASK(0x1, I40E_GLSCD_RAM_DBG_CTL_DONE_SHIFT)
 
-#define I40E_GLSCD_RAM_DBG_DATA(_i)                      (0x000b28e8 + ((_i) * 4)) /* _i=0...9 */
+#define I40E_GLSCD_RAM_DBG_DATA(_i)                      (0x000b28e8 + ((_i) * 4)) /* _i=0...9 */ /* Reset: POR */
 #define I40E_GLSCD_RAM_DBG_DATA_MAX_INDEX                9
 #define I40E_GLSCD_RAM_DBG_DATA_GLSCD_RAM_DBG_DATA_SHIFT 0
 #define I40E_GLSCD_RAM_DBG_DATA_GLSCD_RAM_DBG_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSCD_RAM_DBG_DATA_GLSCD_RAM_DBG_DATA_SHIFT)
 
-#define I40E_GLSCD_RLMTBLRD2CMD                 0x000B2158
+#define I40E_GLSCD_RLMTBLRD2CMD                 0x000B2158 /* Reset: CORER */
 #define I40E_GLSCD_RLMTBLRD2CMD_RLMTBLIDX_SHIFT 0
 #define I40E_GLSCD_RLMTBLRD2CMD_RLMTBLIDX_MASK  I40E_MASK(0x3FF, I40E_GLSCD_RLMTBLRD2CMD_RLMTBLIDX_SHIFT)
 
-#define I40E_GLSCD_RLMTBLRD2DATAHI            0x000B2164
+#define I40E_GLSCD_RLMTBLRD2DATAHI            0x000B2164 /* Reset: CORER */
 #define I40E_GLSCD_RLMTBLRD2DATAHI_DATA_SHIFT 0
 #define I40E_GLSCD_RLMTBLRD2DATAHI_DATA_MASK  I40E_MASK(0x7FFFFFF, I40E_GLSCD_RLMTBLRD2DATAHI_DATA_SHIFT)
 
-#define I40E_GLSCD_RLMTBLRD2DATALO            0x000B2160
+#define I40E_GLSCD_RLMTBLRD2DATALO            0x000B2160 /* Reset: CORER */
 #define I40E_GLSCD_RLMTBLRD2DATALO_DATA_SHIFT 0
 #define I40E_GLSCD_RLMTBLRD2DATALO_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSCD_RLMTBLRD2DATALO_DATA_SHIFT)
 
-#define I40E_GLSCD_RLMTBLRD2STATUS             0x000B215C
+#define I40E_GLSCD_RLMTBLRD2STATUS             0x000B215C /* Reset: CORER */
 #define I40E_GLSCD_RLMTBLRD2STATUS_VALID_SHIFT 0
 #define I40E_GLSCD_RLMTBLRD2STATUS_VALID_MASK  I40E_MASK(0x1, I40E_GLSCD_RLMTBLRD2STATUS_VALID_SHIFT)
 #define I40E_GLSCD_RLMTBLRD2STATUS_RSVD_SHIFT  1
 #define I40E_GLSCD_RLMTBLRD2STATUS_RSVD_MASK   I40E_MASK(0x7FFFFFFF, I40E_GLSCD_RLMTBLRD2STATUS_RSVD_SHIFT)
 
-#define I40E_GLSCD_RLMTBLRDCMD                 0x000B20AC
+#define I40E_GLSCD_RLMTBLRDCMD                 0x000B20AC /* Reset: CORER */
 #define I40E_GLSCD_RLMTBLRDCMD_RLMTBLIDX_SHIFT 0
 #define I40E_GLSCD_RLMTBLRDCMD_RLMTBLIDX_MASK  I40E_MASK(0x3FF, I40E_GLSCD_RLMTBLRDCMD_RLMTBLIDX_SHIFT)
 
-#define I40E_GLSCD_RLMTBLRDDATAHI            0x000B20B8
+#define I40E_GLSCD_RLMTBLRDDATAHI            0x000B20B8 /* Reset: CORER */
 #define I40E_GLSCD_RLMTBLRDDATAHI_DATA_SHIFT 0
 #define I40E_GLSCD_RLMTBLRDDATAHI_DATA_MASK  I40E_MASK(0x7FFFFFF, I40E_GLSCD_RLMTBLRDDATAHI_DATA_SHIFT)
 
-#define I40E_GLSCD_RLMTBLRDDATALO            0x000B20B4
+#define I40E_GLSCD_RLMTBLRDDATALO            0x000B20B4 /* Reset: CORER */
 #define I40E_GLSCD_RLMTBLRDDATALO_DATA_SHIFT 0
 #define I40E_GLSCD_RLMTBLRDDATALO_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLSCD_RLMTBLRDDATALO_DATA_SHIFT)
 
-#define I40E_GLSCD_RLMTBLRDSTATUS             0x000B20B0
+#define I40E_GLSCD_RLMTBLRDSTATUS             0x000B20B0 /* Reset: CORER */
 #define I40E_GLSCD_RLMTBLRDSTATUS_VALID_SHIFT 0
 #define I40E_GLSCD_RLMTBLRDSTATUS_VALID_MASK  I40E_MASK(0x1, I40E_GLSCD_RLMTBLRDSTATUS_VALID_SHIFT)
 #define I40E_GLSCD_RLMTBLRDSTATUS_RSVD_SHIFT  1
 #define I40E_GLSCD_RLMTBLRDSTATUS_RSVD_MASK   I40E_MASK(0x7FFFFFFF, I40E_GLSCD_RLMTBLRDSTATUS_RSVD_SHIFT)
 
-#define I40E_PFSCD_DEFQSETHNDL                   0x000B2000
+#define I40E_PFSCD_DEFQSETHNDL                   0x000B2000 /* Reset: PFR */
 #define I40E_PFSCD_DEFQSETHNDL_DEFQSETHNDL_SHIFT 0
 #define I40E_PFSCD_DEFQSETHNDL_DEFQSETHNDL_MASK  I40E_MASK(0xFFFF, I40E_PFSCD_DEFQSETHNDL_DEFQSETHNDL_SHIFT)
 
 /* PF - Virtualization PF Registers  */
 
-#define I40E_GL_MDCK_RX                 0x0012A50C
+#define I40E_GL_MDCK_RX                 0x0012A50C /* Reset: CORER */
 #define I40E_GL_MDCK_RX_DESC_ADDR_SHIFT 0
 #define I40E_GL_MDCK_RX_DESC_ADDR_MASK  I40E_MASK(0x1, I40E_GL_MDCK_RX_DESC_ADDR_SHIFT)
 
-#define I40E_GL_MDCK_TCMD                         0x000E648C
+#define I40E_GL_MDCK_TCMD                         0x000E648C /* Reset: CORER */
 #define I40E_GL_MDCK_TCMD_DESC_ADDR_SHIFT         0
 #define I40E_GL_MDCK_TCMD_DESC_ADDR_MASK          I40E_MASK(0x1, I40E_GL_MDCK_TCMD_DESC_ADDR_SHIFT)
 #define I40E_GL_MDCK_TCMD_MAX_BUFF_SHIFT          2
@@ -9989,7 +10381,7 @@
 #define I40E_GL_MDCK_TCMD_ZERO_BSIZE_SHIFT        18
 #define I40E_GL_MDCK_TCMD_ZERO_BSIZE_MASK         I40E_MASK(0x1, I40E_GL_MDCK_TCMD_ZERO_BSIZE_SHIFT)
 
-#define I40E_GL_MDCK_TDAT                      0x000442F4
+#define I40E_GL_MDCK_TDAT                      0x000442F4 /* Reset: CORER */
 #define I40E_GL_MDCK_TDAT_BIG_OFFSET_SHIFT     0
 #define I40E_GL_MDCK_TDAT_BIG_OFFSET_MASK      I40E_MASK(0x1, I40E_GL_MDCK_TDAT_BIG_OFFSET_SHIFT)
 #define I40E_GL_MDCK_TDAT_BUFF_ADDR_SHIFT      1
@@ -9999,7 +10391,7 @@
 #define I40E_GL_MDCK_TDAT_MAL_CMD_DIS_SHIFT    3
 #define I40E_GL_MDCK_TDAT_MAL_CMD_DIS_MASK     I40E_MASK(0x1, I40E_GL_MDCK_TDAT_MAL_CMD_DIS_SHIFT)
 
-#define I40E_PF_VIRT_VSTATUS                  0x0009C400
+#define I40E_PF_VIRT_VSTATUS                  0x0009C400 /* Reset: PFR */
 #define I40E_PF_VIRT_VSTATUS_NUM_VFS_SHIFT    0
 #define I40E_PF_VIRT_VSTATUS_NUM_VFS_MASK     I40E_MASK(0xFF, I40E_PF_VIRT_VSTATUS_NUM_VFS_SHIFT)
 #define I40E_PF_VIRT_VSTATUS_TOTAL_VFS_SHIFT  8
@@ -10007,7 +10399,7 @@
 #define I40E_PF_VIRT_VSTATUS_IOV_ACTIVE_SHIFT 16
 #define I40E_PF_VIRT_VSTATUS_IOV_ACTIVE_MASK  I40E_MASK(0x1, I40E_PF_VIRT_VSTATUS_IOV_ACTIVE_SHIFT)
 
-#define I40E_PF_VT_PFALLOC_CSR               0x00078D80
+#define I40E_PF_VT_PFALLOC_CSR               0x00078D80 /* Reset: CORER */
 #define I40E_PF_VT_PFALLOC_CSR_FIRSTVF_SHIFT 0
 #define I40E_PF_VT_PFALLOC_CSR_FIRSTVF_MASK  I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_CSR_FIRSTVF_SHIFT)
 #define I40E_PF_VT_PFALLOC_CSR_LASTVF_SHIFT  8
@@ -10015,7 +10407,7 @@
 #define I40E_PF_VT_PFALLOC_CSR_VALID_SHIFT   31
 #define I40E_PF_VT_PFALLOC_CSR_VALID_MASK    I40E_MASK(0x1, I40E_PF_VT_PFALLOC_CSR_VALID_SHIFT)
 
-#define I40E_PF_VT_PFALLOC_INT               0x0003F080
+#define I40E_PF_VT_PFALLOC_INT               0x0003F080 /* Reset: CORER */
 #define I40E_PF_VT_PFALLOC_INT_FIRSTVF_SHIFT 0
 #define I40E_PF_VT_PFALLOC_INT_FIRSTVF_MASK  I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_INT_FIRSTVF_SHIFT)
 #define I40E_PF_VT_PFALLOC_INT_LASTVF_SHIFT  8
@@ -10023,7 +10415,7 @@
 #define I40E_PF_VT_PFALLOC_INT_VALID_SHIFT   31
 #define I40E_PF_VT_PFALLOC_INT_VALID_MASK    I40E_MASK(0x1, I40E_PF_VT_PFALLOC_INT_VALID_SHIFT)
 
-#define I40E_PF_VT_PFALLOC_PMAT               0x000C0680
+#define I40E_PF_VT_PFALLOC_PMAT               0x000C0680 /* Reset: CORER */
 #define I40E_PF_VT_PFALLOC_PMAT_FIRSTVF_SHIFT 0
 #define I40E_PF_VT_PFALLOC_PMAT_FIRSTVF_MASK  I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_PMAT_FIRSTVF_SHIFT)
 #define I40E_PF_VT_PFALLOC_PMAT_LASTVF_SHIFT  8
@@ -10031,7 +10423,7 @@
 #define I40E_PF_VT_PFALLOC_PMAT_VALID_SHIFT   31
 #define I40E_PF_VT_PFALLOC_PMAT_VALID_MASK    I40E_MASK(0x1, I40E_PF_VT_PFALLOC_PMAT_VALID_SHIFT)
 
-#define I40E_PF_VT_PFALLOC_TSCD               0x000B2280
+#define I40E_PF_VT_PFALLOC_TSCD               0x000B2280 /* Reset: CORER */
 #define I40E_PF_VT_PFALLOC_TSCD_FIRSTVF_SHIFT 0
 #define I40E_PF_VT_PFALLOC_TSCD_FIRSTVF_MASK  I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_TSCD_FIRSTVF_SHIFT)
 #define I40E_PF_VT_PFALLOC_TSCD_LASTVF_SHIFT  8
@@ -10039,7 +10431,7 @@
 #define I40E_PF_VT_PFALLOC_TSCD_VALID_SHIFT   31
 #define I40E_PF_VT_PFALLOC_TSCD_VALID_MASK    I40E_MASK(0x1, I40E_PF_VT_PFALLOC_TSCD_VALID_SHIFT)
 
-#define I40E_PF_VT_PFALLOC_VMLR               0x00092580
+#define I40E_PF_VT_PFALLOC_VMLR               0x00092580 /* Reset: CORER */
 #define I40E_PF_VT_PFALLOC_VMLR_FIRSTVF_SHIFT 0
 #define I40E_PF_VT_PFALLOC_VMLR_FIRSTVF_MASK  I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_VMLR_FIRSTVF_SHIFT)
 #define I40E_PF_VT_PFALLOC_VMLR_LASTVF_SHIFT  8
@@ -10049,7 +10441,7 @@
 
 /* PF - VSI Context */
 
-#define I40E_VSI_L2TAGSTXVALID(_VSI)                      (0x00042800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_L2TAGSTXVALID(_VSI)                      (0x00042800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_L2TAGSTXVALID_MAX_INDEX                  383
 #define I40E_VSI_L2TAGSTXVALID_L2TAG1INSERTID_SHIFT       0
 #define I40E_VSI_L2TAGSTXVALID_L2TAG1INSERTID_MASK        I40E_MASK(0x7, I40E_VSI_L2TAGSTXVALID_L2TAG1INSERTID_SHIFT)
@@ -10072,12 +10464,12 @@
 #define I40E_VSI_L2TAGSTXVALID_TIR2_INSERT_SHIFT          27
 #define I40E_VSI_L2TAGSTXVALID_TIR2_INSERT_MASK           I40E_MASK(0x1, I40E_VSI_L2TAGSTXVALID_TIR2_INSERT_SHIFT)
 
-#define I40E_VSI_PORT(_VSI)          (0x000B22C0 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_PORT(_VSI)          (0x000B22C0 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_PORT_MAX_INDEX      383
 #define I40E_VSI_PORT_PORT_NUM_SHIFT 0
 #define I40E_VSI_PORT_PORT_NUM_MASK  I40E_MASK(0x3, I40E_VSI_PORT_PORT_NUM_SHIFT)
 
-#define I40E_VSI_RUPR(_VSI)     (0x00050000 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_RUPR(_VSI)     (0x00050000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_RUPR_MAX_INDEX 383
 #define I40E_VSI_RUPR_UP0_SHIFT 0
 #define I40E_VSI_RUPR_UP0_MASK  I40E_MASK(0x7, I40E_VSI_RUPR_UP0_SHIFT)
@@ -10096,14 +10488,14 @@
 #define I40E_VSI_RUPR_UP7_SHIFT 21
 #define I40E_VSI_RUPR_UP7_MASK  I40E_MASK(0x7, I40E_VSI_RUPR_UP7_SHIFT)
 
-#define I40E_VSI_RXSWCTRL(_VSI)                   (0x00208800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_RXSWCTRL(_VSI)                   (0x00208800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_RXSWCTRL_MAX_INDEX               383
 #define I40E_VSI_RXSWCTRL_MACVSIPRUNEENABLE_SHIFT 0
 #define I40E_VSI_RXSWCTRL_MACVSIPRUNEENABLE_MASK  I40E_MASK(0x1, I40E_VSI_RXSWCTRL_MACVSIPRUNEENABLE_SHIFT)
 #define I40E_VSI_RXSWCTRL_VLANPRUNEENABLE_SHIFT   1
 #define I40E_VSI_RXSWCTRL_VLANPRUNEENABLE_MASK    I40E_MASK(0x1, I40E_VSI_RXSWCTRL_VLANPRUNEENABLE_SHIFT)
 
-#define I40E_VSI_SRCSWCTRL(_VSI)                   (0x00209800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_SRCSWCTRL(_VSI)                   (0x00209800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_SRCSWCTRL_MAX_INDEX               383
 #define I40E_VSI_SRCSWCTRL_SWID_SHIFT              0
 #define I40E_VSI_SRCSWCTRL_SWID_MASK               I40E_MASK(0xFFF, I40E_VSI_SRCSWCTRL_SWID_SHIFT)
@@ -10122,34 +10514,34 @@
 #define I40E_VSI_SRCSWCTRL_MACAS_SHIFT             23
 #define I40E_VSI_SRCSWCTRL_MACAS_MASK              I40E_MASK(0x1, I40E_VSI_SRCSWCTRL_MACAS_SHIFT)
 
-#define I40E_VSI_TAIR(_VSI)             (0x00041800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_TAIR(_VSI)             (0x00041800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_TAIR_MAX_INDEX         383
 #define I40E_VSI_TAIR_PORT_TAG_ID_SHIFT 0
 #define I40E_VSI_TAIR_PORT_TAG_ID_MASK  I40E_MASK(0xFFFF, I40E_VSI_TAIR_PORT_TAG_ID_SHIFT)
 
-#define I40E_VSI_TAR(_VSI)                (0x00042000 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_TAR(_VSI)                (0x00042000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_TAR_MAX_INDEX            383
 #define I40E_VSI_TAR_ACCEPTTAGGED_SHIFT   0
 #define I40E_VSI_TAR_ACCEPTTAGGED_MASK    I40E_MASK(0x3FF, I40E_VSI_TAR_ACCEPTTAGGED_SHIFT)
 #define I40E_VSI_TAR_ACCEPTUNTAGGED_SHIFT 16
 #define I40E_VSI_TAR_ACCEPTUNTAGGED_MASK  I40E_MASK(0x3FF, I40E_VSI_TAR_ACCEPTUNTAGGED_SHIFT)
 
-#define I40E_VSI_TIR_0(_VSI)             (0x00040000 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_TIR_0(_VSI)             (0x00040000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_TIR_0_MAX_INDEX         383
 #define I40E_VSI_TIR_0_PORT_TAG_ID_SHIFT 0
 #define I40E_VSI_TIR_0_PORT_TAG_ID_MASK  I40E_MASK(0xFFFF, I40E_VSI_TIR_0_PORT_TAG_ID_SHIFT)
 
-#define I40E_VSI_TIR_1(_VSI)             (0x00040800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_TIR_1(_VSI)             (0x00040800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_TIR_1_MAX_INDEX         383
 #define I40E_VSI_TIR_1_PORT_TAG_ID_SHIFT 0
 #define I40E_VSI_TIR_1_PORT_TAG_ID_MASK  I40E_MASK(0xFFFFFFFF, I40E_VSI_TIR_1_PORT_TAG_ID_SHIFT)
 
-#define I40E_VSI_TIR_2(_VSI)             (0x00041000 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_TIR_2(_VSI)             (0x00041000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_TIR_2_MAX_INDEX         383
 #define I40E_VSI_TIR_2_PORT_TAG_ID_SHIFT 0
 #define I40E_VSI_TIR_2_PORT_TAG_ID_MASK  I40E_MASK(0xFFFF, I40E_VSI_TIR_2_PORT_TAG_ID_SHIFT)
 
-#define I40E_VSI_TSR(_VSI)             (0x00050800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_TSR(_VSI)             (0x00050800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_TSR_MAX_INDEX         383
 #define I40E_VSI_TSR_STRIPTAG_SHIFT    0
 #define I40E_VSI_TSR_STRIPTAG_MASK     I40E_MASK(0x3FF, I40E_VSI_TSR_STRIPTAG_SHIFT)
@@ -10158,7 +10550,7 @@
 #define I40E_VSI_TSR_SHOWPRIONLY_SHIFT 20
 #define I40E_VSI_TSR_SHOWPRIONLY_MASK  I40E_MASK(0x3FF, I40E_VSI_TSR_SHOWPRIONLY_SHIFT)
 
-#define I40E_VSI_TUPIOM(_VSI)     (0x00043800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_TUPIOM(_VSI)     (0x00043800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_TUPIOM_MAX_INDEX 383
 #define I40E_VSI_TUPIOM_UP0_SHIFT 0
 #define I40E_VSI_TUPIOM_UP0_MASK  I40E_MASK(0x7, I40E_VSI_TUPIOM_UP0_SHIFT)
@@ -10177,7 +10569,7 @@
 #define I40E_VSI_TUPIOM_UP7_SHIFT 21
 #define I40E_VSI_TUPIOM_UP7_MASK  I40E_MASK(0x7, I40E_VSI_TUPIOM_UP7_SHIFT)
 
-#define I40E_VSI_TUPR(_VSI)     (0x00043000 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_TUPR(_VSI)     (0x00043000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_TUPR_MAX_INDEX 383
 #define I40E_VSI_TUPR_UP0_SHIFT 0
 #define I40E_VSI_TUPR_UP0_MASK  I40E_MASK(0x7, I40E_VSI_TUPR_UP0_SHIFT)
@@ -10196,7 +10588,7 @@
 #define I40E_VSI_TUPR_UP7_SHIFT 21
 #define I40E_VSI_TUPR_UP7_MASK  I40E_MASK(0x7, I40E_VSI_TUPR_UP7_SHIFT)
 
-#define I40E_VSI_VSI2F(_VSI)              (0x0020B800 + ((_VSI) * 4)) /* _i=0...383 */
+#define I40E_VSI_VSI2F(_VSI)              (0x0020B800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
 #define I40E_VSI_VSI2F_MAX_INDEX          383
 #define I40E_VSI_VSI2F_VFVMNUMBER_SHIFT   0
 #define I40E_VSI_VSI2F_VFVMNUMBER_MASK    I40E_MASK(0x3FF, I40E_VSI_VSI2F_VFVMNUMBER_SHIFT)
@@ -10215,17 +10607,17 @@
 
 /* PF - Wake-Up and Proxying Registers  */
 
-#define I40E_PFPM_FHFT_DATA(_i, _j)      (0x00060000 + ((_i) * 4096 + (_j) * 128)) /* _i=0...7, _j=0...31 */
+#define I40E_PFPM_FHFT_DATA(_i, _j)      (0x00060000 + ((_i) * 4096 + (_j) * 128)) /* _i=0...7, _j=0...31 */ /* Reset: POR */
 #define I40E_PFPM_FHFT_DATA_MAX_INDEX   7
 #define I40E_PFPM_FHFT_DATA_DWORD_SHIFT 0
 #define I40E_PFPM_FHFT_DATA_DWORD_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFPM_FHFT_DATA_DWORD_SHIFT)
 
-#define I40E_PFPM_FHFT_MASK(_i, _j)     (0x00068000 + ((_i) * 1024 + (_j) * 128)) /* _i=0...7, _j=0...7 */
+#define I40E_PFPM_FHFT_MASK(_i, _j)     (0x00068000 + ((_i) * 1024 + (_j) * 128)) /* _i=0...7, _j=0...7 */ /* Reset: POR */
 #define I40E_PFPM_FHFT_MASK_MAX_INDEX  7
 #define I40E_PFPM_FHFT_MASK_MASK_SHIFT 0
 #define I40E_PFPM_FHFT_MASK_MASK_MASK  I40E_MASK(0xFFFF, I40E_PFPM_FHFT_MASK_MASK_SHIFT)
 
-#define I40E_PFPM_PROXYFC                    0x00245A80
+#define I40E_PFPM_PROXYFC                    0x00245A80 /* Reset: POR */
 #define I40E_PFPM_PROXYFC_PPROXYE_SHIFT      0
 #define I40E_PFPM_PROXYFC_PPROXYE_MASK       I40E_MASK(0x1, I40E_PFPM_PROXYFC_PPROXYE_SHIFT)
 #define I40E_PFPM_PROXYFC_EX_SHIFT           1
@@ -10241,7 +10633,7 @@
 #define I40E_PFPM_PROXYFC_MLD_SHIFT          12
 #define I40E_PFPM_PROXYFC_MLD_MASK           I40E_MASK(0x1, I40E_PFPM_PROXYFC_MLD_SHIFT)
 
-#define I40E_PFPM_PROXYS                    0x00245B80
+#define I40E_PFPM_PROXYS                    0x00245B80 /* Reset: POR */
 #define I40E_PFPM_PROXYS_EX_SHIFT           1
 #define I40E_PFPM_PROXYS_EX_MASK            I40E_MASK(0x1, I40E_PFPM_PROXYS_EX_SHIFT)
 #define I40E_PFPM_PROXYS_ARP_SHIFT          4
@@ -10261,7 +10653,7 @@
 
 /* VF - Interrupts */
 
-#define I40E_VFINT_ITR0_STAT1(_i)              (0x00004400 + ((_i) * 4)) /* _i=0...2 */
+#define I40E_VFINT_ITR0_STAT1(_i)              (0x00004400 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
 #define I40E_VFINT_ITR0_STAT1_MAX_INDEX        2
 #define I40E_VFINT_ITR0_STAT1_ITR_EXPIRE_SHIFT 0
 #define I40E_VFINT_ITR0_STAT1_ITR_EXPIRE_MASK  I40E_MASK(0x1, I40E_VFINT_ITR0_STAT1_ITR_EXPIRE_SHIFT)
@@ -10270,7 +10662,7 @@
 #define I40E_VFINT_ITR0_STAT1_ITR_TIME_SHIFT   2
 #define I40E_VFINT_ITR0_STAT1_ITR_TIME_MASK    I40E_MASK(0xFFF, I40E_VFINT_ITR0_STAT1_ITR_TIME_SHIFT)
 
-#define I40E_VFINT_ITRN_STAT1(_i, _INTVF)       (0x00003000 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */
+#define I40E_VFINT_ITRN_STAT1(_i, _INTVF)       (0x00003000 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
 #define I40E_VFINT_ITRN_STAT1_MAX_INDEX        2
 #define I40E_VFINT_ITRN_STAT1_ITR_EXPIRE_SHIFT 0
 #define I40E_VFINT_ITRN_STAT1_ITR_EXPIRE_MASK  I40E_MASK(0x1, I40E_VFINT_ITRN_STAT1_ITR_EXPIRE_SHIFT)
@@ -10279,13 +10671,13 @@
 #define I40E_VFINT_ITRN_STAT1_ITR_TIME_SHIFT   2
 #define I40E_VFINT_ITRN_STAT1_ITR_TIME_MASK    I40E_MASK(0xFFF, I40E_VFINT_ITRN_STAT1_ITR_TIME_SHIFT)
 
-#define I40E_VFINT_RATE0_STAT1                  0x00005800
+#define I40E_VFINT_RATE0_STAT1                  0x00005800 /* Reset: VFR */
 #define I40E_VFINT_RATE0_STAT1_CREDIT_SHIFT     0
 #define I40E_VFINT_RATE0_STAT1_CREDIT_MASK      I40E_MASK(0xF, I40E_VFINT_RATE0_STAT1_CREDIT_SHIFT)
 #define I40E_VFINT_RATE0_STAT1_INTRL_TIME_SHIFT 4
 #define I40E_VFINT_RATE0_STAT1_INTRL_TIME_MASK  I40E_MASK(0x3F, I40E_VFINT_RATE0_STAT1_INTRL_TIME_SHIFT)
 
-#define I40E_VFINT_RATEN_STAT1(_INTVF)          (0x00004000 + ((_INTVF) * 4)) /* _i=0...15 */
+#define I40E_VFINT_RATEN_STAT1(_INTVF)          (0x00004000 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
 #define I40E_VFINT_RATEN_STAT1_MAX_INDEX        15
 #define I40E_VFINT_RATEN_STAT1_CREDIT_SHIFT     0
 #define I40E_VFINT_RATEN_STAT1_CREDIT_MASK      I40E_MASK(0xF, I40E_VFINT_RATEN_STAT1_CREDIT_SHIFT)
@@ -10300,27 +10692,20 @@
 
 /* VF - Rx Filters Registers */
 
-#define I40E_VPQF_DDPCNT               0x0000C800
+#define I40E_VPQF_DDPCNT               0x0000C800 /* Reset: CORER */
 #define I40E_VPQF_DDPCNT_DDP_CNT_SHIFT 0
 #define I40E_VPQF_DDPCNT_DDP_CNT_MASK  I40E_MASK(0x1FFF, I40E_VPQF_DDPCNT_DDP_CNT_SHIFT)
 
 /* VF - Time Sync Registers */
 
-#define I40E_PRTTSYN_VFTIME_H1                  0x0000E020
+#define I40E_PRTTSYN_VFTIME_H1                  0x0000E020 /* Reset: GLOBR */
 #define I40E_PRTTSYN_VFTIME_H1_TSYNTIME_H_SHIFT 0
 #define I40E_PRTTSYN_VFTIME_H1_TSYNTIME_H_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_VFTIME_H1_TSYNTIME_H_SHIFT)
 
-#define I40E_PRTTSYN_VFTIME_L1                  0x0000E000
+#define I40E_PRTTSYN_VFTIME_L1                  0x0000E000 /* Reset: GLOBR */
 #define I40E_PRTTSYN_VFTIME_L1_TSYNTIME_L_SHIFT 0
 #define I40E_PRTTSYN_VFTIME_L1_TSYNTIME_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_VFTIME_L1_TSYNTIME_L_SHIFT)
 
-/* FPGA supported register */
-#define I40E_GLGEN_PE_ENA                     0x000B81A0
-#define I40E_GLGEN_PE_ENA_PE_ENA_SHIFT         0
-#define I40E_GLGEN_PE_ENA_PE_ENA_MASK    (0x1 << I40E_GLGEN_PE_ENA_PE_ENA_SHIFT)
-#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT 1
-#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_MASK  (0x3 << I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT)
-
 /* Used in A0 code flow */
 #define I40E_GLHMC_PEXFMAX                0x000C2048
 #define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0
diff --git a/sys/dev/i40e/i40e_txrx.c b/sys/dev/i40e/i40e_txrx.c
index 8b41cd4..e6fdc46 100755
--- a/sys/dev/i40e/i40e_txrx.c
+++ b/sys/dev/i40e/i40e_txrx.c
@@ -38,12 +38,15 @@
 ** 	    both the BASE and the VF drivers.
 */
 
+#ifdef HAVE_KERNEL_OPTION_HEADERS
 #include "opt_inet.h"
 #include "opt_inet6.h"
+#endif
+
 #include "i40e.h"
 
 /* Local Prototypes */
-static void	i40e_rx_checksum(struct mbuf *, u32, u32, u32);
+static void	i40e_rx_checksum(struct mbuf *, u32, u32, u8);
 static void	i40e_refresh_mbufs(struct i40e_queue *, int);
 static int      i40e_xmit(struct i40e_queue *, struct mbuf **);
 static int	i40e_tx_setup_offload(struct i40e_queue *,
@@ -52,7 +55,7 @@ static bool	i40e_tso_setup(struct i40e_queue *, struct mbuf *);
 
 static __inline void i40e_rx_discard(struct rx_ring *, int);
 static __inline void i40e_rx_input(struct rx_ring *, struct ifnet *,
-		    struct mbuf *, u32);
+		    struct mbuf *, u8);
 
 /*
 ** Multiqueue Transmit driver
@@ -72,6 +75,10 @@ i40e_mq_start(struct ifnet *ifp, struct mbuf *m)
 	else
 		i = curcpu % vsi->num_queues;
 
+	/* Check for a hung queue and pick alternative */
+	if (((1 << i) & vsi->active_queues) == 0)
+		i = ffsl(vsi->active_queues);
+
 	que = &vsi->queues[i];
 	txr = &que->txr;
 
@@ -79,12 +86,12 @@ i40e_mq_start(struct ifnet *ifp, struct mbuf *m)
 	if (err)
 		return(err);
 	if (I40E_TX_TRYLOCK(txr)) {
-		err = i40e_mq_start_locked(ifp, txr);
+		i40e_mq_start_locked(ifp, txr);
 		I40E_TX_UNLOCK(txr);
 	} else
 		taskqueue_enqueue(que->tq, &que->tx_task);
 
-	return (err);
+	return (0);
 }
 
 int
@@ -159,6 +166,34 @@ i40e_qflush(struct ifnet *ifp)
 	if_qflush(ifp);
 }
 
+/*
+** Find mbuf chains passed to the driver 
+** that are 'sparse', using more than 8
+** mbufs to deliver an mss-size chunk of data
+*/
+static inline bool
+i40e_tso_detect_sparse(struct mbuf *mp)
+{
+	struct mbuf	*m;
+	int		num = 0, mss;
+	bool		ret = FALSE;
+
+	mss = mp->m_pkthdr.tso_segsz;
+	for (m = mp->m_next; m != NULL; m = m->m_next) {
+		num++;
+		mss -= m->m_len;
+		if (mss < 1)
+			break;
+		if (m->m_next == NULL)
+			break;
+	}
+	if (num > I40E_SPARSE_CHAIN)
+		ret = TRUE;
+
+	return (ret);
+}
+
+
 /*********************************************************************
  *
  *  This routine maps the mbufs to tx descriptors, allowing the
@@ -176,22 +211,19 @@ i40e_xmit(struct i40e_queue *que, struct mbuf **m_headp)
 	struct tx_ring		*txr = &que->txr;
 	struct i40e_tx_buf	*buf;
 	struct i40e_tx_desc	*txd = NULL;
-	struct mbuf		*m_head;
-	int             	i, j, error, nsegs;
+	struct mbuf		*m_head, *m;
+	int             	i, j, error, nsegs, maxsegs;
 	int			first, last = 0;
 	u16			vtag = 0;
 	u32			cmd, off;
 	bus_dmamap_t		map;
-	bus_dma_segment_t	segs[I40E_MAX_SEGS];
+	bus_dma_tag_t		tag;
+	bus_dma_segment_t	segs[I40E_MAX_TSO_SEGS];
 
 
 	cmd = off = 0;
 	m_head = *m_headp;
 
-	/* Grab the VLAN tag */
-	if (m_head->m_flags & M_VLANTAG)
-		vtag = htole16(m_head->m_pkthdr.ether_vtag);
-
         /*
          * Important to capture the first descriptor
          * used because it will contain the index of
@@ -200,17 +232,29 @@ i40e_xmit(struct i40e_queue *que, struct mbuf **m_headp)
         first = txr->next_avail;
 	buf = &txr->buffers[first];
 	map = buf->map;
+	tag = txr->tx_tag;
+	maxsegs = I40E_MAX_TX_SEGS;
+
+	if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
+		/* Use larger mapping for TSO */
+		tag = txr->tso_tag;
+		maxsegs = I40E_MAX_TSO_SEGS;
+		if (i40e_tso_detect_sparse(m_head)) {
+			m = m_defrag(m_head, M_NOWAIT);
+			*m_headp = m;
+		}
+	}
 
 	/*
 	 * Map the packet for DMA.
 	 */
-	error = bus_dmamap_load_mbuf_sg(txr->tag, map,
+	error = bus_dmamap_load_mbuf_sg(tag, map,
 	    *m_headp, segs, &nsegs, BUS_DMA_NOWAIT);
 
 	if (error == EFBIG) {
 		struct mbuf *m;
 
-		m = m_defrag(*m_headp, M_NOWAIT);
+		m = m_collapse(*m_headp, M_NOWAIT, maxsegs);
 		if (m == NULL) {
 			que->mbuf_defrag_failed++;
 			m_freem(*m_headp);
@@ -220,7 +264,7 @@ i40e_xmit(struct i40e_queue *que, struct mbuf **m_headp)
 		*m_headp = m;
 
 		/* Try it again */
-		error = bus_dmamap_load_mbuf_sg(txr->tag, map,
+		error = bus_dmamap_load_mbuf_sg(tag, map,
 		    *m_headp, segs, &nsegs, BUS_DMA_NOWAIT);
 
 		if (error == ENOMEM) {
@@ -251,20 +295,25 @@ i40e_xmit(struct i40e_queue *que, struct mbuf **m_headp)
 	m_head = *m_headp;
 
 	/* Set up the TSO/CSUM offload */
-	error = i40e_tx_setup_offload(que, m_head, &cmd, &off);
-	if (error)
-		goto xmit_fail;
+	if (m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) {
+		error = i40e_tx_setup_offload(que, m_head, &cmd, &off);
+		if (error)
+			goto xmit_fail;
+	}
 
 	cmd |= I40E_TX_DESC_CMD_ICRC;
-	/* Add vlan tag to each descriptor */
-	if (m_head->m_flags & M_VLANTAG)
+	/* Grab the VLAN tag */
+	if (m_head->m_flags & M_VLANTAG) {
 		cmd |= I40E_TX_DESC_CMD_IL2TAG1;
+		vtag = htole16(m_head->m_pkthdr.ether_vtag);
+	}
 
 	i = txr->next_avail;
 	for (j = 0; j < nsegs; j++) {
 		bus_size_t seglen;
 
 		buf = &txr->buffers[i];
+		buf->tag = tag; /* Keep track of the type tag */
 		txd = &txr->base[i];
 		seglen = segs[j].ds_len;
 
@@ -294,7 +343,7 @@ i40e_xmit(struct i40e_queue *que, struct mbuf **m_headp)
 	/* Swap the dma map between the first and last descriptor */
 	txr->buffers[first].map = buf->map;
 	buf->map = map;
-	bus_dmamap_sync(txr->tag, map, BUS_DMASYNC_PREWRITE);
+	bus_dmamap_sync(tag, map, BUS_DMASYNC_PREWRITE);
 
         /* Set the index of the descriptor that will be marked done */
         buf = &txr->buffers[first];
@@ -307,8 +356,8 @@ i40e_xmit(struct i40e_queue *que, struct mbuf **m_headp)
 	 * hardware that this frame is available to transmit.
 	 */
 	++txr->total_packets;
+	wr32(hw, txr->tail, i);
 
-	wr32(hw, I40E_QTX_TAIL(que->me), i);
 	i40e_flush(hw);
 	/* Mark outstanding work */
 	if (que->busy == 0)
@@ -316,7 +365,7 @@ i40e_xmit(struct i40e_queue *que, struct mbuf **m_headp)
 	return (0);
 
 xmit_fail:
-	bus_dmamap_unload(txr->tag, buf->map);
+	bus_dmamap_unload(tag, buf->map);
 	return (error);
 }
 
@@ -341,21 +390,38 @@ i40e_allocate_tx_data(struct i40e_queue *que)
 	 * Setup DMA descriptor areas.
 	 */
 	if ((error = bus_dma_tag_create(NULL,		/* parent */
-			       1, 0,		/* alignment, bounds */
+			       1, 0,			/* alignment, bounds */
 			       BUS_SPACE_MAXADDR,	/* lowaddr */
 			       BUS_SPACE_MAXADDR,	/* highaddr */
 			       NULL, NULL,		/* filter, filterarg */
 			       I40E_TSO_SIZE,		/* maxsize */
-			       32,
+			       I40E_MAX_TX_SEGS,	/* nsegments */
 			       PAGE_SIZE,		/* maxsegsize */
 			       0,			/* flags */
 			       NULL,			/* lockfunc */
 			       NULL,			/* lockfuncarg */
-			       &txr->tag))) {
+			       &txr->tx_tag))) {
 		device_printf(dev,"Unable to allocate TX DMA tag\n");
 		goto fail;
 	}
 
+	/* Make a special tag for TSO */
+	if ((error = bus_dma_tag_create(NULL,		/* parent */
+			       1, 0,			/* alignment, bounds */
+			       BUS_SPACE_MAXADDR,	/* lowaddr */
+			       BUS_SPACE_MAXADDR,	/* highaddr */
+			       NULL, NULL,		/* filter, filterarg */
+			       I40E_TSO_SIZE,		/* maxsize */
+			       I40E_MAX_TSO_SEGS,	/* nsegments */
+			       PAGE_SIZE,		/* maxsegsize */
+			       0,			/* flags */
+			       NULL,			/* lockfunc */
+			       NULL,			/* lockfuncarg */
+			       &txr->tso_tag))) {
+		device_printf(dev,"Unable to allocate TX TSO DMA tag\n");
+		goto fail;
+	}
+
 	if (!(txr->buffers =
 	    (struct i40e_tx_buf *) malloc(sizeof(struct i40e_tx_buf) *
 	    que->num_desc, M_DEVBUF, M_NOWAIT | M_ZERO))) {
@@ -364,10 +430,11 @@ i40e_allocate_tx_data(struct i40e_queue *que)
 		goto fail;
 	}
 
-        /* Create the descriptor buffer dma maps */
+        /* Create the descriptor buffer default dma maps */
 	buf = txr->buffers;
 	for (int i = 0; i < que->num_desc; i++, buf++) {
-		error = bus_dmamap_create(txr->tag, 0, &buf->map);
+		buf->tag = txr->tx_tag;
+		error = bus_dmamap_create(buf->tag, 0, &buf->map);
 		if (error != 0) {
 			device_printf(dev, "Unable to create TX DMA map\n");
 			goto fail;
@@ -410,9 +477,9 @@ i40e_init_tx_ring(struct i40e_queue *que)
         buf = txr->buffers;
 	for (int i = 0; i < que->num_desc; i++, buf++) {
 		if (buf->m_head != NULL) {
-			bus_dmamap_sync(txr->tag, buf->map,
+			bus_dmamap_sync(buf->tag, buf->map,
 			    BUS_DMASYNC_POSTWRITE);
-			bus_dmamap_unload(txr->tag, buf->map);
+			bus_dmamap_unload(buf->tag, buf->map);
 			m_freem(buf->m_head);
 			buf->m_head = NULL;
 		}
@@ -445,21 +512,21 @@ i40e_free_que_tx(struct i40e_queue *que)
 	for (int i = 0; i < que->num_desc; i++) {
 		buf = &txr->buffers[i];
 		if (buf->m_head != NULL) {
-			bus_dmamap_sync(txr->tag, buf->map,
+			bus_dmamap_sync(buf->tag, buf->map,
 			    BUS_DMASYNC_POSTWRITE);
-			bus_dmamap_unload(txr->tag,
+			bus_dmamap_unload(buf->tag,
 			    buf->map);
 			m_freem(buf->m_head);
 			buf->m_head = NULL;
 			if (buf->map != NULL) {
-				bus_dmamap_destroy(txr->tag,
+				bus_dmamap_destroy(buf->tag,
 				    buf->map);
 				buf->map = NULL;
 			}
 		} else if (buf->map != NULL) {
-			bus_dmamap_unload(txr->tag,
+			bus_dmamap_unload(buf->tag,
 			    buf->map);
-			bus_dmamap_destroy(txr->tag,
+			bus_dmamap_destroy(buf->tag,
 			    buf->map);
 			buf->map = NULL;
 		}
@@ -470,9 +537,13 @@ i40e_free_que_tx(struct i40e_queue *que)
 		free(txr->buffers, M_DEVBUF);
 		txr->buffers = NULL;
 	}
-	if (txr->tag != NULL) {
-		bus_dma_tag_destroy(txr->tag);
-		txr->tag = NULL;
+	if (txr->tx_tag != NULL) {
+		bus_dma_tag_destroy(txr->tx_tag);
+		txr->tx_tag = NULL;
+	}
+	if (txr->tso_tag != NULL) {
+		bus_dma_tag_destroy(txr->tso_tag);
+		txr->tso_tag = NULL;
 	}
 	return;
 }
@@ -549,8 +620,7 @@ i40e_tx_setup_offload(struct i40e_queue *que,
 	switch (ipproto) {
 		case IPPROTO_TCP:
 			tcp_hlen = th->th_off << 2;
-			if (mp->m_pkthdr.csum_flags & CSUM_TCP || 
-				mp->m_pkthdr.csum_flags & CSUM_TCP_IPV6) {
+			if (mp->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_TCP_IPV6)) {
 				*cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 				*off |= (tcp_hlen >> 2) <<
 				    I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
@@ -560,8 +630,7 @@ i40e_tx_setup_offload(struct i40e_queue *que,
 #endif
 			break;
 		case IPPROTO_UDP:
-			if (mp->m_pkthdr.csum_flags & CSUM_UDP ||
-				mp->m_pkthdr.csum_flags & CSUM_UDP_IPV6) {
+			if (mp->m_pkthdr.csum_flags & (CSUM_UDP|CSUM_UDP_IPV6)) {
 				*cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 				*off |= (sizeof(struct udphdr) >> 2) <<
 				    I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
@@ -569,7 +638,7 @@ i40e_tx_setup_offload(struct i40e_queue *que,
 			break;
 
 		case IPPROTO_SCTP:
-			if (mp->m_pkthdr.csum_flags & CSUM_SCTP) {
+			if (mp->m_pkthdr.csum_flags & (CSUM_SCTP|CSUM_SCTP_IPV6)) {
 				*cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 				*off |= (sizeof(struct sctphdr) >> 2) <<
 				    I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
@@ -679,6 +748,18 @@ i40e_tso_setup(struct i40e_queue *que, struct mbuf *mp)
 	return TRUE;
 }
 
+/*             
+** i40e_get_tx_head - Retrieve the value from the 
+**    location the HW records its HEAD index
+*/
+static inline u32
+i40e_get_tx_head(struct i40e_queue *que)
+{
+	struct tx_ring  *txr = &que->txr;
+	void *head = &txr->base[que->num_desc];
+	return LE32_TO_CPU(*(volatile __le32 *)head);
+}
+
 /**********************************************************************
  *
  *  Examine each tx_buffer in the used queue. If the hardware is done
@@ -692,7 +773,7 @@ i40e_txeof(struct i40e_queue *que)
 	struct i40e_vsi		*vsi = que->vsi;
 	struct ifnet		*ifp = vsi->ifp;
 	struct tx_ring		*txr = &que->txr;
-	u32			first, last, done, processed;
+	u32			first, last, head, done, processed;
 	struct i40e_tx_buf	*buf;
 	struct i40e_tx_desc	*tx_desc, *eop_desc;
 
@@ -715,6 +796,9 @@ i40e_txeof(struct i40e_queue *que)
 		return FALSE;
 	eop_desc = (struct i40e_tx_desc *)&txr->base[last];
 
+	/* Get the Head WB value */
+	head = i40e_get_tx_head(que);
+
 	/*
 	** Get the index of the first descriptor
 	** BEYOND the EOP and call that 'done'.
@@ -727,25 +811,24 @@ i40e_txeof(struct i40e_queue *que)
         bus_dmamap_sync(txr->dma.tag, txr->dma.map,
             BUS_DMASYNC_POSTREAD);
 	/*
-	** Only the EOP descriptor of a packet now has the DD
-	** bit set, this is what we look for...
+	** The HEAD index of the ring is written in a 
+	** defined location, this rather than a done bit
+	** is what is used to keep track of what must be
+	** 'cleaned'.
 	*/
-	while (eop_desc->cmd_type_offset_bsz &
-	    htole32(I40E_TX_DESC_DTYPE_DESC_DONE)) {
+	while (first != head) {
 		/* We clean the range of the packet */
 		while (first != done) {
-			tx_desc->cmd_type_offset_bsz &=
-			    ~I40E_TXD_QW1_DTYPE_MASK;
 			++txr->avail;
 			++processed;
 
 			if (buf->m_head) {
 				txr->bytes +=
 				    buf->m_head->m_pkthdr.len;
-				bus_dmamap_sync(txr->tag,
+				bus_dmamap_sync(buf->tag,
 				    buf->map,
 				    BUS_DMASYNC_POSTWRITE);
-				bus_dmamap_unload(txr->tag,
+				bus_dmamap_unload(buf->tag,
 				    buf->map);
 				m_freem(buf->m_head);
 				buf->m_head = NULL;
@@ -786,10 +869,11 @@ i40e_txeof(struct i40e_queue *que)
 	** be considered hung. If anything has been
 	** cleaned then reset the state.
 	*/
-	if (!processed)
+	if ((processed == 0) && (que->busy != I40E_QUEUE_HUNG))
 		++que->busy;
-	else
-		que->busy = 1;
+
+	if (processed)
+		que->busy = 1; /* Note this turns off HUNG */
 
 	/*
 	 * If there are no pending descriptors, clear the timeout.
@@ -884,6 +968,7 @@ no_split:
 		    BUS_DMASYNC_PREREAD);
 		rxr->base[i].read.pkt_addr =
 		   htole64(pseg[0].ds_addr);
+		/* Used only when doing header split */
 		rxr->base[i].read.hdr_addr = 0;
 
 		refreshed = TRUE;
@@ -895,7 +980,7 @@ no_split:
 	}
 update:
 	if (refreshed) /* Update hardware tail index */
-		wr32(vsi->hw, I40E_QRX_TAIL(que->me), rxr->next_refresh);
+		wr32(vsi->hw, rxr->tail, rxr->next_refresh);
 	return;
 }
 
@@ -1020,6 +1105,7 @@ i40e_init_rx_ring(struct i40e_queue *que)
 		buf->m_pack = NULL;
 	}
 
+	/* header split is off */
 	rxr->hdr_split = FALSE;
 
 	/* Now replenish the mbufs */
@@ -1170,7 +1256,7 @@ i40e_free_que_rx(struct i40e_queue *que)
 }
 
 static __inline void
-i40e_rx_input(struct rx_ring *rxr, struct ifnet *ifp, struct mbuf *m, u32 ptype)
+i40e_rx_input(struct rx_ring *rxr, struct ifnet *ifp, struct mbuf *m, u8 ptype)
 {
         /*
          * ATM LRO is only for IPv4/TCP packets and TCP checksum of the packet
@@ -1260,9 +1346,10 @@ i40e_rxeof(struct i40e_queue *que, int count)
 
 	for (i = rxr->next_check; count != 0;) {
 		struct mbuf	*sendmp, *mh, *mp;
-		u32		rsc, ptype, status, error;
+		u32		rsc, status, error;
 		u16		hlen, plen, vtag;
 		u64		qword;
+		u8		ptype;
 		bool		eop;
  
 		/* Sync the ring. */
@@ -1478,8 +1565,11 @@ next_desc:
  *
  *********************************************************************/
 static void
-i40e_rx_checksum(struct mbuf * mp, u32 status, u32 error, u32 ptype)
+i40e_rx_checksum(struct mbuf * mp, u32 status, u32 error, u8 ptype)
 {
+	struct i40e_rx_ptype_decoded decoded;
+
+	decoded = decode_rx_desc_ptype(ptype);
 
 	/* Errors? */
  	if (error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
@@ -1488,6 +1578,16 @@ i40e_rx_checksum(struct mbuf * mp, u32 status, u32 error, u32 ptype)
 		return;
 	}
 
+	/* IPv6 with extension headers likely have bad csum */
+	if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
+	    decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
+		if (status &
+		    (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) {
+			mp->m_pkthdr.csum_flags = 0;
+			return;
+		}
+
+ 
 	/* IP Checksum Good */
 	mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
 	mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
diff --git a/sys/dev/i40e/i40e_type.h b/sys/dev/i40e/i40e_type.h
index cde31ad..093cfbd 100755
--- a/sys/dev/i40e/i40e_type.h
+++ b/sys/dev/i40e/i40e_type.h
@@ -56,9 +56,6 @@
 #define I40E_DEV_ID_QSFP_A		0x1583
 #define I40E_DEV_ID_QSFP_B		0x1584
 #define I40E_DEV_ID_QSFP_C		0x1585
-#ifdef FORTVILLE_A0_SUPPORT
-#define I40E_DEV_ID_10G_BASE_T		0x1586
-#endif
 #define I40E_DEV_ID_VF			0x154C
 #define I40E_DEV_ID_VF_HV		0x1571
 
@@ -66,8 +63,10 @@
 					 (d) == I40E_DEV_ID_QSFP_B  || \
 					 (d) == I40E_DEV_ID_QSFP_C)
 
+#ifndef I40E_MASK
 /* I40E_MASK is a macro used on 32 bit registers */
 #define I40E_MASK(mask, shift) (mask << shift)
+#endif
 
 #define I40E_MAX_PF			16
 #define I40E_MAX_PF_VSI			64
@@ -214,10 +213,10 @@ enum i40e_fc_mode {
 
 enum i40e_set_fc_aq_failures {
 	I40E_SET_FC_AQ_FAIL_NONE = 0,
-	I40E_SET_FC_AQ_FAIL_GET1 = 1,
+	I40E_SET_FC_AQ_FAIL_GET = 1,
 	I40E_SET_FC_AQ_FAIL_SET = 2,
-	I40E_SET_FC_AQ_FAIL_GET2 = 4,
-	I40E_SET_FC_AQ_FAIL_SET_GET = 6
+	I40E_SET_FC_AQ_FAIL_UPDATE = 4,
+	I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 };
 
 enum i40e_vsi_type {
@@ -533,6 +532,10 @@ struct i40e_hw {
 
 	/* Admin Queue info */
 	struct i40e_adminq_info aq;
+#ifdef I40E_QV
+	bool aq_dbg_ena; /* use Tools AQ instead of PF AQ */
+	bool qv_force_init;
+#endif
 
 	/* state of nvm update process */
 	enum i40e_nvmupd_state nvmupd_state;
diff --git a/sys/dev/i40e/if_i40e.c b/sys/dev/i40e/if_i40e.c
index a763c0d..74e64bf 100755
--- a/sys/dev/i40e/if_i40e.c
+++ b/sys/dev/i40e/if_i40e.c
@@ -32,15 +32,18 @@
 ******************************************************************************/
 /*$FreeBSD$*/
 
+#ifdef HAVE_KERNEL_OPTION_HEADERS
 #include "opt_inet.h"
 #include "opt_inet6.h"
+#endif
+
 #include "i40e.h"
 #include "i40e_pf.h"
 
 /*********************************************************************
  *  Driver version
  *********************************************************************/
-char i40e_driver_version[] = "0.6.9 - Beta Release";
+char i40e_driver_version[] = "1.0.0";
 
 /*********************************************************************
  *  PCI Device ID Table
@@ -145,12 +148,14 @@ static void	i40e_print_debug_info(struct i40e_pf *);
 static void	i40e_intr(void *);
 static void	i40e_msix_que(void *);
 static void	i40e_msix_adminq(void *);
+static void	i40e_handle_mdd_event(struct i40e_pf *);
 
 /* Deferred interrupt tasklets */
 static void	i40e_do_adminq(void *, int);
 
 /* Sysctl handlers */
 static int	i40e_set_flowcntl(SYSCTL_HANDLER_ARGS);
+static int	i40e_set_advertise(SYSCTL_HANDLER_ARGS);
 
 /* Statistics */
 static void     i40e_add_hw_stats(struct i40e_pf *);
@@ -172,6 +177,8 @@ static void	i40e_stat_update32(struct i40e_hw *, u32, bool,
 static int 	i40e_sysctl_link_status(SYSCTL_HANDLER_ARGS);
 static int	i40e_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS);
 static int	i40e_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS);
+static int	i40e_sysctl_hw_res_info(SYSCTL_HANDLER_ARGS);
+static int	i40e_sysctl_dump_txd(SYSCTL_HANDLER_ARGS);
 #endif
 
 /*********************************************************************
@@ -188,7 +195,7 @@ static device_method_t i40e_methods[] = {
 };
 
 static driver_t i40e_driver = {
-	"i40e", i40e_methods, sizeof(struct i40e_pf),
+	"ixl", i40e_methods, sizeof(struct i40e_pf),
 };
 
 devclass_t i40e_devclass;
@@ -198,6 +205,11 @@ MODULE_DEPEND(i40e, pci, 1, 1, 1);
 MODULE_DEPEND(i40e, ether, 1, 1, 1);
 
 /*
+** Global reset mutex
+*/
+static struct mtx i40e_reset_mtx;
+
+/*
  * MSIX should be the default for best performance,
  * but this allows it to be forced off for testing.
  */
@@ -252,6 +264,7 @@ static char *i40e_fc_string[6] = {
 	"Default"
 };
 
+
 /*********************************************************************
  *  Device identification routine
  *
@@ -269,6 +282,7 @@ i40e_probe(device_t dev)
 	u16	pci_vendor_id, pci_device_id;
 	u16	pci_subvendor_id, pci_subdevice_id;
 	char	device_name[256];
+	static bool lock_init = FALSE;
 
 	INIT_DEBUGOUT("i40e_probe: begin");
 
@@ -294,6 +308,13 @@ i40e_probe(device_t dev)
 				i40e_strings[ent->index],
 				i40e_driver_version);
 			device_set_desc_copy(dev, device_name);
+			/* One shot mutex init */
+			if (lock_init == FALSE) {
+				lock_init = TRUE;
+				mtx_init(&i40e_reset_mtx,
+				    "i40e_reset",
+				    "I40E RESET Lock", MTX_DEF);
+			}
 			return (BUS_PROBE_DEFAULT);
 		}
 		ent++;
@@ -318,7 +339,6 @@ i40e_attach(device_t dev)
 	struct i40e_hw	*hw;
 	struct i40e_vsi *vsi;
 	u16		bus;
-	u32		reg;
 	int             error = 0;
 
 	INIT_DEBUGOUT("i40e_attach: begin");
@@ -347,6 +367,11 @@ i40e_attach(device_t dev)
 	    OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW,
 	    pf, 0, i40e_set_flowcntl, "I", "Flow Control");
 
+	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
+	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
+	    OID_AUTO, "advertise_speed", CTLTYPE_INT | CTLFLAG_RW,
+	    pf, 0, i40e_set_advertise, "I", "Advertised Speed");
+
 	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 	    OID_AUTO, "rx_itr", CTLTYPE_INT | CTLFLAG_RW,
@@ -382,6 +407,16 @@ i40e_attach(device_t dev)
 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 	    OID_AUTO, "filter_list", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, i40e_sysctl_sw_filter_list, "A", "SW Filter List");
+
+	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
+	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
+	    OID_AUTO, "hw_res_info", CTLTYPE_STRING | CTLFLAG_RD,
+	    pf, 0, i40e_sysctl_hw_res_info, "A", "HW Resource Allocation");
+
+	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
+	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
+	    OID_AUTO, "dump_desc", CTLTYPE_INT | CTLFLAG_WR,
+	    pf, 0, i40e_sysctl_dump_txd, "I", "Desc dump");
 #endif
 
 	/* Save off the information about this board */
@@ -393,7 +428,7 @@ i40e_attach(device_t dev)
 	hw->subsystem_device_id =
 	    pci_read_config(dev, PCIR_SUBDEV_0, 2);
 
-	hw->bus.device = pci_get_device(dev);
+	hw->bus.device = pci_get_slot(dev);
 	hw->bus.func = pci_get_function(dev);
 
 	/* Do PCI setup - map BAR0, etc */
@@ -409,31 +444,56 @@ i40e_attach(device_t dev)
 	    OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, pf, 0,
 	    i40e_debug_info, "I", "Debug Information");
 
-	/* Workaround to keep ARI detection off */
-	reg = rd32(hw, I40E_GLPCI_CAPSUP);
-	reg &= ~I40E_GLPCI_CAPSUP_ARI_EN_MASK;
-	wr32(hw, I40E_GLPCI_CAPSUP, reg);
 
 	/* Establish a clean starting point */
+	i40e_clear_hw(hw);
 	error = i40e_pf_reset(hw);
 	if (error) {
-		// TODO: Remove EMPR reset
-		/* Use the heavy hammer, force a firmware reset */
-		reg = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
-		reg |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
-		wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, reg);
-		/* force the reset */
-		reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
-		reg |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
-		wr32(&pf->hw, I40E_GLGEN_RTRIG, reg);
-		i40e_flush(hw);
+		device_printf(dev,"PF reset failure %x\n", error);
+		error = EIO;
+		goto err_out;
+	}
 
-		error = i40e_pf_reset(hw);
-		if (error) {
-			device_printf(dev,"PF reset failure %x\n", error);
-			error = EIO;
-			goto err_out;
+	/* For now always do an initial CORE reset on first device */
+	{
+		static int	i40e_dev_count;
+		static int	i40e_dev_track[32];
+		u32		my_dev;
+		int		i, found = FALSE;
+		u16		bus = pci_get_bus(dev);
+
+		mtx_lock(&i40e_reset_mtx);
+		my_dev = (bus << 8) | hw->bus.device;
+
+		for (i = 0; i < i40e_dev_count; i++) {
+			if (i40e_dev_track[i] == my_dev)
+				found = TRUE;
 		}
+
+                if (!found) {
+                        u32 reg;
+
+                        i40e_dev_track[i40e_dev_count] = my_dev;
+                        i40e_dev_count++;
+
+                        device_printf(dev, "Initial CORE RESET\n");
+                        wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
+                        i40e_flush(hw);
+                        i = 50;
+                        do {
+				i40e_msec_delay(50);
+                                reg = rd32(hw, I40E_GLGEN_RSTAT);
+                                if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
+                                        break;
+                        } while (i--);
+
+                        /* paranoia */
+                        wr32(hw, I40E_PF_ATQLEN, 0);
+                        wr32(hw, I40E_PF_ATQBAL, 0);
+                        wr32(hw, I40E_PF_ATQBAH, 0);
+                        i40e_clear_pxe_mode(hw);
+                }
+                mtx_unlock(&i40e_reset_mtx);
 	}
 
 	/* Set admin queue parameters */
@@ -453,17 +513,24 @@ i40e_attach(device_t dev)
 	/* Set up the admin queue */
 	error = i40e_init_adminq(hw);
 	if (error) {
-		device_printf(dev, "Admin Queue setup failure!\n");
+		device_printf(dev, "The driver for the device stopped "
+		    "because the NVM image is newer than expected.\n"
+		    "You must install the most recent version of "
+		    " the network driver.\n");
 		goto err_out;
 	}
-
-#ifdef I40E_DEBUG
-	device_printf(dev,"Firmware version: %d.%d "
-	    "API version %d.%d NVM track %x version %x\n", 
-	    hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
-	    hw->aq.api_maj_ver, hw->aq.api_min_ver,
-	    hw->nvm.eetrack, hw->nvm.version);
-#endif
+	device_printf(dev, "%s\n", i40e_fw_version_str(hw));
+
+        if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
+	    hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
+		device_printf(dev, "The driver for the device detected "
+		    "a newer version of the NVM image than expected.\n"
+		    "Please install the most recent version of the network driver.\n");
+	else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
+	    hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
+		device_printf(dev, "The driver for the device detected "
+		    "an older version of the NVM image than expected.\n"
+		    "Please update the NVM image.\n");
 
 	/* Clear PXE mode */
 	i40e_clear_pxe_mode(hw);
@@ -488,6 +555,9 @@ i40e_attach(device_t dev)
 		goto err_mac_hmc;
 	}
 
+	/* Disable LLDP from the firmware */
+	i40e_aq_stop_lldp(hw, TRUE, NULL);
+
 	i40e_get_mac_addr(hw, hw->mac.addr);
 	error = i40e_validate_mac_addr(hw->mac.addr);
 	if (error) {
@@ -517,6 +587,15 @@ i40e_attach(device_t dev)
 	/* Determine link state */
 	vsi->link_up = i40e_config_link(hw);
 
+	/* Report if Unqualified modules are found */
+	if ((vsi->link_up == FALSE) &&
+	    (pf->hw.phy.link_info.link_info &
+	    I40E_AQ_MEDIA_AVAILABLE) &&
+	    (!(pf->hw.phy.link_info.an_info &
+	    I40E_AQ_QUALIFIED_MODULE)))
+		device_printf(dev, "Link failed because "
+		    "an unqualified module was detected\n");
+
 	/* Setup OS specific network interface */
 	if (i40e_setup_interface(dev, vsi) != 0)
 		goto err_late;
@@ -536,6 +615,7 @@ i40e_attach(device_t dev)
 	vsi->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 	    i40e_unregister_vlan, vsi, EVENTHANDLER_PRI_FIRST);
 
+
 	INIT_DEBUGOUT("i40e_attach: end");
 	return (0);
 
@@ -1014,12 +1094,6 @@ i40e_init_locked(struct i40e_pf *pf)
 	} else
 		i40e_configure_legacy(pf);
 
-	/*
-	** Only a temporary workaround for RX hangs
-	*/
-	if (rd32(hw, I40E_PRTRPB_SLW) != 0x30000)
-		wr32(hw, I40E_PRTRPB_SLW, 0x30000);
-
 	i40e_enable_rings(vsi);
 
 	i40e_aq_set_default_vsi(hw, vsi->seid, NULL);
@@ -1171,6 +1245,10 @@ i40e_msix_que(void *arg)
 	struct tx_ring	*txr = &que->txr;
 	bool		more_tx, more_rx;
 
+	/* Protect against spurious interrupts */
+	if (!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING))
+		return;
+
 	++que->irqs;
 
 	more_rx = i40e_rxeof(que, I40E_RX_LIMIT);
@@ -1219,8 +1297,10 @@ i40e_msix_adminq(void *arg)
 	if (reg & I40E_PFINT_ICR0_ADMINQ_MASK)
 		mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
 
-	if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK)
+	if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
+		i40e_handle_mdd_event(pf);
 		mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
+	}
 
 	if (reg & I40E_PFINT_ICR0_VFLR_MASK)
 		mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
@@ -1274,6 +1354,12 @@ i40e_media_status(struct ifnet * ifp, struct ifmediareq * ifmr)
 		case I40E_PHY_TYPE_1000BASE_T:
 			ifmr->ifm_active |= IFM_1000_T;
 			break;
+		case I40E_PHY_TYPE_1000BASE_SX:
+			ifmr->ifm_active |= IFM_1000_SX;
+			break;
+		case I40E_PHY_TYPE_1000BASE_LX:
+			ifmr->ifm_active |= IFM_1000_LX;
+			break;
 		/* 10 G */
 		case I40E_PHY_TYPE_10GBASE_CR1_CU:
 		case I40E_PHY_TYPE_10GBASE_SFPP_CU:
@@ -1296,16 +1382,11 @@ i40e_media_status(struct ifnet * ifp, struct ifmediareq * ifmr)
 		case I40E_PHY_TYPE_40GBASE_LR4:
 			ifmr->ifm_active |= IFM_40G_LR4;
 			break;
-		/*
-		 * FreeBSD doesn't know about the other phy
-		 * types this hardware supports.
-		 */
 		default:
 			ifmr->ifm_active |= IFM_UNKNOWN;
 			break;
 	}
 	/* Report flow control status as well */
-	/* TODO: Something special if PFC is enabled instead */
 	if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
 		ifmr->ifm_active |= IFM_ETH_TXPAUSE;
 	if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
@@ -1335,7 +1416,9 @@ i40e_media_change(struct ifnet * ifp)
 	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 		return (EINVAL);
 
-	return (0);
+	if_printf(ifp, "Media change is currently not supported.\n");
+
+	return (ENODEV);
 }
 
 
@@ -1568,7 +1651,7 @@ i40e_local_timer(void *arg)
 	i40e_update_stats_counters(pf);
 
 	/*
-	** Check status on the queues for a hang
+	** Check status of the queues
 	*/
 	mask = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
 		I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
@@ -1582,9 +1665,20 @@ i40e_local_timer(void *arg)
 		** are uncleaned descriptors it increments busy. If
 		** we get to 5 we declare it hung.
 		*/
+		if (que->busy == I40E_QUEUE_HUNG) {
+			++hung;
+			/* Mark the queue as inactive */
+			vsi->active_queues &= ~((u64)1 << que->me);
+			continue;
+		} else {
+			/* Check if we've come back from hung */
+			if ((vsi->active_queues & ((u64)1 << que->me)) == 0)
+				vsi->active_queues |= ((u64)1 << que->me);
+		}
 		if (que->busy >= I40E_MAX_TX_BUSY) {
 			device_printf(dev,"Warning queue %d "
-			    "appears to be hung!", i);
+			    "appears to be hung!\n", i);
+			que->busy = I40E_QUEUE_HUNG;
 			++hung;
 		}
 	}
@@ -1809,6 +1903,27 @@ i40e_init_msix(struct i40e_pf *pf)
 	if (i40e_enable_msix == 0)
 		goto msi;
 
+	/*
+	** When used in a virtualized environment 
+	** PCI BUSMASTER capability may not be set
+	** so explicity set it here and rewrite
+	** the ENABLE in the MSIX control register
+	** at this point to cause the host to
+	** successfully initialize us.
+	*/
+	{
+		u16 pci_cmd_word;
+		int msix_ctrl;
+		pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
+		pci_cmd_word |= PCIM_CMD_BUSMASTEREN;
+		pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2);
+		pci_find_cap(dev, PCIY_MSIX, &rid);
+		rid += PCIR_MSIX_CTRL;
+		msix_ctrl = pci_read_config(dev, rid, 2);
+		msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
+		pci_write_config(dev, rid, msix_ctrl, 2);
+	}
+
 	/* First try MSI/X */
 	rid = PCIR_BAR(I40E_BAR);
 	pf->msix_mem = bus_alloc_resource_any(dev,
@@ -1850,7 +1965,6 @@ i40e_init_msix(struct i40e_pf *pf)
 		return (0); /* Will go to Legacy setup */
 	}
 
-	// NOTE this is all simplified based on ONE VSI
 	if (pci_alloc_msix(dev, &vectors) == 0) {
                	device_printf(pf->dev,
 		    "Using MSIX interrupts with %d vectors\n", vectors);
@@ -2194,7 +2308,7 @@ i40e_setup_interface(device_t dev, struct i40e_vsi *vsi)
 		return (EPERM);
 	}
 
-	/* Display PHY's supported media types */
+	/* Display supported media types */
 	if (abilities_resp.phy_type & (1 << I40E_PHY_TYPE_100BASE_TX))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_100_TX, 0, NULL);
 
@@ -2355,7 +2469,11 @@ i40e_initialize_vsi(struct i40e_vsi *vsi)
 		tctx.base = (txr->dma.pa/128);
 		tctx.qlen = que->num_desc;
 		tctx.fc_ena = 0;
-		tctx.rdylist = vsi->info.qs_handle[0];
+		tctx.rdylist = vsi->info.qs_handle[0]; /* index is TC */
+		/* Enable HEAD writeback */
+		tctx.head_wb_ena = 1;
+		tctx.head_wb_addr = txr->dma.pa +
+		    (que->num_desc * sizeof(struct i40e_tx_desc));
 		tctx.rdylist_act = 0;
 		err = i40e_clear_lan_tx_queue_context(hw, i);
 		if (err) {
@@ -2401,11 +2519,7 @@ i40e_initialize_vsi(struct i40e_vsi *vsi)
 		rctx.tphwdesc_ena = 1;
 		rctx.tphdata_ena = 0;
 		rctx.tphhead_ena = 0;
-#ifdef FORTVILLE_A0_SUPPORT
-		rctx.lrxqthresh = 0;
-#else
 		rctx.lrxqthresh = 2;
-#endif
 		rctx.crcstrip = 1;
 		rctx.l2tsel = 1;
 		rctx.showiv = 1;
@@ -2520,16 +2634,20 @@ i40e_setup_stations(struct i40e_pf *pf)
 		que->num_desc = i40e_ringsz;
 		que->me = i;
 		que->vsi = vsi;
+		/* mark the queue as active */
+		vsi->active_queues |= (u64)1 << que->me;
 		txr = &que->txr;
 		txr->que = que;
+		txr->tail = I40E_QTX_TAIL(que->me);
 
 		/* Initialize the TX lock */
 		snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)",
 		    device_get_nameunit(dev), que->me);
 		mtx_init(&txr->mtx, txr->mtx_name, NULL, MTX_DEF);
 		/* Create the TX descriptor ring */
-		tsize = roundup2(que->num_desc *
-		    sizeof(struct i40e_tx_desc), DBA_ALIGN);
+		tsize = roundup2((que->num_desc *
+		    sizeof(struct i40e_tx_desc)) +
+		    sizeof(u32), DBA_ALIGN);
 		if (i40e_allocate_dma(&pf->hw,
 		    &txr->dma, tsize, DBA_ALIGN)) {
 			device_printf(dev,
@@ -2563,6 +2681,7 @@ i40e_setup_stations(struct i40e_pf *pf)
 		    sizeof(union i40e_rx_desc), DBA_ALIGN);
 		rxr = &que->rxr;
 		rxr->que = que;
+		rxr->tail = I40E_QRX_TAIL(que->me);
 
 		/* Initialize the RX side lock */
 		snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)",
@@ -2698,7 +2817,7 @@ i40e_set_queue_tx_itr(struct i40e_queue *que)
 	if (txr->bytes == 0)
 		return;
 
-	if (i40e_dynamic_rx_itr) {
+	if (i40e_dynamic_tx_itr) {
 		tx_bytes = txr->bytes/txr->itr;
 		tx_itr = txr->itr;
 
@@ -2757,6 +2876,10 @@ static void
 i40e_add_hw_stats(struct i40e_pf *pf)
 {
 	device_t dev = pf->dev;
+	struct i40e_vsi *vsi = &pf->vsi;
+	struct i40e_queue *queues = vsi->queues;
+	struct i40e_eth_stats *vsi_stats = &vsi->eth_stats;
+	struct i40e_hw_port_stats *pf_stats = &pf->stats;
 
 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 	struct sysctl_oid *tree = device_get_sysctl_tree(dev);
@@ -2765,9 +2888,8 @@ i40e_add_hw_stats(struct i40e_pf *pf)
 	struct sysctl_oid *vsi_node, *queue_node;
 	struct sysctl_oid_list *vsi_list, *queue_list;
 
-	struct i40e_vsi *vsi = &pf->vsi;
-	struct i40e_eth_stats *vsi_stats = &vsi->eth_stats;
-	struct i40e_hw_port_stats *pf_stats = &pf->stats;
+	struct tx_ring *txr;
+	struct rx_ring *rxr;
 
 	/* Driver statistics */
 	SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events",
@@ -2779,51 +2901,39 @@ i40e_add_hw_stats(struct i40e_pf *pf)
 
 	/* VSI statistics */
 #define QUEUE_NAME_LEN 32
-	char vsi_namebuf[QUEUE_NAME_LEN];
 	char queue_namebuf[QUEUE_NAME_LEN];
 	
-	snprintf(vsi_namebuf, QUEUE_NAME_LEN, "vsi%d", vsi->info.stat_counter_idx);
-	vsi_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, vsi_namebuf,
-				   CTLFLAG_RD, NULL, "VSI Number");
+	// ERJ: Only one vsi now, re-do when >1 VSI enabled
+	// snprintf(vsi_namebuf, QUEUE_NAME_LEN, "vsi%d", vsi->info.stat_counter_idx);
+	vsi_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "vsi",
+				   CTLFLAG_RD, NULL, "VSI-specific stats");
 	vsi_list = SYSCTL_CHILDREN(vsi_node);
 
 	i40e_add_sysctls_eth_stats(ctx, vsi_list, vsi_stats);
 
 	/* Queue statistics */
-	struct i40e_queue *queues = vsi->queues;
-	struct tx_ring *txr;
-	struct rx_ring *rxr;
 	for (int q = 0; q < vsi->num_queues; q++) {
-		snprintf(queue_namebuf, QUEUE_NAME_LEN, "queue%d", q);
+		snprintf(queue_namebuf, QUEUE_NAME_LEN, "que%d", q);
 		queue_node = SYSCTL_ADD_NODE(ctx, vsi_list, OID_AUTO, queue_namebuf,
-					     CTLFLAG_RD, NULL, "Queue Name");
+					     CTLFLAG_RD, NULL, "Queue #");
 		queue_list = SYSCTL_CHILDREN(queue_node);
 
-		SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "mbuf_defrag_failed",
+		txr = &(queues[q].txr);
+		rxr = &(queues[q].rxr);
+
+		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "mbuf_defrag_failed",
 				CTLFLAG_RD, &(queues[q].mbuf_defrag_failed),
 				"m_defrag() failed");
-		SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "dropped",
+		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "dropped",
 				CTLFLAG_RD, &(queues[q].dropped_pkts),
 				"Driver dropped packets");
-
-		txr = &(queues[q].txr);
-		/* ERJ - Need:
-		 * i40e_sysctl_interrupt_rate_handler
-		 * i40e_sysctl_tdh_handler
-		 * i40e_sysctl_tdt_handler
-		 *
-		 * i40e_sysctl_rdh_handler
-		 * i40e_sysctl_rdt_handler
-		 * rx_copies
-		 * LRO stats
-		 */
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs",
 				CTLFLAG_RD, &(queues[q].irqs),
 				"irqs on this queue");
-		SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tso_tx",
+		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx",
 				CTLFLAG_RD, &(queues[q].tso),
 				"TSO");
-		SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_dma_setup",
+		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_dma_setup",
 				CTLFLAG_RD, &(queues[q].tx_dma_setup),
 				"Driver tx dma failure in xmit");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "no_desc_avail",
@@ -2835,8 +2945,6 @@ i40e_add_hw_stats(struct i40e_pf *pf)
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_bytes",
 				CTLFLAG_RD, &(txr->bytes),
 				"Queue Bytes Transmitted");
-		
-		rxr = &(queues[q].rxr);
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets",
 				CTLFLAG_RD, &(rxr->rx_packets),
 				"Queue Packets Received");
@@ -2863,16 +2971,14 @@ i40e_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx,
 			"Multicast Packets Received"},
 		{&eth_stats->rx_broadcast, "bcast_pkts_rcvd",
 			"Broadcast Packets Received"},
-		// Add description
-		{&eth_stats->rx_discards, "rx_discards", "?"},
+		{&eth_stats->rx_discards, "rx_discards", "Discarded RX packets"},
 		{&eth_stats->tx_bytes, "good_octets_txd", "Good Octets Transmitted"},
 		{&eth_stats->tx_unicast, "ucast_pkts_txd", "Unicast Packets Transmitted"},
 		{&eth_stats->tx_multicast, "mcast_pkts_txd",
 			"Multicast Packets Transmitted"},
 		{&eth_stats->tx_broadcast, "bcast_pkts_txd",
 			"Broadcast Packets Transmitted"},
-		// Add description
-		{&eth_stats->tx_discards, "tx_discards", "?"},
+		{&eth_stats->tx_discards, "tx_discards", "Discarded TX packets"},
 		// end
 		{0,0,0}
 	};
@@ -2892,7 +2998,7 @@ i40e_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx,
 	struct sysctl_oid_list *child,
 	struct i40e_hw_port_stats *stats)
 {
-	struct sysctl_oid *stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
+	struct sysctl_oid *stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac",
 				    CTLFLAG_RD, NULL, "Mac Statistics");
 	struct sysctl_oid_list *stat_list = SYSCTL_CHILDREN(stat_node);
 
@@ -3095,11 +3201,9 @@ i40e_setup_vlan_filters(struct i40e_vsi *vsi)
 static void
 i40e_init_filters(struct i40e_vsi *vsi)
 {
-	/* Protocol addresses */
-	/* - Flow control multicast */
-	u8 mc[6] = {0x01, 0x80, 0xC2, 0x00, 0x00, 0x01};
-	i40e_add_filter(vsi, mc, I40E_VLAN_ANY);
-	/* TODO: other protocols */
+	/* Add broadcast address */
+	u8 bc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	i40e_add_filter(vsi, bc, I40E_VLAN_ANY);
 }
 
 /*
@@ -3332,7 +3436,6 @@ i40e_enable_rings(struct i40e_vsi *vsi)
 	u32		reg;
 
 	for (int i = 0; i < vsi->num_queues; i++) {
-		// ERJ: pre_tx_queue_cfg is B0-only?
 		i40e_pre_tx_queue_cfg(hw, i, TRUE);
 
 		reg = rd32(hw, I40E_QTX_ENA(i));
@@ -3372,10 +3475,7 @@ i40e_disable_rings(struct i40e_vsi *vsi)
 	u32		reg;
 
 	for (int i = 0; i < vsi->num_queues; i++) {
-		// ERJ
-		// this step can be executed concurrently for each queue
 		i40e_pre_tx_queue_cfg(hw, i, FALSE);
-		// min 100usec for 2x10, 400usec for 1x10
 		i40e_usec_delay(500);
 
 		reg = rd32(hw, I40E_QTX_ENA(i));
@@ -3406,6 +3506,78 @@ i40e_disable_rings(struct i40e_vsi *vsi)
 	}
 }
 
+/**
+ * i40e_handle_mdd_event
+ *
+ * Called from interrupt handler to identify possibly malicious vfs
+ * (But also detects events from the PF, as well)
+ **/
+static void i40e_handle_mdd_event(struct i40e_pf *pf)
+{
+	struct i40e_hw *hw = &pf->hw;
+	device_t dev = pf->dev;
+	bool mdd_detected = false;
+	bool pf_mdd_detected = false;
+	u32 reg;
+
+	/* find what triggered the MDD event */
+	reg = rd32(hw, I40E_GL_MDET_TX);
+	if (reg & I40E_GL_MDET_TX_VALID_MASK) {
+		u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
+				I40E_GL_MDET_TX_PF_NUM_SHIFT;
+		u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
+				I40E_GL_MDET_TX_EVENT_SHIFT;
+		u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
+				I40E_GL_MDET_TX_QUEUE_SHIFT;
+		device_printf(dev,
+			 "Malicious Driver Detection event 0x%02x"
+			 " on TX queue %d pf number 0x%02x\n",
+			 event, queue, pf_num);
+		wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
+		mdd_detected = true;
+	}
+	reg = rd32(hw, I40E_GL_MDET_RX);
+	if (reg & I40E_GL_MDET_RX_VALID_MASK) {
+		u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
+				I40E_GL_MDET_RX_FUNCTION_SHIFT;
+		u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
+				I40E_GL_MDET_RX_EVENT_SHIFT;
+		u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
+				I40E_GL_MDET_RX_QUEUE_SHIFT;
+		device_printf(dev,
+			 "Malicious Driver Detection event 0x%02x"
+			 " on RX queue %d of function 0x%02x\n",
+			 event, queue, func);
+		wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
+		mdd_detected = true;
+	}
+
+	if (mdd_detected) {
+		reg = rd32(hw, I40E_PF_MDET_TX);
+		if (reg & I40E_PF_MDET_TX_VALID_MASK) {
+			wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
+			device_printf(dev,
+				 "MDD TX event is for this function 0x%08x",
+				 reg);
+			pf_mdd_detected = true;
+		}
+		reg = rd32(hw, I40E_PF_MDET_RX);
+		if (reg & I40E_PF_MDET_RX_VALID_MASK) {
+			wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
+			device_printf(dev,
+				 "MDD RX event is for this function 0x%08x",
+				 reg);
+			pf_mdd_detected = true;
+		}
+	}
+
+	/* re-enable mdd interrupt cause */
+	reg = rd32(hw, I40E_PFINT_ICR0_ENA);
+	reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
+	wr32(hw, I40E_PFINT_ICR0_ENA, reg);
+	i40e_flush(hw);
+}
+
 static void
 i40e_enable_intr(struct i40e_vsi *vsi)
 {
@@ -3505,6 +3677,9 @@ static void
 i40e_update_stats_counters(struct i40e_pf *pf)
 {
 	struct i40e_hw	*hw = &pf->hw;
+	struct i40e_vsi *vsi = &pf->vsi;
+	struct ifnet	*ifp = vsi->ifp;
+
 	struct i40e_hw_port_stats *nsd = &pf->stats;
 	struct i40e_hw_port_stats *osd = &pf->stats_offsets;
 
@@ -3579,7 +3754,7 @@ i40e_update_stats_counters(struct i40e_pf *pf)
 			   &osd->rx_length_errors,
 			   &nsd->rx_length_errors);
 
-	/* Update flow control stats */
+	/* Flow control (LFC) stats */
 	i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->link_xon_rx, &nsd->link_xon_rx);
@@ -3593,10 +3768,7 @@ i40e_update_stats_counters(struct i40e_pf *pf)
 			   pf->stat_offsets_loaded,
 			   &osd->link_xoff_tx, &nsd->link_xoff_tx);
 
-	/* 
-	 * Uncomment these out when priority flow control
-	 * is implemented.
-	 */
+	/* Priority flow control stats */
 #if 0
 	for (int i = 0; i < 8; i++) {
 		i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
@@ -3619,6 +3791,7 @@ i40e_update_stats_counters(struct i40e_pf *pf)
 	}
 #endif
 
+	/* Packet size stats rx */
 	i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
 			   I40E_GLPRT_PRC64L(hw->port),
 			   pf->stat_offsets_loaded,
@@ -3648,6 +3821,7 @@ i40e_update_stats_counters(struct i40e_pf *pf)
 			   pf->stat_offsets_loaded,
 			   &osd->rx_size_big, &nsd->rx_size_big);
 
+	/* Packet size stats tx */
 	i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
 			   I40E_GLPRT_PTC64L(hw->port),
 			   pf->stat_offsets_loaded,
@@ -3690,45 +3864,13 @@ i40e_update_stats_counters(struct i40e_pf *pf)
 			   pf->stat_offsets_loaded,
 			   &osd->rx_jabber, &nsd->rx_jabber);
 	pf->stat_offsets_loaded = true;
-	/* End pf-only stats */
+	/* End hw stats */
 
 	/* Update vsi stats */
-	struct i40e_vsi *vsi = &pf->vsi;
 	i40e_update_eth_stats(vsi);
 
-	/* ERJ - does something need these statistics?
-	u64 rx_p = 0, rx_b = 0, tx_p = 0, tx_b = 0;
-	u64 tx_no_desc;
-	u64 rx_split, rx_discarded, rx_not_done;
-	for (u16 q = 0; q < vsi->num_queues; q++)
-	{
-		struct i40e_queue *p = &vsi->queues[q];	
-	
-		rx_p += p->rxr.packets;
-		tx_p += p->txr.packets;
-		rx_b += p->rxr.bytes;
-		tx_b += p->txr.bytes;
-	
-		tx_no_desc += p->txr.no_desc;
-		rx_split += p->rxr.split;
-		rx_discarded += p->rxr.discarded;
-		rx_not_done += p->rxr.not_done;
-	}
-	*/
-
 	/* OS statistics */
-	struct ifnet	*ifp = vsi->ifp;
-
-	// ifp->if_ipackets = rx_p; // no gprc
-	// ifp->if_opackets = tx_p; // no gptc
-	ifp->if_ibytes = nsd->eth.rx_bytes;
-	ifp->if_obytes = nsd->eth.tx_bytes;
-	ifp->if_imcasts = nsd->eth.rx_multicast;
-	ifp->if_omcasts = nsd->eth.tx_multicast;
-	ifp->if_collisions = 0;
-
-	/* Rx Errors */
-	// Linux uses illegal_bytes instead of rx_length_errors
+	// ERJ - these are per-port, update all vsis?
 	ifp->if_ierrors = nsd->crc_errors + nsd->illegal_bytes;
 }
 
@@ -3781,7 +3923,7 @@ i40e_do_adminq(void *context, int pending)
 	} while (result && (loop++ < I40E_ADM_LIMIT));
 
 	reg = rd32(hw, I40E_PFINT_ICR0_ENA);
-	reg |=  I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
+	reg |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
 	wr32(hw, I40E_PFINT_ICR0_ENA, reg);
 	free(event.msg_buf, M_DEVBUF);
 
@@ -3861,8 +4003,9 @@ i40e_print_debug_info(struct i40e_pf *pf)
  **/
 void i40e_update_eth_stats(struct i40e_vsi *vsi)
 {
-	struct i40e_pf	*pf = (struct i40e_pf *)vsi->back;
+	struct i40e_pf *pf = (struct i40e_pf *)vsi->back;
 	struct i40e_hw *hw = &pf->hw;
+	struct ifnet *ifp = vsi->ifp;
 	struct i40e_eth_stats *es;
 	struct i40e_eth_stats *oes;
 	u16 stat_idx = vsi->info.stat_counter_idx;
@@ -3912,6 +4055,23 @@ void i40e_update_eth_stats(struct i40e_vsi *vsi)
 			   vsi->stat_offsets_loaded,
 			   &oes->tx_broadcast, &es->tx_broadcast);
 	vsi->stat_offsets_loaded = true;
+
+	/* Update ifnet stats */
+	ifp->if_ipackets = es->rx_unicast +
+	                   es->rx_multicast +
+			   es->rx_broadcast;
+	ifp->if_opackets = es->tx_unicast +
+	                   es->tx_multicast +
+			   es->tx_broadcast;
+	ifp->if_ibytes = es->rx_bytes;
+	ifp->if_obytes = es->tx_bytes;
+	ifp->if_imcasts = es->rx_multicast;
+	ifp->if_omcasts = es->tx_multicast;
+
+	ifp->if_oerrors = es->tx_errors;
+	ifp->if_iqdrops = es->rx_discards;
+	ifp->if_noproto = es->rx_unknown_protocol;
+	ifp->if_collisions = 0;
 }
 
 /**
@@ -3952,7 +4112,7 @@ i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
 	new_data = rd64(hw, loreg);
 #else
 	/*
-	 * Use two rd32's instead of one rd64 because FreeBSD versions before
+	 * Use two rd32's instead of one rd64; FreeBSD versions before
 	 * 10 don't support 8 byte bus reads/writes.
 	 */
 	new_data = rd32(hw, loreg);
@@ -3988,7 +4148,6 @@ i40e_stat_update32(struct i40e_hw *hw, u32 reg,
 
 /*
 ** Set flow control using sysctl:
-** Flow control values:
 ** 	0 - off
 **	1 - rx pause
 **	2 - tx pause
@@ -4007,113 +4166,156 @@ i40e_set_flowcntl(SYSCTL_HANDLER_ARGS)
 	struct i40e_pf *pf = (struct i40e_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
-	struct i40e_aq_get_phy_abilities_resp abilities;
 	int requested_fc = 0, error = 0;
 	enum i40e_status_code aq_error = 0;
 	u8 fc_aq_err = 0;
 
-	/* Get current capability information */
-	aq_error = i40e_aq_get_phy_capabilities(hw, FALSE, FALSE, &abilities, NULL);
-	if (aq_error)
-		device_printf(dev, "Error getting phy capabilities %d,"
-		    " aq error: %d\n", aq_error, hw->aq.asq_last_status);
-
-	if ((abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX) &&
-	    (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX))
-		hw->fc.current_mode = I40E_FC_FULL;
-	else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_TX)
-		hw->fc.current_mode = I40E_FC_TX_PAUSE;
-	else if (abilities.abilities & I40E_AQ_PHY_FLAG_PAUSE_RX)
-		hw->fc.current_mode = I40E_FC_RX_PAUSE;
-	else
-		hw->fc.current_mode = I40E_FC_NONE;
+	aq_error = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
+	if (aq_error) {
+		device_printf(dev,
+		    "%s: Error retrieving link info from aq, %d\n",
+		    __func__, aq_error);
+		return (EAGAIN);
+	}
 
 	/* Read in new mode */
 	requested_fc = hw->fc.current_mode;
 	error = sysctl_handle_int(oidp, &requested_fc, 0, req);
 	if ((error) || (req->newptr == NULL))
-		goto no_set;
+		return (error);
 	if (requested_fc < 0 || requested_fc > 3) {
 		device_printf(dev,
 		    "Invalid fc mode; valid modes are 0 through 3\n");
 		return (EINVAL);
 	}
 
+	/*
+	** Changing flow control mode currently does not work on
+	** 40GBASE-CR4 PHYs
+	*/
+	if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4
+	    || hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4_CU) {
+		device_printf(dev, "Changing flow control mode unsupported"
+		    " on 40GBase-CR4 media.\n");
+		return (ENODEV);
+	}
+
 	/* Set fc ability for port */
 	hw->fc.requested_mode = requested_fc;
-	i40e_set_fc(hw, &fc_aq_err, TRUE);
+	aq_error = i40e_set_fc(hw, &fc_aq_err, TRUE);
+	if (aq_error) {
+		device_printf(dev,
+		    "%s: Error setting new fc mode %d; fc_err %#x\n",
+		    __func__, aq_error, fc_aq_err);
+		return (EAGAIN);
+	}
 
-	// DEBUG: Verify flow control setting was successfully set
 	if (hw->fc.current_mode != hw->fc.requested_mode) {
-		device_printf(dev, "FC set failure:\n");
-		device_printf(dev, "Current: %s / Requested: %s\n",
+		device_printf(dev, "%s: FC set failure:\n", __func__);
+		device_printf(dev, "%s: Current: %s / Requested: %s\n",
+		    __func__,
 		    i40e_fc_string[hw->fc.current_mode],
 		    i40e_fc_string[hw->fc.requested_mode]);
 	}
 
-no_set:;
-#ifdef I40E_DEBUG
-	/* Print FC registers */
-	u32 reg = 0;
-	printf("Current FC mode: %s\n", i40e_fc_string[hw->fc.current_mode]);
-	if (i40e_is_40G_device(hw->device_id)) {
-		// XXX: Why are these names so long?
-		reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP);
-		printf("PRTMAC_HSEC_CTL_RX_ENABLE_GPP (LFC)         : %s\n",
-		    ON_OFF_STR(reg & I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK));
-
-		reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP);
-		printf("PRTMAC_HSEC_CTL_RX_ENABLE_PPP (PFC)         : %s\n",
-		    ON_OFF_STR(reg & I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK));
-
-		reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE);
-		printf("PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE (LFC)       : %s\n",
-		    ON_OFF_STR(reg & I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK));
-
-		reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE);
-		printf("PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE (LFC)       : %s\n",
-		    ON_OFF_STR(reg & I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK));
-
-		reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8));
-		printf("PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER (LFC): %#010x\n", reg);
-
-		reg = rd32(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8));
-		printf("PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA (LFC)       : %#010x\n",
-		    reg & I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK);
-	} else {
-		reg = rd32(hw, I40E_PRTDCB_MFLCN);
-		printf("PRTDCB_MFLCN                     :\n");
-		printf("- PMCF  (Pass MAC Control Frames): %s\n",
-		    ON_OFF_STR(reg & I40E_PRTDCB_MFLCN_PMCF_MASK));
-		printf("- DPF   (Discard Pause Frames)   : %s\n",
-		    ON_OFF_STR(reg & I40E_PRTDCB_MFLCN_DPF_MASK));
-		printf("- RPFCM (Rx PFC Mode)            : %s\n",
-		    ON_OFF_STR(reg & I40E_PRTDCB_MFLCN_RPFCM_MASK));
-		printf("- RFCE  (Rx LFC Mode)            : %s\n",
-		    ON_OFF_STR(reg & I40E_PRTDCB_MFLCN_RFCE_MASK));
-		printf("- RPFCE (Rx PFC Enable Bitmap)   : %#04x\n",
-		    reg & I40E_PRTDCB_MFLCN_RPFCE_MASK);
-		reg = rd32(hw, I40E_PRTDCB_FCCFG);
-		printf("PRTDCB_FCCFG                     :\n");
-		u8 tfce = reg & I40E_PRTDCB_FCCFG_TFCE_MASK;
-		printf("- TFCE  (Tx FC Enable)           : %s\n",
-		    (tfce == 3) ? "Reserved" :
-		    (tfce == 2) ? "PFC Enabled" :
-		    (tfce == 1) ? "LFC Enabled" :
-				  "Tx FC Disabled");
-		reg = rd32(hw, I40E_PRTDCB_FCTTVN(0));
-		printf("PRTDCB_FCCTTVN (LFC)             : %#06x\n",
-		    reg & I40E_PRTDCB_FCTTVN_TTV_2N_MASK);
-		reg = rd32(hw, I40E_PRTDCB_FCRTV);
-		printf("PRTDCB_FCRTV (Pause ref thresh)  : %#06x\n",
-		    reg & I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK);
-		reg = rd32(hw, I40E_PRTDCB_TC2PFC);
-		printf("PRTDCB_TC2PFC is 0xff            : %s\n",
-		    ((reg & I40E_PRTDCB_TC2PFC_TC2PFC_MASK) == 0xFF)
-		    ? "Yes" : "No");
+	return (0);
+}
+
+/*
+** Control link advertise speed:
+**	1 - advertise 1G only
+**	2 - advertise 10G only
+**	3 - advertise 1 and 10G
+**
+** Does not work on 40G devices.
+*/
+static int
+i40e_set_advertise(SYSCTL_HANDLER_ARGS)
+{
+	struct i40e_pf *pf = (struct i40e_pf *)arg1;
+	struct i40e_hw *hw = &pf->hw;
+	device_t dev = pf->dev;
+	struct i40e_aq_get_phy_abilities_resp abilities;
+	struct i40e_aq_set_phy_config config;
+	int current_ls = 0, requested_ls = 0;
+	enum i40e_status_code aq_error = 0;
+	int error = 0;
+
+	/*
+	** FW doesn't support changing advertised speed
+	** for 40G devices; speed is always 40G.
+	*/
+	if (i40e_is_40G_device(hw->device_id))
+		return (ENODEV);
+
+	/* Get current capability information */
+	aq_error = i40e_aq_get_phy_capabilities(hw, FALSE, FALSE, &abilities, NULL);
+	if (aq_error) {
+		device_printf(dev, "%s: Error getting phy capabilities %d,"
+		    " aq error: %d\n", __func__, aq_error,
+		    hw->aq.asq_last_status);
+		return (EAGAIN);
 	}
-#endif
-	return (error);
+
+	/* Figure out current mode */
+	else if (abilities.link_speed & I40E_LINK_SPEED_10GB
+	    && abilities.link_speed & I40E_LINK_SPEED_1GB)
+		current_ls = 3;
+	else if (abilities.link_speed & I40E_LINK_SPEED_10GB)
+		current_ls = 2;
+	else if (abilities.link_speed & I40E_LINK_SPEED_1GB)
+		current_ls = 1;
+	else
+		current_ls = 0;
+
+	/* Read in new mode */
+	requested_ls = current_ls;
+	error = sysctl_handle_int(oidp, &requested_ls, 0, req);
+	if ((error) || (req->newptr == NULL))
+		return (error);
+	if (requested_ls < 1 || requested_ls > 3) {
+		device_printf(dev,
+		    "Invalid advertised speed; valid modes are 1 through 3\n");
+		return (EINVAL);
+	}
+
+	/* Exit if no change */
+	if (current_ls == requested_ls)
+		return (0);
+
+	/* Prepare new config */
+	bzero(&config, sizeof(config));
+	config.phy_type = abilities.phy_type;
+	config.abilities = abilities.abilities
+	    | I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
+	config.eee_capability = abilities.eee_capability;
+	config.eeer = abilities.eeer_val;
+	config.low_power_ctrl = abilities.d3_lpan;
+	/* Translate into aq cmd link_speed */
+	switch (requested_ls) {
+	case 3:
+		config.link_speed = I40E_LINK_SPEED_10GB
+		    | I40E_LINK_SPEED_1GB;
+	case 2:
+		config.link_speed = I40E_LINK_SPEED_10GB;
+	case 1:
+		config.link_speed = I40E_LINK_SPEED_1GB;
+	default:
+		// nothing should get here
+		break;
+	}
+
+	/* Do aq command & restart link */
+	aq_error = i40e_aq_set_phy_config(hw, &config, NULL);
+	if (aq_error) {
+		device_printf(dev, "%s: Error setting new phy config %d,"
+		    " aq error: %d\n", __func__, aq_error,
+		    hw->aq.asq_last_status);
+		return (EAGAIN);
+	}
+
+	i40e_update_link_status(pf);
+	return (0);
 }
 
 /*
@@ -4294,5 +4496,129 @@ i40e_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS)
 	free(buf, M_DEVBUF);
 	return error;
 }
+
+#define I40E_SW_RES_SIZE 0x14
+static int
+i40e_sysctl_hw_res_info(SYSCTL_HANDLER_ARGS)
+{
+	struct i40e_pf *pf = (struct i40e_pf *)arg1;
+	struct i40e_hw *hw = &pf->hw;
+	device_t dev = pf->dev;
+	struct sbuf *buf;
+	int error = 0;
+
+	u8 num_entries;
+	struct i40e_aqc_switch_resource_alloc_element_resp resp[I40E_SW_RES_SIZE];
+
+	buf = sbuf_new_for_sysctl(NULL, NULL, 0, req);
+	if (!buf) {
+		device_printf(dev, "Could not allocate sbuf for output.\n");
+		return (ENOMEM);
+	}
+
+	error = i40e_aq_get_switch_resource_alloc(hw, &num_entries,
+				resp,
+				I40E_SW_RES_SIZE,
+				NULL);
+	if (error) {
+		device_printf(dev, "%s: get_switch_resource_alloc() error %d, aq error %d\n",
+		    __func__, error, hw->aq.asq_last_status);
+		sbuf_delete(buf);
+		return error;
+	}
+	device_printf(dev, "Num_entries: %d\n", num_entries);
+
+	sbuf_cat(buf, "\n");
+	sbuf_printf(buf,
+	    "Type | Guaranteed | Total | Used   | Un-allocated\n"
+	    "     | (this)     | (all) | (this) | (all)       \n");
+	for (int i = 0; i < num_entries; i++) {
+		sbuf_printf(buf,
+		    "%#4x | %10d   %5d   %6d   %12d",
+		    resp[i].resource_type,
+		    resp[i].guaranteed,
+		    resp[i].total,
+		    resp[i].used,
+		    resp[i].total_unalloced);
+		if (i < num_entries - 1)
+			sbuf_cat(buf, "\n");
+	}
+
+	error = sbuf_finish(buf);
+	if (error) {
+		device_printf(dev, "Error finishing sbuf: %d\n", error);
+		sbuf_delete(buf);
+		return error;
+	}
+
+	error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req);
+	if (error)
+		device_printf(dev, "sysctl error: %d\n", error);
+	sbuf_delete(buf);
+	return error;
+
+}
+
+/*
+** Dump TX desc given index.
+** Doesn't work; don't use.
+** TODO: Also needs a queue index input!
+**/
+static int
+i40e_sysctl_dump_txd(SYSCTL_HANDLER_ARGS)
+{
+	struct i40e_pf *pf = (struct i40e_pf *)arg1;
+	device_t dev = pf->dev;
+	struct sbuf *buf;
+	int error = 0;
+
+	u16 desc_idx = 0;
+
+	buf = sbuf_new_for_sysctl(NULL, NULL, 0, req);
+	if (!buf) {
+		device_printf(dev, "Could not allocate sbuf for output.\n");
+		return (ENOMEM);
+	}
+
+	/* Read in index */
+	error = sysctl_handle_int(oidp, &desc_idx, 0, req);
+	if (error)
+		return (error);
+	if (req->newptr == NULL)
+		return (EIO); // fix
+	if (desc_idx > 1024) { // fix
+		device_printf(dev,
+		    "Invalid descriptor index, needs to be < 1024\n"); // fix
+		return (EINVAL);
+	}
+
+	// Don't use this sysctl yet
+	if (TRUE)
+		return (ENODEV);
+
+	sbuf_cat(buf, "\n");
+
+	// set to queue 1?
+	struct i40e_queue *que = pf->vsi.queues;
+	struct tx_ring *txr = &(que[1].txr);
+	struct i40e_tx_desc *txd = &txr->base[desc_idx];
+
+	sbuf_printf(buf, "Que: %d, Desc: %d\n", que->me, desc_idx);
+	sbuf_printf(buf, "Addr: %#18lx\n", txd->buffer_addr);
+	sbuf_printf(buf, "Opts: %#18lx\n", txd->cmd_type_offset_bsz);
+
+	error = sbuf_finish(buf);
+	if (error) {
+		device_printf(dev, "Error finishing sbuf: %d\n", error);
+		sbuf_delete(buf);
+		return error;
+	}
+
+	error = sysctl_handle_string(oidp, sbuf_data(buf), sbuf_len(buf), req);
+	if (error)
+		device_printf(dev, "sysctl error: %d\n", error);
+	sbuf_delete(buf);
+	return error;
+}
 #endif
 
diff --git a/sys/modules/i40e/Makefile b/sys/modules/i40e/Makefile
index 7d06a68..0cd6cf4 100755
--- a/sys/modules/i40e/Makefile
+++ b/sys/modules/i40e/Makefile
@@ -11,12 +11,10 @@ SRCS    += if_i40e.c i40e_txrx.c i40e_osdep.c
 # Shared source
 SRCS    += i40e_common.c i40e_nvm.c i40e_adminq.c i40e_lan_hmc.c i40e_hmc.c
 
-CFLAGS	+= -DSMP -DFORTVILLE_HW
+CFLAGS	+= -DSMP
 
 # Add Flow Director support
 # CFLAGS += -DI40E_FDIR
-# A0 hardware support
-# CFLAGS += -DFORTVILLE_A0_SUPPORT
 # Debug messages / sysctls
 # CFLAGS += -DI40E_DEBUG