diff options
| author | ian <ian@FreeBSD.org> | 2015-01-17 19:57:03 +0000 |
|---|---|---|
| committer | ian <ian@FreeBSD.org> | 2015-01-17 19:57:03 +0000 |
| commit | b011ed33bbed20028d149d6090fd65f096b5693f (patch) | |
| tree | 1881198f953b9ee508b3e61f65f78aa2df5f0575 | |
| parent | 730949356cff34f3c184fbbbe7beeadd32537c2e (diff) | |
| download | FreeBSD-src-b011ed33bbed20028d149d6090fd65f096b5693f.zip FreeBSD-src-b011ed33bbed20028d149d6090fd65f096b5693f.tar.gz | |
Add a new SDHCI quirk, SDHCI_QUIRK_DONT_SET_HISPD_BIT. Apparently some
sdhci controllers, such as the one on a Raspberry Pi, mishandle the signal
timing in high speed signaling mode, but run just fine in standard mode
with the bus running at frequencies between 25-50MHz (which shouldn't work).
This is the solution adopted by U-Boot and other OSes (linux and *BSD)
for the timeouts on Raspberry Pi boards with certain SD cards. Some
research shows that this quirk is also used on a few other boards, so the
fix is a generic quirk instead of being in the RPi-specific driver code.
This change is based on information discovered by Michal Meloun.
| -rw-r--r-- | sys/arm/broadcom/bcm2835/bcm2835_sdhci.c | 3 | ||||
| -rw-r--r-- | sys/dev/sdhci/sdhci.c | 3 | ||||
| -rw-r--r-- | sys/dev/sdhci/sdhci.h | 2 |
3 files changed, 6 insertions, 2 deletions
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c b/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c index 1fdece7..7e1ad19 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c @@ -91,7 +91,7 @@ __FBSDID("$FreeBSD$"); * HS mode still can be enabled with the tunable. */ static int bcm2835_sdhci_min_freq = 400000; -static int bcm2835_sdhci_hs = 0; +static int bcm2835_sdhci_hs = 1; static int bcm2835_sdhci_pio_mode = 0; TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); @@ -235,6 +235,7 @@ bcm_sdhci_attach(device_t dev) sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL + | SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_MISSING_CAPS; sdhci_init_slot(dev, &sc->sc_slot, 0); diff --git a/sys/dev/sdhci/sdhci.c b/sys/dev/sdhci/sdhci.c index 272a8f4..03bbeff 100644 --- a/sys/dev/sdhci/sdhci.c +++ b/sys/dev/sdhci/sdhci.c @@ -696,7 +696,8 @@ sdhci_generic_update_ios(device_t brdev, device_t reqdev) slot->hostctrl |= SDHCI_CTRL_4BITBUS; else slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; - if (ios->timing == bus_timing_hs) + if (ios->timing == bus_timing_hs && + !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) slot->hostctrl |= SDHCI_CTRL_HISPD; else slot->hostctrl &= ~SDHCI_CTRL_HISPD; diff --git a/sys/dev/sdhci/sdhci.h b/sys/dev/sdhci/sdhci.h index 80479b7..b7d1960 100644 --- a/sys/dev/sdhci/sdhci.h +++ b/sys/dev/sdhci/sdhci.h @@ -61,6 +61,8 @@ #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13) /* Wait to see reset bit asserted before waiting for de-asserted */ #define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1<<14) +/* Leave controller in standard mode when putting card in HS mode. */ +#define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1<<15) /* * Controller registers |
