Create a method of last resort for rebooting the mips processor: jump

to the reset vector.  This works for many SoCs where other reset
hardware is either missing or unknown.

2 files changed, 13 insertions, 0 deletions

diff --git a/sys/mips/include/md_var.h b/sys/mips/include/md_var.h
index a523851..dbfb451 100644
--- a/sys/mips/include/md_var.h
+++ b/sys/mips/include/md_var.h
@@ -52,6 +52,7 @@ uintptr_t MipsEmulateBranch(struct trapframe *, uintptr_t, int, uintptr_t);
 void MipsSwitchFPState(struct thread *, struct trapframe *);
 u_long	kvtop(void *addr);
 int	is_physical_memory(vm_offset_t addr);
+void	mips_generic_reset(void);
 
 #define	is_cacheable_mem(pa)	is_physical_memory((pa))
 
diff --git a/sys/mips/mips/machdep.c b/sys/mips/mips/machdep.c
index 80e3a47..d31ffce 100644
--- a/sys/mips/mips/machdep.c
+++ b/sys/mips/mips/machdep.c
@@ -84,6 +84,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/cache.h>
 #include <machine/clock.h>
 #include <machine/cpu.h>
+#include <machine/cpuregs.h>
 #include <machine/hwfunc.h>
 #include <machine/intr_machdep.h>
 #include <machine/md_var.h>
@@ -359,6 +360,17 @@ mips_vector_init(void)
 }
 
 /*
+ * Many SoCs have a means to reset the core itself.  Others do not, or
+ * the method is unknown to us.  For those cases, we jump to the mips
+ * reset vector and hope for the best.  This works well in practice.
+ */
+void
+mips_generic_reset()
+{
+	((void(*)(void))(intptr_t)MIPS_VEC_RESET)();
+}
+
+/*
  * Initialise a struct pcpu.
  */
 void