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author | dfr <dfr@FreeBSD.org> | 2002-04-10 19:27:50 +0000 |
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committer | dfr <dfr@FreeBSD.org> | 2002-04-10 19:27:50 +0000 |
commit | 97728cca9c85224afa78c840eb83fafcbf0a6e8e (patch) | |
tree | cf996b11b1e73d39b08c1f0f975889249c8a16bf | |
parent | c3e2d40f397d61f5575d155ad84f66737b4d7290 (diff) | |
download | FreeBSD-src-97728cca9c85224afa78c840eb83fafcbf0a6e8e.zip FreeBSD-src-97728cca9c85224afa78c840eb83fafcbf0a6e8e.tar.gz |
Save and restore the IA-32 state in cpu_switch(). Probably should only do
this if the thread has been executing IA-32 code.
-rw-r--r-- | sys/ia64/ia64/swtch.s | 48 |
1 files changed, 46 insertions, 2 deletions
diff --git a/sys/ia64/ia64/swtch.s b/sys/ia64/ia64/swtch.s index 33a37c7..18e9e64 100644 --- a/sys/ia64/ia64/swtch.s +++ b/sys/ia64/ia64/swtch.s @@ -168,7 +168,29 @@ ENTRY(cpu_switch, 0) st8 [r17]=r16,8 ;; // ar.rnat ld8 r3=[r3] st8 [r17]=r20,8 ;; // pr - st8 [r17]=r3 // current pmap + st8 [r17]=r3,8 // current pmap + + mov r18=ar.fsr + ;; + st8 [r17]=r18,8 // ar.fsr + mov r19=ar.fcr + ;; + st8 [r17]=r19,8 // ar.fcr + mov r18=ar.fir + ;; + st8 [r17]=r18,8 // ar.fir + mov r19=ar.fdr + ;; + st8 [r17]=r19,8 // ar.fdr + mov r18=ar.eflag + ;; + st8 [r17]=r18,8 // ar.eflag + mov r19=ar.csd + ;; + st8 [r17]=r19,8 // ar.csd + mov r18=ar.ssd + ;; + st8 [r17]=r18,8 // ar.ssd mov ar.rsc=3 // turn RSE back on @@ -266,7 +288,7 @@ ENTRY(cpu_switch, 0) ld8 r17=[r15],8 ;; // ar.pfs ld8 r18=[r15],16 ;; // ar.bspstore, skip ar.unat ld8 r19=[r15],8 ;; // ar.rnat - ld8 r20=[r15] ;; // pr + ld8 r20=[r15],16 ;; // pr, skip pmap loadrs // invalidate register stack ;; @@ -276,6 +298,28 @@ ENTRY(cpu_switch, 0) mov ar.rnat=r19 mov pr=r20,0x1ffff ;; + ld8 r16=[r15],8 // ar.fsr + ;; + ld8 r17=[r15],8 // ar.fcr + mov ar.fsr=r16 + ;; + ld8 r16=[r15],8 // ar.fir + mov ar.fcr=r17 + ;; + ld8 r17=[r15],8 // ar.fdr + mov ar.fir=r16 + ;; + ld8 r16=[r15],8 // ar.eflag + mov ar.fdr=r17 + ;; + ld8 r17=[r15],8 // ar.csd + mov ar.eflag=r16 + ;; + ld8 r16=[r15],8 // ar.ssd + mov ar.csd=r17 + ;; + mov ar.ssd=r16 + mov ar.rsc=3 // restart RSE invala ;; |