Introduce the FRAC_5G EEPROM parameter.

This seems to indicate whether to program the NIC for fractional 5ghz
mode (ie, 5mhz spaced channels, rather than 10 or 20mhz spacing) or not.
The default (0) seems to mean "only program fractional mode if needed".
A different value (eg 1) seems to always enable fractional 5ghz mode
regardless of the frequency.

Obtained from:	Atheros
Approved by:	re (kib)

4 files changed, 26 insertions, 6 deletions

diff --git a/sys/dev/ath/ath_hal/ah_eeprom.h b/sys/dev/ath/ath_hal/ah_eeprom.h
index 2ca0589..b77fb64 100644
--- a/sys/dev/ath/ath_hal/ah_eeprom.h
+++ b/sys/dev/ath/ath_hal/ah_eeprom.h
@@ -104,6 +104,7 @@ enum {
 	AR_EEP_PWDCLKIND,	/* uint8_t* */
 	AR_EEP_TEMPSENSE_SLOPE,	/* int8_t* */
 	AR_EEP_TEMPSENSE_SLOPE_PAL_ON,	/* int8_t* */
+	AR_EEP_FRAC_N_5G,	/* uint8_t* */
 };
 
 typedef struct {
diff --git a/sys/dev/ath/ath_hal/ah_eeprom_v14.c b/sys/dev/ath/ath_hal/ah_eeprom_v14.c
index fdddea1..37e973c 100644
--- a/sys/dev/ath/ath_hal/ah_eeprom_v14.c
+++ b/sys/dev/ath/ath_hal/ah_eeprom_v14.c
@@ -97,6 +97,12 @@ v14EepromGet(struct ath_hal *ah, int param, void *val)
 			return HAL_OK;
 		} else
 			return HAL_EIO;
+	case AR_EEP_FRAC_N_5G:
+		if (IS_VERS(>=, AR5416_EEP_MINOR_VER_22)) {
+			*(uint8_t *) val = pBase->frac_n_5g;
+		} else
+			*(uint8_t *) val = 0;
+		return HAL_OK;
 	case AR_EEP_AMODE:
 		HALASSERT(val == AH_NULL);
 		return pBase->opCapFlags & AR5416_OPFLAGS_11A ?
diff --git a/sys/dev/ath/ath_hal/ah_eeprom_v14.h b/sys/dev/ath/ath_hal/ah_eeprom_v14.h
index 6061b2f..7b2c898 100644
--- a/sys/dev/ath/ath_hal/ah_eeprom_v14.h
+++ b/sys/dev/ath/ath_hal/ah_eeprom_v14.h
@@ -187,7 +187,10 @@ typedef struct BaseEepHeader {
 	uint8_t		rcChainMask;	/* "1" if the card is an HB93 1x2 */
 	uint8_t		desiredScaleCCK;
 	uint8_t		pwr_table_offset;
-	uint8_t		frac_n_5g;
+	uint8_t		frac_n_5g;	/*
+					 * bit 0: indicates that fracN synth
+					 * mode applies to all 5G channels
+					 */
 	uint8_t		futureBase[21];
 } __packed BASE_EEP_HEADER; // 64 B
 
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9280.c b/sys/dev/ath/ath_hal/ar9002/ar9280.c
index f1bb4fe..99fd1d7 100644
--- a/sys/dev/ath/ath_hal/ar9002/ar9280.c
+++ b/sys/dev/ath/ath_hal/ar9002/ar9280.c
@@ -76,6 +76,7 @@ ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
 	uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
 	CHAN_CENTERS centers;
 	uint32_t refDivA = 24;
+	uint8_t frac_n_5g;
 
 	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);
 
@@ -85,6 +86,9 @@ ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
 	reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);
 	reg32 &= 0xc0000000;
 
+	if (ath_hal_eepromGet(ah, AR_EEP_FRAC_N_5G, &frac_n_5g) != HAL_OK)
+		frac_n_5g = 0;
+
 	if (freq < 4800) {     /* 2 GHz, fractional mode */
 		uint32_t txctl;
 
@@ -106,11 +110,16 @@ ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
 		bMode = 0;
 		fracMode = 0;
 
-		if ((freq % 20) == 0) {
-			aModeRefSel = 3;
-		} else if ((freq % 10) == 0) {
-			aModeRefSel = 2;
-		} else {
+		switch (frac_n_5g) {
+		case 0:
+			if ((freq % 20) == 0) {
+				aModeRefSel = 3;
+			} else if ((freq % 10) == 0) {
+				aModeRefSel = 2;
+			}
+			if (aModeRefSel) break;
+		case 1:
+		default:
 			aModeRefSel = 0;
 			/* Enable 2G (fractional) mode for channels which are 5MHz spaced */
 			fracMode = 1;
@@ -121,6 +130,7 @@ ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
 			OS_A_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
 			    AR_AN_SYNTH9_REFDIVA, refDivA);
 		}
+
 		if (!fracMode) {
 			ndiv = (freq * (refDivA >> aModeRefSel))/60;
 			channelSel =  ndiv & 0x1ff;