Add a GPIO output mux configuration method.

The AR934x and later (which will turn up eventually) have a new GPIO
output configuration option - a real MUX rather than a "GPIO or this
function."

For now I'm squirreling it away in the CPU code just so it's done -
I may move this to the GPIO layer later.

Specifically, this is required for setting up some boards that have
external receive side LNA (low noise amplifier) that gets switched on/off
by the on-chip wireless MAC.  If we don't add this support for those
boards then we'll end up with really poor performance.

(I don't yet have one of those APs, but it'll likely show up in a week.)

Obtained from:	Linux OpenWRT

2 files changed, 40 insertions, 0 deletions

diff --git a/sys/mips/atheros/ar71xx_cpudef.h b/sys/mips/atheros/ar71xx_cpudef.h
index 85618d4..d2db01a 100644
--- a/sys/mips/atheros/ar71xx_cpudef.h
+++ b/sys/mips/atheros/ar71xx_cpudef.h
@@ -65,6 +65,8 @@ struct ar71xx_cpu_def {
 	void (* ar71xx_chip_init_gmac) (void);
 
 	void (* ar71xx_chip_reset_nfc) (int);
+
+	void (* ar71xx_chip_gpio_out_configure) (int, uint8_t);
 };
 
 extern struct ar71xx_cpu_def * ar71xx_cpu_ops;
@@ -149,6 +151,12 @@ static inline void ar71xx_reset_nfc(int active)
 		ar71xx_cpu_ops->ar71xx_chip_reset_nfc(active);
 }
 
+static inline void ar71xx_gpio_ouput_configure(int gpio, uint8_t func)
+{
+	if (ar71xx_cpu_ops->ar71xx_chip_gpio_out_configure)
+		ar71xx_cpu_ops->ar71xx_chip_gpio_out_configure(gpio, func);
+}
+
 /* XXX shouldn't be here! */
 extern uint32_t u_ar71xx_refclk;
 extern uint32_t u_ar71xx_cpu_freq;
diff --git a/sys/mips/atheros/ar934x_chip.c b/sys/mips/atheros/ar934x_chip.c
index d66fd59..b76b1a0 100644
--- a/sys/mips/atheros/ar934x_chip.c
+++ b/sys/mips/atheros/ar934x_chip.c
@@ -417,6 +417,37 @@ ar934x_chip_reset_nfc(int active)
 	}
 }
 
+/*
+ * Configure the GPIO output mux setup.
+ *
+ * The AR934x introduced an output mux which allowed
+ * certain functions to be configured on any pin.
+ * Specifically, the switch PHY link LEDs and
+ * WMAC external RX LNA switches are not limited to
+ * a specific GPIO pin.
+ */
+static void
+ar934x_chip_gpio_output_configure(int gpio, uint8_t func)
+{
+	uint32_t reg, s;
+	uint32_t t;
+
+	if (gpio > AR934X_GPIO_COUNT)
+		return;
+
+	reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
+	s = 8 * (gpio % 4);
+
+	/* read-modify-write */
+	t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
+	t &= ~(0xff << s);
+	t |= func << s;
+	ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t);
+
+	/* flush write */
+	ATH_READ_REG(AR71XX_GPIO_BASE + reg);
+}
+
 struct ar71xx_cpu_def ar934x_chip_def = {
 	&ar934x_chip_detect_mem_size,
 	&ar934x_chip_detect_sys_frequency,
@@ -434,4 +465,5 @@ struct ar71xx_cpu_def ar934x_chip_def = {
 	&ar934x_chip_reset_wmac,
 	&ar934x_chip_init_gmac,
 	&ar934x_chip_reset_nfc,
+	&ar934x_chip_gpio_output_configure,
 };