Add support for the DEC_ST6600 family of alphas. This includes the

Compaq XP1000, AlphaServer DS20, AlphaServer DS10, and DP264

This has been tested *only* on XP1000's.  I'll be interested to hear from
owners of other types of DEC_ST6600 alphas.

I'd like to thank Don Rice of Compaq for providing the documentation required
to support this platform on FreeBSD.  I'd also like to thank Doug Rabson for newbus,
and for helping me get a multiple hoses working with newbus.

Reviewed by:	Doug Rabson <dfr@nlsystems.com>

11 files changed, 980 insertions, 5 deletions

diff --git a/sys/alpha/alpha/cpuconf.c b/sys/alpha/alpha/cpuconf.c
index 887a542..cacc31c 100644
--- a/sys/alpha/alpha/cpuconf.c
+++ b/sys/alpha/alpha/cpuconf.c
@@ -1,4 +1,4 @@
-/* $Id: cpuconf.c,v 1.1 1998/06/10 10:52:18 dfr Exp $ */
+/* $Id: cpuconf.c,v 1.2 1998/08/10 07:53:58 dfr Exp $ */
 /*	$NetBSD: cpuconf.c,v 1.10 1998/03/20 21:48:21 thorpej Exp $	*/
 
 /*
@@ -99,6 +99,12 @@ extern void st550_init __P((int));
 #define	st550_init		platform_not_configured
 #endif
 
+#ifdef DEC_ST6600
+extern void st6600_init __P((int));
+#else
+#define	st6600_init		platform_not_configured
+#endif
+
 struct cpuinit cpuinit[] = {
 	cpu_notsupp("???"),			     /*  0: ??? */
 	cpu_notsupp("ST_ADU"),			     /*  1: ST_ADU */
@@ -134,6 +140,7 @@ struct cpuinit cpuinit[] = {
 	cpu_notsupp("???"),			     /* 31: ??? */
 	cpu_notsupp("ST_DEC_EV56_PBP"),		     /* 32: ST_DEC_EV56_PBP */
 	cpu_notsupp("ST_DEC_ALPHAVME_320"),	   /* 33: ST_DEC_ALPHAVME_320 */
+	cpu_init(st6600_init, "ST_DEC_ST6600"),	     /* 34: ST_DEC_6600 */
 };
 int ncpuinit = (sizeof(cpuinit) / sizeof(cpuinit[0]));
 
diff --git a/sys/alpha/alpha/dec_st6600.c b/sys/alpha/alpha/dec_st6600.c
new file mode 100644
index 0000000..a1724e5
--- /dev/null
+++ b/sys/alpha/alpha/dec_st6600.c
@@ -0,0 +1,155 @@
+/*-
+ * Copyright (c) 1999 Andrew Gallatin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	$Id $
+ */
+
+#include "opt_ddb.h"
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <machine/intr.h>
+
+#include <sys/device.h>
+#include <sys/termios.h>
+
+#include <machine/rpb.h>
+#include <machine/cpuconf.h>
+#include <machine/clock.h>
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+#include <pci/pci_ioctl.h>
+#include <alpha/pci/tsunamireg.h>
+#include <alpha/pci/tsunamivar.h>
+
+#include "sio.h"
+#include "sc.h"
+
+#ifndef CONSPEED
+#define CONSPEED TTYDEF_SPEED
+#endif
+static int comcnrate = CONSPEED;
+
+void st6600_init __P((void));
+static void st6600_cons_init __P((void));
+static void st6600_intr_init __P((void));
+static void st6600_intr_map __P((void *));
+
+#define ST6600_PCI_IRQ_BEGIN 8
+#define ST6600_PCI_MAX_IRQ  63
+
+extern int siocnattach __P((int, int));
+extern int siogdbattach __P((int, int));
+extern int sccnattach __P((void));
+
+void
+st6600_init()
+{
+	platform.family = "Compaq Professional Workstation (Monet)";
+
+	if ((platform.model = alpha_dsr_sysname()) == NULL) {
+		/* XXX Don't know the system variations, yet. */
+		platform.model = alpha_unknown_sysname();
+	}
+
+	platform.iobus = "tsunami";
+	platform.cons_init = st6600_cons_init;
+	platform.pci_intr_init = st6600_intr_init;
+	platform.pci_intr_map = st6600_intr_map;
+}
+
+extern int comconsole;
+
+static void
+st6600_cons_init()
+{
+	struct ctb *ctb;
+
+	tsunami_init();
+#ifdef DDB
+	siogdbattach(0x2f8, 57600);
+#endif
+
+	ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
+
+	switch (ctb->ctb_term_type) {
+	case 2: 
+		/* serial console ... */
+		/* XXX */
+		{
+			/*
+			 * Delay to allow PROM putchars to complete.
+			 * FIFO depth * character time,
+			 * character time = (1000000 / (defaultrate / 10))
+			 */
+			DELAY(160000000 / comcnrate);
+			comconsole = 0;
+			if (siocnattach(0x3f8, comcnrate))
+				panic("can't init serial console");
+
+			break;
+		}
+
+	case 3:
+		/* display console ... */
+		/* XXX */
+#if NSC > 0
+		sccnattach();
+#else
+		panic("not configured to use display && keyboard console");
+#endif
+		break;
+
+	default:
+		printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
+		printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
+
+		panic("consinit: unknown console type %ld\n",
+		    ctb->ctb_term_type);
+	}
+}
+
+static void
+st6600_intr_init()
+{
+
+	int i;
+	for(i = ST6600_PCI_IRQ_BEGIN; i <= ST6600_PCI_MAX_IRQ; i++)
+		platform.pci_intr_disable(i);
+	/* From Linux... */
+
+	platform.pci_intr_enable(55);	
+	platform.pci_intr_enable(2);	
+
+}
+
+static void
+st6600_intr_map(void *arg)
+{
+	return;
+}
+
diff --git a/sys/alpha/conf/GENERIC b/sys/alpha/conf/GENERIC
index ae00ce9..865313b 100644
--- a/sys/alpha/conf/GENERIC
+++ b/sys/alpha/conf/GENERIC
@@ -11,7 +11,7 @@
 # device lines is present in the ./LINT configuration file. If you are 
 # in doubt as to the purpose or necessity of a line, check first in LINT.
 #
-#	$Id: GENERIC,v 1.21 1999/05/09 11:42:19 dfr Exp $
+#	$Id: GENERIC,v 1.22 1999/05/10 13:30:51 dfr Exp $
 
 machine		"alpha"
 cpu		"EV4"
@@ -26,6 +26,7 @@ options		"DEC_EB64PLUS"		# EB64+, Aspen Alpine, etc
 options		"DEC_2100_A50"		# AlphaStation 200, 250, 255, 400
 options		"DEC_KN20AA"		# AlphaStation 500, 600
 options		"DEC_ST550"		# Personal Workstation 433, 500, 600
+options		"DEC_ST6600"		# xp1000, dp264, ds20, ds10, family
 options		"DEC_3000_300"		# DEC3000/300* Pelic* family
 options		"DEC_3000_500"		# DEC3000/[4-9]00 Flamingo/Sandpiper family
 
@@ -48,6 +49,7 @@ options		FAILSAFE		#Be conservative
 # Platform chipsets
 controller	cia0
 controller	apecs0
+controller	tsunami0
 controller	lca0
 
 # Standard busses
diff --git a/sys/alpha/conf/NOTES b/sys/alpha/conf/NOTES
index ae00ce9..865313b 100644
--- a/sys/alpha/conf/NOTES
+++ b/sys/alpha/conf/NOTES
@@ -11,7 +11,7 @@
 # device lines is present in the ./LINT configuration file. If you are 
 # in doubt as to the purpose or necessity of a line, check first in LINT.
 #
-#	$Id: GENERIC,v 1.21 1999/05/09 11:42:19 dfr Exp $
+#	$Id: GENERIC,v 1.22 1999/05/10 13:30:51 dfr Exp $
 
 machine		"alpha"
 cpu		"EV4"
@@ -26,6 +26,7 @@ options		"DEC_EB64PLUS"		# EB64+, Aspen Alpine, etc
 options		"DEC_2100_A50"		# AlphaStation 200, 250, 255, 400
 options		"DEC_KN20AA"		# AlphaStation 500, 600
 options		"DEC_ST550"		# Personal Workstation 433, 500, 600
+options		"DEC_ST6600"		# xp1000, dp264, ds20, ds10, family
 options		"DEC_3000_300"		# DEC3000/300* Pelic* family
 options		"DEC_3000_500"		# DEC3000/[4-9]00 Flamingo/Sandpiper family
 
@@ -48,6 +49,7 @@ options		FAILSAFE		#Be conservative
 # Platform chipsets
 controller	cia0
 controller	apecs0
+controller	tsunami0
 controller	lca0
 
 # Standard busses
diff --git a/sys/alpha/conf/files.alpha b/sys/alpha/conf/files.alpha
index d0f4003..b589354 100644
--- a/sys/alpha/conf/files.alpha
+++ b/sys/alpha/conf/files.alpha
@@ -1,7 +1,7 @@
 # This file tells config what files go into building a kernel,
 # files marked standard are always included.
 #
-#	$Id: files.alpha,v 1.17 1999/03/10 10:36:50 yokota Exp $
+#	$Id: files.alpha,v 1.18 1999/04/16 21:21:34 peter Exp $
 #
 # The long compile-with and dependency lines are required because of
 # limitations in config: backslash-newline doesn't work in strings, and
@@ -27,6 +27,7 @@ alpha/alpha/dec_eb64plus.c	optional	dec_eb64plus
 alpha/alpha/dec_kn20aa.c	optional	dec_kn20aa
 alpha/alpha/dec_2100_a50.c	optional	dec_2100_a50
 alpha/alpha/dec_st550.c		optional	dec_st550
+alpha/alpha/dec_st6600.c	optional	dec_st6600
 alpha/alpha/dec_axppci_33.c	optional	dec_axppci_33
 alpha/alpha/dec_3000_300.c	optional	dec_3000_300
 alpha/alpha/dec_3000_500.c	optional	dec_3000_500
@@ -119,6 +120,8 @@ alpha/pci/apecs_pci.c		optional	apecs
 alpha/pci/pci_eb64plus_intr.s	optional	apecs
 alpha/pci/lca.c			optional	lca
 alpha/pci/lca_pci.c		optional	lca
+alpha/pci/tsunami.c		optional	tsunami
+alpha/pci/tsunami_pci.c		optional	tsunami
 alpha/pci/pcibus.c		optional	pci
 alpha/isa/isa.c			optional	isa
 alpha/isa/mcclock_isa.c		optional	isa
diff --git a/sys/alpha/include/rpb.h b/sys/alpha/include/rpb.h
index 2b79fd2..33846e7 100644
--- a/sys/alpha/include/rpb.h
+++ b/sys/alpha/include/rpb.h
@@ -76,6 +76,7 @@ struct rpb {
 #define	ST_DEC_550		30		/* "Miata" (PCI/ISA) */
 #define	ST_DEC_EV56_PBP		32		/* "Takara" (?) */
 #define	ST_DEC_ALPHAVME_320	33		/* "Yukon" (VME?) */
+#define	ST_DEC_6600		34		/* "Monet/Goldrush" */
 
 	u_int64_t	rpb_type;		/*  50: */
 
diff --git a/sys/alpha/pci/tsunami.c b/sys/alpha/pci/tsunami.c
new file mode 100644
index 0000000..70278d3
--- /dev/null
+++ b/sys/alpha/pci/tsunami.c
@@ -0,0 +1,576 @@
+/*-
+ * Copyright (c) 1999 Andrew Gallatin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	$Id $
+ */
+
+#include "opt_cpu.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <sys/malloc.h>
+
+#include <pci/pcivar.h>
+#include <alpha/pci/tsunamireg.h>
+#include <alpha/pci/tsunamivar.h>
+#include <alpha/pci/pcibus.h>
+#include <machine/bwx.h>
+#include <machine/intr.h>
+#include <machine/intrcnt.h>
+#include <machine/cpuconf.h>
+#include <machine/rpb.h>
+#include <machine/resource.h>
+
+#define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
+
+static devclass_t	tsunami_devclass;
+static device_t		tsunami0;		/* XXX only one for now */
+extern vm_offset_t      alpha_XXX_dmamap_or;
+struct tsunami_softc {
+	int		junk;		/* no softc */
+};
+
+#define TSUNAMI_SOFTC(dev)	(struct tsunami_softc*) device_get_softc(dev)
+
+static alpha_chipset_inb_t	tsunami_inb;
+static alpha_chipset_inw_t	tsunami_inw;
+static alpha_chipset_inl_t	tsunami_inl;
+static alpha_chipset_outb_t	tsunami_outb;
+static alpha_chipset_outw_t	tsunami_outw;
+static alpha_chipset_outl_t	tsunami_outl;
+static alpha_chipset_readb_t	tsunami_readb;
+static alpha_chipset_readw_t	tsunami_readw;
+static alpha_chipset_readl_t	tsunami_readl;
+static alpha_chipset_writeb_t	tsunami_writeb;
+static alpha_chipset_writew_t	tsunami_writew;
+static alpha_chipset_writel_t	tsunami_writel;
+static alpha_chipset_maxdevs_t	tsunami_maxdevs;
+static alpha_chipset_cfgreadb_t	tsunami_cfgreadb;
+static alpha_chipset_cfgreadw_t	tsunami_cfgreadw;
+static alpha_chipset_cfgreadl_t	tsunami_cfgreadl;
+static alpha_chipset_cfgwriteb_t tsunami_cfgwriteb;
+static alpha_chipset_cfgwritew_t tsunami_cfgwritew;
+static alpha_chipset_cfgwritel_t tsunami_cfgwritel;
+static alpha_chipset_addrcvt_t   tsunami_cvt_dense, tsunami_cvt_bwx;
+
+static alpha_chipset_read_hae_t	tsunami_read_hae;
+static alpha_chipset_write_hae_t tsunami_write_hae;
+
+static alpha_chipset_t tsunami_chipset = {
+	tsunami_inb,
+	tsunami_inw,
+	tsunami_inl,
+	tsunami_outb,
+	tsunami_outw,
+	tsunami_outl,
+	tsunami_readb,
+	tsunami_readw,
+	tsunami_readl,
+	tsunami_writeb,
+	tsunami_writew,
+	tsunami_writel,
+	tsunami_maxdevs,
+	tsunami_cfgreadb,
+	tsunami_cfgreadw,
+	tsunami_cfgreadl,
+	tsunami_cfgwriteb,
+	tsunami_cfgwritew,
+	tsunami_cfgwritel,
+	tsunami_cvt_dense,
+	tsunami_cvt_bwx,
+	tsunami_read_hae,
+	tsunami_write_hae,
+};
+
+/*
+ * This setup will only allow for one additional hose
+ */
+
+#define ADDR_TO_HOSE(x)    ((x)  >> 31)
+#define STRIP_HOSE(x)      ((x) & 0x7fffffff)
+
+static void tsunami_intr_enable  __P((int));
+static void tsunami_intr_disable __P((int));
+
+static u_int8_t
+tsunami_inb(u_int32_t port)
+{
+	int hose = ADDR_TO_HOSE(port);
+	port = STRIP_HOSE(port);
+	alpha_mb();
+	return ldbu(KV(TSUNAMI_IO(hose) + port));
+}
+
+static u_int16_t
+tsunami_inw(u_int32_t port)
+{
+	int hose = ADDR_TO_HOSE(port);
+	port = STRIP_HOSE(port);
+	alpha_mb();
+	return ldwu(KV(TSUNAMI_IO(hose) + port));
+}
+
+static u_int32_t
+tsunami_inl(u_int32_t port)
+{
+	int hose = ADDR_TO_HOSE(port);
+	port = STRIP_HOSE(port);
+	alpha_mb();
+	return ldl(KV(TSUNAMI_IO(hose) + port));
+}
+
+static void
+tsunami_outb(u_int32_t port, u_int8_t data)
+{
+	int hose = ADDR_TO_HOSE(port);
+	port = STRIP_HOSE(port);
+	stb(KV(TSUNAMI_IO(hose) + port), data);
+	alpha_mb();
+}
+
+static void
+tsunami_outw(u_int32_t port, u_int16_t data)
+{
+	int hose = ADDR_TO_HOSE(port);
+	port = STRIP_HOSE(port);
+	stw(KV(TSUNAMI_IO(hose) + port), data);
+	alpha_mb();
+}
+
+static void
+tsunami_outl(u_int32_t port, u_int32_t data)
+{
+	int hose = ADDR_TO_HOSE(port);
+	port = STRIP_HOSE(port);
+	stl(KV(TSUNAMI_IO(hose) + port), data);
+	alpha_mb();
+}
+
+static u_int8_t
+tsunami_readb(u_int32_t pa)
+{
+	int hose = ADDR_TO_HOSE(pa);
+	pa = STRIP_HOSE(pa);
+	alpha_mb();
+	return ldbu(KV(TSUNAMI_MEM(hose) + pa));
+}
+
+static u_int16_t
+tsunami_readw(u_int32_t pa)
+{
+	int hose = ADDR_TO_HOSE(pa);
+	pa = STRIP_HOSE(pa);
+	alpha_mb();
+	return ldwu(KV(TSUNAMI_MEM(hose) + pa));
+}
+
+static u_int32_t
+tsunami_readl(u_int32_t pa)
+{
+	int hose = ADDR_TO_HOSE(pa);
+	pa = STRIP_HOSE(pa);
+	alpha_mb();
+	return ldl(KV(TSUNAMI_MEM(hose) + pa));
+}
+
+static void
+tsunami_writeb(u_int32_t pa, u_int8_t data)
+{
+	int hose = ADDR_TO_HOSE(pa);
+	pa = STRIP_HOSE(pa);
+	stb(KV(TSUNAMI_MEM(hose) + pa), data);
+	alpha_mb();
+}
+
+static void
+tsunami_writew(u_int32_t pa, u_int16_t data)
+{
+	int hose = ADDR_TO_HOSE(pa);
+	pa = STRIP_HOSE(pa);
+	stw(KV(TSUNAMI_MEM(hose) + pa), data);
+	alpha_mb();
+}
+
+static void
+tsunami_writel(u_int32_t pa, u_int32_t data)
+{
+	int hose = ADDR_TO_HOSE(pa);
+	pa = STRIP_HOSE(pa);
+	stl(KV(TSUNAMI_MEM(hose) + pa), data);
+	alpha_mb();
+}
+
+static int
+tsunami_maxdevs(u_int b)
+{
+	return 12;		/* XXX */
+}
+
+static void
+tsunami_clear_abort(void)
+{
+	alpha_mb();
+	alpha_pal_draina();	
+}
+
+static int
+tsunami_check_abort(void)
+{
+/*	u_int32_t errbits;*/
+	int ba = 0;
+
+	alpha_pal_draina();	
+	alpha_mb();
+#if 0
+	errbits = REGVAL(TSUNAMI_CSR_TSUNAMI_ERR);
+	if (errbits & (TSUNAMI_ERR_RCVD_MAS_ABT|TSUNAMI_ERR_RCVD_TAR_ABT))
+		ba = 1;
+
+	if (errbits) {
+		REGVAL(TSUNAMI_CSR_TSUNAMI_ERR) = errbits;
+		alpha_mb();
+		alpha_pal_draina();
+	}
+#endif
+	return ba;
+}
+
+#define TSUNAMI_CFGADDR(b, s, f, r, h)				\
+	KV(TSUNAMI_CONF(h) | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
+
+#define CFGREAD(h, b, s, f, r, op, width, type)			\
+	int bus = tsunami_bus_within_hose(h, b);		\
+	vm_offset_t va = TSUNAMI_CFGADDR(bus, s, f, r, h);	\
+	type data;						\
+	tsunami_clear_abort();					\
+	if (badaddr((caddr_t)va, width)) {			\
+		tsunami_check_abort();				\
+		return ~0;					\
+	}							\
+	data = ##op##(va);					\
+	if (tsunami_check_abort())				\
+		return ~0;					\
+	return data;			
+
+#define CFWRITE(h, b, s, f, r, data, op, width)			\
+	int bus = tsunami_bus_within_hose(h, b);		\
+	vm_offset_t va = TSUNAMI_CFGADDR(bus, s, f, r, h);	\
+	tsunami_clear_abort();					\
+	if (badaddr((caddr_t)va, width)) 			\
+		return;						\
+	##op##(va, data);					\
+	tsunami_check_abort();
+
+
+
+
+static u_int8_t
+tsunami_cfgreadb(u_int h, u_int b, u_int s, u_int f, u_int r)
+{
+	CFGREAD(h, b, s, f, r, ldbu, 1, u_int8_t)
+}
+
+static u_int16_t
+tsunami_cfgreadw(u_int h, u_int b, u_int s, u_int f, u_int r)
+{
+	CFGREAD(h, b, s, f, r, ldwu, 2, u_int16_t)
+}
+
+static u_int32_t
+tsunami_cfgreadl(u_int h, u_int b, u_int s, u_int f, u_int r)
+{
+	CFGREAD(h, b, s, f, r, ldl, 4, u_int32_t)
+}
+
+static void
+tsunami_cfgwriteb(u_int h, u_int b, u_int s, u_int f, u_int r, u_int8_t data)
+{
+	CFWRITE(h, b, s, f, r, data, stb, 1)	
+}
+
+static void
+tsunami_cfgwritew(u_int h, u_int b, u_int s, u_int f, u_int r, u_int16_t data)
+{	
+	CFWRITE(h, b, s, f, r, data, stw, 2)
+}
+
+static void
+tsunami_cfgwritel(u_int h, u_int b, u_int s, u_int f, u_int r, u_int32_t data)
+{
+	CFWRITE(h, b, s, f, r, data, stl, 4)
+}
+
+
+vm_offset_t
+tsunami_cvt_bwx(vm_offset_t addr)
+{
+	int hose;
+	vm_offset_t laddr;
+	laddr = addr & 0xffffffffUL;
+	hose = ADDR_TO_HOSE(laddr);
+	laddr = STRIP_HOSE(addr);
+        laddr |=  TSUNAMI_MEM(hose);
+	return (KV(laddr));
+}
+
+vm_offset_t
+tsunami_cvt_dense(vm_offset_t addr)
+{
+	return tsunami_cvt_bwx(addr);
+}
+
+
+/* 
+ * There doesn't appear to be an hae on this platform
+ */
+
+
+static u_int64_t
+tsunami_read_hae(void)
+{
+	return 0;  
+}
+
+static void
+tsunami_write_hae(u_int64_t hae)
+{
+}
+
+static int tsunami_probe(device_t dev);
+static int tsunami_attach(device_t dev);
+static int tsunami_setup_intr(device_t dev, device_t child, 
+			      struct resource *irq, int flags,
+			  driver_intr_t *intr, void *arg, void **cookiep);
+static int tsunami_teardown_intr(device_t dev, device_t child,
+			     struct resource *irq, void *cookie);
+
+static device_method_t tsunami_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		tsunami_probe),
+	DEVMETHOD(device_attach,	tsunami_attach),
+
+	/* Bus interface */
+	DEVMETHOD(bus_print_child,      bus_generic_print_child),
+	DEVMETHOD(bus_alloc_resource,	pci_alloc_resource),
+	DEVMETHOD(bus_release_resource,	pci_release_resource),
+	DEVMETHOD(bus_activate_resource, pci_activate_resource),
+	DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
+	DEVMETHOD(bus_setup_intr,	tsunami_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	tsunami_teardown_intr),
+
+	{ 0, 0 }
+};
+
+static driver_t tsunami_driver = {
+	"tsunami",
+	tsunami_methods,
+	sizeof(struct tsunami_softc),
+};
+
+static void
+pchip_init(tsunami_pchip *pchip, int index)
+{
+#if 0
+
+	/* 
+	 *  The code below, if active, would attempt to
+	 *  setup the DMA base and size registers of Window 0 
+	 *  to emulate the  placement of the direct-mapped window 
+         *  on previous chipsets.
+	 *
+	 *  HOWEVER: doing this means that a 64-bit card at device 11
+	 *  would not be able to be setup for DMA.
+	 * 
+	 *  For now, we just trust the SRM console to set things up
+	 *  properly.  This works on the xp1000, but may need to be
+	 *  to be revisited for other systems.
+ 	 */ 
+
+	printf("initializing pchip%d\n", index);	
+	pchip->wsba[0].reg = 1L | (1024*1024*1024U & 0xfff00000U);
+	pchip->wsm[0].reg = (1024*1024*1024U - 1) & 0xfff00000UL;
+	pchip->tba[0].reg = 0;
+	/* 
+	 * disable windows 1, 2 and 3 
+	 */
+
+
+	pchip->wsba[1].reg = 0;
+	pchip->wsba[2].reg = 0;
+	pchip->wsba[3].reg = 0;
+
+	alpha_mb();
+#endif	
+
+}	
+
+
+void
+tsunami_init()
+{
+	static int initted = 0;
+
+	if (initted) return;
+	initted = 1;
+
+	chipset = tsunami_chipset;
+	platform.pci_intr_enable =  tsunami_intr_enable;
+	platform.pci_intr_disable = tsunami_intr_disable;
+	alpha_XXX_dmamap_or = 2UL * 1024UL * 1024UL * 1024UL;
+
+	if (platform.pci_intr_init)
+		platform.pci_intr_init();
+}
+
+static int
+tsunami_probe(device_t dev)
+{
+	int *hose;
+	int i;
+	if (tsunami0)
+		return ENXIO;
+	tsunami0 = dev;
+	device_set_desc(dev, "21271 Core Logic chipset"); 
+
+	pci_init_resources();
+	isa_init_intr();
+
+	for(i = 0; i < 2; i++) {
+		hose = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
+		*hose = i;
+		device_add_child(dev, "pcib", i, hose);
+	}
+	pchip_init(pchip0, 0);
+	pchip_init(pchip1, 1);
+	return 0;
+}
+
+	
+
+static int
+tsunami_attach(device_t dev)
+{
+	tsunami_init();
+
+	if (!platform.iointr)	/* XXX */
+		set_iointr(alpha_dispatch_intr);
+
+	snprintf(chipset_type, sizeof(chipset_type), "tsunami");
+	chipset_bwx = 1;
+
+	chipset_ports = TSUNAMI_IO(0);
+	chipset_memory = TSUNAMI_MEM(0);
+	chipset_dense = TSUNAMI_MEM(0);
+	bus_generic_attach(dev);
+	
+	return 0;
+}
+
+static int
+tsunami_setup_intr(device_t dev, device_t child,
+	       struct resource *irq, int flags,
+	       driver_intr_t *intr, void *arg, void **cookiep)
+{
+	int error;
+
+	error = rman_activate_resource(irq);
+	if (error)
+		return error;
+
+	error = alpha_setup_intr(0x900 + (irq->r_start << 4),
+			intr, arg, cookiep,
+			&intrcnt[INTRCNT_EB164_IRQ + irq->r_start]);
+	if (error)
+		return error;
+
+	/* Enable PCI interrupt */
+	platform.pci_intr_enable(irq->r_start);
+
+	device_printf(child, "interrupting at TSUNAMI irq %d\n",
+		      (int) irq->r_start);
+
+	return 0;
+}
+
+static int
+tsunami_teardown_intr(device_t dev, device_t child,
+		  struct resource *irq, void *cookie)
+{
+
+	alpha_teardown_intr(cookie);
+	return rman_deactivate_resource(irq);
+
+}
+
+
+/*
+ * Currently, all interrupts will be funneled through CPU 0
+ */
+
+static void
+tsunami_intr_enable(int irq)
+{
+	volatile u_int64_t *mask;
+	u_int64_t saved_mask;
+
+	mask = &cchip->dim0.reg;
+	saved_mask = *mask;
+
+	saved_mask |= (1UL << (unsigned long)irq);
+	*mask = saved_mask;
+	alpha_mb();
+	alpha_mb();
+	saved_mask = *mask;
+	alpha_mb();
+	alpha_mb();
+}
+
+static void
+tsunami_intr_disable(int irq)
+{
+	volatile u_int64_t *mask;
+	u_int64_t saved_mask;
+
+	mask = &cchip->dim0.reg;
+	saved_mask = *mask;
+
+	saved_mask &= ~(1UL << (unsigned long)irq);
+	*mask = saved_mask;
+	alpha_mb();
+	saved_mask = *mask;
+	alpha_mb();
+	alpha_mb();
+
+}
+
+
+
+DRIVER_MODULE(tsunami, root, tsunami_driver, tsunami_devclass, 0, 0);
+
diff --git a/sys/alpha/pci/tsunami_pci.c b/sys/alpha/pci/tsunami_pci.c
new file mode 100644
index 0000000..1af09c1
--- /dev/null
+++ b/sys/alpha/pci/tsunami_pci.c
@@ -0,0 +1,106 @@
+/*-
+ * Copyright (c) 1999 Andrew Gallatin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	$Id$
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/bus.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <pci/pcivar.h>
+#include <alpha/pci/tsunamireg.h>
+#include <alpha/pci/tsunamivar.h>
+
+
+static devclass_t	pcib_devclass;
+
+int tsunami_hoses[TSUNAMI_MAXHOSES] = {0,0,0,0};
+
+int
+tsunami_bus_within_hose(int hose, int bus)
+{
+	return(bus - tsunami_hoses[hose]);
+}
+
+static int
+tsunami_pcib_probe(device_t dev)
+{
+	static int hoseno = 0;
+	device_t child;
+
+	device_set_desc(dev, "21271 PCI host bus adapter");
+
+	child = device_add_child(dev, "pci", -1, 0);
+
+	if(hoseno)
+		tsunami_hoses[hoseno] = device_get_unit(child);
+	hoseno++;
+	return 0;
+}
+
+static int
+tsunami_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
+{
+	if (which == PCIB_IVAR_HOSE) {
+		*result = *(int*) device_get_ivars(dev);
+		return 0;
+	}
+	return ENOENT;
+}
+
+static device_method_t tsunami_pcib_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		tsunami_pcib_probe),
+	DEVMETHOD(device_attach,	bus_generic_attach),
+
+	/* Bus interface */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+	DEVMETHOD(bus_read_ivar,	tsunami_pcib_read_ivar),
+	DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
+	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
+	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
+	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
+
+	{ 0, 0 }
+};
+
+
+static driver_t tsunami_pcib_driver = {
+	"pcib",
+	tsunami_pcib_methods,
+	1,
+};
+
+
+DRIVER_MODULE(pcib, tsunami, tsunami_pcib_driver, pcib_devclass, 0, 0);
+
+
diff --git a/sys/alpha/pci/tsunamireg.h b/sys/alpha/pci/tsunamireg.h
new file mode 100644
index 0000000..9b29828
--- /dev/null
+++ b/sys/alpha/pci/tsunamireg.h
@@ -0,0 +1,90 @@
+/* $Id$ */
+
+/*
+ * 21271 Chipset registers and constants.
+ *
+ * Taken from Tsunami/Typhoon Specification Rev. 1.2
+ * and Compaq Professional Workstation XP1000: Technical
+ * Information, both graciously provided by Don Rice 
+ */
+
+
+typedef struct {
+	volatile u_int64_t reg __attribute__((aligned(64)));
+} tsunami_reg;
+					/* notes */
+typedef struct { 
+	tsunami_reg	csc;		/* rw */
+	tsunami_reg	mtr;		/* rw */
+	tsunami_reg	misc;		/* rw */
+	tsunami_reg	mpd;		/* rw */
+	tsunami_reg	aar0;		/* rw */
+	tsunami_reg	aar1;		/* rw */
+	tsunami_reg	aar2;		/* rw */
+	tsunami_reg	aar3;		/* rw */
+	tsunami_reg	dim0;		/* rw */
+	tsunami_reg	dim1;		/* rw */
+	tsunami_reg	dir0;		/* ro */
+	tsunami_reg	dir1;		/* ro */
+	tsunami_reg	drir;		/* ro */
+	tsunami_reg	prben;		/* "special" */
+	tsunami_reg	iic0;		/* rw */
+	tsunami_reg	iic1;		/* rw */
+	tsunami_reg	mpr0;		/* wo */
+	tsunami_reg	mpr1;		/* wo */
+	tsunami_reg	mpr2;		/* wo */
+	tsunami_reg	mpr3;		/* wo */
+	tsunami_reg	mctl;		/* rw, Tsunami only */
+	tsunami_reg	ttr;		/* rw */
+	tsunami_reg	tdr;		/* rw */
+	tsunami_reg	dim2;		/* rw, Typhoon only */
+	tsunami_reg	dim3;		/* rw, Typhoon only */
+	tsunami_reg	dir2;		/* ro, Typhoon only */
+	tsunami_reg	dir3;		/* ro, Typhoon only */
+	tsunami_reg	iic2;		/* rw, Typhoon only */
+	tsunami_reg	iic3;		/* rw, Typhoon only */
+	tsunami_reg	pwr;		/* rw */
+} tsunami_cchip;
+
+typedef struct {
+	tsunami_reg	dsc;
+	tsunami_reg	str;
+	tsunami_reg	drev;
+} tsunami_dchip;
+
+typedef struct {
+	tsunami_reg	wsba[4];	/* rw */
+	tsunami_reg	wsm[4];		/* rw */
+	tsunami_reg	tba[4];		/* rw */
+	tsunami_reg	pctl;		/* rw */
+	tsunami_reg	plat;		/* ro */
+	tsunami_reg	reserved;	/* rw */
+	tsunami_reg	perror;		/* rw */
+	tsunami_reg	perrmask;	/* rw */
+	tsunami_reg	perrset;	/* wo */
+	tsunami_reg	tlbiv;		/* wo */
+	tsunami_reg	tlbia;		/* wo */
+	tsunami_reg	pmonctl;	/* rw */
+	tsunami_reg	pmoncnt;	/* rw */
+} tsunami_pchip;
+
+
+#define KV(pa)          ALPHA_PHYS_TO_K0SEG(pa)
+
+#define cchip		((tsunami_cchip *)(KV(0x101A0000000UL)))
+#define dchip		((tsunami_dchip *)(KV(0x101B0000800UL)))
+#define pchip0		((tsunami_pchip *)(KV(0x10180000000UL)))
+#define pchip1		((tsunami_pchip *)(KV(0x10380000000UL)))
+
+/*
+ *   memory / i/o space macros
+ *
+ */
+#define HOSE(h)			(((unsigned long)(h)) << 33)
+#define TSUNAMI_MEM(h)		(0x10000000000UL + HOSE(h))
+#define TSUNAMI_IACK_SC(h)	(0x101F8000000UL + HOSE(h))
+#define TSUNAMI_IO(h)		(0x101FC000000UL + HOSE(h))
+#define TSUNAMI_CONF(h)		(0x101FE000000UL + HOSE(h))
+
+
+#define TSUNAMI_MAXHOSES 4
diff --git a/sys/alpha/pci/tsunamivar.h b/sys/alpha/pci/tsunamivar.h
new file mode 100644
index 0000000..0c34115
--- /dev/null
+++ b/sys/alpha/pci/tsunamivar.h
@@ -0,0 +1,30 @@
+/*-
+ * Copyright (c) 1998 Andrew Gallatin
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	$Id$
+ */
+
+extern void tsunami_init(void);
+extern int tsunami_bus_within_hose(int, int);
diff --git a/sys/conf/files.alpha b/sys/conf/files.alpha
index d0f4003..b589354 100644
--- a/sys/conf/files.alpha
+++ b/sys/conf/files.alpha
@@ -1,7 +1,7 @@
 # This file tells config what files go into building a kernel,
 # files marked standard are always included.
 #
-#	$Id: files.alpha,v 1.17 1999/03/10 10:36:50 yokota Exp $
+#	$Id: files.alpha,v 1.18 1999/04/16 21:21:34 peter Exp $
 #
 # The long compile-with and dependency lines are required because of
 # limitations in config: backslash-newline doesn't work in strings, and
@@ -27,6 +27,7 @@ alpha/alpha/dec_eb64plus.c	optional	dec_eb64plus
 alpha/alpha/dec_kn20aa.c	optional	dec_kn20aa
 alpha/alpha/dec_2100_a50.c	optional	dec_2100_a50
 alpha/alpha/dec_st550.c		optional	dec_st550
+alpha/alpha/dec_st6600.c	optional	dec_st6600
 alpha/alpha/dec_axppci_33.c	optional	dec_axppci_33
 alpha/alpha/dec_3000_300.c	optional	dec_3000_300
 alpha/alpha/dec_3000_500.c	optional	dec_3000_500
@@ -119,6 +120,8 @@ alpha/pci/apecs_pci.c		optional	apecs
 alpha/pci/pci_eb64plus_intr.s	optional	apecs
 alpha/pci/lca.c			optional	lca
 alpha/pci/lca_pci.c		optional	lca
+alpha/pci/tsunami.c		optional	tsunami
+alpha/pci/tsunami_pci.c		optional	tsunami
 alpha/pci/pcibus.c		optional	pci
 alpha/isa/isa.c			optional	isa
 alpha/isa/mcclock_isa.c		optional	isa