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author | adrian <adrian@FreeBSD.org> | 2014-03-18 12:19:39 +0000 |
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committer | adrian <adrian@FreeBSD.org> | 2014-03-18 12:19:39 +0000 |
commit | 8b24253e00e331e26bbecfe0cbddd730a451ef8b (patch) | |
tree | d2c98b078b0328699197cfdcff8811712956c72f | |
parent | 97d88da1c6eea5966a62da63a3b58a65b2b71dea (diff) | |
download | FreeBSD-src-8b24253e00e331e26bbecfe0cbddd730a451ef8b.zip FreeBSD-src-8b24253e00e331e26bbecfe0cbddd730a451ef8b.tar.gz |
Extend the Atheros SoC support to include a method to enable/disable
the NAND flash controller.
Add the AR934x NAND flash controller reset routines.
(It's different on subsequent SoCs.)
Tested:
* AR9344, Atheros DB120 reference platform
Obtained from: OpenWRT
-rw-r--r-- | sys/mips/atheros/ar71xx_cpudef.h | 9 | ||||
-rw-r--r-- | sys/mips/atheros/ar934x_chip.c | 27 |
2 files changed, 36 insertions, 0 deletions
diff --git a/sys/mips/atheros/ar71xx_cpudef.h b/sys/mips/atheros/ar71xx_cpudef.h index 9a1133b..85618d4 100644 --- a/sys/mips/atheros/ar71xx_cpudef.h +++ b/sys/mips/atheros/ar71xx_cpudef.h @@ -63,6 +63,8 @@ struct ar71xx_cpu_def { void (* ar71xx_chip_reset_wmac) (void); void (* ar71xx_chip_init_gmac) (void); + + void (* ar71xx_chip_reset_nfc) (int); }; extern struct ar71xx_cpu_def * ar71xx_cpu_ops; @@ -140,6 +142,13 @@ static inline void ar71xx_device_ddr_flush_ip2(void) ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2(); } +static inline void ar71xx_reset_nfc(int active) +{ + + if (ar71xx_cpu_ops->ar71xx_chip_reset_nfc) + ar71xx_cpu_ops->ar71xx_chip_reset_nfc(active); +} + /* XXX shouldn't be here! */ extern uint32_t u_ar71xx_refclk; extern uint32_t u_ar71xx_cpu_freq; diff --git a/sys/mips/atheros/ar934x_chip.c b/sys/mips/atheros/ar934x_chip.c index 1266fc8..d66fd59 100644 --- a/sys/mips/atheros/ar934x_chip.c +++ b/sys/mips/atheros/ar934x_chip.c @@ -375,6 +375,7 @@ static void ar934x_chip_reset_wmac(void) { + /* XXX TODO */ } static void @@ -391,6 +392,31 @@ ar934x_chip_init_gmac(void) } } +/* + * Reset the NAND Flash Controller. + * + * + active=1 means "make it active". + * + active=0 means "make it inactive". + */ +static void +ar934x_chip_reset_nfc(int active) +{ + + if (active) { + ar71xx_device_start(AR934X_RESET_NANDF); + DELAY(100); + + ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG); + DELAY(250); + } else { + ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG); + DELAY(250); + + ar71xx_device_stop(AR934X_RESET_NANDF); + DELAY(100); + } +} + struct ar71xx_cpu_def ar934x_chip_def = { &ar934x_chip_detect_mem_size, &ar934x_chip_detect_sys_frequency, @@ -407,4 +433,5 @@ struct ar71xx_cpu_def ar934x_chip_def = { &ar934x_chip_reset_ethernet_switch, &ar934x_chip_reset_wmac, &ar934x_chip_init_gmac, + &ar934x_chip_reset_nfc, }; |