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| author | nwhitehorn <nwhitehorn@FreeBSD.org> | 2012-05-04 16:00:22 +0000 |
|---|---|---|
| committer | nwhitehorn <nwhitehorn@FreeBSD.org> | 2012-05-04 16:00:22 +0000 |
| commit | 68e9eabdbf1a8b9a1461c0a249d893b2c5223f45 (patch) | |
| tree | ecee53979b0f999ca24600814860dd57b6ca0ca3 | |
| parent | 4ee7205a6e0fa4716b49b495f88a3f51579b9ab0 (diff) | |
| download | FreeBSD-src-68e9eabdbf1a8b9a1461c0a249d893b2c5223f45.zip FreeBSD-src-68e9eabdbf1a8b9a1461c0a249d893b2c5223f45.tar.gz | |
Fix final bugs in memory barriers on PowerPC:
- Use isync/lwsync unconditionally for acquire/release. Use of isync
guarantees a complete memory barrier, which is important for serialization
of bus space accesses with mutexes on multi-processor systems.
- Go back to using sync as the I/O memory barrier, which solves the same
problem as above with respect to mutex release using lwsync, while not
penalizing non-I/O operations like a return to sync on the atomic release
operations would.
- Place an acquisition barrier around thread lock acquisition in
cpu_switchin().
| -rw-r--r-- | sys/powerpc/aim/swtch32.S | 3 | ||||
| -rw-r--r-- | sys/powerpc/aim/swtch64.S | 3 | ||||
| -rw-r--r-- | sys/powerpc/include/atomic.h | 5 | ||||
| -rw-r--r-- | sys/powerpc/include/pio.h | 7 |
4 files changed, 10 insertions, 8 deletions
diff --git a/sys/powerpc/aim/swtch32.S b/sys/powerpc/aim/swtch32.S index 76bb0f4..fa87aba 100644 --- a/sys/powerpc/aim/swtch32.S +++ b/sys/powerpc/aim/swtch32.S @@ -124,7 +124,8 @@ cpu_switchin: blocked_loop: lwz %r7,TD_LOCK(%r2) cmpw %r6,%r7 - beq blocked_loop + beq- blocked_loop + isync #endif mfsprg %r7,0 /* Get the pcpu pointer */ diff --git a/sys/powerpc/aim/swtch64.S b/sys/powerpc/aim/swtch64.S index 857ae40..ab6f532 100644 --- a/sys/powerpc/aim/swtch64.S +++ b/sys/powerpc/aim/swtch64.S @@ -150,7 +150,8 @@ cpu_switchin: blocked_loop: ld %r7,TD_LOCK(%r13) cmpd %r6,%r7 - beq blocked_loop + beq- blocked_loop + isync #endif mfsprg %r7,0 /* Get the pcpu pointer */ diff --git a/sys/powerpc/include/atomic.h b/sys/powerpc/include/atomic.h index c88c3fa..8ec3ea0 100644 --- a/sys/powerpc/include/atomic.h +++ b/sys/powerpc/include/atomic.h @@ -51,13 +51,8 @@ * with the atomic lXarx/stXcx. sequences below. See Appendix B.2 of Book II * of the architecture manual. */ -#ifdef __powerpc64__ -#define __ATOMIC_REL() __asm __volatile("lwsync" : : : "memory") -#define __ATOMIC_ACQ() __asm __volatile("lwsync" : : : "memory") -#else #define __ATOMIC_REL() __asm __volatile("lwsync" : : : "memory") #define __ATOMIC_ACQ() __asm __volatile("isync" : : : "memory") -#endif /* * atomic_add(p, v) diff --git a/sys/powerpc/include/pio.h b/sys/powerpc/include/pio.h index 0994ed1..b09e68a 100644 --- a/sys/powerpc/include/pio.h +++ b/sys/powerpc/include/pio.h @@ -39,7 +39,12 @@ * I/O macros. */ -#define powerpc_iomb() __asm __volatile("eieio" : : : "memory") +/* + * Use sync so that bus space operations cannot sneak out the bottom of + * mutex-protected sections (mutex release does not guarantee completion of + * accesses to caching-inhibited memory on some systems) + */ +#define powerpc_iomb() __asm __volatile("sync" : : : "memory") static __inline void __outb(volatile u_int8_t *a, u_int8_t v) |
