Corrected indentation on conflicted source files.

Reviewed by:	ambrisko
MFC after:	2 weeks
Sponsored by:	AVAGO Technologies

6 files changed, 319 insertions, 307 deletions

diff --git a/sys/dev/mrsas/mrsas.c b/sys/dev/mrsas/mrsas.c
index ca0a499..6f63c6e 100644
--- a/sys/dev/mrsas/mrsas.c
+++ b/sys/dev/mrsas/mrsas.c
@@ -84,16 +84,17 @@ static int mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex);
 static int mrsas_clear_intr(struct mrsas_softc *sc);
 static int mrsas_get_ctrl_info(struct mrsas_softc *sc);
 static void mrsas_update_ext_vd_details(struct mrsas_softc *sc);
-static int 
+static int
 mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc,
     struct mrsas_mfi_cmd *cmd_to_abort);
-static struct mrsas_softc *mrsas_get_softc_instance(struct cdev *dev,
-						u_long cmd, caddr_t arg);
+static struct mrsas_softc *
+mrsas_get_softc_instance(struct cdev *dev,
+    u_long cmd, caddr_t arg);
 u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset);
-u_int8_t 
+u_int8_t
 mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
     struct mrsas_mfi_cmd *mfi_cmd);
-void mrsas_complete_outstanding_ioctls (struct mrsas_softc *sc);
+void	mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc);
 int	mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr);
 int	mrsas_init_adapter(struct mrsas_softc *sc);
 int	mrsas_alloc_mpt_cmds(struct mrsas_softc *sc);
@@ -105,10 +106,10 @@ int	mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
 int	mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
 int	mrsas_reset_ctrl(struct mrsas_softc *sc);
 int	mrsas_wait_for_outstanding(struct mrsas_softc *sc);
-int 
+int
 mrsas_issue_blocked_cmd(struct mrsas_softc *sc,
     struct mrsas_mfi_cmd *cmd);
-int 
+int
 mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, struct mrsas_tmp_dcmd *tcmd,
     int size);
 void	mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd);
@@ -125,17 +126,17 @@ void	mrsas_teardown_intr(struct mrsas_softc *sc);
 void	mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
 void	mrsas_kill_hba(struct mrsas_softc *sc);
 void	mrsas_aen_handler(struct mrsas_softc *sc);
-void 
+void
 mrsas_write_reg(struct mrsas_softc *sc, int offset,
     u_int32_t value);
-void 
+void
 mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
     u_int32_t req_desc_hi);
 void	mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc);
-void 
+void
 mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc,
     struct mrsas_mfi_cmd *cmd, u_int8_t status);
-void 
+void
 mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status,
     u_int8_t extStatus);
 struct mrsas_mfi_cmd *mrsas_get_mfi_cmd(struct mrsas_softc *sc);
@@ -275,7 +276,7 @@ mrsas_disable_intr(struct mrsas_softc *sc)
 	u_int32_t mask = 0xFFFFFFFF;
 	u_int32_t status;
 
-	sc->mask_interrupts=1;
+	sc->mask_interrupts = 1;
 	mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), mask);
 	/* Dummy read to force pci flush */
 	status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask));
@@ -287,7 +288,7 @@ mrsas_enable_intr(struct mrsas_softc *sc)
 	u_int32_t mask = MFI_FUSION_ENABLE_INTERRUPT_MASK;
 	u_int32_t status;
 
-	sc->mask_interrupts=0;
+	sc->mask_interrupts = 0;
 	mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), ~0);
 	status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status));
 
@@ -1262,18 +1263,22 @@ mrsas_get_softc_instance(struct cdev *dev, u_long cmd, caddr_t arg)
 {
 	struct mrsas_softc *sc = NULL;
 	struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg;
-	if (cmd == MRSAS_IOC_GET_PCI_INFO){
-	sc = dev->si_drv1;
+
+	if (cmd == MRSAS_IOC_GET_PCI_INFO) {
+		sc = dev->si_drv1;
 	} else {
-	/* get the Host number & the softc from data sent by the Application */
-	sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no];
+		/*
+		 * get the Host number & the softc from data sent by the
+		 * Application
+		 */
+		sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no];
 		if ((user_ioc->host_no >= mrsas_mgmt_info.max_index) || (sc == NULL)) {
 			if (sc == NULL)
 				mrsas_dprint(sc, MRSAS_FAULT,
-					"There is no Controller number %d .\n", user_ioc->host_no);
+				    "There is no Controller number %d .\n", user_ioc->host_no);
 			else
 				mrsas_dprint(sc, MRSAS_FAULT,
-					"Invalid Controller number %d .\n", user_ioc->host_no);
+				    "Invalid Controller number %d .\n", user_ioc->host_no);
 		}
 	}
 
@@ -1343,17 +1348,17 @@ do_ioctl:
 		break;
 
 	case MRSAS_IOC_GET_PCI_INFO:
-		pciDrvInfo = (MRSAS_DRV_PCI_INFORMATION *)arg;
-		memset (pciDrvInfo, 0, sizeof(MRSAS_DRV_PCI_INFORMATION));
+		pciDrvInfo = (MRSAS_DRV_PCI_INFORMATION *) arg;
+		memset(pciDrvInfo, 0, sizeof(MRSAS_DRV_PCI_INFORMATION));
 		pciDrvInfo->busNumber = pci_get_bus(sc->mrsas_dev);
 		pciDrvInfo->deviceNumber = pci_get_slot(sc->mrsas_dev);
 		pciDrvInfo->functionNumber = pci_get_function(sc->mrsas_dev);
 		pciDrvInfo->domainID = pci_get_domain(sc->mrsas_dev);
-		mrsas_dprint (sc, MRSAS_INFO, "pci bus no: %d,"
-			"pci device no: %d, pci function no: %d,"
-			"pci domain ID: %d\n",
-			pciDrvInfo->busNumber, pciDrvInfo->deviceNumber,
-			pciDrvInfo->functionNumber, pciDrvInfo->domainID);
+		mrsas_dprint(sc, MRSAS_INFO, "pci bus no: %d,"
+		    "pci device no: %d, pci function no: %d,"
+		    "pci domain ID: %d\n",
+		    pciDrvInfo->busNumber, pciDrvInfo->deviceNumber,
+		    pciDrvInfo->functionNumber, pciDrvInfo->domainID);
 		ret = 0;
 		break;
 
@@ -1670,8 +1675,8 @@ mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status, u_int8_t ex
 static int
 mrsas_alloc_mem(struct mrsas_softc *sc)
 {
-	u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size, chain_frame_size,
-	          evt_detail_size, count;
+	u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size,
+	          chain_frame_size, evt_detail_size, count;
 
 	/*
 	 * Allocate parent DMA tag
@@ -1996,7 +2001,7 @@ ABORT:
  * get_pdlist, get_ld_list and max_sectors are currently not being used, it
  * is left here as placeholder.
  */
-static int 
+static int
 mrsas_init_fw(struct mrsas_softc *sc)
 {
 
@@ -2065,11 +2070,10 @@ mrsas_init_fw(struct mrsas_softc *sc)
 		device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n");
 		return (1);
 	}
-
 	sc->ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT);
 	if (!sc->ctrl_info) {
 		device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n");
-		return(1);
+		return (1);
 	}
 	/*
 	 * Get the controller info from FW, so that the MAX VD support
@@ -2077,10 +2081,10 @@ mrsas_init_fw(struct mrsas_softc *sc)
 	 */
 	if (mrsas_get_ctrl_info(sc)) {
 		device_printf(sc->mrsas_dev, "Unable to get FW ctrl_info.\n");
-		return(1);
+		return (1);
 	}
 	sc->secure_jbod_support =
-		(u_int8_t) sc->ctrl_info->adapterOperations3.supportSecurityonJBOD;
+	    (u_int8_t)sc->ctrl_info->adapterOperations3.supportSecurityonJBOD;
 
 	if (sc->secure_jbod_support)
 		device_printf(sc->mrsas_dev, "FW supports SED \n");
@@ -2109,7 +2113,7 @@ mrsas_init_fw(struct mrsas_softc *sc)
 	 */
 	tmp_sectors = 0;
 	max_sectors_1 = (1 << sc->ctrl_info->stripe_sz_ops.min) *
-		sc->ctrl_info->max_strips_per_io;
+	    sc->ctrl_info->max_strips_per_io;
 	max_sectors_2 = sc->ctrl_info->max_request_size;
 	tmp_sectors = min(max_sectors_1, max_sectors_2);
 	sc->max_sectors_per_req = sc->max_num_sge * MRSAS_PAGE_SIZE / 512;
@@ -2118,9 +2122,9 @@ mrsas_init_fw(struct mrsas_softc *sc)
 		sc->max_sectors_per_req = tmp_sectors;
 
 	sc->disableOnlineCtrlReset =
-		sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
+	    sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
 	sc->UnevenSpanSupport =
-		sc->ctrl_info->adapterOperations2.supportUnevenSpans;
+	    sc->ctrl_info->adapterOperations2.supportUnevenSpans;
 	if (sc->UnevenSpanSupport) {
 		device_printf(sc->mrsas_dev, "FW supports: UnevenSpanSupport=%x\n\n",
 		    sc->UnevenSpanSupport);
@@ -2130,7 +2134,6 @@ mrsas_init_fw(struct mrsas_softc *sc)
 		else
 			sc->fast_path_io = 0;
 	}
-
 	return (0);
 }
 
@@ -2451,7 +2454,7 @@ mrsas_alloc_mpt_cmds(struct mrsas_softc *sc)
  * This functions fires the command to Firmware by writing to the
  * inbound_low_queue_port and inbound_high_queue_port.
  */
-void 
+void
 mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
     u_int32_t req_desc_hi)
 {
@@ -2815,7 +2818,6 @@ mrsas_reset_ctrl(struct mrsas_softc *sc)
 				mrsas_dprint(sc, MRSAS_OCR, "mrsas_ioc_init() failed!\n");
 				continue;
 			}
-
 			/* Re-fire management commands */
 			for (j = 0; j < sc->max_fw_cmds; j++) {
 				mpt_cmd = sc->mpt_cmd_list[j];
@@ -2850,7 +2852,6 @@ mrsas_reset_ctrl(struct mrsas_softc *sc)
 				retval = FAIL;
 				goto out;
 			}
-
 			if (!mrsas_get_map_info(sc))
 				mrsas_sync_map_info(sc);
 
@@ -2895,7 +2896,7 @@ mrsas_kill_hba(struct mrsas_softc *sc)
 	    MFI_STOP_ADP);
 	/* Flush */
 	mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell));
-	mrsas_complete_outstanding_ioctls (sc);
+	mrsas_complete_outstanding_ioctls(sc);
 }
 
 /**
@@ -2904,22 +2905,24 @@ mrsas_kill_hba(struct mrsas_softc *sc)
  *
  * Returns void
  */
-void mrsas_complete_outstanding_ioctls (struct mrsas_softc *sc){
+void 
+mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc)
+{
 	int i;
-    struct mrsas_mpt_cmd *cmd_mpt;
-    struct mrsas_mfi_cmd *cmd_mfi;
-    u_int32_t count, MSIxIndex;
+	struct mrsas_mpt_cmd *cmd_mpt;
+	struct mrsas_mfi_cmd *cmd_mfi;
+	u_int32_t count, MSIxIndex;
 
 	count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
-	for (i=0; i<sc->max_fw_cmds; i++){
+	for (i = 0; i < sc->max_fw_cmds; i++) {
 		cmd_mpt = sc->mpt_cmd_list[i];
 
-		if (cmd_mpt->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX){
+		if (cmd_mpt->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) {
 			cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx];
-			if (cmd_mfi->sync_cmd && cmd_mfi->frame->hdr.cmd != MFI_CMD_ABORT){
-				for (MSIxIndex = 0 ; MSIxIndex < count; MSIxIndex++)
+			if (cmd_mfi->sync_cmd && cmd_mfi->frame->hdr.cmd != MFI_CMD_ABORT) {
+				for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++)
 					mrsas_complete_mptmfi_passthru(sc, cmd_mfi,
-								cmd_mpt->io_request->RaidContext.status);
+					    cmd_mpt->io_request->RaidContext.status);
 			}
 		}
 	}
@@ -3058,18 +3061,19 @@ mrsas_get_ctrl_info(struct mrsas_softc *sc)
  * input:
  *	sc - Controller's softc
 */
-static void mrsas_update_ext_vd_details(struct mrsas_softc *sc)
+static void 
+mrsas_update_ext_vd_details(struct mrsas_softc *sc)
 {
 	sc->max256vdSupport =
-		sc->ctrl_info->adapterOperations3.supportMaxExtLDs;
+	sc->ctrl_info->adapterOperations3.supportMaxExtLDs;
 	/* Below is additional check to address future FW enhancement */
 	if (sc->ctrl_info->max_lds > 64)
 		sc->max256vdSupport = 1;
 
 	sc->drv_supported_vd_count = MRSAS_MAX_LD_CHANNELS
-					* MRSAS_MAX_DEV_PER_CHANNEL;
+	    * MRSAS_MAX_DEV_PER_CHANNEL;
 	sc->drv_supported_pd_count = MRSAS_MAX_PD_CHANNELS
-					* MRSAS_MAX_DEV_PER_CHANNEL;
+	    * MRSAS_MAX_DEV_PER_CHANNEL;
 	if (sc->max256vdSupport) {
 		sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT;
 		sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
@@ -3078,13 +3082,13 @@ static void mrsas_update_ext_vd_details(struct mrsas_softc *sc)
 		sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
 	}
 
-	sc->old_map_sz =  sizeof(MR_FW_RAID_MAP) +
-				(sizeof(MR_LD_SPAN_MAP) *
-				(sc->fw_supported_vd_count - 1));
-	sc->new_map_sz =  sizeof(MR_FW_RAID_MAP_EXT);
-	sc->drv_map_sz =  sizeof(MR_DRV_RAID_MAP) +
-				(sizeof(MR_LD_SPAN_MAP) *
-				(sc->drv_supported_vd_count - 1));
+	sc->old_map_sz = sizeof(MR_FW_RAID_MAP) +
+	    (sizeof(MR_LD_SPAN_MAP) *
+	    (sc->fw_supported_vd_count - 1));
+	sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT);
+	sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP) +
+	    (sizeof(MR_LD_SPAN_MAP) *
+	    (sc->drv_supported_vd_count - 1));
 
 	sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz);
 
@@ -3869,7 +3873,7 @@ mrsas_get_ld_list(struct mrsas_softc *sc)
  * memory is initialized to all zeros upon successful loading of the dma
  * mapped memory.
  */
-int 
+int
 mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc,
     struct mrsas_tmp_dcmd *tcmd, int size)
 {
diff --git a/sys/dev/mrsas/mrsas.h b/sys/dev/mrsas/mrsas.h
index d19c1d9..1cfe89e 100644
--- a/sys/dev/mrsas/mrsas.h
+++ b/sys/dev/mrsas/mrsas.h
@@ -1323,7 +1323,7 @@ typedef enum _MR_SCSI_CMD_TYPE {
 	NON_READ_WRITE_LDIO = 1,
 	READ_WRITE_SYSPDIO = 2,
 	NON_READ_WRITE_SYSPDIO = 3,
-} MR_SCSI_CMD_TYPE;
+}	MR_SCSI_CMD_TYPE;
 
 enum mrsas_req_flags {
 	MRSAS_DIR_UNKNOWN = 0x1,
@@ -1908,27 +1908,27 @@ struct mrsas_ctrl_info {
 	char	reserved6[4];		/* 0x7E4 RESERVED FOR IOV */
 
 	struct {			/* 0x7E8 */
-	u_int32_t     supportPersonalityChange:2;
-	u_int32_t     supportThermalPollInterval:1;
-	u_int32_t     supportDisableImmediateIO:1;
-	u_int32_t     supportT10RebuildAssist:1;
-	u_int32_t     supportMaxExtLDs:1;
-	u_int32_t     supportCrashDump:1;
-	u_int32_t     supportSwZone:1;
-	u_int32_t     supportDebugQueue:1;
-	u_int32_t     supportNVCacheErase:1;
-	u_int32_t     supportForceTo512e:1;
-	u_int32_t     supportHOQRebuild:1;
-	u_int32_t     supportAllowedOpsforDrvRemoval:1;
-	u_int32_t     supportDrvActivityLEDSetting:1;
-	u_int32_t     supportNVDRAM:1;
-	u_int32_t     supportForceFlash:1;
-	u_int32_t     supportDisableSESMonitoring:1;
-	u_int32_t     supportCacheBypassModes:1;
-	u_int32_t     supportSecurityonJBOD:1;
-	u_int32_t     discardCacheDuringLDDelete:1;
-	u_int32_t     reserved:12;
-	} adapterOperations3;
+		u_int32_t supportPersonalityChange:2;
+		u_int32_t supportThermalPollInterval:1;
+		u_int32_t supportDisableImmediateIO:1;
+		u_int32_t supportT10RebuildAssist:1;
+		u_int32_t supportMaxExtLDs:1;
+		u_int32_t supportCrashDump:1;
+		u_int32_t supportSwZone:1;
+		u_int32_t supportDebugQueue:1;
+		u_int32_t supportNVCacheErase:1;
+		u_int32_t supportForceTo512e:1;
+		u_int32_t supportHOQRebuild:1;
+		u_int32_t supportAllowedOpsforDrvRemoval:1;
+		u_int32_t supportDrvActivityLEDSetting:1;
+		u_int32_t supportNVDRAM:1;
+		u_int32_t supportForceFlash:1;
+		u_int32_t supportDisableSESMonitoring:1;
+		u_int32_t supportCacheBypassModes:1;
+		u_int32_t supportSecurityonJBOD:1;
+		u_int32_t discardCacheDuringLDDelete:1;
+		u_int32_t reserved:12;
+	}	adapterOperations3;
 
 	u_int8_t pad[0x800 - 0x7EC];	/* 0x7EC */
 } __packed;
@@ -2002,7 +2002,7 @@ typedef union _MFI_CAPABILITIES {
 		u_int32_t support_core_affinity:1;
 		u_int32_t security_protocol_cmds_fw:1;
 		u_int32_t reserved:25;
-	} mfi_capabilities;
+	}	mfi_capabilities;
 	u_int32_t reg;
 }	MFI_CAPABILITIES;
 
@@ -2444,29 +2444,37 @@ struct mrsas_mgmt_info {
 	int	max_index;
 };
 
-#define PCI_TYPE0_ADDRESSES             6
-#define PCI_TYPE1_ADDRESSES             2
-#define PCI_TYPE2_ADDRESSES             5
-
-typedef struct _MRSAS_DRV_PCI_COMMON_HEADER
-{
-	u_int16_t vendorID;                  // (ro)
-	u_int16_t deviceID;                  // (ro)
-	u_int16_t command;                   // Device control
+#define	PCI_TYPE0_ADDRESSES             6
+#define	PCI_TYPE1_ADDRESSES             2
+#define	PCI_TYPE2_ADDRESSES             5
+
+typedef struct _MRSAS_DRV_PCI_COMMON_HEADER {
+	u_int16_t vendorID;
+	      //(ro)
+	u_int16_t deviceID;
+	      //(ro)
+	u_int16_t command;
+	      //Device control
 	u_int16_t status;
-	u_int8_t revisionID;                 // (ro)
-	u_int8_t progIf;                     // (ro)
-	u_int8_t subClass;                   // (ro)
-	u_int8_t baseClass;                  // (ro)
-	u_int8_t cacheLineSize;              // (ro+)
-	u_int8_t latencyTimer;               // (ro+)
-	u_int8_t headerType;                 // (ro)
-	u_int8_t bist;                       // Built in self test
-
-	union
-	{
-		struct _MRSAS_DRV_PCI_HEADER_TYPE_0
-		{
+	u_int8_t revisionID;
+	      //(ro)
+	u_int8_t progIf;
+	      //(ro)
+	u_int8_t subClass;
+	      //(ro)
+	u_int8_t baseClass;
+	      //(ro)
+	u_int8_t cacheLineSize;
+	      //(ro +)
+	u_int8_t latencyTimer;
+	      //(ro +)
+	u_int8_t headerType;
+	      //(ro)
+	u_int8_t bist;
+	      //Built in self test
+
+	union {
+		struct _MRSAS_DRV_PCI_HEADER_TYPE_0 {
 			u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
 			u_int32_t cis;
 			u_int16_t subVendorID;
@@ -2476,134 +2484,126 @@ typedef struct _MRSAS_DRV_PCI_COMMON_HEADER
 			u_int8_t reserved1[3];
 			u_int32_t reserved2;
 			u_int8_t interruptLine;
-			u_int8_t    interruptPin;       // (ro)
-			u_int8_t    minimumGrant;       // (ro)
-			u_int8_t    maximumLatency;     // (ro)
-		} type0;
-
-        /*
-         * PCI to PCI Bridge
-         */
-
-		struct _MRSAS_DRV_PCI_HEADER_TYPE_1
-		{
-			u_int32_t   baseAddresses[PCI_TYPE1_ADDRESSES];
-			u_int8_t    primaryBus;
-			u_int8_t    secondaryBus;
-			u_int8_t    subordinateBus;
-			u_int8_t    secondaryLatency;
-			u_int8_t    ioBase;
-			u_int8_t    ioLimit;
-			u_int16_t   secondaryStatus;
-			u_int16_t   memoryBase;
-			u_int16_t   memoryLimit;
-			u_int16_t   prefetchBase;
-			u_int16_t   prefetchLimit;
-			u_int32_t   prefetchBaseUpper32;
-			u_int32_t   prefetchLimitUpper32;
-			u_int16_t   ioBaseUpper16;
-			u_int16_t   ioLimitUpper16;
-			u_int8_t    capabilitiesPtr;
-			u_int8_t    reserved1[3];
-			u_int32_t   romBaseAddress;
-			u_int8_t    interruptLine;
-			u_int8_t    interruptPin;
-			u_int16_t   bridgeControl;
-		} type1;
-
-        /*
-         * PCI to CARDBUS Bridge
-         */
-
-		struct _MRSAS_DRV_PCI_HEADER_TYPE_2
-		{
-			u_int32_t   socketRegistersBaseAddress;
-			u_int8_t    capabilitiesPtr;
-			u_int8_t    reserved;
-			u_int16_t   secondaryStatus;
-			u_int8_t    primaryBus;
-			u_int8_t    secondaryBus;
-			u_int8_t    subordinateBus;
-			u_int8_t    secondaryLatency;
-			struct
-			{
-				u_int32_t   base;
-				u_int32_t   limit;
-			}    range[PCI_TYPE2_ADDRESSES-1];
-			u_int8_t   interruptLine;
-			u_int8_t   interruptPin;
-			u_int16_t  bridgeControl;
-		} type2;
-	} u;
-
-} MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
-
-#define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER)   //64 bytes
-
-typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY
-{
-	union
-	{
-		struct
-		{
-			u_int32_t linkSpeed         :4;
-			u_int32_t linkWidth         :6;
-			u_int32_t aspmSupport       :2;
-			u_int32_t losExitLatency    :3;
-			u_int32_t l1ExitLatency     :3;
-			u_int32_t rsvdp             :6;
-			u_int32_t portNumber        :8;
-		}bits;
+			u_int8_t interruptPin;
+			      //(ro)
+			u_int8_t minimumGrant;
+			      //(ro)
+			u_int8_t maximumLatency;
+			      //(ro)
+		}	type0;
+
+		/*
+	         * PCI to PCI Bridge
+	         */
+
+		struct _MRSAS_DRV_PCI_HEADER_TYPE_1 {
+			u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
+			u_int8_t primaryBus;
+			u_int8_t secondaryBus;
+			u_int8_t subordinateBus;
+			u_int8_t secondaryLatency;
+			u_int8_t ioBase;
+			u_int8_t ioLimit;
+			u_int16_t secondaryStatus;
+			u_int16_t memoryBase;
+			u_int16_t memoryLimit;
+			u_int16_t prefetchBase;
+			u_int16_t prefetchLimit;
+			u_int32_t prefetchBaseUpper32;
+			u_int32_t prefetchLimitUpper32;
+			u_int16_t ioBaseUpper16;
+			u_int16_t ioLimitUpper16;
+			u_int8_t capabilitiesPtr;
+			u_int8_t reserved1[3];
+			u_int32_t romBaseAddress;
+			u_int8_t interruptLine;
+			u_int8_t interruptPin;
+			u_int16_t bridgeControl;
+		}	type1;
+
+		/*
+	         * PCI to CARDBUS Bridge
+	         */
+
+		struct _MRSAS_DRV_PCI_HEADER_TYPE_2 {
+			u_int32_t socketRegistersBaseAddress;
+			u_int8_t capabilitiesPtr;
+			u_int8_t reserved;
+			u_int16_t secondaryStatus;
+			u_int8_t primaryBus;
+			u_int8_t secondaryBus;
+			u_int8_t subordinateBus;
+			u_int8_t secondaryLatency;
+			struct {
+				u_int32_t base;
+				u_int32_t limit;
+			}	range [PCI_TYPE2_ADDRESSES - 1];
+			u_int8_t interruptLine;
+			u_int8_t interruptPin;
+			u_int16_t bridgeControl;
+		}	type2;
+	}	u;
+
+}	MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
+
+#define	MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER)   //64 bytes
+
+typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
+	union {
+		struct {
+			u_int32_t linkSpeed:4;
+			u_int32_t linkWidth:6;
+			u_int32_t aspmSupport:2;
+			u_int32_t losExitLatency:3;
+			u_int32_t l1ExitLatency:3;
+			u_int32_t rsvdp:6;
+			u_int32_t portNumber:8;
+		}	bits;
 
 		u_int32_t asUlong;
-	}u;
-}MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
+	}	u;
+}	MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
 
-#define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
+#define	MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
 
-typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY
-{
-	union
-	{
-		struct
-		{
-			u_int16_t linkSpeed             :4;
-			u_int16_t negotiatedLinkWidth   :6;
-			u_int16_t linkTrainingError     :1;
-			u_int16_t linkTraning           :1;
-			u_int16_t slotClockConfig       :1;
-			u_int16_t rsvdZ                  :3;
-		}bits;
+typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY {
+	union {
+		struct {
+			u_int16_t linkSpeed:4;
+			u_int16_t negotiatedLinkWidth:6;
+			u_int16_t linkTrainingError:1;
+			u_int16_t linkTraning:1;
+			u_int16_t slotClockConfig:1;
+			u_int16_t rsvdZ:3;
+		}	bits;
 
 		u_int16_t asUshort;
-	}u;
+	}	u;
 	u_int16_t reserved;
-} MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
+}	MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
 
-#define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
+#define	MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
 
 
-typedef struct _MRSAS_DRV_PCI_CAPABILITIES
-{
-	MRSAS_DRV_PCI_LINK_CAPABILITY         linkCapability;
-	MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY  linkStatusCapability;
-}MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
+typedef struct _MRSAS_DRV_PCI_CAPABILITIES {
+	MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
+	MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
+}	MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
 
-#define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
+#define	MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
 
 /* PCI information */
-typedef struct _MRSAS_DRV_PCI_INFORMATION
-{
-	u_int32_t	busNumber;
-	u_int8_t	deviceNumber;
-	u_int8_t	functionNumber;
-	u_int8_t	interruptVector;
-	u_int8_t	reserved1;
-	MRSAS_DRV_PCI_COMMON_HEADER	pciHeaderInfo;
-	MRSAS_DRV_PCI_CAPABILITIES	capability;
-	u_int32_t	domainID;
-	u_int8_t	reserved2[28];
-}MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
+typedef struct _MRSAS_DRV_PCI_INFORMATION {
+	u_int32_t busNumber;
+	u_int8_t deviceNumber;
+	u_int8_t functionNumber;
+	u_int8_t interruptVector;
+	u_int8_t reserved1;
+	MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
+	MRSAS_DRV_PCI_CAPABILITIES capability;
+	u_int32_t domainID;
+	u_int8_t reserved2[28];
+}	MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
 
 /*******************************************************************
  * per-instance data
@@ -2668,7 +2668,7 @@ struct mrsas_softc {
 	int	msix_vectors;
 	int	msix_enable;
 	uint32_t msix_reg_offset[16];
-	uint8_t mask_interrupts;
+	uint8_t	mask_interrupts;
 	struct mrsas_mpt_cmd **mpt_cmd_list;
 	struct mrsas_mfi_cmd **mfi_cmd_list;
 	TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
@@ -2740,7 +2740,7 @@ struct mrsas_softc {
 	struct task ev_task;
 	u_int32_t CurLdCount;
 	u_int64_t reset_flags;
-	int lb_pending_cmds;
+	int	lb_pending_cmds;
 	LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
 	LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
 
diff --git a/sys/dev/mrsas/mrsas_cam.c b/sys/dev/mrsas/mrsas_cam.c
index 69d1bfd..08f9002 100644
--- a/sys/dev/mrsas/mrsas_cam.c
+++ b/sys/dev/mrsas/mrsas_cam.c
@@ -58,18 +58,19 @@ __FBSDID("$FreeBSD$");
  * Function prototypes
  */
 int	mrsas_cam_attach(struct mrsas_softc *sc);
-int mrsas_find_io_type(struct cam_sim *sim, union ccb *ccb);
+int	mrsas_find_io_type(struct cam_sim *sim, union ccb *ccb);
 int	mrsas_bus_scan(struct mrsas_softc *sc);
 int	mrsas_bus_scan_sim(struct mrsas_softc *sc, struct cam_sim *sim);
-int mrsas_map_request(struct mrsas_softc *sc,
-		struct mrsas_mpt_cmd *cmd, union ccb *ccb);
 int 
+mrsas_map_request(struct mrsas_softc *sc,
+    struct mrsas_mpt_cmd *cmd, union ccb *ccb);
+int
 mrsas_build_ldio(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
     union ccb *ccb);
-int 
+int
 mrsas_build_dcdb(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
     union ccb *ccb, struct cam_sim *sim);
-int 
+int
 mrsas_setup_io(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
     union ccb *ccb, u_int32_t device_id,
     MRSAS_RAID_SCSI_IO_REQUEST * io_request);
@@ -79,10 +80,10 @@ void	mrsas_cam_detach(struct mrsas_softc *sc);
 void	mrsas_release_mpt_cmd(struct mrsas_mpt_cmd *cmd);
 void	mrsas_unmap_request(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd);
 void	mrsas_cmd_done(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd);
-void 
+void
 mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
     u_int32_t req_desc_hi);
-void 
+void
 mrsas_set_pd_lba(MRSAS_RAID_SCSI_IO_REQUEST * io_request,
     u_int8_t cdb_len, struct IO_REQUEST_INFO *io_info, union ccb *ccb,
     MR_DRV_RAID_MAP_ALL * local_map_ptr, u_int32_t ref_tag,
@@ -91,10 +92,10 @@ static void mrsas_freeze_simq(struct mrsas_mpt_cmd *cmd, struct cam_sim *sim);
 static void mrsas_cam_poll(struct cam_sim *sim);
 static void mrsas_action(struct cam_sim *sim, union ccb *ccb);
 static void mrsas_scsiio_timeout(void *data);
-static void 
+static void
 mrsas_data_load_cb(void *arg, bus_dma_segment_t *segs,
     int nseg, int error);
-static int32_t 
+static int32_t
 mrsas_startio(struct mrsas_softc *sc, struct cam_sim *sim,
     union ccb *ccb);
 struct mrsas_mpt_cmd *mrsas_get_mpt_cmd(struct mrsas_softc *sc);
@@ -114,8 +115,9 @@ MR_BuildRaidContext(struct mrsas_softc *sc,
 extern u_int16_t
 MR_LdSpanArrayGet(u_int32_t ld, u_int32_t span,
     MR_DRV_RAID_MAP_ALL * map);
-extern u_int16_t mrsas_get_updated_dev_handle(struct mrsas_softc *sc,
-		PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info);
+extern u_int16_t 
+mrsas_get_updated_dev_handle(struct mrsas_softc *sc,
+    PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info);
 extern u_int8_t
 megasas_get_best_arm(PLD_LOAD_BALANCE_INFO lbInfo, u_int8_t arm,
     u_int64_t block, u_int32_t count);
@@ -385,10 +387,10 @@ mrsas_scsiio_timeout(void *data)
 	 */
 #if (__FreeBSD_version >= 1000510)
 	callout_reset_sbt(&cmd->cm_callout, SBT_1S * 600, 0,
-							mrsas_scsiio_timeout, cmd, 0);
+	    mrsas_scsiio_timeout, cmd, 0);
 #else
 	callout_reset(&cmd->cm_callout, (600000 * hz) / 1000,
-							mrsas_scsiio_timeout, cmd);
+	    mrsas_scsiio_timeout, cmd);
 #endif
 	sc->do_timedout_reset = 1;
 	if (sc->ocr_thread_active)
@@ -549,10 +551,10 @@ mrsas_startio(struct mrsas_softc *sc, struct cam_sim *sim,
 	 */
 #if (__FreeBSD_version >= 1000510)
 	callout_reset_sbt(&cmd->cm_callout, SBT_1S * 600, 0,
-							mrsas_scsiio_timeout, cmd, 0);
+	    mrsas_scsiio_timeout, cmd, 0);
 #else
 	callout_reset(&cmd->cm_callout, (600000 * hz) / 1000,
-							mrsas_scsiio_timeout, cmd);
+	    mrsas_scsiio_timeout, cmd);
 #endif
 	mrsas_atomic_inc(&sc->fw_outstanding);
 
@@ -574,7 +576,8 @@ done:
  * This function determines if the IO is read/write or inquiry.  It returns a 1
  * if the IO is read/write and 0 if it is inquiry.
  */
-int mrsas_find_io_type(struct cam_sim *sim, union ccb *ccb)
+int 
+mrsas_find_io_type(struct cam_sim *sim, union ccb *ccb)
 {
 	struct ccb_scsiio *csio = &(ccb->csio);
 
@@ -588,10 +591,10 @@ int mrsas_find_io_type(struct cam_sim *sim, union ccb *ccb)
 	case READ_16:
 	case WRITE_16:
 		return (cam_sim_bus(sim) ?
-				READ_WRITE_SYSPDIO : READ_WRITE_LDIO);
+		    READ_WRITE_SYSPDIO : READ_WRITE_LDIO);
 	default:
 		return (cam_sim_bus(sim) ?
-				NON_READ_WRITE_SYSPDIO : NON_READ_WRITE_LDIO);
+		    NON_READ_WRITE_SYSPDIO : NON_READ_WRITE_LDIO);
 	}
 }
 
@@ -844,8 +847,8 @@ mrsas_setup_io(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
 		if ((sc->load_balance_info[device_id].loadBalanceFlag) &&
 		    (io_info.isRead)) {
 			io_info.devHandle =
-				mrsas_get_updated_dev_handle(sc,
-					&sc->load_balance_info[device_id], &io_info);
+			    mrsas_get_updated_dev_handle(sc,
+			    &sc->load_balance_info[device_id], &io_info);
 			cmd->load_balance = MRSAS_LOAD_BALANCE_FLAG;
 			cmd->pd_r1_lb = io_info.pd_after_lb;
 		} else
@@ -897,27 +900,27 @@ mrsas_build_dcdb(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
 	device_id = ccb_h->target_id;
 	map_ptr = sc->ld_drv_map[(sc->map_id & 1)];
 
-    /*
-     * Check if this is RW for system PD or
-     * it's a NON RW for sys PD and there is NO secure jbod FW support
-     */
+	/*
+         * Check if this is RW for system PD or
+         * it's a NON RW for sys PD and there is NO secure jbod FW support
+         */
 	if (cam_sim_bus(sim) == 1 &&
-		sc->pd_list[device_id].driveState == MR_PD_STATE_SYSTEM){
+	    sc->pd_list[device_id].driveState == MR_PD_STATE_SYSTEM) {
 
 		io_request->DevHandle =
-			map_ptr->raidMap.devHndlInfo[device_id].curDevHdl;
+		    map_ptr->raidMap.devHndlInfo[device_id].curDevHdl;
 		io_request->RaidContext.RAIDFlags =
-				MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD <<
-				MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT;
+		    MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD <<
+		    MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT;
 		cmd->request_desc->SCSIIO.DevHandle = io_request->DevHandle;
 		cmd->request_desc->SCSIIO.MSIxIndex =
-				sc->msix_vectors ? smp_processor_id() % sc->msix_vectors : 0;
+		    sc->msix_vectors ? smp_processor_id() % sc->msix_vectors : 0;
 
-		if(sc->secure_jbod_support && (mrsas_find_io_type(sim, ccb) == NON_READ_WRITE_SYSPDIO)) {
+		if (sc->secure_jbod_support && (mrsas_find_io_type(sim, ccb) == NON_READ_WRITE_SYSPDIO)) {
 			/* system pd firmware path */
-			io_request->Function  = MRSAS_MPI2_FUNCTION_LD_IO_REQUEST;
+			io_request->Function = MRSAS_MPI2_FUNCTION_LD_IO_REQUEST;
 			cmd->request_desc->SCSIIO.RequestFlags =
-			(MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
+			    (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
 		} else {
 			/* system pd fast path */
 			io_request->Function = MPI2_FUNCTION_SCSI_IO_REQUEST;
@@ -927,8 +930,8 @@ mrsas_build_dcdb(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
 			io_request->RaidContext.regLockLength = 0;
 
 			cmd->request_desc->SCSIIO.RequestFlags =
-				(MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY <<
-				MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
+			    (MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY <<
+			    MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
 
 			/*
 			 * NOTE - For system pd RW cmds only IoFlags will be FAST_PATH
@@ -937,14 +940,14 @@ mrsas_build_dcdb(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
 			 */
 			if ((sc->device_id == MRSAS_INVADER) || (sc->device_id == MRSAS_FURY))
 				io_request->IoFlags |= MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH;
-			}
+		}
 	} else {
-		/* FW path for SysPD or LD Non-RW (SCSI management commands)*/
-		io_request->Function  = MRSAS_MPI2_FUNCTION_LD_IO_REQUEST;
+		/* FW path for SysPD or LD Non-RW (SCSI management commands) */
+		io_request->Function = MRSAS_MPI2_FUNCTION_LD_IO_REQUEST;
 		io_request->DevHandle = device_id;
 		cmd->request_desc->SCSIIO.RequestFlags =
-			(MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO <<
-			MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
+		    (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO <<
+		    MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
 	}
 
 	io_request->RaidContext.VirtualDiskTgtId = device_id;
@@ -974,8 +977,9 @@ mrsas_build_dcdb(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd,
  * is built in the callback.  If the  bus dmamap load is not successful,
  * cmd->error_code will contain the  error code and a 1 is returned.
  */
-int mrsas_map_request(struct mrsas_softc *sc,
-		struct mrsas_mpt_cmd *cmd, union ccb *ccb)
+int 
+mrsas_map_request(struct mrsas_softc *sc,
+    struct mrsas_mpt_cmd *cmd, union ccb *ccb)
 {
 	u_int32_t retcode = 0;
 	struct cam_sim *sim;
@@ -987,10 +991,10 @@ int mrsas_map_request(struct mrsas_softc *sc,
 		mtx_lock(&sc->io_lock);
 #if (__FreeBSD_version >= 902001)
 		retcode = bus_dmamap_load_ccb(sc->data_tag, cmd->data_dmamap, ccb,
-						mrsas_data_load_cb, cmd, 0);
+		    mrsas_data_load_cb, cmd, 0);
 #else
 		retcode = bus_dmamap_load(sc->data_tag, cmd->data_dmamap, cmd->data,
-						cmd->length, mrsas_data_load_cb, cmd, BUS_DMA_NOWAIT);
+		    cmd->length, mrsas_data_load_cb, cmd, BUS_DMA_NOWAIT);
 #endif
 		mtx_unlock(&sc->io_lock);
 		if (retcode)
diff --git a/sys/dev/mrsas/mrsas_fp.c b/sys/dev/mrsas/mrsas_fp.c
index ff52dc6..7ae5662 100644
--- a/sys/dev/mrsas/mrsas_fp.c
+++ b/sys/dev/mrsas/mrsas_fp.c
@@ -55,13 +55,14 @@ __FBSDID("$FreeBSD$");
  * Function prototypes
  */
 u_int8_t MR_ValidateMapInfo(struct mrsas_softc *sc);
-u_int8_t mrsas_get_best_arm_pd(struct mrsas_softc *sc,
-		PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info);
 u_int8_t 
+mrsas_get_best_arm_pd(struct mrsas_softc *sc,
+    PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info);
+u_int8_t
 MR_BuildRaidContext(struct mrsas_softc *sc,
     struct IO_REQUEST_INFO *io_info,
     RAID_CONTEXT * pRAID_Context, MR_DRV_RAID_MAP_ALL * map);
-u_int8_t 
+u_int8_t
 MR_GetPhyParams(struct mrsas_softc *sc, u_int32_t ld,
     u_int64_t stripRow, u_int16_t stripRef, struct IO_REQUEST_INFO *io_info,
     RAID_CONTEXT * pRAID_Context,
@@ -69,31 +70,33 @@ MR_GetPhyParams(struct mrsas_softc *sc, u_int32_t ld,
 u_int16_t MR_TargetIdToLdGet(u_int32_t ldTgtId, MR_DRV_RAID_MAP_ALL * map);
 u_int32_t MR_LdBlockSizeGet(u_int32_t ldTgtId, MR_DRV_RAID_MAP_ALL * map);
 u_int16_t MR_GetLDTgtId(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map);
-u_int16_t mrsas_get_updated_dev_handle(struct mrsas_softc *sc,
-		PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info);
+u_int16_t 
+mrsas_get_updated_dev_handle(struct mrsas_softc *sc,
+    PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info);
 u_int32_t mega_mod64(u_int64_t dividend, u_int32_t divisor);
-u_int32_t 
+u_int32_t
 MR_GetSpanBlock(u_int32_t ld, u_int64_t row, u_int64_t *span_blk,
     MR_DRV_RAID_MAP_ALL * map, int *div_error);
 u_int64_t mega_div64_32(u_int64_t dividend, u_int32_t divisor);
-void mrsas_update_load_balance_params(struct mrsas_softc *sc,
-		MR_DRV_RAID_MAP_ALL *map, PLD_LOAD_BALANCE_INFO lbInfo);
 void 
+mrsas_update_load_balance_params(struct mrsas_softc *sc,
+    MR_DRV_RAID_MAP_ALL * map, PLD_LOAD_BALANCE_INFO lbInfo);
+void
 mrsas_set_pd_lba(MRSAS_RAID_SCSI_IO_REQUEST * io_request,
     u_int8_t cdb_len, struct IO_REQUEST_INFO *io_info, union ccb *ccb,
     MR_DRV_RAID_MAP_ALL * local_map_ptr, u_int32_t ref_tag,
     u_int32_t ld_block_size);
-static u_int16_t 
+static u_int16_t
 MR_LdSpanArrayGet(u_int32_t ld, u_int32_t span,
     MR_DRV_RAID_MAP_ALL * map);
 static u_int16_t MR_PdDevHandleGet(u_int32_t pd, MR_DRV_RAID_MAP_ALL * map);
-static u_int16_t 
+static u_int16_t
 MR_ArPdGet(u_int32_t ar, u_int32_t arm,
     MR_DRV_RAID_MAP_ALL * map);
 static MR_LD_SPAN *
 MR_LdSpanPtrGet(u_int32_t ld, u_int32_t span,
     MR_DRV_RAID_MAP_ALL * map);
-static u_int8_t 
+static u_int8_t
 MR_LdDataArmGet(u_int32_t ld, u_int32_t armIdx,
     MR_DRV_RAID_MAP_ALL * map);
 static MR_SPAN_BLOCK_INFO *
@@ -144,7 +147,7 @@ typedef u_int32_t REGION_LEN;
 #define	FALSE					0
 #define	TRUE					1
 
-#define LB_PENDING_CMDS_DEFAULT 4
+#define	LB_PENDING_CMDS_DEFAULT 4
 
 
 /*
@@ -1107,16 +1110,16 @@ mr_update_span_set(MR_DRV_RAID_MAP_ALL * map, PLD_SPAN_INFO ldSpanInfo)
  * This function updates the load balance parameters for the LD config of a two
  * drive optimal RAID-1.
  */
-void 
+void
 mrsas_update_load_balance_params(struct mrsas_softc *sc,
-	MR_DRV_RAID_MAP_ALL * drv_map, PLD_LOAD_BALANCE_INFO lbInfo)
+    MR_DRV_RAID_MAP_ALL * drv_map, PLD_LOAD_BALANCE_INFO lbInfo)
 {
 	int ldCount;
 	u_int16_t ld;
 	MR_LD_RAID *raid;
 
-	if(sc->lb_pending_cmds > 128 || sc->lb_pending_cmds < 1)
-			sc-> lb_pending_cmds = LB_PENDING_CMDS_DEFAULT;
+	if (sc->lb_pending_cmds > 128 || sc->lb_pending_cmds < 1)
+		sc->lb_pending_cmds = LB_PENDING_CMDS_DEFAULT;
 
 	for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) {
 		ld = MR_TargetIdToLdGet(ldCount, drv_map);
@@ -1124,10 +1127,9 @@ mrsas_update_load_balance_params(struct mrsas_softc *sc,
 			lbInfo[ldCount].loadBalanceFlag = 0;
 			continue;
 		}
-
 		raid = MR_LdRaidGet(ld, drv_map);
 		if ((raid->level != 1) ||
-			(raid->ldState != MR_LD_STATE_OPTIMAL)) {
+		    (raid->ldState != MR_LD_STATE_OPTIMAL)) {
 			lbInfo[ldCount].loadBalanceFlag = 0;
 			continue;
 		}
@@ -1147,7 +1149,7 @@ mrsas_update_load_balance_params(struct mrsas_softc *sc,
  *
  * Used to set the PD logical block address in CDB for FP IOs.
  */
-void 
+void
 mrsas_set_pd_lba(MRSAS_RAID_SCSI_IO_REQUEST * io_request, u_int8_t cdb_len,
     struct IO_REQUEST_INFO *io_info, union ccb *ccb,
     MR_DRV_RAID_MAP_ALL * local_map_ptr, u_int32_t ref_tag,
@@ -1294,6 +1296,7 @@ mrsas_set_pd_lba(MRSAS_RAID_SCSI_IO_REQUEST * io_request, u_int8_t cdb_len,
 		}
 		/* Fall through normal case, just load LBA here */
 		u_int8_t val = cdb[1] & 0xE0;
+
 		switch (cdb_len) {
 		case 6:
 			cdb[3] = (u_int8_t)(start_blk & 0xff);
@@ -1336,10 +1339,11 @@ mrsas_set_pd_lba(MRSAS_RAID_SCSI_IO_REQUEST * io_request, u_int8_t cdb_len,
  * This function determines and returns the best arm by looking at the
  * parameters of the last PD access.
  */
-u_int8_t mrsas_get_best_arm_pd(struct mrsas_softc *sc,
-		PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info)
+u_int8_t 
+mrsas_get_best_arm_pd(struct mrsas_softc *sc,
+    PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info)
 {
-	MR_LD_RAID  *raid;
+	MR_LD_RAID *raid;
 	MR_DRV_RAID_MAP_ALL *drv_map;
 	u_int16_t pend0, pend1, ld;
 	u_int64_t diff0, diff1;
@@ -1350,19 +1354,19 @@ u_int8_t mrsas_get_best_arm_pd(struct mrsas_softc *sc,
 	u_int32_t count = io_info->numBlocks;
 
 	span = ((io_info->span_arm & RAID_CTX_SPANARM_SPAN_MASK)
-				>> RAID_CTX_SPANARM_SPAN_SHIFT);
+	    >> RAID_CTX_SPANARM_SPAN_SHIFT);
 	arm = (io_info->span_arm & RAID_CTX_SPANARM_ARM_MASK);
 
 	drv_map = sc->ld_drv_map[(sc->map_id & 1)];
 	ld = MR_TargetIdToLdGet(io_info->ldTgtId, drv_map);
 	raid = MR_LdRaidGet(ld, drv_map);
 	span_row_size = sc->UnevenSpanSupport ?
-				SPAN_ROW_SIZE(drv_map, ld, span) : raid->rowSize;
+	    SPAN_ROW_SIZE(drv_map, ld, span) : raid->rowSize;
 
-		arRef = MR_LdSpanArrayGet(ld, span, drv_map);
-		pd0 = MR_ArPdGet(arRef, arm, drv_map);
-		pd1 = MR_ArPdGet(arRef, (arm + 1) >= span_row_size ?
-				(arm + 1 - span_row_size): arm + 1, drv_map);
+	arRef = MR_LdSpanArrayGet(ld, span, drv_map);
+	pd0 = MR_ArPdGet(arRef, arm, drv_map);
+	pd1 = MR_ArPdGet(arRef, (arm + 1) >= span_row_size ?
+	    (arm + 1 - span_row_size) : arm + 1, drv_map);
 
 	/* get the pending cmds for the data and mirror arms */
 	pend0 = mrsas_atomic_read(&lbInfo->scsi_pending_cmds[pd0]);
@@ -1374,18 +1378,18 @@ u_int8_t mrsas_get_best_arm_pd(struct mrsas_softc *sc,
 	bestArm = (diff0 <= diff1 ? arm : arm ^ 1);
 
 	if ((bestArm == arm && pend0 > pend1 + sc->lb_pending_cmds) ||
-			(bestArm != arm && pend1 > pend0 + sc->lb_pending_cmds))
+	    (bestArm != arm && pend1 > pend0 + sc->lb_pending_cmds))
 		bestArm ^= 1;
 
 	/* Update the last accessed block on the correct pd */
-	lbInfo->last_accessed_block[bestArm==arm ? pd0 : pd1] = block + count - 1;
+	lbInfo->last_accessed_block[bestArm == arm ? pd0 : pd1] = block + count - 1;
 	io_info->span_arm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | bestArm;
-	io_info->pd_after_lb = (bestArm == arm) ? pd0:pd1;
+	io_info->pd_after_lb = (bestArm == arm) ? pd0 : pd1;
 #if SPAN_DEBUG
-	if(arm != bestArm)
-	printf("AVAGO Debug R1 Load balance occur - span 0x%x arm 0x%x bestArm 0x%x "
-			"io_info->span_arm 0x%x\n",
-			span, arm, bestArm, io_info->span_arm);
+	if (arm != bestArm)
+		printf("AVAGO Debug R1 Load balance occur - span 0x%x arm 0x%x bestArm 0x%x "
+		    "io_info->span_arm 0x%x\n",
+		    span, arm, bestArm, io_info->span_arm);
 #endif
 
 	return io_info->pd_after_lb;
@@ -1400,8 +1404,9 @@ u_int8_t mrsas_get_best_arm_pd(struct mrsas_softc *sc,
  *
  * This function determines and returns the updated dev handle.
  */
-u_int16_t mrsas_get_updated_dev_handle(struct mrsas_softc *sc,
-			PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info)
+u_int16_t 
+mrsas_get_updated_dev_handle(struct mrsas_softc *sc,
+    PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info)
 {
 	u_int8_t arm_pd;
 	u_int16_t devHandle;
@@ -1410,7 +1415,7 @@ u_int16_t mrsas_get_updated_dev_handle(struct mrsas_softc *sc,
 	drv_map = sc->ld_drv_map[(sc->map_id & 1)];
 
 	/* get best new arm */
-	arm_pd  = mrsas_get_best_arm_pd(sc, lbInfo, io_info);
+	arm_pd = mrsas_get_best_arm_pd(sc, lbInfo, io_info);
 	devHandle = MR_PdDevHandleGet(arm_pd, drv_map);
 	mrsas_atomic_inc(&lbInfo->scsi_pending_cmds[arm_pd]);
 
diff --git a/sys/dev/mrsas/mrsas_ioctl.c b/sys/dev/mrsas/mrsas_ioctl.c
index 58cd641..3c4dbf9 100644
--- a/sys/dev/mrsas/mrsas_ioctl.c
+++ b/sys/dev/mrsas/mrsas_ioctl.c
@@ -305,7 +305,6 @@ out:
 		if (ioctl_sense_tag != NULL)
 			bus_dma_tag_destroy(ioctl_sense_tag);
 	}
-
 	/*
 	 * Release data buffers
 	 */
diff --git a/sys/dev/mrsas/mrsas_ioctl.h b/sys/dev/mrsas/mrsas_ioctl.h
index 3f378e7..c43fc6d 100644
--- a/sys/dev/mrsas/mrsas_ioctl.h
+++ b/sys/dev/mrsas/mrsas_ioctl.h
@@ -65,7 +65,7 @@ __FBSDID("$FreeBSD$");
  * into a somewhat unique, 32-bit value.
  */
 
-#define MRSAS_IOC_GET_PCI_INFO				_IOR('M', 7, MRSAS_DRV_PCI_INFORMATION)
+#define	MRSAS_IOC_GET_PCI_INFO				_IOR('M', 7, MRSAS_DRV_PCI_INFORMATION)
 #define	MRSAS_IOC_FIRMWARE_PASS_THROUGH64	_IOWR('M', 1, struct mrsas_iocpacket)
 #ifdef COMPAT_FREEBSD32
 #define	MRSAS_IOC_FIRMWARE_PASS_THROUGH32	_IOWR('M', 1, struct mrsas_iocpacket32)