This commit adds driver support for PCI fast ethernet cards based on the

ADMtek AL981 "Comet" chipset. The AL981 is yet another DEC tulip clone,
except with simpler receive filter options. The AL981 has a built-in
transceiver, power management support, wake on LAN and flow control.
This chip performs extremely well; it's on par with the ASIX chipset
in terms of speed, which is pretty good (it can do 11.5MB/sec with TCP
easily).

I would have committed this driver sooner, except I ran into one problem
with the AL981 that required a workaround. When the chip is transmitting
at full speed, it will sometimes wedge if you queue a series of packets
that wrap from the end of the transmit descriptor list back to the
beginning. I can't explain why this happens, and none of the other tulip
clones behave this way. The workaround this is to just watch for the end
of the transmit ring and make sure that al_start() breaks out of its
packet queuing loop and waiting until the current batch of transmissions
completes before wrapping back to the start of the ring. Fortunately, this
does not significantly impact transmit performance.

This is one of those things that takes weeks of analysis just to come
up with two or three lines of code changes.

17 files changed, 3056 insertions, 13 deletions

diff --git a/release/sysinstall/devices.c b/release/sysinstall/devices.c
index bf4af72..be7a729 100644
--- a/release/sysinstall/devices.c
+++ b/release/sysinstall/devices.c
@@ -4,7 +4,7 @@
  * This is probably the last program in the `sysinstall' line - the next
  * generation being essentially a complete rewrite.
  *
- * $Id: devices.c,v 1.89 1999/04/06 08:25:52 jkh Exp $
+ * $Id: devices.c,v 1.90 1999/04/06 17:08:29 wpaul Exp $
  *
  * Copyright (c) 1995
  *	Jordan Hubbard.  All rights reserved.
@@ -80,6 +80,7 @@ static struct _devname {
     { DEVICE_TYPE_FLOPPY,	"fd%d",		"floppy drive unit A",	2, 0, 64, 4, 'b'			},
     { DEVICE_TYPE_FLOPPY,	"wfd%d",	"ATAPI floppy drive unit A",	1, 0, 8, 4, 'b'			},
     { DEVICE_TYPE_FLOPPY,	"worm%d",	"SCSI optical disk / CDR",	23, 0, 1, 4, 'b'		},
+    { DEVICE_TYPE_NETWORK,	"al",		"ADMtek AL981 PCI ethernet card"				},
     { DEVICE_TYPE_NETWORK,	"ax",		"ASIX AX88140A PCI ethernet card"				},
     { DEVICE_TYPE_NETWORK,	"fpa",		"DEC DEFPA PCI FDDI card"					},
     { DEVICE_TYPE_NETWORK,	"sr",		"SDL T1/E1 sync serial PCI card"				},
diff --git a/release/texts/HARDWARE.TXT b/release/texts/HARDWARE.TXT
index b2a629e..08542a9 100644
--- a/release/texts/HARDWARE.TXT
+++ b/release/texts/HARDWARE.TXT
@@ -86,6 +86,7 @@ sio1    2f8     3       n/a     n/a     Serial Port 1 (COM2)
 lpt0    dyn     7       n/a     n/a     Printer Port 0
 lpt1    dyn     dyn     n/a     n/a     Printer Port 1
 
+al0     dyn     dyn     n/a     dyn     ADMtek AL981 PCI based cards
 ax0     dyn     dyn     n/a     dyn     ASIX AX88140A PCI based cards
 de0     n/a     n/a     n/a     n/a     DEC DC21x40 PCI based cards
                                         (including 21140 100bT cards)
@@ -454,6 +455,7 @@ Lite-On 82c168/82c169 PNIC fast ethernet NICs including the following:
   LinkSys EtherFast LNE100TX
   NetGear FA310-TX Rev. D1
   Matrox FastNIC 10/100
+  Kingston KNE110TX
 
 Macronix 98713, 98713A, 98715, 98715A and 98725 fast ethernet NICs
   NDC Communications SFA100A (98713A)
@@ -477,6 +479,8 @@ Texas Instruments ThunderLAN PCI NICs, including the following:
   Racore 8165 10/100baseTX
   Racore 8148 10baseT/100baseTX/100baseFX multi-personality
 
+ADMtek AL981-based PCI fast ethernet NICs
+
 ASIX Electronics AX88140A PCI NICs, including the following:
   Alfa Inc. GFC2204
   CNet Pro110B
diff --git a/release/texts/RELNOTES.TXT b/release/texts/RELNOTES.TXT
index c32498f..334e8c3 100644
--- a/release/texts/RELNOTES.TXT
+++ b/release/texts/RELNOTES.TXT
@@ -68,6 +68,9 @@ Driver support has been added for IEEE 802.11 PCMCIA wireless network
 adapters based on the Lucent Hermes chipset, including the Lucent
 WaveLAN/IEEE 802.11 and the Cabletron RoamAbout.
 
+Driver support has been added for PCI fast ethernet cards based
+on the ADMtek Inc. AL981 Comet chipset.
+
 1.2. SECURITY FIXES
 -------------------
 A new jail(2) system call and admin command (jail(8)) have been added for
@@ -244,6 +247,7 @@ Lite-On 82c168/82c169 PNIC fast ethernet NICs including the following:
   LinkSys EtherFast LNE100TX
   NetGear FA310-TX Rev. D1
   Matrox FastNIC 10/100
+  Kingston KNE110TX
 
 Macronix 98713, 98713A, 98715, 98715A and 98725 fast ethernet NICs
   NDC Communications SFA100A (98713A)
@@ -267,6 +271,8 @@ Texas Instruments ThunderLAN PCI NICs, including the following:
   Racore 8165 10/100baseTX
   Racore 8148 10baseT/100baseTX/100baseFX multi-personality
 
+ADMtek Inc. AL981-based PCI fast ethernet NICs
+
 ASIX Electronics AX88140A PCI NICs, including the following:
   Alfa Inc. GFC2204
   CNet Pro110B
diff --git a/share/man/man4/al.4 b/share/man/man4/al.4
new file mode 100644
index 0000000..062e7a2
--- /dev/null
+++ b/share/man/man4/al.4
@@ -0,0 +1,152 @@
+.\" Copyright (c) 1997, 1998, 1999
+.\"	Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\" 3. All advertising materials mentioning features or use of this software
+.\"    must display the following acknowledgement:
+.\"	This product includes software developed by Bill Paul.
+.\" 4. Neither the name of the author nor the names of any co-contributors
+.\"    may be used to endorse or promote products derived from this software
+.\"   without specific prior written permission.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+.\" THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.\"	$Id$
+.\"
+.Dd May 20, 1999
+.Dt AL 4 i386
+.Os FreeBSD
+.Sh NAME
+.Nm al
+.Nd
+ADMtek Inc. AL981 Comet fast ethernet device driver
+.Sh SYNOPSIS
+.Cd "device al0"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for PCI ethernet adapters and embedded
+controllers based on the ADMtek Inc. AL981 Comet fast ethernet
+controller chip.
+.Pp
+The ADMtek chip uses bus master DMA and is designed to be a
+DEC 21x4x workalike. The only major difference between the DEC
+and ADMtek parts is that the AL981 receiver filter is programmed
+using two special registers where as the DEC chip is programmed
+by uploading a special setup frame via the transmit DMA engine.
+The AL981 receive filter can only be programmed with a single
+perfect filter entry for the local station address and a 64-bit
+multicast hash table; the DEC filter has supports several other
+options. The ADMtek fast ethernet controller supports both
+10 and 100Mbps speeds in either full or half duplex using
+an internal MII transceiver.
+.Pp
+The
+.Nm
+driver supports the following media types:
+.Pp
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It autoselect
+Enable autoselection of the media type and options.
+The user can manually override
+the autoselected mode by adding media options to the
+.Pa /etc/rc.conf
+fine.
+.It 10baseT/UTP
+Set 10Mbps operation. The
+.Ar mediaopt
+option can also be used to select either
+.Ar full-duplex
+or
+.Ar half-duplex modes.
+.It 100baseTX
+Set 100Mbps (fast ethernet) operation. The
+.Ar mediaopt
+option can also be used to select either
+.Ar full-duplex
+or
+.Ar half-duplex
+modes.
+.El
+.Pp
+The
+.Nm
+driver supports the following media options:
+.Pp
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It full-duplex
+Force full duplex operation
+.It half-duplex
+Force half duplex operation.
+.El
+.Pp
+For more information on configuring this device, see
+.Xr ifconfig 8 .
+.Sh DIAGNOSTICS
+.Bl -diag
+.It "ax%d: couldn't map memory"
+A fatal initialization error has occurred.
+.It "ax%d: couldn't map interrupt"
+A fatal initialization error has occurred.
+.It "ax%d: watchdog timeout"
+The device has stopped responding to the network, or there is a problem with
+the network connection (cable).
+.It "ax%d: no memory for rx list"
+The driver failed to allocate an mbuf for the receiver ring.
+.It "ax%d: no memory for tx list"
+The driver failed to allocate an mbuf for the transmitter ring when
+allocating a pad buffer or collapsing an mbuf chain into a cluster.
+.It "ax%d: chip is in D3 power state -- setting to D0"
+This message applies only to adapters which support power
+management. Some operating systems place the controller in low power
+mode when shutting down, and some PCI BIOSes fail to bring the chip
+out of this state before configuring it. The controller loses all of
+its PCI configuration in the D3 state, so if the BIOS does not set
+it back to full power mode in time, it won't be able to configure it
+correctly. The driver tries to detect this condition and bring
+the adapter back to the D0 (full power) state, but this may not be
+enough to return the driver to a fully operational condition. If
+you see this message at boot time and the driver fails to attach
+the device as a network interface, you will have to perform second
+warm boot to have the device properly configured.
+.Pp
+Note that this condition only occurs when warm booting from another
+operating system. If you power down your system prior to booting
+.Fx ,
+the card should be configured correctly.
+.El
+.Sh SEE ALSO
+.Xr arp 4 ,
+.Xr netintro 4 , 
+.Xr ifconfig 8
+.Rs
+.%T ADMtek AL981 data sheet
+.%O http://www.admtek.com.tw
+.Re
+.Sh HISTORY
+The
+.Nm
+device driver first appeared in
+.Fx 3.0 .
+.Sh AUTHOR
+The
+.Nm
+driver was written by
+.An Bill Paul Aq wpaul@ctr.columbia.edu .
diff --git a/share/man/man4/man4.i386/Makefile b/share/man/man4/man4.i386/Makefile
index 70c2368..3f73397 100644
--- a/share/man/man4/man4.i386/Makefile
+++ b/share/man/man4/man4.i386/Makefile
@@ -1,7 +1,7 @@
-#	$Id: Makefile,v 1.106 1999/05/09 19:35:48 n_hibma Exp $
+#	$Id: Makefile,v 1.107 1999/05/10 03:51:07 bde Exp $
 
 MAN4=	adv.4 adw.4 aha.4 ahb.4 ahc.4 aic.4 alpm.4 apm.4 ar.4 asc.4 atkbd.4 \
-	atkbdc.4 ax.4 bktr.4 bt.4 cs.4 cx.4 cy.4 de.4 \
+	atkbdc.4 al.4 ax.4 bktr.4 bt.4 cs.4 cx.4 cy.4 de.4 \
 	dgb.4 dpt.4 ed.4 el.4 en.4 ep.4 ex.4 fdc.4 fe.4 fxp.4 gsc.4 ie.4 \
 	io.4 joy.4 keyboard.4 labpc.4 le.4 lnc.4 matcd.4 mcd.4 \
 	mem.4 meteor.4 mouse.4 mse.4 mtio.4 mx.4 ncr.4 npx.4 \
@@ -22,6 +22,7 @@ MLINKS+=	ar.4 ../ar.4
 MLINKS+=	asc.4 ../asc.4
 MLINKS+=	atkbd.4 ../atkbd.4
 MLINKS+=	atkbdc.4 ../atkbdc.4
+MLINKS+=	al.4 ../al.4
 MLINKS+=	ax.4 ../ax.4
 MLINKS+=	bktr.4 ../bktr.4
 MLINKS+=	bt.4 ../bt.4
diff --git a/share/man/man4/man4.i386/al.4 b/share/man/man4/man4.i386/al.4
new file mode 100644
index 0000000..062e7a2
--- /dev/null
+++ b/share/man/man4/man4.i386/al.4
@@ -0,0 +1,152 @@
+.\" Copyright (c) 1997, 1998, 1999
+.\"	Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\" 3. All advertising materials mentioning features or use of this software
+.\"    must display the following acknowledgement:
+.\"	This product includes software developed by Bill Paul.
+.\" 4. Neither the name of the author nor the names of any co-contributors
+.\"    may be used to endorse or promote products derived from this software
+.\"   without specific prior written permission.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+.\" THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.\"	$Id$
+.\"
+.Dd May 20, 1999
+.Dt AL 4 i386
+.Os FreeBSD
+.Sh NAME
+.Nm al
+.Nd
+ADMtek Inc. AL981 Comet fast ethernet device driver
+.Sh SYNOPSIS
+.Cd "device al0"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for PCI ethernet adapters and embedded
+controllers based on the ADMtek Inc. AL981 Comet fast ethernet
+controller chip.
+.Pp
+The ADMtek chip uses bus master DMA and is designed to be a
+DEC 21x4x workalike. The only major difference between the DEC
+and ADMtek parts is that the AL981 receiver filter is programmed
+using two special registers where as the DEC chip is programmed
+by uploading a special setup frame via the transmit DMA engine.
+The AL981 receive filter can only be programmed with a single
+perfect filter entry for the local station address and a 64-bit
+multicast hash table; the DEC filter has supports several other
+options. The ADMtek fast ethernet controller supports both
+10 and 100Mbps speeds in either full or half duplex using
+an internal MII transceiver.
+.Pp
+The
+.Nm
+driver supports the following media types:
+.Pp
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It autoselect
+Enable autoselection of the media type and options.
+The user can manually override
+the autoselected mode by adding media options to the
+.Pa /etc/rc.conf
+fine.
+.It 10baseT/UTP
+Set 10Mbps operation. The
+.Ar mediaopt
+option can also be used to select either
+.Ar full-duplex
+or
+.Ar half-duplex modes.
+.It 100baseTX
+Set 100Mbps (fast ethernet) operation. The
+.Ar mediaopt
+option can also be used to select either
+.Ar full-duplex
+or
+.Ar half-duplex
+modes.
+.El
+.Pp
+The
+.Nm
+driver supports the following media options:
+.Pp
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It full-duplex
+Force full duplex operation
+.It half-duplex
+Force half duplex operation.
+.El
+.Pp
+For more information on configuring this device, see
+.Xr ifconfig 8 .
+.Sh DIAGNOSTICS
+.Bl -diag
+.It "ax%d: couldn't map memory"
+A fatal initialization error has occurred.
+.It "ax%d: couldn't map interrupt"
+A fatal initialization error has occurred.
+.It "ax%d: watchdog timeout"
+The device has stopped responding to the network, or there is a problem with
+the network connection (cable).
+.It "ax%d: no memory for rx list"
+The driver failed to allocate an mbuf for the receiver ring.
+.It "ax%d: no memory for tx list"
+The driver failed to allocate an mbuf for the transmitter ring when
+allocating a pad buffer or collapsing an mbuf chain into a cluster.
+.It "ax%d: chip is in D3 power state -- setting to D0"
+This message applies only to adapters which support power
+management. Some operating systems place the controller in low power
+mode when shutting down, and some PCI BIOSes fail to bring the chip
+out of this state before configuring it. The controller loses all of
+its PCI configuration in the D3 state, so if the BIOS does not set
+it back to full power mode in time, it won't be able to configure it
+correctly. The driver tries to detect this condition and bring
+the adapter back to the D0 (full power) state, but this may not be
+enough to return the driver to a fully operational condition. If
+you see this message at boot time and the driver fails to attach
+the device as a network interface, you will have to perform second
+warm boot to have the device properly configured.
+.Pp
+Note that this condition only occurs when warm booting from another
+operating system. If you power down your system prior to booting
+.Fx ,
+the card should be configured correctly.
+.El
+.Sh SEE ALSO
+.Xr arp 4 ,
+.Xr netintro 4 , 
+.Xr ifconfig 8
+.Rs
+.%T ADMtek AL981 data sheet
+.%O http://www.admtek.com.tw
+.Re
+.Sh HISTORY
+The
+.Nm
+device driver first appeared in
+.Fx 3.0 .
+.Sh AUTHOR
+The
+.Nm
+driver was written by
+.An Bill Paul Aq wpaul@ctr.columbia.edu .
diff --git a/sys/amd64/conf/GENERIC b/sys/amd64/conf/GENERIC
index ccbd054..6665c25 100644
--- a/sys/amd64/conf/GENERIC
+++ b/sys/amd64/conf/GENERIC
@@ -11,7 +11,7 @@
 # device lines is present in the ./LINT configuration file. If you are 
 # in doubt as to the purpose or necessity of a line, check first in LINT.
 #
-#	$Id: GENERIC,v 1.170 1999/05/14 03:57:23 obrien Exp $
+#	$Id: GENERIC,v 1.171 1999/05/20 20:02:34 n_hibma Exp $
 
 machine		i386
 cpu		I386_CPU
@@ -152,6 +152,7 @@ device		ppi0	at ppbus?
 #
 # The following Ethernet NICs are all PCI devices.
 #
+device al0		# ADMtek AL981 (``Comet'')
 device ax0		# ASIX AX88140A
 device de0		# DEC/Intel DC21x4x (``Tulip'')
 device fxp0		# Intel EtherExpress PRO/100B (82557, 82558)
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index a0eb435..7904560 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -2,7 +2,7 @@
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
-#	$Id: LINT,v 1.600 1999/05/20 10:08:37 hm Exp $
+#	$Id: LINT,v 1.601 1999/05/20 20:02:35 n_hibma Exp $
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
@@ -1532,6 +1532,9 @@ options	EISA_SLOTS=12
 # nd 1040B PCI SCSI host adapters, as well as the Qlogic ISP 2100
 # FC/AL Host Adapter.
 #
+# The `al' device provides support for PCI fast ethernet adapters
+# based on the ADMtek Inc. AL981 "Comet" chip.
+#
 # The `ax' device provides support for PCI fast ethernet adapters
 # based on the ASIX Electronics AX88140A chip, including the Alfa
 # Inc. GFC2204.
@@ -1668,6 +1671,7 @@ options SCSI_ISP_PREFER_MEM_MAP=0	# prefer I/O mapping
 #options	ISP_DISABLE_1080_SUPPORT
 #options	ISP_DISABLE_2100_SUPPORT
 
+device		al0
 device		ax0
 device		de0
 device		fxp0
diff --git a/sys/conf/files b/sys/conf/files
index f76e6f5..bdd7962 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -588,6 +588,7 @@ pci/bt848_i2c.c		optional bktr device-driver
 pci/bt_pci.c		optional bt device-driver
 pci/dpt_pci.c		optional pci dpt device-driver
 pci/cy_pci.c		optional cy device-driver
+pci/if_al.c		optional al device-driver
 pci/if_ax.c		optional ax device-driver
 pci/if_de.c		optional de device-driver
 pci/if_ed_p.c		optional ed device-driver
diff --git a/sys/i386/conf/GENERIC b/sys/i386/conf/GENERIC
index ccbd054..6665c25 100644
--- a/sys/i386/conf/GENERIC
+++ b/sys/i386/conf/GENERIC
@@ -11,7 +11,7 @@
 # device lines is present in the ./LINT configuration file. If you are 
 # in doubt as to the purpose or necessity of a line, check first in LINT.
 #
-#	$Id: GENERIC,v 1.170 1999/05/14 03:57:23 obrien Exp $
+#	$Id: GENERIC,v 1.171 1999/05/20 20:02:34 n_hibma Exp $
 
 machine		i386
 cpu		I386_CPU
@@ -152,6 +152,7 @@ device		ppi0	at ppbus?
 #
 # The following Ethernet NICs are all PCI devices.
 #
+device al0		# ADMtek AL981 (``Comet'')
 device ax0		# ASIX AX88140A
 device de0		# DEC/Intel DC21x4x (``Tulip'')
 device fxp0		# Intel EtherExpress PRO/100B (82557, 82558)
diff --git a/sys/i386/conf/LINT b/sys/i386/conf/LINT
index a0eb435..7904560 100644
--- a/sys/i386/conf/LINT
+++ b/sys/i386/conf/LINT
@@ -2,7 +2,7 @@
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
-#	$Id: LINT,v 1.600 1999/05/20 10:08:37 hm Exp $
+#	$Id: LINT,v 1.601 1999/05/20 20:02:35 n_hibma Exp $
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
@@ -1532,6 +1532,9 @@ options	EISA_SLOTS=12
 # nd 1040B PCI SCSI host adapters, as well as the Qlogic ISP 2100
 # FC/AL Host Adapter.
 #
+# The `al' device provides support for PCI fast ethernet adapters
+# based on the ADMtek Inc. AL981 "Comet" chip.
+#
 # The `ax' device provides support for PCI fast ethernet adapters
 # based on the ASIX Electronics AX88140A chip, including the Alfa
 # Inc. GFC2204.
@@ -1668,6 +1671,7 @@ options SCSI_ISP_PREFER_MEM_MAP=0	# prefer I/O mapping
 #options	ISP_DISABLE_1080_SUPPORT
 #options	ISP_DISABLE_2100_SUPPORT
 
+device		al0
 device		ax0
 device		de0
 device		fxp0
diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES
index a0eb435..7904560 100644
--- a/sys/i386/conf/NOTES
+++ b/sys/i386/conf/NOTES
@@ -2,7 +2,7 @@
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
-#	$Id: LINT,v 1.600 1999/05/20 10:08:37 hm Exp $
+#	$Id: LINT,v 1.601 1999/05/20 20:02:35 n_hibma Exp $
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
@@ -1532,6 +1532,9 @@ options	EISA_SLOTS=12
 # nd 1040B PCI SCSI host adapters, as well as the Qlogic ISP 2100
 # FC/AL Host Adapter.
 #
+# The `al' device provides support for PCI fast ethernet adapters
+# based on the ADMtek Inc. AL981 "Comet" chip.
+#
 # The `ax' device provides support for PCI fast ethernet adapters
 # based on the ASIX Electronics AX88140A chip, including the Alfa
 # Inc. GFC2204.
@@ -1668,6 +1671,7 @@ options SCSI_ISP_PREFER_MEM_MAP=0	# prefer I/O mapping
 #options	ISP_DISABLE_1080_SUPPORT
 #options	ISP_DISABLE_2100_SUPPORT
 
+device		al0
 device		ax0
 device		de0
 device		fxp0
diff --git a/sys/i386/i386/userconfig.c b/sys/i386/i386/userconfig.c
index e803a28..19e11c1 100644
--- a/sys/i386/i386/userconfig.c
+++ b/sys/i386/i386/userconfig.c
@@ -46,7 +46,7 @@
  ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  **
- **      $Id: userconfig.c,v 1.143 1999/05/14 05:25:44 jkoshy Exp $
+ **      $Id: userconfig.c,v 1.144 1999/05/15 18:20:19 obrien Exp $
  **/
 
 /**
@@ -394,7 +394,8 @@ static DEV_INFO device_info[] = {
 {"xe",          "Xircom PC Card Ethernet adapter",		0,	CLS_NETWORK},
 {"ze",          "IBM/National Semiconductor PCMCIA Ethernet adapter",0,	CLS_NETWORK},
 {"zp",          "3COM PCMCIA Etherlink III Ethernet adapter",	0,	CLS_NETWORK},
-{"ax",          "ASIC AX88140A ethernet adapter",	FLG_FIXED,	CLS_NETWORK},
+{"al",          "ADMtek AL981 ethernet adapter",	FLG_FIXED,	CLS_NETWORK},
+{"ax",          "ASIX AX88140A ethernet adapter",	FLG_FIXED,	CLS_NETWORK},
 {"de",          "DEC DC21040 Ethernet adapter",		FLG_FIXED,	CLS_NETWORK},
 {"fpa",         "DEC DEFPA PCI FDDI adapter",		FLG_FIXED,	CLS_NETWORK},
 {"rl",          "RealTek 8129/8139 ethernet adapter",	FLG_FIXED,	CLS_NETWORK},
@@ -2539,7 +2540,7 @@ visuserconfig(void)
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *      $Id: userconfig.c,v 1.143 1999/05/14 05:25:44 jkoshy Exp $
+ *      $Id: userconfig.c,v 1.144 1999/05/15 18:20:19 obrien Exp $
  */
 
 #include "scbus.h"
diff --git a/sys/pci/if_al.c b/sys/pci/if_al.c
new file mode 100644
index 0000000..5ec07b7
--- /dev/null
+++ b/sys/pci/if_al.c
@@ -0,0 +1,2002 @@
+/*
+ * Copyright (c) 1997, 1998, 1999
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	$Id: if_al.c,v 1.10 1999/05/21 02:48:49 wpaul Exp $
+ */
+
+/*
+ * ADMtek AL981 Comet fast ethernet PCI NIC driver. Datasheets for
+ * the AL981 are available from http://www.admtek.com.tw.
+ *
+ * Written by Bill Paul <wpaul@ctr.columbia.edu>
+ * Electrical Engineering Department
+ * Columbia University, New York City
+ */
+
+/*
+ * The ADMtek AL981 Comet is still another DEC 21x4x clone. It's
+ * a reasonably close copy of the tulip, except for the receiver filter
+ * programming. Where the DEC chip has a special setup frame that
+ * needs to be downloaded into the transmit DMA engine, the ADMtek chip
+ * has physical address and multicast address registers.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <vm/vm.h>              /* for vtophys */
+#include <vm/pmap.h>            /* for vtophys */
+#include <machine/clock.h>      /* for DELAY */
+#include <machine/bus_pio.h>
+#include <machine/bus_memio.h>
+#include <machine/bus.h>
+
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+
+#define AL_USEIOSPACE
+
+/* #define AL_BACKGROUND_AUTONEG */
+
+#include <pci/if_alreg.h>
+
+#ifndef lint
+static const char rcsid[] =
+	"$Id: if_al.c,v 1.10 1999/05/21 02:48:49 wpaul Exp $";
+#endif
+
+/*
+ * Various supported device vendors/types and their names.
+ */
+static struct al_type al_devs[] = {
+	{ AL_VENDORID, AL_DEVICEID_AL981,
+		"ADMtek AL981 10/100BaseTX" },
+	{ 0, 0, NULL }
+};
+
+/*
+ * Various supported PHY vendors/types and their names. Note that
+ * this driver will work with pretty much any MII-compliant PHY,
+ * so failure to positively identify the chip is not a fatal error.
+ */
+
+static struct al_type al_phys[] = {
+	{ TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
+	{ TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
+	{ NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
+	{ LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 
+	{ INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
+	{ SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
+	{ 0, 0, "<MII-compliant physical interface>" }
+};
+
+static unsigned long al_count = 0;
+static const char *al_probe	__P((pcici_t, pcidi_t));
+static void al_attach		__P((pcici_t, int));
+
+static int al_newbuf		__P((struct al_softc *,
+						struct al_chain_onefrag *));
+static int al_encap		__P((struct al_softc *, struct al_chain *,
+						struct mbuf *));
+
+static void al_rxeof		__P((struct al_softc *));
+static void al_rxeoc		__P((struct al_softc *));
+static void al_txeof		__P((struct al_softc *));
+static void al_txeoc		__P((struct al_softc *));
+static void al_intr		__P((void *));
+static void al_start		__P((struct ifnet *));
+static int al_ioctl		__P((struct ifnet *, u_long, caddr_t));
+static void al_init		__P((void *));
+static void al_stop		__P((struct al_softc *));
+static void al_watchdog		__P((struct ifnet *));
+static void al_shutdown		__P((int, void *));
+static int al_ifmedia_upd	__P((struct ifnet *));
+static void al_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));
+
+static void al_delay		__P((struct al_softc *));
+static void al_eeprom_idle	__P((struct al_softc *));
+static void al_eeprom_putbyte	__P((struct al_softc *, int));
+static void al_eeprom_getword	__P((struct al_softc *, int, u_int16_t *));
+static void al_read_eeprom	__P((struct al_softc *, caddr_t, int,
+							int, int));
+
+static u_int16_t al_phy_readreg	__P((struct al_softc *, int));
+static void al_phy_writereg	__P((struct al_softc *, int, int));
+
+static void al_autoneg_xmit	__P((struct al_softc *));
+static void al_autoneg_mii	__P((struct al_softc *, int, int));
+static void al_setmode_mii	__P((struct al_softc *, int));
+static void al_getmode_mii	__P((struct al_softc *));
+static u_int32_t al_calchash	__P((caddr_t));
+static void al_setmulti		__P((struct al_softc *));
+static void al_reset		__P((struct al_softc *));
+static int al_list_rx_init	__P((struct al_softc *));
+static int al_list_tx_init	__P((struct al_softc *));
+
+#define AL_SETBIT(sc, reg, x)				\
+	CSR_WRITE_4(sc, reg,				\
+		CSR_READ_4(sc, reg) | x)
+
+#define AL_CLRBIT(sc, reg, x)				\
+	CSR_WRITE_4(sc, reg,				\
+		CSR_READ_4(sc, reg) & ~x)
+
+#define SIO_SET(x)					\
+	CSR_WRITE_4(sc, AL_SIO,				\
+		CSR_READ_4(sc, AL_SIO) | x)
+
+#define SIO_CLR(x)					\
+	CSR_WRITE_4(sc, AL_SIO,				\
+		CSR_READ_4(sc, AL_SIO) & ~x)
+
+static void al_delay(sc)
+	struct al_softc		*sc;
+{
+	int			idx;
+
+	for (idx = (300 / 33) + 1; idx > 0; idx--)
+		CSR_READ_4(sc, AL_BUSCTL);
+}
+
+static void al_eeprom_idle(sc)
+	struct al_softc		*sc;
+{
+	register int		i;
+
+	CSR_WRITE_4(sc, AL_SIO, AL_SIO_EESEL);
+	al_delay(sc);
+	AL_SETBIT(sc, AL_SIO,  AL_SIO_ROMCTL_READ);
+	al_delay(sc);
+	AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CS);
+	al_delay(sc);
+	AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CLK);
+	al_delay(sc);
+
+	for (i = 0; i < 25; i++) {
+		AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CLK);
+		al_delay(sc);
+		AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CLK);
+		al_delay(sc);
+	}
+
+	AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CLK);
+	al_delay(sc);
+	AL_CLRBIT(sc, AL_SIO, AL_SIO_EE_CS);
+	al_delay(sc);
+	CSR_WRITE_4(sc, AL_SIO, 0x00000000);
+
+	return;
+}
+
+/*
+ * Send a read command and address to the EEPROM, check for ACK.
+ */
+static void al_eeprom_putbyte(sc, addr)
+	struct al_softc		*sc;
+	int			addr;
+{
+	register int		d, i;
+
+	d = addr | AL_EECMD_READ;
+
+	/*
+	 * Feed in each bit and stobe the clock.
+	 */
+	for (i = 0x400; i; i >>= 1) {
+		if (d & i) {
+			SIO_SET(AL_SIO_EE_DATAIN);
+		} else {
+			SIO_CLR(AL_SIO_EE_DATAIN);
+		}
+		al_delay(sc);
+		SIO_SET(AL_SIO_EE_CLK);
+		al_delay(sc);
+		SIO_CLR(AL_SIO_EE_CLK);
+		al_delay(sc);
+	}
+
+	return;
+}
+
+/*
+ * Read a word of data stored in the EEPROM at address 'addr.'
+ */
+static void al_eeprom_getword(sc, addr, dest)
+	struct al_softc		*sc;
+	int			addr;
+	u_int16_t		*dest;
+{
+	register int		i;
+	u_int16_t		word = 0;
+
+	/* Force EEPROM to idle state. */
+	al_eeprom_idle(sc);
+
+	/* Enter EEPROM access mode. */
+	CSR_WRITE_4(sc, AL_SIO, AL_SIO_EESEL);
+	al_delay(sc);
+	AL_SETBIT(sc, AL_SIO,  AL_SIO_ROMCTL_READ);
+	al_delay(sc);
+	AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CS);
+	al_delay(sc);
+	AL_SETBIT(sc, AL_SIO, AL_SIO_EE_CLK);
+	al_delay(sc);
+
+	/*
+	 * Send address of word we want to read.
+	 */
+	al_eeprom_putbyte(sc, addr);
+
+	/*
+	 * Start reading bits from EEPROM.
+	 */
+	for (i = 0x8000; i; i >>= 1) {
+		SIO_SET(AL_SIO_EE_CLK);
+		al_delay(sc);
+		if (CSR_READ_4(sc, AL_SIO) & AL_SIO_EE_DATAOUT)
+			word |= i;
+		al_delay(sc);
+		SIO_CLR(AL_SIO_EE_CLK);
+		al_delay(sc);
+	}
+
+	/* Turn off EEPROM access mode. */
+	al_eeprom_idle(sc);
+
+	*dest = word;
+
+	return;
+}
+
+/*
+ * Read a sequence of words from the EEPROM.
+ */
+static void al_read_eeprom(sc, dest, off, cnt, swap)
+	struct al_softc		*sc;
+	caddr_t			dest;
+	int			off;
+	int			cnt;
+	int			swap;
+{
+	int			i;
+	u_int16_t		word = 0, *ptr;
+
+	for (i = 0; i < cnt; i++) {
+		al_eeprom_getword(sc, off + i, &word);
+		ptr = (u_int16_t *)(dest + (i * 2));
+		if (swap)
+			*ptr = ntohs(word);
+		else
+			*ptr = word;
+	}
+
+	return;
+}
+
+static u_int16_t al_phy_readreg(sc, reg)
+	struct al_softc		*sc;
+	int			reg;
+{
+	u_int16_t		rval = 0;
+	u_int16_t		phy_reg = 0;
+
+	switch(reg) {
+	case PHY_BMCR:
+		phy_reg = AL_BMCR;
+		break;
+	case PHY_BMSR:
+		phy_reg = AL_BMSR;
+		break;
+	case PHY_VENID:
+		phy_reg = AL_VENID;
+		break;
+	case PHY_DEVID:
+		phy_reg = AL_DEVID;
+		break;
+	case PHY_ANAR:
+		phy_reg = AL_ANAR;
+		break;
+	case PHY_LPAR:
+		phy_reg = AL_LPAR;
+		break;
+	case PHY_ANEXP:
+		phy_reg = AL_ANER;
+		break;
+	default:
+		printf("al%d: read: bad phy register %x\n",
+		    sc->al_unit, reg);
+		break;
+	}
+
+	rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
+
+	return(rval);
+}
+
+static void al_phy_writereg(sc, reg, data)
+	struct al_softc		*sc;
+	int			reg;
+	int			data;
+{
+	u_int16_t		phy_reg = 0;
+
+	switch(reg) {
+	case PHY_BMCR:
+		phy_reg = AL_BMCR;
+		break;
+	case PHY_BMSR:
+		phy_reg = AL_BMSR;
+		break;
+	case PHY_VENID:
+		phy_reg = AL_VENID;
+		break;
+	case PHY_DEVID:
+		phy_reg = AL_DEVID;
+		break;
+	case PHY_ANAR:
+		phy_reg = AL_ANAR;
+		break;
+	case PHY_LPAR:
+		phy_reg = AL_LPAR;
+		break;
+	case PHY_ANEXP:
+		phy_reg = AL_ANER;
+		break;
+	default:
+		printf("al%d: phy_write: bad phy register %x\n",
+		    sc->al_unit, reg);
+		break;
+	}
+
+	CSR_WRITE_4(sc, phy_reg, data);
+
+	return;
+}
+
+/*
+ * Calculate CRC of a multicast group address, return the lower 6 bits.
+ */
+static u_int32_t al_calchash(addr)
+	caddr_t			addr;
+{
+	u_int32_t		crc, carry;
+	int			i, j;
+	u_int8_t		c;
+
+	/* Compute CRC for the address value. */
+	crc = 0xFFFFFFFF; /* initial value */
+
+	for (i = 0; i < 6; i++) {
+		c = *(addr + i);
+		for (j = 0; j < 8; j++) {
+			carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
+			crc <<= 1;
+			c >>= 1;
+			if (carry)
+				crc = (crc ^ 0x04c11db6) | carry;
+		}
+	}
+
+	/* return the filter bit position */
+	return((crc >> 26) & 0x0000003F);
+}
+
+static void al_setmulti(sc)
+	struct al_softc		*sc;
+{
+	struct ifnet		*ifp;
+	int			h = 0;
+	u_int32_t		hashes[2] = { 0, 0 };
+	struct ifmultiaddr	*ifma;
+	u_int32_t		rxfilt;
+
+	ifp = &sc->arpcom.ac_if;
+
+	rxfilt = CSR_READ_4(sc, AL_NETCFG);
+
+	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
+		rxfilt |= AL_NETCFG_RX_ALLMULTI;
+		CSR_WRITE_4(sc, AL_NETCFG, rxfilt);
+		return;
+	} else
+		rxfilt &= ~AL_NETCFG_RX_ALLMULTI;
+
+	/* first, zot all the existing hash bits */
+	CSR_WRITE_4(sc, AL_MAR0, 0);
+	CSR_WRITE_4(sc, AL_MAR1, 0);
+
+	/* now program new ones */
+	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
+				ifma = ifma->ifma_link.le_next) {
+		if (ifma->ifma_addr->sa_family != AF_LINK)
+			continue;
+		h = al_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
+		if (h < 32)
+			hashes[0] |= (1 << h);
+		else
+			hashes[1] |= (1 << (h - 32));
+	}
+
+	CSR_WRITE_4(sc, AL_MAR0, hashes[0]);
+	CSR_WRITE_4(sc, AL_MAR1, hashes[1]);
+	CSR_WRITE_4(sc, AL_NETCFG, rxfilt);
+
+	return;
+}
+
+/*
+ * Initiate an autonegotiation session.
+ */
+static void al_autoneg_xmit(sc)
+	struct al_softc		*sc;
+{
+	u_int16_t		phy_sts;
+
+	al_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
+	DELAY(500);
+	while(al_phy_readreg(sc, PHY_BMCR)
+			& PHY_BMCR_RESET);
+
+	phy_sts = al_phy_readreg(sc, PHY_BMCR);
+	phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
+	al_phy_writereg(sc, PHY_BMCR, phy_sts);
+
+	return;
+}
+
+/*
+ * Invoke autonegotiation on a PHY.
+ */
+static void al_autoneg_mii(sc, flag, verbose)
+	struct al_softc		*sc;
+	int			flag;
+	int			verbose;
+{
+	u_int16_t		phy_sts = 0, media, advert, ability;
+	struct ifnet		*ifp;
+	struct ifmedia		*ifm;
+
+	ifm = &sc->ifmedia;
+	ifp = &sc->arpcom.ac_if;
+
+	ifm->ifm_media = IFM_ETHER | IFM_AUTO;
+
+	/*
+	 * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported'
+	 * bit cleared in the status register, but has the 'autoneg enabled'
+	 * bit set in the control register. This is a contradiction, and
+	 * I'm not sure how to handle it. If you want to force an attempt
+	 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
+	 * and see what happens.
+	 */
+#ifndef FORCE_AUTONEG_TFOUR
+	/*
+	 * First, see if autoneg is supported. If not, there's
+	 * no point in continuing.
+	 */
+	phy_sts = al_phy_readreg(sc, PHY_BMSR);
+	if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
+		if (verbose)
+			printf("al%d: autonegotiation not supported\n",
+							sc->al_unit);
+		ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;	
+		return;
+	}
+#endif
+
+	switch (flag) {
+	case AL_FLAG_FORCEDELAY:
+		/*
+	 	 * XXX Never use this option anywhere but in the probe
+	 	 * routine: making the kernel stop dead in its tracks
+ 		 * for three whole seconds after we've gone multi-user
+		 * is really bad manners.
+	 	 */
+		al_autoneg_xmit(sc);
+		DELAY(5000000);
+		break;
+	case AL_FLAG_SCHEDDELAY:
+		/*
+		 * Wait for the transmitter to go idle before starting
+		 * an autoneg session, otherwise al_start() may clobber
+	 	 * our timeout, and we don't want to allow transmission
+		 * during an autoneg session since that can screw it up.
+	 	 */
+		if (sc->al_cdata.al_tx_head != NULL) {
+			sc->al_want_auto = 1;
+			return;
+		}
+		al_autoneg_xmit(sc);
+		ifp->if_timer = 5;
+		sc->al_autoneg = 1;
+		sc->al_want_auto = 0;
+		return;
+		break;
+	case AL_FLAG_DELAYTIMEO:
+		ifp->if_timer = 0;
+		sc->al_autoneg = 0;
+		break;
+	default:
+		printf("al%d: invalid autoneg flag: %d\n", sc->al_unit, flag);
+		return;
+	}
+
+	if (al_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
+		if (verbose)
+			printf("al%d: autoneg complete, ", sc->al_unit);
+		phy_sts = al_phy_readreg(sc, PHY_BMSR);
+	} else {
+		if (verbose)
+			printf("al%d: autoneg not complete, ", sc->al_unit);
+	}
+
+	media = al_phy_readreg(sc, PHY_BMCR);
+
+	/* Link is good. Report modes and set duplex mode. */
+	if (al_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
+		if (verbose)
+			printf("link status good ");
+		advert = al_phy_readreg(sc, PHY_ANAR);
+		ability = al_phy_readreg(sc, PHY_LPAR);
+
+		if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
+			ifm->ifm_media = IFM_ETHER|IFM_100_T4;
+			media |= PHY_BMCR_SPEEDSEL;
+			media &= ~PHY_BMCR_DUPLEX;
+			printf("(100baseT4)\n");
+		} else if (advert & PHY_ANAR_100BTXFULL &&
+			ability & PHY_ANAR_100BTXFULL) {
+			ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
+			media |= PHY_BMCR_SPEEDSEL;
+			media |= PHY_BMCR_DUPLEX;
+			printf("(full-duplex, 100Mbps)\n");
+		} else if (advert & PHY_ANAR_100BTXHALF &&
+			ability & PHY_ANAR_100BTXHALF) {
+			ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
+			media |= PHY_BMCR_SPEEDSEL;
+			media &= ~PHY_BMCR_DUPLEX;
+			printf("(half-duplex, 100Mbps)\n");
+		} else if (advert & PHY_ANAR_10BTFULL &&
+			ability & PHY_ANAR_10BTFULL) {
+			ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
+			media &= ~PHY_BMCR_SPEEDSEL;
+			media |= PHY_BMCR_DUPLEX;
+			printf("(full-duplex, 10Mbps)\n");
+		} else if (advert & PHY_ANAR_10BTHALF &&
+			ability & PHY_ANAR_10BTHALF) {
+			ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
+			media &= ~PHY_BMCR_SPEEDSEL;
+			media &= ~PHY_BMCR_DUPLEX;
+			printf("(half-duplex, 10Mbps)\n");
+		}
+
+		media &= ~PHY_BMCR_AUTONEGENBL;
+
+		/* Set ASIC's duplex mode to match the PHY. */
+		al_phy_writereg(sc, PHY_BMCR, media);
+	} else {
+		if (verbose)
+			printf("no carrier\n");
+	}
+
+	al_init(sc);
+
+	if (sc->al_tx_pend) {
+		sc->al_autoneg = 0;
+		sc->al_tx_pend = 0;
+		al_start(ifp);
+	}
+
+	return;
+}
+
+static void al_getmode_mii(sc)
+	struct al_softc		*sc;
+{
+	u_int16_t		bmsr;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	bmsr = al_phy_readreg(sc, PHY_BMSR);
+	if (bootverbose)
+		printf("al%d: PHY status word: %x\n", sc->al_unit, bmsr);
+
+	/* fallback */
+	sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
+
+	if (bmsr & PHY_BMSR_10BTHALF) {
+		if (bootverbose)
+			printf("al%d: 10Mbps half-duplex mode supported\n",
+								sc->al_unit);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
+	}
+
+	if (bmsr & PHY_BMSR_10BTFULL) {
+		if (bootverbose)
+			printf("al%d: 10Mbps full-duplex mode supported\n",
+								sc->al_unit);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
+	}
+
+	if (bmsr & PHY_BMSR_100BTXHALF) {
+		if (bootverbose)
+			printf("al%d: 100Mbps half-duplex mode supported\n",
+								sc->al_unit);
+		ifp->if_baudrate = 100000000;
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
+	}
+
+	if (bmsr & PHY_BMSR_100BTXFULL) {
+		if (bootverbose)
+			printf("al%d: 100Mbps full-duplex mode supported\n",
+								sc->al_unit);
+		ifp->if_baudrate = 100000000;
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
+	}
+
+	/* Some also support 100BaseT4. */
+	if (bmsr & PHY_BMSR_100BT4) {
+		if (bootverbose)
+			printf("al%d: 100baseT4 mode supported\n", sc->al_unit);
+		ifp->if_baudrate = 100000000;
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
+#ifdef FORCE_AUTONEG_TFOUR
+		if (bootverbose)
+			printf("al%d: forcing on autoneg support for BT4\n",
+							 sc->al_unit);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
+#endif
+	}
+
+	if (bmsr & PHY_BMSR_CANAUTONEG) {
+		if (bootverbose)
+			printf("al%d: autoneg supported\n", sc->al_unit);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
+		sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
+	}
+
+	return;
+}
+
+/*
+ * Set speed and duplex mode.
+ */
+static void al_setmode_mii(sc, media)
+	struct al_softc		*sc;
+	int			media;
+{
+	u_int16_t		bmcr;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	/*
+	 * If an autoneg session is in progress, stop it.
+	 */
+	if (sc->al_autoneg) {
+		printf("al%d: canceling autoneg session\n", sc->al_unit);
+		ifp->if_timer = sc->al_autoneg = sc->al_want_auto = 0;
+		bmcr = al_phy_readreg(sc, PHY_BMCR);
+		bmcr &= ~PHY_BMCR_AUTONEGENBL;
+		al_phy_writereg(sc, PHY_BMCR, bmcr);
+	}
+
+	printf("al%d: selecting MII, ", sc->al_unit);
+
+	bmcr = al_phy_readreg(sc, PHY_BMCR);
+
+	bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
+			PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
+
+	if (IFM_SUBTYPE(media) == IFM_100_T4) {
+		printf("100Mbps/T4, half-duplex\n");
+		bmcr |= PHY_BMCR_SPEEDSEL;
+		bmcr &= ~PHY_BMCR_DUPLEX;
+	}
+
+	if (IFM_SUBTYPE(media) == IFM_100_TX) {
+		printf("100Mbps, ");
+		bmcr |= PHY_BMCR_SPEEDSEL;
+	}
+
+	if (IFM_SUBTYPE(media) == IFM_10_T) {
+		printf("10Mbps, ");
+		bmcr &= ~PHY_BMCR_SPEEDSEL;
+	}
+
+	if ((media & IFM_GMASK) == IFM_FDX) {
+		printf("full duplex\n");
+		bmcr |= PHY_BMCR_DUPLEX;
+	} else {
+		printf("half duplex\n");
+		bmcr &= ~PHY_BMCR_DUPLEX;
+	}
+
+	al_phy_writereg(sc, PHY_BMCR, bmcr);
+
+	return;
+}
+
+static void al_reset(sc)
+	struct al_softc		*sc;
+{
+	register int		i;
+
+	AL_SETBIT(sc, AL_BUSCTL, AL_BUSCTL_RESET);
+
+	for (i = 0; i < AL_TIMEOUT; i++) {
+		DELAY(10);
+		if (!(CSR_READ_4(sc, AL_BUSCTL) & AL_BUSCTL_RESET))
+			break;
+	}
+#ifdef notdef
+	if (i == AL_TIMEOUT)
+		printf("al%d: reset never completed!\n", sc->al_unit);
+#endif
+	CSR_WRITE_4(sc, AL_BUSCTL, AL_BUSCTL_ARBITRATION);
+
+	/* Wait a little while for the chip to get its brains in order. */
+	DELAY(1000);
+        return;
+}
+
+/*
+ * Probe for an ADMtek chip. Check the PCI vendor and device
+ * IDs against our list and return a device name if we find a match.
+ */
+static const char *
+al_probe(config_id, device_id)
+	pcici_t			config_id;
+	pcidi_t			device_id;
+{
+	struct al_type		*t;
+
+	t = al_devs;
+
+	while(t->al_name != NULL) {
+		if ((device_id & 0xFFFF) == t->al_vid &&
+		    ((device_id >> 16) & 0xFFFF) == t->al_did) {
+			return(t->al_name);
+		}
+		t++;
+	}
+
+	return(NULL);
+}
+
+/*
+ * Attach the interface. Allocate softc structures, do ifmedia
+ * setup and ethernet/BPF attach.
+ */
+static void
+al_attach(config_id, unit)
+	pcici_t			config_id;
+	int			unit;
+{
+	int			s, i;
+#ifndef AL_USEIOSPACE
+	vm_offset_t		pbase, vbase;
+#endif
+	u_char			eaddr[ETHER_ADDR_LEN];
+	u_int32_t		command;
+	struct al_softc		*sc;
+	struct ifnet		*ifp;
+	int			media = IFM_ETHER|IFM_100_TX|IFM_FDX;
+	unsigned int		round;
+	caddr_t			roundptr;
+	struct al_type		*p;
+	u_int16_t		phy_vid, phy_did, phy_sts;
+
+	s = splimp();
+
+	sc = malloc(sizeof(struct al_softc), M_DEVBUF, M_NOWAIT);
+	if (sc == NULL) {
+		printf("al%d: no memory for softc struct!\n", unit);
+		goto fail;
+	}
+	bzero(sc, sizeof(struct al_softc));
+
+	/*
+	 * Handle power management nonsense.
+	 */
+
+	command = pci_conf_read(config_id, AL_PCI_CAPID) & 0x000000FF;
+	if (command == 0x01) {
+
+		command = pci_conf_read(config_id, AL_PCI_PWRMGMTCTRL);
+		if (command & AL_PSTATE_MASK) {
+			u_int32_t		iobase, membase, irq;
+
+			/* Save important PCI config data. */
+			iobase = pci_conf_read(config_id, AL_PCI_LOIO);
+			membase = pci_conf_read(config_id, AL_PCI_LOMEM);
+			irq = pci_conf_read(config_id, AL_PCI_INTLINE);
+
+			/* Reset the power state. */
+			printf("al%d: chip is in D%d power mode "
+			"-- setting to D0\n", unit, command & AL_PSTATE_MASK);
+			command &= 0xFFFFFFFC;
+			pci_conf_write(config_id, AL_PCI_PWRMGMTCTRL, command);
+
+			/* Restore PCI config data. */
+			pci_conf_write(config_id, AL_PCI_LOIO, iobase);
+			pci_conf_write(config_id, AL_PCI_LOMEM, membase);
+			pci_conf_write(config_id, AL_PCI_INTLINE, irq);
+		}
+	}
+
+	/*
+	 * Map control/status registers.
+	 */
+	command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
+	command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
+	pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
+	command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
+
+#ifdef AL_USEIOSPACE
+	if (!(command & PCIM_CMD_PORTEN)) {
+		printf("al%d: failed to enable I/O ports!\n", unit);
+		free(sc, M_DEVBUF);
+		goto fail;
+	}
+
+	if (!pci_map_port(config_id, AL_PCI_LOIO,
+					(u_short *)&(sc->al_bhandle))) {
+		printf ("al%d: couldn't map ports\n", unit);
+		goto fail;
+        }
+#ifdef __i386__
+	sc->al_btag = I386_BUS_SPACE_IO;
+#endif
+#ifdef __alpha__
+	sc->al_btag = ALPHA_BUS_SPACE_IO;
+#endif
+#else
+	if (!(command & PCIM_CMD_MEMEN)) {
+		printf("al%d: failed to enable memory mapping!\n", unit);
+		goto fail;
+	}
+
+	if (!pci_map_mem(config_id, AL_PCI_LOMEM, &vbase, &pbase)) {
+		printf ("al%d: couldn't map memory\n", unit);
+		goto fail;
+	}
+#ifdef __i386__
+	sc->al_btag = I386_BUS_SPACE_MEM;
+#endif
+#ifdef __alpha__
+	sc->al_btag = ALPHA_BUS_SPACE_MEM;
+#endif
+	sc->al_bhandle = vbase;
+#endif
+
+	/* Allocate interrupt */
+	if (!pci_map_int(config_id, al_intr, sc, &net_imask)) {
+		printf("al%d: couldn't map interrupt\n", unit);
+		goto fail;
+	}
+
+	/* Save cache line size. */
+	sc->al_cachesize = pci_conf_read(config_id, AL_PCI_CACHELEN) & 0xFF;
+
+	/* Reset the adapter. */
+	al_reset(sc);
+
+	/*
+	 * Get station address from the EEPROM.
+	 */
+	al_read_eeprom(sc, (caddr_t)&eaddr, AL_EE_NODEADDR, 3, 0);
+
+	/*
+	 * An ADMtek chip was detected. Inform the world.
+	 */
+	printf("al%d: Ethernet address: %6D\n", unit, eaddr, ":");
+
+	sc->al_unit = unit;
+	bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
+
+	sc->al_ldata_ptr = malloc(sizeof(struct al_list_data) + 8,
+				M_DEVBUF, M_NOWAIT);
+	if (sc->al_ldata_ptr == NULL) {
+		free(sc, M_DEVBUF);
+		printf("al%d: no memory for list buffers!\n", unit);
+		goto fail;
+	}
+
+	sc->al_ldata = (struct al_list_data *)sc->al_ldata_ptr;
+	round = (unsigned long)sc->al_ldata_ptr & 0xF;
+	roundptr = sc->al_ldata_ptr;
+	for (i = 0; i < 8; i++) {
+		if (round % 8) {
+			round++;
+			roundptr++;
+		} else
+			break;
+	}
+	sc->al_ldata = (struct al_list_data *)roundptr;
+	bzero(sc->al_ldata, sizeof(struct al_list_data));
+
+	ifp = &sc->arpcom.ac_if;
+	ifp->if_softc = sc;
+	ifp->if_unit = unit;
+	ifp->if_name = "al";
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = al_ioctl;
+	ifp->if_output = ether_output;
+	ifp->if_start = al_start;
+	ifp->if_watchdog = al_watchdog;
+	ifp->if_init = al_init;
+	ifp->if_baudrate = 10000000;
+	ifp->if_snd.ifq_maxlen = AL_TX_LIST_CNT - 1;
+
+	if (bootverbose)
+		printf("al%d: probing for a PHY\n", sc->al_unit);
+	for (i = AL_PHYADDR_MIN; i < AL_PHYADDR_MAL + 1; i++) {
+		if (bootverbose)
+			printf("al%d: checking address: %d\n",
+						sc->al_unit, i);
+		sc->al_phy_addr = i;
+		al_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
+		DELAY(500);
+		while(al_phy_readreg(sc, PHY_BMCR)
+				& PHY_BMCR_RESET);
+		if ((phy_sts = al_phy_readreg(sc, PHY_BMSR)))
+			break;
+	}
+	if (phy_sts) {
+		phy_vid = al_phy_readreg(sc, PHY_VENID);
+		phy_did = al_phy_readreg(sc, PHY_DEVID);
+		if (bootverbose)
+			printf("al%d: found PHY at address %d, ",
+				sc->al_unit, sc->al_phy_addr);
+		if (bootverbose)
+			printf("vendor id: %x device id: %x\n",
+			phy_vid, phy_did);
+		p = al_phys;
+		while(p->al_vid) {
+			if (phy_vid == p->al_vid &&
+				(phy_did | 0x000F) == p->al_did) {
+				sc->al_pinfo = p;
+				break;
+			}
+			p++;
+		}
+		if (sc->al_pinfo == NULL)
+			sc->al_pinfo = &al_phys[PHY_UNKNOWN];
+		if (bootverbose)
+			printf("al%d: PHY type: %s\n",
+				sc->al_unit, sc->al_pinfo->al_name);
+	} else {
+#ifdef DIAGNOSTIC
+		printf("al%d: MII without any phy!\n", sc->al_unit);
+#endif
+	}
+
+	/*
+	 * Do ifmedia setup.
+	 */
+	ifmedia_init(&sc->ifmedia, 0, al_ifmedia_upd, al_ifmedia_sts);
+
+	if (sc->al_pinfo != NULL) {
+		al_getmode_mii(sc);
+		al_autoneg_mii(sc, AL_FLAG_FORCEDELAY, 1);
+	} else {
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
+		ifmedia_add(&sc->ifmedia,
+			IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
+		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
+	}
+
+	media = sc->ifmedia.ifm_media;
+	al_stop(sc);
+
+	ifmedia_set(&sc->ifmedia, media);
+
+	/*
+	 * Call MI attach routines.
+	 */
+	if_attach(ifp);
+	ether_ifattach(ifp);
+
+#if NBPFILTER > 0
+	bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
+#endif
+	at_shutdown(al_shutdown, sc, SHUTDOWN_POST_SYNC);
+
+fail:
+	splx(s);
+	return;
+}
+
+/*
+ * Initialize the transmit descriptors.
+ */
+static int al_list_tx_init(sc)
+	struct al_softc		*sc;
+{
+	struct al_chain_data	*cd;
+	struct al_list_data	*ld;
+	int			i;
+
+	cd = &sc->al_cdata;
+	ld = sc->al_ldata;
+	for (i = 0; i < AL_TX_LIST_CNT; i++) {
+		cd->al_tx_chain[i].al_ptr = &ld->al_tx_list[i];
+		if (i == (AL_TX_LIST_CNT - 1))
+			cd->al_tx_chain[i].al_nextdesc =
+				&cd->al_tx_chain[0];
+		else
+			cd->al_tx_chain[i].al_nextdesc =
+				&cd->al_tx_chain[i + 1];
+	}
+
+	cd->al_tx_free = &cd->al_tx_chain[0];
+	cd->al_tx_tail = cd->al_tx_head = NULL;
+
+	return(0);
+}
+
+
+/*
+ * Initialize the RX descriptors and allocate mbufs for them. Note that
+ * we arrange the descriptors in a closed ring, so that the last descriptor
+ * points back to the first.
+ */
+static int al_list_rx_init(sc)
+	struct al_softc		*sc;
+{
+	struct al_chain_data	*cd;
+	struct al_list_data	*ld;
+	int			i;
+
+	cd = &sc->al_cdata;
+	ld = sc->al_ldata;
+
+	for (i = 0; i < AL_RX_LIST_CNT; i++) {
+		cd->al_rx_chain[i].al_ptr =
+			(volatile struct al_desc *)&ld->al_rx_list[i];
+		if (al_newbuf(sc, &cd->al_rx_chain[i]) == ENOBUFS)
+			return(ENOBUFS);
+		if (i == (AL_RX_LIST_CNT - 1)) {
+			cd->al_rx_chain[i].al_nextdesc =
+						&cd->al_rx_chain[0];
+			ld->al_rx_list[i].al_next =
+					vtophys(&ld->al_rx_list[0]);
+		} else {
+			cd->al_rx_chain[i].al_nextdesc =
+						&cd->al_rx_chain[i + 1];
+			ld->al_rx_list[i].al_next =
+					vtophys(&ld->al_rx_list[i + 1]);
+		}
+	}
+
+	cd->al_rx_head = &cd->al_rx_chain[0];
+
+	return(0);
+}
+
+/*
+ * Initialize an RX descriptor and attach an MBUF cluster.
+ * Note: the length fields are only 11 bits wide, which means the
+ * largest size we can specify is 2047. This is important because
+ * MCLBYTES is 2048, so we have to subtract one otherwise we'll
+ * overflow the field and make a mess.
+ */
+static int al_newbuf(sc, c)
+	struct al_softc		*sc;
+	struct al_chain_onefrag	*c;
+{
+	struct mbuf		*m_new = NULL;
+
+	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+	if (m_new == NULL) {
+		printf("al%d: no memory for rx list -- packet dropped!\n",
+								sc->al_unit);
+		return(ENOBUFS);
+	}
+
+	MCLGET(m_new, M_DONTWAIT);
+	if (!(m_new->m_flags & M_EXT)) {
+		printf("al%d: no memory for rx list -- packet dropped!\n",
+								sc->al_unit);
+		m_freem(m_new);
+		return(ENOBUFS);
+	}
+
+	c->al_mbuf = m_new;
+	c->al_ptr->al_status = AL_RXSTAT;
+	c->al_ptr->al_data = vtophys(mtod(m_new, caddr_t));
+	c->al_ptr->al_ctl = MCLBYTES - 1;
+
+	return(0);
+}
+
+/*
+ * A frame has been uploaded: pass the resulting mbuf chain up to
+ * the higher level protocols.
+ */
+static void al_rxeof(sc)
+	struct al_softc		*sc;
+{
+        struct ether_header	*eh;
+        struct mbuf		*m;
+        struct ifnet		*ifp;
+	struct al_chain_onefrag	*cur_rx;
+	int			total_len = 0;
+	u_int32_t		rxstat;
+
+	ifp = &sc->arpcom.ac_if;
+
+	while(!((rxstat = sc->al_cdata.al_rx_head->al_ptr->al_status) &
+							AL_RXSTAT_OWN)) {
+#ifdef __alpha__
+		struct mbuf		*m0 = NULL;
+#endif
+		cur_rx = sc->al_cdata.al_rx_head;
+		sc->al_cdata.al_rx_head = cur_rx->al_nextdesc;
+
+		/*
+		 * If an error occurs, update stats, clear the
+		 * status word and leave the mbuf cluster in place:
+		 * it should simply get re-used next time this descriptor
+	 	 * comes up in the ring.
+		 */
+		if (rxstat & AL_RXSTAT_RXERR) {
+			ifp->if_ierrors++;
+			if (rxstat & AL_RXSTAT_COLLSEEN)
+				ifp->if_collisions++;
+			cur_rx->al_ptr->al_status = AL_RXSTAT;
+			cur_rx->al_ptr->al_ctl = (MCLBYTES - 1);
+			continue;
+		}
+
+		/* No errors; receive the packet. */	
+		m = cur_rx->al_mbuf;
+		total_len = AL_RXBYTES(cur_rx->al_ptr->al_status);
+
+		total_len -= ETHER_CRC_LEN;
+
+#ifdef __alpha__
+		/*
+		 * Try to conjure up a new mbuf cluster. If that
+		 * fails, it means we have an out of memory condition and
+		 * should leave the buffer in place and continue. This will
+		 * result in a lost packet, but there's little else we
+		 * can do in this situation.
+		 */
+		if (al_newbuf(sc, cur_rx) == ENOBUFS) {
+			ifp->if_ierrors++;
+			cur_rx->al_ptr->al_status = AL_RXSTAT;
+			cur_rx->al_ptr->al_ctl = (MCLBYTES - 1);
+			continue;
+		}
+
+		/*
+		 * Sadly, the ADMtek chip doesn't decode the last few
+		 * bits of the RX DMA buffer address, so we have to
+		 * cheat in order to obtain proper payload alignment
+		 * on the alpha.
+		 */
+		MGETHDR(m0, M_DONTWAIT, MT_DATA);
+		if (m0 == NULL) {
+			ifp->if_ierrors++;
+			cur_rx->al_ptr->al_status = AL_RXSTAT;
+			cur_rx->al_ptr->al_ctl = (MCLBYTES - 1);
+			continue;
+		}
+
+		m0->m_data += 2;
+		if (total_len <= (MHLEN - 2)) {
+			bcopy(mtod(m, caddr_t), mtod(m0, caddr_t), total_len);				m_freem(m);
+			m = m0;
+			m->m_pkthdr.len = m->m_len = total_len;
+		} else {
+			bcopy(mtod(m, caddr_t), mtod(m0, caddr_t), (MHLEN - 2));
+			m->m_len = total_len - (MHLEN - 2);
+			m->m_data += (MHLEN - 2);
+			m0->m_next = m;
+			m0->m_len = (MHLEN - 2);
+			m = m0;
+			m->m_pkthdr.len = total_len;
+		}
+		m->m_pkthdr.rcvif = ifp;
+#else
+		if (total_len < MINCLSIZE) {
+			m = m_devget(mtod(cur_rx->al_mbuf, char *),
+				total_len, 0, ifp, NULL);
+			cur_rx->al_ptr->al_status = AL_RXSTAT;
+			cur_rx->al_ptr->al_ctl = (MCLBYTES - 1);
+			if (m == NULL) {
+				ifp->if_ierrors++;
+				continue;
+			}
+		} else {
+			m = cur_rx->al_mbuf;
+		/*
+		 * Try to conjure up a new mbuf cluster. If that
+		 * fails, it means we have an out of memory condition and
+		 * should leave the buffer in place and continue. This will
+		 * result in a lost packet, but there's little else we
+		 * can do in this situation.
+		 */
+			if (al_newbuf(sc, cur_rx) == ENOBUFS) {
+				ifp->if_ierrors++;
+				cur_rx->al_ptr->al_status = AL_RXSTAT;
+				cur_rx->al_ptr->al_ctl = (MCLBYTES - 1);
+				continue;
+			}
+			m->m_pkthdr.rcvif = ifp;
+			m->m_pkthdr.len = m->m_len = total_len;
+		}
+#endif
+
+		ifp->if_ipackets++;
+		eh = mtod(m, struct ether_header *);
+#if NBPFILTER > 0
+		/*
+		 * Handle BPF listeners. Let the BPF user see the packet, but
+		 * don't pass it up to the ether_input() layer unless it's
+		 * a broadcast packet, multicast packet, matches our ethernet
+		 * address or the interface is in promiscuous mode.
+		 */
+		if (ifp->if_bpf) {
+			bpf_mtap(ifp, m);
+			if (ifp->if_flags & IFF_PROMISC &&
+				(bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
+						ETHER_ADDR_LEN) &&
+					(eh->ether_dhost[0] & 1) == 0)) {
+				m_freem(m);
+				continue;
+			}
+		}
+#endif
+		/* Remove header from mbuf and pass it on. */
+		m_adj(m, sizeof(struct ether_header));
+		ether_input(ifp, eh, m);
+	}
+
+	return;
+}
+
+void al_rxeoc(sc)
+	struct al_softc		*sc;
+{
+
+	al_rxeof(sc);
+	AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_RX_ON);
+	CSR_WRITE_4(sc, AL_RXADDR, vtophys(sc->al_cdata.al_rx_head->al_ptr));
+	AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_RX_ON);
+	CSR_WRITE_4(sc, AL_RXSTART, 0xFFFFFFFF);
+
+	return;
+}
+
+/*
+ * A frame was downloaded to the chip. It's safe for us to clean up
+ * the list buffers.
+ */
+
+static void al_txeof(sc)
+	struct al_softc		*sc;
+{
+	struct al_chain		*cur_tx;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	/* Clear the timeout timer. */
+	ifp->if_timer = 0;
+
+	if (sc->al_cdata.al_tx_head == NULL)
+		return;
+
+	/*
+	 * Go through our tx list and free mbufs for those
+	 * frames that have been transmitted.
+	 */
+	while(sc->al_cdata.al_tx_head->al_mbuf != NULL) {
+		u_int32_t		txstat;
+
+		cur_tx = sc->al_cdata.al_tx_head;
+		txstat = AL_TXSTATUS(cur_tx);
+
+		if (txstat & AL_TXSTAT_OWN)
+			break;
+
+		if (txstat & AL_TXSTAT_ERRSUM) {
+			ifp->if_oerrors++;
+			if (txstat & AL_TXSTAT_EXCESSCOLL)
+				ifp->if_collisions++;
+			if (txstat & AL_TXSTAT_LATECOLL)
+				ifp->if_collisions++;
+		}
+
+		ifp->if_collisions += (txstat & AL_TXSTAT_COLLCNT) >> 3;
+
+		ifp->if_opackets++;
+		m_freem(cur_tx->al_mbuf);
+		cur_tx->al_mbuf = NULL;
+
+		if (sc->al_cdata.al_tx_head == sc->al_cdata.al_tx_tail) {
+			sc->al_cdata.al_tx_head = NULL;
+			sc->al_cdata.al_tx_tail = NULL;
+			break;
+		}
+
+		sc->al_cdata.al_tx_head = cur_tx->al_nextdesc;
+	}
+
+	return;
+}
+
+/*
+ * TX 'end of channel' interrupt handler.
+ */
+static void al_txeoc(sc)
+	struct al_softc		*sc;
+{
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+
+	ifp->if_timer = 0;
+
+	if (sc->al_cdata.al_tx_head == NULL) {
+		ifp->if_flags &= ~IFF_OACTIVE;
+		sc->al_cdata.al_tx_tail = NULL;
+		if (sc->al_want_auto)
+			al_autoneg_mii(sc, AL_FLAG_DELAYTIMEO, 1);
+	}
+
+	return;
+}
+
+static void al_intr(arg)
+	void			*arg;
+{
+	struct al_softc		*sc;
+	struct ifnet		*ifp;
+	u_int32_t		status;
+
+	sc = arg;
+	ifp = &sc->arpcom.ac_if;
+
+	/* Supress unwanted interrupts */
+	if (!(ifp->if_flags & IFF_UP)) {
+		al_stop(sc);
+		return;
+	}
+
+	/* Disable interrupts. */
+	CSR_WRITE_4(sc, AL_IMR, 0x00000000);
+
+	for (;;) {
+		status = CSR_READ_4(sc, AL_ISR);
+		if (status)
+			CSR_WRITE_4(sc, AL_ISR, status);
+
+		if ((status & AL_INTRS) == 0)
+			break;
+
+		if (status & AL_ISR_TX_OK)
+			al_txeof(sc);
+
+		if (status & AL_ISR_TX_NOBUF)
+			al_txeoc(sc);
+
+		if (status & AL_ISR_TX_IDLE) {
+			al_txeof(sc);
+			if (sc->al_cdata.al_tx_head != NULL) {
+				AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_TX_ON);
+				CSR_WRITE_4(sc, AL_TXSTART, 0xFFFFFFFF);
+			}
+		}
+
+		if (status & AL_ISR_TX_UNDERRUN) {
+			u_int32_t		cfg;
+			cfg = CSR_READ_4(sc, AL_NETCFG);
+			if ((cfg & AL_NETCFG_TX_THRESH) == AL_TXTHRESH_160BYTES)
+				AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_STORENFWD);
+			else
+				CSR_WRITE_4(sc, AL_NETCFG, cfg + 0x4000);
+		}
+
+		if (status & AL_ISR_RX_OK)
+			al_rxeof(sc);
+
+		if ((status & AL_ISR_RX_WATDOGTIMEO)
+					|| (status & AL_ISR_RX_NOBUF))
+			al_rxeoc(sc);
+
+		if (status & AL_ISR_BUS_ERR) {
+			al_reset(sc);
+			al_init(sc);
+		}
+	}
+
+	/* Re-enable interrupts. */
+	CSR_WRITE_4(sc, AL_IMR, AL_INTRS);
+
+	if (ifp->if_snd.ifq_head != NULL) {
+		al_start(ifp);
+	}
+
+	return;
+}
+
+/*
+ * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
+ * pointers to the fragment pointers.
+ */
+static int al_encap(sc, c, m_head)
+	struct al_softc		*sc;
+	struct al_chain		*c;
+	struct mbuf		*m_head;
+{
+	int			frag = 0;
+	volatile struct al_desc	*f = NULL;
+	int			total_len;
+	struct mbuf		*m;
+
+	/*
+ 	 * Start packing the mbufs in this chain into
+	 * the fragment pointers. Stop when we run out
+ 	 * of fragments or hit the end of the mbuf chain.
+	 */
+	m = m_head;
+	total_len = 0;
+
+	for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
+		if (m->m_len != 0) {
+			if (frag == AL_MAXFRAGS)
+				break;
+			total_len += m->m_len;
+			f = &c->al_ptr->al_frag[frag];
+			f->al_ctl = AL_TXCTL_TLINK | m->m_len;
+			if (frag == 0) {
+				f->al_status = 0;
+				f->al_ctl |= AL_TXCTL_FIRSTFRAG;
+			} else
+				f->al_status = AL_TXSTAT_OWN;
+			f->al_next = vtophys(&c->al_ptr->al_frag[frag + 1]);
+			f->al_data = vtophys(mtod(m, vm_offset_t));
+			frag++;
+		}
+	}
+
+	/*
+	 * Handle special case: we ran out of fragments,
+	 * but we have more mbufs left in the chain. Copy the
+	 * data into an mbuf cluster. Note that we don't
+	 * bother clearing the values in the other fragment
+	 * pointers/counters; it wouldn't gain us anything,
+	 * and would waste cycles.
+	 */
+	if (m != NULL) {
+		struct mbuf		*m_new = NULL;
+
+		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+		if (m_new == NULL) {
+			printf("al%d: no memory for tx list", sc->al_unit);
+			return(1);
+		}
+		if (m_head->m_pkthdr.len > MHLEN) {
+			MCLGET(m_new, M_DONTWAIT);
+			if (!(m_new->m_flags & M_EXT)) {
+				m_freem(m_new);
+				printf("al%d: no memory for tx list",
+						sc->al_unit);
+				return(1);
+			}
+		}
+		m_copydata(m_head, 0, m_head->m_pkthdr.len,	
+					mtod(m_new, caddr_t));
+		m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
+		m_freem(m_head);
+		m_head = m_new;
+		f = &c->al_ptr->al_frag[0];
+		f->al_status = 0;
+		f->al_data = vtophys(mtod(m_new, caddr_t));
+		f->al_ctl = total_len = m_new->m_len;
+		f->al_ctl |= AL_TXCTL_TLINK|AL_TXCTL_FIRSTFRAG;
+		frag = 1;
+	}
+
+	c->al_mbuf = m_head;
+	c->al_lastdesc = frag - 1;
+	AL_TXCTL(c) |= AL_TXCTL_LASTFRAG|AL_TXCTL_FINT;
+	AL_TXNEXT(c) = vtophys(&c->al_nextdesc->al_ptr->al_frag[0]);
+	return(0);
+}
+
+/*
+ * Main transmit routine. To avoid having to do mbuf copies, we put pointers
+ * to the mbuf data regions directly in the transmit lists. We also save a
+ * copy of the pointers since the transmit list fragment pointers are
+ * physical addresses.
+ */
+
+static void al_start(ifp)
+	struct ifnet		*ifp;
+{
+	struct al_softc		*sc;
+	struct mbuf		*m_head = NULL;
+	struct al_chain		*cur_tx = NULL, *start_tx;
+
+	sc = ifp->if_softc;
+
+	if (ifp->if_flags & IFF_OACTIVE)
+		return;
+
+	if (sc->al_autoneg) {
+		sc->al_tx_pend = 1;
+		return;
+	}
+
+	/*
+	 * Check for an available queue slot. If there are none,
+	 * punt.
+	 */
+	if (sc->al_cdata.al_tx_free->al_mbuf != NULL) {
+		ifp->if_flags |= IFF_OACTIVE;
+		return;
+	}
+
+	start_tx = sc->al_cdata.al_tx_free;
+
+	while(sc->al_cdata.al_tx_free->al_mbuf == NULL) {
+		IF_DEQUEUE(&ifp->if_snd, m_head);
+		if (m_head == NULL)
+			break;
+
+		/* Pick a descriptor off the free list. */
+		cur_tx = sc->al_cdata.al_tx_free;
+		sc->al_cdata.al_tx_free = cur_tx->al_nextdesc;
+
+		/* Pack the data into the descriptor. */
+		al_encap(sc, cur_tx, m_head);
+
+#if NBPFILTER > 0
+		/*
+		 * If there's a BPF listener, bounce a copy of this frame
+		 * to him.
+		 */
+		if (ifp->if_bpf)
+			bpf_mtap(ifp, cur_tx->al_mbuf);
+#endif
+		AL_TXOWN(cur_tx) = AL_TXSTAT_OWN;
+		CSR_WRITE_4(sc, AL_TXSTART, 0xFFFFFFFF);
+		/*
+		 * Work around some strange behavior in the Comet. For
+		 * some reason, the transmitter will sometimes wedge if
+		 * we queue up a descriptor chain that wraps from the end
+		 * of the transmit list back to the beginning. If we reach
+		 * the end of the list and still have more packets to queue,
+		 * don't queue them now: end the transmit session here and
+		 * then wait until it finishes before sending the other
+		 * packets.
+		 */
+		if (cur_tx == &sc->al_cdata.al_tx_chain[AL_TX_LIST_CNT - 1]) {
+			ifp->if_flags |= IFF_OACTIVE;
+			break;
+		}
+	}
+
+	sc->al_cdata.al_tx_tail = cur_tx;
+	if (sc->al_cdata.al_tx_head == NULL)
+		sc->al_cdata.al_tx_head = start_tx;
+
+	/*
+	 * Set a timeout in case the chip goes out to lunch.
+	 */
+	ifp->if_timer = 5;
+
+	return;
+}
+
+static void al_init(xsc)
+	void			*xsc;
+{
+	struct al_softc		*sc = xsc;
+	struct ifnet		*ifp = &sc->arpcom.ac_if;
+	u_int16_t		phy_bmcr = 0;
+	int			s;
+
+	if (sc->al_autoneg)
+		return;
+
+	s = splimp();
+
+	if (sc->al_pinfo != NULL)
+		phy_bmcr = al_phy_readreg(sc, PHY_BMCR);
+
+	/*
+	 * Cancel pending I/O and free all RX/TX buffers.
+	 */
+	al_stop(sc);
+	al_reset(sc);
+
+	/*
+	 * Set cache alignment and burst length.
+	 */
+	CSR_WRITE_4(sc, AL_BUSCTL, AL_BUSCTL_ARBITRATION);
+	AL_SETBIT(sc, AL_BUSCTL, AL_BURSTLEN_16LONG);
+	switch(sc->al_cachesize) {
+	case 32:
+		AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_32LONG);
+		break;
+	case 16:
+		AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_16LONG);
+		break;
+	case 8:
+		AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_8LONG);
+		break;
+	case 0:
+	default:
+		AL_SETBIT(sc, AL_BUSCTL, AL_CACHEALIGN_NONE);
+		break;
+	}
+
+	AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_HEARTBEAT);
+	AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_STORENFWD);
+
+	AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_TX_THRESH);
+
+	if (IFM_SUBTYPE(sc->ifmedia.ifm_media) == IFM_10_T)
+		AL_SETBIT(sc, AL_NETCFG, AL_TXTHRESH_160BYTES);
+	else
+		AL_SETBIT(sc, AL_NETCFG, AL_TXTHRESH_72BYTES);
+
+	/* Init our MAC address */
+	CSR_WRITE_4(sc, AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
+	CSR_WRITE_4(sc, AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
+
+	/* Init circular RX list. */
+	if (al_list_rx_init(sc) == ENOBUFS) {
+		printf("al%d: initialization failed: no "
+			"memory for rx buffers\n", sc->al_unit);
+		al_stop(sc);
+		(void)splx(s);
+		return;
+	}
+
+	/*
+	 * Init tx descriptors.
+	 */
+	al_list_tx_init(sc);
+
+	 /* If we want promiscuous mode, set the allframes bit. */
+	if (ifp->if_flags & IFF_PROMISC) {
+		AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_RX_PROMISC);
+	} else {
+		AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_RX_PROMISC);
+	}
+
+	/*
+	 * Set the capture broadcast bit to capture broadcast frames.
+	 */
+#ifdef foo
+	if (ifp->if_flags & IFF_BROADCAST) {
+		AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_RX_BROAD);
+	} else {
+		AL_CLRBIT(sc, AL_NETCFG, AL_NETCFG_RX_BROAD);
+	}
+#endif
+
+	/*
+	 * Load the multicast filter.
+	 */
+	al_setmulti(sc);
+
+	/*
+	 * Load the address of the RX list.
+	 */
+	CSR_WRITE_4(sc, AL_RXADDR, vtophys(sc->al_cdata.al_rx_head->al_ptr));
+	CSR_WRITE_4(sc, AL_TXADDR, vtophys(&sc->al_ldata->al_tx_list[0]));
+
+	/*
+	 * Enable interrupts.
+	 */
+	CSR_WRITE_4(sc, AL_IMR, AL_INTRS);
+	CSR_WRITE_4(sc, AL_ISR, 0xFFFFFFFF);
+
+	/* Enable receiver and transmitter. */
+	AL_SETBIT(sc, AL_NETCFG, AL_NETCFG_TX_ON|AL_NETCFG_RX_ON);
+	CSR_WRITE_4(sc, AL_RXSTART, 0xFFFFFFFF);
+
+	/* Restore state of BMCR */
+	if (sc->al_pinfo != NULL)
+		al_phy_writereg(sc, PHY_BMCR, phy_bmcr);
+
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	(void)splx(s);
+
+	return;
+}
+
+/*
+ * Set media options.
+ */
+static int al_ifmedia_upd(ifp)
+	struct ifnet		*ifp;
+{
+	struct al_softc		*sc;
+	struct ifmedia		*ifm;
+
+	sc = ifp->if_softc;
+	ifm = &sc->ifmedia;
+
+	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
+		return(EINVAL);
+
+	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
+		al_autoneg_mii(sc, AL_FLAG_SCHEDDELAY, 1);
+	else {
+		al_setmode_mii(sc, ifm->ifm_media);
+	}
+
+	return(0);
+}
+
+/*
+ * Report current media status.
+ */
+static void al_ifmedia_sts(ifp, ifmr)
+	struct ifnet		*ifp;
+	struct ifmediareq	*ifmr;
+{
+	struct al_softc		*sc;
+	u_int16_t		advert = 0, ability = 0;
+
+	sc = ifp->if_softc;
+
+	ifmr->ifm_active = IFM_ETHER;
+
+	if (!(al_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
+		if (al_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
+			ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
+		else
+			ifmr->ifm_active = IFM_ETHER|IFM_10_T;
+		if (al_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
+			ifmr->ifm_active |= IFM_FDX;
+		else
+			ifmr->ifm_active |= IFM_HDX;
+		return;
+	}
+
+	ability = al_phy_readreg(sc, PHY_LPAR);
+	advert = al_phy_readreg(sc, PHY_ANAR);
+	if (advert & PHY_ANAR_100BT4 &&
+		ability & PHY_ANAR_100BT4) {
+		ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
+	} else if (advert & PHY_ANAR_100BTXFULL &&
+		ability & PHY_ANAR_100BTXFULL) {
+		ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
+	} else if (advert & PHY_ANAR_100BTXHALF &&
+		ability & PHY_ANAR_100BTXHALF) {
+		ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
+	} else if (advert & PHY_ANAR_10BTFULL &&
+		ability & PHY_ANAR_10BTFULL) {
+		ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
+	} else if (advert & PHY_ANAR_10BTHALF &&
+		ability & PHY_ANAR_10BTHALF) {
+		ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
+	}
+
+	return;
+}
+
+static int al_ioctl(ifp, command, data)
+	struct ifnet		*ifp;
+	u_long			command;
+	caddr_t			data;
+{
+	struct al_softc		*sc = ifp->if_softc;
+	struct ifreq		*ifr = (struct ifreq *) data;
+	int			s, error = 0;
+
+	s = splimp();
+
+	switch(command) {
+	case SIOCSIFADDR:
+	case SIOCGIFADDR:
+	case SIOCSIFMTU:
+		error = ether_ioctl(ifp, command, data);
+		break;
+	case SIOCSIFFLAGS:
+		if (ifp->if_flags & IFF_UP) {
+			al_init(sc);
+		} else {
+			if (ifp->if_flags & IFF_RUNNING)
+				al_stop(sc);
+		}
+		error = 0;
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		al_setmulti(sc);
+		error = 0;
+		break;
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
+		break;
+	default:
+		error = EINVAL;
+		break;
+	}
+
+	(void)splx(s);
+
+	return(error);
+}
+
+static void al_watchdog(ifp)
+	struct ifnet		*ifp;
+{
+	struct al_softc		*sc;
+
+	sc = ifp->if_softc;
+
+	if (sc->al_autoneg) {
+		al_autoneg_mii(sc, AL_FLAG_DELAYTIMEO, 1);
+		return;
+	}
+
+	ifp->if_oerrors++;
+	printf("al%d: watchdog timeout\n", sc->al_unit);
+
+	if (sc->al_pinfo != NULL) {
+		if (!(al_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
+			printf("al%d: no carrier - transceiver "
+				"cable problem?\n", sc->al_unit);
+	}
+
+	al_stop(sc);
+	al_reset(sc);
+	al_init(sc);
+
+	if (ifp->if_snd.ifq_head != NULL)
+		al_start(ifp);
+
+	return;
+}
+
+/*
+ * Stop the adapter and free any mbufs allocated to the
+ * RX and TX lists.
+ */
+static void al_stop(sc)
+	struct al_softc		*sc;
+{
+	register int		i;
+	struct ifnet		*ifp;
+
+	ifp = &sc->arpcom.ac_if;
+	ifp->if_timer = 0;
+
+	AL_CLRBIT(sc, AL_NETCFG, (AL_NETCFG_RX_ON|AL_NETCFG_TX_ON));
+	CSR_WRITE_4(sc, AL_IMR, 0x00000000);
+	CSR_WRITE_4(sc, AL_TXADDR, 0x00000000);
+	CSR_WRITE_4(sc, AL_RXADDR, 0x00000000);
+
+	/*
+	 * Free data in the RX lists.
+	 */
+	for (i = 0; i < AL_RX_LIST_CNT; i++) {
+		if (sc->al_cdata.al_rx_chain[i].al_mbuf != NULL) {
+			m_freem(sc->al_cdata.al_rx_chain[i].al_mbuf);
+			sc->al_cdata.al_rx_chain[i].al_mbuf = NULL;
+		}
+	}
+	bzero((char *)&sc->al_ldata->al_rx_list,
+		sizeof(sc->al_ldata->al_rx_list));
+
+	/*
+	 * Free the TX list buffers.
+	 */
+	for (i = 0; i < AL_TX_LIST_CNT; i++) {
+		if (sc->al_cdata.al_tx_chain[i].al_mbuf != NULL) {
+			m_freem(sc->al_cdata.al_tx_chain[i].al_mbuf);
+			sc->al_cdata.al_tx_chain[i].al_mbuf = NULL;
+		}
+	}
+
+	bzero((char *)&sc->al_ldata->al_tx_list,
+		sizeof(sc->al_ldata->al_tx_list));
+
+	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+
+	return;
+}
+
+/*
+ * Stop all chip I/O so that the kernel's probe routines don't
+ * get confused by errant DMAs when rebooting.
+ */
+static void al_shutdown(howto, arg)
+	int			howto;
+	void			*arg;
+{
+	struct al_softc		*sc = (struct al_softc *)arg;
+
+	al_stop(sc);
+
+	return;
+}
+
+static struct pci_device al_device = {
+	"al",
+	al_probe,
+	al_attach,
+	&al_count,
+	NULL
+};
+COMPAT_PCI_DRIVER(xl, xl_device);
diff --git a/sys/pci/if_alreg.h b/sys/pci/if_alreg.h
new file mode 100644
index 0000000..dfb9915
--- /dev/null
+++ b/sys/pci/if_alreg.h
@@ -0,0 +1,707 @@
+/*
+ * Copyright (c) 1997, 1998, 1999
+ *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	$Id: if_alreg.h,v 1.4 1999/05/21 00:07:34 wpaul Exp $
+ */
+
+/*
+ * COMET register definitions.
+ */
+
+#define AL_BUSCTL		0x00	/* bus control */
+#define AL_TXSTART		0x08	/* tx start demand */
+#define AL_RXSTART		0x10	/* rx start demand */
+#define AL_RXADDR		0x18	/* rx descriptor list start addr */
+#define AL_TXADDR		0x20	/* tx descriptor list start addr */
+#define AL_ISR			0x28	/* interrupt status register */
+#define AL_NETCFG		0x30	/* network config register */
+#define AL_IMR			0x38	/* interrupt mask */
+#define AL_FRAMESDISCARDED	0x40	/* # of discarded frames */
+#define AL_SIO			0x48	/* MII and ROM/EEPROM access */
+#define AL_RESERVED		0x50
+#define AL_GENTIMER		0x58	/* general timer */
+#define AL_GENPORT		0x60	/* general purpose port */
+#define AL_WAKEUP_CTL		0x68	/* wake-up control/status register */
+#define AL_WAKEUP_PAT		0x70	/* wake-up pattern data register */
+#define AL_WATCHDOG		0x78	/* watchdog timer */
+#define AL_ISR2			0x80	/* ISR assist register */
+#define AL_IMR2			0x84	/* IRM assist register */
+#define AL_COMMAND		0x88	/* command register */
+#define AL_PCIPERF		0x8C	/* pci perf counter */
+#define AL_PWRMGMT		0x90	/* pwr management command/status */
+#define AL_TXBURST		0x9C	/* tx burst counter/timeout */
+#define AL_FLASHPROM		0xA0	/* flash(boot) PROM port */
+#define AL_PAR0			0xA4	/* station address */
+#define AL_PAR1			0xA8	/* station address */
+#define AL_MAR0			0xAC	/* multicast hash filter */
+#define AL_MAR1			0xB0	/* multicast hash filter */
+#define AL_BMCR			0xB4	/* built in PHY control */
+#define AL_BMSR			0xB8	/* built in PHY status */
+#define AL_VENID		0xBC	/* built in PHY ID0 */
+#define AL_DEVID		0xC0	/* built in PHY ID1 */
+#define AL_ANAR			0xC4	/* built in PHY autoneg advert */
+#define AL_LPAR			0xC8	/* bnilt in PHY link part. ability */
+#define AL_ANER			0xCC	/* built in PHY autoneg expansion */
+#define AL_PHY_MODECTL		0xD0	/* mode control */
+#define AL_PHY_CONFIG		0xD4	/* config info and inter status */
+#define AL_PHY_INTEN		0xD8	/* interrupto enable */
+#define AL_PHY_MODECTL_100TX	0xDC	/* 100baseTX control/status */
+
+/*
+ * Bus control bits.
+ */
+#define AL_BUSCTL_RESET		0x00000001
+#define AL_BUSCTL_ARBITRATION	0x00000002
+#define AL_BUSCTL_SKIPLEN	0x0000007C
+#define AL_BUSCTL_BIGENDIAN	0x00000080
+#define AL_BUSCTL_BURSTLEN	0x00003F00
+#define AL_BUSCTL_CACHEALIGN	0x0000C000
+#define AL_BUSCTL_XMITPOLL	0x00060000
+#define AL_BUSCTL_BUF_BIGENDIAN	0x00100000
+#define AL_BUSCTL_READMULTI	0x00200000
+#define AL_BUSCTL_READLINE	0x00800000
+#define AL_BUSCTL_WRITEINVAL	0x01000000
+
+#define AL_SKIPLEN_1LONG	0x00000004
+#define AL_SKIPLEN_2LONG	0x00000008
+#define AL_SKIPLEN_3LONG	0x00000010
+#define AL_SKIPLEN_4LONG	0x00000020
+#define AL_SKIPLEN_5LONG	0x00000040
+
+#define AL_BURSTLEN_UNLIMIT	0x00000000
+#define AL_BURSTLEN_1LONG	0x00000100
+#define AL_BURSTLEN_2LONG	0x00000200
+#define AL_BURSTLEN_4LONG	0x00000400
+#define AL_BURSTLEN_8LONG	0x00000800
+#define AL_BURSTLEN_16LONG	0x00001000
+#define AL_BURSTLEN_32LONG	0x00002000
+
+#define AL_CACHEALIGN_NONE	0x00000000
+#define AL_CACHEALIGN_8LONG	0x00004000
+#define AL_CACHEALIGN_16LONG	0x00008000
+#define AL_CACHEALIGN_32LONG	0x0000C000
+
+#define AL_TXPOLL_OFF		0x00000000
+#define AL_TXPOLL_200U		0x00020000
+#define AX_TXPOLL_800U		0x00040000
+#define AL_TXPOLL_1600U		0x00060000
+
+/*
+ * Interrupt status bits.
+ */
+#define AL_ISR_TX_OK		0x00000001
+#define AL_ISR_TX_IDLE		0x00000002
+#define AL_ISR_TX_NOBUF		0x00000004
+#define AL_ISR_TX_JABBERTIMEO	0x00000008
+#define AL_ISR_TX_UNDERRUN	0x00000020
+#define AL_ISR_RX_OK		0x00000040
+#define AL_ISR_RX_NOBUF		0x00000080
+#define AL_ISR_RX_IDLE		0x00000100
+#define AL_ISR_RX_WATDOGTIMEO	0x00000200
+#define AL_ISR_TIMER_EXPIRED	0x00000800
+#define AL_ISR_BUS_ERR		0x00002000
+#define AL_ISR_ABNORMAL		0x00008000
+#define AL_ISR_NORMAL		0x00010000
+#define AL_ISR_RX_STATE		0x000E0000
+#define AL_ISR_TX_STATE		0x00700000
+#define AL_ISR_BUSERRTYPE	0x03800000
+
+#define AL_RXSTATE_STOPPED	0x00000000	/* 000 - Stopped */
+#define AL_RXSTATE_FETCH	0x00020000	/* 001 - Fetching descriptor */
+#define AL_RXSTATE_ENDCHECK	0x00040000	/* 010 - check for rx end */
+#define AL_RXSTATE_WAIT		0x00060000	/* 011 - waiting for packet */
+#define AL_RXSTATE_SUSPEND	0x00080000	/* 100 - suspend rx */
+#define AL_RXSTATE_CLOSE	0x000A0000	/* 101 - close tx desc */
+#define AL_RXSTATE_FLUSH	0x000C0000	/* 110 - flush from FIFO */
+#define AL_RXSTATE_DEQUEUE	0x000E0000	/* 111 - dequeue from FIFO */
+
+#define AL_TXSTATE_RESET	0x00000000	/* 000 - reset */
+#define AL_TXSTATE_FETCH	0x00100000	/* 001 - fetching descriptor */
+#define AL_TXSTATE_WAITEND	0x00200000	/* 010 - wait for tx end */
+#define AL_TXSTATE_READING	0x00300000	/* 011 - read and enqueue */
+#define AL_TXSTATE_RSVD		0x00400000	/* 100 - reserved */
+#define AL_TXSTATE_SETUP	0x00500000	/* 101 - setup packet */
+#define AL_TXSTATE_SUSPEND	0x00600000	/* 110 - suspend tx */
+#define AL_TXSTATE_CLOSE	0x00700000	/* 111 - close tx desc */
+
+/*
+ * Network config bits.
+ */
+#define AL_NETCFG_RX_ON		0x00000002
+#define AL_NETCFG_RX_BADFRAMES	0x00000008
+#define AL_NETCFG_RX_BACKOFF	0x00000020
+#define AL_NETCFG_RX_PROMISC	0x00000040
+#define AL_NETCFG_RX_ALLMULTI	0x00000080
+#define AL_NETCFG_OPMODE	0x00000C00
+#define AL_NETCFG_FORCECOLL	0x00001000
+#define AL_NETCFG_TX_ON		0x00002000
+#define AL_NETCFG_TX_THRESH	0x0000C000
+#define AL_NETCFG_HEARTBEAT	0x00080000	/* 0 == ON, 1 == OFF */
+#define AL_NETCFG_STORENFWD	0x00200000
+
+#define AL_OPMODE_NORM		0x00000000
+#define AL_OPMODE_INTLOOP	0x00000400
+#define AL_OPMODE_EXTLOOP	0x00000800
+
+#define AL_TXTHRESH_72BYTES	0x00000000
+#define AL_TXTHRESH_96BYTES	0x00004000
+#define AL_TXTHRESH_128BYTES	0x00008000
+#define AL_TXTHRESH_160BYTES	0x0000C000
+
+/*
+ * Interrupt mask bits.
+ */
+#define AL_IMR_TX_OK		0x00000001
+#define AL_IMR_TX_IDLE		0x00000002
+#define AL_IMR_TX_NOBUF		0x00000004
+#define AL_IMR_TX_JABBERTIMEO	0x00000008
+#define AL_IMR_TX_UNDERRUN	0x00000020
+#define AL_IMR_RX_OK		0x00000040
+#define AL_IMR_RX_NOBUF		0x00000080
+#define AL_IMR_RX_IDLE		0x00000100
+#define AL_IMR_RX_WATDOGTIMEO	0x00000200
+#define AL_IMR_TIMER_EXPIRED	0x00000800
+#define AL_IMR_BUS_ERR		0x00002000
+#define AL_IMR_ABNORMAL		0x00008000
+#define AL_IMR_NORMAL		0x00010000
+
+#define AL_INTRS	\
+	(AL_IMR_RX_OK|AL_IMR_TX_OK|AL_IMR_RX_NOBUF|AL_IMR_RX_WATDOGTIMEO|\
+	AL_IMR_TX_NOBUF|AL_IMR_TX_UNDERRUN|AL_IMR_BUS_ERR|		\
+	AL_IMR_ABNORMAL|AL_IMR_NORMAL|AL_IMR_TX_IDLE|AL_IMR_RX_IDLE)
+
+/*
+ * Missed packer register.
+ */
+#define AL_MISSEDPKT_CNT	0x0000FFFF
+#define AL_MISSEDPKT_OFLOW	0x00010000
+
+/*
+ * Serial I/O (EEPROM/ROM) bits.
+ */
+#define AL_SIO_EE_CS		0x00000001	/* EEPROM chip select */
+#define AL_SIO_EE_CLK		0x00000002	/* EEPROM clock */
+#define AL_SIO_EE_DATAIN	0x00000004	/* EEPROM data output */
+#define AL_SIO_EE_DATAOUT	0x00000008	/* EEPROM data input */
+#define AL_SIO_EESEL		0x00000800
+#define AL_SIO_ROMCTL_WRITE	0x00002000
+#define AL_SIO_ROMCTL_READ	0x00004000
+
+#define AL_EECMD_WRITE		0x140
+#define AL_EECMD_READ		0x180
+#define AL_EECMD_ERASE		0x1c0
+
+#define AL_EE_NODEADDR_OFFSET	0x70
+#define AL_EE_NODEADDR		4
+
+/*
+ * General purpose timer register
+ */
+#define AL_TIMER_VALUE		0x0000FFFF
+#define AL_TIMER_CONTINUOUS	0x00010000
+
+/*
+ * Wakeup control/status register.
+ */
+#define AL_WU_LINKSTS		0x00000001	/* link status changed */
+#define AL_WU_MAGICPKT		0x00000002	/* magic packet received */
+#define AL_WU_WUPKT		0x00000004	/* wake up pkt received */
+#define AL_WU_LINKSTS_ENB	0x00000100	/* enable linksts event */
+#define AL_WU_MAGICPKT_ENB	0x00000200	/* enable magicpkt event */
+#define AL_WU_WUPKT_ENB		0x00000400	/* enable wakeup pkt event */
+#define AL_WU_LINKON_ENB	0x00010000	/* enable link on detect  */
+#define AL_WU_LINKOFF_ENB	0x00020000	/* enable link off detect */
+#define AL_WU_WKUPMATCH_PAT5	0x02000000	/* enable wkup pat 5 match */
+#define AL_WU_WKUPMATCH_PAT4	0x04000000	/* enable wkup pat 4 match */
+#define AL_WU_WKUPMATCH_PAT3	0x08000000	/* enable wkup pat 3 match */
+#define AL_WU_WKUPMATCH_PAT2	0x10000000	/* enable wkup pat 2 match */
+#define AL_WU_WKUPMATCH_PAT1	0x20000000	/* enable wkup pat 1 match */
+#define AL_WU_CRCTYPE		0x40000000	/* crc: 0=0000, 1=ffff */
+
+/*
+ * Wakeup pattern structure.
+ */
+struct al_wu_pattern {
+	u_int32_t		al_wu_bits[4];
+};
+
+struct al_wakeup {
+	struct al_wu_pattern	al_wu_pat;
+	u_int16_t		al_wu_crc1;
+	u_int16_t		al_wu_offset1;
+};
+
+struct al_wakup_record {
+	struct al_wakeup	al_wakeup[5];
+};
+
+/*
+ * Watchdog timer register.
+ */
+#define AL_WDOG_JABDISABLE	0x00000001
+#define AL_WDOG_NONJABBER	0x00000002
+#define AL_WDOG_JABCLK		0x00000004
+#define AL_WDOG_RXWDOG_DIS	0x00000010
+#define AL_WDOG_RXWDOG_REL	0x00000020
+
+/*
+ * Assistant status register.
+ */
+#define AL_ISR2_ABNORMAL	0x00008000
+#define AL_ISR2_NORMAL		0x00010000
+#define AL_ISR2_RX_STATE	0x000E0000
+#define AL_ISR2_TX_STATE	0x00700000
+#define AL_ISR2_BUSERRTYPE	0x03800000
+#define AL_ISR2_PAUSE		0x04000000	/* PAUSE frame received */
+#define AL_ISR2_TX_DEFER	0x10000000
+#define AL_ISR2_XCVR_INT	0x20000000
+#define AL_ISR2_RX_EARLY	0x40000000
+#define AL_ISR2_TX_EARLY	0x80000000
+
+/*
+ * Assistant mask register.
+ */
+#define AL_IMR2_ABNORMAL	0x00008000
+#define AL_IMR2_NORMAL		0x00010000
+#define AL_IMR2_PAUSE		0x04000000	/* PAUSE frame received */
+#define AL_IMR2_TX_DEFER	0x10000000
+#define AL_IMR2_XCVR_INT	0x20000000
+#define AL_IMR2_RX_EARLY	0x40000000
+#define AL_IMR2_TX_EARLY	0x80000000
+
+/*
+ * Command register, some bits loaded from EEPROM.
+ */
+#define AL_CMD_TXURUN_REC	0x00000001 /* enable TX underflow recovery */
+#define AL_CMD_SOFTWARE_INT	0x00000002 /* software interrupt */
+#define AL_CMD_DRT		0x0000000C /* drain receive threshold */
+#define AL_CMD_RXTHRESH_ENB	0x00000010 /* rx threshold enable */
+#define AL_CMD_PAUSE		0x00000020
+#define AL_CMD_RST_WU_PTR	0x00000040 /* reset wakeup pattern reg. */
+/* Values below loaded from EEPROM. */
+#define AL_CMD_WOL_ENB		0x00040000 /* WOL enable */
+#define AL_CMD_PM_ENB		0x00080000 /* pwr mgmt enable */
+#define AL_CMD_RX_FIFO		0x00300000
+#define AL_CMD_LED_MODE		0x00400000
+#define AL_CMD_CURRENT_MODE	0x70000000
+#define AL_CMD_D3COLD		0x80000000
+
+/*
+ * PCI performance counter.
+ */
+#define AL_PCI_DW_CNT		0x000000FF
+#define AL_PCI_CLK		0xFFFF0000
+
+/*
+ * Power management command and status.
+ */
+#define AL_PWRM_PWR_STATE	0x00000003
+#define AL_PWRM_PME_EN		0x00000100
+#define AL_PWRM_DSEL		0x00001E00
+#define AL_PWRM_DSCALE		0x00006000
+#define AL_PWRM_PME_STAT	0x00008000
+
+/*
+ * TX burst count / timeout register.
+ */
+#define AL_TXB_TIMEO		0x00000FFF
+#define AL_TXB_BURSTCNT		0x0000F000
+
+/*
+ * Flash PROM register.
+ */
+#define AL_PROM_DATA		0x0000000F
+#define AL_PROM_ADDR		0x01FFFFF0
+#define AL_PROM_WR_ENB		0x04000000
+#define AL_PROM_BRA16_ON	0x80000000
+
+/*
+ * COMET TX/RX list structure.
+ */
+
+struct al_desc {
+	volatile u_int32_t	al_status;
+	volatile u_int32_t	al_ctl;
+	volatile u_int32_t	al_ptr1;
+	volatile u_int32_t	al_ptr2;
+};
+
+#define al_data		al_ptr1
+#define al_next		al_ptr2
+
+#define AL_RXSTAT_FIFOOFLOW	0x00000001
+#define AL_RXSTAT_CRCERR	0x00000002
+#define AL_RXSTAT_DRIBBLE	0x00000004
+#define AL_RXSTAT_WATCHDOG	0x00000010
+#define AL_RXSTAT_FRAMETYPE	0x00000020	/* 0 == IEEE 802.3 */
+#define AL_RXSTAT_COLLSEEN	0x00000040
+#define AL_RXSTAT_GIANT		0x00000080
+#define AL_RXSTAT_LASTFRAG	0x00000100
+#define AL_RXSTAT_FIRSTFRAG	0x00000200
+#define AL_RXSTAT_MULTICAST	0x00000400
+#define AL_RXSTAT_RUNT		0x00000800
+#define AL_RXSTAT_RXTYPE	0x00003000
+#define AL_RXSTAT_RXERR		0x00008000
+#define AL_RXSTAT_RXLEN		0x3FFF0000
+#define AL_RXSTAT_OWN		0x80000000
+
+#define AL_RXBYTES(x)		((x & AL_RXSTAT_RXLEN) >> 16)
+#define AL_RXSTAT (AL_RXSTAT_FIRSTFRAG|AL_RXSTAT_LASTFRAG|AL_RXSTAT_OWN)
+
+#define AL_RXCTL_BUFLEN1	0x00000FFF
+#define AL_RXCTL_BUFLEN2	0x00FFF000
+#define AL_RXCTL_RLAST		0x02000000
+
+#define AL_TXSTAT_DEFER		0x00000001
+#define AL_TXSTAT_UNDERRUN	0x00000002
+#define AL_TXSTAT_LINKFAIL	0x00000003
+#define AL_TXSTAT_COLLCNT	0x00000078
+#define AL_TXSTAT_SQE		0x00000080
+#define AL_TXSTAT_EXCESSCOLL	0x00000100
+#define AL_TXSTAT_LATECOLL	0x00000200
+#define AL_TXSTAT_NOCARRIER	0x00000400
+#define AL_TXSTAT_CARRLOST	0x00000800
+#define AL_TXSTAT_JABTIMEO	0x00004000
+#define AL_TXSTAT_ERRSUM	0x00008000
+#define AL_TXSTAT_OWN		0x80000000
+
+#define AL_TXCTL_BUFLEN1	0x000007FF
+#define AL_TXCTL_BUFLEN2	0x003FF800
+#define AL_TXCTL_PAD		0x00800000
+#define AL_TXCTL_TLINK		0x01000000
+#define AL_TXCTL_TLAST		0x02000000
+#define AL_TXCTL_NOCRC		0x04000000
+#define AL_TXCTL_FIRSTFRAG	0x20000000
+#define AL_TXCTL_LASTFRAG	0x40000000
+#define AL_TXCTL_FINT		0x80000000
+
+#define AL_MAXFRAGS		16
+#define AL_RX_LIST_CNT		64
+#define AL_TX_LIST_CNT		128
+#define AL_MIN_FRAMELEN		60
+
+/*
+ * A tx 'super descriptor' is actually 16 regular descriptors
+ * back to back.
+ */
+struct al_txdesc {
+	volatile struct al_desc	al_frag[AL_MAXFRAGS];
+};
+
+#define AL_TXNEXT(x)	x->al_ptr->al_frag[x->al_lastdesc].al_next
+#define AL_TXSTATUS(x)	x->al_ptr->al_frag[x->al_lastdesc].al_status
+#define AL_TXCTL(x)	x->al_ptr->al_frag[x->al_lastdesc].al_ctl
+#define AL_TXDATA(x)	x->al_ptr->al_frag[x->al_lastdesc].al_data
+
+#define AL_TXOWN(x)	x->al_ptr->al_frag[0].al_status
+
+#define AL_UNSENT	0x12341234
+
+struct al_list_data {
+	volatile struct al_desc		al_rx_list[AL_RX_LIST_CNT];
+	volatile struct al_txdesc	al_tx_list[AL_TX_LIST_CNT];
+};
+
+struct al_chain {
+	volatile struct al_txdesc	*al_ptr;
+	struct mbuf			*al_mbuf;
+	struct al_chain			*al_nextdesc;
+	u_int8_t			al_lastdesc;
+};
+
+struct al_chain_onefrag {
+	volatile struct al_desc	*al_ptr;
+	struct mbuf		*al_mbuf;
+	struct al_chain_onefrag	*al_nextdesc;
+};
+
+struct al_chain_data {
+	struct al_chain_onefrag	al_rx_chain[AL_RX_LIST_CNT];
+	struct al_chain		al_tx_chain[AL_TX_LIST_CNT];
+
+	struct al_chain_onefrag	*al_rx_head;
+
+	struct al_chain		*al_tx_head;
+	struct al_chain		*al_tx_tail;
+	struct al_chain		*al_tx_free;
+};
+
+struct al_type {
+	u_int16_t		al_vid;
+	u_int16_t		al_did;
+	char			*al_name;
+};
+
+struct al_mii_frame {
+	u_int8_t		mii_stdelim;
+	u_int8_t		mii_opcode;
+	u_int8_t		mii_phyaddr;
+	u_int8_t		mii_regaddr;
+	u_int8_t		mii_turnaround;
+	u_int16_t		mii_data;
+};
+
+/*
+ * MII constants
+ */
+#define AL_MII_STARTDELIM	0x01
+#define AL_MII_READOP		0x02
+#define AL_MII_WRITEOP		0x01
+#define AL_MII_TURNAROUND	0x02
+
+#define AL_FLAG_FORCEDELAY	1
+#define AL_FLAG_SCHEDDELAY	2
+#define AL_FLAG_DELAYTIMEO	3	
+
+struct al_softc {
+	struct arpcom		arpcom;		/* interface info */
+	struct ifmedia		ifmedia;	/* media info */
+	bus_space_handle_t	al_bhandle;	/* bus space handle */
+	bus_space_tag_t		al_btag;	/* bus space tag */
+	struct al_type		*al_info;	/* COMET adapter info */
+	struct al_type		*al_pinfo;	/* phy info */
+	u_int8_t		al_unit;	/* interface number */
+	u_int8_t		al_type;
+	u_int8_t		al_phy_addr;	/* PHY address */
+	u_int8_t		al_tx_pend;	/* TX pending */
+	u_int8_t		al_want_auto;
+	u_int8_t		al_autoneg;
+	caddr_t			al_ldata_ptr;
+	struct al_list_data	*al_ldata;
+	struct al_chain_data	al_cdata;
+	u_int8_t		al_cachesize;
+};
+
+/*
+ * register space access macros
+ */
+#define CSR_WRITE_4(sc, reg, val)	\
+	bus_space_write_4(sc->al_btag, sc->al_bhandle, reg, val)
+#define CSR_WRITE_2(sc, reg, val)	\
+	bus_space_write_2(sc->al_btag, sc->al_bbhandle, reg, val)
+#define CSR_WRITE_1(sc, reg, val)	\
+	bus_space_write_1(sc->al_btag, sc->al_bhandle, reg, val)
+
+#define CSR_READ_4(sc, reg)		\
+	bus_space_read_4(sc->al_btag, sc->al_bhandle, reg)
+#define CSR_READ_2(sc, reg)		\
+	bus_space_read_2(sc->al_btag, sc->al_bhandle, reg)
+#define CSR_READ_1(sc, reg)		\
+	bus_space_read_1(sc->al_btag, sc->al_bhandle, reg)
+
+#define AL_TIMEOUT		1000
+
+/*
+ * General constants that are fun to know.
+ *
+ * ADMtek PCI vendor ID
+ */
+#define	AL_VENDORID		0x1317
+
+/*
+ * AL981 device IDs.
+ */
+#define AL_DEVICEID_AL981	0x0981
+
+/*
+ * Texas Instruments PHY identifiers
+ */
+#define TI_PHY_VENDORID		0x4000
+#define TI_PHY_10BT		0x501F
+#define TI_PHY_100VGPMI		0x502F
+
+/*
+ * These ID values are for the NS DP83840A 10/100 PHY
+ */
+#define NS_PHY_VENDORID		0x2000
+#define NS_PHY_83840A		0x5C0F
+
+/*
+ * Level 1 10/100 PHY
+ */
+#define LEVEL1_PHY_VENDORID	0x7810
+#define LEVEL1_PHY_LXT970	0x000F
+
+/*
+ * Intel 82555 10/100 PHY
+ */
+#define INTEL_PHY_VENDORID	0x0A28
+#define INTEL_PHY_82555		0x015F
+
+/*
+ * SEEQ 80220 10/100 PHY
+ */
+#define SEEQ_PHY_VENDORID	0x0016
+#define SEEQ_PHY_80220		0xF83F
+
+
+/*
+ * PCI low memory base and low I/O base register, and
+ * other PCI registers.
+ */
+
+#define AL_PCI_VENDOR_ID	0x00
+#define AL_PCI_DEVICE_ID	0x02
+#define AL_PCI_COMMAND		0x04
+#define AL_PCI_STATUS		0x06
+#define AL_PCI_REVID		0x08
+#define AL_PCI_CLASSCODE	0x09
+#define AL_PCI_CACHELEN		0x0C
+#define AL_PCI_LATENCY_TIMER	0x0D
+#define AL_PCI_HEADER_TYPE	0x0E
+#define AL_PCI_LOIO		0x10
+#define AL_PCI_LOMEM		0x14
+#define AL_PCI_BIOSROM		0x30
+#define AL_PCI_INTLINE		0x3C
+#define AL_PCI_INTPIN		0x3D
+#define AL_PCI_MINGNT		0x3E
+#define AL_PCI_MINLAT		0x0F
+#define AL_PCI_RESETOPT		0x48
+#define AL_PCI_EEPROM_DATA	0x4C
+
+/* power management registers */
+#define AL_PCI_CAPID		0x44 /* 8 bits */
+#define AL_PCI_NEXTPTR		0x45 /* 8 bits */
+#define AL_PCI_PWRMGMTCAP	0x46 /* 16 bits */
+#define AL_PCI_PWRMGMTCTRL	0x48 /* 16 bits */
+
+#define AL_PSTATE_MASK		0x0003
+#define AL_PSTATE_D0		0x0000
+#define AL_PSTATE_D1		0x0001
+#define AL_PSTATE_D2		0x0002
+#define AL_PSTATE_D3		0x0003
+#define AL_PME_EN		0x0010
+#define AL_PME_STATUS		0x8000
+
+#define PHY_UNKNOWN		6
+
+#define AL_PHYADDR_MIN		0x00
+#define AL_PHYADDR_MAL		0x1F
+
+#define PHY_BMCR		0x00
+#define PHY_BMSR		0x01
+#define PHY_VENID		0x02
+#define PHY_DEVID		0x03
+#define PHY_ANAR		0x04
+#define PHY_LPAR		0x05
+#define PHY_ANEXP		0x06
+
+#define PHY_ANAR_NEXTPAGE	0x8000
+#define PHY_ANAR_RSVD0		0x4000
+#define PHY_ANAR_TLRFLT		0x2000
+#define PHY_ANAR_RSVD1		0x1000
+#define PHY_ANAR_RSVD2		0x0800
+#define PHY_ANAR_RSVD3		0x0400
+#define PHY_ANAR_100BT4		0x0200
+#define PHY_ANAR_100BTXFULL	0x0100
+#define PHY_ANAR_100BTXHALF	0x0080
+#define PHY_ANAR_10BTFULL	0x0040
+#define PHY_ANAR_10BTHALF	0x0020
+#define PHY_ANAR_PROTO4		0x0010
+#define PHY_ANAR_PROTO3		0x0008
+#define PHY_ANAR_PROTO2		0x0004
+#define PHY_ANAR_PROTO1		0x0002
+#define PHY_ANAR_PROTO0		0x0001
+
+/*
+ * These are the register definitions for the PHY (physical layer
+ * interface chip).
+ */
+/*
+ * PHY BMCR Basic Mode Control Register
+ */
+#define PHY_BMCR_RESET			0x8000
+#define PHY_BMCR_LOOPBK			0x4000
+#define PHY_BMCR_SPEEDSEL		0x2000
+#define PHY_BMCR_AUTONEGENBL		0x1000
+#define PHY_BMCR_RSVD0			0x0800	/* write as zero */
+#define PHY_BMCR_ISOLATE		0x0400
+#define PHY_BMCR_AUTONEGRSTR		0x0200
+#define PHY_BMCR_DUPLEX			0x0100
+#define PHY_BMCR_COLLTEST		0x0080
+#define PHY_BMCR_RSVD1			0x0040	/* write as zero, don't care */
+#define PHY_BMCR_RSVD2			0x0020	/* write as zero, don't care */
+#define PHY_BMCR_RSVD3			0x0010	/* write as zero, don't care */
+#define PHY_BMCR_RSVD4			0x0008	/* write as zero, don't care */
+#define PHY_BMCR_RSVD5			0x0004	/* write as zero, don't care */
+#define PHY_BMCR_RSVD6			0x0002	/* write as zero, don't care */
+#define PHY_BMCR_RSVD7			0x0001	/* write as zero, don't care */
+/*
+ * RESET: 1 == software reset, 0 == normal operation
+ * Resets status and control registers to default values.
+ * Relatches all hardware config values.
+ *
+ * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
+ *
+ * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
+ * Link speed is selected byt his bit or if auto-negotiation if bit
+ * 12 (AUTONEGENBL) is set (in which case the value of this register
+ * is ignored).
+ *
+ * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
+ * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
+ * determine speed and mode. Should be cleared and then set if PHY configured
+ * for no autoneg on startup.
+ *
+ * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
+ *
+ * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
+ *
+ * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
+ *
+ * COLLTEST: 1 == collision test enabled, 0 == normal operation
+ */
+
+/* 
+ * PHY, BMSR Basic Mode Status Register 
+ */   
+#define PHY_BMSR_100BT4			0x8000
+#define PHY_BMSR_100BTXFULL		0x4000
+#define PHY_BMSR_100BTXHALF		0x2000
+#define PHY_BMSR_10BTFULL		0x1000
+#define PHY_BMSR_10BTHALF		0x0800
+#define PHY_BMSR_RSVD1			0x0400	/* write as zero, don't care */
+#define PHY_BMSR_RSVD2			0x0200	/* write as zero, don't care */
+#define PHY_BMSR_RSVD3			0x0100	/* write as zero, don't care */
+#define PHY_BMSR_RSVD4			0x0080	/* write as zero, don't care */
+#define PHY_BMSR_MFPRESUP		0x0040
+#define PHY_BMSR_AUTONEGCOMP		0x0020
+#define PHY_BMSR_REMFAULT		0x0010
+#define PHY_BMSR_CANAUTONEG		0x0008
+#define PHY_BMSR_LINKSTAT		0x0004
+#define PHY_BMSR_JABBER			0x0002
+#define PHY_BMSR_EXTENDED		0x0001
+
+#ifdef __alpha__
+#undef vtophys
+#define vtophys(va)		(pmap_kextract(((vm_offset_t) (va))) \
+					+ 1*1024*1024*1024)
+#endif
diff --git a/usr.sbin/sade/devices.c b/usr.sbin/sade/devices.c
index bf4af72..be7a729 100644
--- a/usr.sbin/sade/devices.c
+++ b/usr.sbin/sade/devices.c
@@ -4,7 +4,7 @@
  * This is probably the last program in the `sysinstall' line - the next
  * generation being essentially a complete rewrite.
  *
- * $Id: devices.c,v 1.89 1999/04/06 08:25:52 jkh Exp $
+ * $Id: devices.c,v 1.90 1999/04/06 17:08:29 wpaul Exp $
  *
  * Copyright (c) 1995
  *	Jordan Hubbard.  All rights reserved.
@@ -80,6 +80,7 @@ static struct _devname {
     { DEVICE_TYPE_FLOPPY,	"fd%d",		"floppy drive unit A",	2, 0, 64, 4, 'b'			},
     { DEVICE_TYPE_FLOPPY,	"wfd%d",	"ATAPI floppy drive unit A",	1, 0, 8, 4, 'b'			},
     { DEVICE_TYPE_FLOPPY,	"worm%d",	"SCSI optical disk / CDR",	23, 0, 1, 4, 'b'		},
+    { DEVICE_TYPE_NETWORK,	"al",		"ADMtek AL981 PCI ethernet card"				},
     { DEVICE_TYPE_NETWORK,	"ax",		"ASIX AX88140A PCI ethernet card"				},
     { DEVICE_TYPE_NETWORK,	"fpa",		"DEC DEFPA PCI FDDI card"					},
     { DEVICE_TYPE_NETWORK,	"sr",		"SDL T1/E1 sync serial PCI card"				},
diff --git a/usr.sbin/sysinstall/devices.c b/usr.sbin/sysinstall/devices.c
index bf4af72..be7a729 100644
--- a/usr.sbin/sysinstall/devices.c
+++ b/usr.sbin/sysinstall/devices.c
@@ -4,7 +4,7 @@
  * This is probably the last program in the `sysinstall' line - the next
  * generation being essentially a complete rewrite.
  *
- * $Id: devices.c,v 1.89 1999/04/06 08:25:52 jkh Exp $
+ * $Id: devices.c,v 1.90 1999/04/06 17:08:29 wpaul Exp $
  *
  * Copyright (c) 1995
  *	Jordan Hubbard.  All rights reserved.
@@ -80,6 +80,7 @@ static struct _devname {
     { DEVICE_TYPE_FLOPPY,	"fd%d",		"floppy drive unit A",	2, 0, 64, 4, 'b'			},
     { DEVICE_TYPE_FLOPPY,	"wfd%d",	"ATAPI floppy drive unit A",	1, 0, 8, 4, 'b'			},
     { DEVICE_TYPE_FLOPPY,	"worm%d",	"SCSI optical disk / CDR",	23, 0, 1, 4, 'b'		},
+    { DEVICE_TYPE_NETWORK,	"al",		"ADMtek AL981 PCI ethernet card"				},
     { DEVICE_TYPE_NETWORK,	"ax",		"ASIX AX88140A PCI ethernet card"				},
     { DEVICE_TYPE_NETWORK,	"fpa",		"DEC DEFPA PCI FDDI card"					},
     { DEVICE_TYPE_NETWORK,	"sr",		"SDL T1/E1 sync serial PCI card"				},