diff options
| author | adrian <adrian@FreeBSD.org> | 2012-07-29 09:23:32 +0000 |
|---|---|---|
| committer | adrian <adrian@FreeBSD.org> | 2012-07-29 09:23:32 +0000 |
| commit | 6009a2eb434a1c413557b4d2bc90c32da1b6e1d4 (patch) | |
| tree | 5eb387792d6449c527bb0b7a9d89d18030eabb0e | |
| parent | 42e4d592441c659494072ebb7868dfa5f52299b8 (diff) | |
| download | FreeBSD-src-6009a2eb434a1c413557b4d2bc90c32da1b6e1d4.zip FreeBSD-src-6009a2eb434a1c413557b4d2bc90c32da1b6e1d4.tar.gz | |
Shuffle the rate control call to be consistent with non-aggregate TX.
The correct ordering for non-aggregate TX is:
* call ath_hal_setuptxdesc() to setup the first TX descriptor complete
with the first TX rate/try count;
* call ath_hal_setupxtxdesc() to setup the multi-rate retry;
* .. or for 802.11n NICs, call ath_hal_set11nratescenario() for MRR and
802.11n flags;
* then call ath_hal_filltxdesc() to setup intermediary descriptors
in a multi-descriptor single frame.
The call to ath_hal_filltxdesc() routines seem to correctly (consistently?)
handle the intermediary descriptor flags, including copying the rate
control information to the final descriptor in the frame. That's used
by the rate control module rather than the hardware.
Tested:
* Only on AR9280 STA mode, however it should work on other chips in
both STA and AP mode.
| -rw-r--r-- | sys/dev/ath/if_ath_tx.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sys/dev/ath/if_ath_tx.c b/sys/dev/ath/if_ath_tx.c index c0dfa2b..149b4f1 100644 --- a/sys/dev/ath/if_ath_tx.c +++ b/sys/dev/ath/if_ath_tx.c @@ -3895,9 +3895,9 @@ ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an, ath_tx_set_rtscts(sc, bf); ath_tx_rate_fill_rcflags(sc, bf); ath_tx_setds(sc, bf); + ath_tx_set_ratectrl(sc, ni, bf); ath_tx_chaindesclist(sc, bf); ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); - ath_tx_set_ratectrl(sc, ni, bf); sc->sc_aggr_stats.aggr_nonbaw_pkt++; @@ -3955,9 +3955,9 @@ ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an, "%s: single-frame aggregate\n", __func__); bf->bf_state.bfs_aggr = 0; ath_tx_setds(sc, bf); + ath_tx_set_ratectrl(sc, ni, bf); ath_tx_chaindesclist(sc, bf); ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); - ath_tx_set_ratectrl(sc, ni, bf); if (status == ATH_AGGR_BAW_CLOSED) sc->sc_aggr_stats.aggr_baw_closed_single_pkt++; else @@ -4084,8 +4084,8 @@ ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an, ath_tx_set_rtscts(sc, bf); ath_tx_rate_fill_rcflags(sc, bf); ath_tx_setds(sc, bf); - ath_tx_chaindesclist(sc, bf); ath_tx_set_ratectrl(sc, ni, bf); + ath_tx_chaindesclist(sc, bf); /* Track outstanding buffer count to hardware */ /* aggregates are "one" buffer */ |
