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| author | marcel <marcel@FreeBSD.org> | 2006-07-26 17:29:37 +0000 |
|---|---|---|
| committer | marcel <marcel@FreeBSD.org> | 2006-07-26 17:29:37 +0000 |
| commit | 5c244cdde1372808f85f903d7ff74f651c6fd00f (patch) | |
| tree | a1491563662d72aa013c63d8c3ab0b0ef6c4b12a | |
| parent | 9552f61e79c935125c356acdcec65fbd3b1468c0 (diff) | |
| download | FreeBSD-src-5c244cdde1372808f85f903d7ff74f651c6fd00f.zip FreeBSD-src-5c244cdde1372808f85f903d7ff74f651c6fd00f.tar.gz | |
On PowerPC the clock for the BRG comes from RTxC, not PCLK. Add a
quick hack to deal with this. We may need to formalize this better
and have this information come from the bus attachments.
| -rw-r--r-- | sys/dev/uart/uart_dev_z8530.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/sys/dev/uart/uart_dev_z8530.c b/sys/dev/uart/uart_dev_z8530.c index 49b152b..04ebc69 100644 --- a/sys/dev/uart/uart_dev_z8530.c +++ b/sys/dev/uart/uart_dev_z8530.c @@ -43,6 +43,13 @@ __FBSDID("$FreeBSD$"); #define DEFAULT_RCLK 307200 +/* Hack! */ +#ifdef __powerpc__ +#define UART_PCLK 0 +#else +#define UART_PCLK MCB2_PCLK +#endif + /* Multiplexed I/O. */ static __inline void uart_setmreg(struct uart_bas *bas, int reg, int val) @@ -124,7 +131,7 @@ z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, } else divisor = -1; - uart_setmreg(bas, WR_MCB2, MCB2_PCLK); + uart_setmreg(bas, WR_MCB2, UART_PCLK); uart_barrier(bas); if (divisor >= 0) { @@ -140,7 +147,7 @@ z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, uart_barrier(bas); uart_setmreg(bas, WR_TPC, tpc); uart_barrier(bas); - uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE); + uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE); uart_barrier(bas); *tpcp = tpc; return (0); @@ -167,7 +174,7 @@ z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, uart_barrier(bas); /* Set clock sources. */ uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); - uart_setmreg(bas, WR_MCB2, MCB2_PCLK); + uart_setmreg(bas, WR_MCB2, UART_PCLK); uart_barrier(bas); /* Set data encoding. */ uart_setmreg(bas, WR_MCB1, MCB1_NRZ); |
