Revert "MFC r327964:"

This reverts commit 75492dc7653f9d5eb0e33bc8277957739f587ff0.

3 files changed, 2 insertions, 50 deletions

diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h
index b897b42..77f01cd 100644
--- a/sys/x86/include/specialreg.h
+++ b/sys/x86/include/specialreg.h
@@ -383,17 +383,6 @@
 #define	CPUID_STDEXT2_SGXLC	0x40000000
 
 /*
- * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
- */
-#define	CPUID_STDEXT3_IBPB	0x04000000
-#define	CPUID_STDEXT3_STIBP	0x08000000
-#define	CPUID_STDEXT3_ARCH_CAP	0x20000000
-
-/* MSR IA32_ARCH_CAP(ABILITIES) bits */
-#define	IA32_ARCH_CAP_RDCL_NO	0x00000001
-#define	IA32_ARCH_CAP_IBRS_ALL	0x00000002
-
-/*
  * CPUID manufacturers identifiers
  */
 #define	AMD_VENDOR_ID		"AuthenticAMD"
@@ -421,8 +410,6 @@
 #define	MSR_EBL_CR_POWERON	0x02a
 #define	MSR_TEST_CTL		0x033
 #define	MSR_IA32_FEATURE_CONTROL 0x03a
-#define	MSR_IA32_SPEC_CTRL	0x048
-#define	MSR_IA32_PRED_CMD	0x049
 #define	MSR_BIOS_UPDT_TRIG	0x079
 #define	MSR_BBL_CR_D0		0x088
 #define	MSR_BBL_CR_D1		0x089
@@ -435,7 +422,6 @@
 #define	MSR_APERF		0x0e8
 #define	MSR_IA32_EXT_CONFIG	0x0ee	/* Undocumented. Core Solo/Duo only */
 #define	MSR_MTRRcap		0x0fe
-#define	MSR_IA32_ARCH_CAP	0x10a
 #define	MSR_BBL_CR_ADDR		0x116
 #define	MSR_BBL_CR_DECC		0x118
 #define	MSR_BBL_CR_CTL		0x119
@@ -578,13 +564,6 @@
 #define	IA32_MISC_EN_xTPRD	0x0000000000800000ULL
 #define	IA32_MISC_EN_XDD	0x0000000400000000ULL
 
-/* MSR IA32_SPEC_CTRL */
-#define	IA32_SPEC_CTRL_IBRS	0x0000000000000001ULL
-#define	IA32_SPEC_CTRL_STIBP	0x0000000000000002ULL
-
-/* MSR IA32_PRED_CMD */
-#define	IA32_PRED_CMD_IBPB_BARRIER	0x0000000000000001ULL
-
 /*
  * PAT modes.
  */
diff --git a/sys/x86/include/x86_var.h b/sys/x86/include/x86_var.h
index 0f720b3..73a24c7 100644
--- a/sys/x86/include/x86_var.h
+++ b/sys/x86/include/x86_var.h
@@ -51,8 +51,6 @@ extern	u_int	via_feature_xcrypt;
 extern	u_int	cpu_clflush_line_size;
 extern	u_int	cpu_stdext_feature;
 extern	u_int	cpu_stdext_feature2;
-extern	u_int	cpu_stdext_feature3;
-extern	uint64_t cpu_ia32_arch_caps;
 extern	u_int	cpu_fxsr;
 extern	u_int	cpu_high;
 extern	u_int	cpu_id;
diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c
index 033f873..d2fc82b 100644
--- a/sys/x86/x86/identcpu.c
+++ b/sys/x86/x86/identcpu.c
@@ -105,10 +105,8 @@ u_int	cpu_vendor_id;		/* CPU vendor ID */
 u_int	cpu_fxsr;		/* SSE enabled */
 u_int	cpu_mxcsr_mask;		/* Valid bits in mxcsr */
 u_int	cpu_clflush_line_size = 32;
-u_int	cpu_stdext_feature;	/* %ebx */
-u_int	cpu_stdext_feature2;	/* %ecx */
-u_int	cpu_stdext_feature3;	/* %edx */
-uint64_t cpu_ia32_arch_caps;
+u_int	cpu_stdext_feature;
+u_int	cpu_stdext_feature2;
 u_int	cpu_max_ext_state_size;
 u_int	cpu_mon_mwait_flags;	/* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 u_int	cpu_mon_min_size;	/* MONITOR minimum range size, bytes */
@@ -982,16 +980,6 @@ printcpuinfo(void)
 				       );
 			}
 
-			if (cpu_stdext_feature3 != 0) {
-				printf("\n  Structured Extended Features3=0x%b",
-				    cpu_stdext_feature3,
-				       "\020"
-				       "\033IBPB"
-				       "\034STIBP"
-				       "\036ARCH_CAP"
-				       );
-			}
-
 			if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 				cpuid_count(0xd, 0x1, regs);
 				if (regs[0] != 0) {
@@ -1005,15 +993,6 @@ printcpuinfo(void)
 				}
 			}
 
-			if (cpu_ia32_arch_caps != 0) {
-				printf("\n  IA32_ARCH_CAPS=0x%b",
-				    (u_int)cpu_ia32_arch_caps,
-				       "\020"
-				       "\001RDCL_NO"
-				       "\002IBRS_ALL"
-				       );
-			}
-
 			if (amd_extended_feature_extensions != 0) {
 				printf("\n  "
 				    "AMD Extended Feature Extensions ID EBX="
@@ -1442,10 +1421,6 @@ identify_cpu2(void)
 		cpu_stdext_feature &= ~cpu_stdext_disable;
 
 		cpu_stdext_feature2 = regs[2];
-		cpu_stdext_feature3 = regs[3];
-
-		if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
-			cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
 	}
 }