ARM: Remove support for xscale i80219 and i80321 CPUs. We haven't single

supported config/board with these CPUs.

37 files changed, 29 insertions, 5436 deletions

diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 514a6b1..2b226ef 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -60,18 +60,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/cpuconf.h>
 #include <machine/cpufunc.h>
 
-#if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-#endif
-
-/*
- * Some definitions in i81342reg.h clash with i80321reg.h.
- * This only happens for the LINT kernel. As it happens,
- * we don't need anything from i81342reg.h that we already
- * got from somewhere else during a LINT compile.
- */
-#if defined(CPU_XSCALE_81342) && !defined(COMPILING_LINT)
+#if defined(CPU_XSCALE_81342)
 #include <arm/xscale/i8134x/i81342reg.h>
 #endif
 
@@ -306,9 +295,7 @@ struct cpu_functions pj4bv7_cpufuncs = {
 };
 #endif /* CPU_MV_PJ4B */
 
-#if defined(CPU_XSCALE_80321) || \
-  defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
-  defined(CPU_XSCALE_80219)
+#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
 
 struct cpu_functions xscale_cpufuncs = {
 	/* CPU functions */
@@ -359,8 +346,7 @@ struct cpu_functions xscale_cpufuncs = {
 	xscale_setup			/* cpu setup		*/
 };
 #endif
-/* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
-   CPU_XSCALE_80219 */
+/* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
 
 #ifdef CPU_XSCALE_81342
 struct cpu_functions xscalec3_cpufuncs = {
@@ -588,10 +574,10 @@ u_int cpu_reset_needs_v4_MMU_disable;	/* flag used in locore.s */
 
 #if defined(CPU_ARM9) ||	\
   defined (CPU_ARM9E) ||	\
-  defined(CPU_ARM1176) || defined(CPU_XSCALE_80321) ||		\
+  defined(CPU_ARM1176) ||	\
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
   defined(CPU_FA526) || defined(CPU_MV_PJ4B) ||			\
-  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
+  defined(CPU_XSCALE_81342) || \
   defined(CPU_CORTEXA) || defined(CPU_KRAIT)
 
 /* Global cache line sizes, use 32 as default */
@@ -829,18 +815,6 @@ set_cpufuncs()
 	}
 #endif	/* CPU_FA526 */
 
-#if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
-	if (cputype == CPU_ID_80321_400 || cputype == CPU_ID_80321_600 ||
-	    cputype == CPU_ID_80321_400_B0 || cputype == CPU_ID_80321_600_B0 ||
-	    cputype == CPU_ID_80219_400 || cputype == CPU_ID_80219_600) {
-		cpufuncs = xscale_cpufuncs;
-		cpu_reset_needs_v4_MMU_disable = 1;	/* XScale needs it */
-		get_cachetype_cp15();
-		pmap_pte_init_xscale();
-		goto out;
-	}
-#endif /* CPU_XSCALE_80321 */
-
 #if defined(CPU_XSCALE_81342)
 	if (cputype == CPU_ID_81342) {
 		cpufuncs = xscalec3_cpufuncs;
@@ -1207,9 +1181,8 @@ fa526_setup(void)
 }
 #endif	/* CPU_FA526 */
 
-#if defined(CPU_XSCALE_80321) || \
-  defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
-  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
+#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
+  defined(CPU_XSCALE_81342)
 void
 xscale_setup(void)
 {
@@ -1276,5 +1249,4 @@ xscale_setup(void)
 	__asm __volatile("mcr p15, 0, %0, c1, c0, 1"
 		: : "r" (auxctl));
 }
-#endif	/* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
-	   CPU_XSCALE_80219 */
+#endif	/* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
diff --git a/sys/arm/arm/elf_trampoline.c b/sys/arm/arm/elf_trampoline.c
index 6c086ea..e25a849 100644
--- a/sys/arm/arm/elf_trampoline.c
+++ b/sys/arm/arm/elf_trampoline.c
@@ -67,9 +67,7 @@ extern void fa526_idcache_wbinv_all(void);
 extern void armv5_ec_idcache_wbinv_all(void);
 #elif defined(CPU_ARM1176)
 #define cpu_idcache_wbinv_all	armv6_idcache_wbinv_all
-#elif defined(CPU_XSCALE_80321) || \
-  defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
-  defined(CPU_XSCALE_80219)
+#elif defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
 #define cpu_idcache_wbinv_all	xscale_cache_purgeID
 extern void xscale_cache_purgeID(void);
 #elif defined(CPU_XSCALE_81342)
diff --git a/sys/arm/conf/NOTES b/sys/arm/conf/NOTES
index f4259f2..db64f8e 100644
--- a/sys/arm/conf/NOTES
+++ b/sys/arm/conf/NOTES
@@ -5,8 +5,6 @@ machine	arm
 cpu	CPU_ARM9
 cpu	CPU_ARM9E
 cpu	CPU_FA526
-cpu 	CPU_XSCALE_80219
-cpu 	CPU_XSCALE_80321
 cpu 	CPU_XSCALE_81342
 cpu 	CPU_XSCALE_IXP425
 cpu 	CPU_XSCALE_IXP435
diff --git a/sys/arm/include/cpuconf.h b/sys/arm/include/cpuconf.h
index ecee280..24a3b8f 100644
--- a/sys/arm/include/cpuconf.h
+++ b/sys/arm/include/cpuconf.h
@@ -53,7 +53,6 @@
 #define	CPU_NTYPES	(defined(CPU_ARM9) +				\
 			 defined(CPU_ARM9E) +				\
 			 defined(CPU_ARM1176) +				\
-			 defined(CPU_XSCALE_80321) +			\
 			 defined(CPU_XSCALE_PXA2X0) +			\
 			 defined(CPU_FA526) +				\
 			 defined(CPU_XSCALE_IXP425)) +			\
@@ -71,8 +70,7 @@
 #endif
 
 #if (defined(CPU_ARM9E) ||						\
-     defined(CPU_XSCALE_80321) ||					\
-     defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) ||		\
+     defined(CPU_XSCALE_81342) ||					\
      defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
 #define	ARM_ARCH_5	1
 #else
@@ -163,9 +161,8 @@
 #define ARM_MMU_V7		0
 #endif
 
-#if (defined(CPU_XSCALE_80321) ||					\
-     defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
-     defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
+#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
+     defined(CPU_XSCALE_81342))
 #define	ARM_MMU_XSCALE		1
 #else
 #define	ARM_MMU_XSCALE		0
@@ -180,11 +177,10 @@
 /*
  * Step 4: Define features that may be present on a subset of CPUs
  *
- *	ARM_XSCALE_PMU		Performance Monitoring Unit on 80200 and 80321
+ *	ARM_XSCALE_PMU		Performance Monitoring Unit on 81342
  */
 
-#if (defined(CPU_XSCALE_80321) || \
-     defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
+#if (defined(CPU_XSCALE_81342))
 #define ARM_XSCALE_PMU	1
 #else
 #define ARM_XSCALE_PMU	0
diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index aad0feb..726c808 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -342,10 +342,9 @@ void	armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
 #endif
 
 #if defined(CPU_ARM9) || defined(CPU_ARM9E) ||				\
-  defined(CPU_XSCALE_80321) ||						\
   defined(CPU_FA526) ||							\
   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
-  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
+  defined(CPU_XSCALE_81342)
 
 void	armv4_tlb_flushID	(void);
 void	armv4_tlb_flushD	(void);
@@ -355,9 +354,8 @@ void	armv4_drain_writebuf	(void);
 void	armv4_idcache_inv_all	(void);
 #endif
 
-#if defined(CPU_XSCALE_80321) ||				\
-  defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
-  defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
+#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
+  defined(CPU_XSCALE_81342)
 void	xscale_cpwait		(void);
 
 void	xscale_cpu_sleep	(int mode);
@@ -395,8 +393,7 @@ void	xscale_cache_flushD_rng	(vm_offset_t start, vm_size_t end);
 void	xscale_context_switch	(void);
 
 void	xscale_setup		(void);
-#endif	/* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
-	   CPU_XSCALE_80219 */
+#endif	/* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
 
 #ifdef	CPU_XSCALE_81342
 
diff --git a/sys/arm/xscale/i80321/ep80219_machdep.c b/sys/arm/xscale/i80321/ep80219_machdep.c
deleted file mode 100644
index 6c0d1f5..0000000
--- a/sys/arm/xscale/i80321/ep80219_machdep.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/*	$NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $	*/
-
-/*-
- * Copyright (c) 1994-1998 Mark Brinicombe.
- * Copyright (c) 1994 Brini.
- * All rights reserved.
- *
- * This code is derived from software written for Brini by Mark Brinicombe
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *      This product includes software developed by Brini.
- * 4. The name of the company nor the name of the author may be used to
- *    endorse or promote products derived from this software without specific
- *    prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RiscBSD kernel project
- *
- * machdep.c
- *
- * Machine dependant functions for kernel setup
- *
- * This file needs a lot of work.
- *
- * Created      : 17/09/94
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_kstack_pages.h"
-
-#define _ARM32_BUS_DMA_PRIVATE
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/sysproto.h>
-#include <sys/signalvar.h>
-#include <sys/imgact.h>
-#include <sys/kernel.h>
-#include <sys/ktr.h>
-#include <sys/linker.h>
-#include <sys/lock.h>
-#include <sys/malloc.h>
-#include <sys/mutex.h>
-#include <sys/pcpu.h>
-#include <sys/proc.h>
-#include <sys/ptrace.h>
-#include <sys/cons.h>
-#include <sys/bio.h>
-#include <sys/bus.h>
-#include <sys/buf.h>
-#include <sys/exec.h>
-#include <sys/kdb.h>
-#include <sys/msgbuf.h>
-#include <machine/reg.h>
-#include <machine/cpu.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-#include <vm/vm_object.h>
-#include <vm/vm_page.h>
-#include <vm/vm_map.h>
-#include <machine/devmap.h>
-#include <machine/vmparam.h>
-#include <machine/pcb.h>
-#include <machine/undefined.h>
-#include <machine/machdep.h>
-#include <machine/metadata.h>
-#include <machine/armreg.h>
-#include <machine/bus.h>
-#include <machine/physmem.h>
-#include <sys/reboot.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-#include <arm/xscale/i80321/iq80321reg.h>
-#include <arm/xscale/i80321/obiovar.h>
-
-#define	KERNEL_PT_SYS		0	/* Page table for mapping proc0 zero page */
-#define	KERNEL_PT_IOPXS		1
-#define	KERNEL_PT_BEFOREKERN	2
-#define	KERNEL_PT_AFKERNEL	3	/* L2 table for mapping after kernel */
-#define	KERNEL_PT_AFKERNEL_NUM	9
-
-/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
-#define NUM_KERNEL_PTS		(KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
-
-struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
-
-/* Physical and virtual addresses for some global pages */
-
-struct pv_addr systempage;
-struct pv_addr msgbufpv;
-struct pv_addr irqstack;
-struct pv_addr undstack;
-struct pv_addr abtstack;
-struct pv_addr kernelstack;
-struct pv_addr minidataclean;
-
-
-/* #define IQ80321_OBIO_BASE 0xfe800000UL */
-/* #define IQ80321_OBIO_SIZE 0x00100000UL */
-
-/* Static device mappings. */
-static const struct arm_devmap_entry ep80219_devmap[] = {
-	/*
-	 * Map the on-board devices VA == PA so that we can access them
-	 * with the MMU on or off.
-	 */
-	{
-		IQ80321_OBIO_BASE,
-		IQ80321_OBIO_BASE,
-		IQ80321_OBIO_SIZE,
-		VM_PROT_READ|VM_PROT_WRITE,
-		PTE_DEVICE,
-	},
-	{
-		IQ80321_IOW_VBASE,
-		VERDE_OUT_XLATE_IO_WIN0_BASE,
-		VERDE_OUT_XLATE_IO_WIN_SIZE,
-		VM_PROT_READ|VM_PROT_WRITE,
-		PTE_DEVICE,
-	},	
-	{
-		IQ80321_80321_VBASE,
-		VERDE_PMMR_BASE,
-		VERDE_PMMR_SIZE,
-		VM_PROT_READ|VM_PROT_WRITE,
-		PTE_DEVICE,
-	},
-	{
-		0,
-		0,
-		0,
-		0,
-		0,
-	}
-};
-
-extern vm_offset_t xscale_cache_clean_addr;
-
-void *
-initarm(struct arm_boot_params *abp)
-{
-	struct pv_addr  kernel_l1pt;
-	struct pv_addr  dpcpu;
-	int loop, i;
-	u_int l1pagetable;
-	vm_offset_t freemempos;
-	vm_offset_t freemem_pt;
-	vm_offset_t afterkern;
-	vm_offset_t freemem_after;
-	vm_offset_t lastaddr;
-	uint32_t memsize, memstart;
-
-	lastaddr = parse_boot_param(abp);
-	arm_physmem_kernaddr = abp->abp_physaddr;
-	set_cpufuncs();
-	pcpu_init(pcpup, 0, sizeof(struct pcpu));
-	PCPU_SET(curthread, &thread0);
-
-	/* Do basic tuning, hz etc */
-	init_param1();
-
-	freemempos = 0xa0200000;
-	/* Define a macro to simplify memory allocation */
-#define	valloc_pages(var, np)			\
-	alloc_pages((var).pv_pa, (np));		\
-	(var).pv_va = (var).pv_pa + 0x20000000;
-
-#define alloc_pages(var, np)			\
-	freemempos -= (np * PAGE_SIZE);		\
-	(var) = freemempos;		\
-	memset((char *)(var), 0, ((np) * PAGE_SIZE));
-
-	while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
-		freemempos -= PAGE_SIZE;
-	valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
-	for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
-		if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
-			valloc_pages(kernel_pt_table[loop],
-			    L2_TABLE_SIZE / PAGE_SIZE);
-		} else {
-			kernel_pt_table[loop].pv_pa = freemempos +
-			    (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
-			    L2_TABLE_SIZE_REAL;
-			kernel_pt_table[loop].pv_va =
-			    kernel_pt_table[loop].pv_pa + 0x20000000;
-		}
-	}
-	freemem_pt = freemempos;
-	freemempos = 0xa0100000;
-	/*
-	 * Allocate a page for the system page mapped to V0x00000000
-	 * This page will just contain the system vectors and can be
-	 * shared by all processes.
-	 */
-	valloc_pages(systempage, 1);
-
-	/* Allocate dynamic per-cpu area. */
-	valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
-	dpcpu_init((void *)dpcpu.pv_va, 0);
-
-	/* Allocate stacks for all modes */
-	valloc_pages(irqstack, IRQ_STACK_SIZE);
-	valloc_pages(abtstack, ABT_STACK_SIZE);
-	valloc_pages(undstack, UND_STACK_SIZE);
-	valloc_pages(kernelstack, kstack_pages);
-	alloc_pages(minidataclean.pv_pa, 1);
-	valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
-	/*
-	 * Allocate memory for the l1 and l2 page tables. The scheme to avoid
-	 * wasting memory by allocating the l1pt on the first 16k memory was
-	 * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
-	 * this to work (which is supposed to be the case).
-	 */
-
-	/*
-	 * Now we start construction of the L1 page table
-	 * We start by mapping the L2 page tables into the L1.
-	 * This means that we can replace L1 mappings later on if necessary
-	 */
-	l1pagetable = kernel_l1pt.pv_va;
-
-	/* Map the L2 pages tables in the L1 page table */
-	pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
-	    &kernel_pt_table[KERNEL_PT_SYS]);
-	pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
-	    &kernel_pt_table[KERNEL_PT_IOPXS]);
-	pmap_link_l2pt(l1pagetable, KERNBASE,
-	    &kernel_pt_table[KERNEL_PT_BEFOREKERN]);
-	pmap_map_chunk(l1pagetable, KERNBASE, IQ80321_SDRAM_START, 0x100000,
-	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-	pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, IQ80321_SDRAM_START + 0x100000,
-	    0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
-	pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, IQ80321_SDRAM_START + 0x200000,
-	    (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
-	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-	freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
-	afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
-	    - 1));
-	for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
-		pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
-		    &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
-	}
-	pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
-	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-	
-
-	/* Map the Mini-Data cache clean area. */
-	xscale_setup_minidata(l1pagetable, afterkern,
-	    minidataclean.pv_pa);
-
-	/* Map the vector page. */
-	pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
-	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-	arm_devmap_bootstrap(l1pagetable, ep80219_devmap);
-	/*
-	 * Give the XScale global cache clean code an appropriately
-	 * sized chunk of unmapped VA space starting at 0xff000000
-	 * (our device mappings end before this address).
-	 */
-	xscale_cache_clean_addr = 0xff000000U;
-
-	cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
-	setttb(kernel_l1pt.pv_pa);
-	cpu_tlb_flushID();
-	cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
-	/*
-	 * Pages were allocated during the secondary bootstrap for the
-	 * stacks for different CPU modes.
-	 * We must now set the r13 registers in the different CPU modes to
-	 * point to these stacks.
-	 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
-	 * of the stack memory.
-	 */
-	set_stackptrs(0);
-
-	/*
-	 * We must now clean the cache again....
-	 * Cleaning may be done by reading new data to displace any
-	 * dirty data in the cache. This will have happened in setttb()
-	 * but since we are boot strapping the addresses used for the read
-	 * may have just been remapped and thus the cache could be out
-	 * of sync. A re-clean after the switch will cure this.
-	 * After booting there are no gross relocations of the kernel thus
-	 * this problem will not occur after initarm().
-	 */
-	cpu_idcache_wbinv_all();
-	cpu_setup();
-
-	/*
-	 * Fetch the SDRAM start/size from the i80321 SDRAM configration
-	 * registers.
-	 */
-	i80321_calibrate_delay();
-	i80321_sdram_bounds(obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE,
-	    &memstart, &memsize);
-	physmem = memsize / PAGE_SIZE;
-	cninit();
-
-	undefined_init();
-				
-	init_proc0(kernelstack.pv_va);
-	
-	/* Enable MMU, I-cache, D-cache, write buffer. */
-
-	arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
-	vm_max_kernel_address = 0xe0000000;
-	pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt);
-	msgbufp = (void*)msgbufpv.pv_va;
-	msgbufinit(msgbufp, msgbufsize);
-	mutex_init();
-	
-	/*
-	 * Add the physical ram we have available.
-	 *
-	 * Exclude the kernel (and all the things we allocated which immediately
-	 * follow the kernel) from the VM allocation pool but not from crash
-	 * dumps.  virtual_avail is a global variable which tracks the kva we've
-	 * "allocated" while setting up pmaps.
-	 *
-	 * Prepare the list of physical memory available to the vm subsystem.
-	 */
-	arm_physmem_hardware_region(IQ80321_SDRAM_START, memsize);
-	arm_physmem_exclude_region(freemem_pt, abp->abp_physaddr -
-	    freemem_pt, EXFLAG_NOALLOC);
-	arm_physmem_exclude_region(freemempos, abp->abp_physaddr - 0x100000 -
-	    freemempos, EXFLAG_NOALLOC);
-	arm_physmem_exclude_region(abp->abp_physaddr, 
-	    virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
-	arm_physmem_init_kernel_globals();
-
-	init_param2(physmem);
-	kdb_init();
-	return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
-	    sizeof(struct pcb)));
-}
-
-extern int
-machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin)
-{
-	int bus;
-	int device;
-	int func;
-	uint32_t busno;
-	struct i80321_pci_softc *sc = device_get_softc(pcib);
-	bus = pci_get_bus(dev);
-	device = pci_get_slot(dev);
-	func = pci_get_function(dev);
-	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
-	busno = PCIXSR_BUSNO(busno);
-	if (busno == 0xff)
-		busno = 0;
-	if (bus != busno)
-		goto no_mapping;
-	switch (device) {
-		/* EP80219 PCI */
-	case 1: /* Ethernet i82555 10/100 */
-		printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(0));
-		return (ICU_INT_XINT(0));
-	case 2: /* UART */
-		printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(1));
-		return (ICU_INT_XINT(1));
-	case 3:
-		/*
-		 * The S-ATA chips are behind the bridge, and all of
-		 * the S-ATA interrupts are wired together.
-		 */
-		printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(2));
-		return (ICU_INT_XINT(2));
-	case 4: /* MINI-PIC_INT */
-		printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(3));
-		return( ICU_INT_XINT(3));
-	default:
-no_mapping:
-		printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
-		
-	}
-	return (0);
-
-}
diff --git a/sys/arm/xscale/i80321/files.ep80219 b/sys/arm/xscale/i80321/files.ep80219
deleted file mode 100644
index 0eaf9db..0000000
--- a/sys/arm/xscale/i80321/files.ep80219
+++ /dev/null
@@ -1,11 +0,0 @@
-#$FreeBSD$
-#
-#
-# EP80219 Board Specific
-#
-arm/xscale/i80321/iq80321.c		standard
-arm/xscale/i80321/ep80219_machdep.c	standard
-arm/xscale/i80321/obio.c		standard
-arm/xscale/i80321/uart_cpu_i80321.c	optional	uart
-arm/xscale/i80321/uart_bus_i80321.c	optional	uart
-dev/uart/uart_dev_ns8250.c		optional	uart
diff --git a/sys/arm/xscale/i80321/files.i80219 b/sys/arm/xscale/i80321/files.i80219
deleted file mode 100644
index 306376b..0000000
--- a/sys/arm/xscale/i80321/files.i80219
+++ /dev/null
@@ -1,11 +0,0 @@
-#$FreeBSD$
-#
-# IOP Specific
-# 
-arm/xscale/i80321/i80321.c		standard
-arm/xscale/i80321/i80321_dma.c		optional	dma
-arm/xscale/i80321/i80321_mcu.c		standard
-arm/xscale/i80321/i80321_pci.c		optional	pci
-arm/xscale/i80321/i80321_space.c	standard
-arm/xscale/i80321/i80321_timer.c	standard
-arm/xscale/i80321/i80321_wdog.c		optional	iopwdog
diff --git a/sys/arm/xscale/i80321/files.i80321 b/sys/arm/xscale/i80321/files.i80321
deleted file mode 100644
index bd318af..0000000
--- a/sys/arm/xscale/i80321/files.i80321
+++ /dev/null
@@ -1,9 +0,0 @@
-#$FreeBSD$
-arm/xscale/i80321/i80321.c		standard
-arm/xscale/i80321/i80321_aau.c		optional	aau
-arm/xscale/i80321/i80321_dma.c		optional	dma
-arm/xscale/i80321/i80321_mcu.c		standard
-arm/xscale/i80321/i80321_pci.c		optional	pci
-arm/xscale/i80321/i80321_space.c	standard
-arm/xscale/i80321/i80321_timer.c	standard
-arm/xscale/i80321/i80321_wdog.c		optional	iopwdog
diff --git a/sys/arm/xscale/i80321/files.iq31244 b/sys/arm/xscale/i80321/files.iq31244
deleted file mode 100644
index d28d49b..0000000
--- a/sys/arm/xscale/i80321/files.iq31244
+++ /dev/null
@@ -1,8 +0,0 @@
-#$FreeBSD$
-arm/xscale/i80321/iq80321.c		standard
-arm/xscale/i80321/iq31244_machdep.c	standard
-arm/xscale/i80321/iq31244_7seg.c	optional	iq31244_7seg
-arm/xscale/i80321/obio.c		standard
-arm/xscale/i80321/uart_cpu_i80321.c	optional	uart
-arm/xscale/i80321/uart_bus_i80321.c	optional	uart
-dev/uart/uart_dev_ns8250.c		optional	uart
diff --git a/sys/arm/xscale/i80321/i80321.c b/sys/arm/xscale/i80321/i80321.c
deleted file mode 100644
index e65f38d..0000000
--- a/sys/arm/xscale/i80321/i80321.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*	$NetBSD: i80321.c,v 1.15 2003/10/06 16:06:05 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Autoconfiguration support for the Intel i80321 I/O Processor.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-
-#define	_ARM32_BUS_DMA_PRIVATE
-#include <machine/bus.h>
-#include <machine/intr.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-#include <arm/xscale/i80321/i80321_intr.h>
-
-#include <dev/pci/pcireg.h>
-
-volatile uint32_t intr_enabled;
-uint32_t intr_steer = 0;
-/*
- * Statically-allocated bus_space stucture used to access the
- * i80321's own registers.
- */
-struct bus_space i80321_bs_tag;
-
-/*
- * There can be only one i80321, so we keep a global pointer to
- * the softc, so board-specific code can use features of the
- * i80321 without having to have a handle on the softc itself.
- */
-struct i80321_softc *i80321_softc;
-
-#define PCI_MAPREG_MEM_ADDR(x) ((x) & 0xfffffff0)
-/*
- * i80321_attach:
- *
- *	Board-independent attach routine for the i80321.
- */
-void
-i80321_attach(struct i80321_softc *sc)
-{
-
-	i80321_softc = sc;
-	uint32_t preg;
-
-	/* We expect the Memory Controller to be already sliced off. */
-
-	/*
-	 * Program the Inbound windows.
-	 */
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0,
-	    (0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR0,
-	    sc->sc_iwin[0].iwin_xlate);
-	if (sc->sc_is_host) {
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-		    PCIR_BARS, sc->sc_iwin[0].iwin_base_lo);
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-		    PCIR_BARS + 0x04, sc->sc_iwin[0].iwin_base_hi);
-	} else {
-		sc->sc_iwin[0].iwin_base_lo = bus_space_read_4(sc->sc_st,
-		    sc->sc_atu_sh, PCIR_BARS);
-		sc->sc_iwin[0].iwin_base_hi = bus_space_read_4(sc->sc_st,
-		    sc->sc_atu_sh, PCIR_BARS + 0x04);
-		sc->sc_iwin[0].iwin_base_lo =
-		    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[0].iwin_base_lo);
-	}
-
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1,
-	    (0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0);
-
-	/* no xlate for window 1 */
-	if (sc->sc_is_host) {
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-		    PCIR_BARS + 0x08, sc->sc_iwin[1].iwin_base_lo);
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-		    PCIR_BARS + 0x0c, sc->sc_iwin[1].iwin_base_hi);
-	} else {
-		sc->sc_iwin[1].iwin_base_lo = bus_space_read_4(sc->sc_st,
-		    sc->sc_atu_sh, PCIR_BARS + 0x08);
-		sc->sc_iwin[1].iwin_base_hi = bus_space_read_4(sc->sc_st,
-		    sc->sc_atu_sh, PCIR_BARS + 0x0c);
-		sc->sc_iwin[1].iwin_base_lo =
-		    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
-	}
-
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2,
-	    (0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR2,
-	    sc->sc_iwin[2].iwin_xlate);
-
-	if (sc->sc_is_host) {
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-		    PCIR_BARS + 0x10, sc->sc_iwin[2].iwin_base_lo);
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-		    PCIR_BARS + 0x14, sc->sc_iwin[2].iwin_base_hi);
-	} else {
-		sc->sc_iwin[2].iwin_base_lo = bus_space_read_4(sc->sc_st,
-		    sc->sc_atu_sh, PCIR_BARS + 0x10);
-		sc->sc_iwin[2].iwin_base_hi = bus_space_read_4(sc->sc_st,
-		    sc->sc_atu_sh, PCIR_BARS + 0x14);
-		sc->sc_iwin[2].iwin_base_lo =
-		    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
-	}
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR3,
-	    (0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR3,
-	    sc->sc_iwin[3].iwin_xlate);
-
-	if (sc->sc_is_host) {
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-		    ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo);
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-		    ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi);
-	} else {
-		sc->sc_iwin[3].iwin_base_lo = bus_space_read_4(sc->sc_st,
-		    sc->sc_atu_sh, ATU_IABAR3);
-		sc->sc_iwin[3].iwin_base_hi = bus_space_read_4(sc->sc_st,
-		    sc->sc_atu_sh, ATU_IAUBAR3);
-		sc->sc_iwin[3].iwin_base_lo =
-		    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[3].iwin_base_lo);
-	}
-	/*
-	 * Mask (disable) the ATU interrupt sources.
-	 * XXX May want to revisit this if we encounter
-	 * XXX an application that wants it.
-	 */
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-	    ATU_ATUIMR,
-	    ATUIMR_IMW1BU|ATUIMR_ISCEM|ATUIMR_RSCEM|ATUIMR_PST|
-	    ATUIMR_DPE|ATUIMR_P_SERR_ASRT|ATUIMR_PMA|ATUIMR_PTAM|
-	    ATUIMR_PTAT|ATUIMR_PMPE);
-
-	/*
-	 * Program the outbound windows.
-	 */
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-	    ATU_OIOWTVR, sc->sc_ioout_xlate);
-
-	if (!sc->sc_is_host) {
-		sc->sc_owin[0].owin_xlate_lo = sc->sc_iwin[1].iwin_base_lo;
-		sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
-	}
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-	    ATU_OMWTVR0, sc->sc_owin[0].owin_xlate_lo);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-	    ATU_OUMWTVR0, sc->sc_owin[0].owin_xlate_hi);
-
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-	    ATU_OMWTVR1, sc->sc_owin[1].owin_xlate_lo);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-	    ATU_OUMWTVR1, sc->sc_owin[1].owin_xlate_hi);
-
-	/*
-	 * Set up the ATU configuration register.  All we do
-	 * right now is enable Outbound Windows.
-	 */
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUCR,
-	    ATUCR_OUT_EN);
-
-	/*
-	 * Enable bus mastering, memory access, SERR, and parity
-	 * checking on the ATU.
-	 */
-	if (sc->sc_is_host) {
-		preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
-		    PCIR_COMMAND);
-		preg |= PCIM_CMD_MEMEN |
-		    PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN |
-		    PCIM_CMD_SERRESPEN;
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
-		    PCIR_COMMAND, preg);
-	}
-	/* Initialize the bus space tags. */
-	i80321_io_bs_init(&sc->sc_pci_iot, sc);
-	i80321_mem_bs_init(&sc->sc_pci_memt, sc);
-	intr_enabled = 0;
-	i80321_set_intrmask();
-	i80321_set_intrsteer();
-}
-
-
-static __inline uint32_t
-i80321_iintsrc_read(void)
-{
-	uint32_t iintsrc;
-		
-	__asm __volatile("mrc p6, 0, %0, c8, c0, 0"
-	    : "=r" (iintsrc));
-	
-	/*
-	 * The IINTSRC register shows bits that are active even
-	 * if they are masked in INTCTL, so we have to mask them
-	 * off with the interrupts we consider enabled.
-	 */
-	return (iintsrc & intr_enabled);
-}
-
-int
-arm_get_next_irq(int last __unused)
-{
-	int irq;
-
-	if ((irq = i80321_iintsrc_read()))
-		return (ffs(irq) - 1);
-	return (-1);
-}
diff --git a/sys/arm/xscale/i80321/i80321_aau.c b/sys/arm/xscale/i80321/i80321_aau.c
deleted file mode 100644
index 288411b..0000000
--- a/sys/arm/xscale/i80321/i80321_aau.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*-
- * Copyright (c) 2005 Olivier Houchard.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/rman.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/proc.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-#include <vm/vm_map.h>
-#include <machine/bus.h>
-#include <machine/cpu.h>
-#include <machine/md_var.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-#include <arm/xscale/i80321/iq80321reg.h>
-#include <arm/xscale/i80321/iq80321var.h>
-#include <arm/xscale/i80321/i80321_intr.h>
-
-typedef struct i80321_aaudesc_s {
-	vm_paddr_t next_desc;
-	uint32_t sar[4];
-	vm_paddr_t local_addr;
-	vm_size_t count;
-	uint32_t descr_ctrl;
-} __packed	i80321_aaudesc_t;
-
-typedef struct i80321_aauring_s {
-	i80321_aaudesc_t *desc;
-	vm_paddr_t phys_addr;
-	bus_dmamap_t map;
-} i80321_aauring_t;
-
-#define AAU_RING_SIZE 64
-
-struct i80321_aau_softc {
-	bus_space_tag_t sc_st;
-	bus_space_handle_t sc_aau_sh;
-	bus_dma_tag_t dmatag;
-	i80321_aauring_t aauring[AAU_RING_SIZE];
-	int flags;
-#define BUSY	0x1
-	int unit;
-	struct mtx mtx;
-};
-
-static int
-i80321_aau_probe(device_t dev)
-{
-	device_set_desc(dev, "I80321 AAU");
-	return (0);
-}
-
-static struct i80321_aau_softc *aau_softc;
-
-static void
-i80321_mapphys(void *arg, bus_dma_segment_t *segs, int nseg, int error)
-{
-	vm_paddr_t *addr = (vm_paddr_t *)arg;
-
-	*addr = segs->ds_addr;
-}
-
-#define AAU_REG_WRITE(softc, reg, val) \
-    bus_space_write_4((softc)->sc_st, (softc)->sc_aau_sh, \
-	(reg), (val))
-#define AAU_REG_READ(softc, reg) \
-    bus_space_read_4((softc)->sc_st, (softc)->sc_aau_sh, \
-	(reg))
-
-static int aau_bzero(void *, int, int);
-
-static int
-i80321_aau_attach(device_t dev)
-{
-	struct i80321_aau_softc *softc = device_get_softc(dev);
-	struct i80321_softc *sc = device_get_softc(device_get_parent(dev));
-	struct i80321_aaudesc_s *aaudescs;
-
-	mtx_init(&softc->mtx, "AAU mtx", NULL, MTX_SPIN);
-	softc->sc_st = sc->sc_st;
-	if (bus_space_subregion(softc->sc_st, sc->sc_sh, VERDE_AAU_BASE,
-	    VERDE_AAU_SIZE, &softc->sc_aau_sh) != 0)
-		panic("%s: unable to subregion AAU registers",
-		    device_get_name(dev));
-	if (bus_dma_tag_create(NULL, sizeof(i80321_aaudesc_t), 0,
-	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
-	    AAU_RING_SIZE * sizeof(i80321_aaudesc_t),
-	    1, sizeof(i80321_aaudesc_t), BUS_DMA_ALLOCNOW, busdma_lock_mutex,
-	    &Giant, &softc->dmatag))
-		panic("Couldn't create a dma tag");
-	if (bus_dmamem_alloc(softc->dmatag, (void **)&aaudescs,
-    	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &softc->aauring[0].map))
-		panic("Couldn't alloc dma memory");
-
-	for (int i = 0; i < AAU_RING_SIZE; i++) {
-		if (i > 0)
-			if (bus_dmamap_create(softc->dmatag, 0,
-			    &softc->aauring[i].map))
-				panic("Couldn't create dma map");
-		softc->aauring[i].desc = &aaudescs[i];
-		bus_dmamap_load(softc->dmatag, softc->aauring[i].map,
-		    softc->aauring[i].desc, sizeof(i80321_aaudesc_t),
-		    i80321_mapphys, &softc->aauring[i].phys_addr, 0);
-		bzero(softc->aauring[i].desc, sizeof(i80321_aaudesc_t));
-	}
-	aau_softc = softc;
-	_arm_bzero = aau_bzero;
-	_min_bzero_size = 1024;
-	return (0);
-}
-
-static __inline void
-test_virt_addr(void *addr, int len)
-{
-	int to_nextpage;
-
-	while (len > 0) {
-		*(char *)addr = 0;
-		to_nextpage = ((vm_offset_t)addr & ~PAGE_MASK) +
-		    PAGE_SIZE - (vm_offset_t)addr;
-		if (to_nextpage >= len)
-			break;
-		len -= to_nextpage;
-		addr = (void *)((vm_offset_t)addr + to_nextpage);
-	}
-}
-
-static int
-aau_bzero(void *dst, int len, int flags)
-{
-	struct i80321_aau_softc *sc = aau_softc;
-	i80321_aaudesc_t *desc;
-	int ret;
-	int csr;
-	int descnb = 0;
-	int tmplen = len;
-	int to_nextpagedst;
-	int min_hop;
-	vm_paddr_t pa, tmppa;
-
-	if (!sc)
-		return (-1);
-	mtx_lock_spin(&sc->mtx);
-	if (sc->flags & BUSY) {
-		mtx_unlock_spin(&sc->mtx);
-		return (-1);
-	}
-	sc->flags |= BUSY;
-	mtx_unlock_spin(&sc->mtx);
-	desc = sc->aauring[0].desc;
-	if (flags & IS_PHYSICAL) {
-		desc->local_addr = (vm_paddr_t)dst;
-		desc->next_desc = 0;
-		desc->count = len;
-		desc->descr_ctrl = 2 << 1 | 1 << 31; /* Fill, enable dest write */
-		bus_dmamap_sync(sc->dmatag, sc->aauring[0].map,
-		    BUS_DMASYNC_PREWRITE);
-	} else {
-		test_virt_addr(dst, len);
-		if ((vm_offset_t)dst & (31))
-			cpu_dcache_wb_range((vm_offset_t)dst & ~31, 32);
-		if (((vm_offset_t)dst + len) & 31)
-			cpu_dcache_wb_range(((vm_offset_t)dst + len) & ~31,
-			    32);
-		cpu_dcache_inv_range((vm_offset_t)dst, len);
-		while (tmplen > 0) {
-			pa = vtophys(dst);
-			to_nextpagedst = ((vm_offset_t)dst & ~PAGE_MASK) +
-			    PAGE_SIZE - (vm_offset_t)dst;
-			while (to_nextpagedst < tmplen) {
-				tmppa = vtophys((vm_offset_t)dst +
-				    to_nextpagedst);
-				if (tmppa != pa + to_nextpagedst)
-					break;
-				to_nextpagedst += PAGE_SIZE;
-			}
-			min_hop = to_nextpagedst;
-			if (min_hop < 64) {
-				tmplen -= min_hop;
-				bzero(dst, min_hop);
-				cpu_dcache_wbinv_range((vm_offset_t)dst,
-				    min_hop);
-
-				dst = (void *)((vm_offset_t)dst + min_hop);
-				if (tmplen <= 0 && descnb > 0) {
-					sc->aauring[descnb - 1].desc->next_desc
-					    = 0;
-					bus_dmamap_sync(sc->dmatag,
-					    sc->aauring[descnb - 1].map,
-					    BUS_DMASYNC_PREWRITE);
-				}
-				continue;
-			}
-			desc->local_addr = pa;
-			desc->count = tmplen > min_hop ? min_hop : tmplen;
-			desc->descr_ctrl = 2 << 1 | 1 << 31; /* Fill, enable dest write */;
-			if (min_hop < tmplen) {
-				tmplen -= min_hop;
-				dst = (void *)((vm_offset_t)dst + min_hop);
-			} else
-				tmplen = 0;
-			if (descnb + 1 >= AAU_RING_SIZE) {
-				mtx_lock_spin(&sc->mtx);
-				sc->flags &= ~BUSY;
-				mtx_unlock_spin(&sc->mtx);
-				return (-1);
-			}
-			if (tmplen > 0) {
-				desc->next_desc = sc->aauring[descnb + 1].
-				    phys_addr;
-				bus_dmamap_sync(sc->dmatag,
-				    sc->aauring[descnb].map,
-				    BUS_DMASYNC_PREWRITE);
-				desc = sc->aauring[descnb + 1].desc;
-				descnb++;
-			} else {
-				desc->next_desc = 0;
-				bus_dmamap_sync(sc->dmatag,
-				    sc->aauring[descnb].map,
-				    BUS_DMASYNC_PREWRITE);
-			}
-									
-		}
-
-	}
-	AAU_REG_WRITE(sc, 0x0c /* Descriptor addr */,
-	    sc->aauring[0].phys_addr);
-	AAU_REG_WRITE(sc, 0 /* Control register */, 1 << 0/* Start transfer */);
-	while ((csr = AAU_REG_READ(sc, 0x4)) & (1 << 10));
-	/* Wait until it's done. */
-	if (csr & (1 << 5)) /* error */
-		ret = -1;
-	else
-		ret = 0;
-	/* Clear the interrupt. */
-	AAU_REG_WRITE(sc, 0x4, csr);
-	/* Stop the AAU. */
-	AAU_REG_WRITE(sc, 0, 0);
-	mtx_lock_spin(&sc->mtx);
-	sc->flags &= ~BUSY;
-	mtx_unlock_spin(&sc->mtx);
-	return (ret);
-}
-
-static device_method_t i80321_aau_methods[] = {
-	DEVMETHOD(device_probe, i80321_aau_probe),
-	DEVMETHOD(device_attach, i80321_aau_attach),
-	{0, 0},
-};
-
-static driver_t i80321_aau_driver = {
-	"i80321_aau",
-	i80321_aau_methods,
-	sizeof(struct i80321_aau_softc),
-};
-
-static devclass_t i80321_aau_devclass;
-
-DRIVER_MODULE(i80321_aau, iq, i80321_aau_driver, i80321_aau_devclass, 0, 0);
diff --git a/sys/arm/xscale/i80321/i80321_dma.c b/sys/arm/xscale/i80321/i80321_dma.c
deleted file mode 100644
index abf7dcc..0000000
--- a/sys/arm/xscale/i80321/i80321_dma.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/*-
- * Copyright (c) 2005 Olivier Houchard.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/rman.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/proc.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-#include <vm/vm_map.h>
-#include <machine/bus.h>
-#include <machine/cpu.h>
-#include <machine/md_var.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-#include <arm/xscale/i80321/iq80321reg.h>
-#include <arm/xscale/i80321/iq80321var.h>
-#include <arm/xscale/i80321/i80321_intr.h>
-
-typedef struct i80321_dmadesc_s {
-	vm_paddr_t next_desc;
-	vm_paddr_t low_pciaddr;
-	vm_paddr_t high_pciaddr;
-	vm_paddr_t local_addr;
-	vm_size_t count;
-	uint32_t descr_ctrl;
-	uint64_t unused;
-} __packed	i80321_dmadesc_t;
-
-typedef struct i80321_dmaring_s {
-	i80321_dmadesc_t *desc;
-	vm_paddr_t phys_addr;
-	bus_dmamap_t map;
-} i80321_dmaring_t;
-
-#define DMA_RING_SIZE 64
-
-struct i80321_dma_softc {
-	bus_space_tag_t sc_st;
-	bus_space_handle_t sc_dma_sh;
-	bus_dma_tag_t dmatag;
-	i80321_dmaring_t dmaring[DMA_RING_SIZE];
-	int flags;
-#define BUSY	0x1
-	int unit;
-	struct mtx mtx;
-};
-
-static int
-i80321_dma_probe(device_t dev)
-{
-	device_set_desc(dev, "I80321 DMA Unit");
-	return (0);
-}
-
-static struct i80321_dma_softc *softcs[2]; /* XXX */
-
-static void
-i80321_mapphys(void *arg, bus_dma_segment_t *segs, int nseg, int error)
-{
-	vm_paddr_t *addr = (vm_paddr_t *)arg;
-
-	*addr = segs->ds_addr;
-}
-
-#define DMA_REG_WRITE(softc, reg, val) \
-    bus_space_write_4((softc)->sc_st, (softc)->sc_dma_sh, \
-	(reg), (val))
-#define DMA_REG_READ(softc, reg) \
-    bus_space_read_4((softc)->sc_st, (softc)->sc_dma_sh, \
-	(reg))
-
-#define DMA_CLEAN_MASK (0x2|0x4|0x8|0x20|0x100|0x200)
-static int dma_memcpy(void *, void *, int, int);
-
-static int
-i80321_dma_attach(device_t dev)
-{
-	struct i80321_dma_softc *softc = device_get_softc(dev);
-	struct i80321_softc *sc = device_get_softc(device_get_parent(dev));
-	int unit = device_get_unit(dev);
-	i80321_dmadesc_t *dmadescs;
-
-	mtx_init(&softc->mtx, "DMA engine mtx", NULL, MTX_SPIN);
-	softc->sc_st = sc->sc_st;
-	if (bus_space_subregion(softc->sc_st, sc->sc_sh, unit == 0 ?
-	    VERDE_DMA_BASE0 : VERDE_DMA_BASE1, VERDE_DMA_SIZE,
-	    &softc->sc_dma_sh) != 0)
-		panic("%s: unable to subregion DMA registers",
-		    device_get_name(dev));
-	if (bus_dma_tag_create(NULL, sizeof(i80321_dmadesc_t),
-	    0, BUS_SPACE_MAXADDR,  BUS_SPACE_MAXADDR, NULL, NULL,
-	    DMA_RING_SIZE * sizeof(i80321_dmadesc_t), 1,
-	    sizeof(i80321_dmadesc_t), BUS_DMA_ALLOCNOW, busdma_lock_mutex,
-	    &Giant, &softc->dmatag))
-		panic("Couldn't create a dma tag");
-	DMA_REG_WRITE(softc, 0, 0);
-	if (bus_dmamem_alloc(softc->dmatag, (void **)&dmadescs,
-    	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &softc->dmaring[0].map))
-		panic("Couldn't alloc dma memory");
-	for (int i = 0; i < DMA_RING_SIZE; i++) {
-		if (i > 0)
-			if (bus_dmamap_create(softc->dmatag, 0,
-			    &softc->dmaring[i].map))
-				panic("Couldn't alloc dmamap");
-		softc->dmaring[i].desc = &dmadescs[i];	
-		bus_dmamap_load(softc->dmatag, softc->dmaring[i].map,
-		    softc->dmaring[i].desc, sizeof(i80321_dmadesc_t),
-		    i80321_mapphys, &softc->dmaring[i].phys_addr, 0);
-	}
-	softc->unit = unit;
-	softcs[unit] = softc;
-	_arm_memcpy = dma_memcpy;
-	_min_memcpy_size = 1024;
-	return (0);
-}
-
-static __inline int
-virt_addr_is_valid(void *addr, int len, int write, int is_kernel)
-{
-	int to_nextpage;
-	char tmp = 0;
-
-	while (len > 0) {
-		if (write) {
-			if (is_kernel)
-				*(char *)addr = 0;
-			else if (subyte(addr, 0) != 0) {
-				return (0);
-			}
-		} else {
-			if (is_kernel)
-				badaddr_read(addr, 1, &tmp);
-			else if (fubyte(addr) == -1) {
-				return (0);
-			}
-		}
-		to_nextpage = ((vm_offset_t)addr & ~PAGE_MASK) +
-		    PAGE_SIZE - (vm_offset_t)addr;
-		if (to_nextpage >= len)
-			break;
-		len -= to_nextpage;
-		addr = (void *)((vm_offset_t)addr + to_nextpage);
-	}
-	return (1);
-}
-
-static int
-dma_memcpy(void *dst, void *src, int len, int flags)
-{
-	struct i80321_dma_softc *sc;
-	i80321_dmadesc_t *desc;
-	int ret;
-	int csr;
-	int descnb = 0;
-	int tmplen = len;
-	int to_nextpagesrc, to_nextpagedst;
-	int min_hop;
-	vm_paddr_t pa, pa2, tmppa;
-	pmap_t pmap = vmspace_pmap(curthread->td_proc->p_vmspace);
-
-	if (!softcs[0] || !softcs[1])
-		return (-1);
-	mtx_lock_spin(&softcs[0]->mtx);
-	if (softcs[0]->flags & BUSY) {
-		mtx_unlock_spin(&softcs[0]->mtx);
-		mtx_lock_spin(&softcs[1]->mtx);
-		if (softcs[1]->flags & BUSY) {
-			mtx_unlock(&softcs[1]->mtx);
-			return (-1);
-		}
-		sc = softcs[1];
-	} else
-		sc = softcs[0];
-	sc->flags |= BUSY;
-	mtx_unlock_spin(&sc->mtx);
-	desc = sc->dmaring[0].desc;
-	if (flags & IS_PHYSICAL) {
-		desc->next_desc = 0;
-		desc->low_pciaddr = (vm_paddr_t)src;
-		desc->high_pciaddr = 0;
-		desc->local_addr = (vm_paddr_t)dst;
-		desc->count = len;
-		desc->descr_ctrl = 1 << 6; /* Local memory to local memory. */
-		bus_dmamap_sync(sc->dmatag,
-		    sc->dmaring[0].map,
-		    BUS_DMASYNC_PREWRITE);
-	} else {
-		if (!virt_addr_is_valid(dst, len, 1, !(flags & DST_IS_USER)) ||
-		    !virt_addr_is_valid(src, len, 0, !(flags & SRC_IS_USER))) {
-			mtx_lock_spin(&sc->mtx);
-			sc->flags &= ~BUSY;
-			mtx_unlock_spin(&sc->mtx);
-			return (-1);
-		}
-		cpu_dcache_wb_range((vm_offset_t)src, len);
-		if ((vm_offset_t)dst & (31))
-			cpu_dcache_wb_range((vm_offset_t)dst & ~31, 32);
-		if (((vm_offset_t)dst + len) & 31)
-			cpu_dcache_wb_range(((vm_offset_t)dst + len) & ~31,
-			    32);
-		cpu_dcache_inv_range((vm_offset_t)dst, len);
-		while (tmplen > 0) {
-			pa = (flags & SRC_IS_USER) ?
-			    pmap_extract(pmap, (vm_offset_t)src) :
-				    vtophys(src);
-			pa2 = (flags & DST_IS_USER) ?
-			    pmap_extract(pmap, (vm_offset_t)dst) :
-				    vtophys(dst);
-			to_nextpagesrc = ((vm_offset_t)src & ~PAGE_MASK) +
-			    PAGE_SIZE - (vm_offset_t)src;
-			to_nextpagedst = ((vm_offset_t)dst & ~PAGE_MASK) +
-			    PAGE_SIZE - (vm_offset_t)dst;
-			while (to_nextpagesrc < tmplen) {
-				tmppa = (flags & SRC_IS_USER) ?
-				    pmap_extract(pmap, (vm_offset_t)src +
-				    to_nextpagesrc) :
-					    vtophys((vm_offset_t)src +
-						to_nextpagesrc);
-				if (tmppa != pa + to_nextpagesrc)
-					break;
-				to_nextpagesrc += PAGE_SIZE;
-			}
-			while (to_nextpagedst < tmplen) {
-				tmppa = (flags & DST_IS_USER) ?
-				    pmap_extract(pmap, (vm_offset_t)dst +
-				    to_nextpagedst) :
-					    vtophys((vm_offset_t)dst +
-						to_nextpagedst);
-				if (tmppa != pa2 + to_nextpagedst)
-					break;
-				to_nextpagedst += PAGE_SIZE;
-			}
-			min_hop = to_nextpagedst > to_nextpagesrc ?
-			    to_nextpagesrc : to_nextpagedst;
-			if (min_hop < 64) {
-				tmplen -= min_hop;
-				memcpy(dst, src, min_hop);
-				cpu_dcache_wbinv_range((vm_offset_t)dst,
-				    min_hop);
-
-				src = (void *)((vm_offset_t)src + min_hop);
-				dst = (void *)((vm_offset_t)dst + min_hop);
-				if (tmplen <= 0 && descnb > 0) {
-					sc->dmaring[descnb - 1].desc->next_desc
-					    = 0;
-					bus_dmamap_sync(sc->dmatag,
-					    sc->dmaring[descnb - 1].map,
-					    BUS_DMASYNC_PREWRITE);
-				}
-				continue;
-			}
-			desc->low_pciaddr = pa;
-			desc->high_pciaddr = 0;
-			desc->local_addr = pa2;
-			desc->count = tmplen > min_hop ? min_hop : tmplen;
-			desc->descr_ctrl = 1 << 6;
-			if (min_hop < tmplen) {
-				tmplen -= min_hop;
-				src = (void *)((vm_offset_t)src + min_hop);
-				dst = (void *)((vm_offset_t)dst + min_hop);
-			} else
-				tmplen = 0;
-			if (descnb + 1 >= DMA_RING_SIZE) {
-				mtx_lock_spin(&sc->mtx);
-				sc->flags &= ~BUSY;
-				mtx_unlock_spin(&sc->mtx);
-				return (-1);
-			}
-			if (tmplen > 0) {
-				desc->next_desc = sc->dmaring[descnb + 1].
-				    phys_addr;
-				bus_dmamap_sync(sc->dmatag,
-				    sc->dmaring[descnb].map,
-				    BUS_DMASYNC_PREWRITE);
-				desc = sc->dmaring[descnb + 1].desc;
-				descnb++;
-			} else {
-				desc->next_desc = 0;
-				bus_dmamap_sync(sc->dmatag,
-				    sc->dmaring[descnb].map,
-				    BUS_DMASYNC_PREWRITE);
-			}
-									
-		}
-
-	}
-	DMA_REG_WRITE(sc, 4 /* Status register */,
-	    DMA_REG_READ(sc, 4) | DMA_CLEAN_MASK);
-	DMA_REG_WRITE(sc, 0x10 /* Descriptor addr */,
-	    sc->dmaring[0].phys_addr);
-	DMA_REG_WRITE(sc, 0 /* Control register */, 1 | 2/* Start transfer */);
-	while ((csr = DMA_REG_READ(sc, 0x4)) & (1 << 10));
-	/* Wait until it's done. */
-	if (csr & 0x2e) /* error */
-		ret = -1;
-	else
-		ret = 0;
-	DMA_REG_WRITE(sc, 0, 0);
-	mtx_lock_spin(&sc->mtx);
-	sc->flags &= ~BUSY;
-	mtx_unlock_spin(&sc->mtx);
-	return (ret);
-}
-
-static device_method_t i80321_dma_methods[] = {
-	DEVMETHOD(device_probe, i80321_dma_probe),
-	DEVMETHOD(device_attach, i80321_dma_attach),
-	{0, 0},
-};
-
-static driver_t i80321_dma_driver = {
-	"i80321_dma",
-	i80321_dma_methods,
-	sizeof(struct i80321_dma_softc),
-};
-
-static devclass_t i80321_dma_devclass;
-
-DRIVER_MODULE(i80321_dma, iq, i80321_dma_driver, i80321_dma_devclass, 0, 0);
diff --git a/sys/arm/xscale/i80321/i80321_intr.h b/sys/arm/xscale/i80321/i80321_intr.h
deleted file mode 100644
index 29003a0..0000000
--- a/sys/arm/xscale/i80321/i80321_intr.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*	$NetBSD: i80321_intr.h,v 1.5 2004/01/12 10:25:06 scw Exp $	*/
-
-/*-
- * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- *
- */
-
-#ifndef _I80321_INTR_H_
-#define _I80321_INTR_H_
-
-#define	ARM_IRQ_HANDLER	_C_LABEL(i80321_intr_dispatch)
-
-#ifndef _LOCORE
-
-#include <machine/armreg.h>
-#include <machine/cpufunc.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-
-void i80321_do_pending(void);
-
-extern __volatile uint32_t intr_enabled;
-extern uint32_t intr_steer;
-
-static __inline void __attribute__((__unused__))
-i80321_set_intrmask(void)
-{
-
-	__asm __volatile("mcr p6, 0, %0, c0, c0, 0"
-		:
-		: "r" (intr_enabled & ICU_INT_HWMASK));
-}
-
-static __inline void
-i80321_set_intrsteer(void)
-{
-
-	__asm __volatile("mcr p6, 0, %0, c4, c0, 0"
-	    :
-	    : "r" (intr_steer & ICU_INT_HWMASK));
-}
-
-#if defined ( CPU_XSCALE_80219 )
-#define INT_SWMASK														\
-	((1U << ICU_INT_bit26) |											\
-	 (1U << ICU_INT_bit25) |											\
-	 (1U << ICU_INT_bit23) |											\
-	 (1U << ICU_INT_bit22) |											\
-	 (1U << ICU_INT_bit7)  |											\
-	 (1U << ICU_INT_bit6)  |											\
-	 (1U << ICU_INT_bit5)  |											\
-	 (1U << ICU_INT_bit4))
-#else
-#define INT_SWMASK                                                      \
-        ((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) |                \
-         (1U << ICU_INT_bit5)  | (1U << ICU_INT_bit4))
-#endif
-
-#if 0
-static __inline void __attribute__((__unused__))
-i80321_splx(int new)
-{
-	extern __volatile uint32_t intr_enabled;
-	extern __volatile int current_spl_level;
-	extern __volatile int i80321_ipending;
-	extern void i80321_do_pending(void);
-	int oldirqstate, hwpend;
-
-	/* Don't let the compiler re-order this code with preceding code */
-	__insn_barrier();
-
-	current_spl_level = new;
-
-	hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
-	if (hwpend != 0) {
-		oldirqstate = disable_interrupts(PSR_I);
-		intr_enabled |= hwpend;
-		i80321_set_intrmask();
-		restore_interrupts(oldirqstate);
-	}
-
-	if ((i80321_ipending & INT_SWMASK) & ~new)
-		i80321_do_pending();
-}
-
-static __inline int __attribute__((__unused__))
-i80321_splraise(int ipl)
-{
-	extern __volatile int current_spl_level;
-	extern int i80321_imask[];
-	int	old;
-
-	old = current_spl_level;
-	current_spl_level |= i80321_imask[ipl];
-
-	/* Don't let the compiler re-order this code with subsequent code */
-	__insn_barrier();
-
-	return (old);
-}
-
-static __inline int __attribute__((__unused__))
-i80321_spllower(int ipl)
-{
-	extern __volatile int current_spl_level;
-	extern int i80321_imask[];
-	int old = current_spl_level;
-
-	i80321_splx(i80321_imask[ipl]);
-	return(old);
-}
-
-#endif
-#if !defined(EVBARM_SPL_NOINLINE)
-
-#define splx(new)		i80321_splx(new)
-#define	_spllower(ipl)		i80321_spllower(ipl)
-#define	_splraise(ipl)		i80321_splraise(ipl)
-void	_setsoftintr(int);
-
-#else
-
-int	_splraise(int);
-int	_spllower(int);
-void	splx(int);
-void	_setsoftintr(int);
-
-#endif /* ! EVBARM_SPL_NOINLINE */
-
-#endif /* _LOCORE */
-
-#endif /* _I80321_INTR_H_ */
diff --git a/sys/arm/xscale/i80321/i80321_mcu.c b/sys/arm/xscale/i80321/i80321_mcu.c
deleted file mode 100644
index a51a433..0000000
--- a/sys/arm/xscale/i80321/i80321_mcu.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*	$NetBSD: i80321_mcu.c,v 1.2 2003/07/15 00:24:54 lukem Exp $	*/
-
-/*-
- * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Intel i80321 I/O Processor memory controller support.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-
-#include <machine/bus.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-
-/*
- * i80321_sdram_bounds:
- *
- *	Retrieve the start and size of SDRAM.
- */
-void
-i80321_sdram_bounds(bus_space_tag_t st, bus_space_handle_t sh,
-    vm_paddr_t *start, vm_size_t *size)
-{
-	uint32_t sdbr, sbr0, sbr1;
-	uint32_t bank0, bank1;
-
-	sdbr = bus_space_read_4(st, sh, MCU_SDBR);
-	sbr0 = bus_space_read_4(st, sh, MCU_SBR0);
-	sbr1 = bus_space_read_4(st, sh, MCU_SBR1);
-
-#ifdef VERBOSE_INIT_ARM
-	printf("i80321: SBDR = 0x%08x SBR0 = 0x%08x SBR1 = 0x%08x\n",
-	    sdbr, sbr0, sbr1);
-#endif
-
-	*start = sdbr;
-
-	sdbr = (sdbr >> 25) & 0x1f;
-
-	sbr0 &= 0x3f;
-	sbr1 &= 0x3f;
-
-	bank0 = (sbr0 - sdbr) << 25;
-	bank1 = (sbr1 - sbr0) << 25;
-
-#ifdef VERBOSE_INIT_ARM
-	printf("i80321: BANK0 = 0x%08x BANK1 = 0x%08x\n", bank0, bank1);
-#endif
-
-	*size = bank0 + bank1;
-}
diff --git a/sys/arm/xscale/i80321/i80321_pci.c b/sys/arm/xscale/i80321/i80321_pci.c
deleted file mode 100644
index 5f78577..0000000
--- a/sys/arm/xscale/i80321/i80321_pci.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/*	$NetBSD: i80321_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $	*/
-
-/*-
- * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * PCI configuration support for i80321 I/O Processor chip.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/malloc.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/rman.h>
-
-#include <machine/bus.h>
-#include <machine/cpu.h>
-#include <machine/pcb.h>
-#include <vm/vm.h>
-#include <vm/pmap.h>
-#include <vm/vm_extern.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-#include <arm/xscale/i80321/i80321_intr.h>
-
-#include <dev/pci/pcib_private.h>
-#include "pcib_if.h"
-
-#include <dev/pci/pcireg.h>
-extern struct i80321_softc *i80321_softc;
-
-static int
-i80321_pci_probe(device_t dev)
-{
-	device_set_desc(dev, "i80321 PCI bus");
-	return (0);
-}
-
-static int
-i80321_pci_attach(device_t dev)
-{
-
-	uint32_t busno;
-	struct i80321_pci_softc *sc = device_get_softc(dev);
-
-	sc->sc_st = i80321_softc->sc_st;
-	sc->sc_atu_sh = i80321_softc->sc_atu_sh;
-	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
-	busno = PCIXSR_BUSNO(busno);
-	if (busno == 0xff)
-		busno = 0;
-	sc->sc_dev = dev;
-	sc->sc_busno = busno;
-	sc->sc_pciio = &i80321_softc->sc_pci_iot;
-	sc->sc_pcimem = &i80321_softc->sc_pci_memt;
-	sc->sc_mem = i80321_softc->sc_owin[0].owin_xlate_lo +
-	    VERDE_OUT_XLATE_MEM_WIN_SIZE;
-	
-	sc->sc_io = i80321_softc->sc_iow_vaddr;
-	/* Initialize memory and i/o rmans. */
-	sc->sc_io_rman.rm_type = RMAN_ARRAY;
-	sc->sc_io_rman.rm_descr = "I80321 PCI I/O Ports";
-	if (rman_init(&sc->sc_io_rman) != 0 ||
-		rman_manage_region(&sc->sc_io_rman,
-		sc->sc_io,
-		    sc->sc_io +
-		    VERDE_OUT_XLATE_IO_WIN_SIZE) != 0) {
-		panic("i80321_pci_probe: failed to set up I/O rman");
-	}
-	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
-	sc->sc_mem_rman.rm_descr = "I80321 PCI Memory";
-	if (rman_init(&sc->sc_mem_rman) != 0 ||
-	    rman_manage_region(&sc->sc_mem_rman,
-	    0, VERDE_OUT_XLATE_MEM_WIN_SIZE) != 0) {
-		panic("i80321_pci_probe: failed to set up memory rman");
-	}
-	sc->sc_irq_rman.rm_type = RMAN_ARRAY;
-	sc->sc_irq_rman.rm_descr = "i80321 PCI IRQs";
-	if (rman_init(&sc->sc_irq_rman) != 0 ||
-	    rman_manage_region(&sc->sc_irq_rman, 26, 32) != 0)
-		panic("i80321_pci_probe: failed to set up IRQ rman");
-	device_add_child(dev, "pci", -1);
-	return (bus_generic_attach(dev));
-}
-
-static int
-i80321_pci_maxslots(device_t dev)
-{
-	return (PCI_SLOTMAX);
-}
-
-
-
-static int
-i80321_pci_conf_setup(struct i80321_pci_softc *sc, int bus, int slot, int func,
-    int reg, uint32_t *addr)
-{
-	uint32_t busno;
-
-	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
-	busno = PCIXSR_BUSNO(busno);
-	if (busno == 0xff)
-		busno = 0;
-
-	/*
-	 * If the bus # is the same as our own, then use Type 0 cycles,
-	 * else use Type 1.
-	 *
-	 * XXX We should filter out all non-private devices here!
-	 * XXX How does private space interact with PCI-PCI bridges?
-	 */
-	if (bus == busno) {
-		if (slot > (31 - 16))
-			return (1);
-		/*
-		 * NOTE: PCI-X requires that that devices updated their
-		 * PCIXSR on every config write with the device number
-		 * specified in AD[15:11].  If we don't set this field,
-		 * each device could end of thinking it is at device 0,
-		 * which can cause a number of problems.  Doing this
-		 * unconditionally should be OK when only PCI devices
-		 * are present.
-		 */
-		bus &= 0xff;
-		slot &= 0x1f;
-		func &= 0x07;
-		
-		*addr = (1U << (slot + 16)) |
-		    (slot << 11) | (func << 8) | reg;
-	} else {
-		*addr = (bus << 16) | (slot << 11) | (func << 8) | reg | 1;
-	}
-
-	return (0);
-}
-
-static u_int32_t
-i80321_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
-    u_int reg, int bytes)
-{
-	struct i80321_pci_softc *sc = device_get_softc(dev);
-	uint32_t isr;
-	uint32_t addr;
-	u_int32_t ret = 0;
-	vm_offset_t va;
-	int err = 0;
-	if (i80321_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
-		return (-1);
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
-	    addr);
-
-	va = sc->sc_atu_sh;
-	switch (bytes) {
-	case 1:
-		err = badaddr_read((void*)(va + ATU_OCCDR + (reg & 3)), 1, &ret);
-		break;
-	case 2:
-		err = badaddr_read((void*)(va + ATU_OCCDR + (reg & 3)), 2, &ret);
-		break;
-	case 4:
-		err = badaddr_read((void *)(va + ATU_OCCDR), 4, &ret);
-		break;
-	default:
-		printf("i80321_read_config: invalid size %d\n", bytes);
-		ret = -1;
-	}
-	if (err) {
-
-		isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR);
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR,
-		    isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM|
-		    ATUISR_PTAT|ATUISR_PMPE));
-		return (-1);
-	}
-	return (ret);
-}
-
-static void
-i80321_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
-    u_int reg, u_int32_t data, int bytes)
-{
-	struct i80321_pci_softc *sc = device_get_softc(dev);
-	uint32_t addr;
-
-	if (i80321_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
-		return;
-
-
-	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
-	    addr);
-	switch (bytes) {
-	case 1:
-		bus_space_write_1(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR +
-		    (reg & 3), data);
-		break;
-	case 2:
-		bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR +
-		    (reg & 3), data);
-		break;
-	case 4:
-		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, data);
-		break;
-	default:
-		printf("i80321_pci_write_config: Invalid size : %d\n", bytes);
-	}
-
-}
-
-static int
-i80321_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
-{
-	struct i80321_pci_softc *sc = device_get_softc(dev);
-	switch (which) {
-	case PCIB_IVAR_DOMAIN:
-		*result = 0;
-		return (0);
-	case PCIB_IVAR_BUS:
-		*result = sc->sc_busno;
-		return (0);
-		
-	}
-	return (ENOENT);
-}
-
-static int
-i80321_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
-{
-	struct i80321_pci_softc * sc = device_get_softc(dev);
-
-	switch (which) {
-	case PCIB_IVAR_DOMAIN:
-		return (EINVAL);
-	case PCIB_IVAR_BUS:
-		sc->sc_busno = result;
-		return (0);
-	}
-	return (ENOENT);
-}
-
-static struct resource *
-i80321_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
-{
-	struct i80321_pci_softc *sc = device_get_softc(bus);	
-	struct resource *rv;
-	struct rman *rm;
-	bus_space_tag_t bt = NULL;
-	bus_space_handle_t bh = 0;
-
-	switch (type) {
-	case SYS_RES_IRQ:
-		rm = &sc->sc_irq_rman;
-		break;
-	case SYS_RES_MEMORY:
-		rm = &sc->sc_mem_rman;
-		bt = sc->sc_pcimem;
-		bh = (start >= 0x80000000 && start < 0x84000000) ? 0x80000000 :
-		    sc->sc_mem;
-		start &= (0x1000000 - 1);
-		end &= (0x1000000 - 1);
-		break;
-	case SYS_RES_IOPORT:
-		rm = &sc->sc_io_rman;
-		bt = sc->sc_pciio;
-		bh = sc->sc_io;
-		if (start < sc->sc_io) {
-			start = start - 0x90000000 + sc->sc_io;
-			end = end - 0x90000000 + sc->sc_io;
-		}
-		break;
-	default:
-		return (NULL);
-	}
-
-	rv = rman_reserve_resource(rm, start, end, count, flags, child);
-	if (rv == NULL)
-		return (NULL);
-	rman_set_rid(rv, *rid);
-	if (type != SYS_RES_IRQ) {
-		if (type == SYS_RES_MEMORY)
-			bh += (rman_get_start(rv));
-		rman_set_bustag(rv, bt);
-		rman_set_bushandle(rv, bh);
-		if (flags & RF_ACTIVE) {
-			if (bus_activate_resource(child, type, *rid, rv)) {
-				rman_release_resource(rv);
-				return (NULL);
-			}
-		}
-	}
-	return (rv);
-}
-
-static int
-i80321_pci_activate_resource(device_t bus, device_t child, int type, int rid,
-    struct resource *r)
-{
-	u_long p;
-	int error;
-	
-	if (type == SYS_RES_MEMORY) {
-		error = bus_space_map(rman_get_bustag(r),
-		    rman_get_bushandle(r), rman_get_size(r), 0, &p);
-		if (error)
-			return (error);
-		rman_set_bushandle(r, p);
-	
-	}
-	return (rman_activate_resource(r));
-}
-
-static int
-i80321_pci_setup_intr(device_t dev, device_t child,
-    struct resource *ires, int flags, driver_filter_t *filt,
-    driver_intr_t *intr, void *arg, void **cookiep)
-{
-	return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
-	    filt, intr, arg, cookiep));
-}
-
-static int
-i80321_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
-    void *cookie)
-{
-	return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
-}
-
-static device_method_t i80321_pci_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		i80321_pci_probe),
-	DEVMETHOD(device_attach,	i80321_pci_attach),
-	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	DEVMETHOD(device_suspend,	bus_generic_suspend),
-	DEVMETHOD(device_resume,	bus_generic_resume),
-
-	/* Bus interface */
-	DEVMETHOD(bus_read_ivar,	i80321_read_ivar),
-	DEVMETHOD(bus_write_ivar,	i80321_write_ivar),
-	DEVMETHOD(bus_alloc_resource,	i80321_pci_alloc_resource),
-	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
-	DEVMETHOD(bus_activate_resource, i80321_pci_activate_resource),
-	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
-	DEVMETHOD(bus_setup_intr,	i80321_pci_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	i80321_pci_teardown_intr),
-
-	/* pcib interface */
-	DEVMETHOD(pcib_maxslots,	i80321_pci_maxslots),
-	DEVMETHOD(pcib_read_config,	i80321_pci_read_config),
-	DEVMETHOD(pcib_write_config,	i80321_pci_write_config),
-	DEVMETHOD(pcib_route_interrupt,	machdep_pci_route_interrupt),
-
-	DEVMETHOD_END
-};
-
-static driver_t i80321_pci_driver = {
-	"pcib",
-	i80321_pci_methods,
-	sizeof(struct i80321_pci_softc),
-};
-
-static devclass_t i80321_pci_devclass;
-
-DRIVER_MODULE(ipci, iq, i80321_pci_driver, i80321_pci_devclass, 0, 0);
diff --git a/sys/arm/xscale/i80321/i80321_space.c b/sys/arm/xscale/i80321/i80321_space.c
deleted file mode 100644
index 64c2225..0000000
--- a/sys/arm/xscale/i80321/i80321_space.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*	$NetBSD: i80321_space.c,v 1.6 2003/10/06 15:43:35 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * bus_space functions for i80321 I/O Processor.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-
-#include <machine/pcb.h>
-
-#include <vm/vm.h>
-#include <vm/vm_kern.h>
-#include <vm/pmap.h>
-#include <vm/vm_page.h>
-#include <vm/vm_extern.h>
-
-#include <machine/bus.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-
-/* Prototypes for all the bus_space structure functions */
-bs_protos(i80321);
-bs_protos(i80321_io);
-bs_protos(i80321_mem);
-
-void
-i80321_bs_init(bus_space_tag_t bs, void *cookie)
-{
-
-	*bs = *arm_base_bs_tag;
-	bs->bs_privdata = cookie;
-}
-
-void
-i80321_io_bs_init(bus_space_tag_t bs, void *cookie)
-{
-
-	*bs = *arm_base_bs_tag;
-	bs->bs_privdata = cookie;
-
-	bs->bs_map = i80321_io_bs_map;
-	bs->bs_unmap = i80321_io_bs_unmap;
-	bs->bs_alloc = i80321_io_bs_alloc;
-	bs->bs_free = i80321_io_bs_free;
-
-}
-
-void
-i80321_mem_bs_init(bus_space_tag_t bs, void *cookie)
-{
-
-	*bs = *arm_base_bs_tag;
-	bs->bs_privdata = cookie;
-
-	bs->bs_map = i80321_mem_bs_map;
-	bs->bs_unmap = i80321_mem_bs_unmap;
-	bs->bs_alloc = i80321_mem_bs_alloc;
-	bs->bs_free = i80321_mem_bs_free;
-
-}
-
-/* *** Routines shared by i80321, PCI IO, and PCI MEM. *** */
-
-int
-i80321_bs_subregion(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset,
-    bus_size_t size, bus_space_handle_t *nbshp)
-{
-
-	*nbshp = bsh + offset;
-	return (0);
-}
-
-void
-i80321_bs_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset,
-    bus_size_t len, int flags)
-{
-
-	/* Nothing to do. */
-}
-
-/* *** Routines for PCI IO. *** */
-
-extern struct i80321_softc *i80321_softc;
-int
-i80321_io_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags,
-    bus_space_handle_t *bshp)
-{
-	struct i80321_softc *sc = i80321_softc;
-	vm_offset_t winvaddr;
-	uint32_t busbase;
-
-	if (bpa >= sc->sc_ioout_xlate &&
-	    bpa < (sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE)) {
-		busbase = sc->sc_ioout_xlate;
-		winvaddr = sc->sc_iow_vaddr;
-	} else
-		return (EINVAL);
-
-	if ((bpa + size) >= (busbase + VERDE_OUT_XLATE_IO_WIN_SIZE))
-		return (EINVAL);
-
-	/*
-	 * Found the window -- PCI I/O space is mapped at a fixed
-	 * virtual address by board-specific code.  Translate the
-	 * bus address to the virtual address.
-	 */
-	*bshp = winvaddr + (bpa - busbase);
-
-	return (0);
-}
-
-void
-i80321_io_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size)
-{
-
-	/* Nothing to do. */
-}
-
-int
-i80321_io_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend,
-    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
-    bus_addr_t *bpap, bus_space_handle_t *bshp)
-{
-
-	panic("i80321_io_bs_alloc(): not implemented");
-}
-
-void
-i80321_io_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size)
-{
-
-	panic("i80321_io_bs_free(): not implemented");
-}
-
-
-/* *** Routines for PCI MEM. *** */
-extern int badaddr_read(void *, int, void *);
-int
-i80321_mem_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags,
-    bus_space_handle_t *bshp)
-{
-
-	*bshp = (vm_offset_t)pmap_mapdev(bpa, size);
-	return (0);
-}
-
-void
-i80321_mem_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size)
-{
-
-	pmap_unmapdev((vm_offset_t)h, size);
-}
-
-int
-i80321_mem_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend,
-    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
-    bus_addr_t *bpap, bus_space_handle_t *bshp)
-{
-
-	panic("i80321_mem_bs_alloc(): not implemented");
-}
-
-void
-i80321_mem_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size)
-{
-
-	panic("i80321_mem_bs_free(): not implemented");
-}
diff --git a/sys/arm/xscale/i80321/i80321_timer.c b/sys/arm/xscale/i80321/i80321_timer.c
deleted file mode 100644
index 3b4e5a1..0000000
--- a/sys/arm/xscale/i80321/i80321_timer.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/*	$NetBSD: i80321_timer.c,v 1.7 2003/07/27 04:52:28 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Timer/clock support for the Intel i80321 I/O processor.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/time.h>
-#include <sys/bus.h>
-#include <sys/resource.h>
-#include <sys/rman.h>
-#include <sys/timetc.h>
-
-#include <machine/armreg.h>
-#include <machine/bus.h>
-#include <machine/cpu.h>
-#include <machine/cpufunc.h>
-#include <machine/frame.h>
-#include <machine/resource.h>
-#include <machine/intr.h>
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-
-#ifdef CPU_XSCALE_81342
-#define ICU_INT_TIMER0	(8) /* XXX: Can't include i81342reg.h because
-			       definitions overrides the ones from i80321reg.h
-			       */
-#endif
-#include "opt_timer.h"
-
-void (*i80321_hardclock_hook)(void) = NULL;
-struct i80321_timer_softc {
-	device_t	dev;
-} timer_softc;
-
-
-static unsigned i80321_timer_get_timecount(struct timecounter *tc);
-	
-
-static uint32_t counts_per_hz;
-
-#if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
-static uint32_t offset;
-static uint32_t last = -1;
-#endif
-
-static int ticked = 0;
-
-#ifndef COUNTS_PER_SEC
-#define	COUNTS_PER_SEC		200000000	/* 200MHz */
-#endif
-
-#define	COUNTS_PER_USEC		(COUNTS_PER_SEC / 1000000)
-
-static struct timecounter i80321_timer_timecounter = {
-	i80321_timer_get_timecount, /* get_timecount */
-	NULL,			    /* no poll_pps */
-	~0u,			    /* counter_mask */
-#if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
-	COUNTS_PER_SEC,
-#else
-	COUNTS_PER_SEC * 3,	 	   /* frequency */
-#endif
-	"i80321 timer",		    /* name */
-	1000			    /* quality */
-};
-
-static int
-i80321_timer_probe(device_t dev)
-{
-
-	device_set_desc(dev, "i80321 timer");
-	return (0);
-}
-
-static int
-i80321_timer_attach(device_t dev)
-{
-	timer_softc.dev = dev;
-
-	return (0);
-}
-
-static device_method_t i80321_timer_methods[] = {
-	DEVMETHOD(device_probe, i80321_timer_probe),
-	DEVMETHOD(device_attach, i80321_timer_attach),
-	{0, 0},
-};
-
-static driver_t i80321_timer_driver = {
-	"itimer",
-	i80321_timer_methods,
-	sizeof(struct i80321_timer_softc),
-};
-static devclass_t i80321_timer_devclass;
-
-DRIVER_MODULE(itimer, iq, i80321_timer_driver, i80321_timer_devclass, 0, 0);
-
-int	clockhandler(void *);
-
-
-static __inline uint32_t
-tmr1_read(void)
-{
-	uint32_t rv;
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mrc p6, 0, %0, c1, c9, 0"
-#else
-	__asm __volatile("mrc p6, 0, %0, c1, c1, 0"
-#endif
-		: "=r" (rv));
-	return (rv);
-}
-
-static __inline void
-tmr1_write(uint32_t val)
-{
-
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mcr p6, 0, %0, c1, c9, 0"
-#else
-	__asm __volatile("mcr p6, 0, %0, c1, c1, 0"
-#endif
-		:
-		: "r" (val));
-}
-
-static __inline uint32_t
-tcr1_read(void)
-{
-	uint32_t rv;
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mrc p6, 0, %0, c3, c9, 0"
-#else
-	__asm __volatile("mrc p6, 0, %0, c3, c1, 0"
-#endif
-		: "=r" (rv));
-	return (rv);
-}
-static __inline void
-tcr1_write(uint32_t val)
-{
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mcr p6, 0, %0, c3, c9, 0"
-#else
-	__asm __volatile("mcr p6, 0, %0, c3, c1, 0"
-#endif
-		:
-		: "r" (val));
-}
-
-static __inline void
-trr1_write(uint32_t val)
-{
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mcr p6, 0, %0, c5, c9, 0"
-#else
-	__asm __volatile("mcr p6, 0, %0, c5, c1, 0"
-#endif
-		:
-		: "r" (val));
-}
-
-static __inline uint32_t
-tmr0_read(void)
-{
-	uint32_t rv;
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mrc p6, 0, %0, c0, c9, 0"
-#else
-	__asm __volatile("mrc p6, 0, %0, c0, c1, 0"
-#endif
-		: "=r" (rv));
-	return (rv);
-}
-
-static __inline void
-tmr0_write(uint32_t val)
-{
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mcr p6, 0, %0, c0, c9, 0"
-#else
-	__asm __volatile("mcr p6, 0, %0, c0, c1, 0"
-#endif
-		:
-		: "r" (val));
-}
-
-static __inline uint32_t
-tcr0_read(void)
-{
-	uint32_t rv;
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mrc p6, 0, %0, c2, c9, 0"
-#else
-	__asm __volatile("mrc p6, 0, %0, c2, c1, 0"
-#endif
-		: "=r" (rv));
-	return (rv);
-}
-static __inline void
-tcr0_write(uint32_t val)
-{
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mcr p6, 0, %0, c2, c9, 0"
-#else
-	__asm __volatile("mcr p6, 0, %0, c2, c1, 0"
-#endif
-		:
-		: "r" (val));
-}
-
-static __inline void
-trr0_write(uint32_t val)
-{
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mcr p6, 0, %0, c4, c9, 0"
-#else
-	__asm __volatile("mcr p6, 0, %0, c4, c1, 0"
-#endif
-		:
-		: "r" (val));
-}
-
-static __inline void
-tisr_write(uint32_t val)
-{
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mcr p6, 0, %0, c6, c9, 0"
-#else
-	__asm __volatile("mcr p6, 0, %0, c6, c1, 0"
-#endif
-		:
-		: "r" (val));
-}
-
-static __inline uint32_t
-tisr_read(void)
-{
-	int ret;
-	
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mrc p6, 0, %0, c6, c9, 0" : "=r" (ret));
-#else
-	__asm __volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (ret));
-#endif
-	return (ret);
-}
-
-static unsigned
-i80321_timer_get_timecount(struct timecounter *tc)
-{
-#if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
-	uint32_t cur = tcr0_read();
-
-	if (cur > last && last != -1) {
-		offset += counts_per_hz;
-		if (ticked > 0)
-			ticked--;
-	}
-	if (ticked) {
-		offset += ticked * counts_per_hz;
-		ticked = 0;
-	}
-	return (counts_per_hz - cur + offset);
-#else
-	uint32_t ret;
-
-	__asm __volatile("mrc p14, 0, %0, c1, c0, 0\n"
-	    : "=r" (ret));
-	return (ret);
-#endif
-}
-
-/*
- * i80321_calibrate_delay:
- *
- *	Calibrate the delay loop.
- */
-void
-i80321_calibrate_delay(void)
-{
-
-	/*
-	 * Just use hz=100 for now -- we'll adjust it, if necessary,
-	 * in cpu_initclocks().
-	 */
-	counts_per_hz = COUNTS_PER_SEC / 100;
-
-	tmr0_write(0);			/* stop timer */
-	tisr_write(TISR_TMR0);		/* clear interrupt */
-	trr0_write(counts_per_hz);	/* reload value */
-	tcr0_write(counts_per_hz);	/* current value */
-
-	tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
-}
-
-/*
- * cpu_initclocks:
- *
- *	Initialize the clock and get them going.
- */
-void
-cpu_initclocks(void)
-{
-	u_int oldirqstate;
-	struct resource *irq;
-	int rid = 0;
-	void *ihl;
-	device_t dev = timer_softc.dev;
-
-	if (hz < 50 || COUNTS_PER_SEC % hz) {
-		printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
-		hz = 100;
-	}
-	tick = 1000000 / hz;	/* number of microseconds between interrupts */
-
-	/*
-	 * We only have one timer available; stathz and profhz are
-	 * always left as 0 (the upper-layer clock code deals with
-	 * this situation).
-	 */
-	if (stathz != 0)
-		printf("Cannot get %d Hz statclock\n", stathz);
-	stathz = 0;
-
-	if (profhz != 0)
-		printf("Cannot get %d Hz profclock\n", profhz);
-	profhz = 0;
-
-	/* Report the clock frequency. */
-
-	oldirqstate = disable_interrupts(PSR_I);
-
-	irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
-#ifdef CPU_XSCALE_81342
-	    ICU_INT_TIMER0, ICU_INT_TIMER0,
-#else
-	    ICU_INT_TMR0, ICU_INT_TMR0,
-#endif
-	    1, RF_ACTIVE);
-	if (!irq)
-		panic("Unable to setup the clock irq handler.\n");
-	else
-		bus_setup_intr(dev, irq, INTR_TYPE_CLK, clockhandler, NULL,
-		    NULL, &ihl);
-	tmr0_write(0);			/* stop timer */
-	tisr_write(TISR_TMR0);		/* clear interrupt */
-
-	counts_per_hz = COUNTS_PER_SEC / hz;
-
-	trr0_write(counts_per_hz);	/* reload value */
-	tcr0_write(counts_per_hz);	/* current value */
-	tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
-
-	tc_init(&i80321_timer_timecounter);
-	restore_interrupts(oldirqstate);
-	rid = 0;
-#if !defined(XSCALE_DISABLE_CCNT) && !defined(CPU_XSCALE_81342)
-	/* Enable the clock count register. */
-	__asm __volatile("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (rid));
-	rid &= ~(1 <<  3);
-	rid |= (1 << 2) | 1;
-	__asm __volatile("mcr p14, 0, %0, c0, c0, 0\n"
-	    : : "r" (rid));
-#endif
-}
-
-
-/*
- * DELAY:
- *
- *	Delay for at least N microseconds.
- */
-void
-DELAY(int n)
-{
-	uint32_t cur, last, delta, usecs;
-
-	/*
-	 * This works by polling the timer and counting the
-	 * number of microseconds that go by.
-	 */
-	last = tcr0_read();
-	delta = usecs = 0;
-
-	while (n > usecs) {
-		cur = tcr0_read();
-
-		/* Check to see if the timer has wrapped around. */
-		if (last < cur)
-			delta += (last + (counts_per_hz - cur));
-		else
-			delta += (last - cur);
-
-		last = cur;
-
-		if (delta >= COUNTS_PER_USEC) {
-			usecs += delta / COUNTS_PER_USEC;
-			delta %= COUNTS_PER_USEC;
-		}
-	}
-}
-
-/*
- * clockhandler:
- *
- *	Handle the hardclock interrupt.
- */
-int
-clockhandler(void *arg)
-{
-	struct trapframe *frame = arg;
-
-	ticked++;
-	tisr_write(TISR_TMR0);
-	hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
-
-	if (i80321_hardclock_hook != NULL)
-		(*i80321_hardclock_hook)();
-	return (FILTER_HANDLED);
-}
-
-void
-cpu_startprofclock(void)
-{
-}
-
-void
-cpu_stopprofclock(void)
-{
-	
-}
diff --git a/sys/arm/xscale/i80321/i80321_wdog.c b/sys/arm/xscale/i80321/i80321_wdog.c
deleted file mode 100644
index 9be98d2..0000000
--- a/sys/arm/xscale/i80321/i80321_wdog.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*	$NetBSD: i80321_wdog.c,v 1.6 2003/07/15 00:24:54 lukem Exp $	*/
-
-/*-
- * Copyright (c) 2005 Olivier Houchard
- * Copyright (c) 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Watchdog timer support for the Intel i80321 I/O processor.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/watchdog.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-
-#include <machine/bus.h>
-#include <machine/cpufunc.h>
-#include <machine/machdep.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-
-
-struct iopwdog_softc {
-	device_t dev;
-	int armed;
-	int wdog_period;
-};
-
-static __inline void
-wdtcr_write(uint32_t val)
-{
-
-#ifdef CPU_XSCALE_81342
-	__asm __volatile("mcr p6, 0, %0, c7, c9, 0"
-#else
-	__asm __volatile("mcr p6, 0, %0, c7, c1, 0"
-#endif
-		:
-		: "r" (val));
-}
-
-static void
-iopwdog_tickle(void *arg)
-{
-	struct iopwdog_softc *sc = arg;
-
-	if (!sc->armed)
-		return;
-	wdtcr_write(WDTCR_ENABLE1);
-	wdtcr_write(WDTCR_ENABLE2);
-}
-
-static int
-iopwdog_probe(device_t dev)
-{
-	struct iopwdog_softc *sc = device_get_softc(dev);
-	char buf[128];
-
-	/*
-	 * XXX Should compute the period based on processor speed.
-	 * For a 600MHz XScale core, the wdog must be tickled approx.
-	 * every 7 seconds.
-	 */
-
-	sc->wdog_period = 7;
-	sprintf(buf, "i80321 Watchdog, must be tickled every %d seconds",
-	    sc->wdog_period);
-	device_set_desc_copy(dev, buf);
-
-	return (0);
-}
-
-static void
-iopwdog_watchdog_fn(void *private, u_int cmd, int *error)
-{
-	struct iopwdog_softc *sc = private;
-
-	cmd &= WD_INTERVAL;
-	if (cmd > 0 && cmd <= 63
-	    && (uint64_t)1<<cmd <= (uint64_t)sc->wdog_period * 1000000000) {
-		/* Valid value -> Enable watchdog */
-		iopwdog_tickle(sc);
-		sc->armed = 1;
-		*error = 0;
-	} else {
-		/* Can't disable this watchdog! */
-		if (sc->armed)
-			*error = EOPNOTSUPP;
-	}
-}
-
-static int
-iopwdog_attach(device_t dev)
-{
-	struct iopwdog_softc *sc = device_get_softc(dev);
-	
-	sc->dev = dev;
-	sc->armed = 0;
-	EVENTHANDLER_REGISTER(watchdog_list, iopwdog_watchdog_fn, sc, 0);
-	return (0);
-}
-
-static device_method_t iopwdog_methods[] = {
-	DEVMETHOD(device_probe, iopwdog_probe),
-	DEVMETHOD(device_attach, iopwdog_attach),
-	{0, 0},
-};
-
-static driver_t iopwdog_driver = {
-	"iopwdog",
-	iopwdog_methods,
-	sizeof(struct iopwdog_softc),
-};
-static devclass_t iopwdog_devclass;
-
-DRIVER_MODULE(iopwdog, iq, iopwdog_driver, iopwdog_devclass, 0, 0);
diff --git a/sys/arm/xscale/i80321/i80321reg.h b/sys/arm/xscale/i80321/i80321reg.h
deleted file mode 100644
index 53617f9..0000000
--- a/sys/arm/xscale/i80321/i80321reg.h
+++ /dev/null
@@ -1,547 +0,0 @@
-/*	$NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $	*/
-
-/*-
- * Copyright (c) 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- *
- */
-
-#ifndef _ARM_XSCALE_I80321REG_H_
-#define _ARM_XSCALE_I80321REG_H_
-
-/*
- * Register definitions for the Intel 80321 (``Verde'') I/O processor,
- * based on the XScale core.
- */
-
-/*
- * Base i80321 memory map:
- *
- *	0x0000.0000 - 0x7fff.ffff	ATU Outbound Direct Addressing Window
- *	0x8000.0000 - 0x9001.ffff	ATU Outbound Translation Windows
- *	0x9002.0000 - 0xffff.dfff	External Memory
- *	0xffff.e000 - 0xffff.e8ff	Peripheral Memory Mapped Registers
- *	0xffff.e900 - 0xffff.ffff	Reserved
- */
-
-#define	VERDE_OUT_DIRECT_WIN_BASE	0x00000000UL
-#define	VERDE_OUT_DIRECT_WIN_SIZE	0x80000000UL
-
-#define	VERDE_OUT_XLATE_MEM_WIN_SIZE	0x04000000UL
-#define	VERDE_OUT_XLATE_IO_WIN_SIZE	0x00010000UL
-
-#define	VERDE_OUT_XLATE_MEM_WIN0_BASE	0x80000000UL
-#define	VERDE_OUT_XLATE_MEM_WIN1_BASE	0x84000000UL
-
-#define	VERDE_OUT_XLATE_IO_WIN0_BASE	0x90000000UL
-
-#define	VERDE_EXTMEM_BASE		0x90020000UL
-
-#define	VERDE_PMMR_BASE			0xffffe000UL
-#define	VERDE_PMMR_SIZE			0x00001700UL
-
-/*
- * Peripheral Memory Mapped Registers.  Defined as offsets
- * from the VERDE_PMMR_BASE.
- */
-#define	VERDE_ATU_BASE			0x0100
-#define	VERDE_ATU_SIZE			0x0100
-
-#define	VERDE_MU_BASE			0x0300
-#define	VERDE_MU_SIZE			0x0100
-
-#define	VERDE_DMA_BASE			0x0400
-#define	VERDE_DMA_BASE0			(VERDE_DMA_BASE + 0x00)
-#define	VERDE_DMA_BASE1			(VERDE_DMA_BASE + 0x40)
-#define	VERDE_DMA_SIZE			0x0100
-#define	VERDE_DMA_CHSIZE		0x0040
-
-#define	VERDE_MCU_BASE			0x0500
-#define	VERDE_MCU_SIZE			0x0100
-
-#if defined(CPU_XSCALE_80321)
-#define	VERDE_SSP_BASE			0x0600
-#define	VERDE_SSP_SIZE			0x0080
-#endif
-
-#define	VERDE_PBIU_BASE			0x0680
-#define	VERDE_PBIU_SIZE			0x0080
-
-#if defined(CPU_XSCALE_80321)
-#define	VERDE_AAU_BASE			0x0800
-#define	VERDE_AAU_SIZE			0x0100
-#endif
-
-#define	VERDE_I2C_BASE			0x1680
-#define	VERDE_I2C_BASE0			(VERDE_I2C_BASE + 0x00)
-#define	VERDE_I2C_BASE1			(VERDE_I2C_BASE + 0x20)
-#define	VERDE_I2C_SIZE			0x0080
-#define	VERDE_I2C_CHSIZE		0x0020
-
-/*
- * Address Translation Unit
- */
-	/* 0x00 - 0x38 -- PCI configuration space header */
-#define	ATU_IALR0	0x40	/* Inbound ATU Limit 0 */
-#define	ATU_IATVR0	0x44	/* Inbound ATU Xlate Value 0 */
-#define	ATU_ERLR	0x48	/* Expansion ROM Limit */
-#define	ATU_ERTVR	0x4c	/* Expansion ROM Xlate Value */
-#define	ATU_IALR1	0x50	/* Inbound ATU Limit 1 */
-#define	ATU_IALR2	0x54	/* Inbound ATU Limit 2 */
-#define	ATU_IATVR2	0x58	/* Inbound ATU Xlate Value 2 */
-#define	ATU_OIOWTVR	0x5c	/* Outbound I/O Window Xlate Value */
-#define	ATU_OMWTVR0	0x60	/* Outbound Mem Window Xlate Value 0 */
-#define	ATU_OUMWTVR0	0x64	/* Outbound Mem Window Xlate Value 0 Upper */
-#define	ATU_OMWTVR1	0x68	/* Outbound Mem Window Xlate Value 1 */
-#define	ATU_OUMWTVR1	0x6c	/* Outbound Mem Window Xlate Value 1 Upper */
-#define	ATU_OUDWTVR	0x78	/* Outbound Mem Direct Xlate Value Upper */
-#define	ATU_ATUCR	0x80	/* ATU Configuration */
-#define	ATU_PCSR	0x84	/* PCI Configuration and Status */
-#define	ATU_ATUISR	0x88	/* ATU Interrupt Status */
-#define	ATU_ATUIMR	0x8c	/* ATU Interrupt Mask */
-#define	ATU_IABAR3	0x90	/* Inbound ATU Base Address 3 */
-#define	ATU_IAUBAR3	0x94	/* Inbound ATU Base Address 3 Upper */
-#define	ATU_IALR3	0x98	/* Inbound ATU Limit 3 */
-#define	ATU_IATVR3	0x9c	/* Inbound ATU Xlate Value 3 */
-#define	ATU_OCCAR	0xa4	/* Outbound Configuration Cycle Address */
-#define	ATU_OCCDR	0xac	/* Outbound Configuration Cycle Data */
-#define	ATU_MSI_PORT	0xb4	/* MSI port */
-#define	ATU_PDSCR	0xbc	/* PCI Bus Drive Strength Control */
-#define	ATU_PCI_X_CAP_ID 0xe0	/* (1) */
-#define	ATU_PCI_X_NEXT	0xe1	/* (1) */
-#define	ATU_PCIXCMD	0xe2	/* PCI-X Command Register (2) */
-#define	ATU_PCIXSR	0xe4	/* PCI-X Status Register */
-
-#define	ATUCR_DRC_ALIAS		(1U << 19)
-#define	ATUCR_DAU2GXEN		(1U << 18)
-#define	ATUCR_P_SERR_MA		(1U << 16)
-#define	ATUCR_DTS		(1U << 15)
-#define	ATUCR_P_SERR_DIE	(1U << 9)
-#define	ATUCR_DAE		(1U << 8)
-#define	ATUCR_BIST_IE		(1U << 3)
-#define	ATUCR_OUT_EN		(1U << 1)
-
-#define	PCSR_DAAAPE		(1U << 18)
-#define	PCSR_PCI_X_CAP		(3U << 16)
-#define	PCSR_PCI_X_CAP_BORING	(0 << 16)
-#define	PCSR_PCI_X_CAP_66	(1U << 16)
-#define	PCSR_PCI_X_CAP_100	(2U << 16)
-#define	PCSR_PCI_X_CAP_133	(3U << 16)
-#define	PCSR_OTQB		(1U << 15)
-#define	PCSR_IRTQB		(1U << 14)
-#define	PCSR_DTV		(1U << 12)
-#define	PCSR_BUS66		(1U << 10)
-#define	PCSR_BUS64		(1U << 8)
-#define	PCSR_RIB		(1U << 5)
-#define	PCSR_RPB		(1U << 4)
-#define	PCSR_CCR		(1U << 2)
-#define	PCSR_CPR		(1U << 1)
-
-#define	ATUISR_IMW1BU		(1U << 14)
-#define	ATUISR_ISCEM		(1U << 13)
-#define	ATUISR_RSCEM		(1U << 12)
-#define	ATUISR_PST		(1U << 11)
-#define	ATUISR_P_SERR_ASRT	(1U << 10)
-#define	ATUISR_DPE		(1U << 9)
-#define	ATUISR_BIST		(1U << 8)
-#define	ATUISR_IBMA		(1U << 7)
-#define	ATUISR_P_SERR_DET	(1U << 4)
-#define	ATUISR_PMA		(1U << 3)
-#define	ATUISR_PTAM		(1U << 2)
-#define	ATUISR_PTAT		(1U << 1)
-#define	ATUISR_PMPE		(1U << 0)
-
-#define	ATUIMR_IMW1BU		(1U << 11)
-#define	ATUIMR_ISCEM		(1U << 10)
-#define	ATUIMR_RSCEM		(1U << 9)
-#define	ATUIMR_PST		(1U << 8)
-#define	ATUIMR_DPE		(1U << 7)
-#define	ATUIMR_P_SERR_ASRT	(1U << 6)
-#define	ATUIMR_PMA		(1U << 5)
-#define	ATUIMR_PTAM		(1U << 4)
-#define	ATUIMR_PTAT		(1U << 3)
-#define	ATUIMR_PMPE		(1U << 2)
-#define	ATUIMR_IE_SERR_EN	(1U << 1)
-#define	ATUIMR_ECC_TAE		(1U << 0)
-
-#define	PCIXCMD_MOST_1		(0 << 4)
-#define	PCIXCMD_MOST_2		(1 << 4)
-#define	PCIXCMD_MOST_3		(2 << 4)
-#define	PCIXCMD_MOST_4		(3 << 4)
-#define	PCIXCMD_MOST_8		(4 << 4)
-#define	PCIXCMD_MOST_12		(5 << 4)
-#define	PCIXCMD_MOST_16		(6 << 4)
-#define	PCIXCMD_MOST_32		(7 << 4)
-#define	PCIXCMD_MOST_MASK	(7 << 4)
-#define	PCIXCMD_MMRBC_512	(0 << 2)
-#define	PCIXCMD_MMRBC_1024	(1 << 2)
-#define	PCIXCMD_MMRBC_2048	(2 << 2)
-#define	PCIXCMD_MMRBC_4096	(3 << 2)
-#define	PCIXCMD_MMRBC_MASK	(3 << 2)
-#define	PCIXCMD_ERO		(1U << 1)
-#define	PCIXCMD_DPERE		(1U << 0)
-
-#define	PCIXSR_RSCEM		(1U << 29)
-#define	PCIXSR_DMCRS_MASK	(7 << 26)
-#define	PCIXSR_DMOST_MASK	(7 << 23)
-#define	PCIXSR_COMPLEX		(1U << 20)
-#define	PCIXSR_USC		(1U << 19)
-#define	PCIXSR_SCD		(1U << 18)
-#define	PCIXSR_133_CAP		(1U << 17)
-#define	PCIXSR_32PCI		(1U << 16)	/* 0 = 32, 1 = 64 */
-#define	PCIXSR_BUSNO(x)		(((x) & 0xff00) >> 8)
-#define	PCIXSR_DEVNO(x)		(((x) & 0xf8) >> 3)
-#define	PCIXSR_FUNCNO(x)	((x) & 0x7)
-
-/*
- * Memory Controller Unit
- */
-#define	MCU_SDIR		0x00	/* DDR SDRAM Init. Register */
-#define	MCU_SDCR		0x04	/* DDR SDRAM Control Register */
-#define	MCU_SDBR		0x08	/* SDRAM Base Register */
-#define	MCU_SBR0		0x0c	/* SDRAM Boundary 0 */
-#define	MCU_SBR1		0x10	/* SDRAM Boundary 1 */
-#define	MCU_ECCR		0x34	/* ECC Control Register */
-#define	MCU_ELOG0		0x38	/* ECC Log 0 */
-#define	MCU_ELOG1		0x3c	/* ECC Log 1 */
-#define	MCU_ECAR0		0x40	/* ECC address 0 */
-#define	MCU_ECAR1		0x44	/* ECC address 1 */
-#define	MCU_ECTST		0x48	/* ECC test register */
-#define	MCU_MCISR		0x4c	/* MCU Interrupt Status Register */
-#define	MCU_RFR			0x50	/* Refresh Frequency Register */
-#define	MCU_DBUDSR		0x54	/* Data Bus Pull-up Drive Strength */
-#define	MCU_DBDDSR		0x58	/* Data Bus Pull-down Drive Strength */
-#define	MCU_CUDSR		0x5c	/* Clock Pull-up Drive Strength */
-#define	MCU_CDDSR		0x60	/* Clock Pull-down Drive Strength */
-#define	MCU_CEUDSR		0x64	/* Clock En Pull-up Drive Strength */
-#define	MCU_CEDDSR		0x68	/* Clock En Pull-down Drive Strength */
-#define	MCU_CSUDSR		0x6c	/* Chip Sel Pull-up Drive Strength */
-#define	MCU_CSDDSR		0x70	/* Chip Sel Pull-down Drive Strength */
-#define	MCU_REUDSR		0x74	/* Rx En Pull-up Drive Strength */
-#define	MCU_REDDSR		0x78	/* Rx En Pull-down Drive Strength */
-#define	MCU_ABUDSR		0x7c	/* Addr Bus Pull-up Drive Strength */
-#define	MCU_ABDDSR		0x80	/* Addr Bus Pull-down Drive Strength */
-#define	MCU_DSDR		0x84	/* Data Strobe Delay Register */
-#define	MCU_REDR		0x88	/* Rx Enable Delay Register */
-
-#define	SDCR_DIMMTYPE		(1U << 1)	/* 0 = unbuf, 1 = reg */
-#define	SDCR_BUSWIDTH		(1U << 2)	/* 0 = 64, 1 = 32 */
-
-#define	SBRx_TECH		(1U << 31)
-#define	SBRx_BOUND		0x0000003f
-
-#define	ECCR_SBERE		(1U << 0)
-#define	ECCR_MBERE		(1U << 1)
-#define	ECCR_SBECE		(1U << 2)
-#define	ECCR_ECCEN		(1U << 3)
-
-#define	ELOGx_SYNDROME		0x000000ff
-#define	ELOGx_ERRTYPE		(1U << 8)	/* 1 = multi-bit */
-#define	ELOGx_RW		(1U << 12)	/* 1 = write error */
-	/*
-	 * Dev ID	Func		Requester
-	 * 2		0		XScale core
-	 * 2		1		ATU
-	 * 13		0		DMA channel 0
-	 * 13		1		DMA channel 1
-	 * 26		0		ATU
-	 */
-#define	ELOGx_REQ_DEV(x)	(((x) >> 19) & 0x1f)
-#define	ELOGx_REQ_FUNC(x)	(((x) >> 16) & 0x3)
-
-#define	MCISR_ECC_ERR0		(1U << 0)
-#define	MCISR_ECC_ERR1		(1U << 1)
-#define	MCISR_ECC_ERRN		(1U << 2)
-
-/*
- * Timers
- *
- * The i80321 timer registers are available in both memory-mapped
- * and coprocessor spaces.  Most of the registers are read-only
- * if memory-mapped, so we access them via coprocessor space.
- *
- *	TMR0	cp6 c0,1	0xffffe7e0
- *	TMR1	cp6 c1,1	0xffffe7e4
- *	TCR0	cp6 c2,1	0xffffe7e8
- *	TCR1	cp6 c3,1	0xffffe7ec
- *	TRR0	cp6 c4,1	0xffffe7f0
- *	TRR1	cp6 c5,1	0xffffe7f4
- *	TISR	cp6 c6,1	0xffffe7f8
- *	WDTCR	cp6 c7,1	0xffffe7fc
- */
-
-#define	TMRx_TC			(1U << 0)
-#define	TMRx_ENABLE		(1U << 1)
-#define	TMRx_RELOAD		(1U << 2)
-#define	TMRx_CSEL_CORE		(0 << 4)
-#define	TMRx_CSEL_CORE_div4	(1 << 4)
-#define	TMRx_CSEL_CORE_div8	(2 << 4)
-#define	TMRx_CSEL_CORE_div16	(3 << 4)
-
-#define	TISR_TMR0		(1U << 0)
-#define	TISR_TMR1		(1U << 1)
-
-#define	WDTCR_ENABLE1		0x1e1e1e1e
-#define	WDTCR_ENABLE2		0xe1e1e1e1
-
-/*
- * Interrupt Controller Unit.
- *
- *	INTCTL	cp6 c0,0	0xffffe7d0
- *	INTSTR	cp6 c4,0	0xffffe7d4
- *	IINTSRC	cp6 c8,0	0xffffe7d8
- *	FINTSRC	cp6 c9,0	0xffffe7dc
- *	PIRSR			0xffffe1ec
- */
-
-#define	ICU_PIRSR		0x01ec
-#define	ICU_GPOE		0x07c4
-#define	ICU_GPID		0x07c8
-#define	ICU_GPOD		0x07cc
-
-/*
- * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE
- * INTERRUPTS.  See i80321_icu.c
- */
-#define	ICU_INT_HPI		31	/* high priority interrupt */
-#define	ICU_INT_XINT0		27	/* external interrupts */
-#define	ICU_INT_XINT(x)		((x) + ICU_INT_XINT0)
-#define	ICU_INT_bit26		26
-
-#if defined (CPU_XSCALE_80219)
-#define	ICU_INT_bit25		25	/* reserved */
-#else
-/* CPU_XSCALE_80321 */
-#define	ICU_INT_SSP		25	/* SSP serial port */
-#endif
-
-#define	ICU_INT_MUE		24	/* msg unit error */
-
-#if defined (CPU_XSCALE_80219)
-#define	ICU_INT_bit23		23	/* reserved */
-#else
-/* CPU_XSCALE_80321 */
-#define	ICU_INT_AAUE		23	/* AAU error */
-#endif
-
-#define	ICU_INT_bit22		22
-#define	ICU_INT_DMA1E		21	/* DMA Ch 1 error */
-#define	ICU_INT_DMA0E		20	/* DMA Ch 0 error */
-#define	ICU_INT_MCUE		19	/* memory controller error */
-#define	ICU_INT_ATUE		18	/* ATU error */
-#define	ICU_INT_BIUE		17	/* bus interface unit error */
-#define	ICU_INT_PMU		16	/* XScale PMU */
-#define	ICU_INT_PPM		15	/* peripheral PMU */
-#define	ICU_INT_BIST		14	/* ATU Start BIST */
-#define	ICU_INT_MU		13	/* messaging unit */
-#define	ICU_INT_I2C1		12	/* i2c unit 1 */
-#define	ICU_INT_I2C0		11	/* i2c unit 0 */
-#define	ICU_INT_TMR1		10	/* timer 1 */
-#define	ICU_INT_TMR0		9	/* timer 0 */
-#define	ICU_INT_CPPM		8	/* core processor PMU */
-
-#if defined(CPU_XSCALE_80219)
-#define	ICU_INT_bit7		7 /* reserved */
-#define	ICU_INT_bit6		6 /* reserved */
-#else
-/* CPU_XSCALE_80321 */
-#define	ICU_INT_AAU_EOC		7	/* AAU end-of-chain */
-#define	ICU_INT_AAU_EOT		6	/* AAU end-of-transfer */
-#endif
-
-#define	ICU_INT_bit5		5
-#define	ICU_INT_bit4		4
-#define	ICU_INT_DMA1_EOC	3	/* DMA1 end-of-chain */
-#define	ICU_INT_DMA1_EOT	2	/* DMA1 end-of-transfer */
-#define	ICU_INT_DMA0_EOC	1	/* DMA0 end-of-chain */
-#define	ICU_INT_DMA0_EOT	0	/* DMA0 end-of-transfer */
-
-#if defined (CPU_XSCALE_80219)
-#define	ICU_INT_HWMASK		(0xffffffff &	 \
-							 ~((1 << ICU_INT_bit26) |	\
-							   (1 << ICU_INT_bit25) |	\
-							   (1 << ICU_INT_bit23) |	\
-							   (1 << ICU_INT_bit22) |	\
-							   (1 << ICU_INT_bit7)  |	\
-							   (1 << ICU_INT_bit6)  |	\
-							   (1 << ICU_INT_bit5)  |	\
-							   (1 << ICU_INT_bit4)))
-
-#else
-/* CPU_XSCALE_80321 */
-#define	ICU_INT_HWMASK		(0xffffffff & \
-					~((1 << ICU_INT_bit26) | \
-					  (1 << ICU_INT_bit22) | \
-					  (1 << ICU_INT_bit5)  | \
-					  (1 << ICU_INT_bit4)))
-#endif
-
-/*
- * SSP Serial Port
- */
-#if defined (CPU_XSCALE_80321)
-
-#define	SSP_SSCR0	0x00		/* SSC control 0 */
-#define	SSP_SSCR1	0x04		/* SSC control 1 */
-#define	SSP_SSSR	0x08		/* SSP status */
-#define	SSP_SSITR	0x0c		/* SSP interrupt test */
-#define	SSP_SSDR	0x10		/* SSP data */
-
-#define	SSP_SSCR0_DSIZE(x)	((x) - 1)/* data size: 4..16 */
-#define	SSP_SSCR0_FRF_SPI	(0 << 4) /* Motorola Serial Periph Iface */
-#define	SSP_SSCR0_FRF_SSP	(1U << 4)/* TI Sync. Serial Protocol */
-#define	SSP_SSCR0_FRF_UWIRE	(2U << 4)/* NatSemi Microwire */
-#define	SSP_SSCR0_FRF_rsvd	(3U << 4)/* reserved */
-#define	SSP_SSCR0_ECS		(1U << 6)/* external clock select */
-#define	SSP_SSCR0_SSE		(1U << 7)/* sync. serial port enable */
-#define	SSP_SSCR0_SCR(x)	((x) << 8)/* serial clock rate */
-					  /* bit rate = 3.6864 * 10e6 /
-					        (2 * (SCR + 1)) */
-
-#define	SSP_SSCR1_RIE		(1U << 0)/* Rx FIFO interrupt enable */
-#define	SSP_SSCR1_TIE		(1U << 1)/* Tx FIFO interrupt enable */
-#define	SSP_SSCR1_LBM		(1U << 2)/* loopback mode enable */
-#define	SSP_SSCR1_SPO		(1U << 3)/* Moto SPI SSCLK pol. (1 = high) */
-#define	SSP_SSCR1_SPH		(1U << 4)/* Moto SPI SSCLK phase:
-					    0 = inactive full at start,
-						1/2 at end of frame
-					    1 = inactive 1/2 at start,
-						full at end of frame */
-#define	SSP_SSCR1_MWDS		(1U << 5)/* Microwire data size:
-					    0 = 8 bit
-					    1 = 16 bit */
-#define	SSP_SSCR1_TFT		(((x) - 1) << 6) /* Tx FIFO threshold */
-#define	SSP_SSCR1_RFT		(((x) - 1) << 10)/* Rx FIFO threshold */
-#define	SSP_SSCR1_EFWR		(1U << 14)/* enab. FIFO write/read */
-#define	SSP_SSCR1_STRF		(1U << 15)/* FIFO write/read FIFO select:
-					     0 = Tx FIFO
-					     1 = Rx FIFO */
-
-#define	SSP_SSSR_TNF		(1U << 2)/* Tx FIFO not full */
-#define	SSP_SSSR_RNE		(1U << 3)/* Rx FIFO not empty */
-#define	SSP_SSSR_BSY		(1U << 4)/* SSP is busy */
-#define	SSP_SSSR_TFS		(1U << 5)/* Tx FIFO service request */
-#define	SSP_SSSR_RFS		(1U << 6)/* Rx FIFO service request */
-#define	SSP_SSSR_ROR		(1U << 7)/* Rx FIFO overrun */
-#define	SSP_SSSR_TFL(x)		(((x) >> 8) & 0xf) /* Tx FIFO level */
-#define	SSP_SSSR_RFL(x)		(((x) >> 12) & 0xf)/* Rx FIFO level */
-
-#define	SSP_SSITR_TTFS		(1U << 5)/* Test Tx FIFO service */
-#define	SSP_SSITR_TRFS		(1U << 6)/* Test Rx FIFO service */
-#define	SSP_SSITR_TROR		(1U << 7)/* Test Rx overrun */
-
-#endif /* CPU_XSCALE_80321 */
-
-/*
- * Peripheral Bus Interface Unit
- */
-
-#define PBIU_PBCR		0x00	/* PBIU Control Register */
-#define PBIU_PBBAR0		0x08	/* PBIU Base Address Register 0 */
-#define PBIU_PBLR0		0x0c	/* PBIU Limit Register 0 */
-#define PBIU_PBBAR1		0x10	/* PBIU Base Address Register 1 */
-#define PBIU_PBLR1		0x14	/* PBIU Limit Register 1 */
-#define PBIU_PBBAR2		0x18	/* PBIU Base Address Register 2 */
-#define PBIU_PBLR2		0x1c	/* PBIU Limit Register 2 */
-#define PBIU_PBBAR3		0x20	/* PBIU Base Address Register 3 */
-#define PBIU_PBLR3		0x24	/* PBIU Limit Register 3 */
-#define PBIU_PBBAR4		0x28	/* PBIU Base Address Register 4 */
-#define PBIU_PBLR4		0x2c	/* PBIU Limit Register 4 */
-#define PBIU_PBBAR5		0x30	/* PBIU Base Address Register 5 */
-#define PBIU_PBLR5		0x34	/* PBIU Limit Register 5 */
-#define PBIU_DSCR		0x38	/* PBIU Drive Strength Control Reg. */
-#define PBIU_MBR0		0x40	/* PBIU Memory-less Boot Reg. 0 */
-#define PBIU_MBR1		0x60	/* PBIU Memory-less Boot Reg. 1 */
-#define PBIU_MBR2		0x64	/* PBIU Memory-less Boot Reg. 2 */
-
-#define	PBIU_PBCR_PBIEN		(1 << 0)
-#define	PBIU_PBCR_PBI100	(1 << 1)
-#define	PBIU_PBCR_PBI66		(2 << 1)
-#define	PBIU_PBCR_PBI33		(3 << 1)
-#define	PBIU_PBCR_PBBEN		(1 << 3)
-
-#define	PBIU_PBARx_WIDTH8	(0 << 0)
-#define	PBIU_PBARx_WIDTH16	(1 << 0)
-#define	PBIU_PBARx_WIDTH32	(2 << 0)
-#define	PBIU_PBARx_ADWAIT4	(0 << 2)
-#define	PBIU_PBARx_ADWAIT8	(1 << 2)
-#define	PBIU_PBARx_ADWAIT12	(2 << 2)
-#define	PBIU_PBARx_ADWAIT16	(3 << 2)
-#define	PBIU_PBARx_ADWAIT20	(4 << 2)
-#define	PBIU_PBARx_RCWAIT1	(0 << 6)
-#define	PBIU_PBARx_RCWAIT4	(1 << 6)
-#define	PBIU_PBARx_RCWAIT8	(2 << 6)
-#define	PBIU_PBARx_RCWAIT12	(3 << 6)
-#define	PBIU_PBARx_RCWAIT16	(4 << 6)
-#define	PBIU_PBARx_RCWAIT20	(5 << 6)
-#define	PBIU_PBARx_FWE		(1 << 9)
-#define	PBIU_BASE_MASK		0xfffff000U
-
-#define	PBIU_PBLRx_SIZE(x)	(~((x) - 1))
-
-/*
- * Messaging Unit
- */
-#define MU_IMR0			0x0010	/* MU Inbound Message Register 0 */
-#define MU_IMR1			0x0014	/* MU Inbound Message Register 1 */
-#define MU_OMR0			0x0018	/* MU Outbound Message Register 0 */
-#define MU_OMR1			0x001c	/* MU Outbound Message Register 1 */
-#define MU_IDR			0x0020	/* MU Inbound Doorbell Register */
-#define MU_IISR			0x0024	/* MU Inbound Interrupt Status Reg */
-#define MU_IIMR			0x0028	/* MU Inbound Interrupt Mask Reg */
-#define MU_ODR			0x002c	/* MU Outbound Doorbell Register */
-#define MU_OISR			0x0030	/* MU Outbound Interrupt Status Reg */
-#define MU_OIMR			0x0034	/* MU Outbound Interrupt Mask Reg */
-#define MU_MUCR			0x0050	/* MU Configuration Register */
-#define MU_QBAR			0x0054	/* MU Queue Base Address Register */
-#define MU_IFHPR		0x0060	/* MU Inbound Free Head Pointer Reg */
-#define MU_IFTPR		0x0064	/* MU Inbound Free Tail Pointer Reg */
-#define MU_IPHPR		0x0068	/* MU Inbound Post Head Pointer Reg */
-#define MU_IPTPR		0x006c	/* MU Inbound Post Tail Pointer Reg */
-#define MU_OFHPR		0x0070	/* MU Outbound Free Head Pointer Reg */
-#define MU_OFTPR		0x0074	/* MU Outbound Free Tail Pointer Reg */
-#define MU_OPHPR		0x0078	/* MU Outbound Post Head Pointer Reg */
-#define MU_OPTPR		0x007c	/* MU Outbound Post Tail Pointer Reg */
-#define MU_IAR			0x0080	/* MU Index Address Register */
-
-#define MU_IIMR_IRI	(1 << 6)	/* Index Register Interrupt */
-#define MU_IIMR_OFQFI	(1 << 5)	/* Outbound Free Queue Full Int. */
-#define MU_IIMR_IPQI	(1 << 4)	/* Inbound Post Queue Interrupt */
-#define MU_IIMR_EDI	(1 << 3)	/* Error Doorbell Interrupt */
-#define MU_IIMR_IDI	(1 << 2)	/* Inbound Doorbell Interrupt */
-#define MU_IIMR_IM1I	(1 << 1)	/* Inbound Message 1 Interrupt */
-#define MU_IIMR_IM0I	(1 << 0)	/* Inbound Message 0 Interrupt */
-
-#endif /* _ARM_XSCALE_I80321REG_H_ */
diff --git a/sys/arm/xscale/i80321/i80321var.h b/sys/arm/xscale/i80321/i80321var.h
deleted file mode 100644
index 0fead25..0000000
--- a/sys/arm/xscale/i80321/i80321var.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*	$NetBSD: i80321var.h,v 1.8 2003/10/06 16:06:06 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- *
- */
-
-#ifndef _ARM_XSCALE_I80321VAR_H_
-#define	_ARM_XSCALE_I80321VAR_H_
-
-#include <sys/queue.h>
-#include <dev/pci/pcivar.h>
-#include <sys/rman.h>
-
-extern struct bus_space i80321_bs_tag;
-
-struct i80321_softc {
-	device_t 		dev;
-	bus_space_tag_t 	sc_st;
-	bus_space_handle_t	sc_sh;
-	/* Handles for the various subregions. */
-	bus_space_handle_t 	sc_atu_sh;
-	bus_space_handle_t 	sc_mcu_sh;
-	int			sc_is_host;
-
-	/*
-	 * We expect the board-specific front-end to have already mapped
-	 * the PCI I/O space .. it is only 64K, and I/O mappings tend to
-	 * be smaller than a page size, so it's generally more efficient
-	 * to map them all into virtual space in one fell swoop.
-	 */
-	vm_offset_t		sc_iow_vaddr;		/* I/O window vaddr */
-
-	/*
-	 * Variables that define the Inbound windows.  The base address of
-	 * 0-2 are configured by a host via BARs.  The xlate variable
-	 * defines the start of the local address space that it maps to.
-	 * The size variable defines the byte size.
-	 *
-	 * The first 3 windows are for incoming PCI memory read/write
-	 * cycles from a host.  The 4th window, not configured by the
-	 * host (as it outside the normal BAR range) is the inbound
-	 * window for PCI devices controlled by the i80321.
-	 */
-	struct {
-		uint32_t iwin_base_hi;
-		uint32_t iwin_base_lo;
-		uint32_t iwin_xlate;
-		uint32_t iwin_size;
-	} sc_iwin[4];
-
-	/*
-	 * Variables that define the Outbound windows.
-	 */
-	struct {
-		uint32_t owin_xlate_lo;
-		uint32_t owin_xlate_hi;
-	} sc_owin[2];
-
-	/*
-	 * This is the PCI address that the Outbound I/O
-	 * window maps to.
-	 */
-	uint32_t		sc_ioout_xlate;
-
-	/* Bus space, DMA, and PCI tags for the PCI bus (private devices). */
-	struct bus_space 	sc_pci_iot;
-	struct bus_space 	sc_pci_memt;
-
-	/* GPIO state */
-	uint8_t sc_gpio_dir;    /* GPIO pin direction (1 == output) */
-	uint8_t sc_gpio_val;    /* GPIO output pin value */
-	struct rman sc_irq_rman;
-			
-};
-
-
-struct i80321_pci_softc {
-	device_t 		sc_dev;
-	bus_space_tag_t 	sc_st;
-	bus_space_handle_t 	sc_atu_sh;
-	bus_space_tag_t		sc_pciio;
-	bus_space_tag_t		sc_pcimem;
-	int			sc_busno;
-	struct rman		sc_mem_rman;
-	struct rman		sc_io_rman;
-	struct rman		sc_irq_rman;
-	uint32_t		sc_mem;
-	uint32_t		sc_io;
-};
-
-void	i80321_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
-	    vm_paddr_t *, vm_size_t *);
-
-void	i80321_attach(struct i80321_softc *);
-void	i80321_calibrate_delay(void);
-
-void	i80321_bs_init(bus_space_tag_t, void *);
-void	i80321_io_bs_init(bus_space_tag_t, void *);
-void	i80321_mem_bs_init(bus_space_tag_t, void *);
-extern int machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin);
-
-
-#endif /* _ARM_XSCALE_I80321VAR_H_ */
diff --git a/sys/arm/xscale/i80321/iq31244_7seg.c b/sys/arm/xscale/i80321/iq31244_7seg.c
deleted file mode 100644
index 3737094..0000000
--- a/sys/arm/xscale/i80321/iq31244_7seg.c
+++ /dev/null
@@ -1,390 +0,0 @@
-/*	$NetBSD: iq31244_7seg.c,v 1.2 2003/07/15 00:25:01 lukem Exp $	*/
-
-/*-
- * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * Support for the 7-segment display on the Intel IQ31244.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/bus.h>
-#include <sys/sysctl.h>
-
-#include <machine/bus.h>
-
-#include <arm/xscale/i80321/iq80321reg.h>
-#include <arm/xscale/i80321/iq80321var.h>
-
-#define	WRITE(x, v)	*((__volatile uint8_t *) (x)) = (v)
-
-static int snakestate;
-
-/*
- * The 7-segment display looks like so:
- *
- *         A
- *	+-----+
- *	|     |
- *    F	|     | B
- *	|  G  |
- *	+-----+
- *	|     |
- *    E	|     | C
- *	|  D  |
- *	+-----+ o  DP
- *
- * Setting a bit clears the corresponding segment on the
- * display.
- */
-#define	SEG_A			(1 << 0)
-#define	SEG_B			(1 << 1)
-#define	SEG_C			(1 << 2)
-#define	SEG_D			(1 << 3)
-#define	SEG_E			(1 << 4)
-#define	SEG_F			(1 << 5)
-#define	SEG_G			(1 << 6)
-#define	SEG_DP			(1 << 7)
-
-static const uint8_t digitmap[] = {
-/*	+#####+
- *	#     #
- *	#     #
- *	#     #
- *	+-----+
- *	#     #
- *	#     #
- *	#     #
- *	+#####+
- */
-	SEG_G,
-
-/*	+-----+
- *	|     #
- *	|     #
- *	|     #
- *	+-----+
- *	|     #
- *	|     #
- *	|     #
- *	+-----+
- */
-	SEG_A|SEG_D|SEG_E|SEG_F|SEG_G,
-
-/*	+#####+
- *	|     #
- *	|     #
- *	|     #
- *	+#####+
- *	#     |
- *	#     |
- *	#     |
- *	+#####+
- */
-	SEG_C|SEG_F,
-
-/*	+#####+
- *	|     #
- *	|     #
- *	|     #
- *	+#####+
- *	|     #
- *	|     #
- *	|     #
- *	+#####+
- */
-	SEG_E|SEG_F,
-
-/*	+-----+
- *	#     #
- *	#     #
- *	#     #
- *	+#####+
- *	|     #
- *	|     #
- *	|     #
- *	+-----+
- */
-	SEG_A|SEG_D|SEG_E,
-
-/*	+#####+
- *	#     |
- *	#     |
- *	#     |
- *	+#####+
- *	|     #
- *	|     #
- *	|     #
- *	+#####+
- */
-	SEG_B|SEG_E,
-
-/*	+#####+
- *	#     |
- *	#     |
- *	#     |
- *	+#####+
- *	#     #
- *	#     #
- *	#     #
- *	+#####+
- */
-	SEG_B,
-
-/*	+#####+
- *	|     #
- *	|     #
- *	|     #
- *	+-----+
- *	|     #
- *	|     #
- *	|     #
- *	+-----+
- */
-	SEG_D|SEG_E|SEG_F,
-
-/*	+#####+
- *	#     #
- *	#     #
- *	#     #
- *	+#####+
- *	#     #
- *	#     #
- *	#     #
- *	+#####+
- */
-	0,
-
-/*	+#####+
- *	#     #
- *	#     #
- *	#     #
- *	+#####+
- *	|     #
- *	|     #
- *	|     #
- *	+-----+
- */
-	SEG_D|SEG_E,
-};
-
-static uint8_t
-iq80321_7seg_xlate(char c)
-{
-	uint8_t rv;
-
-	if (c >= '0' && c <= '9')
-		rv = digitmap[c - '0'];
-	else if (c == '.')
-		rv = (uint8_t) ~SEG_DP;
-	else
-		rv = 0xff;
-
-	return (rv);
-}
-
-void
-iq80321_7seg(char a, char b)
-{
-	uint8_t msb, lsb;
-
-	msb = iq80321_7seg_xlate(a);
-	lsb = iq80321_7seg_xlate(b);
-
-	snakestate = 0;
-
-	WRITE(IQ80321_7SEG_MSB, msb);
-	WRITE(IQ80321_7SEG_LSB, lsb);
-}
-
-static const uint8_t snakemap[][2] = {
-
-/*	+#####+		+#####+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+-----+		+-----+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+-----+		+-----+
- */
-	{ ~SEG_A,	~SEG_A },
-
-/*	+-----+		+-----+
- *	#     |		|     #
- *	#     |		|     #
- *	#     |		|     #
- *	+-----+		+-----+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+-----+		+-----+
- */
-	{ ~SEG_F,	~SEG_B },
-
-/*	+-----+		+-----+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+#####+		+#####+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+-----+		+-----+
- */
-	{ ~SEG_G,	~SEG_G },
-
-/*	+-----+		+-----+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+-----+		+-----+
- *	|     #		#     |
- *	|     #		#     |
- *	|     #		#     |
- *	+-----+		+-----+
- */
-	{ ~SEG_C,	~SEG_E },
-
-/*	+-----+		+-----+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+-----+		+-----+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+#####+		+#####+
- */
-	{ ~SEG_D,	~SEG_D },
-
-/*	+-----+		+-----+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+-----+		+-----+
- *	#     |		|     #
- *	#     |		|     #
- *	#     |		|     #
- *	+-----+		+-----+
- */
-	{ ~SEG_E,	~SEG_C },
-
-/*	+-----+		+-----+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+#####+		+#####+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+-----+		+-----+
- */
-	{ ~SEG_G,	~SEG_G },
-
-/*	+-----+		+-----+
- *	|     #		#     |
- *	|     #		#     |
- *	|     #		#     |
- *	+-----+		+-----+
- *	|     |		|     |
- *	|     |		|     |
- *	|     |		|     |
- *	+-----+		+-----+
- */
-	{ ~SEG_B,	~SEG_F },
-};
-
-static SYSCTL_NODE(_hw, OID_AUTO, sevenseg, CTLFLAG_RD, 0, "7 seg");
-static int freq = 20;
-SYSCTL_INT(_hw_sevenseg, OID_AUTO, freq, CTLFLAG_RW, &freq, 0,
-    "7 Seg update frequency");
-static void
-iq31244_7seg_snake(void)
-{
-	static int snakefreq;
-	int cur = snakestate;
-
-	snakefreq++;
-	if ((snakefreq % freq))
-		return;
-	WRITE(IQ80321_7SEG_MSB, snakemap[cur][0]);
-	WRITE(IQ80321_7SEG_LSB, snakemap[cur][1]);
-
-	snakestate = (cur + 1) & 7;
-}
-
-struct iq31244_7seg_softc {
-	device_t	dev;
-};
-
-static int
-iq31244_7seg_probe(device_t dev)
-{
-
-	device_set_desc(dev, "IQ31244 7seg");
-	return (0);
-}
-
-extern void (*i80321_hardclock_hook)(void);
-static int
-iq31244_7seg_attach(device_t dev)
-{
-
-	i80321_hardclock_hook = iq31244_7seg_snake;
-	return (0);
-}
-
-static device_method_t iq31244_7seg_methods[] = {
-	DEVMETHOD(device_probe, iq31244_7seg_probe),
-	DEVMETHOD(device_attach, iq31244_7seg_attach),
-	{0, 0},
-};
-
-static driver_t iq31244_7seg_driver = {
-	"iqseg",
-	iq31244_7seg_methods,
-	sizeof(struct iq31244_7seg_softc),
-};
-static devclass_t iq31244_7seg_devclass;
-
-DRIVER_MODULE(iqseg, iq, iq31244_7seg_driver, iq31244_7seg_devclass, 0, 0);
diff --git a/sys/arm/xscale/i80321/iq31244_machdep.c b/sys/arm/xscale/i80321/iq31244_machdep.c
deleted file mode 100644
index eb19f78..0000000
--- a/sys/arm/xscale/i80321/iq31244_machdep.c
+++ /dev/null
@@ -1,416 +0,0 @@
-/*	$NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $	*/
-
-/*-
- * Copyright (c) 1994-1998 Mark Brinicombe.
- * Copyright (c) 1994 Brini.
- * All rights reserved.
- *
- * This code is derived from software written for Brini by Mark Brinicombe
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *      This product includes software developed by Brini.
- * 4. The name of the company nor the name of the author may be used to
- *    endorse or promote products derived from this software without specific
- *    prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RiscBSD kernel project
- *
- * machdep.c
- *
- * Machine dependant functions for kernel setup
- *
- * This file needs a lot of work.
- *
- * Created      : 17/09/94
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_kstack_pages.h"
-
-#define _ARM32_BUS_DMA_PRIVATE
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/sysproto.h>
-#include <sys/signalvar.h>
-#include <sys/imgact.h>
-#include <sys/kernel.h>
-#include <sys/ktr.h>
-#include <sys/linker.h>
-#include <sys/lock.h>
-#include <sys/malloc.h>
-#include <sys/mutex.h>
-#include <sys/pcpu.h>
-#include <sys/proc.h>
-#include <sys/ptrace.h>
-#include <sys/cons.h>
-#include <sys/bio.h>
-#include <sys/bus.h>
-#include <sys/buf.h>
-#include <sys/exec.h>
-#include <sys/kdb.h>
-#include <sys/msgbuf.h>
-#include <machine/reg.h>
-#include <machine/cpu.h>
-#include <machine/physmem.h>
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-#include <vm/vm_object.h>
-#include <vm/vm_page.h>
-#include <vm/vm_map.h>
-#include <machine/devmap.h>
-#include <machine/vmparam.h>
-#include <machine/pcb.h>
-#include <machine/undefined.h>
-#include <machine/machdep.h>
-#include <machine/metadata.h>
-#include <machine/armreg.h>
-#include <machine/bus.h>
-#include <sys/reboot.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-#include <arm/xscale/i80321/iq80321reg.h>
-#include <arm/xscale/i80321/obiovar.h>
-
-#define	KERNEL_PT_SYS		0	/* Page table for mapping proc0 zero page */
-#define	KERNEL_PT_IOPXS		1
-#define	KERNEL_PT_BEFOREKERN	2
-#define	KERNEL_PT_AFKERNEL	3	/* L2 table for mapping after kernel */
-#define	KERNEL_PT_AFKERNEL_NUM	9
-
-/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
-#define NUM_KERNEL_PTS		(KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
-
-struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
-
-/* Physical and virtual addresses for some global pages */
-
-struct pv_addr systempage;
-struct pv_addr msgbufpv;
-struct pv_addr irqstack;
-struct pv_addr undstack;
-struct pv_addr abtstack;
-struct pv_addr kernelstack;
-struct pv_addr minidataclean;
-
-#define IQ80321_OBIO_BASE 0xfe800000UL
-#define IQ80321_OBIO_SIZE 0x00100000UL
-/* Static device mappings. */
-static const struct arm_devmap_entry iq80321_devmap[] = {
-	/*
-	 * Map the on-board devices VA == PA so that we can access them
-	 * with the MMU on or off.
-	 */
-	    {
-		    IQ80321_OBIO_BASE,
-		    IQ80321_OBIO_BASE,
-		    IQ80321_OBIO_SIZE,
-		    VM_PROT_READ|VM_PROT_WRITE,
-		    PTE_DEVICE,
-	    },
-	    {
-	    	    IQ80321_IOW_VBASE,
-		    VERDE_OUT_XLATE_IO_WIN0_BASE,
-		    VERDE_OUT_XLATE_IO_WIN_SIZE,
-		    VM_PROT_READ|VM_PROT_WRITE,
-		    PTE_DEVICE,
-	    },
-	
-	    {
-		    IQ80321_80321_VBASE,
-		    VERDE_PMMR_BASE,
-		    VERDE_PMMR_SIZE,
-		    VM_PROT_READ|VM_PROT_WRITE,
-		    PTE_DEVICE,
-	    },
-	    {
-		    0,
-		    0,
-		    0,
-		    0,
-		    0,
-	    }
-};
-
-#define SDRAM_START 0xa0000000
-
-extern vm_offset_t xscale_cache_clean_addr;
-
-void *
-initarm(struct arm_boot_params *abp)
-{
-	struct pv_addr  kernel_l1pt;
-	struct pv_addr  dpcpu;
-	int loop, i;
-	u_int l1pagetable;
-	vm_offset_t freemempos;
-	vm_offset_t freemem_pt;
-	vm_offset_t afterkern;
-	vm_offset_t freemem_after;
-	vm_offset_t lastaddr;
-	uint32_t memsize, memstart;
-
-	lastaddr = parse_boot_param(abp);
-	arm_physmem_kernaddr = abp->abp_physaddr;
-	set_cpufuncs();
-	pcpu_init(pcpup, 0, sizeof(struct pcpu));
-	PCPU_SET(curthread, &thread0);
-
-	/* Do basic tuning, hz etc */
-	init_param1();
-
-	freemempos = 0xa0200000;
-	/* Define a macro to simplify memory allocation */
-#define	valloc_pages(var, np)			\
-	alloc_pages((var).pv_pa, (np));		\
-	(var).pv_va = (var).pv_pa + 0x20000000;
-
-#define alloc_pages(var, np)			\
-	freemempos -= (np * PAGE_SIZE);		\
-	(var) = freemempos;		\
-	memset((char *)(var), 0, ((np) * PAGE_SIZE));
-
-	while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
-		freemempos -= PAGE_SIZE;
-	valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
-	for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
-		if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
-			valloc_pages(kernel_pt_table[loop],
-			    L2_TABLE_SIZE / PAGE_SIZE);
-		} else {
-			kernel_pt_table[loop].pv_pa = freemempos +
-			    (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
-			    L2_TABLE_SIZE_REAL;
-			kernel_pt_table[loop].pv_va =
-			    kernel_pt_table[loop].pv_pa + 0x20000000;
-		}
-	}
-	freemem_pt = freemempos;
-	freemempos = 0xa0100000;
-	/*
-	 * Allocate a page for the system page mapped to V0x00000000
-	 * This page will just contain the system vectors and can be
-	 * shared by all processes.
-	 */
-	valloc_pages(systempage, 1);
-
-	/* Allocate dynamic per-cpu area. */
-	valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
-	dpcpu_init((void *)dpcpu.pv_va, 0);
-
-	/* Allocate stacks for all modes */
-	valloc_pages(irqstack, IRQ_STACK_SIZE);
-	valloc_pages(abtstack, ABT_STACK_SIZE);
-	valloc_pages(undstack, UND_STACK_SIZE);
-	valloc_pages(kernelstack, kstack_pages);
-	alloc_pages(minidataclean.pv_pa, 1);
-	valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
-	/*
-	 * Allocate memory for the l1 and l2 page tables. The scheme to avoid
-	 * wasting memory by allocating the l1pt on the first 16k memory was
-	 * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
-	 * this to work (which is supposed to be the case).
-	 */
-
-	/*
-	 * Now we start construction of the L1 page table
-	 * We start by mapping the L2 page tables into the L1.
-	 * This means that we can replace L1 mappings later on if necessary
-	 */
-	l1pagetable = kernel_l1pt.pv_va;
-
-	/* Map the L2 pages tables in the L1 page table */
-	pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
-	    &kernel_pt_table[KERNEL_PT_SYS]);
-	pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
-	    &kernel_pt_table[KERNEL_PT_IOPXS]);
-	pmap_link_l2pt(l1pagetable, KERNBASE,
-	    &kernel_pt_table[KERNEL_PT_BEFOREKERN]);
-	pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000,
-	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-	pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000,
-	    0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
-	pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000,
-	    (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
-	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-	freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
-	afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
-	    - 1));
-	for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
-		pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
-		    &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
-	}
-	pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
-	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-	
-
-	/* Map the Mini-Data cache clean area. */
-	xscale_setup_minidata(l1pagetable, afterkern,
-	    minidataclean.pv_pa);
-
-	/* Map the vector page. */
-	pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
-	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
-	arm_devmap_bootstrap(l1pagetable, iq80321_devmap);
-	/*
-	 * Give the XScale global cache clean code an appropriately
-	 * sized chunk of unmapped VA space starting at 0xff000000
-	 * (our device mappings end before this address).
-	 */
-	xscale_cache_clean_addr = 0xff000000U;
-
-	cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
-	setttb(kernel_l1pt.pv_pa);
-	cpu_tlb_flushID();
-	cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
-	/*
-	 * Pages were allocated during the secondary bootstrap for the
-	 * stacks for different CPU modes.
-	 * We must now set the r13 registers in the different CPU modes to
-	 * point to these stacks.
-	 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
-	 * of the stack memory.
-	 */
-	set_stackptrs(0);
-
-	/*
-	 * We must now clean the cache again....
-	 * Cleaning may be done by reading new data to displace any
-	 * dirty data in the cache. This will have happened in setttb()
-	 * but since we are boot strapping the addresses used for the read
-	 * may have just been remapped and thus the cache could be out
-	 * of sync. A re-clean after the switch will cure this.
-	 * After booting there are no gross relocations of the kernel thus
-	 * this problem will not occur after initarm().
-	 */
-	cpu_idcache_wbinv_all();
-	cpu_setup();
-
-	/*
-	 * Fetch the SDRAM start/size from the i80321 SDRAM configration
-	 * registers.
-	 */
-	i80321_calibrate_delay();
-	i80321_sdram_bounds(obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE,
-	    &memstart, &memsize);
-	physmem = memsize / PAGE_SIZE;
-	cninit();
-
-	undefined_init();
-				
-	init_proc0(kernelstack.pv_va);
-	
-	/* Enable MMU, I-cache, D-cache, write buffer. */
-
-	arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
-	pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
-	vm_max_kernel_address = 0xe0000000;
-	pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt);
-	msgbufp = (void*)msgbufpv.pv_va;
-	msgbufinit(msgbufp, msgbufsize);
-	mutex_init();
-	
-	/*
-	 * Add the physical ram we have available.
-	 *
-	 * Exclude the kernel (and all the things we allocated which immediately
-	 * follow the kernel) from the VM allocation pool but not from crash
-	 * dumps.  virtual_avail is a global variable which tracks the kva we've
-	 * "allocated" while setting up pmaps.
-	 *
-	 * Prepare the list of physical memory available to the vm subsystem.
-	 */
-	arm_physmem_hardware_region(SDRAM_START, memsize);
-	arm_physmem_exclude_region(freemem_pt, abp->abp_physaddr -
-	    freemem_pt, EXFLAG_NOALLOC);
-	arm_physmem_exclude_region(freemempos, abp->abp_physaddr - 0x100000 -
-	    freemempos, EXFLAG_NOALLOC);			
-	arm_physmem_exclude_region(abp->abp_physaddr, 
-	    virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
-	arm_physmem_init_kernel_globals();
-
-	init_param2(physmem);
-	kdb_init();
-	return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
-	    sizeof(struct pcb)));
-}
-
-extern int
-machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin)
-{
-	int bus;
-	int device;
-	int func;
-	uint32_t busno;
-	struct i80321_pci_softc *sc = device_get_softc(pcib);
-	bus = pci_get_bus(dev);
-	device = pci_get_slot(dev);
-	func = pci_get_function(dev);
-	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
-	busno = PCIXSR_BUSNO(busno);
-	if (busno == 0xff)
-		busno = 0;
-	if (bus != busno)
-		goto no_mapping;
-	switch (device) {
-		/* IQ31244 PCI */
-	case 1: /* PCIX-PCIX bridge */
-		/*
-		 * The S-ATA chips are behind the bridge, and all of
-		 * the S-ATA interrupts are wired together.
-		 */
-		return (ICU_INT_XINT(2));
-	case 2: /* PCI slot */
-		/* All pins are wired together. */
-		return (ICU_INT_XINT(3));
-	case 3: /* i82546 dual Gig-E */
-		if (pin == 1 || pin == 2)
-			return (ICU_INT_XINT(0));
-		goto no_mapping;
-		/* IQ80321 PCI */
-	case 4: /* i82544 Gig-E */
-	case 8: /*
-		 * Apparently you can set the device for the ethernet adapter
-		 * to 8 with a jumper, so handle that as well
-		 */
-		if (pin == 1)
-			return (ICU_INT_XINT(0));
-		goto no_mapping;
-	case 6: /* S-PCI-X slot */
-		if (pin == 1)
-			return (ICU_INT_XINT(2));
-		if (pin == 2)
-			return (ICU_INT_XINT(3));
-		goto no_mapping;
-	default:
-no_mapping:
-		printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
-		
-	}
-	return (0);
-
-}
diff --git a/sys/arm/xscale/i80321/iq80321.c b/sys/arm/xscale/i80321/iq80321.c
deleted file mode 100644
index fb34455..0000000
--- a/sys/arm/xscale/i80321/iq80321.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*	$NetBSD: i80321_mainbus.c,v 1.13 2003/12/17 22:03:24 abs Exp $	*/
-
-/*-
- * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * IQ80321 front-end for the i80321 I/O Processor.  We take care
- * of setting up the i80321 memory map, PCI interrupt routing, etc.,
- * which are all specific to the board the i80321 is wired up to.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#define _ARM32_BUS_DMA_PRIVATE
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/malloc.h>
-#include <sys/rman.h>
-#include <machine/armreg.h>
-#include <machine/bus.h>
-#include <machine/intr.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-#include <arm/xscale/i80321/i80321var.h>
-#include <arm/xscale/i80321/iq80321reg.h>
-#include <arm/xscale/i80321/iq80321var.h>
-#include <arm/xscale/i80321/i80321_intr.h>
-
-#include <dev/pci/pcireg.h>
-
-
-int	iq80321_probe(device_t);
-void	iq80321_identify(driver_t *, device_t);
-int	iq80321_attach(device_t);
-
-int
-iq80321_probe(device_t dev)
-{
-	device_set_desc(dev, "Intel 80321");
-	return (BUS_PROBE_NOWILDCARD);
-}
-
-void
-iq80321_identify(driver_t *driver, device_t parent)
-{
-	
-	BUS_ADD_CHILD(parent, 0, "iq", 0);
-}
-
-static struct arm32_dma_range i80321_dr;
-static int dma_range_init = 0;
-
-struct arm32_dma_range *
-bus_dma_get_range(void)
-{
-	if (dma_range_init == 0)
-		return (NULL);
-	return (&i80321_dr);
-}
-
-int
-bus_dma_get_range_nb(void)
-{
-	if (dma_range_init == 0)
-		return (0);
-	return (1);
-}
-
-#define PCI_MAPREG_MEM_PREFETCHABLE_MASK	0x00000008
-#define PCI_MAPREG_MEM_TYPE_64BIT		0x00000004
-
-int
-iq80321_attach(device_t dev)
-{
-	struct i80321_softc *sc = device_get_softc(dev);
-	int b0u, b0l, b1u, b1l;
-	vm_paddr_t memstart = 0;
-	vm_size_t memsize = 0;
-	int busno;
-
-	/*
-	 * Fill in the space tag for the i80321's own devices,
-	 * and hand-craft the space handle for it (the device
-	 * was mapped during early bootstrap).
-	 */
-	i80321_bs_init(&i80321_bs_tag, sc);
-	sc->sc_st = &i80321_bs_tag;
-	sc->sc_sh = IQ80321_80321_VBASE;
-	sc->dev = dev;
-	sc->sc_is_host = 1;
-
-	/*
-	 * Slice off a subregion for the Memory Controller -- we need it
-	 * here in order read the memory size.
-	 */
-	if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE,
-	    VERDE_MCU_SIZE, &sc->sc_mcu_sh))
-		panic("%s: unable to subregion MCU registers",
-		    device_get_name(dev));
-
-	if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE,
-	    VERDE_ATU_SIZE, &sc->sc_atu_sh))
-		panic("%s: unable to subregion ATU registers",
-		    device_get_name(dev));
-
-	/*
-	 * We have mapped the PCI I/O windows in the early
-	 * bootstrap phase.
-	 */
-	sc->sc_iow_vaddr = IQ80321_IOW_VBASE;
-
-	/*
-	 * Check the configuration of the ATU to see if another BIOS
-	 * has configured us.  If a PC BIOS didn't configure us, then:
-	 * 	IQ80321: BAR0 00000000.0000000c BAR1 is 00000000.8000000c.
-	 * 	IQ31244: BAR0 00000000.00000004 BAR1 is 00000000.0000000c.
-	 * If a BIOS has configured us, at least one of those should be
-	 * different.  This is pretty fragile, but it's not clear what
-	 * would work better.
-	 */
-	b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x0);
-	b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x4);
-	b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x8);
-	b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0xc);
-
-#ifdef VERBOSE_INIT_ARM	
-	printf("i80321: BAR0 = %08x.%08x BAR1 = %08x.%08x\n",
-		   b0l,b0u, b1l, b1u );
-#endif
-
-#define PCI_MAPREG_MEM_ADDR_MASK	0xfffffff0
-	b0l &= PCI_MAPREG_MEM_ADDR_MASK;
-	b0u &= PCI_MAPREG_MEM_ADDR_MASK;
-	b1l &= PCI_MAPREG_MEM_ADDR_MASK;
-	b1u &= PCI_MAPREG_MEM_ADDR_MASK;
-
-#ifdef VERBOSE_INIT_ARM	
-	printf("i80219: BAR0 = %08x.%08x BAR1 = %08x.%08x\n",
-		   b0l,b0u, b1l, b1u );
-#endif
-
-	if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0))
-		sc->sc_is_host = 0;
-	else
-		sc->sc_is_host = 1;
-
-	/* FIXME: i force it's */	
-
-#ifdef CPU_XSCALE_80219
-	sc->sc_is_host = 1;
-#endif
-	
-	i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
-	/*
-	 * We set up the Inbound Windows as follows:
-	 *
-	 *	0	Access to i80321 PMMRs
-	 *
-	 *	1	Reserve space for private devices
-	 *
-	 *	2	RAM access
-	 *
-	 *	3	Unused.
-	 *
-	 * This chunk needs to be customized for each IOP321 application.
-	 */
-#if 0
-	sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE;
-	sc->sc_iwin[0].iwin_base_hi = 0;
-	sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE;
-	sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE;
-#endif
-	if (sc->sc_is_host) {
-		
-		/* Map PCI:Local 1:1. */
-		sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
-		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
-		    PCI_MAPREG_MEM_TYPE_64BIT;
-		sc->sc_iwin[1].iwin_base_hi = 0;
-	} else {
-		
-		sc->sc_iwin[1].iwin_base_lo = 0;
-		sc->sc_iwin[1].iwin_base_hi = 0;
-	}
-	sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
-	sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
-	
-	if (sc->sc_is_host) {
-		sc->sc_iwin[2].iwin_base_lo = memstart |
-		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
-		    PCI_MAPREG_MEM_TYPE_64BIT;
-		sc->sc_iwin[2].iwin_base_hi = 0;
-	} else {
-		sc->sc_iwin[2].iwin_base_lo = 0;
-		sc->sc_iwin[2].iwin_base_hi = 0;
-	}
-	sc->sc_iwin[2].iwin_xlate = memstart;
-	sc->sc_iwin[2].iwin_size = memsize;
-
-	if (sc->sc_is_host) {
-		sc->sc_iwin[3].iwin_base_lo = 0 |
-		    PCI_MAPREG_MEM_PREFETCHABLE_MASK |
-		    PCI_MAPREG_MEM_TYPE_64BIT;
-	} else {
-		sc->sc_iwin[3].iwin_base_lo = 0;
-	}
-	sc->sc_iwin[3].iwin_base_hi = 0;
-	sc->sc_iwin[3].iwin_xlate = 0;
-	sc->sc_iwin[3].iwin_size = 0;
-	
-#ifdef 	VERBOSE_INIT_ARM
-	printf("i80321: Reserve space for private devices (Inbound Window 1) \n hi:0x%08x lo:0x%08x xlate:0x%08x size:0x%08x\n",
-		   sc->sc_iwin[1].iwin_base_hi,
-		   sc->sc_iwin[1].iwin_base_lo,
-		   sc->sc_iwin[1].iwin_xlate,
-		   sc->sc_iwin[1].iwin_size
-		);
-	printf("i80321: RAM access (Inbound Window 2) \n hi:0x%08x lo:0x%08x xlate:0x%08x size:0x%08x\n",
-		   sc->sc_iwin[2].iwin_base_hi,
-		   sc->sc_iwin[2].iwin_base_lo,
-		   sc->sc_iwin[2].iwin_xlate,
-		   sc->sc_iwin[2].iwin_size
-		);
-#endif
-
-	/*
-	 * We set up the Outbound Windows as follows:
-	 *
-	 *	0	Access to private PCI space.
-	 *
-	 *	1	Unused.
-	 */
-#define PCI_MAPREG_MEM_ADDR(x) ((x) & 0xfffffff0)
-	sc->sc_owin[0].owin_xlate_lo =
-    	    PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
-	sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
-	/*
-	 * Set the Secondary Outbound I/O window to map
-	 * to PCI address 0 for all 64K of the I/O space.
-	 */
-	sc->sc_ioout_xlate = 0;
-	i80321_attach(sc);
-	i80321_dr.dr_sysbase = sc->sc_iwin[2].iwin_xlate;
-	i80321_dr.dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
-	i80321_dr.dr_len = sc->sc_iwin[2].iwin_size;
-	dma_range_init = 1;
-	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
-	busno = PCIXSR_BUSNO(busno);
-	if (busno == 0xff)
-		busno = 0;
-	sc->sc_irq_rman.rm_type = RMAN_ARRAY;
-	sc->sc_irq_rman.rm_descr = "i80321 IRQs";
-	if (rman_init(&sc->sc_irq_rman) != 0 ||
-	    rman_manage_region(&sc->sc_irq_rman, 0, 25) != 0)
-		panic("i80321_attach: failed to set up IRQ rman");
-
-	device_add_child(dev, "obio", 0);
-	device_add_child(dev, "itimer", 0);
-	device_add_child(dev, "iopwdog", 0);
-#ifndef 	CPU_XSCALE_80219
-	device_add_child(dev, "iqseg", 0);
-#endif	
-	device_add_child(dev, "pcib", busno);
-	device_add_child(dev, "i80321_dma", 0);
-	device_add_child(dev, "i80321_dma", 1);
-#ifndef CPU_XSCALE_80219	
-	device_add_child(dev, "i80321_aau", 0);
-#endif
-	bus_generic_probe(dev);
-	bus_generic_attach(dev);
-
-	return (0);
-}
-
-void
-arm_mask_irq(uintptr_t nb)
-{
-	intr_enabled &= ~(1 << nb);
-	i80321_set_intrmask();
-}
-
-void
-arm_unmask_irq(uintptr_t nb)
-{
-	intr_enabled |= (1 << nb);
-	i80321_set_intrmask();
-}
-
-
-void
-cpu_reset()
-{
-	(void) disable_interrupts(PSR_I|PSR_F);
-	*(__volatile uint32_t *)(IQ80321_80321_VBASE + VERDE_ATU_BASE +
-	    ATU_PCSR) = PCSR_RIB | PCSR_RPB;
-	printf("Reset failed!\n");
-	for(;;);
-}
-
-static struct resource *
-iq80321_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
-{
-	struct i80321_softc *sc = device_get_softc(dev);
-	struct resource *rv;
-
-	if (type == SYS_RES_IRQ) {
-		rv = rman_reserve_resource(&sc->sc_irq_rman,
-		    start, end, count, flags, child);
-		if (rv != NULL)
-			rman_set_rid(rv, *rid);
-		return (rv);
-	}
-	return (NULL);
-}
-
-static int
-iq80321_setup_intr(device_t dev, device_t child,
-    struct resource *ires, int flags, driver_filter_t *filt,
-    driver_intr_t *intr, void *arg, void **cookiep)
-{
-	int error;
-
-	error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
-	    filt, intr, arg, cookiep);
-	if (error)
-		return (error);
-	intr_enabled |= 1 << rman_get_start(ires);
-	i80321_set_intrmask();
-	
-	return (0);
-}
-
-static int
-iq80321_teardown_intr(device_t dev, device_t child, struct resource *res,
-    void *cookie)
-{
-	return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
-}
-
-static device_method_t iq80321_methods[] = {
-	DEVMETHOD(device_probe, iq80321_probe),
-	DEVMETHOD(device_attach, iq80321_attach),
-	DEVMETHOD(device_identify, iq80321_identify),
-	DEVMETHOD(bus_alloc_resource, iq80321_alloc_resource),
-	DEVMETHOD(bus_setup_intr, iq80321_setup_intr),
-	DEVMETHOD(bus_teardown_intr, iq80321_teardown_intr),
-	{0, 0},
-};
-
-static driver_t iq80321_driver = {
-	"iq",
-	iq80321_methods,
-	sizeof(struct i80321_softc),
-};
-static devclass_t iq80321_devclass;
-
-DRIVER_MODULE(iq, nexus, iq80321_driver, iq80321_devclass, 0, 0);
diff --git a/sys/arm/xscale/i80321/iq80321reg.h b/sys/arm/xscale/i80321/iq80321reg.h
deleted file mode 100644
index d887fcd..0000000
--- a/sys/arm/xscale/i80321/iq80321reg.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*	$NetBSD: iq80321reg.h,v 1.4 2003/05/14 19:46:39 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- *
- */
-
-#ifndef _IQ80321REG_H_
-#define	_IQ80321REG_H_
-
-/*
- * Memory map and register definitions for the Intel IQ80321
- * Evaluation Board.
- */
-
-/*
- * The memory map of the IQ80321 looks like so:
- *
- *           ------------------------------
- *		Intel 80321 IOP Reserved
- * FFFF E900 ------------------------------
- *		Peripheral Memory Mapped
- *		    Registers
- * FFFF E000 ------------------------------
- *		On-board devices
- * FE80 0000 ------------------------------
- *		SDRAM
- * A000 0000 ------------------------------
- *		Reserved
- * 9100 0000 ------------------------------
- * 		Flash
- * 9080 0000 ------------------------------
- *		Reserved
- * 9002 0000 ------------------------------
- *		ATU Outbound Transaction
- *		    Windows
- * 8000 0000 ------------------------------
- *		ATU Outbound Direct
- *		    Addressing Windows
- * 0000 1000 ------------------------------
- *		Initialization Boot Code
- *		    from Flash
- * 0000 0000 ------------------------------
- */
-
-/*
- * We allocate a page table for VA 0xfe400000 (4MB) and map the
- * PCI I/O space (64K) and i80321 memory-mapped registers (4K) there.
- */
-#define	IQ80321_IOPXS_VBASE	0xfe400000UL
-#define	IQ80321_IOW_VBASE	IQ80321_IOPXS_VBASE
-#define	IQ80321_80321_VBASE	(IQ80321_IOW_VBASE +			\
-				 VERDE_OUT_XLATE_IO_WIN_SIZE)
-
-#define	IQ80321_SDRAM_START	0xa0000000
-/*
- * The IQ80321 on-board devices are mapped VA==PA during bootstrap.
- * Conveniently, the size of the on-board register space is 1 section
- * mapping.
- */
-#define	IQ80321_OBIO_BASE	0xfe800000UL
-#define	IQ80321_OBIO_SIZE	0x00100000UL	/* 1MB */
-
-#define	IQ80321_UART1		0xfe800000UL	/* TI 16550 */
-
-#if defined( CPU_XSCALE_80321 )
-#define	IQ80321_7SEG_MSB	0xfe840000UL
-#define	IQ80321_7SEG_LSB	0xfe850000UL
-
-#define	IQ80321_ROT_SWITCH	0xfe8d0000UL
-
-#define	IQ80321_BATTERY_STAT	0xfe8f0000UL
-#define	BATTERY_STAT_PRES	(1U << 0)
-#define	BATTERY_STAT_CHRG	(1U << 1)
-#define	BATTERY_STAT_DISCHRG	(1U << 2)
-#endif /* CPU_XSCALE_80321 */
-
-#endif /* _IQ80321REG_H_ */
diff --git a/sys/arm/xscale/i80321/iq80321var.h b/sys/arm/xscale/i80321/iq80321var.h
deleted file mode 100644
index 4a03500..0000000
--- a/sys/arm/xscale/i80321/iq80321var.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*	$NetBSD: iq80321var.h,v 1.1 2002/03/27 21:51:30 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2002 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- *
- */
-
-#ifndef _IQ80321_IQ80321VAR_H_
-#define	_IQ80321_IQ80321VAR_H_
-
-#include <dev/pci/pcivar.h>
-
-void	iq80321_7seg(char, char);
-void	iq80321_7seg_snake(void);
-
-#if 0
-void	iq80321_pci_init(pci_chipset_tag_t, void *);
-#endif
-
-#endif /* _IQ80321_IQ80321VAR_H_ */
diff --git a/sys/arm/xscale/i80321/obio.c b/sys/arm/xscale/i80321/obio.c
deleted file mode 100644
index 55218cc..0000000
--- a/sys/arm/xscale/i80321/obio.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*	$NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $	*/
-
-/*-
- * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * On-board device autoconfiguration support for Intel IQ80321
- * evaluation boards.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/rman.h>
-#include <sys/malloc.h>
-
-#include <machine/bus.h>
-
-#include <arm/xscale/i80321/i80321reg.h>
-
-#include <arm/xscale/i80321/iq80321reg.h>
-#include <arm/xscale/i80321/obiovar.h>
-
-bus_space_tag_t obio_bs_tag;
-
-int	obio_probe(device_t);
-int	obio_attach(device_t);
-
-int
-obio_probe(device_t dev)
-{
-	return (0);
-}
-
-int
-obio_attach(device_t dev)
-{
-	struct obio_softc *sc = device_get_softc(dev);
-
-	obio_bs_tag = arm_base_bs_tag;
-        sc->oba_st = obio_bs_tag;
-	sc->oba_addr = IQ80321_OBIO_BASE;
-	sc->oba_size = IQ80321_OBIO_SIZE;
-	sc->oba_rman.rm_type = RMAN_ARRAY;
-	sc->oba_rman.rm_descr = "OBIO I/O";
-	if (rman_init(&sc->oba_rman) != 0 ||
-	    rman_manage_region(&sc->oba_rman,
-	    sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
-		panic("obio_attach: failed to set up I/O rman");
-	sc->oba_irq_rman.rm_type = RMAN_ARRAY;
-	sc->oba_irq_rman.rm_descr = "OBIO IRQ";
-	if (rman_init(&sc->oba_irq_rman) != 0 ||
-	    rman_manage_region(&sc->oba_irq_rman, 28, 28) != 0)
-		panic("obio_attach: failed to set up IRQ rman");
-	device_add_child(dev, "uart", 0);
-	bus_generic_probe(dev);
-	bus_generic_attach(dev);
-	return (0);
-}
-
-static struct resource *
-obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
-{
-	struct resource *rv;
-	struct rman *rm;
-	bus_space_tag_t bt = NULL;
-	bus_space_handle_t bh = 0;
-	struct obio_softc *sc = device_get_softc(bus);
-
-	switch (type) {
-	case SYS_RES_IRQ:
-		rm = &sc->oba_irq_rman;
-		break;
-	case SYS_RES_MEMORY:
-		return (NULL);
-	case SYS_RES_IOPORT:
-		rm = &sc->oba_rman;
-		bt = sc->oba_st;
-		bh = sc->oba_addr;
-		start = bh;
-		break;
-	default:
-		return (NULL);
-	}
-
-
-	rv = rman_reserve_resource(rm, start, end, count, flags, child);
-	if (rv == NULL)
-		return (NULL);
-	if (type == SYS_RES_IRQ)
-		return (rv);
-	rman_set_rid(rv, *rid);
-	rman_set_bustag(rv, bt);
-	rman_set_bushandle(rv, bh);
-	
-	return (rv);
-
-}
-
-static int
-obio_activate_resource(device_t bus, device_t child, int type, int rid,
-    struct resource *r)
-{
-	return (0);
-}
-static device_method_t obio_methods[] = {
-	DEVMETHOD(device_probe, obio_probe),
-	DEVMETHOD(device_attach, obio_attach),
-
-	DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
-	DEVMETHOD(bus_activate_resource, obio_activate_resource),
-	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
-	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
-
-	{0, 0},
-};
-
-static driver_t obio_driver = {
-	"obio",
-	obio_methods,
-	sizeof(struct obio_softc),
-};
-static devclass_t obio_devclass;
-
-DRIVER_MODULE(obio, iq, obio_driver, obio_devclass, 0, 0);
diff --git a/sys/arm/xscale/i80321/obiovar.h b/sys/arm/xscale/i80321/obiovar.h
deleted file mode 100644
index 182b52f..0000000
--- a/sys/arm/xscale/i80321/obiovar.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*	$NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $	*/
-
-/*-
- * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
- * All rights reserved.
- *
- * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed for the NetBSD Project by
- *	Wasabi Systems, Inc.
- * 4. The name of Wasabi Systems, Inc. may not be used to endorse
- *    or promote products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- *
- */
-
-#ifndef _IQ80321_OBIOVAR_H_
-#define	_IQ80321_OBIOVAR_H_
-
-#include <sys/rman.h>
-
-struct obio_softc {
-	bus_space_tag_t oba_st;		/* bus space tag */
-	bus_addr_t oba_addr;		/* address of device */
-	bus_size_t oba_size;		/* size of device */
-	int oba_width;			/* bus width */
-	int oba_irq;			/* XINT interrupt bit # */
-	struct rman oba_rman;
-	struct rman oba_irq_rman;
-	
-};
-extern bus_space_tag_t obio_bs_tag;
-
-#endif /* _IQ80321_OBIOVAR_H_ */
diff --git a/sys/arm/xscale/i80321/std.ep80219 b/sys/arm/xscale/i80321/std.ep80219
deleted file mode 100644
index 9f5cbb7..0000000
--- a/sys/arm/xscale/i80321/std.ep80219
+++ /dev/null
@@ -1,7 +0,0 @@
-#EP80219 board configuration
-#$FreeBSD$
-include	"../xscale/i80321/std.i80219"
-files		"../xscale/i80321/files.ep80219"
-makeoptions	KERNPHYSADDR=0xa0200000
-makeoptions	KERNVIRTADDR=0xc0200000
-options	COUNTS_PER_SEC=198000000
diff --git a/sys/arm/xscale/i80321/std.i80219 b/sys/arm/xscale/i80321/std.i80219
deleted file mode 100644
index 7cc8f37..0000000
--- a/sys/arm/xscale/i80321/std.i80219
+++ /dev/null
@@ -1,5 +0,0 @@
-#XScale i80219 generic configuration
-#$FreeBSD$
-files		"../xscale/i80321/files.i80219"
-include		"../xscale/std.xscale-be"
-cpu 		CPU_XSCALE_80219
diff --git a/sys/arm/xscale/i80321/std.i80321 b/sys/arm/xscale/i80321/std.i80321
deleted file mode 100644
index 8142bdf..0000000
--- a/sys/arm/xscale/i80321/std.i80321
+++ /dev/null
@@ -1,5 +0,0 @@
-#XScale i80321 generic configuration
-#$FreeBSD$
-files		"../xscale/i80321/files.i80321"
-include		"../xscale/std.xscale-be"
-cpu 		CPU_XSCALE_80321
diff --git a/sys/arm/xscale/i80321/std.iq31244 b/sys/arm/xscale/i80321/std.iq31244
deleted file mode 100644
index c4c23bf..0000000
--- a/sys/arm/xscale/i80321/std.iq31244
+++ /dev/null
@@ -1,7 +0,0 @@
-#IQ31244 board configuration
-#$FreeBSD$
-include		"../xscale/i80321/std.i80321"
-files		"../xscale/i80321/files.iq31244"
-makeoptions	KERNPHYSADDR=0xa0200000
-makeoptions	KERNVIRTADDR=0xc0200000
-options		COUNTS_PER_SEC=198000000
diff --git a/sys/arm/xscale/i80321/uart_bus_i80321.c b/sys/arm/xscale/i80321/uart_bus_i80321.c
deleted file mode 100644
index 5bb903d..0000000
--- a/sys/arm/xscale/i80321/uart_bus_i80321.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*-
- * Copyright (c) 2004 Olivier Houchard.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/conf.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <machine/resource.h>
-
-#include <dev/pci/pcivar.h>
-
-#include <dev/uart/uart.h>
-#include <dev/uart/uart_bus.h>
-#include <dev/uart/uart_cpu.h>
-
-#include "uart_if.h"
-
-static int uart_i80321_probe(device_t dev);
-
-static device_method_t uart_i80321_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		uart_i80321_probe),
-	DEVMETHOD(device_attach,	uart_bus_attach),
-	DEVMETHOD(device_detach,	uart_bus_detach),
-	{ 0, 0 }
-};
-
-static driver_t uart_i80321_driver = {
-	uart_driver_name,
-	uart_i80321_methods,
-	sizeof(struct uart_softc),
-};
-
-extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
-static int
-uart_i80321_probe(device_t dev)
-{
-	struct uart_softc *sc;
-
-	sc = device_get_softc(dev);
-	sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
-	sc->sc_class = &uart_ns8250_class;
-	bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
-	return(uart_bus_probe(dev, 0, 0, 0, 0));
-}
-
-
-DRIVER_MODULE(uart, obio, uart_i80321_driver, uart_devclass, 0, 0);
diff --git a/sys/arm/xscale/i80321/uart_cpu_i80321.c b/sys/arm/xscale/i80321/uart_cpu_i80321.c
deleted file mode 100644
index a3faec7..0000000
--- a/sys/arm/xscale/i80321/uart_cpu_i80321.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*-
- * Copyright (c) 2003 Marcel Moolenaar
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/cons.h>
-#include <machine/bus.h>
-
-#include <dev/uart/uart.h>
-#include <dev/uart/uart_cpu.h>
-
-#include <arm/xscale/i80321/i80321var.h>
-#include <arm/xscale/i80321/obiovar.h>
-
-bus_space_tag_t uart_bus_space_io;
-bus_space_tag_t uart_bus_space_mem;
-
-int
-uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
-{
-	return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
-}
-
-int
-uart_cpu_getdev(int devtype, struct uart_devinfo *di)
-{
-	di->ops = uart_getops(&uart_ns8250_class);
-	di->bas.chan = 0;
-	di->bas.bst = obio_bs_tag;
-	di->bas.regshft = 0;
-	di->bas.rclk = 0;
-	di->baudrate = 115200;
-	di->databits = 8;
-	di->stopbits = 1;
-	di->parity = UART_PARITY_NONE;
-	uart_bus_space_io = obio_bs_tag;
-	uart_bus_space_mem = NULL;
-	di->bas.bsh = 0xfe800000;
-	return (0);
-}
diff --git a/sys/arm/xscale/i8134x/i80321reg.h b/sys/arm/xscale/i8134x/i80321reg.h
index 53617f9..115900c 100644
--- a/sys/arm/xscale/i8134x/i80321reg.h
+++ b/sys/arm/xscale/i8134x/i80321reg.h
@@ -91,19 +91,9 @@
 #define	VERDE_MCU_BASE			0x0500
 #define	VERDE_MCU_SIZE			0x0100
 
-#if defined(CPU_XSCALE_80321)
-#define	VERDE_SSP_BASE			0x0600
-#define	VERDE_SSP_SIZE			0x0080
-#endif
-
 #define	VERDE_PBIU_BASE			0x0680
 #define	VERDE_PBIU_SIZE			0x0080
 
-#if defined(CPU_XSCALE_80321)
-#define	VERDE_AAU_BASE			0x0800
-#define	VERDE_AAU_SIZE			0x0100
-#endif
-
 #define	VERDE_I2C_BASE			0x1680
 #define	VERDE_I2C_BASE0			(VERDE_I2C_BASE + 0x00)
 #define	VERDE_I2C_BASE1			(VERDE_I2C_BASE + 0x20)
@@ -340,21 +330,13 @@
 #define	ICU_INT_XINT(x)		((x) + ICU_INT_XINT0)
 #define	ICU_INT_bit26		26
 
-#if defined (CPU_XSCALE_80219)
-#define	ICU_INT_bit25		25	/* reserved */
-#else
 /* CPU_XSCALE_80321 */
-#define	ICU_INT_SSP		25	/* SSP serial port */
-#endif
+//#define	ICU_INT_SSP		25	/* SSP serial port */
 
 #define	ICU_INT_MUE		24	/* msg unit error */
 
-#if defined (CPU_XSCALE_80219)
-#define	ICU_INT_bit23		23	/* reserved */
-#else
 /* CPU_XSCALE_80321 */
-#define	ICU_INT_AAUE		23	/* AAU error */
-#endif
+//#define	ICU_INT_AAUE		23	/* AAU error */
 
 #define	ICU_INT_bit22		22
 #define	ICU_INT_DMA1E		21	/* DMA Ch 1 error */
@@ -372,14 +354,9 @@
 #define	ICU_INT_TMR0		9	/* timer 0 */
 #define	ICU_INT_CPPM		8	/* core processor PMU */
 
-#if defined(CPU_XSCALE_80219)
-#define	ICU_INT_bit7		7 /* reserved */
-#define	ICU_INT_bit6		6 /* reserved */
-#else
 /* CPU_XSCALE_80321 */
-#define	ICU_INT_AAU_EOC		7	/* AAU end-of-chain */
-#define	ICU_INT_AAU_EOT		6	/* AAU end-of-transfer */
-#endif
+//#define	ICU_INT_AAU_EOC		7	/* AAU end-of-chain */
+//#define	ICU_INT_AAU_EOT		6	/* AAU end-of-transfer */
 
 #define	ICU_INT_bit5		5
 #define	ICU_INT_bit4		4
@@ -388,81 +365,12 @@
 #define	ICU_INT_DMA0_EOC	1	/* DMA0 end-of-chain */
 #define	ICU_INT_DMA0_EOT	0	/* DMA0 end-of-transfer */
 
-#if defined (CPU_XSCALE_80219)
-#define	ICU_INT_HWMASK		(0xffffffff &	 \
-							 ~((1 << ICU_INT_bit26) |	\
-							   (1 << ICU_INT_bit25) |	\
-							   (1 << ICU_INT_bit23) |	\
-							   (1 << ICU_INT_bit22) |	\
-							   (1 << ICU_INT_bit7)  |	\
-							   (1 << ICU_INT_bit6)  |	\
-							   (1 << ICU_INT_bit5)  |	\
-							   (1 << ICU_INT_bit4)))
-
-#else
 /* CPU_XSCALE_80321 */
-#define	ICU_INT_HWMASK		(0xffffffff & \
-					~((1 << ICU_INT_bit26) | \
-					  (1 << ICU_INT_bit22) | \
-					  (1 << ICU_INT_bit5)  | \
-					  (1 << ICU_INT_bit4)))
-#endif
-
-/*
- * SSP Serial Port
- */
-#if defined (CPU_XSCALE_80321)
-
-#define	SSP_SSCR0	0x00		/* SSC control 0 */
-#define	SSP_SSCR1	0x04		/* SSC control 1 */
-#define	SSP_SSSR	0x08		/* SSP status */
-#define	SSP_SSITR	0x0c		/* SSP interrupt test */
-#define	SSP_SSDR	0x10		/* SSP data */
-
-#define	SSP_SSCR0_DSIZE(x)	((x) - 1)/* data size: 4..16 */
-#define	SSP_SSCR0_FRF_SPI	(0 << 4) /* Motorola Serial Periph Iface */
-#define	SSP_SSCR0_FRF_SSP	(1U << 4)/* TI Sync. Serial Protocol */
-#define	SSP_SSCR0_FRF_UWIRE	(2U << 4)/* NatSemi Microwire */
-#define	SSP_SSCR0_FRF_rsvd	(3U << 4)/* reserved */
-#define	SSP_SSCR0_ECS		(1U << 6)/* external clock select */
-#define	SSP_SSCR0_SSE		(1U << 7)/* sync. serial port enable */
-#define	SSP_SSCR0_SCR(x)	((x) << 8)/* serial clock rate */
-					  /* bit rate = 3.6864 * 10e6 /
-					        (2 * (SCR + 1)) */
-
-#define	SSP_SSCR1_RIE		(1U << 0)/* Rx FIFO interrupt enable */
-#define	SSP_SSCR1_TIE		(1U << 1)/* Tx FIFO interrupt enable */
-#define	SSP_SSCR1_LBM		(1U << 2)/* loopback mode enable */
-#define	SSP_SSCR1_SPO		(1U << 3)/* Moto SPI SSCLK pol. (1 = high) */
-#define	SSP_SSCR1_SPH		(1U << 4)/* Moto SPI SSCLK phase:
-					    0 = inactive full at start,
-						1/2 at end of frame
-					    1 = inactive 1/2 at start,
-						full at end of frame */
-#define	SSP_SSCR1_MWDS		(1U << 5)/* Microwire data size:
-					    0 = 8 bit
-					    1 = 16 bit */
-#define	SSP_SSCR1_TFT		(((x) - 1) << 6) /* Tx FIFO threshold */
-#define	SSP_SSCR1_RFT		(((x) - 1) << 10)/* Rx FIFO threshold */
-#define	SSP_SSCR1_EFWR		(1U << 14)/* enab. FIFO write/read */
-#define	SSP_SSCR1_STRF		(1U << 15)/* FIFO write/read FIFO select:
-					     0 = Tx FIFO
-					     1 = Rx FIFO */
-
-#define	SSP_SSSR_TNF		(1U << 2)/* Tx FIFO not full */
-#define	SSP_SSSR_RNE		(1U << 3)/* Rx FIFO not empty */
-#define	SSP_SSSR_BSY		(1U << 4)/* SSP is busy */
-#define	SSP_SSSR_TFS		(1U << 5)/* Tx FIFO service request */
-#define	SSP_SSSR_RFS		(1U << 6)/* Rx FIFO service request */
-#define	SSP_SSSR_ROR		(1U << 7)/* Rx FIFO overrun */
-#define	SSP_SSSR_TFL(x)		(((x) >> 8) & 0xf) /* Tx FIFO level */
-#define	SSP_SSSR_RFL(x)		(((x) >> 12) & 0xf)/* Rx FIFO level */
-
-#define	SSP_SSITR_TTFS		(1U << 5)/* Test Tx FIFO service */
-#define	SSP_SSITR_TRFS		(1U << 6)/* Test Rx FIFO service */
-#define	SSP_SSITR_TROR		(1U << 7)/* Test Rx overrun */
-
-#endif /* CPU_XSCALE_80321 */
+//#define	ICU_INT_HWMASK		(0xffffffff & \
+//					~((1 << ICU_INT_bit26) | \
+//					  (1 << ICU_INT_bit22) | \
+//					  (1 << ICU_INT_bit5)  | \
+//					  (1 << ICU_INT_bit4)))
 
 /*
  * Peripheral Bus Interface Unit
diff --git a/sys/conf/files.arm b/sys/conf/files.arm
index 9f3a6bf..bc5d8a3 100644
--- a/sys/conf/files.arm
+++ b/sys/conf/files.arm
@@ -14,14 +14,14 @@ arm/arm/cpufunc_asm.S		standard
 arm/arm/cpufunc_asm_arm9.S 	optional	cpu_arm9 | cpu_arm9e
 arm/arm/cpufunc_asm_arm11.S	optional	cpu_arm1176
 arm/arm/cpufunc_asm_arm11x6.S	optional	cpu_arm1176
-arm/arm/cpufunc_asm_armv4.S 	optional	cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_80321 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_80219 | cpu_xscale_81342
+arm/arm/cpufunc_asm_armv4.S 	optional	cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342
 arm/arm/cpufunc_asm_armv5_ec.S 	optional	cpu_arm9e
 arm/arm/cpufunc_asm_armv6.S 	optional	cpu_arm1176
 arm/arm/cpufunc_asm_armv7.S	optional	cpu_cortexa | cpu_krait | cpu_mv_pj4b
 arm/arm/cpufunc_asm_fa526.S	optional	cpu_fa526
 arm/arm/cpufunc_asm_pj4b.S	optional	cpu_mv_pj4b
 arm/arm/cpufunc_asm_sheeva.S 	optional	cpu_arm9e
-arm/arm/cpufunc_asm_xscale.S	optional	cpu_xscale_80321 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_80219 | cpu_xscale_81342
+arm/arm/cpufunc_asm_xscale.S	optional	cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342
 arm/arm/cpufunc_asm_xscale_c3.S	optional	cpu_xscale_81342
 arm/arm/cpuinfo.c		standard
 arm/arm/cpu_asm-v6.S		optional	armv6
diff --git a/sys/conf/options.arm b/sys/conf/options.arm
index ef66413..7beae5b 100644
--- a/sys/conf/options.arm
+++ b/sys/conf/options.arm
@@ -15,8 +15,6 @@ CPU_CORTEXA		opt_global.h
 CPU_KRAIT		opt_global.h
 CPU_FA526		opt_global.h
 CPU_MV_PJ4B		opt_global.h
-CPU_XSCALE_80219	opt_global.h
-CPU_XSCALE_80321	opt_global.h
 CPU_XSCALE_81342	opt_global.h
 CPU_XSCALE_IXP425	opt_global.h
 CPU_XSCALE_IXP435	opt_global.h