MFC r277306, r277307, r277346:

  Add defines for SDHCI 3.0 controllers.

  Add a new SDHCI quirk, SDHCI_QUIRK_DONT_SET_HISPD_BIT.

  Save the command-and-flags value into shadow register when it is written.

3 files changed, 38 insertions, 2 deletions

diff --git a/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c b/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
index 42ce786..93bfcab 100644
--- a/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
+++ b/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c
@@ -232,6 +232,7 @@ bcm_sdhci_attach(device_t dev)
 	sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
 	sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 
 		| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
+		| SDHCI_QUIRK_DONT_SET_HISPD_BIT
 		| SDHCI_QUIRK_MISSING_CAPS;
  
 	sdhci_init_slot(dev, &sc->sc_slot, 0);
@@ -401,8 +402,11 @@ bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_
 	val32 |= (val << (off & 3)*8);
 	if (off == SDHCI_TRANSFER_MODE)
 		sc->cmd_and_mode = val32;
-	else
+	else {
 		WR4(sc, off & ~3, val32);
+		if (off == SDHCI_COMMAND_FLAGS)
+			sc->cmd_and_mode = val32;
+	}
 }
 
 static void
diff --git a/sys/dev/sdhci/sdhci.c b/sys/dev/sdhci/sdhci.c
index bb99937..009decd 100644
--- a/sys/dev/sdhci/sdhci.c
+++ b/sys/dev/sdhci/sdhci.c
@@ -697,7 +697,8 @@ sdhci_generic_update_ios(device_t brdev, device_t reqdev)
 		slot->hostctrl |= SDHCI_CTRL_4BITBUS;
 	else
 		slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
-	if (ios->timing == bus_timing_hs)
+	if (ios->timing == bus_timing_hs && 
+	    !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
 		slot->hostctrl |= SDHCI_CTRL_HISPD;
 	else
 		slot->hostctrl &= ~SDHCI_CTRL_HISPD;
diff --git a/sys/dev/sdhci/sdhci.h b/sys/dev/sdhci/sdhci.h
index ff1576e..b7d1960 100644
--- a/sys/dev/sdhci/sdhci.h
+++ b/sys/dev/sdhci/sdhci.h
@@ -61,6 +61,8 @@
 #define	SDHCI_QUIRK_DONT_SHIFT_RESPONSE			(1<<13)
 /* Wait to see reset bit asserted before waiting for de-asserted  */
 #define	SDHCI_QUIRK_WAITFOR_RESET_ASSERTED		(1<<14)
+/* Leave controller in standard mode when putting card in HS mode. */
+#define	SDHCI_QUIRK_DONT_SET_HISPD_BIT			(1<<15)
 
 /*
  * Controller registers
@@ -169,6 +171,10 @@
 #define  SDHCI_INT_CARD_INSERT	0x00000040
 #define  SDHCI_INT_CARD_REMOVE	0x00000080
 #define  SDHCI_INT_CARD_INT	0x00000100
+#define  SDHCI_INT_INT_A	0x00000200
+#define  SDHCI_INT_INT_B	0x00000400
+#define  SDHCI_INT_INT_C	0x00000800
+#define  SDHCI_INT_RETUNE	0x00001000
 #define  SDHCI_INT_ERROR	0x00008000
 #define  SDHCI_INT_TIMEOUT	0x00010000
 #define  SDHCI_INT_CRC		0x00020000
@@ -180,6 +186,7 @@
 #define  SDHCI_INT_BUS_POWER	0x00800000
 #define  SDHCI_INT_ACMD12ERR	0x01000000
 #define  SDHCI_INT_ADMAERR	0x02000000
+#define  SDHCI_INT_TUNEERR	0x04000000
 
 #define  SDHCI_INT_NORMAL_MASK	0x00007FFF
 #define  SDHCI_INT_ERROR_MASK	0xFFFF8000
@@ -195,6 +202,7 @@
 		SDHCI_INT_DATA_END_BIT)
 
 #define SDHCI_ACMD12_ERR	0x3C
+#define SDHCI_HOST_CONTROL2	0x3E
 
 #define SDHCI_CAPABILITIES	0x40
 #define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
@@ -214,8 +222,31 @@
 #define  SDHCI_CAN_VDD_300	0x02000000
 #define  SDHCI_CAN_VDD_180	0x04000000
 #define  SDHCI_CAN_DO_64BIT	0x10000000
+#define  SDHCI_CAN_ASYNC_INTR	0x20000000
+
+#define SDHCI_CAPABILITIES2	0x44
+#define  SDHCI_CAN_SDR50	0x00000001
+#define  SDHCI_CAN_SDR104	0x00000002
+#define  SDHCI_CAN_DDR50	0x00000004
+#define  SDHCI_CAN_DRIVE_TYPE_A	0x00000010
+#define  SDHCI_CAN_DRIVE_TYPE_B	0x00000020
+#define  SDHCI_CAN_DRIVE_TYPE_C	0x00000040
+#define  SDHCI_RETUNE_CNT_MASK	0x00000F00
+#define  SDHCI_RETUNE_CNT_SHIFT	8
+#define  SDHCI_TUNE_SDR50	0x00002000
+#define  SDHCI_RETUNE_MODES_MASK  0x0000C000
+#define  SDHCI_RETUNE_MODES_SHIFT 14
+#define  SDHCI_CLOCK_MULT_MASK	0x00FF0000
+#define  SDHCI_CLOCK_MULT_SHIFT	16
 
 #define SDHCI_MAX_CURRENT	0x48
+#define SDHCI_FORCE_AUTO_EVENT	0x50
+#define SDHCI_FORCE_INTR_EVENT	0x52
+#define SDHCI_ADMA_ERR		0x54
+#define SDHCI_ADMA_ADDRESS_LOW	0x58
+#define SDHCI_ADMA_ADDRESS_HI	0x5C
+#define SDHCI_PRESET_VALUE	0x60
+#define SDHCI_SHARED_BUS_CTRL	0xE0
 
 #define SDHCI_SLOT_INT_STATUS	0xFC