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| author | andre <andre@FreeBSD.org> | 2005-11-15 20:18:13 +0000 |
|---|---|---|
| committer | andre <andre@FreeBSD.org> | 2005-11-15 20:18:13 +0000 |
| commit | 2444f687d5f6e2e5d377a05b9109889630146321 (patch) | |
| tree | bef4e1a2e169aa00616db2d35a177a9dba70186b | |
| parent | 644983853bb5c7cb9171a1de252a5431440da82e (diff) | |
| download | FreeBSD-src-2444f687d5f6e2e5d377a05b9109889630146321.zip FreeBSD-src-2444f687d5f6e2e5d377a05b9109889630146321.tar.gz | |
Provide a link to the documentation of the I/O APIC at Intel.
| -rw-r--r-- | sys/i386/i386/io_apic.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/i386/i386/io_apic.c b/sys/i386/i386/io_apic.c index ab426c7..e4f49c5 100644 --- a/sys/i386/i386/io_apic.c +++ b/sys/i386/i386/io_apic.c @@ -74,6 +74,10 @@ static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures"); * IRQs behave as PCI IRQs by default. We also assume that the pin for * IRQ 0 is actually an ExtINT pin. The apic enumerators override the * configuration of individual pins as indicated by their tables. + * + * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable + * Interrupt Controller (IOAPIC)", May 1996, Intel Corp. + * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf */ struct ioapic_intsrc { |
