From 2444f687d5f6e2e5d377a05b9109889630146321 Mon Sep 17 00:00:00 2001 From: andre Date: Tue, 15 Nov 2005 20:18:13 +0000 Subject: Provide a link to the documentation of the I/O APIC at Intel. --- sys/i386/i386/io_apic.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sys/i386/i386/io_apic.c b/sys/i386/i386/io_apic.c index ab426c7..e4f49c5 100644 --- a/sys/i386/i386/io_apic.c +++ b/sys/i386/i386/io_apic.c @@ -74,6 +74,10 @@ static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures"); * IRQs behave as PCI IRQs by default. We also assume that the pin for * IRQ 0 is actually an ExtINT pin. The apic enumerators override the * configuration of individual pins as indicated by their tables. + * + * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable + * Interrupt Controller (IOAPIC)", May 1996, Intel Corp. + * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf */ struct ioapic_intsrc { -- cgit v1.1