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# ex:ts=8
# New ports collection makefile for: iverilog
# Date created: Feb 13, 2001
# Whom: Ying-Chieh Liao <ijliao@FreeBSD.org>
#
# $FreeBSD$
#
PORTNAME= iverilog
PORTVERSION= 0.7
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/
DISTNAME= verilog-${PORTVERSION}
MAINTAINER= keichii@FreeBSD.org
COMMENT= Icarus Verilog is a Verilog simulation and synthesis tool
GNU_CONFIGURE= yes
USE_BISON= yes
USE_GMAKE= yes
MAN1= iverilog.1 vvp.1
.include <bsd.port.mk>
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