blob: 6c25425fe7d9f38dc81ccf5b6550582926d8386f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
# Created by: ijliao
# $FreeBSD$
PORTNAME= gplcver
PORTVERSION= 2.12.a
CATEGORIES= cad
MASTER_SITES= SF/${PORTNAME}/${PORTNAME}/${PORTVERSION:R}${PORTVERSION:E}/
DISTNAME= ${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src
MAINTAINER= ports@FreeBSD.org
COMMENT= Verilog HDL simulator
USES= tar:bzip2 gmake
BUILD_WRKSRC= ${WRKSRC}/src
MAKEFILE= makefile.freebsd
PLIST_FILES= bin/cver
do-install:
${INSTALL_PROGRAM} ${WRKSRC}/bin/cver ${STAGEDIR}${PREFIX}/bin
.include <bsd.port.mk>
|