summaryrefslogtreecommitdiffstats
path: root/cad/chipvault/Makefile
blob: ed6f8a1c0cb4fc6d669512e8d6a82015fc1aa074 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
# Created by: ijliao
# $FreeBSD$

PORTNAME=	chipvault
PORTVERSION=	200607
CATEGORIES=	cad
MASTER_SITES=	http://chipvault.sourceforge.net/
DISTNAME=	cv.pl
EXTRACT_SUFX=	.gz

MAINTAINER=	ports@FreeBSD.org
COMMENT=	A project organizer for VHDL and Verilog RTL hardware designs

NO_WRKSUBDIR=	yes
EXTRACT_CMD=	${GZCAT}
EXTRACT_BEFORE_ARGS=	# empty
EXTRACT_AFTER_ARGS=	> ${DISTNAME}
NO_BUILD=	yes
PLIST_FILES=	bin/cv
USES=		perl5
USE_PERL5=	run

NO_STAGE=	yes
do-install:
	${INSTALL_SCRIPT} ${WRKSRC}/cv.pl ${PREFIX}/bin/cv

.include <bsd.port.mk>
OpenPOWER on IntegriCloud