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-rw-r--r--cad/iverilog/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index 3df1153..82094e4 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -9,7 +9,7 @@ MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \
DISTNAME= verilog-${PORTVERSION}
MAINTAINER= zeising@FreeBSD.org
-COMMENT= A Verilog simulation and synthesis tool
+COMMENT= Verilog simulation and synthesis tool
LICENSE= GPLv2
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