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authorlinimon <linimon@FreeBSD.org>2003-10-17 08:26:42 +0000
committerlinimon <linimon@FreeBSD.org>2003-10-17 08:26:42 +0000
commit0671c05e31e4d3610aac75695ccc35196bff3f08 (patch)
treec07fd16d509d783d05dd528fee4ba2018dfff228 /cad/iverilog
parent106f259dd4d65d89be2e423198793d494c9f356e (diff)
downloadFreeBSD-ports-0671c05e31e4d3610aac75695ccc35196bff3f08.zip
FreeBSD-ports-0671c05e31e4d3610aac75695ccc35196bff3f08.tar.gz
Maintainer update to snapshot version. In addition to fixing the port
for gcc3.3, 10 months of updates are included: - Rework expression parsing and elaboration to accomodate real/realtime values and expressions. - Calculate delay statement delays using elaborated expressions instead of pre-elaborated expression trees. - Implement the wait statement behaviorally instead of as nets. - Support event names as expression elements. - Fix configuration errors, spelling errors, clarification of certain objects. See internal revision logs in each file for more elaboration.
Diffstat (limited to 'cad/iverilog')
-rw-r--r--cad/iverilog/Makefile8
-rw-r--r--cad/iverilog/distinfo2
2 files changed, 6 insertions, 4 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index f1048e3..e0ce997 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -7,10 +7,12 @@
#
PORTNAME= iverilog
-PORTVERSION= 0.7
+PORTVERSION= 0.7.20030722
CATEGORIES= cad
-MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/
-DISTNAME= verilog-${PORTVERSION}
+#MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/
+#DISTNAME= verilog-${PORTVERSION}
+MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
+DISTNAME= verilog-20030722
MAINTAINER= watchman@ludd.luth.se
COMMENT= A Verilog simulation and synthesis tool
diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo
index 7bfda1f..d334394 100644
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@@ -1 +1 @@
-MD5 (verilog-0.7.tar.gz) = c8f09bc061e890242d39b9afc8e69698
+MD5 (verilog-20030722.tar.gz) = b435baa100fb368a9cfc12f510af9c6e
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