From f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Wed, 2 Jan 2008 21:52:27 +0000
Subject: Initial import from www.ecosforge.net

---
 zpu/.project                                       |    11 +
 zpu/COPYING                                        |    12 +
 zpu/ChangeLog                                      |    11 +
 zpu/STATUS                                         |    11 +
 zpu/docs/presentations/zpu.odp                     |   Bin 0 -> 60715 bytes
 zpu/docs/presentations/zpudemo.odp                 |   Bin 0 -> 222644 bytes
 zpu/docs/zpupresentation.odp                       |   Bin 0 -> 78518 bytes
 zpu/docs/zpupresentation.ppt                       |   Bin 0 -> 150016 bytes
 zpu/docs/zpupresentation_old.odt                   |   Bin 0 -> 126772 bytes
 zpu/docs/zpuprotoarch.odt                          |   Bin 0 -> 23961 bytes
 zpu/hdl/example/helloworld.vhd                     | 12506 +++++++++++++++++++
 zpu/hdl/example/io.vhd                             |    97 +
 zpu/hdl/example/log.txt                            |    15 +
 zpu/hdl/example/sim_fpga_top.vhd                   |   179 +
 zpu/hdl/example/simzpu.do                          |    29 +
 zpu/hdl/example/zpu_config.vhd                     |    20 +
 zpu/hdl/index.html                                 |    47 +
 zpu/hdl/wishbone/wishbone_pkg.vhd                  |    52 +
 zpu/hdl/wishbone/zpu_system.vhd                    |    71 +
 zpu/hdl/wishbone/zpu_wb_bridge.vhd                 |    49 +
 zpu/hdl/zpu3/src/.cvsignore                        |     1 +
 zpu/hdl/zpu3/src/build.xml                         |   114 +
 zpu/hdl/zpu3/src/clocks.vhd                        |   246 +
 zpu/hdl/zpu3/src/ddr_bridge.vhd                    |   203 +
 zpu/hdl/zpu3/src/dmips_ram.vhd                     |  3824 ++++++
 zpu/hdl/zpu3/src/dualport_ram.vhd                  |  4996 ++++++++
 zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd       |  5012 ++++++++
 zpu/hdl/zpu3/src/helloworld_ram.vhd                |  3345 +++++
 zpu/hdl/zpu3/src/ic300.bitgen                      |    27 +
 zpu/hdl/zpu3/src/ic300.lso                         |     1 +
 zpu/hdl/zpu3/src/ic300.ucf                         |   146 +
 zpu/hdl/zpu3/src/ic300.vhd                         |   144 +
 zpu/hdl/zpu3/src/ic300_config.vhd                  |    20 +
 zpu/hdl/zpu3/src/ic300pkg.vhd                      |    88 +
 zpu/hdl/zpu3/src/io.vhd                            |    95 +
 zpu/hdl/zpu3/src/log.txt                           |   156 +
 zpu/hdl/zpu3/src/niltrace.vhd                      |    26 +
 zpu/hdl/zpu3/src/sim_fpga_top.vhd                  |   127 +
 zpu/hdl/zpu3/src/status.txt                        |    67 +
 zpu/hdl/zpu3/src/testlut.vhd                       |   106 +
 zpu/hdl/zpu3/src/timer.vhd                         |   157 +
 zpu/hdl/zpu3/src/trace.vhd                         |    80 +
 zpu/hdl/zpu3/src/txt_util.vhd                      |   586 +
 zpu/hdl/zpu3/src/xilinx_dualport.vhd               |  1482 +++
 zpu/hdl/zpu3/src/xmake.filelist                    |     5 +
 zpu/hdl/zpu3/src/xmake.xst                         |    53 +
 zpu/hdl/zpu3/src/zpu_config.vhd                    |    25 +
 zpu/hdl/zpu3/src/zpu_pipelined.vhd                 |   852 ++
 zpu/hdl/zpu3/src/zpu_top.vhd                       |   421 +
 zpu/hdl/zpu3/src/zpu_top_medium.vhd                |   768 ++
 zpu/hdl/zpu3/src/zpuio.vhd                         |   180 +
 zpu/hdl/zpu3/src/zpupkg.vhd                        |   130 +
 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd     |    31 +
 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd      |   213 +
 .../dummyfpgalib/ddrsdram/simscripts/ddr_tb.do     |    17 +
 .../dummyfpgalib/ddrsdram/simscripts/ddr_top.do    |   111 +
 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd |    90 +
 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd  |   301 +
 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd |   660 +
 .../zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd  |  1320 ++
 zpu/hdl/zpu4/src/.cvsignore                        |     5 +
 zpu/hdl/zpu4/src/bram.vhd                          |  3807 ++++++
 zpu/hdl/zpu4/src/bram_dmips.vhd                    |  3717 ++++++
 zpu/hdl/zpu4/src/build.xml                         |   114 +
 zpu/hdl/zpu4/src/clocks.vhd                        |   246 +
 zpu/hdl/zpu4/src/dmipssmalltrace.do                |    26 +
 zpu/hdl/zpu4/src/dmipstrace.do                     |    25 +
 zpu/hdl/zpu4/src/dmipstraceintstack.do             |    25 +
 zpu/hdl/zpu4/src/dram_dmips.vhd                    |  3702 ++++++
 zpu/hdl/zpu4/src/dram_hello.vhd                    |  3214 +++++
 zpu/hdl/zpu4/src/fastdmips.do                      |    19 +
 zpu/hdl/zpu4/src/fastdmipsintstack.do              |    19 +
 zpu/hdl/zpu4/src/fastdmipssmall.do                 |    21 +
 zpu/hdl/zpu4/src/fastsimzpu.do                     |    19 +
 zpu/hdl/zpu4/src/ic300.bitgen                      |    27 +
 zpu/hdl/zpu4/src/ic300.lso                         |     1 +
 zpu/hdl/zpu4/src/ic300.ucf                         |   146 +
 zpu/hdl/zpu4/src/ic300.vhd                         |   144 +
 zpu/hdl/zpu4/src/ic300_config.vhd                  |    26 +
 zpu/hdl/zpu4/src/ic300pkg.vhd                      |    88 +
 zpu/hdl/zpu4/src/io.vhd                            |    92 +
 zpu/hdl/zpu4/src/log.txt                           |   380 +
 zpu/hdl/zpu4/src/niltrace.vhd                      |    26 +
 zpu/hdl/zpu4/src/sim_fpga_top.vhd                  |   190 +
 zpu/hdl/zpu4/src/simzpu.do                         |    23 +
 zpu/hdl/zpu4/src/simzpu_intstack.do                |    23 +
 zpu/hdl/zpu4/src/status.txt                        |   109 +
 zpu/hdl/zpu4/src/testlut.vhd                       |   114 +
 zpu/hdl/zpu4/src/timer.vhd                         |    61 +
 zpu/hdl/zpu4/src/trace.vhd                         |    84 +
 zpu/hdl/zpu4/src/txt_util.vhd                      |   587 +
 zpu/hdl/zpu4/src/xmake.filelist                    |    12 +
 zpu/hdl/zpu4/src/xmake.filelist.bramsmall          |     5 +
 zpu/hdl/zpu4/src/xmake.xst                         |    53 +
 zpu/hdl/zpu4/src/zpu_config.vhd                    |    16 +
 zpu/hdl/zpu4/src/zpu_config_fastsim.vhd            |    15 +
 zpu/hdl/zpu4/src/zpu_config_trace.vhd              |    15 +
 zpu/hdl/zpu4/src/zpu_core.vhd                      |   900 ++
 zpu/hdl/zpu4/src/zpu_core_small.vhd                |   433 +
 zpu/hdl/zpu4/src/zpuio.vhd                         |   256 +
 zpu/hdl/zpu4/src/zpuio_bram.vhd                    |   229 +
 zpu/hdl/zpu4/src/zpupkg.vhd                        |   168 +
 zpu/hdl/zpu4/test/dmips/build.sh                   |     3 +
 zpu/hdl/zpu4/test/dmips/dmips.bin                  |   Bin 0 -> 14612 bytes
 zpu/hdl/zpu4/test/dmips/dmips.elf                  |   Bin 0 -> 89778 bytes
 zpu/hdl/zpu4/test/dmips/dmips.ram                  |  3507 ++++++
 zpu/hdl/zpu4/test/hello/build.sh                   |     3 +
 zpu/hdl/zpu4/test/hello/hello.bin                  |   Bin 0 -> 12664 bytes
 zpu/hdl/zpu4/test/hello/hello.c                    |    51 +
 zpu/hdl/zpu4/test/hello/hello.elf                  |   Bin 0 -> 150455 bytes
 zpu/hdl/zpu4/test/hello/hello.ram                  |  3165 +++++
 zpu/index.html                                     |    20 +
 zpu/roadshow/roadshow/build/makefirmware.sh        |    13 +
 zpu/roadshow/roadshow/codesize/.cvsignore          |     1 +
 zpu/roadshow/roadshow/codesize/crt0_phi.S          |   178 +
 zpu/roadshow/roadshow/codesize/hello.c             |     9 +
 zpu/roadshow/roadshow/codesize/index.html          |    58 +
 zpu/roadshow/roadshow/codesize/small.c             |     9 +
 zpu/roadshow/roadshow/codesize/small.elf           |   Bin 0 -> 1577 bytes
 zpu/roadshow/roadshow/codesize/smallstd.c          |     9 +
 zpu/roadshow/roadshow/dhrystone/.cvsignore         |     2 +
 zpu/roadshow/roadshow/dhrystone/RATIONALE          |   361 +
 zpu/roadshow/roadshow/dhrystone/README_C           |    78 +
 zpu/roadshow/roadshow/dhrystone/VARIATIONS         |   157 +
 zpu/roadshow/roadshow/dhrystone/build.sh           |     7 +
 zpu/roadshow/roadshow/dhrystone/dhry-c             |  1779 +++
 zpu/roadshow/roadshow/dhrystone/dhry.h             |   423 +
 zpu/roadshow/roadshow/dhrystone/dhry_1.c           |   533 +
 zpu/roadshow/roadshow/dhrystone/dhry_2.c           |   192 +
 zpu/roadshow/roadshow/dhrystone/dhry_c.dif         |   141 +
 zpu/roadshow/roadshow/dhrystone/dhrystone.bin      |   Bin 0 -> 13028 bytes
 zpu/roadshow/roadshow/dhrystone/dhrystone.zpu      |   Bin 0 -> 13069 bytes
 zpu/roadshow/roadshow/dhrystone/submit.frm         |    17 +
 .../roadshow/ecos/codesize/zpuarmcodesize.htm      |  1049 ++
 zpu/roadshow/roadshow/ecos/index.html              |   145 +
 zpu/roadshow/roadshow/ecos/repository.tar.bz2      |   Bin 0 -> 28572 bytes
 zpu/roadshow/roadshow/games/.cvsignore             |     5 +
 zpu/roadshow/roadshow/games/build.sh               |     7 +
 zpu/roadshow/roadshow/games/eliza.bin              |   Bin 0 -> 46920 bytes
 zpu/roadshow/roadshow/games/eliza.elf              |   Bin 0 -> 342451 bytes
 zpu/roadshow/roadshow/games/eliza.zpu              |   Bin 0 -> 46961 bytes
 zpu/roadshow/roadshow/games/eliza/eliza.c          |   269 +
 zpu/roadshow/roadshow/games/eliza/parse.c          |   719 ++
 zpu/roadshow/roadshow/games/eliza/parse.h          |    33 +
 zpu/roadshow/roadshow/games/eliza/response.c       |   365 +
 zpu/roadshow/roadshow/games/eliza/response.h       |    41 +
 zpu/roadshow/roadshow/games/sumeria.bin            |   Bin 0 -> 42324 bytes
 zpu/roadshow/roadshow/games/sumeria.c              |   444 +
 zpu/roadshow/roadshow/games/sumeria.zpu            |   Bin 0 -> 42365 bytes
 zpu/roadshow/roadshow/helloworld/build.sh          |     6 +
 zpu/roadshow/roadshow/helloworld/test.bin          |   Bin 0 -> 49836 bytes
 zpu/roadshow/roadshow/helloworld/test.c            |    11 +
 zpu/roadshow/roadshow/helloworld/test.elf          |   Bin 0 -> 279826 bytes
 zpu/roadshow/roadshow/helloworld/test.zpu          |   Bin 0 -> 262353 bytes
 zpu/roadshow/roadshow/hwtest/build.sh              |     6 +
 zpu/roadshow/roadshow/hwtest/test.S                |    19 +
 zpu/roadshow/roadshow/hwtest/test.bin              |   Bin 0 -> 48 bytes
 zpu/roadshow/roadshow/hwtest/test.elf              |   Bin 0 -> 1343 bytes
 zpu/roadshow/roadshow/hwtest/test.zpu              |   Bin 0 -> 212562 bytes
 zpu/roadshow/roadshow/images/bootloader.phi        |   Bin 0 -> 167015 bytes
 zpu/roadshow/roadshow/images/dhrystone.zpu         |   Bin 0 -> 13069 bytes
 zpu/roadshow/roadshow/images/eliza.zpu             |   Bin 0 -> 46961 bytes
 zpu/roadshow/roadshow/images/ic300.bit             |   Bin 0 -> 212463 bytes
 zpu/roadshow/roadshow/images/net_test.zpu          |   Bin 0 -> 206210 bytes
 zpu/roadshow/roadshow/images/sumeria.zpu           |   Bin 0 -> 42365 bytes
 zpu/roadshow/roadshow/iss/index.html               |    14 +
 zpu/roadshow/roadshow/iss/simulator.jar            |   Bin 0 -> 54378 bytes
 zpu/roadshow/roadshow/net_test/.cvsignore          |     8 +
 zpu/roadshow/roadshow/net_test/http_pages.c        |   206 +
 zpu/roadshow/roadshow/net_test/init.cpp            |    52 +
 zpu/roadshow/roadshow/net_test/makefile            |    41 +
 zpu/roadshow/roadshow/net_test/net_test.ecm        |   237 +
 zpu/roadshow/roadshow/net_test/ping_test.c         |   585 +
 zpu/roadshow/roadshow/pics/GCC_logo.png            |   Bin 0 -> 23450 bytes
 zpu/roadshow/roadshow/pics/codesize1.PNG           |   Bin 0 -> 9329 bytes
 zpu/roadshow/roadshow/pics/codesize2.PNG           |   Bin 0 -> 16967 bytes
 zpu/roadshow/roadshow/pics/ecos.gif                |   Bin 0 -> 1660 bytes
 zpu/roadshow/roadshow/pics/elizadebug1.PNG         |   Bin 0 -> 72126 bytes
 zpu/roadshow/roadshow/pics/elizadebug2.PNG         |   Bin 0 -> 67822 bytes
 zpu/snapshot.sh                                    |     7 +
 .../current/cdl/opencores_ethermac_drivers.cdl     |   149 +
 zpu/sw/ecos/repository/ecos.db                     |   128 +
 zpu/sw/helloworld/gccgdb.PNG                       |   Bin 0 -> 34473 bytes
 zpu/sw/helloworld/gmon.out                         |   Bin 0 -> 120053 bytes
 zpu/sw/helloworld/hello.bin                        |   Bin 0 -> 49768 bytes
 zpu/sw/helloworld/hello.bram                       | 12441 ++++++++++++++++++
 zpu/sw/helloworld/hello.c                          |     6 +
 zpu/sw/helloworld/hello.elf                        |   Bin 0 -> 279938 bytes
 zpu/sw/helloworld/zpusim.PNG                       |   Bin 0 -> 17817 bytes
 zpu/sw/index.html                                  |    44 +
 zpu/sw/simulator/.classpath                        |     6 +
 zpu/sw/simulator/.project                          |    17 +
 .../simulator/.settings/org.eclipse.jdt.core.prefs |    66 +
 zpu/sw/simulator/ChangeLog                         |     2 +
 zpu/sw/simulator/build.xml                         |     7 +
 zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java |   109 +
 .../com/zylin/zpu/simulator/FileTracer.java        |   285 +
 zpu/sw/simulator/com/zylin/zpu/simulator/Host.java |    46 +
 .../simulator/com/zylin/zpu/simulator/Machine.java |    17 +
 zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java  |   126 +
 .../com/zylin/zpu/simulator/PhiFeeble.java         |    34 +
 zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java  |    62 +
 .../simulator/com/zylin/zpu/simulator/SimApp.java  |   112 +
 .../com/zylin/zpu/simulator/SimFactory.java        |     8 +
 .../com/zylin/zpu/simulator/Simulator.java         |  2063 +++
 .../simulator/com/zylin/zpu/simulator/State.java   |     9 +
 .../simulator/com/zylin/zpu/simulator/Tracer.java  |    21 +
 zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java  |    14 +
 .../com/zylin/zpu/simulator/applet/ZPUApplet.java  |   281 +
 .../simulator/exceptions/BadPacketException.java   |    22 +
 .../zpu/simulator/exceptions/CPUException.java     |    23 +
 .../exceptions/DebuggerBreakpointException.java    |    10 +
 .../simulator/exceptions/EndSessionException.java  |    22 +
 .../simulator/exceptions/GDBServerException.java   |    25 +
 .../exceptions/HardwareWatchPointException.java    |    12 +
 .../exceptions/IllegalInstructionException.java    |    23 +
 .../simulator/exceptions/InterruptException.java   |    23 +
 .../exceptions/MemoryAccessException.java          |    23 +
 .../zpu/simulator/exceptions/NoAckException.java   |    22 +
 .../zpu/simulator/exceptions/TraceException.java   |    22 +
 .../exceptions/UnknownPacketException.java         |    10 +
 .../exceptions/UnsupportedSyscallException.java    |    12 +
 .../com/zylin/zpu/simulator/gdb/GDBServer.java     |   609 +
 .../com/zylin/zpu/simulator/gdb/Packet.java        |   455 +
 .../com/zylin/zpu/simulator/tools/MakeDRAM.java    |    39 +
 .../com/zylin/zpu/simulator/tools/MakeRam.java     |    39 +
 .../com/zylin/zpu/stats/CountSequences.java        |    94 +
 zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java   |    17 +
 .../simulator/com/zylin/zpu/stats/Instruction.java |    62 +
 .../simulator/com/zylin/zpu/stats/StatKeeper.java  |    52 +
 zpu/sw/simulator/gmon.out                          |   Bin 0 -> 120053 bytes
 zpu/sw/simulator/zpusim.jar                        |   Bin 0 -> 68039 bytes
 232 files changed, 91172 insertions(+)
 create mode 100644 zpu/.project
 create mode 100644 zpu/COPYING
 create mode 100644 zpu/ChangeLog
 create mode 100644 zpu/STATUS
 create mode 100644 zpu/docs/presentations/zpu.odp
 create mode 100644 zpu/docs/presentations/zpudemo.odp
 create mode 100644 zpu/docs/zpupresentation.odp
 create mode 100644 zpu/docs/zpupresentation.ppt
 create mode 100644 zpu/docs/zpupresentation_old.odt
 create mode 100644 zpu/docs/zpuprotoarch.odt
 create mode 100644 zpu/hdl/example/helloworld.vhd
 create mode 100644 zpu/hdl/example/io.vhd
 create mode 100644 zpu/hdl/example/log.txt
 create mode 100644 zpu/hdl/example/sim_fpga_top.vhd
 create mode 100644 zpu/hdl/example/simzpu.do
 create mode 100644 zpu/hdl/example/zpu_config.vhd
 create mode 100644 zpu/hdl/index.html
 create mode 100644 zpu/hdl/wishbone/wishbone_pkg.vhd
 create mode 100644 zpu/hdl/wishbone/zpu_system.vhd
 create mode 100644 zpu/hdl/wishbone/zpu_wb_bridge.vhd
 create mode 100644 zpu/hdl/zpu3/src/.cvsignore
 create mode 100644 zpu/hdl/zpu3/src/build.xml
 create mode 100644 zpu/hdl/zpu3/src/clocks.vhd
 create mode 100644 zpu/hdl/zpu3/src/ddr_bridge.vhd
 create mode 100644 zpu/hdl/zpu3/src/dmips_ram.vhd
 create mode 100644 zpu/hdl/zpu3/src/dualport_ram.vhd
 create mode 100644 zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd
 create mode 100644 zpu/hdl/zpu3/src/helloworld_ram.vhd
 create mode 100644 zpu/hdl/zpu3/src/ic300.bitgen
 create mode 100644 zpu/hdl/zpu3/src/ic300.lso
 create mode 100644 zpu/hdl/zpu3/src/ic300.ucf
 create mode 100644 zpu/hdl/zpu3/src/ic300.vhd
 create mode 100644 zpu/hdl/zpu3/src/ic300_config.vhd
 create mode 100644 zpu/hdl/zpu3/src/ic300pkg.vhd
 create mode 100644 zpu/hdl/zpu3/src/io.vhd
 create mode 100644 zpu/hdl/zpu3/src/log.txt
 create mode 100644 zpu/hdl/zpu3/src/niltrace.vhd
 create mode 100644 zpu/hdl/zpu3/src/sim_fpga_top.vhd
 create mode 100644 zpu/hdl/zpu3/src/status.txt
 create mode 100644 zpu/hdl/zpu3/src/testlut.vhd
 create mode 100644 zpu/hdl/zpu3/src/timer.vhd
 create mode 100644 zpu/hdl/zpu3/src/trace.vhd
 create mode 100644 zpu/hdl/zpu3/src/txt_util.vhd
 create mode 100644 zpu/hdl/zpu3/src/xilinx_dualport.vhd
 create mode 100644 zpu/hdl/zpu3/src/xmake.filelist
 create mode 100644 zpu/hdl/zpu3/src/xmake.xst
 create mode 100644 zpu/hdl/zpu3/src/zpu_config.vhd
 create mode 100644 zpu/hdl/zpu3/src/zpu_pipelined.vhd
 create mode 100644 zpu/hdl/zpu3/src/zpu_top.vhd
 create mode 100644 zpu/hdl/zpu3/src/zpu_top_medium.vhd
 create mode 100644 zpu/hdl/zpu3/src/zpuio.vhd
 create mode 100644 zpu/hdl/zpu3/src/zpupkg.vhd
 create mode 100644 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd
 create mode 100644 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd
 create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do
 create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do
 create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd
 create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd
 create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd
 create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd
 create mode 100644 zpu/hdl/zpu4/src/.cvsignore
 create mode 100644 zpu/hdl/zpu4/src/bram.vhd
 create mode 100644 zpu/hdl/zpu4/src/bram_dmips.vhd
 create mode 100644 zpu/hdl/zpu4/src/build.xml
 create mode 100644 zpu/hdl/zpu4/src/clocks.vhd
 create mode 100644 zpu/hdl/zpu4/src/dmipssmalltrace.do
 create mode 100644 zpu/hdl/zpu4/src/dmipstrace.do
 create mode 100644 zpu/hdl/zpu4/src/dmipstraceintstack.do
 create mode 100644 zpu/hdl/zpu4/src/dram_dmips.vhd
 create mode 100644 zpu/hdl/zpu4/src/dram_hello.vhd
 create mode 100644 zpu/hdl/zpu4/src/fastdmips.do
 create mode 100644 zpu/hdl/zpu4/src/fastdmipsintstack.do
 create mode 100644 zpu/hdl/zpu4/src/fastdmipssmall.do
 create mode 100644 zpu/hdl/zpu4/src/fastsimzpu.do
 create mode 100644 zpu/hdl/zpu4/src/ic300.bitgen
 create mode 100644 zpu/hdl/zpu4/src/ic300.lso
 create mode 100644 zpu/hdl/zpu4/src/ic300.ucf
 create mode 100644 zpu/hdl/zpu4/src/ic300.vhd
 create mode 100644 zpu/hdl/zpu4/src/ic300_config.vhd
 create mode 100644 zpu/hdl/zpu4/src/ic300pkg.vhd
 create mode 100644 zpu/hdl/zpu4/src/io.vhd
 create mode 100644 zpu/hdl/zpu4/src/log.txt
 create mode 100644 zpu/hdl/zpu4/src/niltrace.vhd
 create mode 100644 zpu/hdl/zpu4/src/sim_fpga_top.vhd
 create mode 100644 zpu/hdl/zpu4/src/simzpu.do
 create mode 100644 zpu/hdl/zpu4/src/simzpu_intstack.do
 create mode 100644 zpu/hdl/zpu4/src/status.txt
 create mode 100644 zpu/hdl/zpu4/src/testlut.vhd
 create mode 100644 zpu/hdl/zpu4/src/timer.vhd
 create mode 100644 zpu/hdl/zpu4/src/trace.vhd
 create mode 100644 zpu/hdl/zpu4/src/txt_util.vhd
 create mode 100644 zpu/hdl/zpu4/src/xmake.filelist
 create mode 100644 zpu/hdl/zpu4/src/xmake.filelist.bramsmall
 create mode 100644 zpu/hdl/zpu4/src/xmake.xst
 create mode 100644 zpu/hdl/zpu4/src/zpu_config.vhd
 create mode 100644 zpu/hdl/zpu4/src/zpu_config_fastsim.vhd
 create mode 100644 zpu/hdl/zpu4/src/zpu_config_trace.vhd
 create mode 100644 zpu/hdl/zpu4/src/zpu_core.vhd
 create mode 100644 zpu/hdl/zpu4/src/zpu_core_small.vhd
 create mode 100644 zpu/hdl/zpu4/src/zpuio.vhd
 create mode 100644 zpu/hdl/zpu4/src/zpuio_bram.vhd
 create mode 100644 zpu/hdl/zpu4/src/zpupkg.vhd
 create mode 100644 zpu/hdl/zpu4/test/dmips/build.sh
 create mode 100644 zpu/hdl/zpu4/test/dmips/dmips.bin
 create mode 100644 zpu/hdl/zpu4/test/dmips/dmips.elf
 create mode 100644 zpu/hdl/zpu4/test/dmips/dmips.ram
 create mode 100644 zpu/hdl/zpu4/test/hello/build.sh
 create mode 100644 zpu/hdl/zpu4/test/hello/hello.bin
 create mode 100644 zpu/hdl/zpu4/test/hello/hello.c
 create mode 100644 zpu/hdl/zpu4/test/hello/hello.elf
 create mode 100644 zpu/hdl/zpu4/test/hello/hello.ram
 create mode 100644 zpu/index.html
 create mode 100644 zpu/roadshow/roadshow/build/makefirmware.sh
 create mode 100644 zpu/roadshow/roadshow/codesize/.cvsignore
 create mode 100644 zpu/roadshow/roadshow/codesize/crt0_phi.S
 create mode 100644 zpu/roadshow/roadshow/codesize/hello.c
 create mode 100644 zpu/roadshow/roadshow/codesize/index.html
 create mode 100644 zpu/roadshow/roadshow/codesize/small.c
 create mode 100644 zpu/roadshow/roadshow/codesize/small.elf
 create mode 100644 zpu/roadshow/roadshow/codesize/smallstd.c
 create mode 100644 zpu/roadshow/roadshow/dhrystone/.cvsignore
 create mode 100644 zpu/roadshow/roadshow/dhrystone/RATIONALE
 create mode 100644 zpu/roadshow/roadshow/dhrystone/README_C
 create mode 100644 zpu/roadshow/roadshow/dhrystone/VARIATIONS
 create mode 100644 zpu/roadshow/roadshow/dhrystone/build.sh
 create mode 100644 zpu/roadshow/roadshow/dhrystone/dhry-c
 create mode 100644 zpu/roadshow/roadshow/dhrystone/dhry.h
 create mode 100644 zpu/roadshow/roadshow/dhrystone/dhry_1.c
 create mode 100644 zpu/roadshow/roadshow/dhrystone/dhry_2.c
 create mode 100644 zpu/roadshow/roadshow/dhrystone/dhry_c.dif
 create mode 100644 zpu/roadshow/roadshow/dhrystone/dhrystone.bin
 create mode 100644 zpu/roadshow/roadshow/dhrystone/dhrystone.zpu
 create mode 100644 zpu/roadshow/roadshow/dhrystone/submit.frm
 create mode 100644 zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm
 create mode 100644 zpu/roadshow/roadshow/ecos/index.html
 create mode 100644 zpu/roadshow/roadshow/ecos/repository.tar.bz2
 create mode 100644 zpu/roadshow/roadshow/games/.cvsignore
 create mode 100644 zpu/roadshow/roadshow/games/build.sh
 create mode 100644 zpu/roadshow/roadshow/games/eliza.bin
 create mode 100644 zpu/roadshow/roadshow/games/eliza.elf
 create mode 100644 zpu/roadshow/roadshow/games/eliza.zpu
 create mode 100644 zpu/roadshow/roadshow/games/eliza/eliza.c
 create mode 100644 zpu/roadshow/roadshow/games/eliza/parse.c
 create mode 100644 zpu/roadshow/roadshow/games/eliza/parse.h
 create mode 100644 zpu/roadshow/roadshow/games/eliza/response.c
 create mode 100644 zpu/roadshow/roadshow/games/eliza/response.h
 create mode 100644 zpu/roadshow/roadshow/games/sumeria.bin
 create mode 100644 zpu/roadshow/roadshow/games/sumeria.c
 create mode 100644 zpu/roadshow/roadshow/games/sumeria.zpu
 create mode 100644 zpu/roadshow/roadshow/helloworld/build.sh
 create mode 100644 zpu/roadshow/roadshow/helloworld/test.bin
 create mode 100644 zpu/roadshow/roadshow/helloworld/test.c
 create mode 100644 zpu/roadshow/roadshow/helloworld/test.elf
 create mode 100644 zpu/roadshow/roadshow/helloworld/test.zpu
 create mode 100644 zpu/roadshow/roadshow/hwtest/build.sh
 create mode 100644 zpu/roadshow/roadshow/hwtest/test.S
 create mode 100644 zpu/roadshow/roadshow/hwtest/test.bin
 create mode 100644 zpu/roadshow/roadshow/hwtest/test.elf
 create mode 100644 zpu/roadshow/roadshow/hwtest/test.zpu
 create mode 100644 zpu/roadshow/roadshow/images/bootloader.phi
 create mode 100644 zpu/roadshow/roadshow/images/dhrystone.zpu
 create mode 100644 zpu/roadshow/roadshow/images/eliza.zpu
 create mode 100644 zpu/roadshow/roadshow/images/ic300.bit
 create mode 100644 zpu/roadshow/roadshow/images/net_test.zpu
 create mode 100644 zpu/roadshow/roadshow/images/sumeria.zpu
 create mode 100644 zpu/roadshow/roadshow/iss/index.html
 create mode 100644 zpu/roadshow/roadshow/iss/simulator.jar
 create mode 100644 zpu/roadshow/roadshow/net_test/.cvsignore
 create mode 100644 zpu/roadshow/roadshow/net_test/http_pages.c
 create mode 100644 zpu/roadshow/roadshow/net_test/init.cpp
 create mode 100644 zpu/roadshow/roadshow/net_test/makefile
 create mode 100644 zpu/roadshow/roadshow/net_test/net_test.ecm
 create mode 100644 zpu/roadshow/roadshow/net_test/ping_test.c
 create mode 100644 zpu/roadshow/roadshow/pics/GCC_logo.png
 create mode 100644 zpu/roadshow/roadshow/pics/codesize1.PNG
 create mode 100644 zpu/roadshow/roadshow/pics/codesize2.PNG
 create mode 100644 zpu/roadshow/roadshow/pics/ecos.gif
 create mode 100644 zpu/roadshow/roadshow/pics/elizadebug1.PNG
 create mode 100644 zpu/roadshow/roadshow/pics/elizadebug2.PNG
 create mode 100644 zpu/snapshot.sh
 create mode 100644 zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl
 create mode 100644 zpu/sw/ecos/repository/ecos.db
 create mode 100644 zpu/sw/helloworld/gccgdb.PNG
 create mode 100644 zpu/sw/helloworld/gmon.out
 create mode 100644 zpu/sw/helloworld/hello.bin
 create mode 100644 zpu/sw/helloworld/hello.bram
 create mode 100644 zpu/sw/helloworld/hello.c
 create mode 100644 zpu/sw/helloworld/hello.elf
 create mode 100644 zpu/sw/helloworld/zpusim.PNG
 create mode 100644 zpu/sw/index.html
 create mode 100644 zpu/sw/simulator/.classpath
 create mode 100644 zpu/sw/simulator/.project
 create mode 100644 zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs
 create mode 100644 zpu/sw/simulator/ChangeLog
 create mode 100644 zpu/sw/simulator/build.xml
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Host.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/State.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java
 create mode 100644 zpu/sw/simulator/gmon.out
 create mode 100644 zpu/sw/simulator/zpusim.jar

(limited to 'zpu')

diff --git a/zpu/.project b/zpu/.project
new file mode 100644
index 0000000..55b1cb8
--- /dev/null
+++ b/zpu/.project
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>zpu</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+	</buildSpec>
+	<natures>
+	</natures>
+</projectDescription>
diff --git a/zpu/COPYING b/zpu/COPYING
new file mode 100644
index 0000000..96b27d3
--- /dev/null
+++ b/zpu/COPYING
@@ -0,0 +1,12 @@
+About ZPU licensing:
+
+Licensing is not entirely fleshed out yet(there are many parts to a
+soft CPU), but the license for the HDL will be BSD/eCos-like to be
+friendly towards commercially oriented projects, however the
+architecture, documentation and tools will be GPL. This means that all
+updates to the architecture must be shared, but actual
+implementations(which are small and can be very project speific) can
+be friendly towards commercial considerations.
+
+
+Patches to update files w/correct licensing info will be most appreciated!
diff --git a/zpu/ChangeLog b/zpu/ChangeLog
new file mode 100644
index 0000000..827ede8
--- /dev/null
+++ b/zpu/ChangeLog
@@ -0,0 +1,11 @@
+2007-09-11 Øyvind Harboe
+	* Cleaning up zpu/hdl/example. simzpu.do file now uses zpu4/src files instead
+	  of duplicating them. Hello world simzpu.do now works out of the box.
+2007-09-10 Øyvind Harboe
+	* Cleaning up .html files a bit.
+	* retired zpututorial.odt. 
+2007-08-04 Øyvind Harboe
+	* small ZPU hello world example now simulates with valid log.txt/trace.txt file.
+	* Until files are properly organized, ChangeLog will not be kept up to date.
+2007-08-03 Øyvind Harboe
+	* Starting to commit files
diff --git a/zpu/STATUS b/zpu/STATUS
new file mode 100644
index 0000000..e28f191
--- /dev/null
+++ b/zpu/STATUS
@@ -0,0 +1,11 @@
+The current state of the ZPU:
+
+- Patches welcome!
+- Zylin is rummaging up the various files that might be of interest
+  to the open source ZPU project. 
+- The ZPU, GCC toolchain and HDL works. Zylin eCosBoard 1.1 ships w/a 
+  ZPU(see http://www.zylin.com), if you need a development board before 
+  implementing on your own system.
+- The docs leave a lot to be desired at this point.
+- Licensing needs to be ironed out. After which lots of files will have
+  to be updated, strictly speaking. Patches welcome!
diff --git a/zpu/docs/presentations/zpu.odp b/zpu/docs/presentations/zpu.odp
new file mode 100644
index 0000000..e2a6554
Binary files /dev/null and b/zpu/docs/presentations/zpu.odp differ
diff --git a/zpu/docs/presentations/zpudemo.odp b/zpu/docs/presentations/zpudemo.odp
new file mode 100644
index 0000000..d0085a8
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diff --git a/zpu/docs/zpupresentation.odp b/zpu/docs/zpupresentation.odp
new file mode 100644
index 0000000..28d9a7b
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diff --git a/zpu/docs/zpupresentation.ppt b/zpu/docs/zpupresentation.ppt
new file mode 100644
index 0000000..100c4a4
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diff --git a/zpu/docs/zpupresentation_old.odt b/zpu/docs/zpupresentation_old.odt
new file mode 100644
index 0000000..53e1f98
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diff --git a/zpu/docs/zpuprotoarch.odt b/zpu/docs/zpuprotoarch.odt
new file mode 100644
index 0000000..67a4171
Binary files /dev/null and b/zpu/docs/zpuprotoarch.odt differ
diff --git a/zpu/hdl/example/helloworld.vhd b/zpu/hdl/example/helloworld.vhd
new file mode 100644
index 0000000..9c99259
--- /dev/null
+++ b/zpu/hdl/example/helloworld.vhd
@@ -0,0 +1,12506 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"82f4e00c",
+3 => x"3a0b0b81",
+4 => x"e48c0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"81e4fd2d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c9040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88ac",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b82f4",
+162 => x"cc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88af0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8e",
+171 => x"c42d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b90",
+179 => x"8d2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"82f4dc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"0b0b0b83",
+257 => x"e93f0b0b",
+258 => x"82e4cc3f",
+259 => x"04101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101010",
+266 => x"10101010",
+267 => x"53510473",
+268 => x"81ff0673",
+269 => x"83060981",
+270 => x"05830510",
+271 => x"10102b07",
+272 => x"72fc060c",
+273 => x"5151043c",
+274 => x"04727280",
+275 => x"728106ff",
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+12203 => x"0000bea0",
+12204 => x"0000bea8",
+12205 => x"0000bea8",
+12206 => x"0000beb0",
+12207 => x"0000beb0",
+12208 => x"0000beb8",
+12209 => x"0000beb8",
+12210 => x"0000bec0",
+12211 => x"0000bec0",
+12212 => x"0000bec8",
+12213 => x"0000bec8",
+12214 => x"0000bed0",
+12215 => x"0000bed0",
+12216 => x"0000bed8",
+12217 => x"0000bed8",
+12218 => x"0000bee0",
+12219 => x"0000bee0",
+12220 => x"0000bee8",
+12221 => x"0000bee8",
+12222 => x"0000bef0",
+12223 => x"0000bef0",
+12224 => x"0000bef8",
+12225 => x"0000bef8",
+12226 => x"0000bf00",
+12227 => x"0000bf00",
+12228 => x"0000bf08",
+12229 => x"0000bf08",
+12230 => x"0000bf10",
+12231 => x"0000bf10",
+12232 => x"0000bf18",
+12233 => x"0000bf18",
+12234 => x"0000bf20",
+12235 => x"0000bf20",
+12236 => x"0000bf28",
+12237 => x"0000bf28",
+12238 => x"0000bf30",
+12239 => x"0000bf30",
+12240 => x"0000bf38",
+12241 => x"0000bf38",
+12242 => x"0000bf40",
+12243 => x"0000bf40",
+12244 => x"0000bf48",
+12245 => x"0000bf48",
+12246 => x"0000bf50",
+12247 => x"0000bf50",
+12248 => x"0000bf58",
+12249 => x"0000bf58",
+12250 => x"0000bf60",
+12251 => x"0000bf60",
+12252 => x"0000bf68",
+12253 => x"0000bf68",
+12254 => x"0000bf70",
+12255 => x"0000bf70",
+12256 => x"0000bf78",
+12257 => x"0000bf78",
+12258 => x"0000bf80",
+12259 => x"0000bf80",
+12260 => x"0000bf88",
+12261 => x"0000bf88",
+12262 => x"0000bf90",
+12263 => x"0000bf90",
+12264 => x"0000bf98",
+12265 => x"0000bf98",
+12266 => x"0000bfa0",
+12267 => x"0000bfa0",
+12268 => x"0000bfa8",
+12269 => x"0000bfa8",
+12270 => x"0000bfb0",
+12271 => x"0000bfb0",
+12272 => x"0000bfb8",
+12273 => x"0000bfb8",
+12274 => x"0000bfc0",
+12275 => x"0000bfc0",
+12276 => x"0000bfc8",
+12277 => x"0000bfc8",
+12278 => x"0000bfd0",
+12279 => x"0000bfd0",
+12280 => x"0000bfd8",
+12281 => x"0000bfd8",
+12282 => x"0000bfe0",
+12283 => x"0000bfe0",
+12284 => x"0000bfe8",
+12285 => x"0000bfe8",
+12286 => x"0000bff0",
+12287 => x"0000bff0",
+12288 => x"0000bff8",
+12289 => x"0000bff8",
+12290 => x"0000c000",
+12291 => x"0000c000",
+12292 => x"0000c008",
+12293 => x"0000c008",
+12294 => x"0000c010",
+12295 => x"0000c010",
+12296 => x"0000c018",
+12297 => x"0000c018",
+12298 => x"0000c020",
+12299 => x"0000c020",
+12300 => x"0000c028",
+12301 => x"0000c028",
+12302 => x"0000c030",
+12303 => x"0000c030",
+12304 => x"0000c038",
+12305 => x"0000c038",
+12306 => x"0000c040",
+12307 => x"0000c040",
+12308 => x"0000c048",
+12309 => x"0000c048",
+12310 => x"0000c050",
+12311 => x"0000c050",
+12312 => x"0000c058",
+12313 => x"0000c058",
+12314 => x"0000c060",
+12315 => x"0000c060",
+12316 => x"0000c068",
+12317 => x"0000c068",
+12318 => x"0000c070",
+12319 => x"0000c070",
+12320 => x"0000c078",
+12321 => x"0000c078",
+12322 => x"0000c080",
+12323 => x"0000c080",
+12324 => x"0000c088",
+12325 => x"0000c088",
+12326 => x"0000c090",
+12327 => x"0000c090",
+12328 => x"0000c098",
+12329 => x"0000c098",
+12330 => x"0000c0a0",
+12331 => x"0000c0a0",
+12332 => x"0000c0a8",
+12333 => x"0000c0a8",
+12334 => x"0000c0b0",
+12335 => x"0000c0b0",
+12336 => x"0000c0b8",
+12337 => x"0000c0b8",
+12338 => x"0000c0c0",
+12339 => x"0000c0c0",
+12340 => x"0000c0c8",
+12341 => x"0000c0c8",
+12342 => x"0000c0d0",
+12343 => x"0000c0d0",
+12344 => x"0000c0d8",
+12345 => x"0000c0d8",
+12346 => x"0000c0e0",
+12347 => x"0000c0e0",
+12348 => x"0000c0e8",
+12349 => x"0000c0e8",
+12350 => x"0000c0f0",
+12351 => x"0000c0f0",
+12352 => x"0000c0f8",
+12353 => x"0000c0f8",
+12354 => x"0000c100",
+12355 => x"0000c100",
+12356 => x"0000c108",
+12357 => x"0000c108",
+12358 => x"0000c110",
+12359 => x"0000c110",
+12360 => x"0000c118",
+12361 => x"0000c118",
+12362 => x"0000c120",
+12363 => x"0000c120",
+12364 => x"0000c128",
+12365 => x"0000c128",
+12366 => x"0000c130",
+12367 => x"0000c130",
+12368 => x"0000c138",
+12369 => x"0000c138",
+12370 => x"0000c140",
+12371 => x"0000c140",
+12372 => x"0000c148",
+12373 => x"0000c148",
+12374 => x"0000c150",
+12375 => x"0000c150",
+12376 => x"0000c158",
+12377 => x"0000c158",
+12378 => x"0000c160",
+12379 => x"0000c160",
+12380 => x"0000c168",
+12381 => x"0000c168",
+12382 => x"0000c170",
+12383 => x"0000c170",
+12384 => x"0000c178",
+12385 => x"0000c178",
+12386 => x"0000c180",
+12387 => x"0000c180",
+12388 => x"0000c188",
+12389 => x"0000c188",
+12390 => x"0000c190",
+12391 => x"0000c190",
+12392 => x"0000c198",
+12393 => x"0000c198",
+12394 => x"0000c1a0",
+12395 => x"0000c1a0",
+12396 => x"0000c1a8",
+12397 => x"0000c1a8",
+12398 => x"0000c1b0",
+12399 => x"0000c1b0",
+12400 => x"0000c1b8",
+12401 => x"0000c1b8",
+12402 => x"0000c1c0",
+12403 => x"0000c1c0",
+12404 => x"0000c1c8",
+12405 => x"0000c1c8",
+12406 => x"0000c1d0",
+12407 => x"0000c1d0",
+12408 => x"0000c1d8",
+12409 => x"0000c1d8",
+12410 => x"0000c1e0",
+12411 => x"0000c1e0",
+12412 => x"0000c1e8",
+12413 => x"0000c1e8",
+12414 => x"0000c1f0",
+12415 => x"0000c1f0",
+12416 => x"0000c1f8",
+12417 => x"0000c1f8",
+12418 => x"0000c200",
+12419 => x"0000c200",
+12420 => x"0000c208",
+12421 => x"0000c208",
+12422 => x"0000c210",
+12423 => x"0000c210",
+12424 => x"0000c218",
+12425 => x"0000c218",
+12426 => x"0000c220",
+12427 => x"0000c220",
+12428 => x"0000c228",
+12429 => x"0000c228",
+12430 => x"0000c230",
+12431 => x"0000c230",
+12432 => x"0000c238",
+12433 => x"0000c238",
+12434 => x"0000c240",
+12435 => x"0000c240",
+12436 => x"0000ba2c",
+12437 => x"ffffffff",
+12438 => x"00000000",
+12439 => x"ffffffff",
+12440 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(conv_integer(memAAddr)) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(conv_integer(memAAddr));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(conv_integer(memBAddr)) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(conv_integer(memBAddr));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/example/io.vhd b/zpu/hdl/example/io.vhd
new file mode 100644
index 0000000..7dbe36f
--- /dev/null
+++ b/zpu/hdl/example/io.vhd
@@ -0,0 +1,97 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+ 
+entity  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end zpu_io;
+   
+   
+architecture behave of zpu_io is
+
+
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+signal serving : std_logic;
+
+file 		l_file		: TEXT open write_mode is log_file;
+
+begin
+
+	
+	timerinst: timer port map (
+       clk => clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => write(7 downto 0),
+		 adr => addr(4 downto 2),
+		 dout => timer_read);
+	
+	busy <= writeEnable or readEnable;
+	timer_we <= writeEnable and addr(12);
+	
+	process(areset, clk)
+	begin
+		if (areset = '1') then
+--			timer_we <= '0';
+		elsif (clk'event and clk = '1') then
+--			timer_we <= '0';
+			if writeEnable = '1' then
+				-- external interface
+				if addr=x"2028003" then
+					-- Write to UART
+					-- report "" & character'image(conv_integer(memBint)) severity note;
+				    print(l_file, character'val(conv_integer(write)));
+				elsif addr(12)='1' then
+--				    report "xxx" severity failure;
+-- 					timer_we <= '1';
+				else
+					print(l_file, character'val(conv_integer(write)));
+					report "Illegal IO write" severity warning;
+				end if;
+				
+			end if;
+			read <= (others => '0');
+			if (readEnable = '1') then
+				if addr=x"1001" then
+					read <= (0=>'1', others => '0'); -- recieve empty
+ 				elsif addr(12)='1' then
+ 					read(7 downto 0) <= timer_read;
+ 				elsif addr(11)='1' then
+ 					read(7 downto 0) <= ZPU_Frequency;
+ 				elsif addr=x"2028003" then
+					read <= (others => '0');
+				else
+					read <= (others => '0');
+					read(8) <= '1';
+					report "Illegal IO read" severity warning;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+end behave;
+ 
diff --git a/zpu/hdl/example/log.txt b/zpu/hdl/example/log.txt
new file mode 100644
index 0000000..6954a81
--- /dev/null
+++ b/zpu/hdl/example/log.txt
@@ -0,0 +1,15 @@
+H
+e
+l
+l
+o
+ 
+w
+o
+r
+l
+d
+!
+
+
+
diff --git a/zpu/hdl/example/sim_fpga_top.vhd b/zpu/hdl/example/sim_fpga_top.vhd
new file mode 100644
index 0000000..b51fea0
--- /dev/null
+++ b/zpu/hdl/example/sim_fpga_top.vhd
@@ -0,0 +1,179 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    20:15:31 04/14/05
+-- Design Name:    
+-- Module Name:    fpga_top - behave
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity fpga_top is
+end fpga_top;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal	areset			: std_logic;
+
+
+component  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(wordSize-1 downto 0);
+		read	: out std_logic_vector(wordSize-1 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end component;
+
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  enable : std_logic;
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+signal	 		  io_busy : std_logic;
+
+signal			  io_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  io_mem_writeEnable : std_logic; 
+signal			  io_mem_readEnable : std_logic;
+
+
+signal			  dram_ready : std_logic;
+signal			  io_ready : std_logic;
+signal			  io_reading : std_logic;
+
+
+signal break : std_logic;
+
+begin
+	poweronreset: roc port map (O => areset);
+
+
+
+	zpu: zpu_core port map (
+		clk => clk ,
+	 	areset => areset,
+	 	enable => enable,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+
+	ioMap: zpu_io port map (
+       	clk => clk,
+	 	areset => areset,
+		busy => io_busy,
+		writeEnable => io_mem_writeEnable,
+		readEnable => io_mem_readEnable,
+		write	=> mem_write,
+		read	=> io_mem_read,
+		addr => mem_addr(maxAddrBit downto minAddrBit)
+	);
+
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy;
+	
+	
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+	begin
+		mem_read <= (others => 'U');
+		if dram_ready='1' then
+			mem_read <= dram_mem_read;
+		end if;
+			 
+		if io_ready='1' then
+			mem_read <= (others => '0');
+			mem_read <= io_mem_read;
+		end if;
+	end process;
+
+	
+	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+	memoryControlSync:
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			enable <= '0';
+			io_reading <= '0';
+			dram_ready <= '0';
+		elsif (clk'event and clk = '1') then
+			enable <= '1';
+			io_reading <= io_busy or io_mem_readEnable; 
+			dram_ready<=dram_mem_readEnable;
+			
+		end if;
+	end process;
+
+	-- wiggle the clock @ 100MHz
+	clock : PROCESS
+	   begin
+   			clk <= '0';
+		   wait for 5 ns; 
+   			clk <= '1';
+		   wait for 5 ns; 
+	end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/example/simzpu.do b/zpu/hdl/example/simzpu.do
new file mode 100644
index 0000000..083187f
--- /dev/null
+++ b/zpu/hdl/example/simzpu.do
@@ -0,0 +1,29 @@
+# Xilinx WebPack modelsim script
+#
+# 1. Change directory to this source directory
+# cd C:/workspace/zpunew/hdl/example
+# "do zimzpu.do"
+
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config.vhd
+vcom -93 -explicit  ../zpu4/src/zpupkg.vhd
+vcom -93 -explicit  ../zpu4/src/txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  ../zpu4/src/zpu_core_small.vhd
+vcom -93 -explicit  helloworld.vhd
+vcom -93 -explicit  ../zpu4/src/timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  ../zpu4/src/trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 10 ms
diff --git a/zpu/hdl/example/zpu_config.vhd b/zpu/hdl/example/zpu_config.vhd
new file mode 100644
index 0000000..a59ac8e
--- /dev/null
+++ b/zpu/hdl/example/zpu_config.vhd
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+	-- generate trace output
+	constant	Generate_Trace		: boolean := true;
+	constant 	wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 27;
+	constant 	maxAddrBitBRAM		: integer := 16;
+		
+	-- start byte address of stack. 
+	-- point to top of RAM - 2*words
+	constant 	spStart				: std_logic_vector(maxAddrBitIncIO downto 0) := x"1fffff8"; 	
+end zpu_config;
diff --git a/zpu/hdl/index.html b/zpu/hdl/index.html
new file mode 100644
index 0000000..d3b4c1a
--- /dev/null
+++ b/zpu/hdl/index.html
@@ -0,0 +1,47 @@
+<html>
+<body>
+<h1>Getting started - FPGA </h1>
+The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART
+is a good place to start.
+<p>
+You'll find a working simulation script in hdl/example/simzpu.do.
+<p>
+When implementing the ZPU, copy the following files and modify them to your needs:
+<ol>
+    <li>hdl/example/zpu_config.vhd - set up RAM size here
+    <li>hdl/example/helloworld.vhd - dual port BRAM implementation. 
+</ol>
+Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is memory mapped(read/write) in the ZPU.
+<h2>Generating VHDL BRAM initialization </h2>
+
+<code>
+../install/bin/zpu-elf-objdump -O binary hello.elf hello.bin<br>
+java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin &gt;hello.bram<br>
+
+</code>
+<h2>Running example simulation</h2>
+The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt:
+<ol>
+<li>cd c:/&lt;installfolder&gt;/hdl/example
+<li>do zpusim.do
+</ol>
+<p>
+After running the hello world simulation (see zpusim.do), two files are written to the hdl/exmaple directory:
+<ol>
+<li>log.txt - contains the "Hello world!" text written to the debug channel/simplified UART.
+<li>trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking
+this file as input in order to verify that the HDL implementation matches the instruction set simulator. 
+When a mismatch is found, the GDB debugger will break. Very handy for debugging custom ZPU implementations. 
+</ol>  
+<h2>HDL Directories & files </h2>
+<ul>
+<li>example - contains example files & working ZPU. Start here.
+<li>wishbone - contains wishbone interface for the ZPU
+<li>zpu3 - if you are interested in developing ZPU cores and not only using them, then this directory contains various stuff of more or less historical interest.
+<li>zpu4 -  if you are interested in developing ZPU cores and not only using them, then this is the active development version. You'll also want to copy out the
+files you need from this folder to your own project.
+</ul>
+
+The HDL files need a bit of spit and polish!
+</body>
+</html>
diff --git a/zpu/hdl/wishbone/wishbone_pkg.vhd b/zpu/hdl/wishbone/wishbone_pkg.vhd
new file mode 100644
index 0000000..c3b0d9b
--- /dev/null
+++ b/zpu/hdl/wishbone/wishbone_pkg.vhd
@@ -0,0 +1,52 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package wishbone_pkg is
+
+	type wishbone_bus_in is record
+		adr			: std_logic_vector(31 downto 0); 
+		sel			: std_logic_vector(3 downto 0); 
+		we			: std_logic;
+		dat			: std_logic_vector(31 downto 0); 	-- Note! Data written with 'we'
+		cyc			: std_logic; 
+		stb			: std_logic;
+	end record;
+
+	type wishbone_bus_out is record
+		dat		: std_logic_vector(31 downto 0);
+		ack			: std_logic;
+	end record;
+	
+	type wishbone_bus is record
+		insig		: wishbone_bus_in;
+		outsig  	: wishbone_bus_out;
+	end record;
+
+	component atomic32_access is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from CPU interface
+			wb_16_i			: in wishbone_bus_in;
+			wb_16_o     	: out wishbone_bus_out;
+			-- Wishbone to FPGA registers and ethernet core
+			wb_32_i			: in wishbone_bus_out;
+			wb_32_o			: out wishbone_bus_in);
+	end component;
+	
+	component eth_access_corr is
+	port (	cpu_clk			: in std_logic;
+			areset			: in std_logic;
+	
+			-- Wishbone from Wishbone MUX
+			eth_raw_o		: out wishbone_bus_out;
+			eth_raw_i		: in wishbone_bus_in;
+			
+			-- Wishbone ethernet core
+			eth_slave_i 	: in wishbone_bus_out;
+			eth_slave_o		: out wishbone_bus_in);
+	end component;
+
+
+end wishbone_pkg;
diff --git a/zpu/hdl/wishbone/zpu_system.vhd b/zpu/hdl/wishbone/zpu_system.vhd
new file mode 100644
index 0000000..6e79370
--- /dev/null
+++ b/zpu/hdl/wishbone/zpu_system.vhd
@@ -0,0 +1,71 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all; 
+
+library work;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+use work.ic300pkg.all;
+
+entity zpu_system is
+	generic(
+			simulate		: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+
+			-- ZPU Control signals
+			enable			: in std_logic;
+			interrupt		: in std_logic;
+
+			zpu_status		: out std_logic_vector(63 downto 0);
+
+			-- wishbone interfaces
+			zpu_wb_i		: in wishbone_bus_out;
+			zpu_wb_o		: out wishbone_bus_in);
+end zpu_system;
+
+architecture behave of zpu_system is
+
+signal	mem_req					: std_logic;
+signal	mem_we 					: std_logic;
+signal	mem_ack 				: std_logic; 
+signal	mem_read 				: std_logic_vector(wordSize-1 downto 0);
+signal	mem_write 				: std_logic_vector(wordSize-1 downto 0);
+signal	out_mem_addr 			: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	mem_writeMask			: std_logic_vector(wordBytes-1 downto 0);
+
+
+begin
+
+	my_zpu_core:
+	zpu_core port map (
+    	clk 				=> cpu_clk, 
+		areset 				=> areset,
+	 	enable 				=> enable,
+	  	mem_req 			=> mem_req,
+	 	mem_we 				=> mem_we,
+	 	mem_ack 			=> mem_ack, 
+	 	mem_read 			=> mem_read,
+	 	mem_write 			=> mem_write,
+		out_mem_addr 		=> out_mem_addr,
+	 	mem_writeMask		=> mem_writeMask,
+	 	interrupt			=> interrupt,
+	 	zpu_status			=> zpu_status,
+	 	break				=> open);
+
+	my_zpu_wb_bridge:
+	zpu_wb_bridge port map (
+		clk 				=> cpu_clk,
+	 	areset 				=> areset,
+	  	mem_req 			=> mem_req,
+	 	mem_we 				=> mem_we,
+	 	mem_ack 			=> mem_ack, 
+	 	mem_read 			=> mem_read,
+	 	mem_write 			=> mem_write,
+		out_mem_addr 		=> out_mem_addr,
+	 	mem_writeMask		=> mem_writeMask,
+		zpu_wb_i			=> zpu_wb_i,
+		zpu_wb_o			=> zpu_wb_o);
+
+end behave;
diff --git a/zpu/hdl/wishbone/zpu_wb_bridge.vhd b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
new file mode 100644
index 0000000..4182f7a
--- /dev/null
+++ b/zpu/hdl/wishbone/zpu_wb_bridge.vhd
@@ -0,0 +1,49 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.phi_config.all;
+use work.wishbone_pkg.all;
+use work.zpupkg.all;
+use work.zpu_config.all;
+
+entity zpu_wb_bridge is
+	port (	-- Native ZPU interface
+ 			clk 				: in std_logic;
+	 		areset 				: in std_logic;
+
+	 		mem_req 			: in std_logic;
+	 		mem_we				: in std_logic;
+	 		mem_ack				: out std_logic; 
+	 		mem_read 			: out std_logic_vector(wordSize-1 downto 0);
+	 		mem_write 			: in std_logic_vector(wordSize-1 downto 0);
+			out_mem_addr 		: in std_logic_vector(maxAddrBitIncIO downto 0);
+	 		mem_writeMask		: in std_logic_vector(wordBytes-1 downto 0);
+			
+			-- Wishbone from ZPU
+			zpu_wb_i			: in wishbone_bus_out;
+			zpu_wb_o			: out wishbone_bus_in);
+
+end zpu_wb_bridge;
+
+architecture behave of zpu_wb_bridge is
+
+begin
+
+	mem_read <= zpu_wb_i.dat;
+	mem_ack <= zpu_wb_i.ack;
+	
+	zpu_wb_o.adr <= "000000" & out_mem_addr(27) & out_mem_addr(24 downto 0);
+	zpu_wb_o.dat <= mem_write;
+	zpu_wb_o.sel <= mem_writeMask;
+	zpu_wb_o.stb <= mem_req;
+	zpu_wb_o.cyc <= mem_req;
+	zpu_wb_o.we <= mem_we;
+
+end behave;
+
+			
+
+	
+
diff --git a/zpu/hdl/zpu3/src/.cvsignore b/zpu/hdl/zpu3/src/.cvsignore
new file mode 100644
index 0000000..760be11
--- /dev/null
+++ b/zpu/hdl/zpu3/src/.cvsignore
@@ -0,0 +1 @@
+xilinx_device_details.xml
diff --git a/zpu/hdl/zpu3/src/build.xml b/zpu/hdl/zpu3/src/build.xml
new file mode 100644
index 0000000..e1b268a
--- /dev/null
+++ b/zpu/hdl/zpu3/src/build.xml
@@ -0,0 +1,114 @@
+<!--
+
+FIX!!! start /b /wait /belownormal does not propagate return code..
+-->
+<project name="ZPU3" default="all" basedir=".">
+	<property name="chipname" value="ic300"/>
+	<property name="packagetype" value="xc3s400-ft256-4"/>
+		
+		  
+	<description>eCosBoard firmware build file</description>
+
+	<target name="setuplibs">
+		<!-- N/A yet
+		<copy todir="../src">
+			<fileset dir="..\fpgalib\" includes="foo_top.ngc" />
+		</copy>
+		-->
+	</target>
+
+	<target name="setup">
+		<mkdir dir="..\reports"/>
+		<mkdir dir="..\syn"/>
+		<mkdir dir="..\ngo"/>
+		<mkdir dir="..\output"/>
+		<mkdir dir="..\tmp"/>
+		<mkdir dir="..\xst"/>
+	</target>
+
+	<target name="clean">
+		<delete dir="..\reports"/>
+		<delete dir="..\syn"/>
+		<delete dir="..\ngo"/>
+		<delete dir="..\output"/>
+		<delete dir="..\tmp"/>
+		<delete dir="..\xst"/>
+	</target>
+
+	<target name="synthesis" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c xst -intstyle ise -ifn xmake.xst -ofn ..\reports\1_synthesis.txt"/>
+		</exec>
+	</target>
+
+
+	<target name="translate" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c ngdbuild -intstyle ise -dd ..\ngo -uc ${chipname}.ucf -a  -p ${packagetype} ..\syn\${chipname}.ngc ..\ngo\${chipname}.ngd"/>
+		</exec>
+		<move tofile="..\reports\2_translate.txt">
+			<fileset dir="..\ngo" includes="${chipname}.bld"/>
+		</move>
+	</target>
+
+	<target name="mapping" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c map -intstyle ise -p ${packagetype} -ol high -timing -detail -cm area -ignore_keep_hierarchy -pr b -k 6 -r -c 100 -tx off -o ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ngd ..\ngo\${chipname}.pcf"/>
+		</exec>
+		<move tofile="..\reports\3_mapping.txt">
+			<fileset dir="..\ngo" includes="${chipname}_map.mrp"/>
+		</move>
+	</target>
+
+
+	<target name="placeandroute" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c par -w -intstyle ise -ol high -t 1 ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ncd ..\ngo\${chipname}.pcf"/>
+		</exec>
+		<move tofile="..\reports\4_placeandroute.txt">
+			<fileset dir="..\ngo" includes="${chipname}.par"/>
+		</move>
+		<move tofile="..\reports\5_pads.txt">
+			<fileset dir="..\ngo" includes="${chipname}_pad.txt"/>
+		</move>
+	</target>
+
+
+	<target name="gentime" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c trce -intstyle ise -v 3 -l 3 -a -u 100 ..\ngo\${chipname}.ncd -o ..\reports\timing.twr ..\ngo\${chipname}.pcf"/>
+		</exec>
+		<delete file="..\reports\6_timing.txt"/>
+		<move tofile="..\reports\6_timing.txt">
+			<fileset dir="..\reports" includes="timing.twr"/>
+		</move>
+	</target>
+
+
+	<target name="genbit" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c bitgen -intstyle ise -w -f ${chipname}.bitgen ..\ngo\${chipname}.ncd"/>
+		</exec>
+		<move tofile="..\reports\7_bitgen.txt">
+			<fileset dir="..\ngo" includes="${chipname}.bgn"/>
+		</move>
+	</target>
+
+	<target name="copyfiles" depends="setup">
+		<copy todir="../output">
+			<fileset dir="..\ngo" includes="${chipname}.bin"/>
+		</copy>
+		<!--
+		<copy tofile="${workspace_loc}\firmware\board\xeddvifpgadata.rawdata">
+			<fileset dir="..\ngo" includes="${chipname}.bin"/>
+		</copy>
+		-->
+	</target>
+
+
+	<target name="all" depends="setuplibs,synthesis,translate,mapping,placeandroute,gentime,genbit,copyfiles">
+
+	</target>
+
+
+</project>
\ No newline at end of file
diff --git a/zpu/hdl/zpu3/src/clocks.vhd b/zpu/hdl/zpu3/src/clocks.vhd
new file mode 100644
index 0000000..a352b3c
--- /dev/null
+++ b/zpu/hdl/zpu3/src/clocks.vhd
@@ -0,0 +1,246 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clocks is
+	port (	areset			: in std_logic;
+			cpu_clk_p		: in std_logic;
+			sdr_clk_fb_p	: in std_logic;
+			cpu_clk			: out std_logic;
+			cpu_clk_2x		: out std_logic;
+			cpu_clk_4x		: out std_logic;
+			ddr_in_clk		: out std_logic;
+			ddr_in_clk_2x	: out std_logic;
+			locked			: out std_logic_vector(2 downto 0));
+end clocks;
+
+architecture behave of clocks is
+
+signal	low					: std_logic;
+
+signal	cpu_clk_in			: std_logic;
+signal	sdr_clk_fb_in		: std_logic;
+
+signal	dcm_cpu1			: std_logic;
+signal	dcm_cpu2			: std_logic;
+signal	dcm_cpu2_dum		: std_logic;
+signal	dcm_cpu4			: std_logic;
+signal	dcm_ddr2			: std_logic;
+signal	dcm_ddr2_2x			: std_logic;
+
+signal	cpu_clk_int			: std_logic;
+signal	cpu_clk_2x_int		: std_logic;
+signal	cpu_clk_2x_dum_int	: std_logic;
+signal	cpu_clk_4x_int		: std_logic;
+signal	ddr_in_clk_int		: std_logic;
+signal	ddr_in_clk_2x_int	: std_logic;
+
+signal	dcm1_locked_del		: std_logic;
+signal	dcm2_locked_del		: std_logic;
+signal	dcm2_reset			: std_logic;
+signal	dcm3_reset			: std_logic;
+
+signal	locked_int			: std_logic_vector(2 downto 0);
+signal	del_addr			: std_logic_vector(3 downto 0);
+
+begin
+
+	low <= '0';				
+	del_addr <= "1111";
+	
+	cpu_clk <= cpu_clk_int;
+	cpu_clk_2x <= cpu_clk_2x_int;
+	cpu_clk_4x <= cpu_clk_4x_int;
+	ddr_in_clk <= ddr_in_clk_int;
+	ddr_in_clk_2x <= ddr_in_clk_2x_int;
+	locked <= locked_int;
+	
+
+   	CPU_IBUFG: 
+   	IBUFG port map (
+      	O => cpu_clk_in,
+      	I => cpu_clk_p);
+	
+   	SDR_FB_IBUFG: 
+   	IBUFG port map (
+      	O => sdr_clk_fb_in,
+      	I => sdr_clk_fb_p);
+      	
+   dcm2_rst: 
+   SRL16 generic map (
+      	INIT => X"0000")
+   port map (
+      	Q => dcm1_locked_del,
+      	A0 => del_addr(0),
+      	A1 => del_addr(1),
+      	A2 => del_addr(2),
+      	A3 => del_addr(3),
+      	CLK => cpu_clk_int,
+      	D => locked_int(0));
+      	
+	dcm2_reset <= not(dcm1_locked_del);      	
+	
+   dcm3_rst: 
+   SRL16 generic map (
+      	INIT => X"0000")
+   port map (
+      	Q => dcm2_locked_del,
+      	A0 => del_addr(0),
+      	A1 => del_addr(1),
+      	A2 => del_addr(2),
+      	A3 => del_addr(3),
+      	CLK => cpu_clk_int,
+      	D => locked_int(1));
+      	
+	dcm3_reset <= not(dcm2_locked_del);      	
+	
+   	cpu1_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 15.625,          --  Specify period of input clock
+      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_cpu1,   -- 0 degree DCM CLK ouptput
+      	CLK180 => open, 	-- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_cpu2, 	-- 2X DCM CLK output
+      	CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(0), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => cpu_clk_int,   -- DCM clock feedback
+      	CLKIN => cpu_clk_in,   -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => areset);     -- DCM asynchronous reset input
+   
+   	cpu2_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
+      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_cpu2_dum,     	-- 0 degree DCM CLK ouptput
+      	CLK180 => open,		 -- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_cpu4,  -- 2X DCM CLK output
+      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(1), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => cpu_clk_2x_dum_int,   -- DCM clock feedback
+      	CLKIN => cpu_clk_2x_int,   -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => dcm2_reset);     -- DCM asynchronous reset input
+   
+   	ddr_read_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
+     	CLKOUT_PHASE_SHIFT => "FIXED", --  Specify phase shift of NONE, FIXED or VARIABLE
+--      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 103,        --  Amount of fixed phase shift from -255 to 255
+--      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_ddr2,     	-- 0 degree DCM CLK ouptput
+      	CLK180 => open,		 -- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_ddr2_2x,  -- 2X DCM CLK output
+      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(2), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => ddr_in_clk_int,   -- DCM clock feedback
+      	CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => dcm3_reset);     -- DCM asynchronous reset input
+   
+   	cpu1:
+	BUFG port map (
+		I => dcm_cpu1,
+		O => cpu_clk_int);
+		
+   	cpu2:
+	BUFG port map (
+		I => dcm_cpu2,
+		O => cpu_clk_2x_int);
+		
+   	cpu2_dum:
+	BUFG port map (
+		I => dcm_cpu2_dum,
+		O => cpu_clk_2x_dum_int);
+		
+   	cpu4:
+	BUFG port map (
+		I => dcm_cpu4,
+		O => cpu_clk_4x_int);
+		
+   	ddr_clk:
+	BUFG port map (
+		I => dcm_ddr2,
+		O => ddr_in_clk_int);
+
+   	ddr_clk_2x:
+	BUFG port map (
+		I => dcm_ddr2_2x,
+		O => ddr_in_clk_2x_int);
+
+end behave;
\ No newline at end of file
diff --git a/zpu/hdl/zpu3/src/ddr_bridge.vhd b/zpu/hdl/zpu3/src/ddr_bridge.vhd
new file mode 100644
index 0000000..7dece76
--- /dev/null
+++ b/zpu/hdl/zpu3/src/ddr_bridge.vhd
@@ -0,0 +1,203 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library zylin;
+use zylin.ddr.all;
+
+library work;
+use work.phi_config.all;
+
+entity ddr_bridge is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_clk_4x		: in std_logic;
+			ddr_in_clk		: in std_logic;
+			ddr_in_clk_2x	: in std_logic;
+
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_dout		: inout std_logic_vector(15 downto 0);
+			
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
+end ddr_bridge;
+
+architecture behave of ddr_bridge is
+
+signal	refresh_en			: std_logic;
+signal	ddr_command_we		: std_logic;
+signal	ddr_command			: std_logic_vector(15 downto 0);
+
+signal	ddr_req				: std_logic;
+signal	ddr_req_adr			: std_logic_vector(23 downto 1);
+signal	ddr_rd_wr_n			: std_logic;
+signal	ddr_req_len			: std_logic;
+
+signal	ddr_read_en			: std_logic;
+signal	ddr_write_en		: std_logic;
+signal	ddr_data_read		: std_logic_vector(31 downto 0);
+signal	ddr_data_write		: std_logic_vector(35 downto 0);
+
+signal	ddr_read_smp		: std_logic_vector(31 downto 0);
+signal	ddr_read_delay		: std_logic_vector(15 downto 0);
+
+signal	ddr_write_smp		: std_logic_vector(15 downto 0);
+signal	ddr_addr_smp		: std_logic_vector(15 downto 0);
+
+signal	ddr_req_type_smp	: std_logic;
+signal	ddr_req_on			: std_logic;
+signal	ddr_req_off			: std_logic;
+signal	ddr_req_int			: std_logic;
+
+constant Sim_Delay			: time := 1.0 ns;
+
+begin
+
+	ddr_req_len <= '0';
+	ddr_data_write <= "0000" & ddr_write_smp & ddr_write_smp;
+	ddr_req_adr <= "0000000" & ddr_addr_smp;
+	ddr_rd_wr_n	<= ddr_req_type_smp;
+	ddr_req <= ddr_req_int;
+
+	process(cpu_clk, areset)	-- CPU writeable registers
+	begin
+		if areset = '1' then
+			refresh_en <= '0';
+			ddr_command_we <= '0';
+			ddr_command <= "0000000000000000";
+			ddr_write_smp <= "0000000000000000";
+			ddr_req_type_smp <= '0';
+			ddr_req_on <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+
+			if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Ctrl_Reg_Addr then
+				refresh_en <= cpu_din(0);
+			else
+				refresh_en <= refresh_en;
+			end if;
+			
+			if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Mode_Reg_Addr then
+				ddr_command <= cpu_din;
+				ddr_command_we <= '1';
+			else
+				ddr_command <= ddr_command;
+				ddr_command_we <= '0';
+			end if;
+			
+			if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr then
+				ddr_write_smp <= cpu_din;
+			else
+				ddr_write_smp <= ddr_write_smp;
+			end if;
+			
+			if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Addr_Reg_Addr then
+				ddr_addr_smp <= cpu_din;
+			else
+				ddr_addr_smp <= ddr_addr_smp;
+			end if;
+			
+			if cpu_we(0) = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Req_Reg_Addr then
+				ddr_req_type_smp <= cpu_din(0);
+				ddr_req_on <= '1';
+			else
+				ddr_req_type_smp <= ddr_req_type_smp;
+				ddr_req_on <= '0';
+			end if;
+			
+		end if;
+	end process;
+	
+	-- CPU readable registers
+	cpu_dout <= ddr_read_delay when (cpu_re = '1' and cpu_a(19 downto 17) = Fpga_DDR_Ctrl_Base and cpu_a(3 downto 1) = DDR_Data_Reg_Addr) else "ZZZZZZZZZZZZZZZZ";
+	
+	-- Capture data read from DDR
+	process(cpu_clk_2x, areset)
+	begin
+		if areset = '1' then
+			ddr_read_smp <= (others => '0');
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			if ddr_read_en = '1' then
+				ddr_read_smp <= ddr_data_read after Sim_Delay;
+			else
+				ddr_read_smp <= ddr_read_smp after Sim_Delay;
+			end if;
+		end if;
+	end process;
+	
+	-- Move captured data from DDR to cpu_clk domain (for better routing timing)
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			ddr_read_delay <= "0000000000000000";
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			ddr_read_delay <= ddr_read_smp(15 downto 0);
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)
+	begin
+		if areset = '1' then
+			ddr_req_int <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			if ddr_req_on = '1' then
+				ddr_req_int <= '1' after Sim_Delay;
+			elsif ddr_read_en = '1' or ddr_write_en = '1' then
+				ddr_req_int <= '0' after Sim_Delay;
+			else
+				ddr_req_int <= ddr_req_int after Sim_Delay;
+			end if;
+		end if;
+	end process;
+	
+
+	ddr_interface:
+	ddr_top port map(
+		areset => areset,
+		cpu_clk => cpu_clk,
+		cpu_clk_2x => cpu_clk_2x,
+		cpu_clk_4x => cpu_clk_4x,
+		ddr_in_clk => ddr_in_clk,
+		ddr_in_clk_2x => ddr_in_clk_2x,
+		ddr_command => ddr_command,
+		ddr_command_we => ddr_command_we,
+		refresh_en => refresh_en,
+		ddr_data_read => ddr_data_read,
+		ddr_data_write => ddr_data_write,
+		ddr_req => ddr_req,
+		ddr_req_adr => ddr_req_adr,
+		ddr_rd_wr_n => ddr_rd_wr_n,
+		ddr_req_len => ddr_req_len,
+		ddr_read_en => ddr_read_en,
+		ddr_write_en => ddr_write_en,
+	    sdr_clk_p => sdr_clk_p,
+	    sdr_clk_n_p => sdr_clk_n_p,
+	    cke_q_p => cke_q_p,
+	    cs_qn_p => cs_qn_p,
+	    ras_qn_p => ras_qn_p,
+	    cas_qn_p => cas_qn_p,
+	    we_qn_p => we_qn_p,
+	    dm_q_p => dm_q_p,
+	    dqs_q_p => dqs_q_p,
+	    ba_q_p => ba_q_p,
+	    sdr_a_p => sdr_a_p,
+	    sdr_d_p => sdr_d_p);
+
+
+end behave;
diff --git a/zpu/hdl/zpu3/src/dmips_ram.vhd b/zpu/hdl/zpu3/src/dmips_ram.vhd
new file mode 100644
index 0000000..f472653
--- /dev/null
+++ b/zpu/hdl/zpu3/src/dmips_ram.vhd
@@ -0,0 +1,3824 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"800b0b0b",
+1 => x"0b0b8070",
+2 => x"0b0b80e5",
+3 => x"d00c3a0b",
+4 => x"0b0bbed7",
+5 => x"04000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0bbfa72d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"0b0b0400",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"530b0b51",
+38 => x"04000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"0b0b5104",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"530b0b51",
+55 => x"04000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"0b0b5104",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c6040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a530b0b",
+82 => x"51040000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"0607530b",
+101 => x"0b510400",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"7171530b",
+105 => x"0b510406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"0b0b5104",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"530b0b51",
+125 => x"04000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"520b0b04",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"0505530b",
+138 => x"0b510400",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07530b0b",
+147 => x"51040000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"0b0b0400",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80e5",
+162 => x"bc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88ac0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0ba3",
+171 => x"fa2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0ba4",
+179 => x"ca2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70540b0b",
+188 => x"71067309",
+189 => x"727405ff",
+190 => x"05060751",
+191 => x"51510400",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"0570540b",
+196 => x"0b710673",
+197 => x"09727405",
+198 => x"ff050607",
+199 => x"51515104",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80e5cc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"0b0b0400",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"0b0b0400",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"0571530b",
+250 => x"0b510400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"84803f80",
+257 => x"cef23f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"0b0b5104",
+267 => x"7381ff06",
+268 => x"73830609",
+269 => x"81058305",
+270 => x"1010102b",
+271 => x"0772fc06",
+272 => x"0c515104",
+273 => x"3c047272",
+274 => x"80728106",
+275 => x"ff050972",
+276 => x"06057110",
+277 => x"520b0b72",
+278 => x"0a100a53",
+279 => x"0b0b72e9",
+280 => x"38515153",
+281 => x"0b0b5104",
+282 => x"70700b0b",
+283 => x"80f5c008",
+284 => x"520b0b84",
+285 => x"0b720508",
+286 => x"70810651",
+287 => x"510b0b70",
+288 => x"f2387108",
+289 => x"81ff0680",
+290 => x"0c505004",
+291 => x"70700b0b",
+292 => x"80f5c008",
+293 => x"520b0b84",
+294 => x"0b720508",
+295 => x"700a100a",
+296 => x"70810651",
+297 => x"51510b0b",
+298 => x"70ed3873",
+299 => x"720c5050",
+300 => x"0480e5cc",
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+3382 => x"000034d0",
+3383 => x"000034d0",
+3384 => x"000034d8",
+3385 => x"000034d8",
+3386 => x"000034e0",
+3387 => x"000034e0",
+3388 => x"000034e8",
+3389 => x"000034e8",
+3390 => x"000034f0",
+3391 => x"000034f0",
+3392 => x"000034f8",
+3393 => x"000034f8",
+3394 => x"00003500",
+3395 => x"00003500",
+3396 => x"00003508",
+3397 => x"00003508",
+3398 => x"00003510",
+3399 => x"00003510",
+3400 => x"00003518",
+3401 => x"00003518",
+3402 => x"00003520",
+3403 => x"00003520",
+3404 => x"00003528",
+3405 => x"00003528",
+3406 => x"00003530",
+3407 => x"00003530",
+3408 => x"00003538",
+3409 => x"00003538",
+3410 => x"00003540",
+3411 => x"00003540",
+3412 => x"00003548",
+3413 => x"00003548",
+3414 => x"00003550",
+3415 => x"00003550",
+3416 => x"00003558",
+3417 => x"00003558",
+3418 => x"00003560",
+3419 => x"00003560",
+3420 => x"00003568",
+3421 => x"00003568",
+3422 => x"00003570",
+3423 => x"00003570",
+3424 => x"00003578",
+3425 => x"00003578",
+3426 => x"00003580",
+3427 => x"00003580",
+3428 => x"00003588",
+3429 => x"00003588",
+3430 => x"00003590",
+3431 => x"00003590",
+3432 => x"00003598",
+3433 => x"00003598",
+3434 => x"000035a0",
+3435 => x"000035a0",
+3436 => x"000035a8",
+3437 => x"000035a8",
+3438 => x"000035b0",
+3439 => x"000035b0",
+3440 => x"000035b8",
+3441 => x"000035b8",
+3442 => x"000035c0",
+3443 => x"000035c0",
+3444 => x"000035c8",
+3445 => x"000035c8",
+3446 => x"000035d0",
+3447 => x"000035d0",
+3448 => x"000035d8",
+3449 => x"000035d8",
+3450 => x"000035e0",
+3451 => x"000035e0",
+3452 => x"000035e8",
+3453 => x"000035e8",
+3454 => x"000035f0",
+3455 => x"000035f0",
+3456 => x"000035f8",
+3457 => x"000035f8",
+3458 => x"00003600",
+3459 => x"00003600",
+3460 => x"00003608",
+3461 => x"00003608",
+3462 => x"00003610",
+3463 => x"00003610",
+3464 => x"00003618",
+3465 => x"00003618",
+3466 => x"00003620",
+3467 => x"00003620",
+3468 => x"00003628",
+3469 => x"00003628",
+3470 => x"00003630",
+3471 => x"00003630",
+3472 => x"00003638",
+3473 => x"00003638",
+3474 => x"00003640",
+3475 => x"00003640",
+3476 => x"00003648",
+3477 => x"00003648",
+3478 => x"00003650",
+3479 => x"00003650",
+3480 => x"00003658",
+3481 => x"00003658",
+3482 => x"00003660",
+3483 => x"00003660",
+3484 => x"00003668",
+3485 => x"00003668",
+3486 => x"00003670",
+3487 => x"00003670",
+3488 => x"00003678",
+3489 => x"00003678",
+3490 => x"00003680",
+3491 => x"00003680",
+3492 => x"00003688",
+3493 => x"00003688",
+3494 => x"00003690",
+3495 => x"00003690",
+3496 => x"00003698",
+3497 => x"00003698",
+3498 => x"000036a0",
+3499 => x"000036a0",
+3500 => x"000036a8",
+3501 => x"000036a8",
+3502 => x"000036b0",
+3503 => x"000036b0",
+3504 => x"000036b8",
+3505 => x"000036b8",
+3506 => x"000036c0",
+3507 => x"000036c0",
+3508 => x"000036c8",
+3509 => x"000036c8",
+3510 => x"000036d0",
+3511 => x"000036d0",
+3512 => x"000036d8",
+3513 => x"000036d8",
+3514 => x"000036e0",
+3515 => x"000036e0",
+3516 => x"000036e8",
+3517 => x"000036e8",
+3518 => x"000036f0",
+3519 => x"000036f0",
+3520 => x"000036f8",
+3521 => x"000036f8",
+3522 => x"00003700",
+3523 => x"00003700",
+3524 => x"00003708",
+3525 => x"00003708",
+3526 => x"00003710",
+3527 => x"00003710",
+3528 => x"00003718",
+3529 => x"00003718",
+3530 => x"0000372c",
+3531 => x"00000000",
+3532 => x"00003994",
+3533 => x"000039f0",
+3534 => x"00003a4c",
+3535 => x"00000000",
+3536 => x"00000000",
+3537 => x"00000000",
+3538 => x"00000000",
+3539 => x"00000000",
+3540 => x"00000000",
+3541 => x"00000000",
+3542 => x"00000000",
+3543 => x"00000000",
+3544 => x"000031ac",
+3545 => x"00000000",
+3546 => x"00000000",
+3547 => x"00000000",
+3548 => x"00000000",
+3549 => x"00000000",
+3550 => x"00000000",
+3551 => x"00000000",
+3552 => x"00000000",
+3553 => x"00000000",
+3554 => x"00000000",
+3555 => x"00000000",
+3556 => x"00000000",
+3557 => x"00000000",
+3558 => x"00000000",
+3559 => x"00000000",
+3560 => x"00000000",
+3561 => x"00000000",
+3562 => x"00000000",
+3563 => x"00000000",
+3564 => x"00000000",
+3565 => x"00000000",
+3566 => x"00000000",
+3567 => x"00000000",
+3568 => x"00000000",
+3569 => x"00000000",
+3570 => x"00000000",
+3571 => x"00000000",
+3572 => x"00000000",
+3573 => x"00000001",
+3574 => x"330eabcd",
+3575 => x"1234e66d",
+3576 => x"deec0005",
+3577 => x"000b0000",
+3578 => x"00000000",
+3579 => x"00000000",
+3580 => x"00000000",
+3581 => x"00000000",
+3582 => x"00000000",
+3583 => x"00000000",
+3584 => x"00000000",
+3585 => x"00000000",
+3586 => x"00000000",
+3587 => x"00000000",
+3588 => x"00000000",
+3589 => x"00000000",
+3590 => x"00000000",
+3591 => x"00000000",
+3592 => x"00000000",
+3593 => x"00000000",
+3594 => x"00000000",
+3595 => x"00000000",
+3596 => x"00000000",
+3597 => x"00000000",
+3598 => x"00000000",
+3599 => x"00000000",
+3600 => x"00000000",
+3601 => x"00000000",
+3602 => x"00000000",
+3603 => x"00000000",
+3604 => x"00000000",
+3605 => x"00000000",
+3606 => x"00000000",
+3607 => x"00000000",
+3608 => x"00000000",
+3609 => x"00000000",
+3610 => x"00000000",
+3611 => x"00000000",
+3612 => x"00000000",
+3613 => x"00000000",
+3614 => x"00000000",
+3615 => x"00000000",
+3616 => x"00000000",
+3617 => x"00000000",
+3618 => x"00000000",
+3619 => x"00000000",
+3620 => x"00000000",
+3621 => x"00000000",
+3622 => x"00000000",
+3623 => x"00000000",
+3624 => x"00000000",
+3625 => x"00000000",
+3626 => x"00000000",
+3627 => x"00000000",
+3628 => x"00000000",
+3629 => x"00000000",
+3630 => x"00000000",
+3631 => x"00000000",
+3632 => x"00000000",
+3633 => x"00000000",
+3634 => x"00000000",
+3635 => x"00000000",
+3636 => x"00000000",
+3637 => x"00000000",
+3638 => x"00000000",
+3639 => x"00000000",
+3640 => x"00000000",
+3641 => x"00000000",
+3642 => x"00000000",
+3643 => x"00000000",
+3644 => x"00000000",
+3645 => x"00000000",
+3646 => x"00000000",
+3647 => x"00000000",
+3648 => x"00000000",
+3649 => x"00000000",
+3650 => x"00000000",
+3651 => x"00000000",
+3652 => x"00000000",
+3653 => x"00000000",
+3654 => x"00000000",
+3655 => x"00000000",
+3656 => x"00000000",
+3657 => x"00000000",
+3658 => x"00000000",
+3659 => x"00000000",
+3660 => x"00000000",
+3661 => x"00000000",
+3662 => x"00000000",
+3663 => x"00000000",
+3664 => x"00000000",
+3665 => x"00000000",
+3666 => x"00000000",
+3667 => x"00000000",
+3668 => x"00000000",
+3669 => x"00000000",
+3670 => x"00000000",
+3671 => x"00000000",
+3672 => x"00000000",
+3673 => x"00000000",
+3674 => x"00000000",
+3675 => x"00000000",
+3676 => x"00000000",
+3677 => x"00000000",
+3678 => x"00000000",
+3679 => x"00000000",
+3680 => x"00000000",
+3681 => x"00000000",
+3682 => x"00000000",
+3683 => x"00000000",
+3684 => x"00000000",
+3685 => x"00000000",
+3686 => x"00000000",
+3687 => x"00000000",
+3688 => x"00000000",
+3689 => x"00000000",
+3690 => x"00000000",
+3691 => x"00000000",
+3692 => x"00000000",
+3693 => x"00000000",
+3694 => x"00000000",
+3695 => x"00000000",
+3696 => x"00000000",
+3697 => x"00000000",
+3698 => x"00000000",
+3699 => x"00000000",
+3700 => x"00000000",
+3701 => x"00000000",
+3702 => x"00000000",
+3703 => x"00000000",
+3704 => x"00000000",
+3705 => x"00000000",
+3706 => x"00000000",
+3707 => x"00000000",
+3708 => x"00000000",
+3709 => x"00000000",
+3710 => x"00000000",
+3711 => x"00000000",
+3712 => x"00000000",
+3713 => x"00000000",
+3714 => x"00000000",
+3715 => x"00000000",
+3716 => x"00000000",
+3717 => x"00000000",
+3718 => x"00000000",
+3719 => x"00000000",
+3720 => x"00000000",
+3721 => x"00000000",
+3722 => x"00000000",
+3723 => x"00000000",
+3724 => x"00000000",
+3725 => x"00000000",
+3726 => x"00000000",
+3727 => x"00000000",
+3728 => x"00000000",
+3729 => x"00000000",
+3730 => x"00000000",
+3731 => x"00000000",
+3732 => x"00000000",
+3733 => x"00000000",
+3734 => x"00000000",
+3735 => x"00000000",
+3736 => x"00000000",
+3737 => x"00000000",
+3738 => x"00000000",
+3739 => x"00000000",
+3740 => x"00000000",
+3741 => x"00000000",
+3742 => x"00000000",
+3743 => x"00000000",
+3744 => x"00000000",
+3745 => x"00000000",
+3746 => x"00000000",
+3747 => x"00000000",
+3748 => x"00000000",
+3749 => x"00000000",
+3750 => x"00000000",
+3751 => x"00000000",
+3752 => x"00000000",
+3753 => x"00000000",
+3754 => x"000031b0",
+3755 => x"ffffffff",
+3756 => x"00000000",
+3757 => x"ffffffff",
+3758 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(conv_integer(memAAddr)) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(conv_integer(memAAddr));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(conv_integer(memBAddr)) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(conv_integer(memBAddr));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/dualport_ram.vhd b/zpu/hdl/zpu3/src/dualport_ram.vhd
new file mode 100644
index 0000000..54380ce
--- /dev/null
+++ b/zpu/hdl/zpu3/src/dualport_ram.vhd
@@ -0,0 +1,4996 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"800b0b0b",
+1 => x"0b0b8070",
+2 => x"0b0b818a",
+3 => x"880c3a0b",
+4 => x"0b80fae8",
+5 => x"04000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80fbba2d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"530b0b51",
+38 => x"04000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"0b0b5104",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"530b0b51",
+55 => x"04000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"0b0b5104",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"72728072",
+73 => x"8106ff05",
+74 => x"09720605",
+75 => x"71105272",
+76 => x"0a100a53",
+77 => x"0b0b72eb",
+78 => x"38515153",
+79 => x"0b0b5104",
+80 => x"720a722b",
+81 => x"0a530b0b",
+82 => x"51040000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"0607530b",
+101 => x"0b510400",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"7171530b",
+105 => x"0b510406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"0b0b5104",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"530b0b51",
+125 => x"04000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"0505530b",
+138 => x"0b510400",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07530b0b",
+147 => x"51040000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b8189",
+162 => x"f4738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88ac0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8f",
+171 => x"e42d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b91",
+179 => x"9c2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70540b0b",
+188 => x"71067309",
+189 => x"727405ff",
+190 => x"05060751",
+191 => x"51510400",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"0570540b",
+196 => x"0b710673",
+197 => x"09727405",
+198 => x"ff050607",
+199 => x"51515104",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"818a840c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"0571530b",
+250 => x"0b510400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"83cd3f80",
+257 => x"fd803f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"0b0b5104",
+267 => x"7381ff06",
+268 => x"73830609",
+269 => x"81058305",
+270 => x"1010102b",
+271 => x"0772fc06",
+272 => x"0c515104",
+273 => x"3c047070",
+274 => x"0b0b819a",
+275 => x"90085284",
+276 => x"0b720508",
+277 => x"70810651",
+278 => x"510b0b70",
+279 => x"f2387108",
+280 => x"81ff0680",
+281 => x"0c505004",
+282 => x"70700b0b",
+283 => x"819a9008",
+284 => x"52840b72",
+285 => x"0508700a",
+286 => x"100a7081",
+287 => x"06515151",
+288 => x"0b0b70ed",
+289 => x"3873720c",
+290 => x"50500481",
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+4641 => x"00000000",
+4642 => x"00000000",
+4643 => x"00000000",
+4644 => x"00000000",
+4645 => x"43000000",
+4646 => x"00000000",
+4647 => x"00000000",
+4648 => x"00000000",
+4649 => x"00000000",
+4650 => x"00000000",
+4651 => x"00000001",
+4652 => x"000044dc",
+4653 => x"00000000",
+4654 => x"00000000",
+4655 => x"00000000",
+4656 => x"00000000",
+4657 => x"00000000",
+4658 => x"00000000",
+4659 => x"00000000",
+4660 => x"00000000",
+4661 => x"00000000",
+4662 => x"00000000",
+4663 => x"00000000",
+4664 => x"00000000",
+4665 => x"ffffffff",
+4666 => x"00000000",
+4667 => x"00020000",
+4668 => x"00000000",
+4669 => x"00000000",
+4670 => x"000048f0",
+4671 => x"000048f0",
+4672 => x"000048f8",
+4673 => x"000048f8",
+4674 => x"00004900",
+4675 => x"00004900",
+4676 => x"00004908",
+4677 => x"00004908",
+4678 => x"00004910",
+4679 => x"00004910",
+4680 => x"00004918",
+4681 => x"00004918",
+4682 => x"00004920",
+4683 => x"00004920",
+4684 => x"00004928",
+4685 => x"00004928",
+4686 => x"00004930",
+4687 => x"00004930",
+4688 => x"00004938",
+4689 => x"00004938",
+4690 => x"00004940",
+4691 => x"00004940",
+4692 => x"00004948",
+4693 => x"00004948",
+4694 => x"00004950",
+4695 => x"00004950",
+4696 => x"00004958",
+4697 => x"00004958",
+4698 => x"00004960",
+4699 => x"00004960",
+4700 => x"00004968",
+4701 => x"00004968",
+4702 => x"00004970",
+4703 => x"00004970",
+4704 => x"00004978",
+4705 => x"00004978",
+4706 => x"00004980",
+4707 => x"00004980",
+4708 => x"00004988",
+4709 => x"00004988",
+4710 => x"00004990",
+4711 => x"00004990",
+4712 => x"00004998",
+4713 => x"00004998",
+4714 => x"000049a0",
+4715 => x"000049a0",
+4716 => x"000049a8",
+4717 => x"000049a8",
+4718 => x"000049b0",
+4719 => x"000049b0",
+4720 => x"000049b8",
+4721 => x"000049b8",
+4722 => x"000049c0",
+4723 => x"000049c0",
+4724 => x"000049c8",
+4725 => x"000049c8",
+4726 => x"000049d0",
+4727 => x"000049d0",
+4728 => x"000049d8",
+4729 => x"000049d8",
+4730 => x"000049e0",
+4731 => x"000049e0",
+4732 => x"000049e8",
+4733 => x"000049e8",
+4734 => x"000049f0",
+4735 => x"000049f0",
+4736 => x"000049f8",
+4737 => x"000049f8",
+4738 => x"00004a00",
+4739 => x"00004a00",
+4740 => x"00004a08",
+4741 => x"00004a08",
+4742 => x"00004a10",
+4743 => x"00004a10",
+4744 => x"00004a18",
+4745 => x"00004a18",
+4746 => x"00004a20",
+4747 => x"00004a20",
+4748 => x"00004a28",
+4749 => x"00004a28",
+4750 => x"00004a30",
+4751 => x"00004a30",
+4752 => x"00004a38",
+4753 => x"00004a38",
+4754 => x"00004a40",
+4755 => x"00004a40",
+4756 => x"00004a48",
+4757 => x"00004a48",
+4758 => x"00004a50",
+4759 => x"00004a50",
+4760 => x"00004a58",
+4761 => x"00004a58",
+4762 => x"00004a60",
+4763 => x"00004a60",
+4764 => x"00004a68",
+4765 => x"00004a68",
+4766 => x"00004a70",
+4767 => x"00004a70",
+4768 => x"00004a78",
+4769 => x"00004a78",
+4770 => x"00004a80",
+4771 => x"00004a80",
+4772 => x"00004a88",
+4773 => x"00004a88",
+4774 => x"00004a90",
+4775 => x"00004a90",
+4776 => x"00004a98",
+4777 => x"00004a98",
+4778 => x"00004aa0",
+4779 => x"00004aa0",
+4780 => x"00004aa8",
+4781 => x"00004aa8",
+4782 => x"00004ab0",
+4783 => x"00004ab0",
+4784 => x"00004ab8",
+4785 => x"00004ab8",
+4786 => x"00004ac0",
+4787 => x"00004ac0",
+4788 => x"00004ac8",
+4789 => x"00004ac8",
+4790 => x"00004ad0",
+4791 => x"00004ad0",
+4792 => x"00004ad8",
+4793 => x"00004ad8",
+4794 => x"00004ae0",
+4795 => x"00004ae0",
+4796 => x"00004ae8",
+4797 => x"00004ae8",
+4798 => x"00004af0",
+4799 => x"00004af0",
+4800 => x"00004af8",
+4801 => x"00004af8",
+4802 => x"00004b00",
+4803 => x"00004b00",
+4804 => x"00004b08",
+4805 => x"00004b08",
+4806 => x"00004b10",
+4807 => x"00004b10",
+4808 => x"00004b18",
+4809 => x"00004b18",
+4810 => x"00004b20",
+4811 => x"00004b20",
+4812 => x"00004b28",
+4813 => x"00004b28",
+4814 => x"00004b30",
+4815 => x"00004b30",
+4816 => x"00004b38",
+4817 => x"00004b38",
+4818 => x"00004b40",
+4819 => x"00004b40",
+4820 => x"00004b48",
+4821 => x"00004b48",
+4822 => x"00004b50",
+4823 => x"00004b50",
+4824 => x"00004b58",
+4825 => x"00004b58",
+4826 => x"00004b60",
+4827 => x"00004b60",
+4828 => x"00004b68",
+4829 => x"00004b68",
+4830 => x"00004b70",
+4831 => x"00004b70",
+4832 => x"00004b78",
+4833 => x"00004b78",
+4834 => x"00004b80",
+4835 => x"00004b80",
+4836 => x"00004b88",
+4837 => x"00004b88",
+4838 => x"00004b90",
+4839 => x"00004b90",
+4840 => x"00004b98",
+4841 => x"00004b98",
+4842 => x"00004ba0",
+4843 => x"00004ba0",
+4844 => x"00004ba8",
+4845 => x"00004ba8",
+4846 => x"00004bb0",
+4847 => x"00004bb0",
+4848 => x"00004bb8",
+4849 => x"00004bb8",
+4850 => x"00004bc0",
+4851 => x"00004bc0",
+4852 => x"00004bc8",
+4853 => x"00004bc8",
+4854 => x"00004bd0",
+4855 => x"00004bd0",
+4856 => x"00004bd8",
+4857 => x"00004bd8",
+4858 => x"00004be0",
+4859 => x"00004be0",
+4860 => x"00004be8",
+4861 => x"00004be8",
+4862 => x"00004bf0",
+4863 => x"00004bf0",
+4864 => x"00004bf8",
+4865 => x"00004bf8",
+4866 => x"00004c00",
+4867 => x"00004c00",
+4868 => x"00004c08",
+4869 => x"00004c08",
+4870 => x"00004c10",
+4871 => x"00004c10",
+4872 => x"00004c18",
+4873 => x"00004c18",
+4874 => x"00004c20",
+4875 => x"00004c20",
+4876 => x"00004c28",
+4877 => x"00004c28",
+4878 => x"00004c30",
+4879 => x"00004c30",
+4880 => x"00004c38",
+4881 => x"00004c38",
+4882 => x"00004c40",
+4883 => x"00004c40",
+4884 => x"00004c48",
+4885 => x"00004c48",
+4886 => x"00004c50",
+4887 => x"00004c50",
+4888 => x"00004c58",
+4889 => x"00004c58",
+4890 => x"00004c60",
+4891 => x"00004c60",
+4892 => x"00004c68",
+4893 => x"00004c68",
+4894 => x"00004c70",
+4895 => x"00004c70",
+4896 => x"00004c78",
+4897 => x"00004c78",
+4898 => x"00004c80",
+4899 => x"00004c80",
+4900 => x"00004c88",
+4901 => x"00004c88",
+4902 => x"00004c90",
+4903 => x"00004c90",
+4904 => x"00004c98",
+4905 => x"00004c98",
+4906 => x"00004ca0",
+4907 => x"00004ca0",
+4908 => x"00004ca8",
+4909 => x"00004ca8",
+4910 => x"00004cb0",
+4911 => x"00004cb0",
+4912 => x"00004cb8",
+4913 => x"00004cb8",
+4914 => x"00004cc0",
+4915 => x"00004cc0",
+4916 => x"00004cc8",
+4917 => x"00004cc8",
+4918 => x"00004cd0",
+4919 => x"00004cd0",
+4920 => x"00004cd8",
+4921 => x"00004cd8",
+4922 => x"00004ce0",
+4923 => x"00004ce0",
+4924 => x"00004ce8",
+4925 => x"00004ce8",
+4926 => x"000044e8",
+4927 => x"ffffffff",
+4928 => x"00000000",
+4929 => x"ffffffff",
+4930 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(conv_integer(memAAddr)) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(conv_integer(memAAddr));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(conv_integer(memBAddr)) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(conv_integer(memBAddr));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd b/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd
new file mode 100644
index 0000000..83a7de2
--- /dev/null
+++ b/zpu/hdl/zpu3/src/dualport_ram_synplicity.vhd
@@ -0,0 +1,5012 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+
+--shared variable ram : ram_type :=
+signal ram : ram_type :=
+(
+0 => x"800b0b0b",
+1 => x"0b0b8070",
+2 => x"0b0b818a",
+3 => x"dc0c3a0b",
+4 => x"0b80dab4",
+5 => x"04000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80db972d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b0b2a",
+20 => x"83ffff06",
+21 => x"52810504",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b0b2b09",
+29 => x"067383ff",
+30 => x"ff0b0b0b",
+31 => x"0b83a704",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53518105",
+38 => x"04000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51810504",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53518105",
+55 => x"04000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51810504",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"72ff0571",
+65 => x"81050673",
+66 => x"ff050972",
+67 => x"74058005",
+68 => x"06075350",
+69 => x"50040000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b8c",
+73 => x"f8040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535181",
+82 => x"05040000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"81050400",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71718105",
+105 => x"53510406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515181",
+111 => x"05040000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51810504",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53518105",
+125 => x"04000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52810504",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"81050409",
+139 => x"81058305",
+140 => x"1010102b",
+141 => x"0772fc06",
+142 => x"0c515181",
+143 => x"05040000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535181",
+147 => x"05040000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"81050400",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b818a",
+162 => x"88738306",
+163 => x"10100508",
+164 => x"067381ff",
+165 => x"06738306",
+166 => x"0b0b0b84",
+167 => x"ab040000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0bb3",
+171 => x"912d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c810551",
+175 => x"04000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0bb4",
+179 => x"8a2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c810551",
+183 => x"04000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547181",
+188 => x"05067309",
+189 => x"72740580",
+190 => x"05060753",
+191 => x"50500400",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"81050673",
+197 => x"09727405",
+198 => x"80050607",
+199 => x"53505004",
+200 => x"05800504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"818ad80c",
+210 => x"51810504",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"72830610",
+217 => x"10728306",
+218 => x"0710100b",
+219 => x"0b818a98",
+220 => x"05080400",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"81050400",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"71710571",
+249 => x"81055351",
+250 => x"04000000",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"8db33f80",
+257 => x"f39e3f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51810504",
+267 => x"72fc0608",
+268 => x"81ff0a06",
+269 => x"72fc0670",
+270 => x"5408fe80",
+271 => x"0a060772",
+272 => x"0c515181",
+273 => x"050472fc",
+274 => x"06080a10",
+275 => x"10101010",
+276 => x"1010100a",
+277 => x"87fc8080",
+278 => x"0672fc06",
+279 => x"08f883ff",
+280 => x"ff060772",
+281 => x"fc060c51",
+282 => x"51810504",
+283 => x"72fc0608",
+284 => x"0a101010",
+285 => x"10101010",
+286 => x"10101010",
+287 => x"10101010",
+288 => x"100a83fe",
+289 => x"800672fc",
+290 => x"0608fc81",
+291 => x"ff060772",
+292 => x"fc060c51",
+293 => x"51810504",
+294 => x"72fc0608",
+295 => x"0a101010",
+296 => x"10101010",
+297 => x"10101010",
+298 => x"10101010",
+299 => x"10101010",
+300 => x"10101010",
+301 => x"100a81ff",
+302 => x"0672fc06",
+303 => x"08fe8006",
+304 => x"0772fc06",
+305 => x"0c515181",
+306 => x"050472fc",
+307 => x"06081010",
+308 => x"10101010",
+309 => x"101081ff",
+310 => x"0a0672fc",
+311 => x"0608fe80",
+312 => x"0a060772",
+313 => x"fc060c51",
+314 => x"51810504",
+315 => x"72fc0608",
+316 => x"87fc8080",
+317 => x"0672fc06",
+318 => x"705408f8",
+319 => x"83ffff06",
+320 => x"07720c51",
+321 => x"51810504",
+322 => x"72fc0608",
+323 => x"0a101010",
+324 => x"10101010",
+325 => x"100a83fe",
+326 => x"800672fc",
+327 => x"0608fc81",
+328 => x"ff060772",
+329 => x"fc060c51",
+330 => x"51810504",
+331 => x"72fc0608",
+332 => x"0a101010",
+333 => x"10101010",
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+4831 => x"00000000",
+4832 => x"00000000",
+4833 => x"00000000",
+4834 => x"00000000",
+4835 => x"00000000",
+4836 => x"00000000",
+4837 => x"00000000",
+4838 => x"00000000",
+4839 => x"00000000",
+4840 => x"00000000",
+4841 => x"00000000",
+4842 => x"00000000",
+4843 => x"00000000",
+4844 => x"00000000",
+4845 => x"00000000",
+4846 => x"00000000",
+4847 => x"00000000",
+4848 => x"00000000",
+4849 => x"00000000",
+4850 => x"00000000",
+4851 => x"00000000",
+4852 => x"00000000",
+4853 => x"00000000",
+4854 => x"00000000",
+4855 => x"00000000",
+4856 => x"00000000",
+4857 => x"00000000",
+4858 => x"00000000",
+4859 => x"00000000",
+4860 => x"00000000",
+4861 => x"00000000",
+4862 => x"00000000",
+4863 => x"00000000",
+4864 => x"00000000",
+4865 => x"00000000",
+4866 => x"00000000",
+4867 => x"00000000",
+4868 => x"00000000",
+4869 => x"00000000",
+4870 => x"00000000",
+4871 => x"00000000",
+4872 => x"00000000",
+4873 => x"00000000",
+4874 => x"00000000",
+4875 => x"00000000",
+4876 => x"00000000",
+4877 => x"00000000",
+4878 => x"00000000",
+4879 => x"00000000",
+4880 => x"00000000",
+4881 => x"00000000",
+4882 => x"00000000",
+4883 => x"00000000",
+4884 => x"00000000",
+4885 => x"00000000",
+4886 => x"00000000",
+4887 => x"00000000",
+4888 => x"00000000",
+4889 => x"00000000",
+4890 => x"00000000",
+4891 => x"00000000",
+4892 => x"00000000",
+4893 => x"00000000",
+4894 => x"00000000",
+4895 => x"00000000",
+4896 => x"00000000",
+4897 => x"00000000",
+4898 => x"00000000",
+4899 => x"00000000",
+4900 => x"00000000",
+4901 => x"00000000",
+4902 => x"00000000",
+4903 => x"00000000",
+4904 => x"00000000",
+4905 => x"00000000",
+4906 => x"00000000",
+4907 => x"00000000",
+4908 => x"00000000",
+4909 => x"00000000",
+4910 => x"00000000",
+4911 => x"00000000",
+4912 => x"00000000",
+4913 => x"00000000",
+4914 => x"00000000",
+4915 => x"00000000",
+4916 => x"00000000",
+4917 => x"00000000",
+4918 => x"00000000",
+4919 => x"00000000",
+4920 => x"00000000",
+4921 => x"00000000",
+4922 => x"00000000",
+4923 => x"00000000",
+4924 => x"00000000",
+4925 => x"00000000",
+4926 => x"00000000",
+4927 => x"00000000",
+4928 => x"00000000",
+4929 => x"00000000",
+4930 => x"00000000",
+4931 => x"00000000",
+4932 => x"00000000",
+4933 => x"00000000",
+4934 => x"00000000",
+4935 => x"00000000",
+4936 => x"00000000",
+4937 => x"00000000",
+4938 => x"00000000",
+4939 => x"00000000",
+4940 => x"00000000",
+4941 => x"000043fc",
+4942 => x"ffffffff",
+4943 => x"00000000",
+4944 => x"ffffffff",
+4945 => x"00000000",
+	others => x"00000000"
+);
+
+attribute syn_ramstyle : string;
+attribute syn_ramstyle of ram : signal is "no_rw_check" ;
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') then
+			ram(conv_integer(memAAddr)) <= memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(conv_integer(memAAddr));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(conv_integer(memBAddr)) <= memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(conv_integer(memBAddr));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/helloworld_ram.vhd b/zpu/hdl/zpu3/src/helloworld_ram.vhd
new file mode 100644
index 0000000..2e1d35d
--- /dev/null
+++ b/zpu/hdl/zpu3/src/helloworld_ram.vhd
@@ -0,0 +1,3345 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"800b0b0b",
+1 => x"0b0b8070",
+2 => x"0b0b80d6",
+3 => x"f00c3a0b",
+4 => x"0b80cd92",
+5 => x"04000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80cde02d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b0b2a",
+20 => x"83ffff06",
+21 => x"52040000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b0b2b09",
+29 => x"067383ff",
+30 => x"ff0b0b0b",
+31 => x"0b83a504",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"72728072",
+73 => x"8106ff05",
+74 => x"09720605",
+75 => x"71105272",
+76 => x"0a100a53",
+77 => x"72ed3851",
+78 => x"51535104",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"04067383",
+106 => x"06098105",
+107 => x"8205832b",
+108 => x"0b2b0772",
+109 => x"fc060c51",
+110 => x"51040000",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04098105",
+139 => x"83051010",
+140 => x"102b0772",
+141 => x"fc060c51",
+142 => x"51040000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80d6",
+162 => x"dc738306",
+163 => x"10100508",
+164 => x"067381ff",
+165 => x"06738306",
+166 => x"0b0b0b84",
+167 => x"a9040000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8e",
+171 => x"fd2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b90",
+179 => x"af2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07535050",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075350",
+199 => x"50040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80d6ec0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"04000000",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"839f3f80",
+257 => x"cdf83f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51043c04",
+267 => x"70700b0b",
+268 => x"80e6d808",
+269 => x"52841208",
+270 => x"70810651",
+271 => x"5170f638",
+272 => x"710881ff",
+273 => x"06800c50",
+274 => x"50047070",
+275 => x"0b0b80e6",
+276 => x"d8085284",
+277 => x"1208700a",
+278 => x"100a7081",
+279 => x"06515151",
+280 => x"70f13873",
+281 => x"720c5050",
+282 => x"0480d6ec",
+283 => x"08802ea8",
+284 => x"38838080",
+285 => x"0b0b0b80",
+286 => x"e6d80c82",
+287 => x"a0800b0b",
+288 => x"0b80e6dc",
+289 => x"0c829080",
+290 => x"0b80e6ec",
+291 => x"0c0b0b80",
+292 => x"e6e00b80",
+293 => x"e6f00c04",
+294 => x"f8808080",
+295 => x"a40b0b0b",
+296 => x"80e6d80c",
+297 => x"f8808082",
+298 => x"800b0b0b",
+299 => x"80e6dc0c",
+300 => x"f8808084",
+301 => x"800b80e6",
+302 => x"ec0cf880",
+303 => x"8080940b",
+304 => x"80e6f00c",
+305 => x"f8808080",
+306 => x"9c0b80e6",
+307 => x"e80cf880",
+308 => x"8080a00b",
+309 => x"80e6f40c",
+310 => x"04f23d0d",
+311 => x"600b0b80",
+312 => x"e6dc0856",
+313 => x"5d82750c",
+314 => x"8059805a",
+315 => x"800b8f3d",
+316 => x"71101017",
+317 => x"70085a57",
+318 => x"5d5b8077",
+319 => x"81ff067c",
+320 => x"832b5658",
+321 => x"5276537b",
+322 => x"5182fc3f",
+323 => x"7d7f7a72",
+324 => x"077c7207",
+325 => x"71716081",
+326 => x"05415f5d",
+327 => x"5b595755",
+328 => x"7a8724bb",
+329 => x"380b0b80",
+330 => x"e6dc087b",
+331 => x"10101170",
+332 => x"08595155",
+333 => x"807781ff",
+334 => x"067c832b",
+335 => x"56585276",
+336 => x"537b5182",
+337 => x"c23f7d7f",
+338 => x"7a72077c",
+339 => x"72077171",
+340 => x"60810541",
+341 => x"5f5d5b59",
+342 => x"5755877b",
+343 => x"25c73876",
+344 => x"7d0c7784",
+345 => x"1e0c7c80",
+346 => x"0c903d0d",
+347 => x"04707080",
+348 => x"e6e43351",
+349 => x"70a73880",
+350 => x"d6f80870",
+351 => x"08525270",
+352 => x"802e9438",
+353 => x"841280d6",
+354 => x"f80c702d",
+355 => x"80d6f808",
+356 => x"70085252",
+357 => x"70ee3881",
+358 => x"0b80e6e4",
+359 => x"34505004",
+360 => x"04700b0b",
+361 => x"80e6d408",
+362 => x"802e8e38",
+363 => x"0b0b0b0b",
+364 => x"800b802e",
+365 => x"09810683",
+366 => x"3850040b",
+367 => x"0b80e6d4",
+368 => x"510b0b0b",
+369 => x"f4ba3f50",
+370 => x"04048c08",
+371 => x"028c0c70",
+372 => x"70707080",
+373 => x"0b8c08fc",
+374 => x"050c8c08",
+375 => x"fc050889",
+376 => x"24818e38",
+377 => x"0b0b80d6",
+378 => x"a85188f3",
+379 => x"3f0b0b80",
+380 => x"d6b85188",
+381 => x"ea3ffc0b",
+382 => x"80e6f80c",
+383 => x"80e6f808",
+384 => x"812c5372",
+385 => x"fe2e8438",
+386 => x"86f13f8a",
+387 => x"0b80e6fc",
+388 => x"0c80e6fc",
+389 => x"0880e6f8",
+390 => x"08295372",
+391 => x"d82e8438",
+392 => x"86d93f8a",
+393 => x"0b80e6f8",
+394 => x"0c84e2ad",
+395 => x"800b80e6",
+396 => x"fc0c80e6",
+397 => x"fc0880e6",
+398 => x"f8082953",
+399 => x"72afd7c2",
+400 => x"802e8438",
+401 => x"86b53f81",
+402 => x"0a0b80e6",
+403 => x"f80cff0b",
+404 => x"80e6fc0c",
+405 => x"80e6fc08",
+406 => x"80e6f808",
+407 => x"25843886",
+408 => x"9a3f8c08",
+409 => x"fc050881",
+410 => x"058c08fc",
+411 => x"050cfeea",
+412 => x"398c08fc",
+413 => x"05088a2e",
+414 => x"843885ff",
+415 => x"3f72800c",
+416 => x"50505050",
+417 => x"8c0c048c",
+418 => x"08028c0c",
+419 => x"f53d0d8c",
+420 => x"08940508",
+421 => x"9d388c08",
+422 => x"8c05088c",
+423 => x"08900508",
+424 => x"8c088805",
+425 => x"08585654",
+426 => x"73760c74",
+427 => x"84170c81",
+428 => x"bf39800b",
+429 => x"8c08f005",
+430 => x"0c800b8c",
+431 => x"08f4050c",
+432 => x"8c088c05",
+433 => x"088c0890",
+434 => x"05085654",
+435 => x"738c08f0",
+436 => x"050c748c",
+437 => x"08f4050c",
+438 => x"8c08f805",
+439 => x"8c08f005",
+440 => x"56568870",
+441 => x"54755376",
+442 => x"5254859a",
+443 => x"3fa00b8c",
+444 => x"08940508",
+445 => x"318c08ec",
+446 => x"050c8c08",
+447 => x"ec050880",
+448 => x"249d3880",
+449 => x"0b8c08f4",
+450 => x"050c8c08",
+451 => x"ec050830",
+452 => x"8c08fc05",
+453 => x"08712b8c",
+454 => x"08f0050c",
+455 => x"54b9398c",
+456 => x"08fc0508",
+457 => x"8c08ec05",
+458 => x"082a8c08",
+459 => x"e8050c8c",
+460 => x"08fc0508",
+461 => x"8c089405",
+462 => x"082b8c08",
+463 => x"f4050c8c",
+464 => x"08f80508",
+465 => x"8c089405",
+466 => x"082b708c",
+467 => x"08e80508",
+468 => x"078c08f0",
+469 => x"050c548c",
+470 => x"08f00508",
+471 => x"8c08f405",
+472 => x"088c0888",
+473 => x"05085856",
+474 => x"5473760c",
+475 => x"7484170c",
+476 => x"8c088805",
+477 => x"08800c8d",
+478 => x"3d0d8c0c",
+479 => x"048c0802",
+480 => x"8c0cf93d",
+481 => x"0d800b8c",
+482 => x"08fc050c",
+483 => x"8c088805",
+484 => x"088025ab",
+485 => x"388c0888",
+486 => x"0508308c",
+487 => x"0888050c",
+488 => x"800b8c08",
+489 => x"f4050c8c",
+490 => x"08fc0508",
+491 => x"8838810b",
+492 => x"8c08f405",
+493 => x"0c8c08f4",
+494 => x"05088c08",
+495 => x"fc050c8c",
+496 => x"088c0508",
+497 => x"8025ab38",
+498 => x"8c088c05",
+499 => x"08308c08",
+500 => x"8c050c80",
+501 => x"0b8c08f0",
+502 => x"050c8c08",
+503 => x"fc050888",
+504 => x"38810b8c",
+505 => x"08f0050c",
+506 => x"8c08f005",
+507 => x"088c08fc",
+508 => x"050c8053",
+509 => x"8c088c05",
+510 => x"08528c08",
+511 => x"88050851",
+512 => x"81a73f80",
+513 => x"08708c08",
+514 => x"f8050c54",
+515 => x"8c08fc05",
+516 => x"08802e8c",
+517 => x"388c08f8",
+518 => x"0508308c",
+519 => x"08f8050c",
+520 => x"8c08f805",
+521 => x"0870800c",
+522 => x"54893d0d",
+523 => x"8c0c048c",
+524 => x"08028c0c",
+525 => x"fb3d0d80",
+526 => x"0b8c08fc",
+527 => x"050c8c08",
+528 => x"88050880",
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+3095 => x"00003050",
+3096 => x"00003058",
+3097 => x"00003058",
+3098 => x"00003060",
+3099 => x"00003060",
+3100 => x"00003068",
+3101 => x"00003068",
+3102 => x"00003070",
+3103 => x"00003070",
+3104 => x"00003078",
+3105 => x"00003078",
+3106 => x"00003080",
+3107 => x"00003080",
+3108 => x"00003088",
+3109 => x"00003088",
+3110 => x"00003090",
+3111 => x"00003090",
+3112 => x"00003098",
+3113 => x"00003098",
+3114 => x"000030a0",
+3115 => x"000030a0",
+3116 => x"000030a8",
+3117 => x"000030a8",
+3118 => x"000030b0",
+3119 => x"000030b0",
+3120 => x"000030b8",
+3121 => x"000030b8",
+3122 => x"000030c0",
+3123 => x"000030c0",
+3124 => x"000030c8",
+3125 => x"000030c8",
+3126 => x"000030d0",
+3127 => x"000030d0",
+3128 => x"000030d8",
+3129 => x"000030d8",
+3130 => x"000030e0",
+3131 => x"000030e0",
+3132 => x"000030e8",
+3133 => x"000030e8",
+3134 => x"000030f0",
+3135 => x"000030f0",
+3136 => x"000030f8",
+3137 => x"000030f8",
+3138 => x"00003100",
+3139 => x"00003100",
+3140 => x"00003108",
+3141 => x"00003108",
+3142 => x"00003110",
+3143 => x"00003110",
+3144 => x"00003118",
+3145 => x"00003118",
+3146 => x"00003120",
+3147 => x"00003120",
+3148 => x"00003128",
+3149 => x"00003128",
+3150 => x"00003130",
+3151 => x"00003130",
+3152 => x"00003138",
+3153 => x"00003138",
+3154 => x"00003140",
+3155 => x"00003140",
+3156 => x"00003148",
+3157 => x"00003148",
+3158 => x"00003150",
+3159 => x"00003150",
+3160 => x"00003158",
+3161 => x"00003158",
+3162 => x"00003160",
+3163 => x"00003160",
+3164 => x"00003168",
+3165 => x"00003168",
+3166 => x"00003170",
+3167 => x"00003170",
+3168 => x"00003178",
+3169 => x"00003178",
+3170 => x"00003180",
+3171 => x"00003180",
+3172 => x"00003188",
+3173 => x"00003188",
+3174 => x"00003190",
+3175 => x"00003190",
+3176 => x"00003198",
+3177 => x"00003198",
+3178 => x"000031a0",
+3179 => x"000031a0",
+3180 => x"000031a8",
+3181 => x"000031a8",
+3182 => x"000031b0",
+3183 => x"000031b0",
+3184 => x"000031b8",
+3185 => x"000031b8",
+3186 => x"000031c0",
+3187 => x"000031c0",
+3188 => x"000031c8",
+3189 => x"000031c8",
+3190 => x"000031d0",
+3191 => x"000031d0",
+3192 => x"000031d8",
+3193 => x"000031d8",
+3194 => x"000031e0",
+3195 => x"000031e0",
+3196 => x"000031e8",
+3197 => x"000031e8",
+3198 => x"000031f0",
+3199 => x"000031f0",
+3200 => x"000031f8",
+3201 => x"000031f8",
+3202 => x"00003200",
+3203 => x"00003200",
+3204 => x"00003208",
+3205 => x"00003208",
+3206 => x"00003210",
+3207 => x"00003210",
+3208 => x"00003218",
+3209 => x"00003218",
+3210 => x"00003220",
+3211 => x"00003220",
+3212 => x"00003228",
+3213 => x"00003228",
+3214 => x"00003230",
+3215 => x"00003230",
+3216 => x"00003238",
+3217 => x"00003238",
+3218 => x"00003240",
+3219 => x"00003240",
+3220 => x"00003248",
+3221 => x"00003248",
+3222 => x"00003250",
+3223 => x"00003250",
+3224 => x"00003258",
+3225 => x"00003258",
+3226 => x"00003260",
+3227 => x"00003260",
+3228 => x"00003268",
+3229 => x"00003268",
+3230 => x"00003270",
+3231 => x"00003270",
+3232 => x"00003278",
+3233 => x"00003278",
+3234 => x"00003280",
+3235 => x"00003280",
+3236 => x"00003288",
+3237 => x"00003288",
+3238 => x"00003290",
+3239 => x"00003290",
+3240 => x"00003298",
+3241 => x"00003298",
+3242 => x"000032a0",
+3243 => x"000032a0",
+3244 => x"000032a8",
+3245 => x"000032a8",
+3246 => x"000032b0",
+3247 => x"000032b0",
+3248 => x"000032b8",
+3249 => x"000032b8",
+3250 => x"000032c0",
+3251 => x"000032c0",
+3252 => x"000032c8",
+3253 => x"000032c8",
+3254 => x"000032d0",
+3255 => x"000032d0",
+3256 => x"000032d8",
+3257 => x"000032d8",
+3258 => x"000032e0",
+3259 => x"000032e0",
+3260 => x"000032e8",
+3261 => x"000032e8",
+3262 => x"000032f0",
+3263 => x"000032f0",
+3264 => x"000032f8",
+3265 => x"000032f8",
+3266 => x"00003300",
+3267 => x"00003300",
+3268 => x"00003308",
+3269 => x"00003308",
+3270 => x"00003310",
+3271 => x"00003310",
+3272 => x"00003318",
+3273 => x"00003318",
+3274 => x"00003320",
+3275 => x"00003320",
+3276 => x"00003328",
+3277 => x"00003328",
+3278 => x"00003330",
+3279 => x"00003330",
+3280 => x"00002b50",
+3281 => x"ffffffff",
+3282 => x"00000000",
+3283 => x"ffffffff",
+3284 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') then
+			ram(conv_integer(memAAddr)) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(conv_integer(memAAddr));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(conv_integer(memBAddr)) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(conv_integer(memBAddr));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/ic300.bitgen b/zpu/hdl/zpu3/src/ic300.bitgen
new file mode 100644
index 0000000..1095099
--- /dev/null
+++ b/zpu/hdl/zpu3/src/ic300.bitgen
@@ -0,0 +1,27 @@
+-g DebugBitstream:No
+-g Binary:yes
+-g CRC:Enable
+-g ConfigRate:50
+-g CclkPin:Pullnone
+-g M0Pin:Pullnone
+-g M1Pin:Pullnone
+-g M2Pin:Pullnone
+-g ProgPin:PullUp
+-g DonePin:Pullnone
+-g TckPin:Pullnone
+-g TdiPin:Pullnone
+-g TdoPin:Pullnone
+-g TmsPin:Pullnone
+-g UnusedPin:Pullnone
+-g UserID:0xFFFFFFFF
+-g DCMShutDown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:Level1
+-g DonePipe:No
+-g DriveDone:Yes
+
diff --git a/zpu/hdl/zpu3/src/ic300.lso b/zpu/hdl/zpu3/src/ic300.lso
new file mode 100644
index 0000000..22de730
--- /dev/null
+++ b/zpu/hdl/zpu3/src/ic300.lso
@@ -0,0 +1 @@
+work
diff --git a/zpu/hdl/zpu3/src/ic300.ucf b/zpu/hdl/zpu3/src/ic300.ucf
new file mode 100644
index 0000000..e11357f
--- /dev/null
+++ b/zpu/hdl/zpu3/src/ic300.ucf
@@ -0,0 +1,146 @@
+# clock inputs
+net "cpu_clk_p" loc = "R9" | iostandard=LVTTL;
+
+# input pins
+net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL;
+net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL;
+net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL;
+net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL;
+net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL;
+net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL;
+net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL;
+net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL;
+net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL;
+net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL;
+net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL;
+net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL;
+net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL;
+net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL;
+net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL;
+net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL;
+net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL;
+net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL;
+net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL;
+net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL;
+net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL;
+net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL;
+net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL;
+net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL;
+net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL;
+net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL;
+net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL;
+
+#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I;
+
+# output pins
+net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL;
+net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL;
+net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL;
+net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL;
+
+#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST;
+#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST;
+#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST;
+#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP;
+#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
+#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
+#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
+#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST;
+#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST;
+#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST;
+#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST;
+#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST;
+#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST;
+
+# bidirectional pins
+net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL;
+net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL;
+net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL;
+net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL;
+net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL;
+net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL;
+net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL;
+net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL;
+net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL;
+net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL;
+net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL;
+net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL;
+net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL;
+net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL;
+net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL;
+net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL;
+
+#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST;
+
+# TIMING
+# Create timing names
+NET "cpu_clk_p" TNM_NET = "cpu_clk_p";
+NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p";
+#NET "cpu_clk" TNM_NET = "cpu_clk";
+#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x";
+#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x";
+#NET "ddr_in_clk" TNM_NET = "ddr_in_clk";
+#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x";
+
+## Create timing
+
+# Periode timing
+TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 15.6 ns HIGH 50 %;
+#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %;
+
+# Clock domain crossing timing
+#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns;
+#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns;
+#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns;
+#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns;
+
+#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns;
+#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns;
+#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns;
+#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns;
+
+#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns;
+#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns;
+#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns;
+#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns;
+
+#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns;
+#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns;
+#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns;
+#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns;
+
+#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns;
+#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns;
+#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns;
+#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns;
+
+
+
diff --git a/zpu/hdl/zpu3/src/ic300.vhd b/zpu/hdl/zpu3/src/ic300.vhd
new file mode 100644
index 0000000..a1b4f41
--- /dev/null
+++ b/zpu/hdl/zpu3/src/ic300.vhd
@@ -0,0 +1,144 @@
+--------------------------------------------------------------------------------
+-- Company: Zylin AS
+-- Engineer: Tore Ramsland
+--
+-- Create Date:    21:47:41 07/03/05
+-- Design Name:    ic300
+-- Module Name:    ic300 - behave
+-- Project Name:   eCosBoard
+-- Target Device:  XC3S400400-FG256
+-- Tool versions:  7.1i
+-- Description:	   Top level
+--
+-- Dependencies:
+-- 
+-- Revision:
+--	2005-07-11	Updated to test FPGA
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library zylin;
+use zylin.arm7.all;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+library work;
+use work.phi_config.all;
+use work.ic300pkg.all;
+
+entity ic300 is
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	-- Clock inputs
+			cpu_clk_p		: in std_logic;
+			
+			-- CPU interface signals
+			cpu_a_p			: in std_logic_vector(20 downto 0);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_irq_p		: out std_logic_vector(1 downto 0);
+			cpu_fiq_p		: out std_logic;
+			cpu_wait_n_p	: out std_logic;
+			
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0); 			-- bidir data bus
+		    sdr_clk_fb_p	: in std_logic		-- DDR clock feedback
+		);
+end ic300;
+
+architecture behave of ic300 is
+
+signal	cpu_we				: std_logic_vector(1 downto 0);			-- Write signal for lower(0) and upper(1) 8 data bits
+signal	cpu_re				: std_logic;							-- Read enable signal for all 16 bits
+signal	areset				: std_logic;							-- Asyncronous active high reset (for initialization)
+signal	areset_dummy		: std_logic;
+
+-- Clock module signals
+signal	clk_status			: std_logic_vector(2 downto 0);			-- DLL lock status (from 3 DLL's)
+signal	cpu_clk				: std_logic;							-- 64 MHz CPU clk
+signal	cpu_clk_2x			: std_logic;							-- 128 MHz CPU clk (in phase with 64 MHz)
+signal	cpu_clk_4x			: std_logic;							-- 256 MHz CPU clk (in phase with 64 MHz)
+signal	ddr_in_clk			: std_logic;							-- 128 MHz clock from DDR SDRAM
+signal	ddr_in_clk_2x		: std_logic;							-- 256 MHz clock from DDR SDRAM
+																	-- NOTE! Phase relation to 64 MHz clock unknown
+
+-- Internal CPU interface signals
+signal	cpu_din				: std_logic_vector(15 downto 0);		-- 16-bit data from CPU
+signal	cpu_dout			: std_logic_vector(15 downto 0);		-- 16-bit data to CPU
+signal	cpu_a				: std_logic_vector(20 downto 0);		-- 21-bit address from CPU
+
+begin
+
+--	areset <= '0';
+	areset_dummy <= '0';
+
+	global_init_reset:
+	rocbuf port map(I=>areset_dummy,O=>areset);
+
+	allclocks:
+	clocks port map(
+		areset => areset,
+		cpu_clk_p => cpu_clk_p,
+		cpu_clk => cpu_clk,
+		cpu_clk_2x => cpu_clk_2x,
+		cpu_clk_4x => cpu_clk_4x,
+		sdr_clk_fb_p => sdr_clk_fb_p,
+		ddr_in_clk => ddr_in_clk,
+		ddr_in_clk_2x => ddr_in_clk_2x,
+		locked => clk_status);
+
+	arm7cpu:
+	arm7wb generic map (simulate_io_time => simulate_io_time)
+	port map(
+		areset => areset,
+		cpu_clk => cpu_clk,
+		cpu_clk_2x => cpu_clk_2x,
+		cpu_a_p => cpu_a_p,
+		cpu_wr_n_p => cpu_wr_n_p,
+		cpu_cs_n_p => cpu_cs_n_p,
+		cpu_oe_n_p => cpu_oe_n_p,
+		cpu_d_p => cpu_d_p,
+		cpu_irq_p => cpu_irq_p,
+		cpu_fiq_p => cpu_fiq_p,
+		cpu_wait_n_p => cpu_wait_n_p,
+		cpu_din => cpu_din,
+		cpu_a => cpu_a,
+		cpu_we => cpu_we,
+		cpu_re => cpu_re,
+		cpu_dout => cpu_dout);
+		
+		
+	cpu_fpga_regs:
+	zpuio port map(
+		areset => areset,
+		cpu_clk => cpu_clk,
+		clk_status => clk_status,
+		cpu_din => cpu_din,
+		cpu_a => cpu_a,
+		cpu_we => cpu_we,
+		cpu_re => cpu_re,
+		cpu_dout => cpu_dout);
+
+
+end behave;
diff --git a/zpu/hdl/zpu3/src/ic300_config.vhd b/zpu/hdl/zpu3/src/ic300_config.vhd
new file mode 100644
index 0000000..9d3f939
--- /dev/null
+++ b/zpu/hdl/zpu3/src/ic300_config.vhd
@@ -0,0 +1,20 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package phi_config is
+
+	constant		Fpga_Global_Base		: std_logic_vector(19 downto 17) 	:= "000";		-- 0x0280....
+		constant	Clock_Stat_Reg_Addr		: std_logic_vector(3 downto 1)		:= "000";		-- 0x....0000
+		constant	Testreg32_Lower_Addr	: std_logic_vector(3 downto 1) 		:= "110";		-- 0x....000C
+		constant	Testreg32_Upper_Addr	: std_logic_vector(3 downto 1) 		:= "111";		-- 0x....000E
+		
+	constant		Fpga_DDR_Ctrl_Base		: std_logic_vector(19 downto 17)	:= "111";		-- 0x028E....
+		constant	DDR_Ctrl_Reg_Addr		: std_logic_vector(3 downto 1)		:= "000";		-- 0x....0000
+		constant	DDR_Mode_Reg_Addr		: std_logic_vector(3 downto 1)		:= "001";		-- 0x....0002
+		
+		-- These are temporary test registers only!
+		constant	DDR_Data_Reg_Addr		: std_logic_vector(3 downto 1)		:= "100";		-- 0x....0008
+		constant 	DDR_Addr_Reg_Addr		: std_logic_vector(3 downto 1) 		:= "101";		-- 0x....000A
+		constant 	DDR_Req_Reg_Addr		: std_logic_vector(3 downto 1) 		:= "110";		-- 0x....000C
+	
+end phi_config;
diff --git a/zpu/hdl/zpu3/src/ic300pkg.vhd b/zpu/hdl/zpu3/src/ic300pkg.vhd
new file mode 100644
index 0000000..13da306
--- /dev/null
+++ b/zpu/hdl/zpu3/src/ic300pkg.vhd
@@ -0,0 +1,88 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package ic300pkg is
+
+	component ic300 is
+	port (	-- Clock inputs
+			cpu_clk_p		: in std_logic;
+			
+			-- CPU interface signals
+			cpu_a_p			: in std_logic_vector(20 downto 0);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_irq_p		: out std_logic_vector(1 downto 0);
+			cpu_fiq_p		: out std_logic;
+			cpu_wait_n_p	: out std_logic;
+			
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0); 			-- bidir data bus
+		    sdr_clk_fb_p	: in std_logic		-- DDR clock feedback
+		);
+	end component;
+
+	component clocks is
+	port (	areset			: in std_logic;
+			cpu_clk_p		: in std_logic;
+			sdr_clk_fb_p	: in std_logic;
+			cpu_clk			: out std_logic;
+			cpu_clk_2x		: out std_logic;
+			cpu_clk_4x		: out std_logic;
+			ddr_in_clk		: out std_logic;
+			ddr_in_clk_2x	: out std_logic;
+			locked			: out std_logic_vector(2 downto 0));
+	end component;
+
+	component cpu_regs is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			clk_status		: in std_logic_vector(2 downto 0);
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_dout		: inout std_logic_vector(15 downto 0));
+	end component;
+
+	component ddr_bridge is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_clk_4x		: in std_logic;
+			ddr_in_clk		: in std_logic;
+			ddr_in_clk_2x	: in std_logic;
+
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_dout		: inout std_logic_vector(15 downto 0);
+			
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
+	end component;
+	
+end ic300pkg;
diff --git a/zpu/hdl/zpu3/src/io.vhd b/zpu/hdl/zpu3/src/io.vhd
new file mode 100644
index 0000000..6b50ca1
--- /dev/null
+++ b/zpu/hdl/zpu3/src/io.vhd
@@ -0,0 +1,95 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+use zylin.txt_util.all;
+ 
+entity  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(7 downto 0);
+		read	: out std_logic_vector(7 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end zpu_io;
+   
+   
+architecture behave of zpu_io is
+
+
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+file 		l_file		: TEXT open write_mode is log_file;
+
+begin
+
+	
+	timerinst: timer port map (
+       clk => clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => write,
+		 adr => addr(4 downto 2),
+		 dout => timer_read);
+	
+	
+	process(areset, clk)
+	begin
+		if (areset = '1') then
+			timer_we <= '0';
+			busy <= '1';
+		elsif (clk'event and clk = '1') then
+			busy <= '1';
+			timer_we <= '0';
+			if writeEnable = '1' then
+				-- external interface
+				if addr=x"1000" then
+					-- Write to UART
+					-- report "" & character'image(conv_integer(memBint)) severity note;
+				    print(l_file, character'val(conv_integer(write)));
+				    busy <= '0';
+				elsif addr(12)='1' then
+ 					timer_we <= '1';
+				    busy <= '0';
+				else
+					report "Illegal IO write" severity failure;
+				end if;
+				
+			end if;
+			if (readEnable = '1') then
+				if addr=x"1001" then
+					read <= (0=>'1', others => '0'); -- recieve empty
+				    busy <= '0';
+ 				elsif addr(12)='1' then
+ 					read <= timer_read;
+				    busy <= '0';
+ 				elsif addr(11)='1' then
+ 					read <= ZPU_Frequency;
+				    busy <= '0';
+				else
+					report "Illegal IO read" severity failure;
+				end if;
+			else 
+				read <= (others => '1');
+			end if;
+		end if;
+	end process;
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu3/src/log.txt b/zpu/hdl/zpu3/src/log.txt
new file mode 100644
index 0000000..5557b06
--- /dev/null
+++ b/zpu/hdl/zpu3/src/log.txt
@@ -0,0 +1,156 @@
+
+
+
+D
+h
+r
+y
+s
+t
+o
+n
+e
+ 
+B
+e
+n
+c
+h
+m
+a
+r
+k
+,
+ 
+V
+e
+r
+s
+i
+o
+n
+ 
+2
+.
+1
+ 
+(
+L
+a
+n
+g
+u
+a
+g
+e
+:
+ 
+C
+)
+
+
+
+
+
+
+P
+r
+o
+g
+r
+a
+m
+ 
+c
+o
+m
+p
+i
+l
+e
+d
+ 
+w
+i
+t
+h
+o
+u
+t
+ 
+'
+r
+e
+g
+i
+s
+t
+e
+r
+'
+ 
+a
+t
+t
+r
+i
+b
+u
+t
+e
+
+
+
+
+
+
+E
+x
+e
+c
+u
+t
+i
+o
+n
+ 
+s
+t
+a
+r
+t
+s
+,
+ 
+2
+0
+0
+0
+0
+0
+ 
+r
+u
+n
+s
+ 
+t
+h
+r
+o
+u
+g
+h
+ 
+D
+h
+r
+y
+s
+t
+o
+n
+e
+
+
+
diff --git a/zpu/hdl/zpu3/src/niltrace.vhd b/zpu/hdl/zpu3/src/niltrace.vhd
new file mode 100644
index 0000000..40fc1ca
--- /dev/null
+++ b/zpu/hdl/zpu3/src/niltrace.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+use work.zpu_config.all;
+ 
+ 
+entity trace is
+  port(
+       	clk         : in std_logic;
+       	begin_inst  : in std_logic;
+       	pc          : in std_logic_vector(maxAddrBit downto 0);
+		opcode		: in std_logic_vector(7 downto 0);
+		sp			: in std_logic_vector(maxAddrBit downto 2);
+		memA		: in std_logic_vector(wordSize-1 downto 0);
+		busy  : in std_logic);
+end trace;
+   
+   
+architecture behave of trace is
+  
+begin
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu3/src/sim_fpga_top.vhd b/zpu/hdl/zpu3/src/sim_fpga_top.vhd
new file mode 100644
index 0000000..3044606
--- /dev/null
+++ b/zpu/hdl/zpu3/src/sim_fpga_top.vhd
@@ -0,0 +1,127 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    20:15:31 04/14/05
+-- Design Name:    
+-- Module Name:    fpga_top - behave
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity fpga_top is
+end fpga_top;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal	areset			: std_logic;
+
+
+component zpu_top is
+    Port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  io_busy : in std_logic;
+	 		  io_read : in std_logic_vector(7 downto 0);
+	 		  io_write : out std_logic_vector(7 downto 0);
+			  io_addr : out std_logic_vector(maxAddrBit downto minAddrBit);
+			  io_writeEnable : out std_logic;
+			  io_readEnable : out std_logic;
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic);
+end component;
+
+
+component  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(7 downto 0);
+		read	: out std_logic_vector(7 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end component;
+
+
+
+signal	 		  io_busy : std_logic;
+signal	 		  io_read : std_logic_vector(7 downto 0);
+signal	 		  io_write : std_logic_vector(7 downto 0);
+signal			  io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal			  io_writeEnable : std_logic;
+signal			  io_readEnable : std_logic;
+
+signal break : std_logic;
+
+begin
+	poweronreset: roc port map (O => areset);
+
+
+
+	zpu: zpu_top port map (
+    	clk => clk ,
+	 	areset => areset,
+	 	io_busy => io_busy,
+	 	io_read => io_read,
+	 	io_write => io_write,
+		io_addr => io_addr,
+		io_writeEnable => io_writeEnable,
+		io_readEnable => io_readEnable,
+		interrupt => '0',
+	 	break => break);
+
+
+	ioMap: zpu_io port map (
+       	clk => clk,
+	 	areset => areset,
+		busy => io_busy,
+		writeEnable => io_writeEnable,
+		readEnable => io_readEnable,
+		write	=> io_write,
+		read	=> io_read,
+		addr => io_addr
+	);
+
+
+
+	-- wiggle the clock @ 100MHz
+	clock : PROCESS
+	   begin
+   			clk <= '0';
+		   wait for 5 ns; 
+   			clk <= '1';
+		   wait for 5 ns; 
+	end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/zpu3/src/status.txt b/zpu/hdl/zpu3/src/status.txt
new file mode 100644
index 0000000..df8773a
--- /dev/null
+++ b/zpu/hdl/zpu3/src/status.txt
@@ -0,0 +1,67 @@
+- Make LOADSP/STORESP/ADDSP/PUSHPC & OR emulated => From 444 => 428 LUT.
+  A pitiful saving in return for destroying performance.
+- If I reduce datapath to 8(which is useless) => 197 LUT.
+
+Bare bones version of ZPU3:
+
+- remove NOP, PUSHPC, STORESP, LOADSP, ADDSP and OR instructions. This requires
+  modification to the GCC toolchain and will result in a fairly significant 
+  code increase. We should still do better than ARM though.
+- reduce datapath to 16 bits. This will reduce stack usage, which is good.
+- 4kBytes of RAM.
+
+     [exec] =========================================================================
+     [exec] Device utilization summary:
+     [exec] ---------------------------
+     [exec] Selected Device : 3s400ft256-4
+     [exec] Number of Slices:                     167  out of   3584     4%
+     [exec] Number of Slice Flip Flops:           126  out of   7168     1%
+     [exec] Number of 4 input LUTs:               288  out of   7168     4%
+     [exec] Number of bonded IOBs:                 49  out of    173    28%
+     [exec] Number of BRAMs:                        1  out of     16     6%
+     [exec] Number of GCLKs:                        1  out of      8    12%
+     [exec] =========================================================================
+
+
+
+
+Measurements:
+
+- Removing PUSHPC(which is possible) reduces usage by 2 LUT's.
+- I tried to introduce the instructions as seperate states at the top level,
+  but did not succeed in reducing LUT count. This might be an avenue to
+  pursue if asynchronous(?) ROM's could replace logic.
+- 550 LUT @ 76MHz. 32 bit datapath & 8 bit instructions. Added seperate decode
+  stage.
+- Tried to move memAControl into decoded opcode. Usage went up to 594 from 550.
+
+- using 16 bit opcodes to encode signals directly. 466 LUT's.
+- w/2kBytes 32 RAM & 32 bit opcodes. 415 LUT's.
+- 16 bit opcode, 16 bit datapath and 1kbyte RAM. 292 LUT's.
+
+- 725 LUT's @ 63MHz
+	 Minimum period:  15.909ns{1}  (Maximum frequency:  62.858MHz)
+- removed addsp, loadsp & storesp.  => 670 LUT's.
+- removed all pushes & pops to sp. => 638 LUT's.
+- removed OR instruction. => 672 LUT's.
+- on the second cycle an ADD is done regardless => 713 LUT's.
+- using others => 'x' for e.g. pushsp. 713 => 703.
+- switching from lots of prioritized if() for decoding instruction to a case
+  statement. 713 => 631.
+- Using ZPU1's memory scheme instead of inferred memory. 713 => 715, i.e. no
+  difference.
+- Removing AddSP. 715 => 704 LUT's.
+- Add COMPARE. 715 => 743 LUT's.
+- Slight reorganization of binary operand & NOP 715 => 704. 
+- STORE only pops 1 (which can be fixed in the assembler). 704 => 701.
+- Remove NOP. NOP is only used to clear idim_flag. Use NOT instead.
+- Removing FLIP. 681 => 646. Using a different way to generate the FLIP,
+  681 => 679.
+- Add a seperate memory system for code?
+- Use IDIM_FLAG to cache value before IM and make add single cycle.
+
+- by expanding the opcode to 32 bits, encoding everything in the opcode &
+  using case statements. 713 => 433 LUT.
+- 32 bit opcode w/encoded state & 16 bit datapath. => 325 LUT
+- by using 512 byte RAM, 16 bit datapath and 32 bit instructions => 285.
+
diff --git a/zpu/hdl/zpu3/src/testlut.vhd b/zpu/hdl/zpu3/src/testlut.vhd
new file mode 100644
index 0000000..fcc8fde
--- /dev/null
+++ b/zpu/hdl/zpu3/src/testlut.vhd
@@ -0,0 +1,106 @@
+-- Company: Zylin AS
+--
+-- Hooks up the ZPU to physical pads to ensure that it is not optimized to
+-- oblivion. This is purely to have something to measure LUT usage against.
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity ic300 is
+	port (	-- Clock inputs
+			cpu_clk_p		: in std_logic;
+			
+			-- CPU interface signals
+			cpu_a_p			: in std_logic_vector(20 downto 0);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: out std_logic_vector(15 downto 0);
+			cpu_irq_p		: out std_logic_vector(1 downto 0);
+			cpu_fiq_p		: out std_logic;
+			cpu_wait_n_p	: out std_logic;
+			
+		    sdr_clk_fb_p	: in std_logic		-- DDR clock feedback
+		);
+end ic300;
+
+architecture behave of ic300 is
+
+
+signal io_busy : std_logic;
+signal io_read : std_logic_vector(7 downto 0);
+signal io_write : std_logic_vector(7 downto 0);
+signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal io_writeEnable : std_logic;
+signal io_readEnable : std_logic;
+
+
+signal	cpu_we				: std_logic_vector(1 downto 0);
+signal	cpu_re				: std_logic;
+signal	areset				: std_logic;
+
+-- Clock module signals
+signal	clk_status			: std_logic_vector(2 downto 0);
+signal	cpu_clk				: std_logic;
+signal	cpu_clk_2x			: std_logic;
+signal	cpu_clk_4x			: std_logic;
+signal	ddr_in_clk			: std_logic;
+
+
+-- Internal CPU interface signals
+signal	cpu_din				: std_logic_vector(15 downto 0);
+signal	cpu_dout			: std_logic_vector(15 downto 0);
+signal	cpu_a				: std_logic_vector(20 downto 0);
+
+signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5);
+
+begin
+
+	areset <= '0';	-- MUST BE CHANGED TO SOMETHING CORRECT
+	
+--	cpu_d_p <= (others => '0');
+	cpu_irq_p <= (others => '0');
+	cpu_fiq_p <= '0';
+	cpu_wait_n_p <= '0';
+
+	cpu_d_p(15 downto 15) <= (others => '0');
+
+	-- delay signals going out/in w/1 clk so the 
+	-- ZPU does not have to drive those pins. 
+	-- 
+	-- these registers can be placed close to the ZPU and these
+	-- registers then have a full clock to drive the pins.
+	process(cpu_clk_p, areset)
+	begin
+		if (cpu_clk_p'event and cpu_clk_p = '1') then
+			cpu_d_p(0) <= io_writeEnable;
+			cpu_d_p(1) <= io_readEnable;
+			cpu_d_p(9 downto 2) <= io_write;
+			io_read <= cpu_a_p(7 downto 0);
+			-- 32 read/write registers is plenty realisitic for a minimal size
+			-- soft-CPU
+			cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit);
+		end if;
+	end process;
+	
+
+	zpu: zpu_top port map (
+    	clk => cpu_clk_p ,
+	 	areset => areset,
+		io_busy => '0',
+		io_writeEnable => io_writeEnable,
+		io_readEnable => io_readEnable,
+		io_write	=> io_write,
+		io_read	=> io_read,
+		io_addr => io_addr,
+		interrupt => '0'
+	);
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu3/src/timer.vhd b/zpu/hdl/zpu3/src/timer.vhd
new file mode 100644
index 0000000..65836f0
--- /dev/null
+++ b/zpu/hdl/zpu3/src/timer.vhd
@@ -0,0 +1,157 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+ 
+entity timer is
+  port(
+       clk              : in std_logic;
+		 areset				: in std_logic;
+		 we					: in std_logic;
+		 din					: in std_logic_vector(7 downto 0);
+		 adr					: in std_logic_vector(2 downto 0);
+		 dout					: out std_logic_vector(7 downto 0));
+end timer;
+   
+   
+architecture behave of timer is
+
+signal	sample	: std_logic;
+signal	reset		: std_logic;
+
+signal	c			: std_logic_vector(1 to 7);
+
+signal	cnt		: std_logic_vector(63 downto 0);
+signal	cnt_smp	: std_logic_vector(63 downto 0);
+
+begin
+
+	reset <= '1' when (we = '1' and din(0) = '1') else '0';
+	sample <= '1' when (we = '1' and din(1) = '1') else '0';
+
+	process(clk, areset)	-- Carry generation
+	begin
+		if areset = '1' then
+			c <= "0000000";
+		elsif (clk'event and clk = '1') then
+			if reset = '1' then
+				c <= "0000000";
+			else
+				if cnt(7 downto 0) = "11111110" then
+					c(1) <= '1';
+				else
+					c(1) <= '0';
+				end if;
+				if cnt(15 downto 8) = "11111111" then
+					c(2) <= '1';
+				else
+					c(2) <= '0';
+				end if;
+				if cnt(23 downto 16) = "11111111" and c(2) = '1' then
+					c(3) <= '1';
+				else
+					c(3) <= '0';
+				end if;
+				if cnt(31 downto 24) = "11111111" and c(3) = '1' then
+					c(4) <= '1';
+				else
+					c(4) <= '0';
+				end if;
+				if cnt(39 downto 32) = "11111111" and c(4) = '1' then
+					c(5) <= '1';
+				else
+					c(5) <= '0';
+				end if;
+				if cnt(47 downto 40) = "11111111" and c(5) = '1' then
+					c(6) <= '1';
+				else
+					c(6) <= '0';
+				end if;
+				if cnt(55 downto 48) = "11111111" and c(6) = '1' then
+					c(7) <= '1';
+				else
+					c(7) <= '0';
+				end if;
+			end if;	
+		end if;
+	end process;
+	
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			cnt <= (others=>'0');
+		elsif (clk'event and clk = '1') then
+			if reset = '1' then
+				cnt <= (others=>'0');
+			else
+				cnt(7 downto 0) <= cnt(7 downto 0) + '1';
+				if c(1) = '1' then
+					cnt(15 downto 8) <= cnt(15 downto 8) + '1';
+				else
+					cnt(15 downto 8) <= cnt(15 downto 8);
+				end if;
+				if c(2) = '1' and c(1) = '1' then
+					cnt(23 downto 16) <= cnt(23 downto 16) + '1';
+				else
+					cnt(23 downto 16) <= cnt(23 downto 16);
+				end if;
+				if c(3) = '1' and c(1) = '1' then
+					cnt(31 downto 24) <= cnt(31 downto 24) + '1';
+				else
+					cnt(31 downto 24) <= cnt(31 downto 24);
+				end if;
+				if c(4) = '1' and c(1) = '1' then
+					cnt(39 downto 32) <= cnt(39 downto 32) + '1';
+				else
+					cnt(39 downto 32) <= cnt(39 downto 32);
+				end if;
+				if c(5) = '1' and c(1) = '1' then
+					cnt(47 downto 40) <= cnt(47 downto 40) + '1';
+				else
+					cnt(47 downto 40) <= cnt(47 downto 40);
+				end if;
+				if c(6) = '1' and c(1) = '1' then
+					cnt(55 downto 48) <= cnt(55 downto 48) + '1';
+				else
+					cnt(55 downto 48) <= cnt(55 downto 48);
+				end if;
+				if c(7) = '1' and c(1) = '1' then
+					cnt(63 downto 56) <= cnt(63 downto 56) + '1';
+				else
+					cnt(63 downto 56) <= cnt(63 downto 56);
+				end if;
+			end if;
+		end if;
+	end process;
+	
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			cnt_smp <= (others=>'0');
+		elsif (clk'event and clk = '1') then
+			if reset = '1' then
+				cnt_smp <= (others=>'0');
+			elsif sample = '1' then
+				cnt_smp <= cnt;
+			else
+				cnt_smp <= cnt_smp;
+			end if;
+		end if;
+	end process;
+	
+	process(cnt_smp, adr)
+	begin
+		case adr is
+			when "000"	=> dout <= cnt_smp(7 downto 0);
+			when "001"	=> dout <= cnt_smp(15 downto 8);
+			when "010"	=> dout <= cnt_smp(23 downto 16);
+			when "011"	=> dout <= cnt_smp(31 downto 24);
+			when "100"	=> dout <= cnt_smp(39 downto 32);
+			when "101"	=> dout <= cnt_smp(47 downto 40);
+			when "110"	=> dout <= cnt_smp(55 downto 48);
+			when others	=> dout <= cnt_smp(63 downto 56);
+		end case;
+	end process;
+	
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu3/src/trace.vhd b/zpu/hdl/zpu3/src/trace.vhd
new file mode 100644
index 0000000..81eb448
--- /dev/null
+++ b/zpu/hdl/zpu3/src/trace.vhd
@@ -0,0 +1,80 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+use zylin.txt_util.all;
+ 
+ 
+entity trace is
+  generic (
+           log_file:       string  := "trace.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	begin_inst  : in std_logic;
+       	pc          : in std_logic_vector(maxAddrBit downto 0);
+		opcode		: in std_logic_vector(7 downto 0);
+		sp			: in std_logic_vector(maxAddrBit downto 2);
+		memA		: in std_logic_vector(wordSize-1 downto 0);
+		memB		: in std_logic_vector(wordSize-1 downto 0);
+		busy  : in std_logic
+		);
+end trace;
+   
+   
+architecture behave of trace is
+  
+  
+file 		l_file		: TEXT open write_mode is log_file;
+
+
+begin
+
+
+-- write data and control information to a file
+
+receive_data: process
+
+variable l: line;
+variable t	: std_logic_vector(wordSize-1 downto 0);
+variable t2	: std_logic_vector(maxAddrBit downto 0);
+   
+   
+   
+begin                                       
+
+	t:= (others => '0');
+	t2:= (others => '0');
+
+   -- print header for the logfile
+   print(l_file, "#pc,opcode,sp,top_of_stack ");
+   print(l_file, "#----------");
+   print(l_file, " ");
+
+	wait until clk = '1';
+	wait until clk = '0'; 
+
+   while true loop
+
+		if begin_inst = '1' then
+			t(maxAddrBit downto 2):=sp;
+			t2:=pc;
+     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB));
+		end if;
+		
+     	wait until clk = '0';
+    
+   end loop;
+
+ end process receive_data;
+
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu3/src/txt_util.vhd b/zpu/hdl/zpu3/src/txt_util.vhd
new file mode 100644
index 0000000..d42303b
--- /dev/null
+++ b/zpu/hdl/zpu3/src/txt_util.vhd
@@ -0,0 +1,586 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+
+
+package txt_util is
+
+    -- prints a message to the screen
+    procedure print(text: string);
+
+    -- prints the message when active
+    -- useful for debug switches
+    procedure print(active: boolean; text: string);
+
+    -- converts std_logic into a character
+    function chr(sl: std_logic) return character;
+
+    -- converts std_logic into a string (1 to 1)
+    function str(sl: std_logic) return string;
+
+    -- converts std_logic_vector into a string (binary base)
+    function str(slv: std_logic_vector) return string;
+
+    -- converts boolean into a string
+    function str(b: boolean) return string;
+
+    -- converts an integer into a single character
+    -- (can also be used for hex conversion and other bases)
+    function chr(int: integer) return character;
+
+    -- converts integer into string using specified base
+    function str(int: integer; base: integer) return string;
+
+    -- converts integer to string, using base 10
+    function str(int: integer) return string;
+
+    -- convert std_logic_vector into a string in hex format
+    function hstr(slv: std_logic_vector) return string;
+
+
+    -- functions to manipulate strings
+    -----------------------------------
+
+    -- convert a character to upper case
+    function to_upper(c: character) return character;
+
+    -- convert a character to lower case
+    function to_lower(c: character) return character;
+
+    -- convert a string to upper case
+    function to_upper(s: string) return string;
+
+    -- convert a string to lower case
+    function to_lower(s: string) return string;
+
+   
+    
+    -- functions to convert strings into other formats
+    --------------------------------------------------
+    
+    -- converts a character into std_logic
+    function to_std_logic(c: character) return std_logic; 
+    
+    -- converts a string into std_logic_vector
+    function to_std_logic_vector(s: string) return std_logic_vector; 
+
+
+  
+    -- file I/O
+    -----------
+       
+    -- read variable length string from input file
+    procedure str_read(file in_file: TEXT; 
+                       res_string: out string);
+        
+    -- print string to a file and start new line
+    procedure print(file out_file: TEXT;
+                    new_string: in  string);
+    
+    -- print character to a file and start new line
+    procedure print(file out_file: TEXT;
+                    char:       in  character);
+                    
+end txt_util;
+
+
+
+
+package body txt_util is
+
+
+
+
+   -- prints text to the screen
+
+   procedure print(text: string) is
+     variable msg_line: line;
+     begin
+       write(msg_line, text);
+       writeline(output, msg_line);
+   end print;
+
+
+
+
+   -- prints text to the screen when active
+
+   procedure print(active: boolean; text: string)  is
+     begin
+      if active then
+         print(text);
+      end if;
+   end print;
+
+
+   -- converts std_logic into a character
+
+   function chr(sl: std_logic) return character is
+    variable c: character;
+    begin
+      case sl is
+         when 'U' => c:= 'U';
+         when 'X' => c:= 'X';
+         when '0' => c:= '0';
+         when '1' => c:= '1';
+         when 'Z' => c:= 'Z';
+         when 'W' => c:= 'W';
+         when 'L' => c:= 'L';
+         when 'H' => c:= 'H';
+         when '-' => c:= '-';
+      end case;
+    return c;
+   end chr;
+
+
+
+   -- converts std_logic into a string (1 to 1)
+
+   function str(sl: std_logic) return string is
+    variable s: string(1 to 1);
+    begin
+        s(1) := chr(sl);
+        return s;
+   end str;
+
+
+
+   -- converts std_logic_vector into a string (binary base)
+   -- (this also takes care of the fact that the range of
+   --  a string is natural while a std_logic_vector may
+   --  have an integer range)
+
+   function str(slv: std_logic_vector) return string is
+     variable result : string (1 to slv'length);
+     variable r : integer;
+   begin
+     r := 1;
+     for i in slv'range loop
+        result(r) := chr(slv(i));
+        r := r + 1;
+     end loop;
+     return result;
+   end str;
+
+
+   function str(b: boolean) return string is
+
+    begin
+       if b then
+          return "true";
+      else
+        return "false";
+       end if;
+    end str;
+
+
+   -- converts an integer into a character
+   -- for 0 to 9 the obvious mapping is used, higher
+   -- values are mapped to the characters A-Z
+   -- (this is usefull for systems with base > 10)
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function chr(int: integer) return character is
+    variable c: character;
+   begin
+        case int is
+          when  0 => c := '0';
+          when  1 => c := '1';
+          when  2 => c := '2';
+          when  3 => c := '3';
+          when  4 => c := '4';
+          when  5 => c := '5';
+          when  6 => c := '6';
+          when  7 => c := '7';
+          when  8 => c := '8';
+          when  9 => c := '9';
+          when 10 => c := 'A';
+          when 11 => c := 'B';
+          when 12 => c := 'C';
+          when 13 => c := 'D';
+          when 14 => c := 'E';
+          when 15 => c := 'F';
+          when 16 => c := 'G';
+          when 17 => c := 'H';
+          when 18 => c := 'I';
+          when 19 => c := 'J';
+          when 20 => c := 'K';
+          when 21 => c := 'L';
+          when 22 => c := 'M';
+          when 23 => c := 'N';
+          when 24 => c := 'O';
+          when 25 => c := 'P';
+          when 26 => c := 'Q';
+          when 27 => c := 'R';
+          when 28 => c := 'S';
+          when 29 => c := 'T';
+          when 30 => c := 'U';
+          when 31 => c := 'V';
+          when 32 => c := 'W';
+          when 33 => c := 'X';
+          when 34 => c := 'Y';
+          when 35 => c := 'Z';
+          when others => c := '?';
+        end case;
+        return c;
+    end chr;
+
+
+
+   -- convert integer to string using specified base
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function str(int: integer; base: integer) return string is
+
+    variable temp:      string(1 to 10);
+    variable num:       integer;
+    variable abs_int:   integer;
+    variable len:       integer := 1;
+    variable power:     integer := 1;
+
+   begin
+
+    -- bug fix for negative numbers
+    abs_int := abs(int);
+
+    num     := abs_int;
+
+    while num >= base loop                     -- Determine how many
+      len := len + 1;                          -- characters required
+      num := num / base;                       -- to represent the
+    end loop ;                                 -- number.
+
+    for i in len downto 1 loop                 -- Convert the number to
+      temp(i) := chr(abs_int/power mod base);  -- a string starting
+      power := power * base;                   -- with the right hand
+    end loop ;                                 -- side.
+
+    -- return result and add sign if required
+    if int < 0 then
+       return '-'& temp(1 to len);
+     else
+       return temp(1 to len);
+    end if;
+
+   end str;
+
+
+  -- convert integer to string, using base 10
+  function str(int: integer) return string is
+
+   begin
+
+    return str(int, 10) ;
+
+   end str;
+
+
+
+   -- converts a std_logic_vector into a hex string.
+   function hstr(slv: std_logic_vector) return string is
+       variable hexlen: integer;
+       variable longslv : std_logic_vector(67 downto 0) := (others => '0');
+       variable hex : string(1 to 16);
+       variable fourbit : std_logic_vector(3 downto 0);
+     begin
+       hexlen := (slv'left+1)/4;
+       if (slv'left+1) mod 4 /= 0 then
+         hexlen := hexlen + 1;
+       end if;
+       longslv(slv'left downto 0) := slv;
+       for i in (hexlen -1) downto 0 loop
+         fourbit := longslv(((i*4)+3) downto (i*4));
+         case fourbit is
+           when "0000" => hex(hexlen -I) := '0';
+           when "0001" => hex(hexlen -I) := '1';
+           when "0010" => hex(hexlen -I) := '2';
+           when "0011" => hex(hexlen -I) := '3';
+           when "0100" => hex(hexlen -I) := '4';
+           when "0101" => hex(hexlen -I) := '5';
+           when "0110" => hex(hexlen -I) := '6';
+           when "0111" => hex(hexlen -I) := '7';
+           when "1000" => hex(hexlen -I) := '8';
+           when "1001" => hex(hexlen -I) := '9';
+           when "1010" => hex(hexlen -I) := 'A';
+           when "1011" => hex(hexlen -I) := 'B';
+           when "1100" => hex(hexlen -I) := 'C';
+           when "1101" => hex(hexlen -I) := 'D';
+           when "1110" => hex(hexlen -I) := 'E';
+           when "1111" => hex(hexlen -I) := 'F';
+           when "ZZZZ" => hex(hexlen -I) := 'z';
+           when "UUUU" => hex(hexlen -I) := 'u';
+           when "XXXX" => hex(hexlen -I) := 'x';
+           when others => hex(hexlen -I) := '?';
+         end case;
+       end loop;
+       return hex(1 to hexlen);
+     end hstr;
+
+
+
+   -- functions to manipulate strings
+   -----------------------------------
+
+
+   -- convert a character to upper case
+
+   function to_upper(c: character) return character is
+
+      variable u: character;
+
+    begin
+
+       case c is
+        when 'a' => u := 'A';
+        when 'b' => u := 'B';
+        when 'c' => u := 'C';
+        when 'd' => u := 'D';
+        when 'e' => u := 'E';
+        when 'f' => u := 'F';
+        when 'g' => u := 'G';
+        when 'h' => u := 'H';
+        when 'i' => u := 'I';
+        when 'j' => u := 'J';
+        when 'k' => u := 'K';
+        when 'l' => u := 'L';
+        when 'm' => u := 'M';
+        when 'n' => u := 'N';
+        when 'o' => u := 'O';
+        when 'p' => u := 'P';
+        when 'q' => u := 'Q';
+        when 'r' => u := 'R';
+        when 's' => u := 'S';
+        when 't' => u := 'T';
+        when 'u' => u := 'U';
+        when 'v' => u := 'V';
+        when 'w' => u := 'W';
+        when 'x' => u := 'X';
+        when 'y' => u := 'Y';
+        when 'z' => u := 'Z';
+        when others => u := c;
+    end case;
+
+      return u;
+
+   end to_upper;
+
+
+   -- convert a character to lower case
+
+   function to_lower(c: character) return character is
+
+      variable l: character;
+
+    begin
+
+       case c is
+        when 'A' => l := 'a';
+        when 'B' => l := 'b';
+        when 'C' => l := 'c';
+        when 'D' => l := 'd';
+        when 'E' => l := 'e';
+        when 'F' => l := 'f';
+        when 'G' => l := 'g';
+        when 'H' => l := 'h';
+        when 'I' => l := 'i';
+        when 'J' => l := 'j';
+        when 'K' => l := 'k';
+        when 'L' => l := 'l';
+        when 'M' => l := 'm';
+        when 'N' => l := 'n';
+        when 'O' => l := 'o';
+        when 'P' => l := 'p';
+        when 'Q' => l := 'q';
+        when 'R' => l := 'r';
+        when 'S' => l := 's';
+        when 'T' => l := 't';
+        when 'U' => l := 'u';
+        when 'V' => l := 'v';
+        when 'W' => l := 'w';
+        when 'X' => l := 'x';
+        when 'Y' => l := 'y';
+        when 'Z' => l := 'z';
+        when others => l := c;
+    end case;
+
+      return l;
+
+   end to_lower;
+
+
+
+   -- convert a string to upper case
+
+   function to_upper(s: string) return string is
+
+     variable uppercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        uppercase(i):= to_upper(s(i));
+     end loop;
+     return uppercase;
+
+   end to_upper;
+
+
+
+   -- convert a string to lower case
+
+   function to_lower(s: string) return string is
+
+     variable lowercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        lowercase(i):= to_lower(s(i));
+     end loop;
+     return lowercase;
+
+   end to_lower;
+
+
+
+-- functions to convert strings into other types
+
+
+-- converts a character into a std_logic
+
+function to_std_logic(c: character) return std_logic is 
+    variable sl: std_logic;
+    begin
+      case c is
+        when 'U' => 
+           sl := 'U'; 
+        when 'X' =>
+           sl := 'X';
+        when '0' => 
+           sl := '0';
+        when '1' => 
+           sl := '1';
+        when 'Z' => 
+           sl := 'Z';
+        when 'W' => 
+           sl := 'W';
+        when 'L' => 
+           sl := 'L';
+        when 'H' => 
+           sl := 'H';
+        when '-' => 
+           sl := '-';
+        when others =>
+           sl := 'X'; 
+    end case;
+   return sl;
+  end to_std_logic;
+
+
+-- converts a string into std_logic_vector
+
+function to_std_logic_vector(s: string) return std_logic_vector is 
+  variable slv: std_logic_vector(s'high-s'low downto 0);
+  variable k: integer;
+begin
+   k := s'high-s'low;
+  for i in s'range loop
+     slv(k) := to_std_logic(s(i));
+     k      := k - 1;
+  end loop;
+  return slv;
+end to_std_logic_vector;                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+----------------
+--  file I/O  --
+----------------
+
+
+
+-- read variable length string from input file
+     
+procedure str_read(file in_file: TEXT; 
+                   res_string: out string) is
+       
+       variable l:         line;
+       variable c:         character;
+       variable is_string: boolean;
+       
+   begin
+           
+     readline(in_file, l);
+     -- clear the contents of the result string
+     for i in res_string'range loop
+         res_string(i) := ' ';
+     end loop;   
+     -- read all characters of the line, up to the length  
+     -- of the results string
+     for i in res_string'range loop
+        read(l, c, is_string);
+        res_string(i) := c;
+        if not is_string then -- found end of line
+           exit;
+        end if;   
+     end loop; 
+                     
+end str_read;
+
+
+-- print string to a file
+procedure print(file out_file: TEXT;
+                new_string: in  string) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, new_string);
+     writeline(out_file, l);
+                     
+end print;
+
+
+-- print character to a file and start new line
+procedure print(file out_file: TEXT;
+                char: in  character) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, char);
+     writeline(out_file, l);
+                     
+end print;
+
+
+
+-- appends contents of a string to a file until line feed occurs
+-- (LF is considered to be the end of the string)
+
+procedure str_write(file out_file: TEXT; 
+                    new_string: in  string) is
+ begin
+      
+   for i in new_string'range loop
+      print(out_file, new_string(i));
+      if new_string(i) = LF then -- end of string
+         exit;
+      end if;
+   end loop;               
+                     
+end str_write;
+
+
+
+
+end txt_util;
+
+
+
+
diff --git a/zpu/hdl/zpu3/src/xilinx_dualport.vhd b/zpu/hdl/zpu3/src/xilinx_dualport.vhd
new file mode 100644
index 0000000..0e6edc9
--- /dev/null
+++ b/zpu/hdl/zpu3/src/xilinx_dualport.vhd
@@ -0,0 +1,1482 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    11:47:36 03/22/05
+-- Design Name:    
+-- Module Name:    mem_sys - behave
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 				  
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+library zylin;
+use zylin.zpu_config.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+signal	low				: std_logic;
+signal	high				: std_logic;
+signal  re : std_logic;
+																		 
+begin
+
+	high <= '1';
+	low <= '0';
+	re <= '1';
+
+
+   ZPU_RAM0 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"01A100E100010001003600770002006D000F0000000F06AD000302940008003C",
+      INIT_01 => X"7D4000000741F68100C800030000377935990003000300030003002A00150001",
+      INIT_02 => X"0007584101010C3D55555555370000000092800000001490000000066A594EBB",
+      INIT_03 => X"0009015555932D564C093A4024055555564CB555593C1569EA90C00000007000",
+      INIT_04 => X"BF8AA55961BE2A956586C40A4CB00932C00024A80000024C9569C893C0024E90",
+      INIT_05 => X"18A1251E2A956586F8AA55961BF8AA55961BE2A956586FE2A956586F8AA55961",
+      INIT_06 => X"51349D53764E258A2043E21BE5645DE5C4FC00E0100430C140E4665595558750",
+      INIT_07 => X"47B1656A855555D435575A815D077558E475559E755715A1C364945042425555",
+      INIT_08 => X"5555F123348C17657C405070D5E745A518B58DD5555F55551D5506F00D707B15",
+      INIT_09 => X"C141C74DD5137120D51C0715094CC4F01006A8131DD91531B913118944815155",
+      INIT_0A => X"5E559655003D3549550D458C5994A04D476568D05B0F45451D143E53D0F2CD6B",
+      INIT_0B => X"4D1E1C5D3474C5C5A1E1C5D34787171C44DC7844D3451D37974D164DD55DD555",
+      INIT_0C => X"2074532E4C3A5074DE129D074D1137134477D546C01D374DD348774DE15D3717",
+      INIT_0D => X"875650117671948CB05545A5A2615074889149341D04D4956F843575543E1A19",
+      INIT_0E => X"F804036D9753106651D5140E6905C158D8979404C7459123540DD9955A43F563",
+      INIT_0F => X"7958D037C3557056405549520F96E88622775767141BA3755D1418E1BE234480",
+      INIT_10 => X"294A1C405ACCC3705D5599D55037776149584D8F98F98F98FDD00D904D205421",
+      INIT_11 => X"74710D5C26798346751441DD555BE179544D8F98F98F98FDD00D910DC3D357C3",
+      INIT_12 => X"605D5570051840119D04C0DC3755B61D7951D9A9522D995D51D5BB106B90F7C0",
+      INIT_13 => X"D81BC3646611D695A02D1A9419695D695422C40110C0F85D6F899E4D0D555BC3",
+      INIT_14 => X"28531104D5F01EDD204141807555735D38346423303676407555545F6B945696",
+      INIT_15 => X"5212D7645155503146685C599546660676E81041C85D570DCE1B07116F116021",
+      INIT_16 => X"5F9D03530F840406A5725910604E420D910DD521D6170F9AF0F940D91836445D",
+      INIT_17 => X"83E03E03C03414D5D5F5D9BE7550DD55775514A145E5405657024C3664F3059C",
+      INIT_18 => X"444C7584143756C431049D594DC444FD19CE181427555124440155503F58E14D",
+      INIT_19 => X"D54521B201810644D895159C568F40C6C85503E135203FCF555151102C7343CC",
+      INIT_1A => X"5A95904431351D93820C4D1AA2C7FD0CD95555311185802971639A1755607515",
+      INIT_1B => X"E7D41815C826057201815C826057201815C806057209815C82741C75D1BF4336",
+      INIT_1C => X"41BD443664E14155000C4191440445305B46A8D40443A3E115495503116861C3",
+      INIT_1D => X"A1520F9C10F850FC18DB80D4777F1D5757195241D35F9754D755DD35F40D9D99",
+      INIT_1E => X"65E6A10F206870F0557411545536F0D5FA1765C8D5443E658956E52727558D14",
+      INIT_1F => X"DDD2151D31A956A0400F03FC754175510FD4A34252E0DC4076A5EC66A10FB312",
+      INIT_20 => X"77C1676610FBD310C3C3CC76F05C9FF20755DC17ECE5451D3472D9D215D34C40",
+      INIT_21 => X"55556189C508B6C3F0F0FF1D9F4561676610F207A5EF52D7957CC0F8800F7726",
+      INIT_22 => X"8890203480C224080B251D4352F126920C8CF13E00C15A16445A44DA4F105554",
+      INIT_23 => X"0F203CF4495240B82923890203080E20B8809249524080C2C0B490210C803203",
+      INIT_24 => X"854F25C74C20400C1030000B24838A6F858A08E24080F2823890203C80D203C8",
+      INIT_25 => X"00000C000000001F75D5D74FC0000000000000003FFFFFFFEAAA95438104DA47",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"0000000000000000000000000000000000000000000154000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(1 downto 0),      -- Port A 2-bit Data Output
+      DOB => memBRead(1 downto 0),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(1 downto 0),      -- Port A 2-bit Data Input
+      DIB => memBWrite(1 downto 0),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => low,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM1 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"01510111000100020061006B0000004000100002001005510001059A00360064",
+      INIT_01 => X"40300000064005640380001E0001543802180002000200010002000500110005",
+      INIT_02 => X"000653709D19C24E555555552400000000920000000024000000000162843876",
+      INIT_03 => X"0000CC55555DC1557EC5DC00033155555577055555D315607655000000007000",
+      INIT_04 => X"74818211417206084505C705770000F940000398000001765560745D30017700",
+      INIT_05 => X"165081C206084505C8182114174818211417206084505D206084505C81821141",
+      INIT_06 => X"51200592163801450816D095E0044564ADB5C58C82606080118051A1162881C8",
+      INIT_07 => X"550175554516163566505D44014118AA4818516C185014519662131830201616",
+      INIT_08 => X"96140906D01981608AF43685992015DA5245D45628675859062835B511755017",
+      INIT_09 => X"6000B8F861B22CE39C0EC602ED202FC596B59458405845C55118595694001162",
+      INIT_0A => X"55A58300016D31668D5941040556516111611710005B4D4545716E190280595B",
+      INIT_0B => X"C968C00BA5BE80B2C68C00B65A3002C1BC8BA32CBE70C3EA02C9CAC89C59458A",
+      INIT_0C => X"0B1A0D6164EC408F8A047008D9CB622E2D19546CB32362C8BE8312FACC4BA202",
+      INIT_0D => X"4455CCCC1601143B2E45916976DC147401104104059F14685B456418596D1171",
+      INIT_0E => X"B4B55655D7453C5DA01654441070416015693378C475DC495A0458256156D15F",
+      INIT_0F => X"468751645665865943F040105B8164446641416011165018A11454D15D007415",
+      INIT_10 => X"8175134656FB96434615446289641B554684057595597595D066598611165695",
+      INIT_11 => X"18A6599B55F856501AD764059656556684017495497495C066598559C91D555D",
+      INIT_12 => X"5346166005EB404406411356518A35554684656685DD4686446112185F85B684",
+      INIT_13 => X"D555D6601585546854151468D5568546895EB4044115B4595F454E12599655D6",
+      INIT_14 => X"335D511B5557C55D467C504218A4E119C7135101456604AE1A05A1555F861668",
+      INIT_15 => X"91101161116169E0F5D448156855955595171C7110462859E41D55815FD556C1",
+      INIT_16 => X"153011465B440F059A495550560474598A50591544045B8105B8459841662905",
+      INIT_17 => X"16E16C16C16514546104654E051C0615418A9450651A1155A1B165662D1D417D",
+      INIT_18 => X"700111F690095D6159A445904D270024D7D3C3B711855915976D62896C56D165",
+      INIT_19 => X"62A10F7C5B0C0557D468857E5149D00170C316D15CCD6EC558AD0441D72116D2",
+      INIT_1A => X"97681F4400824581000023D4516DE3E2517161920D8D38057557861185921514",
+      INIT_1B => X"E152154484F551212D544846551210954484D551212154484515A45C3B78F895",
+      INIT_1C => X"457E256626804961925697473A0E2C44D0F51470F47849C431468400D048CD56",
+      INIT_1D => X"51105B8C05B445B315555C05417946285153C440619C2166018A4619C8598151",
+      INIT_1E => X"4595955BA2EA0761584405655975B59920519556E9056E0566859A4581645C14",
+      INIT_1F => X"9055965A909455530D5B16F1185118A55B15520D55159076C55AF455155B50B6",
+      INIT_20 => X"8085515155B6E90616D6E0146830806841851156724A0EC620DD04559653A415",
+      INIT_21 => X"75858C001F40514145B5B40507C305515155BA2D93E496D5695545B4605B9418",
+      INIT_22 => X"0810203080F20408032DA18003C200E266D1C15050400CF788038803844E58A1",
+      INIT_23 => X"0F203CCF4CF040B12103010203480F208C80A24CF04080D0C03C1023BC82F203",
+      INIT_24 => X"0600F6CFD04155043040000C38832340070840C04080F2103010203C803203C8",
+      INIT_25 => X"0A000C00000020061C7185CFEAAAAAAAAAAAAAAA95555555555555540B080387",
+      INIT_26 => X"0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A",
+      INIT_27 => X"313A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A",
+      INIT_28 => X"00000000000000000000000000000000000000000001F0000000000000030000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(3 downto 2),      -- Port A 2-bit Data Output
+      DOB => memBRead(3 downto 2),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(3 downto 2),      -- Port A 2-bit Data Input
+      DIB => memBWrite(3 downto 2),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM2 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"0008000800000000000000010001002A000200000002000800000080000800C6",
+      INIT_01 => X"023AAAAAA028A040002A0000000002B000000000000000000000000000080000",
+      INIT_02 => X"AAA00B000020000C0000000002AAAAAAAA082AAAAAAA828AAAAAAAA008223032",
+      INIT_03 => X"AAA8CC000000E0000CC00E2AA33000000003800000030008300C2AAAAAAA3AAA",
+      INIT_04 => X"3C2828002830A0A000A0C020038AA8F02AAAA302AAAAA8000008300032A8038A",
+      INIT_05 => X"820800C0A0A000A0C282800283C2828002830A0A000A0F0A0A000A0C28280028",
+      INIT_06 => X"00000C00303000208600C841C0008C028AB00806C170000010000C0080002A30",
+      INIT_07 => X"8AB83808200000C000020C2000023002A830001E300380080002A00230100000",
+      INIT_08 => X"0000C00C00322300330800E0008020C088C0E280000B0003CC0020F08038AB83",
+      INIT_09 => X"40001DA0C0200401080400000CD880A23C00C23008C00A3B20303010102C8000",
+      INIT_0A => X"0000002AEC0C70000A0093220A8008C0230028EE00032A008CA00C230004F00B",
+      INIT_0B => X"9030420240C820130704202C1C108041C900C10A2CD04E0C00B34C80380E4000",
+      INIT_0C => X"8E32028C080030DA0244070DA342C0BC26AA40880A36C0A020D1008304020040",
+      INIT_0D => X"20A0303230280000AC0020A828028A20220000000C2080000B200030000C82C2",
+      INIT_0E => X"323200204380C300000080880B80A80B83008D037820E3A00008C0400000C203",
+      INIT_0F => X"00004800400008012C2000000300820808A323008D800A30008083C81C801000",
+      INIT_10 => X"8030808000C0002F8C0008C0000230000002200882883881C8CB0002FA000000",
+      INIT_11 => X"3080000A8030002A3220A08C0002800002200882883881C8CB000200C1200170",
+      INIT_12 => X"2F8C000AB0282A0A8CAFA006230000040008C8300080100408C08A820B003028",
+      INIT_13 => X"0002C0020208400002C8C1020800040002C282A0A800320003203C02000000C0",
+      INIT_14 => X"28002208005C2A840002A08A3009090828820E0900000A823200200507004300",
+      INIT_15 => X"0880A3000000020F00420E030000A080A0208208828C00000821810007080322",
+      INIT_16 => X"85002D080320300040088382000800000008C080E0AA0300E030A0000000008C",
+      INIT_17 => X"80C00C00C0010088C088C83C00028C002300800820000200013834000010B03C",
+      INIT_18 => X"0A20108A00290E4080038C088C00A20081C12810A30000E0A0A000000C02C804",
+      INIT_19 => X"C000020C0223C020C300000C002300C20882C0C813280FEF0008C0A8280900C0",
+      INIT_1A => X"8200000030428C0E008C100108E0CC084020000ABA882800380702E300026028",
+      INIT_1B => X"C0CE4280A240A02890280A240A02890280A200A02880280A2230228824330210",
+      INIT_1C => X"081C8000008000008C00C204DC280368800042CE0002C1C0A0000383A00E0280",
+      INIT_1D => X"0880030E803200308281822223088C00020082C0C08C630003008C08CA000000",
+      INIT_1E => X"00206003248C882E00238008023030008EB33021D0D00C002020400323020E80",
+      INIT_1F => X"08CA008A00888008AE0300F230223002030008AE02A00808A040812060030823",
+      INIT_20 => X"88B0060A0032E00880C0C8322821A22AA3020D83B00D808C182E28CA00878020",
+      INIT_21 => X"20000C003280A28E2030320C8B8220060A003248C6EA80C3003820302403026A",
+      INIT_22 => X"C2BA0AAC2AA0AE82A93AAEABA2A0B110EAAFA3EFEE8ABBAAC2C442444F300000",
+      INIT_23 => X"A90AA4BABAAAE82F04946BA0AAC2AA0AC82AE0BAAAE82AB24E5ABA09E42B90AA",
+      INIT_24 => X"AA8FAAAAACFBBEE8BED8AAA9EC0AEEBECAC1251AE82A905946BA0AA42AA0AA42",
+      INIT_25 => X"FAA00C000000700562A2FC8FC00000000000000000000000000000000E02C44E",
+      INIT_26 => X"FAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500F",
+      INIT_27 => X"0D25500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500FFAA5500F",
+      INIT_28 => X"0000000000000000000000000000000000000000000080000000000000020000",
+      INIT_29 => X"00000000000000000CF000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(5 downto 4),      -- Port A 2-bit Data Output
+      DOB => memBRead(5 downto 4),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(5 downto 4),      -- Port A 2-bit Data Input
+      DIB => memBWrite(5 downto 4),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM3 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"00040044000000020008000200020115000500020005000400020000000C0089",
+      INIT_01 => X"2975555550165082031500000000017218820002000200020002002000040000",
+      INIT_02 => X"5550070B0150281C000000008155555555849555555561555555555404117230",
+      INIT_03 => X"5555EE000000D8000CE00D9557B8000000036000000B80053000555555553555",
+      INIT_04 => X"31141484143450521050E090036555F0955557015555540000053200B9540365",
+      INIT_05 => X"4305181450521050D1414841431141484143450521050C450521050D14148414",
+      INIT_06 => X"088A0C0830B088305988C583C9824C914136660AEABA8A2AAA2A08084081160A",
+      INIT_07 => X"1544300C14808010800A0C1694A932055632082D3208420448095991A8684080",
+      INIT_08 => X"008210800A02130B030A8092006990C04620C540821702028C8290F568315443",
+      INIT_09 => X"9AB92A20C8084AAB01A820AB082640D53AA081A164C265B750A1702032124808",
+      INIT_0A => X"08016955148DF82021207E5595420685930996D9952351204C588C926A2FC00B",
+      INIT_0B => X"20E9A590C3A2192A9E9A590C3A6964A7A312A6830CEBA08A6433AA21310CA020",
+      INIT_0C => X"6E31A15036890AA312FD78AA33A084ACBE61820106E8843108A6A4229A90C4A4",
+      INIT_0D => X"11510AC9309402005C20185021614512190A28A28CF042020F108232008C45C4",
+      INIT_0E => X"31214814832100080940422454855404420142448520CC9E00A4C2C40808D90B",
+      INIT_0F => X"20268482C800150257062188232541244453130942420532044203C43C593612",
+      INIT_10 => X"7830466802C008134C8064C8208132082025942102102103D4C6202525980008",
+      INIT_11 => X"3241200540B2481531105A4C0002082025942102102103D4C6202520FB5002B0",
+      INIT_12 => X"134C801D711635AD4C525809932060882024C4202648202924C855430F223516",
+      INIT_13 => X"8282C80B91A8820265040201042028202691635AD44231040B103C99200003C8",
+      INIT_14 => X"9600999400AC154C98015A653207468C14C808871080914131A01A0A0F24C301",
+      INIT_15 => X"044853098808030C00C111820210C16080C44104654C8220949E86A80B240B19",
+      INIT_16 => X"4B46A224231280A0801E421B0AA401202064C048D1552324123252026480814C",
+      INIT_17 => X"48E88E88E8828204C864C42C90814C8053204205108099080A743C809070883D",
+      INIT_18 => X"0596A8858AA60CAA58004C066C60594203DB16B053201012505808208D03C468",
+      INIT_19 => X"C818807D4458A0C2C202603D081702E6862888C460988FDF02089AD4164688C6",
+      INIT_1A => X"420200A2B99B4C29286E640205F1CC088844081F49601684300F25132009D084",
+      INIT_1B => X"C9C2831215A0C4856831215A0C4856831215A0C485683121593251515C730222",
+      INIT_1C => X"203D4080904A20086864E4682C918096010081C30A0292C6442020EBD9160148",
+      INIT_1D => X"0548232D623112344203115113204C82084015E8C94D930063204C94D5202448",
+      INIT_1E => X"1080842348196501021064050170B2005553108554208C902010C06313012D42",
+      INIT_1F => X"04C500542A464205692388F93219320523420569084206041080560084234606",
+      INIT_20 => X"660408084234C2A548C8D63106851905632142433C9D654C965D54C5005B0A92",
+      INIT_21 => X"00201E21706259615232358C576854080842348195C541C3003112361A235591",
+      INIT_22 => X"005000100050140005055541515105505555514554414515441544554002020A",
+      INIT_23 => X"0500145455514015051545000140050014001055514000514054500114005001",
+      INIT_24 => X"4545554554515544005000055401555541414551400050515450001400500140",
+      INIT_25 => X"FFF00C000000501394E93A4FC000000000000000000000000000000005041545",
+      INIT_26 => X"FFFFFFFAAAAAAAA5555555500000000FFFFFFFFAAAAAAAA5555555500000000F",
+      INIT_27 => X"093FFFFAAAAAAAA5555555500000000FFFFFFFFAAAAAAAA5555555500000000F",
+      INIT_28 => X"0000000000000000000000000000000000000000000070000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(7 downto 6),      -- Port A 2-bit Data Output
+      DOB => memBRead(7 downto 6),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(7 downto 6),      -- Port A 2-bit Data Input
+      DIB => memBWrite(7 downto 6),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM4 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"02550195000200030077007600030359001E0003001C09DD000307EA00000064",
+      INIT_01 => X"706555555755A365027600130001222837780003000300030003001600120005",
+      INIT_02 => X"555709831042087800000000D355555554DA5555555536355555554D5AA46DF7",
+      INIT_03 => X"5541AA00002A2800AC82A25506A8000000A8A00002A200018329555555559555",
+      INIT_04 => X"A6956586F8AA55961BE2AAACA89541B85555060D555554AAC001822A2154A895",
+      INIT_05 => X"15564C3A55961BE2A956586F8A6956586F8AA55961BE29A55961BE2A956586F8",
+      INIT_06 => X"C4DD0F9C3E254D554C5A94D4A3500F07C1D00B5C330CF3C3F3CC5544DD52494A",
+      INIT_07 => X"E1B5D755571D97818E76755CE71835646436755036461D5558E13248A5555D99",
+      INIT_08 => X"DD953042010B03E0024CD486B931E7579D27491D5550765A0D55154409D21B5D",
+      INIT_09 => X"4424F150D91D3714CDB070020425D4601515551100F8018994D19555114041D5",
+      INIT_0A => X"75543554959F55D556679190489D554403E0072C4060DE140F41BA11D6E44451",
+      INIT_0B => X"6845704D611544DC545704D5111C1371144C1DC79E5C71E113697174D0747754",
+      INIT_0C => X"38344823553107174E413471697193C477905D84C7455344DE19D378574D9313",
+      INIT_0D => X"55DD48483E1B310505675CCD58860351454104100F441D5552558C3655B95098",
+      INIT_0E => X"65111AF8DD1AD055541D1D54F08F41D115509285CE0754B47450F82DDB5B6556",
+      INIT_0F => X"D550499F18E4B076DA4214846A8499649843C3E382555435685D9495496C3106",
+      INIT_10 => X"4DD55C3555001BD40D9110D5558C3701D5515951951D5114D0D2678221658145",
+      INIT_11 => X"340D6B9445289AC434711C0F9F15CDD5515951951D5114D0D2678267C4950175",
+      INIT_12 => X"F40D912D604235CD0D221D444356E005D550D1555381555500D97D875686A420",
+      INIT_13 => X"80549BE357DF5D553D7DD55A1DD555D557D4336CD746A5475E5D6A216391175A",
+      INIT_14 => X"010501F5405D40C8D5940C1435580D3849CE5740B18E1910340745C556881D5B",
+      INIT_15 => X"9B4603E049D9C0084555521555D5710555774D34040D536B8421F9D453441141",
+      INIT_16 => X"041175106E554455555F9551036500638510F943D169668356285678818E340F",
+      INIT_17 => X"D8F98F98F98FDD00D920DD6A08440D9103545D563755637555C621AE0505C164",
+      INIT_18 => X"1157D3918169757BC8590F9710611503950440C103644653210DD555BE179544",
+      INIT_19 => X"D54C433594B0854455550145755140154527D89514BD8B95754C1CD64F0D1906",
+      INIT_1A => X"5551405045830F8D75D16D155464110C4D99D918486C8049DD528503667CD750",
+      INIT_1B => X"A3429553102554C409553102554C409553102554C4095531003C972139044313",
+      INIT_1C => X"D151519E005111D94414170D204D0484CA4555500503216C59D5301C3526441B",
+      INIT_1D => X"57046685066556A495D5DD4103D10D51773591C0DE4C83E503570DE4CD6B889D",
+      INIT_1E => X"1775776F4CCF97A4766261D877D536396DC347407021AA255525558D03E7055D",
+      INIT_1F => X"30F31DBD15BBDD56706F9BF83648357C6F5D547377B6FD0855545F35776F3A33",
+      INIT_20 => X"8837575776B0C15859D9843C816FE39A4366411D28401C0D41F3E0FB1D9F4566",
+      INIT_21 => X"07670D146590C32F1676610FF31267545776B40CCCCFC89D59D5A6E8DC6F2CDF",
+      INIT_22 => X"CC30300C00300C000C320499A95208E1C4535A2755E92DCB882389238A427556",
+      INIT_23 => X"000002951C50C080313003030BC02D003400811C50C002CB87E43003F803E300",
+      INIT_24 => X"5841550C544F955C0740000C380831B1C14C8C00C0C023330030300800D00000",
+      INIT_25 => X"FFF00C000000F01400FFEAB3C0000000000000003FFFFFFFEAAA9543850823A8",
+      INIT_26 => X"555555555555555555555555555555500000000000000000000000000000000F",
+      INIT_27 => X"3A3FFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5",
+      INIT_28 => X"00000000000000000000000000000000000000000000B0000000000000020000",
+      INIT_29 => X"00000000000000000CE000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(9 downto 8),      -- Port A 2-bit Data Output
+      DOB => memBRead(9 downto 8),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(9 downto 8),      -- Port A 2-bit Data Input
+      DIB => memBWrite(9 downto 8),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM5 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"0028016800040002006B00A40002002500150002001500200002078500620060",
+      INIT_01 => X"090555555A16501F0555001E00011554543400020002000200020008001C0004",
+      INIT_02 => X"555A082282D08E55000000009355555555841555555561455555555058510938",
+      INIT_03 => X"5564320000C598030D3C595590C80000031660000C58C0246FC1555555550555",
+      INIT_04 => X"12084505C8182114172040DF165564345555903D55555715C0246FC58D571655",
+      INIT_05 => X"96296A48211417206084505C81A084505C8182114172058211417206084505C8",
+      INIT_06 => X"E18B5B896D1CD962A7546A5450CF5B71580861C4E138618E91B8586205916041",
+      INIT_07 => X"17146758A54584656E0B18A04CF16646C1660945661A862854D183703F0F0588",
+      INIT_08 => X"0582C0F063C156D030459915F861A18480718705961516185996751FBC617146",
+      INIT_09 => X"378E9CA59823E272012C64BB400C144101558A49B5B4BD50710945615F380059",
+      INIT_0A => X"1852855419554461645F509EE3462926D6D2F546F1595CCC5B756511B2343155",
+      INIT_0B => X"B7702AFAD5CB6C8B1702AFAD9C0AB629CBD9C4BA28082E8CBEA02C8E801A1166",
+      INIT_0C => X"0166AC531C4502C8D941902C80263E735D40066BA5723A8DA8CCBEA322DAFEBE",
+      INIT_0D => X"A01240416D1107E5A19151016694527B3730C30C5B44061651A15D6601668510",
+      INIT_0E => X"DA01D4D9861C12585D05065D2811A8519615D0104661940514C5B41453955451",
+      INIT_0F => X"6168095D15E114149C58BE2F5542950D5956D6D080162966440614694692E3C5",
+      INIT_10 => X"40628441544996DA5988A599654D643461695D65165D65D45596534A07012D74",
+      INIT_11 => X"668D5784B55457D16459CA5B8496B061695D65165D65D4559653465304D4BC14",
+      INIT_12 => X"CA5985D59F72958459207121566453606155996169016161A5985D5559451715",
+      INIT_13 => X"4D5555D195940616913116116061606165B7295844555A2759A175215B85D555",
+      INIT_14 => X"70B417352F056B6A715694656668C4C6756858D0D14D121D66E164A05D440611",
+      INIT_15 => X"80ACD6D20058E080458A141616C58D8595B41041C55991577DC058B25D774D57",
+      INIT_16 => X"A01F145855A314C58515165132DC89574495B80B0855514715545534054D025B",
+      INIT_17 => X"17495497495C066598559D45356659889666462941859D185867416D14046975",
+      INIT_18 => X"99524CDD7720192513505B84634995CA1454710996622409D9C0596565546840",
+      INIT_19 => X"996DF895A74805A21616894518A86430CC0D5568440545001645484671C4D444",
+      INIT_1A => X"561B22C94D195B472D1345162807D10000A4582043DF16F464514116627A61A5",
+      INIT_1B => X"5100966998A59A662966998A59A662966998A59A66296699896E9892E1FC400C",
+      INIT_1C => X"6545195D1AC85458697806A50148143DF1458A102C00D046646190140D247717",
+      INIT_1D => X"280F5144451A15D51616D05456C1599118412815927256E196655927215B4460",
+      INIT_1E => X"11858751486456951621685817855578511641A9DF0165016105845C16E02E06",
+      INIT_1F => X"35B8051B0CB846294559D7456619664659462A441B75B441C587E5058759A619",
+      INIT_20 => X"641759587598E0C15454556E8BAA56A5566140865C12B2596B3255B40507C305",
+      INIT_21 => X"C1632BBD073618665515155B50B647595875948676CA8846106405D4D05DA420",
+      INIT_22 => X"C030003C40F10C040D284715799040C1155498499FE9FDA30103010304C41658",
+      INIT_23 => X"0D1036025D60C0F617D18300080422103440125D60C0420B00C4301190424003",
+      INIT_24 => X"D0456C31905419FC4108000C300999F50245F460C000C14D1830003040D10344",
+      INIT_25 => X"AAA00C000000002AAA555573EAAAAAAAAAAAAAAA955555555555555407010320",
+      INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA",
+      INIT_27 => X"003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
+      INIT_28 => X"0000000000000000000000000000000000000000000060000000000000020000",
+      INIT_29 => X"00000000000000000CE000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(11 downto 10),      -- Port A 2-bit Data Output
+      DOB => memBRead(11 downto 10),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(11 downto 10),      -- Port A 2-bit Data Input
+      DIB => memBWrite(11 downto 10),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM6 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"00000000000000000001000200000000000200000002008800000300000000B0",
+      INIT_01 => X"202000000800080A010000000000080202B20000000000000000000200000000",
+      INIT_02 => X"0008A20300A00C02AAAAAAAA0B00000000020000000000000000000002002830",
+      INIT_03 => X"0000B8AAAAC002AB2CBC000002E2AAAAAB000AAAAC0EEA800FC8000000000000",
+      INIT_04 => X"84A000A0C2828002830A22CF000000B00000023C00000300EA800FC0EC030000",
+      INIT_05 => X"000003028002830A0A000A0C284A000A0C2828002830A328002830A0A000A0C2",
+      INIT_06 => X"3C0003000CA33000040300400B38030004028238020082002600000C8C080000",
+      INIT_07 => X"8A08CB00028C0A803C31300EA08000208000200800208C0003C8380232828C02",
+      INIT_08 => X"8C000B04881380C8800F0400B03803020093020C000A30280000202224C0A08C",
+      INIT_09 => X"003914C000B6C0E02C000003000820C882A00080003200900D800800B802D8C0",
+      INIT_0A => X"30003002B808C8C004033000800C020000C802409E0608CE03080080A00C0302",
+      INIT_0B => X"C0D00083034C08010D100830340028034CB3403C3000030420C004DA00322302",
+      INIT_0C => X"E0002A07384C004DB0C22004D00B6894C2820CAE22D364D8304820C120932820",
+      INIT_0D => X"00E002C00C811C0028A3282C08228A2400CB2CB203C08C0000002C0008000200",
+      INIT_0E => X"000E80CACC0B80002A0C0C80280088C20008800A22B32C0E30803220CB808800",
+      INIT_0F => X"C002283E00C289320830C830042028000200C0C8200000002A8C80000022BC30",
+      INIT_10 => X"88C0020880BB82C800080000003C02F8C0000C08408008008002032202088038",
+      INIT_11 => X"022C0B02300202C0000020030A00B8C0000C0840800800800203220B08800010",
+      INIT_12 => X"C8000A04800A12240020200280022F80C000000001080000200000010020A080",
+      INIT_13 => X"BE8081C90A260C0010BA8008A8C000C00100A122401000030C0030880F0A0080",
+      INIT_14 => X"0A00822000040020688002080028208008480200401C8A80002302800C200C08",
+      INIT_15 => X"00A000C8D8C0C0800000028000E00C20200082082000080B202050200E020802",
+      INIT_16 => X"000218020C02208000050088F8834C0F2A20300FB400002380C20072201CA803",
+      INIT_17 => X"00882883881C8CB000200C008880000800028C00230002300003203C81004038",
+      INIT_18 => X"000008428210320A080A03020820002200880A80000202B92028C00028000022",
+      INIT_19 => X"00890210803420210000280A30001020B8C8C200000C1800302F82430A2083B2",
+      INIT_1A => X"0000D0B68823032CC0A208000200000C20A8C0E000830008C800228000B06320",
+      INIT_1B => X"0820808E8CA023A12808E84A023A12808E84A023A12808E8480C0B8AE0040304",
+      INIT_1C => X"C808003C8233A0C00C30080800009008320000000B83A00828C0082808800001",
+      INIT_1D => X"00B00820E0C000A08080022200C6000A322860C0083880C000020083800F2028",
+      INIT_1E => X"E320230E188022AA300E24C13380203035000332ED0C20800080020E80C03C8C",
+      INIT_1F => X"70320C8A08388C003602C18800000022028C00363330F3888002A2E0230A2220",
+      INIT_20 => X"2263020230E1E0880182800C92308AAA0000384C8C202300C23220320C8B8220",
+      INIT_21 => X"E303800A0100820A0060A003082303020230E18800DAB48C08C8B0E0C80202AA",
+      INIT_22 => X"4AAA2AA4AAA2AA8AAB2AEEEAE2A12512CFEFA2FAAA8F2AA2C59444944F803000",
+      INIT_23 => X"A32A8CAAABAAA8EF04892AA3AC4AB02AD0AAC2ABAAA8AB12CF7EAA2B4CA932AA",
+      INIT_24 => X"AE8EEAAFA8FBFAA8AE94AAAAAC8FABAA8A81224AA8EA305892AA3A8CAAB2A8CA",
+      INIT_25 => X"00000C000000100000000033C00000000000000000000000000000000A04944E",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"1500000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"00000000000000000000000000000000000000000000A0000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(13 downto 12),      -- Port A 2-bit Data Output
+      DOB => memBRead(13 downto 12),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(13 downto 12),      -- Port A 2-bit Data Input
+      DIB => memBWrite(13 downto 12),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM7 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"028200020002000000020081000001800000000000000A4600000320002A00CA",
+      INIT_01 => X"905000000C800680020000080000444101710000000000000000001100000002",
+      INIT_02 => X"000C51A6981A9A015555555587000000002140000000081000000006010850B2",
+      INIT_03 => X"0001745555E001579D7E000005D15555578005555E0DD5410FE400000000A000",
+      INIT_04 => X"4C521050D1414841434519CF80000172000005BC00000380D5410FE0DC038000",
+      INIT_05 => X"00800311484143450521050D148521050D1414841434521484143450521050D1",
+      INIT_06 => X"B21023208C60000808020082040823582DA15A0A0A828A202A0202024C040620",
+      INIT_07 => X"5454C702054C25583CB23201564080111480B02080B14C8202C4451530504C29",
+      INIT_08 => X"4C2CD70F843F88C6782C0E40B2442321A663258C008530942000508418C9454C",
+      INIT_09 => X"90332AA202A8C4867C420A02E68152956550205C02310276425C64087C4124C0",
+      INIT_0A => X"320900014031E4C8090F7980048C817008C409D4390C4DAD23442049465EBE08",
+      INIT_0B => X"A6EA40229BAA42128EA40229BA900843AA22A93A69924E9A08A64AA22E319301",
+      INIT_0C => X"1080551FB198A8AA21E92A8AA64A88A82A6D8C6B22EA88A329A508A694328808",
+      INIT_0D => X"091921E08C46AC38145316580551649C4024924923E24C8008083C80A4202506",
+      INIT_0E => X"809103D78C9C4802118C8C50462554C94085486515E31E1D32123198C7831708",
+      INIT_0F => X"C805903D82C942314421C0700C1514904108C8C518408080114C42002005E000",
+      INIT_10 => X"64C82514423FC3D4202E1200002C8134C8000C048048048202080B1484546834",
+      INIT_11 => X"81380F25708102D882181023258074C8000C048048048202080B140BA642AAA2",
+      INIT_12 => X"D42025987905A11A208844A948010368C80200080368080812025822081080C0",
+      INIT_13 => X"0D4202C615198C803475408494C808C802D05A11A220C0A30C0830540B258202",
+      INIT_14 => X"45A24450AAA8001ED44005148016322E0482011A9C2C554C8013056A0C128C84",
+      INIT_15 => X"267108C424C2CAA22020854080D02C10102165961120040B501AB6060C09A404",
+      INIT_16 => X"2A80668308085210208B405C3410A90B1512326F49010C17408110F1542C5423",
+      INIT_17 => X"42102102103D4C6202520C204660202E08014C80932001320243982C52A28031",
+      INIT_18 => X"800422C160763185560523251E58003082160568080B914B1814C00020820259",
+      INIT_19 => X"00470222620A101A808054213206208A2193C202621C225A301FD1A305320225",
+      INIT_1A => X"408028096013231C01580480818028AE6674C292201F5104C60814480A709312",
+      INIT_1B => X"05A8405D4A5017529405D4A5017529405D4A5017529405D4A48D445D900A2B99",
+      INIT_1C => X"C421882C5F0098C24E6697488A6D6201F520208A80EBD91434C81A9690E40082",
+      INIT_1D => X"81700C11108080C14040851988D92005316491C20534C8C808012053440F1254",
+      INIT_1E => X"1310130866891415309108C2332080B255482315568030580850212D48C9BC4C",
+      INIT_1F => X"B2358C41A1714C810908C22080848011084C81093370B4E690215110130841A2",
+      INIT_20 => X"119301013086DA150202108D206544150809068C5E980520407852358C576850",
+      INIT_21 => X"D30B40018241451440808423460613010130866895E50E4C84C54086C6085545",
+      INIT_22 => X"4410101440510404051545555151455155455154554145554515451540283001",
+      INIT_23 => X"0510145455504015151141010144051054405055504040514154101054415101",
+      INIT_24 => X"5445551554515554415400041401555541454450404051511410101440510144",
+      INIT_25 => X"55500C000000D00000000033C000000000000000000000000000000005051544",
+      INIT_26 => X"5555555555555555555555555555555555555555555555555555555555555555",
+      INIT_27 => X"1515555555555555555555555555555555555555555555555555555555555555",
+      INIT_28 => X"00000000000000000000000000000000000000000000E0000000000000010000",
+      INIT_29 => X"00000000000000000CD000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(15 downto 14),      -- Port A 2-bit Data Output
+      DOB => memBRead(15 downto 14),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(15 downto 14),      -- Port A 2-bit Data Input
+      DIB => memBWrite(15 downto 14),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM8 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"015502550005000300F6005200030357002A0003002A066500030BDD001C000F",
+      INIT_01 => X"793000000D4EC7C70123002F0001191522250003000300030003003D00060009",
+      INIT_02 => X"000D601010C040A555555554DA00000001DCC000000077600000001645953DFD",
+      INIT_03 => X"0024C9555693855A7CB92A00932555555A4E15556932D564899E00000000A000",
+      INIT_04 => X"5D961BE2A956586F8AA567064E0024F0000093A4000002405564CB932C024A80",
+      INIT_05 => X"5D510E56586F8AA55961BE2A955961BE2A956586F8AA566586F8AA55961BE2A9",
+      INIT_06 => X"A2CD6E8D995445D50415505D54486DAC86F2014401004100D90F76420F951317",
+      INIT_07 => X"1510D0756C0F85016A08356D69D1AE7545BE09D1BE090D551595211564540F86",
+      INIT_08 => X"0F805644C511DB9595044165E874C364C783450F96543E146F9B074370D9510D",
+      INIT_09 => X"D0059716B8C5137DC0372001534D13641227546416A51443126409D9590120F9",
+      INIT_0A => X"36560854A95A40D9CF52944C950D51909A94912C5C5517E569C5555639E4D274",
+      INIT_0B => X"1C5D34787171C74DC5D34787174D1531714974D1874D34571E113716083403E4",
+      INIT_0C => X"11BC45059E74587172579D87113C5A54D9100D71F15C56148574D215D3785A1E",
+      INIT_0D => X"57101951A951691C0443C079D85206791520820865500D917555498E15555D43",
+      INIT_0E => X"5643D4020DC94C76460F0D54FD2FB0F89D9E0713B48365143E566570FDD56475",
+      INIT_0F => X"D9515D4955A1203DB50398E455555344471A9996A41D51BE6B0D1D51D5B6B105",
+      INIT_10 => X"10D5514C5D3FD4116B8D1639C1459E40D9C401D0DD3DD2DD36BE5659440CD400",
+      INIT_11 => X"9F7C5E85475555A1AF08416284DD00D9F401D01D31D21D36BE56595B07104410",
+      INIT_12 => X"016B86C4001110346B344830DAE76470D916F1D9C089D9C816783811755571F1",
+      INIT_13 => X"905DD595B4040D9C0A341D9FD0D9C0D98D1111034FC55553757DD5545E865D17",
+      INIT_14 => X"11907484261415500C0179A5BE6373A31C467445C5596D8D8C03C3F0755C0D9D",
+      INIT_15 => X"83E4589420F845D51755749D9C37408777410410826F9657E7434002771C0034",
+      INIT_16 => X"354053475556521764441D2BC0A4815E5456A851083F555955557525B559536A",
+      INIT_17 => X"951951D5114D0D2678263DD55BD1678D58E60D5903659436431C1549535241DD",
+      INIT_18 => X"44003B04E4403403010B6681900440719D0110345BE343C85440F9715CDD5515",
+      INIT_19 => X"7986431374C5975D9D99B9D835502D49FC805555310551403E56034C107395E0",
+      INIT_1A => X"9D9120C85C8066553413241D5C5014B168B0F8D350CD1D40D275549BE1100366",
+      INIT_1B => X"54B49D071CE741C739D071CE741C739D071C2741C739D071CD815C8654051858",
+      INIT_1C => X"D1D145596B4080F8C1518D8456E6310CD53754060C2C353430D91D85BC110115",
+      INIT_1D => X"5264555525557571DDDD84001BD76B9437189636B0241BA01AE46B024D525D40",
+      INIT_1E => X"0377485474C5E3903E3400F03FC755E86D59C3478B415575D96767055BA26C0D",
+      INIT_1F => X"E6A10F207A310D5D0455154D8E21AE7F540D550437D5EC0C6767EA6748574D31",
+      INIT_20 => X"EF2D7675C576C499D515DDAD233DBA2F18E0360D814C1E67410C66A10FB31265",
+      INIT_21 => X"03E10116505841CC7565776BFB332B767485444C49EF430D90DD1554E856A57E",
+      INIT_22 => X"060010B042F18004022C024D1C0C8C024C88055CCD9726B03330313015D43E70",
+      INIT_23 => X"2E10B94C860800712F77200103040C105040C086080040C8029A0013B84AE10B",
+      INIT_24 => X"7D02A0C02689FCD84294002EC00712EB68CBDDC80042C2F7720010B040210B84",
+      INIT_25 => X"00008C00000000000000003CC0000000000000003FFFFFFFEAAA954349323032",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"0000000000000000000000000000000000000000000C20000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(17 downto 16),      -- Port A 2-bit Data Output
+      DOB => memBRead(17 downto 16),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(17 downto 16),      -- Port A 2-bit Data Input
+      DIB => memBWrite(17 downto 16),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM9 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"009600160000000600E4009200060557000C0006000C02960006039300FA003A",
+      INIT_01 => X"B5D000000581E4BC081000060000110A155A0006000600060006004200740002",
+      INIT_02 => X"000959D19C274612555555558600000001AD000000006B60000000120541D009",
+      INIT_03 => X"00176555560F45581050E6005D955555583D155560F955579000000000002000",
+      INIT_04 => X"811417206084505C818201B03D00174C00005DC0000000331557D00F94003980",
+      INIT_05 => X"05904844505C8182114172060811417206084505C818204505C8182114172060",
+      INIT_06 => X"00B95D4956847059025610062B41597E299E04403812086A800816305B801AB3",
+      INIT_07 => X"16159116405B452D7501664AC09D5E01854D00657D01599654685565C7F75B44",
+      INIT_08 => X"5B405444511054691C433355D45496618696555B86456D155784919B25916159",
+      INIT_09 => X"970A02C57472B208C4E68B5073F10827B8D166E7551A574890E7B45841D905B8",
+      INIT_0A => X"6608B8000D640598E4514E75D5599B9D54695D15555904C55955628C08C3901A",
+      INIT_0B => X"C00B65A3002C1BE880B25A3002E96FA02CB02E9C30CB670268CB22CAE16696E1",
+      INIT_0C => X"356F85644232302C85304B02CBE7201284D6591C100B20C8302FA0CCBEB32C68",
+      INIT_0D => X"5A1BF03D468501103796DC24564AC421C50C30C3550C59841859454D1161632D",
+      INIT_0E => X"85D4D448590820161C5B595667C5A5B00581FCE8121643C16C95DA45B0D65418",
+      INIT_0F => X"985951471451596F6CB8120458A153154515546A2F45996E0059061061011525",
+      INIT_10 => X"659969F546555451534615B81D455DA5981400574554574665B551AAF5F542E5",
+      INIT_11 => X"6E55514D618A545D4CF26151450565984400574554574665B151AA555CD50306",
+      INIT_12 => X"615B4500879C03135F4F516357E04A6598053058E04058E495F4D4C818A5A16D",
+      INIT_13 => X"2B06D5689712598E0D3485815598E5986439C031312585AA184862965D454615",
+      INIT_14 => X"5C56557980C2D511356D69554E245A019110147CD1668D555F16CD6E18AD5981",
+      INIT_15 => X"4547156A05B44C709165B5058C4155014151861854578151255C0A1E1890E155",
+      INIT_16 => X"2C2148055859485162900507A804095DA5159403033C58A4458A051A45469451",
+      INIT_17 => X"D65165D65D4559653465B062850D534657E159901662056619D03156BAC41061",
+      INIT_18 => X"B40CA027558966CDB0B5594581EB405406459A4355D1A9405265B84963061695",
+      INIT_19 => X"B88C400052E3616445894869665813035A621616A3C160716E0031309D5A160E",
+      INIT_1A => X"85810003DF1055A137F7C24592C0B0534655B4753E2568459918A017D1809655",
+      INIT_1B => X"2ABF45A916115A458456916115A458456916D15A4584569161554844B32CD4D2",
+      INIT_1C => X"90665146A34835B4405B2243F45997E25841667C00140D3415982F3F5F100D16",
+      INIT_1D => X"914458A14585B58D0505057316525381649A743537DD175394E25B7DD251A445",
+      INIT_1E => X"564156596A42E5216D10D5B16F1195145157D6798BF562805801602E55501859",
+      INIT_1F => X"55955BA2D8F159910159565D4D217E105A5995016785D8328160E61156594E90",
+      INIT_20 => X"ED891416A5952D91D6561D652197FA6617D2065983117557579455155B50B645",
+      INIT_21 => X"96D1C15CCF5965D07595875966192514156597A438065D59859925A5D55A7182",
+      INIT_22 => X"86601098427198040F00102D2065F4638C0066147C25890194D197D1A48D6E32",
+      INIT_23 => X"2F10BD01DBE980D133F4660103040C10F04001DBE98040CF435E60123048C109",
+      INIT_24 => X"41CC71F0461277C043200020184454DCA90C7D198042D31F466010B440F10BC4",
+      INIT_25 => X"00000C00000000000000003CEAAAAAAAAAAAAAAA95555555555555540D14D180",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"0000000000000000000000000000000000000000000B70000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(19 downto 18),      -- Port A 2-bit Data Output
+      DOB => memBRead(19 downto 18),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(19 downto 18),      -- Port A 2-bit Data Input
+      DIB => memBWrite(19 downto 18),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM10 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"00000000000200000042000800000003000A0000000A00000000038300200000",
+      INIT_01 => X"300AAAAAA020C232008800040000088008000000000000000000000800020000",
+      INIT_02 => X"AAA00002000008000000000000AAAAAAA8042AAAAAAA010AAAAAAA8020080088",
+      INIT_03 => X"AA800000008F00020208C0AA00000000023C000008F00000088CAAAAAAAA0AAA",
+      INIT_04 => X"0002830A0A000A0C282820323C2A800CAAAA00E2AAAAAA330000C88F02AA302A",
+      INIT_05 => X"8C0800000A0C2828002830A0A0002830A0A000A0C2828000A0C2828002830A0A",
+      INIT_06 => X"00300020200000C0A1000A0C000002088CA200005C130CB400003000030080C3",
+      INIT_07 => X"020002302E0320083088002282802C00880C88C83C880000C000083000800320",
+      INIT_08 => X"0322C80CE030C20033203A80C2CB0000E00022030A800C830F0A2321A0082000",
+      INIT_09 => X"020C00407253203845C00010EF0EF6002003008C60406000008C08C000200030",
+      INIT_0A => X"000003AAA80820008C020809000002318101802138028CC00E20000838403030",
+      INIT_0B => X"4202C0C108040C8010241C108090720804C0093413A20D00B042004C0C0000C0",
+      INIT_0C => X"802D008C8E130004D020800042893401283000252C01344D1008344020C13030",
+      INIT_0D => X"008A4000100000328380C228C82C20A028000000063200023000082C800000C0",
+      INIT_0E => X"02A8408800BCD830040300828028A0328C009022AA0000000EA0800030C08030",
+      INIT_0F => X"00A0000A0008280C031A0E8000000B8020C18000808C083C0A000C08C0A20800",
+      INIT_10 => X"000000808C9540880F24C0F0A0183C8000A2A0C78C78C68C90B000080080A800",
+      INIT_11 => X"0C100020230080883C080804208C8000A2A0C78C78C68C90B00008020822A882",
+      INIT_12 => X"880720A2880288820F00008800C0A800008070C0C0A8C0C140320BE030002868",
+      INIT_13 => X"A00C000080A0000C0A120C004000C000880028882000002E3028C0000C208C00",
+      INIT_14 => X"02A03008AA200022008010800C001222002A3008243000041C40D082300C0002",
+      INIT_15 => X"20808202003208CF6300308C0EA32823032C208220030202210210BA32028B30",
+      INIT_16 => X"08D080B10000B62300200C028200260C0080C20B80FF0000000030003800020C",
+      INIT_17 => X"C084080080080020322030C02A200B2401C0000880028000200AA000258210C8",
+      INIT_18 => X"82A22200A08000200A0A0820C2282A1A8CA0000800C90280080030A00B8C0000",
+      INIT_19 => X"7038030C21E023288C0238C80023663238A100000C2002080C000822021200A2",
+      INIT_1A => X"8C0C088083000C003020CD8C08382EA2083032C0008420000A3000C0C8000020",
+      INIT_1B => X"00F08C08A0A3022828C08A0A3022828C08A023022828C08A08280A2C0D0B6882",
+      INIT_1C => X"00C800000108003200820121208428084F63002088280880B000FC0A230B8800",
+      INIT_1D => X"088000002000300C8C0CB208838A0300000AA21072EA030B82C00F2EA2000820",
+      INIT_1E => X"802328022802E2A80C8AE0300F2320023A02C0294F080038C023003C03080E00",
+      INIT_1F => X"206003248E340008E002008C3C903C08020008E00380E000E30008A328021E00",
+      INIT_20 => X"ECAA3232802208C0C0808C386200BAA2C3C8E20012002B0B0281206003082300",
+      INIT_21 => X"00C82C04338C00893020230E2220EA32328022800A22AC00000AA020E00200AA",
+      INIT_22 => X"8BAA2AC8AB22EA8AAA3AAAABAEF12242EAEEFAAAEAEAB9EB858904893FB00C38",
+      INIT_23 => X"B62ADAAFAAAEA88604013AA2AD8AB62AA8AAA3AAAEA8AB6ECAA3AA299CAE72AC",
+      INIT_24 => X"FA8BABAAF8BEAEACBAC0AABBF88B3FAB8FC1804EA8AB706013AA2ADCAA22AD8A",
+      INIT_25 => X"00000C00000000000000003CC00000000000000000000000000000000B05893B",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"00000000000000000000000000000000000000000002C0000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(21 downto 20),      -- Port A 2-bit Data Output
+      DOB => memBRead(21 downto 20),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(21 downto 20),      -- Port A 2-bit Data Input
+      DIB => memBWrite(21 downto 20),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM11 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"010002800005000000C1008400000003002100000021040000000B0B00000080",
+      INIT_01 => X"300555555818C13E024600280002446044400000000000000000001400210008",
+      INIT_02 => X"5558001502C05488000000002055555554085555555502055555554490240A60",
+      INIT_03 => X"55400000005F20014925C05500000000017C800005F080001652555555554555",
+      INIT_04 => X"284143450521050D141494397C95402E555500D95555557B8000D65F09557015",
+      INIT_05 => X"4C06A011050D1414841434505284143450521050D1414A1050D1414841434505",
+      INIT_06 => X"08300810202228C05A80858C82220C544955A62AAEABAEBA2AA230A8232640C7",
+      INIT_07 => X"81820930112311843064801515403C98683C64CC3C642000820254B002222311",
+      INIT_08 => X"2319C42EE8BAC200709BF860C11608091088112325648C440F25531652041820",
+      INIT_09 => X"0AAA64A0B1AA88B6AE80A0F9CB0D89600123002ED080D0A1082E04C2601C8232",
+      INIT_0A => X"80B1F855540592024B086067802000BB42034297B9016AC008640821B6A83830",
+      INIT_0B => X"A590C3A6964A7A3129083A696430E8864AA6423AE830CEA4A9A084AA0C8048C8",
+      INIT_0C => X"402E609E6DA6824AA1855024A08AA99B160820AA6292A9AA6A4229A908A6A9E9",
+      INIT_0D => X"0155C680202440B64308D144C55D125014820820088920293200203C44080420",
+      INIT_0E => X"21158224204A263099232052441402364C257115550828288DD0801236C05232",
+      INIT_0F => X"025008204204448D20BD0F420204075350030300404C042C95208C84C8591480",
+      INIT_10 => X"120000824C6A82140F18C0B258202D42025358CF4CF4CF4C70F6080202425682",
+      INIT_11 => X"2D2E0814132042102D960C0C114C42025358CF4CF4CF4C70F608020811195469",
+      INIT_12 => X"140F1159658164C80B60264402C9144202E0B8C2CA74C2C6C0F140DA32001498",
+      INIT_13 => X"508C820240D8202CA5A58C268202C2024698164C8BB0201D3214C8120C114C82",
+      INIT_14 => X"41582246551A8099826834902C91209986B53201DC3018282FC8F041320C2024",
+      INIT_15 => X"14404302823121C09300314C2D531653231C1041590B25085301B0E5318547A2",
+      INIT_16 => X"812A614202024993081A8C9343921D0C01408167603C02062020808004200508",
+      INIT_17 => X"C048048048202080B140B8C815580B1803C9200648096080914544201F19B8C4",
+      INIT_18 => X"635309A05A60803045A50814A916352D4C51801602C6196216023258074C8000",
+      INIT_19 => X"B2642B997AD453154C2904C48011F864F8BA80800C1809048C988C8B81208071",
+      INIT_1A => X"4C2886A01F5A0808B007D24C040A0258047231C180889E2205320603C46A4810",
+      INIT_1B => X"80704C945513251544C945513251544C945513251544C9455031215D42809601",
+      INIT_1C => X"08C528201A2E02316950461B05582C08889300706A9690E6B2029C005E94E8C0",
+      INIT_1D => X"044202085020302C4C8C718442140B248247C1B0F4D18206C3C90B4D15080612",
+      INIT_1E => X"4813140150A9C5588C5692388F9310815542C81567040804C25309BC02058D20",
+      INIT_1F => X"80842348197820041901405C3C782C95012004188320C6849309555314016C2A",
+      INIT_20 => X"CC55313140158184C0404C219A25715003C510202846A50F6A46008423460610",
+      INIT_21 => X"08C41C890A4D24963010130841A215313140150A91905D2022045012D6015414",
+      INIT_22 => X"4050001400501400051411551455445144445554554505515511551140808CB4",
+      INIT_23 => X"0500154555414015155545000500140050004155414001414154500154015001",
+      INIT_24 => X"5545515054551554015400055445555541451551400051455450001400500140",
+      INIT_25 => X"00000C00000000000000003CC000000000000000000000000000000001151151",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(23 downto 22),      -- Port A 2-bit Data Output
+      DOB => memBRead(23 downto 22),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(23 downto 22),      -- Port A 2-bit Data Input
+      DIB => memBWrite(23 downto 22),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM12 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"039A019A000D000B001200DA0007023A001E000F001E0FDA000F0BD9003C00CC",
+      INIT_01 => X"B69555554C5750DF077600150001D65619160003000B0003000B007E00620009",
+      INIT_02 => X"554C39042084105A00000001DD55555555D955555555769555555565615EB5BE",
+      INIT_03 => X"554AAC0000192000620183552AB000000064800001B8800A0819555555549555",
+      INIT_04 => X"686F8AA55961BE2A9565862064954A8855552A255555506A800A481B855060D5",
+      INIT_05 => X"0F947491BE2A956586F8AA559686F8AA55961BE2A9565A1BE2A956586F8AA559",
+      INIT_06 => X"55E4555D553130F9471D940D531356044986430CC330E31F333C3E346A848391",
+      INIT_07 => X"35D6B03E5162555DD551BE454D416A32594950D1695D6F969D55D0B050106257",
+      INIT_08 => X"6A55650674135555948D2557551899E1D319DC6686C599575286C34146735D6B",
+      INIT_09 => X"0B511375E55C5CCB20300054564209022543E5E74557415004E410F8141746E8",
+      INIT_0A => X"AE0A5E5545D396F84475FC1100639791155105719777D7445735D550CB8C5434",
+      INIT_0B => X"704D5111C1371164C4DA119C13584551371134971C79E5D3C571D371018C5BA1",
+      INIT_0C => X"994753E402D391371FF80D1371A5C46D51346795104DC671DD378774DE15C546",
+      INIT_0D => X"5B5A9011555CD497541A5760FB60D8541C4D34D354C86B843665D9495DD99522",
+      INIT_0E => X"64695D546782203E03646F924107E6D50F86A6360919C905A7E55556E49D9436",
+      INIT_0F => X"B8440DDE1D5511B9048D4B53755C343160951559A40F957A056F0D90D94114C7",
+      INIT_10 => X"D679D4140D155DD85255D5E851D14116B87360F80F80F00D0537757F43D40796",
+      INIT_11 => X"7410755803559DF9600C1C55540FD6387360F80F80F00D0534757C75D144000D",
+      INIT_12 => X"D8525415078455CE5804350557A1910638D530F845D0F840E5651B0C35474055",
+      INIT_13 => X"450D5D5551C06F8451150F8B46F8467840C8455CEC0766083640D5A775540D9D",
+      INIT_14 => X"C435C39600054001D41427915A29110183343D0001D5B8055FDAF500354C6B86",
+      INIT_15 => X"5E50155F46A5765083E7050F8583D043C3C4D34D43568A75400001C83704D943",
+      INIT_16 => X"092310E176738BC3E0850F1317C143755645556B5856754057556754DDD55B55",
+      INIT_17 => X"1D05D35D25D36BE56595F0D52318565417A1679C5AE171AE108065D5B81070DC",
+      INIT_18 => X"137710413751AC75D19455584241371D0D284586159535150C16284DD40D9740",
+      INIT_19 => X"68B51C594F5503C60F85C0DDBE728B201C6CDD960905D341AA04DCE847119D04",
+      INIT_1A => X"0F8C5FD0CDD555441033720F9048321F20C6655390C4D1167C355C5495C159F5",
+      INIT_1B => X"54650F25F943C97E50F25F943C97E50F25F943C97E50F25F99553100D20C86C8",
+      INIT_1C => X"B0D3CDD5C10D16651A0001CA4C27190C4C83E467FD85FC2686B8D90E8F841C1D",
+      INIT_1D => X"9B517557476727680F0FB03495F05689BECE30C59D995556D6A05DD991756036",
+      INIT_1E => X"9AC3CC76F058CBDDA96706F9BF837755E8D719DE3645D500F8C3E26C15549C6B",
+      INIT_1F => X"75776F40CEB46F9098761DF5694D6A1D776B9C198FF7418483E18F83EC767C15",
+      INIT_20 => X"CF6C3C3EC76E0CC7DD9D71515318703B9794416707741951E1AF35776F3A3327",
+      INIT_21 => X"1995184149CDC7DFA76748564D310C3C3CC76F45BAFA416F86F01755E5775604",
+      INIT_22 => X"C13000BC02E04C002D999D80225BDDC38B0652041E3E0C672F772F7700859A10",
+      INIT_23 => X"3900D6125104C0BE1369130006001000D000C25104C001872DE13009E407500B",
+      INIT_24 => X"9B24DA1D155701E2091800057049300F44449A44C003B116913000DC02D00F40",
+      INIT_25 => X"00000C00000000000000003F00000000000000003FFFFFFFEAAA954314EF7729",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"00000000000000000000000000000000000000000002B0000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(25 downto 24),      -- Port A 2-bit Data Output
+      DOB => memBRead(25 downto 24),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(25 downto 24),      -- Port A 2-bit Data Input
+      DIB => memBWrite(25 downto 24),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM13 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"048000800000000200D00184000A017000000002000011200002000000180188",
+      INIT_01 => X"7C5555555854138606440000000108641104000E0006000A0002005000C00000",
+      INIT_02 => X"5558042D08A0B41A00000001AD555555549155555555E41555555541A0206648",
+      INIT_03 => X"55715C000240F00919240F55C57000000903C000243480300640555555555555",
+      INIT_04 => X"405C8182114172060845114903D571635555C5955555590C80300643455903D5",
+      INIT_05 => X"5B801D017206084505C818211405C8182114172060845017206084505C818211",
+      INIT_06 => X"CF9158A961AC95B82D05825991BD5A818146BA784E178E05EE196D1F5140921C",
+      INIT_07 => X"B005756E115DA14862955E25811175003146959146905384061691264ACA55A0",
+      INIT_08 => X"59A42C80120D1614043907018A5255D15255DD5D458556865145564855BB005F",
+      INIT_09 => X"01CCB2259A0B2392C28EB25C2C44439D7556E1C065846DC42FC145B4B017F5D4",
+      INIT_0A => X"5D045055085455F440192D596B5B87059615B7094314F0445810596FD2990D67",
+      INIT_0B => X"2AFAD9C0AB629CBFAFADDC0ABEB572DBE2CBEB0208A280BA712A3A2C017F5451",
+      INIT_0C => X"11556380E4B31F22CC8459F22A00B2C9AD2F53440AC8B22C8BAA332CA8CCB170",
+      INIT_0D => X"20521D116161320750D75445BA63043113F3CF3C5A8353456600614680580100",
+      INIT_0E => X"61C0465D5B55056D2C59536A410615565B4484160756D1354445850590451166",
+      INIT_0F => X"34540464C6282165840F2FC01644185361165611845B8175155F598598574301",
+      INIT_10 => X"95B81610590006D555A145D454614515B44D55B85B05B059451518414910F155",
+      INIT_11 => X"754218A4566586A15676D758A25B95745945B85B05B05945151841195403B8C5",
+      INIT_12 => X"D551A2D57526556851549CC515512185746555B44C55B454651AD2896651552D",
+      INIT_13 => X"8559861581715344E5155B4405F4557449226556808162B96615991018A25946",
+      INIT_14 => X"26810900EE302D971042C7156514441D7E116C47006114D165575485665C5744",
+      INIT_15 => X"A0C05611F51A011016E3015B4416DC56D6D50410605144194847857167575649",
+      INIT_16 => X"8501D75816390056D02C5B13154B001851558A06B000164401658184C0614458",
+      INIT_17 => X"0574554574665B151AA515999DD755A194515B8256D1855D195248612057559C",
+      INIT_18 => X"294541ADD1C95F545C0658A6DD729444592D35B5D46841BCF6D5145056598440",
+      INIT_19 => X"149C18D3853DD6ED5B46C5954E2306988017058001305075452D168064440507",
+      INIT_1A => X"5B45DE3E255C5866C889405B844000F7C4859A19500318D5F56654D4686755D5",
+      INIT_1B => X"94C55B661556D98555B661556D98555B661556D98555B6615966998090003DF1",
+      INIT_1C => X"3592E46160BFE5DAB10482E8425701001416E005E33F6F15057471E127141505",
+      INIT_1D => X"80C9165B516301415B5B0701161251457D340D55D4531628D7525D4509184AA5",
+      INIT_1E => X"16D6E0146835CA997694559D7456518A815556F59C405905B416D01856291657",
+      INIT_1F => X"8587514864C4538C5A1605E146B57504145784994C01A31416D14956D0141E0C",
+      INIT_20 => X"CD516D6D0145C6464505A965E90EB3E9566B0C5F1536A2596A25058759A61921",
+      INIT_21 => X"5468563D4019C7D5514156594E90616D6E0146C37529415345B4115925148658",
+      INIT_22 => X"01C0003000C07000268DD053D75C7D13203354162007003471F473F46485451C",
+      INIT_23 => X"020009137507003F200E1C000C003400D00003750700030D29C1C00BC00F0003",
+      INIT_24 => X"CC244C4D1D8522020A340015444E300FD448038700000200E1C0000002D00080",
+      INIT_25 => X"00000C00000000000000003F2AAAAAAAAAAAAAAA95555555555555541931F475",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(27 downto 26),      -- Port A 2-bit Data Output
+      DOB => memBRead(27 downto 26),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(27 downto 26),      -- Port A 2-bit Data Input
+      DIB => memBWrite(27 downto 26),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM14 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"000A000A00020008000A0002000400B2000A0008000A008A000C000A00100010",
+      INIT_01 => X"3C00000002000B2100020000000000020882000C000800000004000A00060002",
+      INIT_02 => X"0002800A00C02800AAAAAAA80400000003080000000042000000000008082020",
+      INIT_03 => X"00300EAAA808FAA00C008F00C03AAAAAA023EAAA80B02AB22008000000000000",
+      INIT_04 => X"2A0C2828002830A0A000802023C0303B0000C0000000002E2AB2200B000023C0",
+      INIT_05 => X"0302A00830A0A000A0C2828002A0C2828002830A0A000A830A0A000A0C282800",
+      INIT_06 => X"322C0000000F2030098C00000AC20218800000408020003A00A00C9008220000",
+      INIT_07 => X"3000B00C08080028C0002C008CC030B82000000000000B0A0C00001031310403",
+      INIT_08 => X"080003203C800000000302230088C3CB2C00CF0420E030020020000200F3000F",
+      INIT_09 => X"0284200000013410000200FB000402024000C082C002C087A08260320D0F0002",
+      INIT_0A => X"1C88F20068CB00320032CA23C00F020B000B0203C230201A00B0C00610320001",
+      INIT_0B => X"00830340024034CA0830340020C0D302C0420C0001C30028D0036C04002D0108",
+      INIT_0C => X"CC390F8224230200473B002007401083A38D0B0080801204828C120B304810D1",
+      INIT_0D => X"2B020380000CCE810202820030002ACC0B082082000003200008C80000C02802",
+      INIT_0E => X"004C8C800F22000C8E0E072BB02AA0A003228022B000F80018400000228C0000",
+      INIT_0F => X"7202A8CC8C002008E004CD363022A22F0A808008200300308807000000200D83",
+      INIT_10 => X"4070A00200000C00000240C208C0188072012030030030004022302201020A80",
+      INIT_11 => X"3802300200028CA00A8A040000030032012030030030004022302232C0A80B28",
+      INIT_12 => X"000000000880004802201A200008A820F24020320800321260002A2000232800",
+      INIT_13 => X"A0008C000C4A0B208080032230B210720008000488830208000000823000008C",
+      INIT_14 => X"0008812A02CA808202280340308C0A8280900FC200C08BE03940902800240B22",
+      INIT_15 => X"0234800B00400A0000C3A0032000C200C0C820820A0022322904885000800281",
+      INIT_16 => X"2209082030310040C888038181680230000000030082302223002302E8C00200",
+      INIT_17 => X"0C78C78C68C90B0000802000A02800020008070001C8203C880808C0A0281003",
+      INIT_18 => X"A121A82029842D1002A00002420A1204002880CA000088080A004208C8000A2A",
+      INIT_19 => X"0233E882882000C80320E0080C0E0A284C208C024008C0AC10800488800A8C00",
+      INIT_1A => X"032E0CC0840800023421000303022020C080C00080C20BA070002200000E03C0",
+      INIT_1B => X"0B000302E000C0B800302E000C0B800302E000C0B800302E0808E84000880830",
+      INIT_1C => X"B002E8C088442000220300C83023800C1400C300CC0A33000032C00B0700280C",
+      INIT_1D => X"003630032303A32803032088808800201CC82C30E08A000243080E0882302220",
+      INIT_1E => X"82C0C8322820D2881003602C1880230035C081C88008C0A032C0C80E00000C0B",
+      INIT_1F => X"20230E18800B030389304CE000303088320703880C23280000C88880C8322E08",
+      INIT_20 => X"DE080C0C8320883A8C8CA008A00036AA8300AE0F0221300E1312E0230A2220E3",
+      INIT_21 => X"03000BCE003CC3C2A32328021E00880C0C83228208AAA00720B0E32A223212A9",
+      INIT_22 => X"0ABA2A90AA42AE8AB02AAEFA8AC18042EFAACFBAAB4AAEAB060104013F402082",
+      INIT_23 => X"AC2AB3AAAEEAE8940911ABA2AB8AAE2AB8AAE2AEEAE8AAE84B2ABA2DB0A6C2A9",
+      INIT_24 => X"AB4EAAEAB2AAAAB4BA84AAAAB08BAAAA2A42C46AE8AAD0B11ABA2AB4AB42AB0A",
+      INIT_25 => X"00000C00000000000000003F000000000000000000000000000000002E06012A",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"0000000000000000000000000000000000000000000170000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(29 downto 28),      -- Port A 2-bit Data Output
+      DOB => memBRead(29 downto 28),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(29 downto 28),      -- Port A 2-bit Data Input
+      DIB => memBWrite(29 downto 28),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+   ZPU_RAM15 : RAMB16_S2_S2
+   generic map (
+      INIT_A => X"0", --  Value of output RAM registers on Port A at startup
+      INIT_B => X"0", --  Value of output RAM registers on Port B at startup
+      SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
+      SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
+      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
+      SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
+      INIT_00 => X"012501250005000C00850021000C04790015000800150445000C06A500A20022",
+      INIT_01 => X"3E0000000102861A0021001A000062014461000800080008000C000500090005",
+      INIT_02 => X"00016181A9A606405555555408000000020400000000C1800000002406860012",
+      INIT_03 => X"00380D555416F5504C816F00E0355555505BD555417215799015000000000000",
+      INIT_04 => X"150D141484143450521044505BC038370000E0000000005D1579901720005BC0",
+      INIT_05 => X"232560943450521050D141484150D1414841434505210543450521050D141484",
+      INIT_06 => X"00220200080CA232424C242006C10156652140C2A0A8208A00A08C600C152802",
+      INIT_07 => X"7960B48C94080954C8002C90603830464420020820060B290C804A2B0A8A0808",
+      INIT_08 => X"0801A099B260808262038663204603C45802DC0C111020210811482500B7960F",
+      INIT_09 => X"B21A08408092A834489A08F2B02D6019E008C8D9C021C81E70D9D231028F00C1",
+      INIT_0A => X"3C65F50054C400B126310D53AA0B236700872053A93255150278C00D7442A482",
+      INIT_0B => X"40229BA900843AA20229BA9008A6EA90C4A08A6493A69908EA4E884AE83E0304",
+      INIT_0C => X"083213991D0B0084AC3620084E992813008A0B666021294A508A694329A528EA",
+      INIT_0D => X"941900480802026609C30522351855428704104100200F1080A4C42028C29489",
+      INIT_0E => X"09924C500B55848C49080F5E48945081231541904403C48021D020A0854C8880",
+      INIT_0F => X"F11354CE4C829821D2282A093015515E4540408412232430540F202202542263",
+      INIT_10 => X"C0B252C920AA8C820809A0C114C82140F11A123A23A23A20A08132192B490540",
+      INIT_11 => X"31A9320188014C4821458A02082340F11A123A23A23A20A08132193189540F14",
+      INIT_12 => X"82080840056000820852B53082055430F180823121423135908045108013168C",
+      INIT_13 => X"50204C8060860B121484231580B130B12056000826630914809200493208204C",
+      INIT_14 => X"60147B5503C56A444956B3C8304DAD4164688CA9A8C840D832822238801B0B15",
+      INIT_15 => X"050A408700809D8A08CB58231148D108C8D65965050811315FBC68B48264017B",
+      INIT_16 => X"3987081A30B361C8C641238A42DC6932092020630669301593001321D4C82502",
+      INIT_17 => X"8CF4CF4CF4C70F60802082005016080982040F2403C4582C4D2424C852942208",
+      INIT_18 => X"5A12D4581F1C3F2241500201C105A1AA20896085820254018580C114C4202535",
+      INIT_19 => X"81709601658808D02311D2042C992E2EAE684C29A084C9682040482661AD4CA0",
+      INIT_1A => X"231F1CC0888102070A2228232621A807D66080894AE65C90B4801182024003D0",
+      INIT_1B => X"060023511408D445023511408D445023511408D4450235114405D4AA486A01F5",
+      INIT_1C => X"F208D4C846C8108005EA29C4245760AE6A08CA81CC005E9120F1C00A4B12968C",
+      INIT_1D => X"26093003130B531623235855404608102D249870C644408183040C6451321180",
+      INIT_1E => X"42C8D6310685E5402010908C22081320554202D55024C0523108C58D80818C0F",
+      INIT_1F => X"1013086689640B2442308CC820343062310B24402E93142648C56148D6315DA1",
+      INIT_20 => X"ED148C8D631068854C4C500542A579414301690F86B5240C527110130841A213",
+      INIT_21 => X"82028B29217CE3C1531314016C2A548C8D6310685441680F10F6131181315052",
+      INIT_22 => X"4150005401505400051555515555155155055515155504555455555540A03041",
+      INIT_23 => X"1100451145454055115515000500140050004145454001414151500144051005",
+      INIT_24 => X"5544555515551154011400155405100554441545400111055150004400500440",
+      INIT_25 => X"00000C00000000000000003F0000000000000000000000000000000015545555",
+      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_28 => X"0000000000000000000000000000000000000000000300000000000000000000",
+      INIT_29 => X"00000000000000000CC000000000000000000000000000000000000000000000",
+      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+   port map (
+      DOA => memARead(31 downto 30),      -- Port A 2-bit Data Output
+      DOB => memBRead(31 downto 30),      -- Port B 2-bit Data Output
+      ADDRA => memAAddr(14 downto 2),  -- Port A 13-bit Address Input
+      ADDRB => memBAddr(14 downto 2),  -- Port B 13-bit Address Input
+      CLKA => clk,    -- Port A Clock
+      CLKB => clk,    -- Port B Clock
+      DIA => memAWrite(31 downto 30),      -- Port A 2-bit Data Input
+      DIB => memBWrite(31 downto 30),      -- Port B 2-bit Data Input
+      ENA => re,      -- Port A RAM Enable Input
+      ENB => high,     -- PortB RAM Enable Input
+      SSRA => low,    -- Port A Synchronous Set/Reset Input
+      SSRB => low,    -- Port B Synchronous Set/Reset Input
+      WEA => memAWriteEnable,      -- Port A Write Enable Input
+      WEB => memBWriteEnable       -- Port B Write Enable Input
+   );
+end dualport_ram_arch;
diff --git a/zpu/hdl/zpu3/src/xmake.filelist b/zpu/hdl/zpu3/src/xmake.filelist
new file mode 100644
index 0000000..3d0a779
--- /dev/null
+++ b/zpu/hdl/zpu3/src/xmake.filelist
@@ -0,0 +1,5 @@
+vhdl zylin "zpu_config.vhd"
+vhdl zylin "zpupkg.vhd"
+vhdl work "dmips_ram.vhd"
+vhdl zylin "zpu_top_bram_intstack.vhd"
+vhdl work "testlut.vhd"
diff --git a/zpu/hdl/zpu3/src/xmake.xst b/zpu/hdl/zpu3/src/xmake.xst
new file mode 100644
index 0000000..bfdb23f
--- /dev/null
+++ b/zpu/hdl/zpu3/src/xmake.xst
@@ -0,0 +1,53 @@
+set -tmpdir ../tmp
+set -xsthdpdir ../xst
+run
+-ifn xmake.filelist
+-ifmt mixed
+-ofn ../syn/ic300
+-ofmt NGC
+-p xc3s400-4-ft256
+-top ic300
+-opt_mode Area
+-opt_level 2
+-iuc NO
+-lso ic300.lso
+-keep_hierarchy NO
+-glob_opt AllClockNets
+-rtlview Yes
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-rom_style Auto
+-mux_extract YES
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-resource_sharing YES
+-mult_style auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-equivalent_register_removal NO
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set No
+-use_sync_reset No
+-iob true
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zpu3/src/zpu_config.vhd b/zpu/hdl/zpu3/src/zpu_config.vhd
new file mode 100644
index 0000000..506121c
--- /dev/null
+++ b/zpu/hdl/zpu3/src/zpu_config.vhd
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+
+	constant	Generate_Trace		: boolean := false;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
+	-- maximum address includes upper bit for IO registers
+	-- the rest is RAM
+	constant maxAddrBit			: integer := 14;
+	constant minAddrBit			: integer := 2;
+	-- This bit is set for read/writes to IO
+	-- FIX!!! eventually this should be set to wordSize-1 so as to
+	-- to make the address of IO independent of amount of memory
+	-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
+	-- libraries.
+	constant ioBit				: integer := maxAddrBit+1;
+	constant wordPower			: integer := 5;
+	constant wordSize			: integer := 2**wordPower;
+	
+end zpu_config;
diff --git a/zpu/hdl/zpu3/src/zpu_pipelined.vhd b/zpu/hdl/zpu3/src/zpu_pipelined.vhd
new file mode 100644
index 0000000..207939d
--- /dev/null
+++ b/zpu/hdl/zpu3/src/zpu_pipelined.vhd
@@ -0,0 +1,852 @@
+-- Company: ZPU3
+-- Engineer: Øyvind Harboe
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+
+entity zpu_top is
+    Port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  io_busy : in std_logic;
+	 		  io_read : in std_logic_vector(7 downto 0);
+	 		  io_write : out std_logic_vector(7 downto 0);
+			  io_addr : out std_logic_vector(maxAddrBit downto minAddrBit);
+			  io_writeEnable : out std_logic;
+			  io_readEnable : out std_logic;
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic);
+end zpu_top;
+
+architecture behave of zpu_top is
+
+signal		readIO : std_logic;
+
+
+
+signal memAWriteEnable : std_logic;
+signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal memAWrite : std_logic_vector(wordSize-1 downto 0);
+signal memARead : std_logic_vector(wordSize-1 downto 0);
+signal memBWriteEnable : std_logic;
+signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal memBWrite : std_logic_vector(wordSize-1 downto 0);
+signal memBRead : std_logic_vector(wordSize-1 downto 0);
+
+
+signal	busy 				: std_logic;
+
+signal	begin_inst			: std_logic;
+
+
+
+signal trace_opcode		: std_logic_vector(7 downto 0);
+signal	trace_pc				: std_logic_vector(maxAddrBit downto 0);
+signal	trace_sp				: std_logic_vector(maxAddrBit downto minAddrBit);
+signal	trace_topOfStack				: std_logic_vector(wordSize-1 downto 0);
+signal	trace_topOfStackB				: std_logic_vector(wordSize-1 downto 0);
+
+type DecodedOpcodeType is 
+(
+Decoded_Stall				,
+Decoded_Nop				,
+Decoded_Im					,
+Decoded_ImShift			,
+Decoded_LoadSP				,
+Decoded_StoreSP			,
+Decoded_AddSP				,
+Decoded_Emulate			,
+Decoded_Break				,
+Decoded_PushPC				,
+Decoded_PushSP				,
+Decoded_PopPC				,
+Decoded_Add				,
+Decoded_Or					,
+Decoded_And				,
+Decoded_Load				,
+Decoded_Not				,
+Decoded_Flip				,
+Decoded_Store				,
+Decoded_Storeb				,
+Decoded_PopSP				,
+Decoded_Ashiftleft 		,
+Decoded_Ashiftright		,
+Decoded_Lshiftright		,
+Decoded_Eqbranch			,
+Decoded_Neqbranch			,
+Decoded_Eq					,
+Decoded_Neq				,
+Decoded_Loadb				,
+Decoded_Lessthan			,
+Decoded_Lessthanorequal	,
+Decoded_Ulessthan			,
+Decoded_Ulessthanorequal	,
+Decoded_Duplicate			,
+Decoded_Duplicate2			,
+Decoded_Duplicate3			,
+Decoded_MoveDown,			
+Decoded_MoveDown2,			
+Decoded_MoveDown3,
+Decoded_Pushspadd,
+Decoded_Callpcrel,
+Decoded_Sub
+); 
+
+
+signal decode_pc : std_logic_vector(maxAddrBit downto 0);
+signal decode_fetchedPC : std_logic_vector(maxAddrBit downto 0);
+signal decode_fetched : std_logic;
+signal decode_opcode : std_logic_vector(OpCode_Size-1 downto 0);
+signal decode_opcodeWord : std_logic_vector(wordSize-1 downto 0);
+signal decode_starved : std_logic;
+signal decode_wordStarved : std_logic;
+signal decode_willBeStarved : std_logic;
+signal decode_idim_flag : std_logic;
+
+signal execute1_stall : std_logic;
+signal execute1_fetched : std_logic;
+signal execute1_decodedOpcode : DecodedOpcodeType;
+signal execute1_fetchedPC : std_logic_vector(maxAddrBit downto 0);
+signal execute1_sp : std_logic_vector(maxAddrBit downto minAddrBit);
+signal execute1_opcode : std_logic_vector(opCode_Size-1 downto 0);
+signal execute1_spOffset : std_logic_vector(4 downto 0);
+signal execute1_fetchPC : std_logic_vector(maxAddrBit downto 0);
+signal execute1_push1 : std_logic;
+signal execute1_push2 : std_logic;
+signal execute1_pop1 : std_logic;
+signal execute1_pop2 : std_logic;
+signal execute1_antialias : std_logic;
+signal execute1_savedTopOfStack : std_logic_vector(wordSize-1 downto 0);
+
+
+signal load_decodedOpcode : DecodedOpcodeType;
+signal load_opcode : std_logic_vector(opCode_Size-1 downto 0);
+signal load_spOffset : std_logic_vector(4 downto 0);
+signal load_stall : std_logic;
+signal load_willBeStalled : std_logic;
+
+signal execute2_opcode : std_logic_vector(opCode_Size-1 downto 0);
+signal execute2_topOfStack : std_logic_vector(wordSize-1 downto 0);
+signal execute2_addResult : std_logic_vector(wordSize-1 downto 0);
+signal execute2_topOfStackB : std_logic_vector(wordSize-1 downto 0);
+signal execute2_pc : std_logic_vector(maxAddrBit downto 0);
+signal execute2_sp : std_logic_vector(maxAddrBit downto minAddrBit);
+signal execute2_loading : std_logic;
+signal execute2_loadByte : std_logic;
+signal execute2_storeByte : std_logic;
+signal execute2_loadingDone : std_logic;
+signal execute2_decodedOpcode : DecodedOpcodeType;
+signal execute2_spOffset : std_logic_vector(4 downto 0);
+signal execute2_persistTopOfStack : std_logic;
+signal execute2_persistTopOfStackB : std_logic;
+signal execute2_resync : std_logic;
+signal execute2_resync2 : std_logic;
+signal execute2_resync3 : std_logic;
+signal execute2_resync4 : std_logic;
+signal execute2_resync5 : std_logic;
+signal execute2_resync6 : std_logic;
+signal execute2_resync7 : std_logic;
+signal execute2_resync8 : std_logic;
+signal execute2_resync9 : std_logic;
+signal execute2_resync10 : std_logic;
+			
+
+begin
+	traceFileGenerate:
+   if Generate_Trace generate
+	trace_file: trace port map (
+       	clk => clk,
+       	begin_inst => begin_inst,
+       	pc => trace_pc,
+		opcode => trace_opcode,
+		sp => trace_sp,
+		memA => trace_topOfStack,
+		memB => trace_topOfStackB,
+		busy => busy
+        );
+	end generate;
+
+
+	memory: dualport_ram port map (
+       	clk => clk,
+	memAWriteEnable => memAWriteEnable,
+	memAAddr => memAAddr,
+	memAWrite => memAWrite,
+	memARead => memARead,
+	memBWriteEnable => memBWriteEnable,
+	memBAddr => memBAddr,
+	memBWrite => memBWrite,
+	memBRead => memBRead
+        );
+
+	opcodeControl:
+	process(clk, areset)
+		variable compareA : signed(wordSize-1 downto 0);
+		variable compareB : signed(wordSize-1 downto 0);
+		variable execute1_doFetch : boolean;
+	begin
+		if areset = '1' then
+			break <= '0';
+			begin_inst <= '0';
+			memAAddr <= (others => '0');
+			memBAddr <= (others => '0');
+			memAWriteEnable <= '0';
+			memBWriteEnable <= '0';
+			memAWrite <= (others => '0');
+			memBWrite <= (others => '0');
+			
+			memBAddr <= (others => '0');
+			memBWrite <= (others => '0');
+
+
+			io_writeEnable <= '0';
+			io_readEnable <= '0';
+			io_addr <= (others => '0');
+			io_write <= (others => '0');
+		
+			-- stage 1. Don't care since this is driven by stage2
+			decode_pc <= (others => '0');
+			decode_fetched <= '0';
+			decode_starved <= '0';
+			decode_opcode <= (others => '0');
+			decode_opcodeWord  <= (others => '0');
+
+			-- stage 2.
+			execute1_antialias <= '0';
+			execute1_fetchPC <= (others => '0');
+			execute1_fetched <= '0';
+			execute1_decodedOpcode <= Decoded_Stall; 
+			execute1_sp <= (2 => '0', others => '1'); 
+			execute1_push1 <= '0';
+			execute1_push2 <= '0';
+			execute1_pop1 <= '0';
+			execute1_pop2 <= '0';
+			execute1_stall <= '1';
+
+			-- stage 3
+			load_decodedOpcode <= Decoded_Stall;
+			load_stall <= '1';
+			load_willBeStalled <= '1';
+
+			-- stage 4
+			decode_idim_flag <= '0';
+			execute2_pc <= (others => '0');
+			execute2_sp <= (2 => '0', others => '1'); 
+			execute2_loading <= '0';
+			execute2_loadByte <= '0';
+			execute2_storeByte <= '0';
+			execute2_loadingDone <= '0';
+			execute2_decodedOpcode <= Decoded_Stall;
+			execute2_resync <= '1';
+			execute2_resync2 <= '0';
+			execute2_resync3 <= '0';
+			execute2_resync4 <= '0';
+			execute2_resync5 <= '0';
+			execute2_resync6 <= '0';
+			execute2_resync7 <= '0';
+			execute2_resync8 <= '0';
+			execute2_resync9 <= '0';
+			execute2_resync10 <= '0';
+			execute2_persistTopOfStack <= '0';
+			execute2_persistTopOfStackB <= '0';
+
+			-- stage 5 
+			memBWriteEnable <= '0';
+			
+			
+		elsif (clk'event and clk = '1') then
+			memAWriteEnable <= '0';
+			memBWriteEnable <= '0';
+			io_writeEnable <= '0';
+			io_readEnable <= '0';
+			begin_inst <= '0';
+
+			-- stage0: fetch
+			decode_willBeStarved <= '0';
+			if (decode_fetched='1') then
+				-- resync #4
+				decode_opcodeWord <= memARead;
+				decode_pc <= decode_fetchedPC;
+			elsif (decode_pc(minAddrBit-1 downto 0)=b"11") then
+				decode_willBeStarved <= '1';
+			else
+				-- we can continue decoding.
+				decode_pc <= decode_pc + 1;
+			end if;
+			
+			-- stage 0b: move to byte..
+			-- resync #5
+			decode_starved <= decode_willBeStarved;
+			case decode_pc(minAddrBit-1 downto 0) is
+				when "00" 	=> decode_opcode <= decode_opcodeWord(31 downto 24);
+				when "01" 	=> decode_opcode <= decode_opcodeWord(23 downto 16);
+				when "10" 	=> decode_opcode <= decode_opcodeWord(15 downto 8);
+				when others	=> decode_opcode <= decode_opcodeWord(7 downto 0);
+			end case;
+			
+			-- stage1: decode 1
+			execute1_opcode <= decode_opcode;
+
+			execute1_spOffset(4)<=not decode_opcode(4);
+			execute1_spOffset(3 downto 0)<=decode_opcode(3 downto 0);
+
+			execute1_decodedOpcode<=Decoded_Break;
+
+			decode_idim_flag <= '0';
+
+			-- resync #6
+			-- resync #1
+			if (decode_starved = '1') then
+				execute1_decodedOpcode<=Decoded_Stall;
+				decode_idim_flag <= decode_idim_flag;
+			elsif (decode_opcode(7 downto 7)=OpCode_Im) then
+				decode_idim_flag <= '1';
+				if (decode_idim_flag = '0') then
+					execute1_decodedOpcode<=Decoded_Im;
+				else
+					execute1_decodedOpcode<=Decoded_ImShift;
+				end if;
+			elsif (decode_opcode(7 downto 5)=OpCode_StoreSP) then
+				if (decode_opcode(4 downto 0)=b"10001") then
+					execute1_decodedOpcode<=Decoded_MoveDown;
+				elsif (decode_opcode(4 downto 0)=b"10010") then
+					execute1_decodedOpcode<=Decoded_MoveDown2;
+--				elsif (decode_opcode(4 downto 0)=b"10011") then
+--					execute1_decodedOpcode<=Decoded_MoveDown3;
+				else
+					execute1_decodedOpcode<=Decoded_StoreSP;
+				end if;
+			elsif (decode_opcode(7 downto 5)=OpCode_LoadSP) then
+				if (decode_opcode(4 downto 0)=b"10000") then
+					execute1_decodedOpcode<=Decoded_Duplicate;
+				elsif (decode_opcode(4 downto 0)=b"10001") then
+					execute1_decodedOpcode<=Decoded_Duplicate2;
+				elsif (decode_opcode(4 downto 0)=b"10010") then
+					execute1_decodedOpcode<=Decoded_Duplicate3;
+				else
+					execute1_decodedOpcode<=Decoded_LoadSP;
+				end if;
+			elsif (decode_opcode(7 downto 5)=OpCode_Emulate) then
+				execute1_decodedOpcode<=Decoded_Emulate;
+				if decode_opcode(5 downto 0)=OpCode_Neqbranch then
+					execute1_decodedOpcode <= Decoded_Neqbranch;
+				elsif decode_opcode(5 downto 0)=OpCode_Eq then
+					execute1_decodedOpcode <= Decoded_Eq;
+				elsif decode_opcode(5 downto 0)=OpCode_Lessthan then
+					execute1_decodedOpcode <= Decoded_Lessthan;
+				elsif decode_opcode(5 downto 0)=OpCode_Ulessthan then
+					execute1_decodedOpcode <= Decoded_Ulessthan;
+				elsif decode_opcode(5 downto 0)=OpCode_Loadb then
+					execute1_decodedOpcode <= Decoded_Loadb;
+				elsif decode_opcode(5 downto 0)=OpCode_Storeb then
+					execute1_decodedOpcode <= Decoded_Storeb;
+				elsif decode_opcode(5 downto 0)=OpCode_Pushspadd then
+					execute1_decodedOpcode <= Decoded_Pushspadd;
+				elsif decode_opcode(5 downto 0)=OpCode_Callpcrel then
+					execute1_decodedOpcode <= Decoded_Callpcrel;
+				elsif decode_opcode(5 downto 0)=OpCode_Sub then
+					execute1_decodedOpcode <= Decoded_Sub;
+				end if;
+			elsif (decode_opcode(7 downto 4)=OpCode_AddSP) then
+				if (decode_opcode(3 downto 0) = 0) then
+					execute1_decodedOpcode<=Decoded_Ashiftleft;
+				elsif (decode_opcode(3 downto 0) = 1) then
+--					execute1_decodedOpcode<=Decoded_AddSP;
+				elsif (decode_opcode(3 downto 0) = 2) then
+--					execute1_decodedOpcode<=Decoded_AddSP;
+				else
+					execute1_decodedOpcode<=Decoded_AddSP;
+				end if;
+			else
+				case decode_opcode(3 downto 0) is
+					when OpCode_Nop =>
+						execute1_decodedOpcode<=Decoded_Nop;
+					when OpCode_PushSP =>
+						execute1_decodedOpcode<=Decoded_PushSP;
+					when OpCode_PopPC =>
+						execute1_decodedOpcode<=Decoded_PopPC;
+					when OpCode_Add =>
+						execute1_decodedOpcode<=Decoded_Add;
+					when OpCode_Or =>
+						execute1_decodedOpcode<=Decoded_Or;
+					when OpCode_And =>
+						execute1_decodedOpcode<=Decoded_And;
+					when OpCode_Load =>
+						execute1_decodedOpcode<=Decoded_Load;
+					when OpCode_Not =>
+						execute1_decodedOpcode<=Decoded_Not;
+					when OpCode_Flip =>
+						execute1_decodedOpcode<=Decoded_Flip;
+					when OpCode_Store =>
+						execute1_decodedOpcode<=Decoded_Store;
+					when OpCode_PopSP =>
+						execute1_decodedOpcode<=Decoded_PopSP;
+					when others =>
+						execute1_decodedOpcode<=Decoded_Break;
+				end case;
+			end if;
+
+
+			-- stage 2: execute 1 - load stage.
+			-- 
+			-- the address must be known without using the value on top of the stack...
+			-- resync #3
+			execute1_fetched <= '0';
+			decode_fetched <= execute1_fetched; -- the value in memAAddr will be valid for 1 cycle only
+			decode_fetchedPC <= execute1_fetchedPC;
+			
+			if (execute1_fetchPC(1 downto 0)/=b"00") then
+				execute1_fetchPC <= execute1_fetchPC+1;
+			end if;
+
+			execute1_push1 <= '0';
+			execute1_push2 <= execute1_push1;
+			execute1_pop1 <= '0';
+			execute1_pop2 <= execute1_pop1;
+			
+			if ((execute1_push1 and execute1_push2)='1') then
+				memAWrite <= execute2_topOfStack;
+			else
+				memAWrite <= execute2_topOfStackB;
+			end if;
+			
+			-- resync #7
+			case execute1_decodedOpcode is
+				when Decoded_Neqbranch | Decoded_MoveDown3 | Decoded_Load | Decoded_Loadb | Decoded_Store | Decoded_Storeb | Decoded_Emulate | Decoded_PopSP | Decoded_PopPC| Decoded_Callpcrel =>
+					execute1_stall <= '1';
+				when others =>
+					-- nothing...
+			end case;
+			
+			execute1_antialias <= load_stall;
+			execute1_doFetch := false;
+			case execute1_decodedOpcode is
+				when Decoded_PushSP | Decoded_Emulate =>
+					execute1_sp <= execute1_sp - 1;
+					execute1_push1 <= '1';
+					execute1_doFetch := true;
+				when Decoded_Duplicate3 =>
+					memAWriteEnable <= ((execute1_push1 and execute1_push2) or
+					                   (execute1_push1 and not execute1_pop2) or
+					                   (execute1_push2 and not execute1_pop1)) and 
+					                   (not execute1_antialias and not execute1_stall);
+					memAAddr <= execute1_sp + 2;
+					execute1_sp <= execute1_sp - 1;
+					execute1_push1 <= '1';
+				when Decoded_Im | Decoded_Duplicate | Decoded_Duplicate2 =>
+					execute1_sp <= execute1_sp - 1;
+					execute1_push1 <= '1';
+					execute1_doFetch := true;
+				when Decoded_LoadSP =>
+					memAAddr <= execute1_sp+execute1_spOffset;
+					execute1_sp <= execute1_sp - 1;
+					execute1_push1 <= '1';
+				when Decoded_AddSP =>
+					memAAddr <= execute1_sp+execute1_spOffset;
+				when Decoded_MoveDown2 =>
+					execute1_sp <= execute1_sp + 1;
+					execute1_pop1 <= '1';
+					execute1_doFetch := true;
+				when Decoded_Ulessthan | Decoded_Lessthan | Decoded_Eq | Decoded_Neqbranch | Decoded_MoveDown3 | Decoded_MoveDown | Decoded_Add | Decoded_Sub | Decoded_Or | Decoded_And | Decoded_PopPC | Decoded_StoreSP =>
+					-- be afraid :-)
+					memAWriteEnable <= ((execute1_push1 and execute1_push2) or
+					                   (execute1_push1 and not execute1_pop2) or
+					                   (execute1_push2 and not execute1_pop1)) and 
+					                   (not execute1_antialias and not execute1_stall);
+					memAAddr <= execute1_sp + 2;
+					execute1_sp <= execute1_sp + 1;
+					execute1_pop1 <= '1';
+				when others =>
+					execute1_doFetch := true;
+			end case;
+
+			if execute1_doFetch then
+				-- resync #2
+				-- some instruction that does not change the stack pointer
+				-- and does not need use a memory operand.
+				-- We can fetch the next word to be decoded to avoid stalls
+				execute1_fetchPC <= execute1_fetchPC+1;
+				memAAddr <= execute1_fetchPC(maxAddrBit downto minAddrBit);
+				execute1_fetchedPC <= execute1_fetchPC;
+				execute1_fetched <= '1';
+			end if;
+			
+			
+			-- stage 3: fetching memory takes 1 cycle
+			-- here we also verify that we've fetched & decoded the right
+			-- opcode.
+			-- resync #8
+			load_decodedOpcode <= execute1_decodedOpcode;
+			load_opcode <= execute1_opcode;
+			load_spOffset <= execute1_spOffset;
+			load_stall <= execute1_stall;
+			-- resync #9
+			if (load_stall = '1') then
+				execute2_decodedOpcode <= Decoded_Stall;
+			else
+				execute2_decodedOpcode <= load_decodedOpcode;
+			end if;
+			execute2_opcode <= load_opcode;
+			execute2_spOffset <= load_spOffset;
+			
+			-- stage 4: execute 2 - we now have both operands. This is the
+			-- main execute stage...
+			begin_inst <= '1';
+			trace_pc <= execute2_pc;
+			trace_opcode <= execute2_opcode;
+			trace_sp <=	execute2_sp;
+			trace_topOfStack <=	execute2_topOfStack;
+			trace_topOfStackB <=	execute2_topOfStackB;
+			
+			execute2_pc <= execute2_pc + 1;
+			execute2_loading <= '0';
+			memBWriteEnable <= '0';
+			
+			case execute2_decodedOpcode is
+				when Decoded_PopSP =>
+					execute2_sp <= execute2_topOfStack(maxAddrBit downto minAddrBit);
+
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp + 1;
+					memBWrite <= execute2_topOfStackB;
+					execute2_resync <= '1';
+				when Decoded_Callpcrel =>
+					execute2_topOfStack <= (others => DontCareValue);
+					execute2_topOfStack(maxAddrBit downto 0) <= execute2_pc + 1;
+					execute2_pc <= execute2_pc + execute2_topOfStack(maxAddrBit downto 0);
+					execute2_persistTopOfStack <= '1';
+				when Decoded_PopPC =>
+					execute2_pc <= execute2_topOfStack(maxAddrBit downto 0);
+					execute2_sp <= execute2_sp + 1;
+
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp + 1;
+					memBWrite <= execute2_topOfStackB;
+					execute2_resync <= '1';
+				when Decoded_Emulate =>
+					execute2_sp <= execute2_sp - 1;
+					
+					execute2_topOfStack <= (others => DontCareValue);
+					execute2_topOfStack(maxAddrBit downto 0) <= execute2_pc + 1;
+					execute2_topOfStackB <= execute2_topOfStack;
+					
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp+1;
+					memBWrite <= execute2_topOfStackB;
+					-- The emulate address is:
+					--        98 7654 3210
+					-- 0000 00aa aaa0 0000
+					execute2_pc <= (others => '0');
+					execute2_pc(9 downto 5) <= execute2_opcode(4 downto 0);
+					execute2_persistTopOfStack <= '1';
+				when Decoded_Im =>
+					execute2_sp <= execute2_sp - 1;
+					for i in wordSize-1 downto 7 loop
+						execute2_topOfStack(i) <= execute2_opcode(6);
+					end loop;
+					execute2_topOfStack(6 downto 0) <= execute2_opcode(6 downto 0);
+	
+					execute2_topOfStackB <= execute2_topOfStack;
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp + 1;
+					memBWrite <= execute2_topOfStackB;
+				when Decoded_ImShift =>
+					execute2_topOfStack(wordSize-1 downto 7) <= execute2_topOfStack(wordSize-8 downto 0);
+					execute2_topOfStack(6 downto 0) <= execute2_opcode(6 downto 0);
+				when Decoded_LoadSP =>
+					execute2_sp <= execute2_sp - 1;
+					execute2_topOfStack <= memARead;
+					execute2_topOfStackB <= execute2_topOfStack;
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp + 1;
+					memBWrite <= execute2_topOfStackB;
+				when Decoded_Break =>
+					report "Break instruction encountered" severity failure;
+					break <= '1';
+				when Decoded_PushSP =>
+					execute2_topOfStack <= (others => DontCareValue);
+					execute2_topOfStack(maxAddrBit downto minAddrBit) <= execute2_sp;
+
+					execute2_sp <= execute2_sp - 1;
+					execute2_topOfStackB <= execute2_topOfStack;
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp + 1;
+					memBWrite <= execute2_topOfStackB;
+				when Decoded_Add =>
+					execute2_sp <= execute2_sp + 1;
+					execute2_topOfStack <= execute2_topOfStackB + execute2_topOfStack;
+					execute2_topOfStackB <= memARead;
+				when Decoded_Sub =>
+					execute2_sp <= execute2_sp + 1;
+					execute2_topOfStack <= execute2_topOfStackB - execute2_topOfStack;
+					execute2_topOfStackB <= memARead;
+				when Decoded_AddSP =>
+					execute2_topOfStack <= execute2_topOfStack + memARead;
+				when Decoded_Or =>
+					execute2_sp <= execute2_sp + 1;
+					execute2_topOfStack <= execute2_topOfStackB or execute2_topOfStack;
+					execute2_topOfStackB <= memARead;
+				when Decoded_And =>
+					execute2_sp <= execute2_sp + 1;
+					execute2_topOfStack <= execute2_topOfStackB and execute2_topOfStack;
+					execute2_topOfStackB <= memARead;
+				when Decoded_Load | Decoded_Loadb | Decoded_Storeb  =>
+					if (execute2_topOfStack(ioBit)='1') then
+						io_addr <= execute2_topOfStack(maxAddrBit downto minAddrBit);
+						io_readEnable <= '1';
+					else
+						memAAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit);
+						execute1_fetched <= '0';
+					end if;
+					if (execute2_decodedOpcode = Decoded_Loadb) then
+						execute2_loadByte <= '1';
+					else
+						execute2_loadByte <= '0';
+					end if;
+					if (execute2_decodedOpcode = Decoded_Storeb) then
+						execute2_storeByte <= '1';
+					else
+						execute2_storebyte <= '0';
+					end if;
+					execute2_loading <= '1';
+				when Decoded_Ashiftleft =>
+					execute2_topOfStack(wordSize-1 downto 1) <= execute2_topOfStack(wordSize-2 downto 0);
+					execute2_topOfStack(0) <= '0'; 
+				when Decoded_MoveDown =>
+					execute2_sp <= execute2_sp + 1;
+					execute2_topOfStackB <= memARead;
+				when Decoded_MoveDown2 =>
+					execute2_sp <= execute2_sp + 1;
+					execute2_topOfStack <= execute2_topOfStackB;
+					execute2_topOfStackB <= execute2_topOfStack;
+				when Decoded_MoveDown3 =>
+					execute2_sp <= execute2_sp + 1;
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp+execute2_spOffset;
+					memBWrite <= execute2_topOfStack;
+
+					execute2_topOfStack <= execute2_topOfStackB;
+					execute2_topOfStackB <= memARead;
+					execute2_persistTopOfStack <= '1';
+				when Decoded_Duplicate =>
+					execute2_topOfStackB <= execute2_topOfStack;
+					execute2_sp <= execute2_sp - 1;
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp + 1;
+					memBWrite <= execute2_topOfStackB;
+				when Decoded_Duplicate2 =>
+					execute2_topOfStack <= execute2_topOfStackB;
+					execute2_topOfStackB <= execute2_topOfStack;
+					execute2_sp <= execute2_sp - 1;
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp + 1;
+					memBWrite <= execute2_topOfStackB;
+				when Decoded_Duplicate3 =>
+					execute2_topOfStack <= memARead;
+					execute2_topOfStackB <= execute2_topOfStack;
+					execute2_sp <= execute2_sp - 1;
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp + 1;
+					memBWrite <= execute2_topOfStackB;
+				when Decoded_Pushspadd =>
+					execute2_topOfStack <= (others => DontCareValue);
+					execute2_topOfStack(maxAddrBit downto minAddrBit) <= execute2_sp + execute2_topOfStack(maxAddrBit-minAddrBit downto 0);
+				when Decoded_Not =>
+					execute2_topOfStack <= not execute2_topOfStack;
+				when Decoded_Flip =>
+					for i in 0 to wordSize-1 loop
+						execute2_topOfStack(i) <= execute2_topOfStack(wordSize-1-i);
+		  			end loop;
+				when Decoded_Store =>
+					execute2_sp <= execute2_sp + 2;
+					if (execute2_topOfStack(ioBit)='0') then
+						memBAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit);
+						memBWrite <= execute2_topOfStackB;
+						memBWriteEnable <= '1';
+					else
+						io_addr <= execute2_topOfStack(maxAddrBit downto minAddrBit);
+						io_write <= execute2_topOfStackB(7 downto 0);
+						io_writeEnable <= '1';
+					end if;
+					execute2_resync <= '1';
+				when Decoded_StoreSP =>
+					execute2_sp <= execute2_sp + 1;
+					memBWriteEnable <= '1';
+					memBAddr <= execute2_sp+execute2_spOffset;
+					memBWrite <= execute2_topOfStack;
+
+					execute2_topOfStack <= execute2_topOfStackB;
+					execute2_topOfStackB <= memARead;
+                when Decoded_Neqbranch =>
+                	execute2_sp <= execute2_sp + 2;
+                	if (execute2_topOfStackB/=0) then
+                		execute2_pc <= execute2_topOfStack(maxAddrBit downto 0) + execute2_pc;
+                	end if;
+					execute2_resync <= '1';
+                when Decoded_Eq =>
+                	execute2_sp <= execute2_sp + 1;
+            		execute2_topOfStack <= (others => '0');
+                	if (execute2_topOfStack=execute2_topOfStackB) then
+                		execute2_topOfStack(0) <= '1';
+                	end if;
+					execute2_topOfStackB <= memARead;
+                when Decoded_Ulessthan =>
+                	execute2_sp <= execute2_sp + 1;
+            		execute2_topOfStack <= (others => '0');
+                	if (execute2_topOfStack<execute2_topOfStackB) then
+                		execute2_topOfStack(0) <= '1';
+                	end if;
+					execute2_topOfStackB <= memARead;
+                when Decoded_Lessthan =>
+                	execute2_sp <= execute2_sp + 1;
+            		execute2_topOfStack <= (others => '0');
+            		compareA := signed(execute2_topOfStack);
+            		compareB := signed(execute2_topOfStackB);
+                	if (compareA<compareB) then
+                		execute2_topOfStack(0) <= '1';
+                	end if;
+					execute2_topOfStackB <= memARead;
+				when Decoded_Stall =>
+					begin_inst <= '0'; 
+					execute2_pc <= execute2_pc;
+				when others =>
+					-- nop
+			end case;
+			
+			-- load cycle...
+			execute2_loadingDone <= execute2_loading;
+			if (execute2_loadingDone ='1') then
+				if (execute2_topOfStack(ioBit)='1') then
+					if (io_busy = '0') then
+						execute2_topOfStack <= (others => '0');
+						execute2_topOfStack(7 downto 0) <= io_read;
+						execute2_persistTopOfStack <= '1';
+					else
+						execute2_loadingDone <= '1';
+					end if;
+				else
+					if (execute2_storeByte = '1') then
+						execute2_sp <= execute2_sp + 2;
+						memBWriteEnable <= '1';
+						memBAddr <= execute2_topOfStack(maxAddrBit downto minAddrBit);
+						memBWrite <= memARead;
+						case execute2_topOfStack(minAddrBit-1 downto 0) is
+							when "00" 	=> memBWrite(31 downto 24) <= execute2_topOfStackB(7 downto 0);
+							when "01" 	=> memBWrite(23 downto 16) <= execute2_topOfStackB(7 downto 0);
+							when "10" 	=> memBWrite(15 downto 8) <= execute2_topOfStackB(7 downto 0);
+							when others	=> memBWrite(7 downto 0) <= execute2_topOfStackB(7 downto 0);
+						end case;
+--						case execute2_topOfStack(0 downto 0) is
+--							when "1" 	=> memBWrite(15 downto 8) <= execute2_topOfStackB(7 downto 0);
+--							when others	=> memBWrite(7 downto 0) <= execute2_topOfStackB(7 downto 0);
+--						end case;
+						execute2_resync <= '1';
+					elsif (execute2_loadByte = '1') then
+						execute2_topOfStack <= (others => '0');
+						case execute2_topOfStack(minAddrBit-1 downto 0) is
+							when "00" 	=> execute2_topOfStack(7 downto 0) <= memARead(31 downto 24);
+							when "01" 	=> execute2_topOfStack(7 downto 0) <= memARead(23 downto 16);
+							when "10" 	=> execute2_topOfStack(7 downto 0) <= memARead(15 downto 8);
+							when others	=> execute2_topOfStack(7 downto 0) <= memARead(7 downto 0);
+						end case;
+--						case execute2_topOfStack(0 downto 0) is
+--							when "1" 	=> execute2_topOfStack(7 downto 0) <= memARead(15 downto 8);
+--							when others	=> execute2_topOfStack(7 downto 0) <= memARead(7 downto 0);
+--						end case;
+						execute2_persistTopOfStack <= '1';
+					else
+						execute2_topOfStack <= memARead;
+						execute2_persistTopOfStack <= '1';
+					end if;
+				end if;
+			end if;
+
+			-- write top of stack...
+			execute2_persistTopOfStackB <= execute2_persistTopOfStack;
+			if (execute2_persistTopOfStack = '1') then
+				execute2_persistTopOfStack <= '0';
+				memBWriteEnable <= '1';
+				memBAddr <= execute2_sp;
+				memBWrite <= execute2_topOfStack;
+			end if;
+			if (execute2_persistTopOfStackB = '1') then
+				memBWriteEnable <= '1';
+				memBAddr <= execute2_sp+1;
+				memBWrite <= execute2_topOfStackB;
+				
+				execute2_resync <= '1';
+			end if;
+			
+			-- here we resync the pipeline.
+			-- a number of things have to happen on certain cycles 
+			execute2_resync2 <= execute2_resync;
+			execute2_resync3 <= execute2_resync2;
+			execute2_resync4 <= execute2_resync3;
+			execute2_resync5 <= execute2_resync4;
+			execute2_resync6 <= execute2_resync5;
+			execute2_resync7 <= execute2_resync6;
+			execute2_resync8 <= execute2_resync7;
+			execute2_resync9 <= execute2_resync8;
+			execute2_resync10 <= execute2_resync9;
+			
+			if (execute2_resync = '1' ) then
+				-- resync #1
+				execute2_resync <= '0';
+				decode_starved <= '1';
+				memAAddr <= execute2_sp;
+			end if;
+			if (execute2_resync2 = '1') then
+				-- resync #2
+				execute1_fetchPC <= execute2_pc;
+				memAAddr <= execute2_sp + 1;
+			end if;
+			if (execute2_resync3 = '1') then
+				-- resync #3
+				execute2_topOfStack <= memARead;
+			end if;
+			if (execute2_resync4 = '1') then
+				-- resync #4
+				-- during this cycle the address is set to the opcode
+				execute2_topOfStackB <= memARead;
+			end if;
+			if (execute2_resync5 = '1') then
+				-- resync #5
+				execute1_pop1 <= '0';
+				execute1_push1 <= '0';
+			end if;
+			if (execute2_resync6 = '1') then
+				-- resync #6
+				decode_idim_flag <= '0';
+				execute1_pop1 <= '0';
+				execute1_push1 <= '0';
+			end if;
+			if (execute2_resync7 = '1') then
+				-- resync #7
+				execute1_sp <= execute2_sp;
+				execute1_stall <= '0';
+			end if;
+			if (execute2_resync8 = '1') then
+				-- resync #8
+--				load_stall <= '0';
+			end if;
+			if (execute2_resync9 = '1') then
+				-- resync #9
+			end if;
+			if (execute2_resync10 = '1') then
+			end if;
+			
+			
+
+
+		end if;
+	end process;
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu3/src/zpu_top.vhd b/zpu/hdl/zpu3/src/zpu_top.vhd
new file mode 100644
index 0000000..0ac6df4
--- /dev/null
+++ b/zpu/hdl/zpu3/src/zpu_top.vhd
@@ -0,0 +1,421 @@
+-- Company: ZPU3
+-- Engineer: Øyvind Harboe
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+
+entity zpu_top is
+    Port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  io_busy : in std_logic;
+	 		  io_read : in std_logic_vector(7 downto 0);
+	 		  io_write : out std_logic_vector(7 downto 0);
+			  io_addr : out std_logic_vector(maxAddrBit downto minAddrBit);
+			  io_writeEnable : out std_logic;
+			  io_readEnable : out std_logic;
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic);
+end zpu_top;
+
+architecture behave of zpu_top is
+
+signal		readIO : std_logic;
+
+
+
+signal memAWriteEnable : std_logic;
+signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal memAWrite : std_logic_vector(wordSize-1 downto 0);
+signal memARead : std_logic_vector(wordSize-1 downto 0);
+signal memBWriteEnable : std_logic;
+signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal memBWrite : std_logic_vector(wordSize-1 downto 0);
+signal memBRead : std_logic_vector(wordSize-1 downto 0);
+
+
+
+signal	pc				: std_logic_vector(maxAddrBit downto 0);
+signal	sp				: std_logic_vector(maxAddrBit downto minAddrBit);
+
+signal	idim_flag			: std_logic;
+
+--signal	storeToStack		: std_logic;
+--signal	fetchNextInstruction		: std_logic;
+--signal	extraCycle			: std_logic;
+signal	busy 				: std_logic;
+--signal	fetching			: std_logic;
+
+signal	begin_inst			: std_logic;
+
+
+
+signal trace_opcode		: std_logic_vector(7 downto 0);
+signal	trace_pc				: std_logic_vector(maxAddrBit downto 0);
+signal	trace_sp				: std_logic_vector(maxAddrBit downto minAddrBit);
+signal	trace_topOfStack				: std_logic_vector(wordSize-1 downto 0);
+signal	trace_topOfStackB				: std_logic_vector(wordSize-1 downto 0);
+
+-- state machine.
+
+subtype State_Type is std_logic_vector(3 downto 0);
+constant State_Fetch		: State_Type := b"0000";
+constant State_WriteIODone	: State_Type := b"0001";
+constant State_Execute		: State_Type := b"0010";
+constant State_StoreToStack	: State_Type := b"0011";
+constant State_Add			: State_Type := b"0100";
+constant State_Or			: State_Type := b"0101";
+constant State_And			: State_Type := b"0110";
+constant State_Store		: State_Type := b"0111";
+constant State_ReadIO		: State_Type := b"1000";
+constant State_WriteIO		: State_Type := b"1001";
+constant State_Load			: State_Type := b"1010";
+constant State_FetchNext	: State_Type := b"1011";
+constant State_AddSP		: State_Type := b"1100";
+constant State_ReadIODone	: State_Type := b"1101";
+constant State_Decode		: State_Type := b"1110";
+constant State_Resync		: State_Type := b"1111";
+
+
+subtype DecodedOpcodeType is std_logic_vector(4 downto 0);
+constant Decoded_Nop		: DecodedOpcodeType := b"00000";
+constant Decoded_Im			: DecodedOpcodeType := b"00001";
+constant Decoded_ImShift	: DecodedOpcodeType := b"00010";
+constant Decoded_LoadSP		: DecodedOpcodeType := b"00011";
+constant Decoded_StoreSP	: DecodedOpcodeType := b"00100";
+constant Decoded_AddSP		: DecodedOpcodeType := b"00101";
+constant Decoded_Emulate	: DecodedOpcodeType := b"00110";
+constant Decoded_Break		: DecodedOpcodeType := b"00111";
+constant Decoded_PushPC		: DecodedOpcodeType := b"01000";
+constant Decoded_PushSP		: DecodedOpcodeType := b"01001";
+constant Decoded_PopPC		: DecodedOpcodeType := b"01010";
+constant Decoded_Add		: DecodedOpcodeType := b"01011";
+constant Decoded_Or			: DecodedOpcodeType := b"01100";
+constant Decoded_And		: DecodedOpcodeType := b"01101";
+constant Decoded_Load		: DecodedOpcodeType := b"01110";
+constant Decoded_Not		: DecodedOpcodeType := b"01111";
+constant Decoded_Flip		: DecodedOpcodeType := b"10000";
+constant Decoded_Store		: DecodedOpcodeType := b"10001";
+constant Decoded_PopSP		: DecodedOpcodeType := b"10010";
+
+signal opcode : std_logic_vector(OpCode_Size-1 downto 0);
+
+signal decodedOpcode : DecodedOpcodeType;
+
+signal state : State_Type;
+
+begin
+	traceFileGenerate:
+   if Generate_Trace generate
+	trace_file: trace port map (
+       	clk => clk,
+       	begin_inst => begin_inst,
+       	pc => trace_pc,
+		opcode => trace_opcode,
+		sp => trace_sp,
+		memA => trace_topOfStack,
+		memB => trace_topOfStackB,
+		busy => busy
+        );
+	end generate;
+
+
+	memory: dualport_ram port map (
+       	clk => clk,
+	memAWriteEnable => memAWriteEnable,
+	memAAddr => memAAddr,
+	memAWrite => memAWrite,
+	memARead => memARead,
+	memBWriteEnable => memBWriteEnable,
+	memBAddr => memBAddr,
+	memBWrite => memBWrite,
+	memBRead => memBRead
+        );
+
+	
+
+
+	opcodeControl:
+	process(clk, areset)
+		variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+		variable spOffset : std_logic_vector(4 downto 0);
+	begin
+		if areset = '1' then
+			state <= State_Resync;
+			break <= '0';
+			sp <= (2 => '0', others => '1'); 
+			pc <= (others => '0');
+			idim_flag <= '0';
+			begin_inst <= '0';
+			memAAddr <= (others => '0');
+			memBAddr <= (others => '0');
+			memAWriteEnable <= '0';
+			memBWriteEnable <= '0';
+			io_writeEnable <= '0';
+			io_readEnable <= '0';
+			decodedOpcode <= (others => '0');
+			memAWrite <= (others => '0');
+			memBWrite <= (others => '0');
+			opcode <= (others => '0');
+			io_addr <= (others => '0');
+			io_write <= (others => '0');
+		elsif (clk'event and clk = '1') then
+			memAWriteEnable <= '0';
+			memBWriteEnable <= '0';
+			-- This saves ca. 100 LUT's, by explicitly declaring that the
+			-- memAWrite can be left at whatever value if memAWriteEnable is
+			-- not set.
+			memAWrite <= (others => DontCareValue);
+			memBWrite <= (others => DontCareValue);
+			opcode <= (others => DontCareValue);
+--			io_addr <= (others => DontCareValue);
+--			io_write <= (others => DontCareValue);
+			spOffset := (others => DontCareValue);
+			memAAddr <= (others => DontCareValue);
+			memBAddr <= (others => DontCareValue);
+			
+			io_writeEnable <= '0';
+			io_readEnable <= '0';
+			begin_inst <= '0';
+
+			case state is
+				when State_Execute =>
+					state <= State_Fetch;
+					-- at this point:
+					-- memBRead contains opcode word
+					-- memARead contains top of stack
+					pc <= pc + 1;
+	
+					-- trace
+					begin_inst <= '1';
+					trace_pc <= pc;
+					trace_opcode <= opcode;
+					trace_sp <=	sp;
+					trace_topOfStack <= memARead;
+					trace_topOfStackB <= memBRead;
+
+					-- during the next cycle we'll be reading the next opcode	
+					spOffset(4):=not opcode(4);
+					spOffset(3 downto 0):=opcode(3 downto 0);
+	
+					case decodedOpcode is
+						when Decoded_Im =>
+							memAWriteEnable <= '1';
+							sp <= sp - 1;
+							memAAddr <= sp-1;
+							for i in wordSize-1 downto 7 loop
+								memAWrite(i) <= opcode(6);
+							end loop;
+							memAWrite(6 downto 0) <= opcode(6 downto 0);
+						when Decoded_ImShift =>
+							memAAddr <= sp;
+							memAWriteEnable <= '1';
+							memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0);
+							memAWrite(6 downto 0) <= opcode(6 downto 0);
+						when Decoded_StoreSP =>
+							memBWriteEnable <= '1';
+							memBAddr <= sp+spOffset;
+							memBWrite <= memARead;
+							sp <= sp + 1;
+							state <= State_Resync;
+						when Decoded_LoadSP =>
+							sp <= sp - 1;
+							memAAddr <= sp+spOffset;
+						when Decoded_Emulate =>
+							sp <= sp - 1;
+							memAWriteEnable <= '1';
+							memAAddr <= sp - 1;
+							memAWrite <= (others => DontCareValue);
+							memAWrite(maxAddrBit downto 0) <= pc + 1;
+							-- The emulate address is:
+							--        98 7654 3210
+							-- 0000 00aa aaa0 0000
+							pc <= (others => '0');
+							pc(9 downto 5) <= opcode(4 downto 0);
+						when Decoded_AddSP =>
+							memAAddr <= sp;
+							memBAddr <= sp+spOffset;
+							state <= State_AddSP;
+						when Decoded_Break =>
+							report "Break instruction encountered" severity failure;
+							break <= '1';
+						when Decoded_PushSP =>
+							memAWriteEnable <= '1';
+							memAAddr <= sp - 1;
+							sp <= sp - 1;
+							memAWrite <= (others => DontCareValue);
+							memAWrite(maxAddrBit downto minAddrBit) <= sp;
+						when Decoded_PopPC =>
+							pc <= memARead(maxAddrBit downto 0);
+							sp <= sp + 1;
+							state <= State_Resync;
+						when Decoded_Add =>
+							sp <= sp + 1;
+							state <= State_Add;
+						when Decoded_Or =>
+							sp <= sp + 1;
+							state <= State_Or;
+						when Decoded_And =>
+							sp <= sp + 1;
+							state <= State_And;
+						when Decoded_Load =>
+							if (memARead(ioBit)='1') then
+								io_addr <= memARead(maxAddrBit downto minAddrBit);
+								io_readEnable <= '1';
+								state <= State_ReadIO;
+							else 
+								memAAddr <= memARead(maxAddrBit downto minAddrBit);
+							end if;
+						when Decoded_Not =>
+							memAAddr <= sp(maxAddrBit downto minAddrBit);
+							memAWriteEnable <= '1';
+							memAWrite <= not memARead;
+						when Decoded_Flip =>
+							memAAddr <= sp(maxAddrBit downto minAddrBit);
+							memAWriteEnable <= '1';
+							for i in 0 to wordSize-1 loop
+								memAWrite(i) <= memARead(wordSize-1-i);
+				  			end loop;
+						when Decoded_Store =>
+							memBAddr <= sp + 1;
+							sp <= sp + 1;
+							if (memARead(ioBit)='1') then
+								state <= State_WriteIO;
+							else
+								state <= State_Store;
+							end if;
+						when Decoded_PopSP =>
+							sp <= memARead(maxAddrBit downto minAddrBit);
+							state <= State_Resync;
+						when Decoded_Nop =>	
+							memAAddr <= sp;
+						when others =>	
+							null; 
+					end case;
+				when State_ReadIO =>
+					if (io_busy = '0') then
+						state <= State_Fetch;
+						memAWriteEnable <= '1';
+						memAWrite <= (others => '0');
+						memAWrite(7 downto 0) <= io_read;
+					end if;
+				when State_WriteIO =>
+					sp <= sp + 1;
+					io_writeEnable <= '1';
+					io_addr <= memARead(maxAddrBit downto minAddrBit);
+					io_write <= memBRead(7 downto 0);
+					state <= State_WriteIODone;
+				when State_WriteIODone =>
+					if (io_busy = '0') then
+						state <= State_Resync;
+					end if;
+				when State_Fetch =>
+					-- We need to resync. During the *next* cycle
+					-- we'll fetch the opcode @ pc and thus it will
+					-- be available for State_Execute the cycle after
+					-- next
+					memBAddr <= pc(maxAddrBit downto minAddrBit);
+					state <= State_FetchNext;
+				when State_FetchNext =>
+					-- at this point memARead contains the value that is either
+					-- from the top of stack or should be copied to the top of the stack
+					memAWriteEnable <= '1';
+					memAWrite <= memARead; 
+					memAAddr <= sp;
+					memBAddr <= sp + 1;
+					state <= State_Decode;
+				when State_Decode =>
+					case pc(1 downto 0) is
+						when "00" 	=> tOpcode := memBRead(31 downto 24);
+						when "01" 	=> tOpcode := memBRead(23 downto 16);
+						when "10" 	=> tOpcode := memBRead(15 downto 8);
+						when others	=> tOpcode := memBRead(7 downto 0);
+					end case;
+					idim_flag <= tOpcode(7);
+					opcode <= tOpcode;
+					if (tOpcode(7 downto 7)=OpCode_Im) then
+						if (idim_flag='1') then
+							decodedOpcode<=Decoded_ImShift;
+						else
+							decodedOpcode<=Decoded_Im;
+						end if;
+					elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
+						decodedOpcode<=Decoded_StoreSP;
+					elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
+						decodedOpcode<=Decoded_LoadSP;
+					elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
+						decodedOpcode<=Decoded_Emulate;
+					elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
+						decodedOpcode<=Decoded_AddSP;
+					else
+						case tOpcode(3 downto 0) is
+							when OpCode_Break =>
+								decodedOpcode<=Decoded_Break;
+							when OpCode_PushSP =>
+								decodedOpcode<=Decoded_PushSP;
+							when OpCode_PopPC =>
+								decodedOpcode<=Decoded_PopPC;
+							when OpCode_Add =>
+								decodedOpcode<=Decoded_Add;
+							when OpCode_Or =>
+								decodedOpcode<=Decoded_Or;
+							when OpCode_And =>
+								decodedOpcode<=Decoded_And;
+							when OpCode_Load =>
+								decodedOpcode<=Decoded_Load;
+							when OpCode_Not =>
+								decodedOpcode<=Decoded_Not;
+							when OpCode_Flip =>
+								decodedOpcode<=Decoded_Flip;
+							when OpCode_Store =>
+								decodedOpcode<=Decoded_Store;
+							when OpCode_PopSP =>
+								decodedOpcode<=Decoded_PopSP;
+							when others =>
+								decodedOpcode<=Decoded_Nop;
+						end case;
+					end if;
+					-- during the State_Execute cycle we'll be fetching SP+1
+					memAAddr <= sp;
+					memBAddr <= sp + 1;
+					state <= State_Execute;
+				when State_Store =>
+					sp <= sp + 1;
+					memAWriteEnable <= '1';
+					memAAddr <= memARead(maxAddrBit downto minAddrBit);
+					memAWrite <= memBRead;
+					state <= State_Resync;
+				when State_AddSP =>
+					state <= State_Add;
+				when State_Add =>
+					memAAddr <= sp;
+					memAWriteEnable <= '1';
+					memAWrite <= memARead + memBRead;
+					state <= State_Fetch;
+				when State_Or =>
+					memAAddr <= sp;
+					memAWriteEnable <= '1';
+					memAWrite <= memARead or memBRead;
+					state <= State_Fetch;
+				when State_Resync =>
+					memAAddr <= sp;
+					state <= State_Fetch;
+				when State_And =>
+					memAAddr <= sp;
+					memAWriteEnable <= '1';
+					memAWrite <= memARead and memBRead;
+					state <= State_Fetch;
+				when others =>
+					null;
+			end case;				
+		end if;
+	end process;
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu3/src/zpu_top_medium.vhd b/zpu/hdl/zpu3/src/zpu_top_medium.vhd
new file mode 100644
index 0000000..4896b30
--- /dev/null
+++ b/zpu/hdl/zpu3/src/zpu_top_medium.vhd
@@ -0,0 +1,768 @@
+-- Company: ZPU3
+-- Engineer: Øyvind Harboe
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+
+entity zpu_top is
+    Port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  io_busy : in std_logic;
+	 		  io_read : in std_logic_vector(7 downto 0);
+	 		  io_write : out std_logic_vector(7 downto 0);
+			  io_addr : out std_logic_vector(maxAddrBit downto minAddrBit);
+			  io_writeEnable : out std_logic;
+			  io_readEnable : out std_logic;
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic);
+end zpu_top;
+
+architecture behave of zpu_top is
+
+signal		readIO : std_logic;
+
+
+
+signal memAWriteEnable : std_logic;
+signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal memAWrite : std_logic_vector(wordSize-1 downto 0);
+signal memARead : std_logic_vector(wordSize-1 downto 0);
+signal memBWriteEnable : std_logic;
+signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal memBWrite : std_logic_vector(wordSize-1 downto 0);
+signal memBRead : std_logic_vector(wordSize-1 downto 0);
+
+
+
+signal	pc				: std_logic_vector(maxAddrBit downto 0);
+signal	sp				: std_logic_vector(maxAddrBit downto minAddrBit);
+
+signal	idim_flag			: std_logic;
+
+--signal	storeToStack		: std_logic;
+--signal	fetchNextInstruction		: std_logic;
+--signal	extraCycle			: std_logic;
+signal	busy 				: std_logic;
+--signal	fetching			: std_logic;
+
+signal	begin_inst			: std_logic;
+
+
+
+signal trace_opcode		: std_logic_vector(7 downto 0);
+signal	trace_pc				: std_logic_vector(maxAddrBit downto 0);
+signal	trace_sp				: std_logic_vector(maxAddrBit downto minAddrBit);
+signal	trace_topOfStack				: std_logic_vector(wordSize-1 downto 0);
+
+-- state machine.
+
+subtype State_Type is std_logic_vector(4 downto 0);
+constant State_ResyncDecode	: State_Type := b"00000";
+constant State_WriteIODone	: State_Type := b"00001";
+constant State_Execute		: State_Type := b"00010";
+constant State_StoreToStack	: State_Type := b"00011";
+constant State_Add			: State_Type := b"00100";
+constant State_Or			: State_Type := b"00101";
+constant State_And			: State_Type := b"00110";
+constant State_Store		: State_Type := b"00111";
+constant State_ReadIO		: State_Type := b"01000";
+constant State_WriteIO		: State_Type := b"01001";
+constant State_Load			: State_Type := b"01010";
+constant State_ResyncStack	: State_Type := b"01011";
+constant State_AddSP		: State_Type := b"01100";
+constant State_ReadIODone	: State_Type := b"01101";
+constant State_Decode		: State_Type := b"01110";
+constant State_LoadByte1	: State_Type := b"01111";
+constant State_LoadByte2	: State_Type := b"10000";
+constant State_StoreByte1	: State_Type := b"10001";
+constant State_StoreByte2	: State_Type := b"10010";
+constant State_Mult1		: State_Type := b"10011";
+constant State_Mult2		: State_Type := b"10100";
+constant State_Mult3		: State_Type := b"10101";
+
+
+subtype DecodedOpcodeType is std_logic_vector(5 downto 0);
+constant Decoded_Nop				: DecodedOpcodeType := b"000000";
+constant Decoded_Im					: DecodedOpcodeType := b"000001";
+constant Decoded_ImShift			: DecodedOpcodeType := b"000010";
+constant Decoded_LoadSP				: DecodedOpcodeType := b"000011";
+constant Decoded_StoreSP			: DecodedOpcodeType := b"000100";
+constant Decoded_AddSP				: DecodedOpcodeType := b"000101";
+constant Decoded_Emulate			: DecodedOpcodeType := b"000110";
+constant Decoded_Break				: DecodedOpcodeType := b"000111";
+constant Decoded_PushPC				: DecodedOpcodeType := b"001000";
+constant Decoded_PushSP				: DecodedOpcodeType := b"001001";
+constant Decoded_PopPC				: DecodedOpcodeType := b"001010";
+constant Decoded_Add				: DecodedOpcodeType := b"001011";
+constant Decoded_Or					: DecodedOpcodeType := b"001100";
+constant Decoded_And				: DecodedOpcodeType := b"001101";
+constant Decoded_Load				: DecodedOpcodeType := b"001110";
+constant Decoded_Not				: DecodedOpcodeType := b"001111";
+constant Decoded_Flip				: DecodedOpcodeType := b"010000";
+constant Decoded_Store				: DecodedOpcodeType := b"010001";
+constant Decoded_PopSP				: DecodedOpcodeType := b"010010";
+constant Decoded_Ashiftleft 		: DecodedOpcodeType := b"010011";
+constant Decoded_Ashiftright		: DecodedOpcodeType := b"010100";
+constant Decoded_Lshiftright		: DecodedOpcodeType := b"010101";
+constant Decoded_Eqbranch			: DecodedOpcodeType := b"010110";
+constant Decoded_Neqbranch			: DecodedOpcodeType := b"010111";
+constant Decoded_Eq					: DecodedOpcodeType := b"011000";
+constant Decoded_Neq				: DecodedOpcodeType := b"011001";
+constant Decoded_Loadb				: DecodedOpcodeType := b"011010";
+constant Decoded_Lessthan			: DecodedOpcodeType := b"011011";
+constant Decoded_Lessthanorequal	: DecodedOpcodeType := b"011100";
+constant Decoded_Ulessthan			: DecodedOpcodeType := b"011101";
+constant Decoded_Ulessthanorequal	: DecodedOpcodeType := b"011110";
+constant Decoded_Storeb				: DecodedOpcodeType := b"011111";
+constant Decoded_Lshift2			: DecodedOpcodeType := b"100000";
+constant Decoded_DoubleIm			: DecodedOpcodeType := b"100001";
+constant Decoded_AddIm				: DecodedOpcodeType := b"100011";
+constant Decoded_Mult16x16			: DecodedOpcodeType := b"100100";
+constant Decoded_Swap				: DecodedOpcodeType := b"100101";
+constant Decoded_Callpcrel			: DecodedOpcodeType := b"100110";
+constant Decoded_Pushspadd			: DecodedOpcodeType := b"100111";
+
+
+signal mult1			: std_logic_vector(wordSize/2-1 downto 0);
+signal mult2			: std_logic_vector(wordSize/2-1 downto 0);
+signal multResult		: std_logic_vector(wordSize-1 downto 0);
+
+signal storeByte		: std_logic_vector(7 downto 0);
+signal byteSelect		: std_logic_vector(minAddrBit-1 downto 0);
+
+signal opcode : std_logic_vector(OpCode_Size-1 downto 0);
+signal opcode2 : std_logic_vector(OpCode_Size-1 downto 0);
+
+signal decodedOpcode : DecodedOpcodeType;
+
+signal state : State_Type;
+
+begin
+	traceFileGenerate:
+   if Generate_Trace generate
+	trace_file: trace port map (
+       	clk => clk,
+       	begin_inst => begin_inst,
+       	pc => trace_pc,
+		opcode => trace_opcode,
+		sp => trace_sp,
+		memA => trace_topOfStack,
+		busy => busy
+        );
+	end generate;
+
+
+	memory: dualport_ram port map (
+       	clk => clk,
+	memAWriteEnable => memAWriteEnable,
+	memAAddr => memAAddr,
+	memAWrite => memAWrite,
+	memARead => memARead,
+	memBWriteEnable => memBWriteEnable,
+	memBAddr => memBAddr,
+	memBWrite => memBWrite,
+	memBRead => memBRead
+        );
+
+
+	process(clk, areset)
+	begin
+		if (clk'event and clk = '1') then
+			multResult <= mult1 * mult2;
+		end if;
+	end process;
+	
+
+
+	opcodeControl:
+	process(clk, areset)
+		variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+		variable tOpcode2 : std_logic_vector(OpCode_Size-1 downto 0);
+		variable spOffset : std_logic_vector(4 downto 0);
+		variable spOffset2 : std_logic_vector(4 downto 0);
+		variable nextPC	: std_logic_vector(maxAddrBit downto 0);
+		variable pushspaddTemp	: std_logic_vector(maxAddrBit downto minAddrBit);
+		variable tempVal : std_logic_vector(wordSize-1 downto 0);
+		variable compareA : signed(wordSize-1 downto 0);
+		variable compareB : signed(wordSize-1 downto 0);
+	begin
+		if areset = '1' then
+			mult1 <= (others => '0');
+			mult2 <= (others => '0');
+			state <= State_ResyncDecode;
+			break <= '0';
+			sp <= (2 => '0', others => '1'); 
+			pc <= (others => '0');
+			idim_flag <= '0';
+			begin_inst <= '0';
+			memAAddr <= (others => '0');
+			memBAddr <= (others => '0');
+			memAWriteEnable <= '0';
+			memBWriteEnable <= '0';
+			io_writeEnable <= '0';
+			io_readEnable <= '0';
+			decodedOpcode <= (others => '0');
+			memAWrite <= (others => '0');
+			memBWrite <= (others => '0');
+			opcode <= (others => '0');
+			io_addr <= (others => '0');
+			io_write <= (others => '0');
+		elsif (clk'event and clk = '1') then
+			memAWriteEnable <= '0';
+			memBWriteEnable <= '0';
+			
+			io_writeEnable <= '0';
+			io_readEnable <= '0';
+			begin_inst <= '0';
+
+			case state is
+				when State_Decode =>
+					nextPC:=pc+1;
+					case pc(1 downto 0) is
+						when "00" 	=> tOpcode := memARead(31 downto 24);
+						when "01" 	=> tOpcode := memARead(23 downto 16);
+						when "10" 	=> tOpcode := memARead(15 downto 8);
+						when others	=> tOpcode := memARead(7 downto 0);
+					end case;
+					case nextPC(1 downto 0) is
+						when "00" 	=> tOpcode2 := memBRead(31 downto 24);
+						when "01" 	=> tOpcode2 := memBRead(23 downto 16);
+						when "10" 	=> tOpcode2 := memBRead(15 downto 8);
+						when others	=> tOpcode2 := memBRead(7 downto 0);
+					end case;
+					idim_flag <= tOpcode(7);
+					opcode <= tOpcode;
+					opcode2 <= tOpcode2;
+					if (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 4)=0 and tOpcode2(3 downto 0)=Opcode_Add and idim_flag='0') then
+						idim_flag <= '0';
+						decodedOpcode <= Decoded_AddIm;
+						nextPC := pc + 2;
+					elsif (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 7)=OpCode_Im and idim_flag='0') then
+						decodedOpcode <= Decoded_DoubleIm;
+						nextPC := pc + 2;
+					elsif (tOpcode(7 downto 4)=OpCode_AddSP and tOpcode(3 downto 0)=0 and 
+					    tOpcode2(7 downto 4)=OpCode_AddSP and tOpcode2(3 downto 0)=0) then
+						decodedOpcode <= Decoded_Lshift2;
+						nextPC := pc + 2;
+					elsif (tOpcode(7 downto 7)=OpCode_Im) then
+						if (idim_flag='1') then
+							decodedOpcode<=Decoded_ImShift;
+						else
+							decodedOpcode<=Decoded_Im;
+						end if;
+					elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
+						decodedOpcode<=Decoded_StoreSP;
+					elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
+						decodedOpcode<=Decoded_LoadSP;
+					elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
+						if tOpcode(5 downto 0)=OpCode_Eqbranch then
+							decodedOpcode <= Decoded_Eqbranch;
+						elsif tOpcode(5 downto 0)=OpCode_Neqbranch then
+							decodedOpcode <= Decoded_Neqbranch;
+						elsif tOpcode(5 downto 0)=OpCode_Eq then
+							decodedOpcode <= Decoded_Eq;
+						elsif tOpcode(5 downto 0)=OpCode_Neq then
+							decodedOpcode <= Decoded_Neq;
+						elsif tOpcode(5 downto 0)=OpCode_Lessthan then
+							decodedOpcode <= Decoded_Lessthan;
+						elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then
+							decodedOpcode <= Decoded_Lessthanorequal;
+						elsif tOpcode(5 downto 0)=OpCode_Ulessthan then
+							decodedOpcode <= Decoded_Ulessthan;
+						elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then
+							decodedOpcode <= Decoded_Ulessthanorequal;
+						elsif tOpcode(5 downto 0)=OpCode_Loadb then
+							decodedOpcode <= Decoded_Loadb;
+						elsif tOpcode(5 downto 0)=OpCode_Storeb then
+							decodedOpcode <= Decoded_Storeb;
+						elsif tOpcode(5 downto 0)=OpCode_Mult16x16 then
+							decodedOpcode <= Decoded_Mult16x16;
+						elsif tOpcode(5 downto 0)=OpCode_Swap then
+							decodedOpcode <= Decoded_Swap;
+						elsif tOpcode(5 downto 0)=OpCode_Callpcrel then
+							decodedOpcode <= Decoded_Callpcrel;
+						elsif tOpcode(5 downto 0)=OpCode_Pushspadd then
+							decodedOpcode <= Decoded_Pushspadd;
+--						elsif tOpcode(5 downto 0)=OpCode_Lshiftright then
+--							decodedOpcode <= Decoded_Lshiftright;
+--						elsif tOpcode(5 downto 0)=OpCode_Ashiftleft then
+--							decodedOpcode <= Decoded_Ashiftleft;
+--						elsif tOpcode(5 downto 0)=OpCode_Ashiftright then
+--							decodedOpcode <= Decoded_Ashiftright;
+						else
+							decodedOpcode<=Decoded_Emulate;
+						end if;
+					elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
+						decodedOpcode<=Decoded_AddSP;
+					else
+						case tOpcode(3 downto 0) is
+							when OpCode_Break =>
+								decodedOpcode<=Decoded_Break;
+							when OpCode_PushPC =>
+								decodedOpcode<=Decoded_PushPC;
+							when OpCode_PushSP =>
+								decodedOpcode<=Decoded_PushSP;
+							when OpCode_PopPC =>
+								decodedOpcode<=Decoded_PopPC;
+							when OpCode_Add =>
+								decodedOpcode<=Decoded_Add;
+							when OpCode_Or =>
+								decodedOpcode<=Decoded_Or;
+							when OpCode_And =>
+								decodedOpcode<=Decoded_And;
+							when OpCode_Load =>
+								decodedOpcode<=Decoded_Load;
+							when OpCode_Not =>
+								decodedOpcode<=Decoded_Not;
+							when OpCode_Flip =>
+								decodedOpcode<=Decoded_Flip;
+							when OpCode_Store =>
+								decodedOpcode<=Decoded_Store;
+							when OpCode_PopSP =>
+								decodedOpcode<=Decoded_PopSP;
+							when others =>
+								decodedOpcode<=Decoded_Nop;
+						end case;
+					end if;
+					-- Fetch the two next opcodes... :-)
+					memAAddr <= nextPC(maxAddrBit downto minAddrBit);
+					nextPC:=nextPC+1;
+					memBAddr <= nextPC(maxAddrBit downto minAddrBit);
+					state <= State_Execute;
+				when State_Execute =>
+					state <= State_Decode;
+					-- at this point:
+					-- memBRead contains opcode word
+					-- memARead contains top of stack
+					pc <= pc + 1;
+	
+					-- trace
+					begin_inst <= '1';
+					trace_pc <= pc;
+					trace_opcode <= opcode;
+					trace_sp <=	sp;
+					trace_topOfStack <= memARead;
+
+					-- during the next cycle we'll be reading the next opcode	
+					spOffset(4):=not opcode(4);
+					spOffset(3 downto 0):=opcode(3 downto 0);
+					spOffset2(4):=not opcode2(4);
+					spOffset2(3 downto 0):=opcode2(3 downto 0);
+
+					case decodedOpcode is
+							
+						when Decoded_DoubleIm =>
+							memAWriteEnable <= '1';
+							sp <= sp - 1;
+							memAAddr <= sp-1;
+							for i in wordSize-1 downto 14 loop
+								memAWrite(i) <= opcode(6);
+							end loop;
+							memAWrite(13 downto 7) <= opcode(6 downto 0);
+							memAWrite(6 downto 0) <= opcode2(6 downto 0);
+							memBAddr <= sp;
+							memBWrite <= memARead;
+							memBWriteEnable <= '1';
+							pc <= pc + 2;
+						when Decoded_Im =>
+							memAWriteEnable <= '1';
+							sp <= sp - 1;
+							memAAddr <= sp-1;
+							for i in wordSize-1 downto 7 loop
+								memAWrite(i) <= opcode(6);
+							end loop;
+							memAWrite(6 downto 0) <= opcode(6 downto 0);
+							memBAddr <= sp;
+							memBWrite <= memARead;
+							memBWriteEnable <= '1';
+						when Decoded_ImShift =>
+							memAAddr <= sp;
+							memAWriteEnable <= '1';
+							memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0);
+							memAWrite(6 downto 0) <= opcode(6 downto 0);
+							memBAddr <= sp + 1;
+						when Decoded_StoreSP =>
+							memAWriteEnable <= '1';
+							memAAddr <= sp+spOffset;
+							memAWrite <= memARead;
+							-- avoid address crashes.
+							memBAddr <= sp - 1;
+							sp <= sp + 1;
+							state <= State_ResyncDecode;
+						when Decoded_LoadSP =>
+							sp <= sp - 1;
+							if (spOffset = 0) then
+								-- This is a duplicate instruction.
+								memAAddr <= sp-1;
+								memAWriteEnable <= '1';
+								memAWrite <= memARead;
+							else 
+								memAAddr <= sp+spOffset;
+							end if;
+							memBAddr <= sp;
+							memBWrite <= memARead;
+							memBWriteEnable <= '1';
+						when Decoded_Callpcrel =>
+							memAWriteEnable <= '1';
+							memAAddr <= sp;
+							memAWrite <= (others => DontCareValue);
+							memAWrite(maxAddrBit downto 0) <= pc + 1;
+							memBAddr <= sp+1;
+							pc <= pc + memARead(maxAddrBit downto 0);
+							state <= State_ResyncDecode;
+						when Decoded_Emulate =>
+							sp <= sp - 1;
+							memAWriteEnable <= '1';
+							memAAddr <= sp - 1;
+							memAWrite <= (others => DontCareValue);
+							memAWrite(maxAddrBit downto 0) <= pc;
+							memBAddr <= sp;
+							memBWrite <= memARead;
+							memBWriteEnable <= '1';
+							-- The emulate address is:
+							--        98 7654 3210
+							-- 0000 00aa aaa0 0000
+							pc <= (others => '0');
+							pc(9 downto 5) <= opcode(4 downto 0);
+							state <= State_ResyncDecode;
+						when Decoded_AddSP =>
+							if spOffset=0 then
+								-- avoid address line crashes...
+								-- FIX!!! is this an issue?
+								-- oh-well. While we are at it, we've got a faster
+								-- shift operation without updating the toolchain.
+								memAWriteEnable <= '1';
+								memAAddr <= sp;
+								memAWrite <= memARead + memARead;
+								memBAddr <= sp+1;
+							else 
+								memAWriteEnable <= '1';
+								memAAddr <= sp;
+								memAWrite <= memARead;
+								memBAddr <= sp+spOffset;
+								state <= State_AddSP;
+							end if;
+						when Decoded_Break =>
+							report "Break instruction encountered" severity failure;
+							break <= '1';
+						when Decoded_PushPC =>
+							memAWriteEnable <= '1';
+							memAAddr <= sp - 1;
+							sp <= sp - 1;
+							memAWrite <= (others => DontCareValue);
+							memAWrite(maxAddrBit downto 0) <= pc;
+							memBAddr <= sp;
+							memBWrite <= memARead;
+							memBWriteEnable <= '1';
+						when Decoded_PushSP =>
+							memAWriteEnable <= '1';
+							memAAddr <= sp - 1;
+							sp <= sp - 1;
+							memAWrite <= (others => DontCareValue);
+							memAWrite(maxAddrBit downto minAddrBit) <= sp;
+							memBAddr <= sp;
+							memBWrite <= memARead;
+							memBWriteEnable <= '1';
+						when Decoded_Pushspadd =>
+							memAWriteEnable <= '1';
+							memAAddr <= sp;
+							memAWrite <= (others => DontCareValue);
+							pushspaddTemp := memARead(maxAddrBit-minAddrBit downto 0);
+							memAWrite(maxAddrBit downto minAddrBit) <= sp+pushspaddTemp;
+							memBAddr <= sp+1;
+						when Decoded_PopPC =>
+							memAAddr <= sp;
+							pc <= memARead(maxAddrBit downto 0);
+							sp <= sp + 1;
+							state <= State_ResyncDecode;
+						when Decoded_AddIm =>
+							memAWriteEnable <= '1';
+							memAAddr <= sp;
+							tempVal(wordSize-1 downto 7) := (others => tOpcode(6));
+							tempVal(6 downto 0) := tOpcode(6 downto 0);
+							memAWrite <= memARead + tempVal;
+							memBAddr <= sp + 1;
+							pc <= pc + 2;
+						when Decoded_Add =>
+							memAWriteEnable <= '1';
+							memAWrite <= memARead + memBRead;
+							memAAddr <= sp + 1;
+							memBAddr <= sp + 2;
+							sp <= sp + 1;
+						when Decoded_Or =>
+							sp <= sp + 1;
+							memAWriteEnable <= '1';
+							memAWrite <= memARead or memBRead;
+							memAWriteEnable <= '1';
+							memAAddr <= sp + 1;
+							memBAddr <= sp + 2;
+						when Decoded_And =>
+							sp <= sp + 1;
+							memAWriteEnable <= '1';
+							memAWrite <= memARead and memBRead;
+							memAWriteEnable <= '1';
+							memAAddr <= sp + 1;
+							memBAddr <= sp + 2;
+						when Decoded_Load =>
+							if (memARead(ioBit)='1') then
+								io_addr <= memARead(maxAddrBit downto minAddrBit);
+								io_readEnable <= '1';
+								state <= State_ReadIO;
+							else 
+								memAAddr <= memARead(maxAddrBit downto minAddrBit);
+								memBAddr <= sp + 1;
+							end if;
+						when Decoded_Swap =>
+							memAAddr <= sp;
+							memAWriteEnable <= '1';
+							memAWrite(wordSize/2-1 downto 0) <= memARead(wordSize-1 downto wordSize/2);
+							memAWrite(wordSize-1 downto wordSize/2) <= memARead(wordSize/2-1 downto 0);
+							memBAddr <= sp + 1;
+						when Decoded_Not =>
+							memAAddr <= sp;
+							memAWriteEnable <= '1';
+							memAWrite <= not memARead;
+							memBAddr <= sp + 1;
+						when Decoded_Flip =>
+							memAAddr <= sp;
+							memAWriteEnable <= '1';
+							for i in 0 to wordSize-1 loop
+								memAWrite(i) <= memARead(wordSize-1-i);
+				  			end loop;
+							memBAddr <= sp + 1;
+						when Decoded_Lshift2 =>
+							memAAddr <= sp;
+							memAWriteEnable <= '1';
+							memAWrite(1 downto 0) <= (others => '0');
+							memAWrite(wordSize-1 downto 2) <= memARead(wordSize-1-2 downto 0);
+							memBAddr <= sp + 1;
+							pc <= pc + 2;
+						when Decoded_Store =>
+							sp <= sp + 2;
+							if (memARead(ioBit)='1') then
+								io_writeEnable <= '1';
+								io_addr <= memARead(maxAddrBit downto minAddrBit);
+								io_write <= memBRead(7 downto 0);
+								state <= State_WriteIO;
+							else
+								memAWriteEnable <= '1';
+								memAAddr <= memARead(maxAddrBit downto minAddrBit);
+								memAWrite <= memBRead;
+								state <= State_ResyncDecode;
+							end if;
+						when Decoded_PopSP =>
+							sp <= memARead(maxAddrBit downto minAddrBit);
+							state <= State_ResyncDecode;
+	                    when Decoded_Ashiftleft =>
+	                    	memAWrite(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))) <=
+	                        memBRead(wordSize-conv_integer(memARead(wordPower-1 downto 0))-1 downto 0);      
+	                        if memARead(wordPower-1 downto 0)/=0 then
+	                        	memAWrite(conv_integer(memARead(wordPower-1 downto 0))-1 downto 0) <= (others => '0');
+	                        end if;
+	                        memAWriteEnable <= '1';
+	                        memAAddr <= sp + 1;
+	                        memBAddr <= sp + 2;
+	                        sp <= sp + 1;
+                      when Decoded_Ashiftright | Decoded_Lshiftright =>
+                            memAWrite(wordSize-1-conv_integer(memARead(wordPower-1 downto 0)) downto 0) <=
+                            memBRead(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0)));
+                            if memARead(wordPower-1 downto 0)/=0 then
+                            	if decodedOpcode=Decoded_Ashiftright and memBRead(wordSize-1)='1' then
+	    	                        memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '1');
+                            	else
+                	                memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '0');
+                            	end if;
+                            end if;
+	                        memAWriteEnable <= '1';
+                            memAAddr <= sp + 1;
+                            memBAddr <= sp + 2;
+	                        sp <= sp + 1;
+	                    when Decoded_Eqbranch =>
+	                    	sp <= sp + 2;
+	                    	if (memBRead=0) then
+	                    		pc <= memARead(maxAddrBit downto 0) + pc;
+	                    	end if;
+	                    	state <= State_ResyncDecode;
+	                    when Decoded_Neqbranch =>
+	                    	sp <= sp + 2;
+	                    	if (memBRead/=0) then
+	                    		pc <= memARead(maxAddrBit downto 0) + pc;
+	                    	end if;
+	                    	state <= State_ResyncDecode;
+	                    when Decoded_Eq =>
+	                    	sp <= sp + 1;
+                    		memAWrite <= (others => '0');
+	                    	if (memARead=memBRead) then
+	                    		memAWrite(0) <= '1';
+	                    	end if;
+							memAAddr <= sp + 1;
+							memAWriteEnable <= '1';
+							memBAddr <= sp + 2;
+	                    when Decoded_Neq =>
+	                    	sp <= sp + 1;
+                    		memAWrite <= (others => '0');
+	                    	if (memARead/=memBRead) then
+	                    		memAWrite(0) <= '1';
+	                    	end if;
+							memAAddr <= sp + 1;
+							memAWriteEnable <= '1';
+							memBAddr <= sp + 2;
+	                    when Decoded_Ulessthan =>
+	                    	sp <= sp + 1;
+                    		memAWrite <= (others => '0');
+	                    	if (memARead<memBRead) then
+	                    		memAWrite(0) <= '1';
+	                    	end if;
+							memAAddr <= sp + 1;
+							memAWriteEnable <= '1';
+							memBAddr <= sp + 2;
+	                    when Decoded_Ulessthanorequal =>
+	                    	sp <= sp + 1;
+                    		memAWrite <= (others => '0');
+	                    	if (memARead<=memBRead) then
+	                    		memAWrite(0) <= '1';
+	                    	end if;
+							memAAddr <= sp + 1;
+							memAWriteEnable <= '1';
+							memBAddr <= sp + 2;
+	                    when Decoded_Lessthan =>
+	                    	sp <= sp + 1;
+                    		memAWrite <= (others => '0');
+                    		compareA := signed(memARead);
+                    		compareB := signed(memBRead);
+	                    	if (compareA<compareB) then
+	                    		memAWrite(0) <= '1';
+	                    	end if;
+							memAAddr <= sp + 1;
+							memAWriteEnable <= '1';
+							memBAddr <= sp + 2;
+	                    when Decoded_Lessthanorequal =>
+	                    	sp <= sp + 1;
+                    		memAWrite <= (others => '0');
+                    		compareA := signed(memARead);
+                    		compareB := signed(memBRead);
+	                    	if (compareA<=compareB) then
+	                    		memAWrite(0) <= '1';
+	                    	end if;
+							memAAddr <= sp + 1;
+							memAWriteEnable <= '1';
+							memBAddr <= sp + 2;
+	                    when Decoded_Loadb =>
+	                    	byteSelect <= memARead(minAddrBit-1 downto 0);
+							memAAddr <= memARead(maxAddrBit downto minAddrBit);
+							state <= State_LoadByte1;
+	                    when Decoded_Storeb =>
+	                    	sp <= sp + 2;
+	                    	byteSelect <= memARead(minAddrBit-1 downto 0);
+	                    	storeByte <= memBRead(7 downto 0);
+							memAAddr <= memARead(maxAddrBit downto minAddrBit);
+							memBAddr <= sp;
+							state <= State_StoreByte1;
+						when Decoded_Mult16x16 =>
+							mult1 <= memARead(wordSize/2-1 downto 0);
+							mult2 <= memBRead(wordSize/2-1 downto 0);
+							sp <= sp + 1;
+							state <= State_Mult1;
+						when others =>
+							-- nop. Here we persist whatever was loaded into
+							-- memARead
+							memAAddr <= sp;
+							memAWriteEnable <= '1';
+							memAWrite <= memARead;
+							memBAddr <= sp + 1;
+							
+					end case;
+				when State_ReadIO =>
+					state <= State_ReadIODone;
+				when State_ReadIODone =>
+					if (io_busy = '0') then
+						state <= State_ResyncDecode;
+						memAWriteEnable <= '1';
+						memAWrite <= (others => '0');
+						memAWrite(7 downto 0) <= io_read;
+						memAAddr <= sp;
+					end if;
+				when State_WriteIO =>
+					state <= State_WriteIODone;
+				when State_WriteIODone =>
+					if (io_busy = '0') then
+						state <= State_ResyncDecode;
+					end if;
+				when State_ResyncDecode =>
+					memAAddr <= pc(maxAddrBit downto minAddrBit);
+					nextPC:=pc+1;
+					memBAddr <= nextPC(maxAddrBit downto minAddrBit);
+					state <= State_ResyncStack;
+				when State_ResyncStack =>
+					memAAddr <= sp;
+					memBAddr <= sp+1;
+					state <= State_Decode;
+				when State_AddSP =>
+					memAAddr <= pc(maxAddrBit downto minAddrBit);
+					nextPC:=pc+1;
+					memBAddr <= nextPC(maxAddrBit downto minAddrBit);
+					state <= State_Add;
+				when State_Add =>
+					memAWriteEnable <= '1';
+					memAWrite <= memARead + memBRead;
+					memAAddr <= sp;
+					memBAddr <= sp + 1;
+					state <= State_Decode;
+				when State_LoadByte1 =>
+					memAAddr <= pc(maxAddrBit downto minAddrBit);
+					nextPC:=pc+1;
+					memBAddr <= nextPC(maxAddrBit downto minAddrBit);
+					state <= State_LoadByte2;
+				when State_LoadByte2 =>
+					memAWriteEnable <= '1';
+					memAAddr <= sp;
+					memAWrite <= (others => '0');
+					case byteSelect is
+						when "00" 	=> memAWrite(7 downto 0) <= memARead(31 downto 24);
+						when "01" 	=> memAWrite(7 downto 0) <= memARead(23 downto 16);
+						when "10" 	=> memAWrite(7 downto 0) <= memARead(15 downto 8);
+						when others	=> memAWrite(7 downto 0) <= memARead(7 downto 0);
+					end case;
+					memBAddr <= sp + 1;
+					state <= State_Decode;
+				when State_StoreByte1 =>
+					state <= State_StoreByte2;
+				when State_StoreByte2 =>
+					memAWriteEnable <= '1';
+					memAAddr <= memBRead(maxAddrBit downto minAddrBit);
+					memAWrite <= memARead;
+					case byteSelect is
+						when "00" 	=> memAWrite(31 downto 24) <= storeByte;
+						when "01" 	=> memAWrite(23 downto 16) <= storeByte;
+						when "10" 	=> memAWrite(15 downto 8) <= storeByte;
+						when others	=> memAWrite(7 downto 0) <= storeByte;
+					end case;
+					state <= State_ResyncDecode;
+				when State_Mult1 =>
+					memAAddr <= pc(maxAddrBit downto minAddrBit);
+					nextPC:=pc+1;
+					memBAddr <= nextPC(maxAddrBit downto minAddrBit);
+					state <= State_Mult2;
+				when State_Mult2 =>
+					memAWriteEnable <= '1';
+					memAWrite <= multResult;
+					memAAddr <= sp;
+					memBAddr <= sp + 1;
+					state <= State_Decode;
+					
+				when others =>
+					null;
+			end case;				
+		end if;
+	end process;
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu3/src/zpuio.vhd b/zpu/hdl/zpu3/src/zpuio.vhd
new file mode 100644
index 0000000..96e9aea
--- /dev/null
+++ b/zpu/hdl/zpu3/src/zpuio.vhd
@@ -0,0 +1,180 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library zylin;
+use zylin.arm7.all;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity zpuio is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			clk_status		: in std_logic_vector(2 downto 0);
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_dout		: inout std_logic_vector(15 downto 0));
+end zpuio;
+
+architecture behave of zpuio is
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+
+signal io_busy : std_logic;
+signal io_read : std_logic_vector(7 downto 0);
+signal io_write : std_logic_vector(7 downto 0);
+signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal io_writeEnable : std_logic;
+signal io_readEnable : std_logic;
+
+signal		  din :  std_logic_vector(7 downto 0);
+signal	 		  dout : std_logic_vector(7 downto 0);
+signal			  adr : std_logic_vector(15 downto 0);
+signal			  break : std_logic;
+signal			  we : std_logic;
+signal			  re : std_logic;
+
+
+-- uart forwarding...
+
+signal uartTXPending : std_logic;
+signal uartTXCleared : std_logic;
+signal uartData : std_logic_vector(7 downto 0);
+
+signal readingTimer : std_logic;
+begin
+
+	timerinst: timer port map (
+       clk => cpu_clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => io_write,
+		 adr => io_addr(4 downto 2),
+		 dout => timer_read);
+
+	zpu: zpu_top port map (
+    	clk => cpu_clk ,
+	 	areset => areset,
+		io_busy => io_busy,
+		io_writeEnable => io_writeEnable,
+		io_readEnable => io_readEnable,
+		io_write	=> io_write,
+		io_read	=> io_read,
+		io_addr => io_addr,
+		interrupt => '0'
+		--,
+--	 	break => cpu_fiq_p
+);
+
+
+	-- Read/write are on different addresses
+	-- The registers are 8 bits and mapped to bit[7:0]
+	-- 
+	-- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) 
+	--        Read : Reads from UART RX FIFO (4 byte FIFO)
+	-- 0xC004 Read : UART status register
+	--                       Bit 0 = RX FIFO empty
+	--                       Bit 1 = TX FIFO full
+	-- 0xA000 Skrive: LED's (8 stk.)
+	
+	-- 0x9000 Write: bit 0: 1= reset counter
+	-- 			   0= counter running
+	-- 		  bit 1: 1= sample counter (when set to 1)
+	-- 			   0=not used
+	-- 	 Read : counter bit[7:0]
+	-- 0x9004 Read: counter bit [15:8]
+	-- 0x9008 Read: counter bit [23:16]
+	-- 0x900C Read: counter bit [31:24]
+	-- 0x9010 Read: counter bit [39:32]
+	-- 0x9014 Read: counter bit [47:40]
+	-- 0x9018 Read: counter bit [55:48]
+	-- 0x901C Read: counter bit [63:56]
+	-- 
+	-- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz)
+	
+	fauxUart:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			io_busy <= '0';
+			uartTXPending <= '0';
+			timer_we <= '0';
+			io_busy <= '1';
+			uartData <= x"58"; -- 'X'
+			readingTimer <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			timer_we <= '0';
+			io_busy <= '1';
+			if uartTXCleared = '1' then
+				uartTXPending <= '0';
+			end if;
+		
+			if io_writeEnable = '1' then
+				if io_addr=x"1000" then
+					-- Write to UART
+					uartData <= io_write;
+					uartTXPending <= '1';
+					io_busy <= '0';
+ 				elsif io_addr(12)='1' then
+ 					timer_we <= '1';
+					io_busy <= '0';
+				else
+					report "Illegal IO write" severity failure;
+				end if;
+			end if;
+			if (io_readEnable = '1') then
+				if io_addr=x"1001" then
+					io_read <= (0=>'1',  		-- recieve empty
+ 					            1 => uartTXPending,   -- tx full
+ 					            others => '0');
+ 					io_busy <= '0';
+ 				elsif io_addr(12)='1' then
+ 					readingTimer <= '1';
+ 					io_busy <= '1';
+ 				elsif io_addr(11)='1' then
+ 					io_read <= ZPU_Frequency;
+ 					io_busy <= '0';
+				else
+					report "Illegal IO read" severity failure;
+				end if;
+				
+			else 
+				if (readingTimer = '1') then
+					readingTimer <= '0';
+ 					io_read <= timer_read;
+ 					io_busy <= '0';
+ 				else
+					io_read <= (others => '1');
+ 				end if;
+			end if;
+		end if;
+	end process;
+
+
+	forwardUARTOutputToARM:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			uartTXCleared <= '0';
+		elsif (cpu_clk = '1' and cpu_clk'event) then
+			if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
+				uartTXCleared <= cpu_din(0);
+			else
+				uartTXCleared <= uartTXCleared;
+			end if;
+		end if;
+	end process;	
+
+	cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
+	cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
+	
+
+
+end behave;
diff --git a/zpu/hdl/zpu3/src/zpupkg.vhd b/zpu/hdl/zpu3/src/zpupkg.vhd
new file mode 100644
index 0000000..a904b11
--- /dev/null
+++ b/zpu/hdl/zpu3/src/zpupkg.vhd
@@ -0,0 +1,130 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+library zylin;
+use zylin.zpu_config.all;
+
+package zpupkg is
+
+	component dualport_ram is
+	port (clk : in std_logic;
+		memAWriteEnable : in std_logic;
+		memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+		memAWrite : in std_logic_vector(wordSize-1 downto 0);
+		memARead : out std_logic_vector(wordSize-1 downto 0);
+		memBWriteEnable : in std_logic;
+		memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+		memBWrite : in std_logic_vector(wordSize-1 downto 0);
+		memBRead : out std_logic_vector(wordSize-1 downto 0));
+	end component;
+
+
+	component trace is
+	  port(
+	       	clk         : in std_logic;
+	       	begin_inst  : in std_logic;
+	       	pc          : in std_logic_vector(maxAddrBit downto 0);
+			opcode		: in std_logic_vector(7 downto 0);
+			sp			: in std_logic_vector(maxAddrBit downto minAddrBit);
+			memA		: in std_logic_vector(wordSize-1 downto 0);
+			memB		: in std_logic_vector(wordSize-1 downto 0);
+			busy         : in std_logic
+			);
+	end component;
+
+	component zpu_top is
+	    Port ( clk : in std_logic;
+		 		  areset : in std_logic;
+		 		  io_busy : in std_logic;
+		 		  io_read : in std_logic_vector(7 downto 0);
+		 		  io_write : out std_logic_vector(7 downto 0);
+				  io_addr : out std_logic_vector(maxAddrBit downto minAddrBit);
+				  io_writeEnable : out std_logic;
+				  io_readEnable : out std_logic;
+		 		  interrupt : in std_logic;
+		 		  break : out std_logic);
+	end component;
+
+
+	component timer is
+	  port(
+	       clk              : in std_logic;
+			 areset				: in std_logic;
+			 we					: in std_logic;
+			 din					: in std_logic_vector(7 downto 0);
+			 adr					: in std_logic_vector(2 downto 0);
+			 dout					: out std_logic_vector(7 downto 0));
+	end component;
+	
+
+	component  zpuio is
+		port (	areset			: in std_logic;
+				cpu_clk			: in std_logic;
+				clk_status		: in std_logic_vector(2 downto 0);
+				cpu_din			: in std_logic_vector(15 downto 0);
+				cpu_a			: in std_logic_vector(20 downto 0);
+				cpu_we			: in std_logic_vector(1 downto 0);
+				cpu_re			: in std_logic;
+				cpu_dout		: inout std_logic_vector(15 downto 0));
+	end component;
+
+	
+	-- opcode decode constants
+	constant	OpCode_Im		: std_logic_vector(7 downto 7) := "1";
+	constant	OpCode_StoreSP	: std_logic_vector(7 downto 5) := "010";
+	constant	OpCode_LoadSP	: std_logic_vector(7 downto 5) := "011";
+	constant	OpCode_Emulate	: std_logic_vector(7 downto 5) := "001";
+	constant	OpCode_AddSP	: std_logic_vector(7 downto 4) := "0001";
+	constant	OpCode_Short	: std_logic_vector(7 downto 4) := "0000";
+	
+	constant	OpCode_Break	: std_logic_vector(3 downto 0) := "0000";
+	constant	OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
+	constant	OpCode_PushSP	: std_logic_vector(3 downto 0) := "0010";
+	constant	OpCode_PushInt	: std_logic_vector(3 downto 0) := "0011";
+	
+	constant	OpCode_PopPC	: std_logic_vector(3 downto 0) := "0100";
+	constant	OpCode_Add		: std_logic_vector(3 downto 0) := "0101";
+	constant	OpCode_And		: std_logic_vector(3 downto 0) := "0110";
+	constant	OpCode_Or		: std_logic_vector(3 downto 0) := "0111";
+	
+	constant	OpCode_Load		: std_logic_vector(3 downto 0) := "1000";
+	constant	OpCode_Not		: std_logic_vector(3 downto 0) := "1001";
+	constant	OpCode_Flip		: std_logic_vector(3 downto 0) := "1010";
+	constant	OpCode_Nop		: std_logic_vector(3 downto 0) := "1011";
+	
+	constant	OpCode_Store	: std_logic_vector(3 downto 0) := "1100";
+	constant	OpCode_PopSP	: std_logic_vector(3 downto 0) := "1101";
+	constant	OpCode_Compare	: std_logic_vector(3 downto 0) := "1110";
+	constant	OpCode_PopInt	: std_logic_vector(3 downto 0) := "1111";
+	
+	constant	OpCode_Lessthan				: std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
+	constant	OpCode_Lessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
+	constant	OpCode_Ulessthan			: std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
+	constant	OpCode_Ulessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
+
+	constant	OpCode_Swap					: std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
+	
+	constant	OpCode_Lshiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
+	constant	OpCode_Ashiftleft			: std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
+	constant	OpCode_Ashiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
+
+	constant	OpCode_Eq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
+	constant	OpCode_Neq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
+
+	constant	OpCode_Sub					: std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
+	constant	OpCode_Loadb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
+	constant	OpCode_Storeb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
+
+	constant	OpCode_Eqbranch				: std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
+	constant	OpCode_Neqbranch			: std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
+
+	constant	OpCode_Pushspadd			: std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
+	constant	OpCode_Mult16x16			: std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
+	constant	OpCode_Callpcrel			: std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
+	
+
+
+	constant OpCode_Size		: integer := 8;
+		
+end zpupkg;
diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd
new file mode 100644
index 0000000..95fbc18
--- /dev/null
+++ b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd
@@ -0,0 +1,31 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package arm7 is
+
+	component arm7wb
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_a_p			: in std_logic_vector(20 downto 0);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_irq_p		: out std_logic_vector(1 downto 0);
+			cpu_fiq_p		: out std_logic;
+			cpu_wait_n_p	: out std_logic;
+			
+			cpu_din			: out std_logic_vector(15 downto 0);
+			cpu_a			: out std_logic_vector(20 downto 0);
+			cpu_we			: out std_logic_vector(1 downto 0);
+			cpu_re			: out std_logic;
+			cpu_dout		: in std_logic_vector(15 downto 0));
+	end component;
+	
+end arm7;
+
+			
\ No newline at end of file
diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd
new file mode 100644
index 0000000..55b8125
--- /dev/null
+++ b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd
@@ -0,0 +1,213 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity arm7wb is
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_a_p			: in std_logic_vector(20 downto 0);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_irq_p		: out std_logic_vector(1 downto 0);
+			cpu_fiq_p		: out std_logic;
+			cpu_wait_n_p	: out std_logic;
+			
+			cpu_din			: out std_logic_vector(15 downto 0);
+			cpu_a			: out std_logic_vector(20 downto 0);
+			cpu_we			: out std_logic_vector(1 downto 0);
+			cpu_re			: out std_logic;
+			cpu_dout		: in std_logic_vector(15 downto 0));
+end arm7wb;
+			
+architecture behave of arm7wb is
+
+attribute keep : string;
+
+signal	cpu_oe_n		: std_logic;
+signal	cpu_fiq			: std_logic;
+signal	cpu_wait_n		: std_logic;
+signal	cpu_clk_toggle	: std_logic;
+signal	cpu_clk_smp1	: std_logic;
+signal	cpu_clk_smp2	: std_logic;
+signal	cpu_clk_phase	: std_logic;
+signal	cpu_oe_n_del	: std_logic;
+signal	cpu_a_smp		: std_logic_vector(20 downto 0);
+signal	cpu_d_smp		: std_logic_vector(15 downto 0);
+
+signal	int_oe_n		: std_logic_vector(15 downto 0);
+attribute keep of int_oe_n:signal is "true";
+
+signal	cpu_irq			: std_logic_vector(1 downto 0);
+signal	cpu_wr_n		: std_logic_vector(1 downto 0);
+signal	cpu_cs_n		: std_logic_vector(3 downto 1);
+
+signal	dout			: std_logic_vector(15 downto 0);
+signal	cpu_d_p_out		: std_logic_vector(15 downto 0);
+signal	read_cnt		: std_logic_vector(1 downto 0);
+
+signal	cpu_wr_n_p_del	: std_logic_vector(1 downto 0);
+signal	cpu_a_p_del		: std_logic_vector(20 downto 0);
+signal	cpu_d_p_del		: std_logic_vector(15 downto 0);
+signal	cpu_cs_n_p_del	: std_logic_vector(3 downto 1);
+signal	cpu_oe_n_p_del	: std_logic;
+
+constant	Sim_Delay	: time := 0.5 ns;
+constant	Clock_2_Out	: time := 5.5 ns;
+constant	Input_Setup	: time := 2.5 ns;
+
+begin
+
+	cpu_wait_n <= '1';
+	cpu_fiq <= '1';
+	cpu_irq <= "11";
+	
+	iotimingon:
+	if simulate_io_time generate
+	begin
+		cpu_wr_n_p_del <= "XX" after 0 ns, cpu_wr_n_p after Input_Setup;
+		cpu_a_p_del <= "XXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup;
+		cpu_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup;
+		cpu_cs_n_p_del <= "XXX" after 0 ns, cpu_cs_n_p after Input_Setup;
+		cpu_oe_n_p_del <= 'X' after 0 ns, cpu_oe_n_p after Input_Setup;
+	end generate;
+	
+	iotimingoff:
+	if not simulate_io_time generate
+	begin
+		cpu_wr_n_p_del <= cpu_wr_n_p;
+		cpu_a_p_del <=  cpu_a_p;
+		cpu_d_p_del <= cpu_d_p;
+		cpu_cs_n_p_del <= cpu_cs_n_p;
+		cpu_oe_n_p_del <= cpu_oe_n_p;
+	end generate;
+	
+	process(cpu_clk, areset)	-- Toggle FF with 1x clock to find phase
+	begin
+		if areset = '1' then
+			cpu_clk_toggle <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			cpu_clk_toggle <= not(cpu_clk_toggle);
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	-- Find phase relationsship between 1x and 2x clock
+	begin
+		if areset = '1' then
+			cpu_clk_smp1 <= '0';
+			cpu_clk_smp2 <= '1';
+			cpu_clk_phase <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			cpu_clk_smp1 <= cpu_clk_toggle;
+			cpu_clk_smp2 <= cpu_clk_smp1;
+			if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then
+				cpu_clk_phase <= '0' after Sim_Delay;
+			else
+				cpu_clk_phase <= not(cpu_clk_phase) after Sim_Delay;
+			end if;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	-- Sample input signals
+	begin
+		if areset = '1' then
+			cpu_oe_n <= '1';
+			cpu_a_smp <= "000000000000000000000";
+			cpu_d_smp <= "0000000000000000";
+			cpu_wr_n <= "11";
+			cpu_cs_n <= "111";
+		elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then
+			cpu_oe_n <= cpu_oe_n_p_del after Sim_Delay;
+			cpu_a_smp <= cpu_a_p_del after Sim_Delay;
+			cpu_d_smp <= cpu_d_p_del after Sim_Delay;
+			cpu_wr_n <= cpu_wr_n_p_del after Sim_Delay;
+			cpu_cs_n <= cpu_cs_n_p_del after Sim_Delay;
+		end if;
+	end process;
+
+	cpu_d_out:
+   	for i in 0 to 15 generate
+      	begin
+      		process(cpu_clk_2x, areset)
+      		begin
+      			if areset = '1' then
+      				cpu_d_p(i) <= 'Z';
+      			elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+      				if int_oe_n(i) = '0' then
+			        	cpu_d_p(i) <= cpu_d_p_out(i) after Clock_2_Out;
+			       	else
+			       		cpu_d_p(i) <= 'Z' after Clock_2_Out;
+			       	end if;
+			  	end if;
+			end process;
+   	end generate;
+   	
+	process(cpu_clk, areset)	-- Clocked output pins
+	begin
+		if areset = '1' then
+			cpu_d_p_out <= "1111111111111111";
+			cpu_wait_n_p <= '1';
+			cpu_irq_p <= "11";
+			cpu_fiq_p <= '1';
+		elsif (cpu_clk = '1' and cpu_clk'event) then
+			cpu_d_p_out <= cpu_dout;
+			cpu_wait_n_p <= '1';
+			cpu_irq_p <= "11";
+			cpu_fiq_p <= '1';
+		end if;
+	end process;
+	
+	process(cpu_clk, areset)	-- Generate control signals
+	begin
+		if areset = '1' then
+			int_oe_n <= "1111111111111111";
+			read_cnt <= "00";
+			cpu_we <= "00";
+			cpu_re <= '0';
+			cpu_a <= "000000000000000000000";
+			cpu_din <= "0000000000000000";
+		elsif (cpu_clk = '1' and cpu_clk'event) then
+		
+			cpu_a <= cpu_a_smp;
+			cpu_din <= cpu_d_smp;
+			
+			cpu_oe_n_del <= cpu_oe_n;
+			
+			if cpu_cs_n(1) = '1' then
+				read_cnt <= "00";
+			else
+				read_cnt <= read_cnt + '1';
+			end if;
+			
+			if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(0) = '0' then
+				cpu_we(0) <= '1';
+			else
+				cpu_we(0) <= '0';
+			end if;
+			
+			if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(1) = '0' then
+				cpu_we(1) <= '1';
+			else
+				cpu_we(1) <= '0';
+			end if;
+			
+			if read_cnt = "00" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then
+				cpu_re <= '1';
+			else
+				cpu_re <= '0';
+			end if;
+			
+			if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then
+				int_oe_n <= "0000000000000000";
+			else
+				int_oe_n <= "1111111111111111";
+			end if;
+						
+		end if;
+	end process;
+	
+end behave;			
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do
new file mode 100644
index 0000000..d2c22cf
--- /dev/null
+++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do
@@ -0,0 +1,17 @@
+vlib zylin
+vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd
+vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd
+vcom -93 -explicit -work zylin ../ddrsdram/src/mt46v16m16.vhd
+vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_tb.vhd
+vlib work
+vsim -t 1ps  zylin.ddr_tb
+view wave
+view signals
+radix hex
+add wave *
+add wave sim:/ddr_tb/ddr_ctrl/*
+force -freeze sim:/ddr_tb/areset 1 0
+run 10 ns
+force -freeze sim:/ddr_tb/areset 0 0
+when sim:/ddr_tb/break_out stop
+run 10 ms
\ No newline at end of file
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do
new file mode 100644
index 0000000..31dd294
--- /dev/null
+++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do
@@ -0,0 +1,111 @@
+vlib zylin
+vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd
+vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd
+vlib work
+vsim -t 1ps  zylin.ddr_top
+view wave
+view signals
+radix hex
+# Add wave signals
+
+add wave -divider "System"
+add wave sim:/ddr_top/areset
+add wave sim:/ddr_top/cpu_clk
+add wave sim:/ddr_top/cpu_clk_2x
+add wave sim:/ddr_top/cpu_clk_4x
+add wave sim:/ddr_top/ddr_in_clk
+add wave sim:/ddr_top/ddr_in_clk_2x
+
+add wave -divider "Ctrl interface"
+add wave sim:/ddr_top/cpu_clk
+add wave sim:/ddr_top/ddr_data_read
+add wave sim:/ddr_top/ddr_data_write
+add wave sim:/ddr_top/ddr_req
+add wave sim:/ddr_top/ddr_rd_wr_n
+add wave sim:/ddr_top/ddr_req_len
+add wave sim:/ddr_top/ddr_wr_mask
+add wave sim:/ddr_top/ddr_read_en
+add wave sim:/ddr_top/ddr_write_en
+add wave sim:/ddr_top/ddr_command
+add wave sim:/ddr_top/ddr_command_we
+
+add wave -divider "DDR interface"
+add wave sim:/ddr_top/sdr_clk_p
+add wave sim:/ddr_top/sdr_clk_n_p
+add wave sim:/ddr_top/cke_q_p
+add wave sim:/ddr_top/cs_qn_p
+add wave sim:/ddr_top/ras_qn_p
+add wave sim:/ddr_top/cas_qn_p
+add wave sim:/ddr_top/we_qn_p
+add wave sim:/ddr_top/dm_q_p
+add wave sim:/ddr_top/dqs_q_p
+add wave sim:/ddr_top/ba_q_p
+add wave sim:/ddr_top/sdr_a_p
+add wave sim:/ddr_top/sdr_d_p
+
+add wave -divider "Internal signals"
+add wave sim:/ddr_top/clk2_phase
+add wave sim:/ddr_top/clk4_phase
+add wave sim:/ddr_top/ddr_state
+add wave sim:/ddr_top/sdr_oe_n
+add wave sim:/ddr_top/sdr_smp
+add wave sim:/ddr_top/sdr_d
+
+
+# Add input signals
+force -freeze sim:/ddr_top/cpu_clk_4x 1 0, 0 {1.875 ns} -r 3.75
+run 100 ps
+force -freeze sim:/ddr_top/cpu_clk_2x 1 0, 0 {3.75 ns} -r 7.5
+run 100 ps
+force -freeze sim:/ddr_top/cpu_clk 1 0, 0 {7.5 ns} -r 15
+force -freeze sim:/ddr_top/ddr_in_clk 1 2ns, 0 {5.75 ns} -r 7.5
+force -freeze sim:/ddr_top/ddr_in_clk_2x 0 0.125ns, 1 {2 ns} -r 3.75
+
+force -freeze sim:/ddr_top/areset 1 0
+force -freeze sim:/ddr_top/ddr_command 0000 0
+force -freeze sim:/ddr_top/ddr_command_we 0 0
+force -freeze sim:/ddr_top/ddr_data_write 1234abcd 0
+force -freeze sim:/ddr_top/ddr_req 0 0
+force -freeze sim:/ddr_top/ddr_req_adr 000000 0
+force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0
+force -freeze sim:/ddr_top/ddr_req_len 000 0
+force -freeze sim:/ddr_top/ddr_wr_mask 0 0
+
+# Start simulation
+run 45
+force -freeze sim:/ddr_top/areset 0 0
+run 92
+# DDR Command
+force -freeze sim:/ddr_top/ddr_command 000A 0
+force -freeze sim:/ddr_top/ddr_command_we 1 0
+run 15
+force -freeze sim:/ddr_top/ddr_command 0000 0
+force -freeze sim:/ddr_top/ddr_command_we 0 0
+run 90
+# DDR Read
+force -freeze sim:/ddr_top/ddr_req 1 0
+force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0
+force -freeze sim:/ddr_top/ddr_rd_wr_n 1 0
+force -freeze sim:/ddr_top/ddr_req_len 000 0
+force -freeze sim:/ddr_top/ddr_wr_mask 0 0
+run 15
+force -freeze sim:/ddr_top/ddr_req 0 0
+force -freeze sim:/ddr_top/ddr_req_adr 000000 0
+force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0
+force -freeze sim:/ddr_top/ddr_req_len 000 0
+force -freeze sim:/ddr_top/ddr_wr_mask 0 0
+run 150
+# DDR Write
+force -freeze sim:/ddr_top/ddr_req 1 0
+force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0
+force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0
+force -freeze sim:/ddr_top/ddr_req_len 000 0
+force -freeze sim:/ddr_top/ddr_wr_mask 0 0
+run 15
+force -freeze sim:/ddr_top/ddr_req 0 0
+force -freeze sim:/ddr_top/ddr_req_adr 000000 0
+force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0
+force -freeze sim:/ddr_top/ddr_req_len 000 0
+force -freeze sim:/ddr_top/ddr_wr_mask 0 0
+run 180
+
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd
new file mode 100644
index 0000000..95f4b8a
--- /dev/null
+++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd
@@ -0,0 +1,90 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+package ddr is
+
+	component ddr_top
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	-- Asyncronous reset and clocks
+			areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_clk_4x		: in std_logic;
+			ddr_in_clk		: in std_logic;
+			ddr_in_clk_2x	: in std_logic;
+			
+			-- Command interface
+			ddr_command		: in std_logic_vector(15 downto 0);
+			ddr_command_we	: in std_logic;
+			refresh_en		: in std_logic;
+			
+			
+			-- Data interface signals
+			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
+			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
+			ddr_req_adr		: in std_logic_vector(23 downto 1);		-- Request address
+			ddr_req			: in std_logic;							-- Request DDR SDRAM access
+			ddr_req_ack		: out std_logic;							-- Request acknowledge
+			ddr_busy		: out std_logic;							-- Request acknowledge
+			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE
+			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)
+			ddr_read_en		: out std_logic;						-- Enable signal for read data
+			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write
+
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
+	end component;
+	
+	component MT46V16M16
+    GENERIC (                                   -- Timing for -75Z CL2
+        tCK       : TIME    :=  7.500 ns;
+        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tDH       : TIME    :=  0.500 ns;
+        tDS       : TIME    :=  0.500 ns;
+        tIH       : TIME    :=  0.900 ns;
+        tIS       : TIME    :=  0.900 ns;
+        tMRD      : TIME    := 15.000 ns;
+        tRAS      : TIME    := 40.000 ns;
+        tRAP      : TIME    := 20.000 ns;
+        tRC       : TIME    := 65.000 ns;
+        tRFC      : TIME    := 75.000 ns;
+        tRCD      : TIME    := 20.000 ns;
+        tRP       : TIME    := 20.000 ns;
+        tRRD      : TIME    := 15.000 ns;
+        tWR       : TIME    := 15.000 ns;
+        addr_bits : INTEGER := 13;
+        data_bits : INTEGER := 16;
+        cols_bits : INTEGER :=  9
+    );
+    PORT (
+        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
+        Clk   : IN    STD_LOGIC;
+        Clk_n : IN    STD_LOGIC;
+        Cke   : IN    STD_LOGIC;
+        Cs_n  : IN    STD_LOGIC;
+        Ras_n : IN    STD_LOGIC;
+        Cas_n : IN    STD_LOGIC;
+        We_n  : IN    STD_LOGIC;
+        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
+    );
+	end component;
+	
+end ddr;
+	
\ No newline at end of file
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd
new file mode 100644
index 0000000..5666532
--- /dev/null
+++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd
@@ -0,0 +1,301 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library zylin;
+use zylin.ddr.all;
+
+entity ddr_tb is
+	port (	areset			: in std_logic;
+			break_out		: out std_logic);
+end ddr_tb;
+
+architecture behave of ddr_tb is
+
+signal	cpu_clk			: std_logic;
+signal	cpu_clk_2x		: std_logic;
+signal	cpu_clk_4x		: std_logic;
+signal	ddr_in_clk		: std_logic;
+signal	ddr_in_clk_2x	: std_logic;
+
+signal	ddr_command		: std_logic_vector(15 downto 0);
+signal	ddr_command_we	: std_logic;
+			
+signal	ddr_data_read	: std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
+signal	ddr_data_write	: std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
+signal	ddr_req_adr		: std_logic_vector(23 downto 1);		-- Request address
+signal	ddr_req			: std_logic;							-- Request DDR SDRAM access
+signal	ddr_req_ack		: std_logic;							-- Request acknowledge
+signal	ddr_busy		: std_logic;							-- Request acknowledge
+signal	ddr_rd_wr_n		: std_logic;							-- Access type 1=READ, 0=WRITE
+signal	ddr_req_len		: std_logic;							-- Number of 16-bits words to transfer
+signal	ddr_read_en		: std_logic;						-- Enable signal for read data
+signal	ddr_write_en	: std_logic;						-- Enable (read) signal for data write
+signal	refresh_en		: std_logic;
+
+signal	sdr_clk_p       : std_logic;    -- ddr_sdram_clock
+signal	sdr_clk_n_p     : std_logic;    -- /ddr_sdram_clock
+signal	cke_q_p         : std_logic;    -- clock enable
+signal	cs_qn_p         : std_logic;    -- /chip select
+signal	ras_qn_p        : std_logic;    -- /ras
+signal	cas_qn_p        : std_logic;    -- /cas
+signal	we_qn_p         : std_logic;    -- /write enable
+signal	dm_q_p          : std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+signal	dqs_q_p         : std_logic_vector(1 downto 0);    -- data strobe, only for write
+signal	ba_q_p          : std_logic_vector(1 downto 0);   -- bank select
+signal	sdr_a_p		    : std_logic_vector(12 downto 0);   -- address bus 
+signal	sdr_d_p         : std_logic_vector(15 downto 0); 			-- bidir data bus
+
+constant min_time	: time := 1.875 ns;
+
+begin
+
+	clock1:
+	process
+	begin
+		loop
+			cpu_clk_4x <= '1';
+			wait for min_time;
+			cpu_clk_4x <= '0';
+			wait for min_time;
+		end loop;
+	end process;
+
+	clock2:
+	process
+	begin
+		loop
+			cpu_clk_2x <= '1' after 100 ps;
+			wait until rising_edge(cpu_clk_4x);
+			cpu_clk_2x <= '0' after 100 ps;
+			wait until rising_edge(cpu_clk_4x);
+		end loop;
+	end process;
+
+	clock3:
+	process
+	begin
+		loop
+			cpu_clk <= '1' after 100 ps;
+			wait until rising_edge(cpu_clk_2x);
+			cpu_clk <= '0' after 100 ps;
+			wait until rising_edge(cpu_clk_2x);
+		end loop;
+	end process;
+	
+	ddr_in_clk_2x <= cpu_clk_4x after 1 ns;
+
+	clock4:
+	process
+	begin
+		loop
+			ddr_in_clk <= '0' after 100 ps;
+			wait until rising_edge(ddr_in_clk_2x);
+			ddr_in_clk <= '1' after 100 ps;
+			wait until rising_edge(ddr_in_clk_2x);
+		end loop;
+	end process;
+	
+	inputdata:
+	process
+	begin
+		-- Wait until global reset released
+		loop
+			ddr_command <= x"0000";
+			ddr_command_we <= '0';
+			ddr_data_write <= x"000000000";
+			ddr_req <= '0';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			break_out <= '0';
+			refresh_en <= '0';
+			
+			wait until falling_edge(areset);
+			
+			-- DDR initialization sequence
+				-- Wait more than 200 us
+				wait for 201000 ns;	
+				
+				-- Send precharge command
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"8000";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+				
+				-- Wait for 1 us
+				wait for 1000 ns;
+				
+				-- Load extended mode register
+				--  Enable DLL
+				--  Normal drive strength
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"2000";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+							
+				-- Wait for 1 us
+				wait for 1000 ns;
+				
+				-- Load mode register
+				--  Burst length: 2
+				--  Burst type: Sequential
+				--  Cas latency: 2
+				--  Reset DLL
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"0121";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+							
+				-- Wait for 1 us
+				wait for 1000 ns;
+				
+				-- Send precharge command
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"8000";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+				
+				-- Enable refresh
+				refresh_en <= '1';
+			
+				-- Wait 30 us (minimum 2 autorefresh cycles)
+				wait for 30000 ns;
+						
+				-- Load mode register
+				--  Burst length: 2
+				--  Burst type: Sequential
+				--  Cas latency: 2
+				--  Deactivate Reset DLL
+				wait until rising_edge(cpu_clk);	
+				ddr_command <= x"0021";
+				ddr_command_we <= '1';
+				wait until rising_edge(cpu_clk);
+				ddr_command <= x"0000";
+				ddr_command_we <= '0';
+	
+				-- Wait for 2 us (DLL stable)
+				wait for 2000 ns;
+				
+			-- Write data to DDR
+			wait until rising_edge(cpu_clk_2x);
+			ddr_data_write <= x"312345678";
+			ddr_req <= '1';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			wait until rising_edge(ddr_write_en);
+			wait until rising_edge(cpu_clk_2x);
+			ddr_req <= '0';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			ddr_data_write <= x"000000000";
+			wait for 100 ns;
+			
+			-- Read data from DDR
+			wait until rising_edge(cpu_clk_2x);
+			ddr_req <= '1';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '1';
+			ddr_req_len <= '0';
+			wait until rising_edge(ddr_req_ack);
+			wait until rising_edge(cpu_clk_2x);
+			ddr_req <= '0';
+			ddr_req_adr <= "00000000000000000000000";
+			ddr_rd_wr_n <= '0';
+			ddr_req_len <= '0';
+			ddr_data_write <= x"000000000";
+
+
+
+			wait for 100 ns;
+			break_out <= '1';
+			wait for 100 ns;
+						
+		end loop;
+		
+	end process;
+	
+	ddr_ctrl:
+	ddr_top port map(
+		areset => areset,
+		cpu_clk => cpu_clk,
+		cpu_clk_2x => cpu_clk_2x,
+		cpu_clk_4x => cpu_clk_4x,
+		ddr_in_clk => ddr_in_clk,
+		ddr_in_clk_2x => ddr_in_clk_2x,
+		
+		-- Command interface
+		ddr_command => ddr_command,
+		ddr_command_we => ddr_command_we,
+		refresh_en => refresh_en,			
+		
+		-- Data interface signals
+		ddr_data_read => ddr_data_read,
+		ddr_data_write => ddr_data_write,
+		ddr_req_adr => ddr_req_adr,
+		ddr_req => ddr_req,
+		ddr_req_ack => ddr_req_ack,
+		ddr_busy => ddr_busy,
+		ddr_rd_wr_n => ddr_rd_wr_n,
+		ddr_req_len => ddr_req_len,
+		ddr_read_en => ddr_read_en,
+		ddr_write_en => ddr_write_en,
+		    -- DDR SDRAM Signals
+	    sdr_clk_p => sdr_clk_p,
+	    sdr_clk_n_p => sdr_clk_n_p,
+	    cke_q_p => cke_q_p,
+	    cs_qn_p => cs_qn_p,
+	    ras_qn_p => ras_qn_p,
+	    cas_qn_p => cas_qn_p,
+	    we_qn_p => we_qn_p,
+	    dm_q_p => dm_q_p,
+	    dqs_q_p => dqs_q_p,
+	    ba_q_p => ba_q_p,
+	    sdr_a_p => sdr_a_p,
+	    sdr_d_p => sdr_d_p);
+	   
+	myram:
+	MT46V16M16 generic map(
+        tCK => 7.500 ns,
+        tCH => 3.375 ns,       -- 0.45*tCK
+        tCL => 3.375 ns,       -- 0.45*tCK
+        tDH => 0.500 ns,
+        tDS => 0.500 ns,
+        tIH => 0.900 ns,
+        tIS => 0.900 ns,
+        tMRD => 15.000 ns,
+        tRAS => 40.000 ns,
+        tRAP => 20.000 ns,
+        tRC => 65.000 ns,
+        tRFC => 75.000 ns,
+        tRCD => 20.000 ns,
+        tRP => 20.000 ns,
+        tRRD => 15.000 ns,
+        tWR => 15.000 ns,
+        addr_bits => 13,
+        data_bits => 16,
+        cols_bits => 9)
+    port map(
+        Dq => sdr_d_p,
+        Dqs => dqs_q_p,
+        Addr => sdr_a_p,
+        Ba => ba_q_p,
+        Clk => sdr_clk_p,
+        Clk_n => sdr_clk_n_p,
+        Cke => cke_q_p,
+        Cs_n => cs_qn_p,
+        Ras_n => ras_qn_p,
+        Cas_n => cas_qn_p,
+        We_n => we_qn_p,
+        Dm => dm_q_p);
+
+end behave;
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd
new file mode 100644
index 0000000..d5e98e1
--- /dev/null
+++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd
@@ -0,0 +1,660 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity ddr_top is
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	-- Asyncronous reset and clocks
+			areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_clk_4x		: in std_logic;
+			ddr_in_clk		: in std_logic;
+			ddr_in_clk_2x	: in std_logic;
+			
+			-- Command interface
+			ddr_command		: in std_logic_vector(15 downto 0);
+			ddr_command_we	: in std_logic;
+			refresh_en		: in std_logic;
+			
+			-- Data interface signals
+			ddr_data_read	: out std_logic_vector(31 downto 0);	-- Data read from DDR SDRAM
+			ddr_data_write	: in std_logic_vector(35 downto 0);		-- Data to be written to DDR SDRAM
+			ddr_req_adr		: in std_logic_vector(23 downto 1);		-- Request address
+			ddr_req			: in std_logic;							-- Request DDR SDRAM access
+			ddr_req_ack		: out std_logic;							-- Request acknowledge
+			ddr_busy		: out std_logic;							-- Request acknowledge
+			ddr_rd_wr_n		: in std_logic;							-- Access type 1=READ, 0=WRITE
+			ddr_req_len		: in std_logic;							-- Number of 16-bits words to transfer (0=2, 1=8)
+			ddr_read_en		: out std_logic;						-- Enable signal for read data
+			ddr_write_en	: out std_logic;						-- Enable (read) signal for data write
+
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
+end ddr_top;
+
+architecture behave of ddr_top is
+
+attribute keep : string;
+
+signal	cpu_clk_tog			: std_logic;
+signal	ddr_cmd				: std_logic_vector(15 downto 0);
+signal	ddr_cmd_we_smp		: std_logic;
+signal	new_command			: std_logic;
+
+signal	cpu_clk_2x_smp1		: std_logic;		
+signal	cpu_clk_2x_smp2		: std_logic;		
+signal	cpu_clk_4x_smp1		: std_logic;		
+signal	cpu_clk_4x_smp2		: std_logic;
+
+signal	clk2_phase			: std_logic;		
+signal	clk4_phase			: std_logic_vector(3 downto 0);
+signal	clk4_phase_short	: std_logic_vector(1 downto 0);
+
+signal	ddr_clk_tog			: std_logic;
+signal	ddr_clk_smp1		: std_logic;
+signal	ddr_clk_smp2		: std_logic;
+signal	ddr_clk_phase		: std_logic;
+
+signal	smp_req_adr			: std_logic_vector(23 downto 1);
+signal	smp_req_type		: std_logic;
+signal	smp_req_len			: std_logic;
+signal	ddr_write_en_int	: std_logic;
+signal	ddr_read_en_int		: std_logic;
+
+signal	dqs_q				: std_logic_vector(1 downto 0);
+signal	dqs_oe_n			: std_logic_vector(1 downto 0);
+attribute keep of dqs_oe_n:signal is "true";
+signal	cas_qn				: std_logic;
+signal	ras_qn				: std_logic;
+signal	we_qn				: std_logic;
+signal	ba_q				: std_logic_vector(1 downto 0);
+signal	sdr_clk				: std_logic;
+signal	sdr_clk_n			: std_logic;
+signal	sdr_a				: std_logic_vector(12 downto 0);
+signal	sdr_d				: std_logic_vector(15 downto 0);
+signal	sdr_smp				: std_logic_vector(35 downto 0);
+signal	sdr_oe_n			: std_logic_vector(15 downto 0);
+attribute keep of sdr_oe_n:signal is "true";
+signal	sdr_oe_ctrl			: std_logic;
+signal	sdr_wr_msw			: std_logic_vector(17 downto 0);
+attribute keep of sdr_wr_msw:signal is "true";
+signal	dm_q				: std_logic_vector(1 downto 0);
+
+signal	cas_n_smp			: std_logic;
+signal	ras_n_smp			: std_logic;
+signal	we_n_smp			: std_logic;
+signal	read_start_sig		: std_logic;
+signal	sdr_d_in			: std_logic_vector(15 downto 0);
+signal	read_time_cnt		: std_logic_vector(1 downto 0);
+signal	read_input_en		: std_logic;
+signal	ddr_data_read_int	: std_logic_vector(31 downto 0);
+
+signal	refresh_pend		: std_logic;
+signal	refresh_end			: std_logic;
+signal	refresh_cnt			: std_logic_vector(9 downto 0);
+signal	refresh_wait_cnt	: std_logic_vector(2 downto 0);
+signal	refresh_wait_end	: std_logic;
+
+signal	cas_qn_p_del		: std_logic;
+signal	ras_qn_p_del		: std_logic;
+signal	we_qn_p_del			: std_logic;
+signal	sdr_d_p_del			: std_logic_vector(15 downto 0);
+
+type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, 
+					rd_nop2, pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, 
+					wr_nop3, cmd, cpu_pre, refresh, refresh_wait);
+signal	ddr_state			: state_type;
+
+constant	Clk_to_Output	: time := 2.2 ns;
+constant	Sim_Delay		: time := 0.5 ns;
+constant	Input_Setup	: time := 2.5 ns;
+
+constant	Refresh_Interval	: std_logic_vector(9 downto 0) := "1111100110";
+
+begin
+
+	iotimingon:
+	if simulate_io_time generate
+	begin
+		cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup;
+		ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup;
+		we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup;
+		sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup;
+	end generate;
+	
+	iotimingoff:
+	if not simulate_io_time generate
+	begin
+		cas_qn_p_del <= cas_qn_p;
+		ras_qn_p_del <= ras_qn_p;
+		we_qn_p_del <= we_qn_p;
+		sdr_d_p_del <= sdr_d_p;
+	end generate;
+	
+	ddr_write_en <= ddr_write_en_int;
+	ddr_read_en <= ddr_read_en_int;
+	ddr_data_read <= ddr_data_read_int;
+
+	process(cpu_clk, areset)	-- Toggle a flip-flop with cpu_clk, in order 
+	begin						-- to find phase relation with 2x and 4x clocks
+		if areset = '1' then
+			cpu_clk_tog <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			cpu_clk_tog <= not(cpu_clk_tog) after Sim_Delay;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	-- Find phase relation between cpu_clk and cpu_clk_2x
+	begin
+		if areset = '1' then
+			cpu_clk_2x_smp1 <= '0';
+			cpu_clk_2x_smp2 <= '0';
+			clk2_phase <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			cpu_clk_2x_smp1 <= cpu_clk_tog after Sim_Delay;
+			cpu_clk_2x_smp2 <= cpu_clk_2x_smp1 after Sim_Delay;
+			if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then
+				clk2_phase <= '0' after Sim_Delay;
+			else
+				clk2_phase <= not(clk2_phase) after Sim_Delay;
+			end if;
+		end if;
+	end process;
+	
+	process(cpu_clk_4x, areset)	-- Find phase relation between cpu_clk and cpu_clk_4x
+	begin
+		if areset = '1' then
+			cpu_clk_4x_smp1 <= '0';
+			cpu_clk_4x_smp2 <= '0';
+			clk4_phase <= "0000";
+			clk4_phase_short <= "00";
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+			cpu_clk_4x_smp1 <= cpu_clk_tog after Sim_Delay;
+			cpu_clk_4x_smp2 <= cpu_clk_4x_smp1 after Sim_Delay;
+			if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then
+				clk4_phase <= "0100" after Sim_Delay;
+				clk4_phase_short <= "01" after Sim_Delay;
+			else
+				clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3)) after Sim_Delay;
+				clk4_phase_short <= clk4_phase_short(0) & clk4_phase_short(1);
+			end if;
+		end if;
+	end process;
+
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+			sdr_clk <= '0';			
+			sdr_clk_n <= '0';			
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+			if clk4_phase_short(0) = '1' then
+				sdr_clk <= '1' after Sim_Delay;
+			else
+				sdr_clk <= '0' after Sim_Delay;
+			end if;
+			if clk4_phase_short(1) = '1' then
+				sdr_clk_n <= '1' after Sim_Delay;
+			else
+				sdr_clk_n <= '0' after Sim_Delay;
+			end if;
+		end if;
+	end process;
+	
+    cke_q_p <= '1' after Clk_to_Output;
+    cs_qn_p <= '0' after Clk_to_Output;
+	
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+		    ras_qn_p <= '1';
+		    cas_qn_p <= '1';
+		    we_qn_p <= '1';
+		    dqs_q_p <= "ZZ";
+		    sdr_a_p <= "0000000000000";
+			ba_q_p <= "00";
+			sdr_clk_p <= '0';
+			sdr_clk_n_p <= '1';
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+		    ras_qn_p <= transport ras_qn after Clk_to_Output;
+		    cas_qn_p <= transport cas_qn after Clk_to_Output;
+		    we_qn_p <= transport we_qn after Clk_to_Output;
+		    if dqs_oe_n(0) = '0' then
+		    	dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output;
+		    else
+		    	dqs_q_p(0) <= transport 'Z' after Clk_to_Output;
+		    end if;
+		    if dqs_oe_n(1) = '0' then
+		    	dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output;
+		    else
+		    	dqs_q_p(1) <= transport 'Z' after Clk_to_Output;
+		    end if;
+		    sdr_a_p <= transport sdr_a after Clk_to_Output;
+		    ba_q_p <= transport ba_q after Clk_to_Output;
+		    sdr_clk_p <= transport sdr_clk after Clk_to_Output;
+		    sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+			ddr_state <= idle;
+			ras_qn <= '1';
+			cas_qn <= '1';
+			we_qn <= '1';
+			smp_req_adr <= (others => '0');
+			smp_req_type <= '0';
+			smp_req_len <= '0';
+			sdr_a <= "XXXXXXXXXXXXX";
+			ba_q <= "00";
+			ddr_req_ack <= '0';
+			ddr_busy <= '1';
+			ddr_write_en_int <= '0';
+			ddr_read_en_int <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+		
+			-- Default values
+			ras_qn <= '1' after Sim_Delay;
+			cas_qn <= '1' after Sim_Delay;
+			we_qn <= '1' after Sim_Delay;
+			sdr_a <= "XXXXXXXXXXXXX" after Sim_Delay;
+			ba_q <= "00" after Sim_Delay;
+			ddr_req_ack <= '0' after Sim_Delay;
+			ddr_busy <= '1' after Sim_Delay;
+			ddr_write_en_int <= '0' after Sim_Delay;
+			ddr_read_en_int <= '0' after Sim_Delay;
+		
+			case ddr_state is
+				when idle =>
+					smp_req_adr <= ddr_req_adr after Sim_Delay;
+					smp_req_type <= ddr_rd_wr_n after Sim_Delay;
+					smp_req_len <= ddr_req_len after Sim_Delay;
+					ddr_busy <= '0' after Sim_Delay;
+					if refresh_pend = '1' then
+						ddr_state <= refresh after Sim_Delay;
+					elsif new_command = '1' then
+						if ddr_cmd(15) = '1' then
+							ddr_state <= cpu_pre after Sim_Delay;
+						else
+							ddr_state <= cmd after Sim_Delay;
+						end if;
+					elsif ddr_req = '1' then
+						ddr_state <= act after Sim_Delay;
+					else
+						ddr_state <= idle after Sim_Delay;
+					end if;
+				when act =>
+					sdr_a <= smp_req_adr(23 downto 11) after Sim_Delay;
+					ras_qn <= '0' after Sim_Delay;
+					ddr_state <= act_nop1 after Sim_Delay;
+					ddr_req_ack <= '1' after Sim_Delay;
+					ddr_write_en_int <= not(smp_req_type) after Sim_Delay;
+				when act_nop1 =>
+					ddr_state <= act_nop2 after Sim_Delay;
+				when act_nop2 =>
+					ddr_state <= rd_wr after Sim_Delay;
+				when rd_wr =>
+					sdr_a(10) <= '0' after Sim_Delay;		-- Disable auto precharge
+					sdr_a(9 downto 0) <= smp_req_adr(10 downto 1) after Sim_Delay;
+					cas_qn <= '0' after Sim_Delay;
+					we_qn <= smp_req_type after Sim_Delay;
+					if smp_req_type = '1' then
+						ddr_state <= rd_nop1 after Sim_Delay;
+					else
+						ddr_state <= wr_nop1 after Sim_Delay;
+					end if;
+				when wr_nop1 =>
+					ddr_state <= wr_nop2 after Sim_Delay;	
+				when wr_nop2 =>
+					ddr_state <= wr_nop3 after Sim_Delay;	
+				when wr_nop3 =>
+					ddr_state <= pre after Sim_Delay;	
+				when rd_nop1 =>
+					ddr_state <= rd_nop2 after Sim_Delay;	
+				when rd_nop2 =>
+					ddr_state <= pre after Sim_Delay;	
+				when pre =>					
+					ras_qn <= '0' after Sim_Delay;
+					we_qn <= '0' after Sim_Delay;
+					sdr_a(10) <= '1' after Sim_Delay;	-- Precharge all banks
+					ddr_state <= pre_nop1 after Sim_Delay;
+					ddr_read_en_int <= smp_req_type after Sim_Delay;
+				when pre_nop1 =>
+					ddr_state <= pre_nop2 after Sim_Delay;
+				when cmd =>
+					cas_qn <= '0' after Sim_Delay;
+					ras_qn <= '0' after Sim_Delay;
+					we_qn <= '0' after Sim_Delay;
+					ba_q <= ddr_cmd(14 downto 13) after Sim_Delay;
+					sdr_a <= ddr_cmd(12 downto 0) after Sim_Delay;
+					ddr_state <= idle after Sim_Delay;
+				when cpu_pre =>
+					ddr_state <= pre after Sim_Delay;
+				when refresh =>
+					cas_qn <= '0' after Sim_Delay;
+					ras_qn <= '0' after Sim_Delay;
+					ddr_state <= refresh_wait after Sim_Delay;
+				when refresh_wait =>
+					if refresh_wait_end = '1' then
+						ddr_state <= pre after Sim_Delay;
+					end if;
+				when pre_nop2 =>
+					ddr_state <= idle after Sim_Delay;
+				when others =>
+					ddr_state <= idle after Sim_Delay;
+			end case;
+		end if;
+	end process;
+	
+	process(cpu_clk, areset)	--
+	begin
+		if areset = '1' then
+			ddr_cmd <= "0000000000000000";
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			if ddr_command_we = '1' then
+				ddr_cmd <= ddr_command after Sim_Delay;
+			else
+				ddr_cmd <= ddr_cmd after Sim_Delay;
+			end if;
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+			ddr_cmd_we_smp <= '0';
+			new_command <= '0';
+			sdr_smp <= "000000000000000000000000000000000000";
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+			ddr_cmd_we_smp <= ddr_command_we after Sim_Delay;
+			if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then
+				new_command <= '1' after Sim_Delay;
+			elsif ddr_state = cmd or ddr_state = cpu_pre then
+				new_command <= '0' after Sim_Delay;
+			else
+				new_command <= new_command after Sim_Delay;
+			end if;
+			
+			if ddr_write_en_int = '1' then
+			   	sdr_smp <= ddr_data_write after Sim_Delay;
+			else
+				sdr_smp <= sdr_smp after Sim_Delay;
+			end if;
+			
+		end if;
+	end process;
+	
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+			dqs_q <= "00";
+			dqs_oe_n <= "11";
+			sdr_oe_ctrl <= '1';
+			sdr_wr_msw <= "000000000000000000";
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+		
+			if ddr_state = wr_nop1 and clk4_phase_short(0) = '1' then
+				sdr_oe_ctrl <= '0' after Sim_Delay;
+			elsif ddr_state = wr_nop3 and clk4_phase_short(0) = '1' then
+				sdr_oe_ctrl <= '1' after Sim_Delay;
+			else
+				sdr_oe_ctrl <= sdr_oe_ctrl after Sim_Delay;
+			end if;
+
+			if ddr_state = idle or ddr_state = wr_nop3 then
+				dqs_oe_n <= "11" after Sim_Delay;
+			elsif ddr_state = wr_nop1 then
+				dqs_oe_n  <= "00" after Sim_Delay;
+			else
+				dqs_oe_n <= dqs_oe_n after Sim_Delay;
+			end if;
+
+			if (ddr_state = wr_nop2 and clk4_phase_short(0) = '1') then
+				dqs_q <= "11" after Sim_Delay;
+			else
+				dqs_q <= "00" after Sim_Delay;
+			end if;
+			
+			if ddr_state = wr_nop1 and clk4_phase_short(1) = '1' then
+				sdr_wr_msw <= "111111111111111111" after Sim_Delay;
+			else
+				sdr_wr_msw <= "000000000000000000" after Sim_Delay;
+			end if;
+			
+		end if;
+	end process;
+	
+	-- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+		    sdr_d_p <= "ZZZZZZZZZZZZZZZZ";
+		    dm_q_p <= "11";
+		    sdr_oe_n <= "1111111111111111";
+		    sdr_d <= "0000000000000000";
+		    dm_q <= "11";
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then
+
+			for i in 0 to 15 loop
+				if sdr_oe_n(i) = '0' then
+					sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output;
+				else
+					sdr_d_p(i) <= transport 'Z' after Clk_to_Output;
+				end if;
+		   	end loop;			
+
+			dm_q_p <= transport dm_q after Clk_to_Output;
+
+			if sdr_oe_ctrl = '0' then
+				sdr_oe_n <= "0000000000000000" after Sim_Delay;
+			else
+				sdr_oe_n <= "1111111111111111" after Sim_Delay;
+			end if;
+			
+			for i in 0 to 15 loop
+				if sdr_wr_msw(i) = '0' then
+		   			sdr_d(i) <= sdr_smp(i) after Sim_Delay;
+		   		else
+		   			sdr_d(i) <= sdr_smp(i+16) after Sim_Delay;
+		   		end if;
+		   	end loop;
+		   	
+			for i in 0 to 1 loop
+				if sdr_wr_msw(i+16) = '0' then
+		   			dm_q(i) <= sdr_smp(i+32) after Sim_Delay;
+		   		else
+		   			dm_q(i) <= sdr_smp(i+34) after Sim_Delay;
+		   		end if;
+		   	end loop;
+		   	
+		end if;
+	end process;
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+			refresh_cnt <= "0000000000";
+			refresh_pend <= '0';
+			refresh_end <= '0';
+			refresh_wait_cnt <= "000";
+			refresh_wait_end <= '0';
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+		
+			if refresh_cnt = Refresh_Interval then
+				refresh_end <= '1';
+			else
+				refresh_end <= '0';
+			end if;
+			
+			if refresh_end = '1' then
+				refresh_cnt <= "0000000000";
+			else
+				refresh_cnt <= refresh_cnt + '1';
+			end if;
+			
+			if refresh_end = '1' and refresh_en = '1' then
+				refresh_pend <= '1' after Sim_Delay;
+			elsif ddr_state = refresh then
+				refresh_pend <= '0' after Sim_Delay;
+			else
+				refresh_pend <= refresh_pend after Sim_Delay;
+			end if;
+			
+			if ddr_state = refresh_wait then
+				refresh_wait_cnt <= refresh_wait_cnt + '1';
+			else
+				refresh_wait_cnt <= "000";
+			end if;
+			
+			if refresh_wait_cnt = "111" then
+				refresh_wait_end <= '1' after Sim_Delay;
+			else
+				refresh_wait_end <= '0' after Sim_Delay;
+			end if;
+			
+		end if;
+	end process;
+	
+	-- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING
+
+	process(ddr_in_clk, areset)
+	begin
+		if areset = '1' then
+			ddr_clk_tog <= '0';
+		elsif (ddr_in_clk'event and ddr_in_clk = '1') then
+			ddr_clk_tog <= not(ddr_clk_tog) after Sim_Delay;
+		end if;
+	end process;	
+	
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			ddr_clk_smp1 <= '0';
+			ddr_clk_smp2 <= '0';
+			ddr_clk_phase <= '0';
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			ddr_clk_smp1 <= ddr_clk_tog after Sim_Delay;
+			ddr_clk_smp2 <= ddr_clk_smp1 after Sim_Delay;
+			if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then
+				ddr_clk_phase <= '0';
+			else
+				ddr_clk_phase <= not(ddr_clk_phase);
+			end if;
+		end if;
+	end process;
+
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			cas_n_smp <= '0';
+			ras_n_smp <= '0';
+			we_n_smp <= '0';
+			read_start_sig <= '0';
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			cas_n_smp <= cas_qn_p_del after Sim_Delay;
+			ras_n_smp <= ras_qn_p_del after Sim_Delay;
+			we_n_smp <= we_qn_p_del after Sim_Delay;
+			if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then
+				read_start_sig <= '1' after Sim_Delay;
+			else
+				read_start_sig <= '0' after Sim_Delay;
+			end if;
+		end if;
+	end process;
+
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			sdr_d_in <= "0000000000000000";
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			sdr_d_in <= sdr_d_p_del after Sim_Delay;
+		end if;
+	end process;
+	
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			read_time_cnt <= "00";
+			read_input_en <= '0';
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+
+			if read_start_sig = '1' then	
+				read_time_cnt <= "01" after Sim_Delay;
+			elsif read_time_cnt = "00" then
+				read_time_cnt <= read_time_cnt after Sim_Delay;
+			else
+				read_time_cnt <= read_time_cnt + '1' after Sim_Delay;
+			end if;
+
+			if read_time_cnt = "11" then
+				read_input_en <= '1' after Sim_Delay;
+			else
+				read_input_en <= '0' after Sim_Delay;
+			end if;
+
+		end if;
+	end process;
+	
+	process(ddr_in_clk_2x, areset)
+	begin
+		if areset = '1' then
+			ddr_data_read_int <= "00000000000000000000000000000000";
+		elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then
+			ddr_data_read_int(31 downto 16) <= "0000000000000000" after Sim_Delay;
+			if read_input_en = '1' then
+				ddr_data_read_int(15 downto 0) <= sdr_d_in after Sim_Delay;
+			else
+				ddr_data_read_int(15 downto 0) <= ddr_data_read_int(15 downto 0) after Sim_Delay;
+			end if;
+		end if;
+	end process;
+
+
+
+
+
+
+
+
+	-- ###############
+
+	process(cpu_clk, areset)	--
+	begin
+		if areset = '1' then
+		elsif (cpu_clk'event and cpu_clk = '1') then
+		end if;
+	end process;
+	
+	
+	process(cpu_clk_2x, areset)	--
+	begin
+		if areset = '1' then
+		elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then
+		end if;
+	end process;
+	
+	
+	process(cpu_clk_4x, areset)	--
+	begin
+		if areset = '1' then
+		elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then
+		end if;
+	end process;
+	
+
+end behave;
+
+
diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd
new file mode 100644
index 0000000..6b89345
--- /dev/null
+++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd
@@ -0,0 +1,1320 @@
+-----------------------------------------------------------------------------------------
+--
+--     File Name: MT46V16M16.VHD
+--       Version: 2.1
+--          Date: January 14th, 2002
+--         Model: Behavioral
+--     Simulator: NCDesktop      - http://www.cadence.com
+--                ModelSim PE    - http://www.model.com
+--
+--  Dependencies: None
+--
+--        Author: Son P. Huynh
+--         Email: sphuynh@micron.com
+--         Phone: (208) 368-3825
+--       Company: Micron Technology, Inc.
+--   Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
+--
+--   Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
+--
+--    Limitation: Doesn't model internal refresh counter
+--
+--          Note: 
+--
+--    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
+--                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
+--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+--
+--                Copyright (c) 1998 Micron Semiconductor Products, Inc.
+--                All rights researved
+--
+--  Rev  Author                        Date        Changes
+--  ---  ----------------------------  ----------  -------------------------------------
+--  2.1  Son P. Huynh                  01/14/2002  - Fix Burst_counter
+--       Micron Technology, Inc.
+--
+--  2.0  Son P. Huynh                  11/08/2001  - Second release
+--       Micron Technology, Inc.                   - Rewrote and remove SHARED VARIABLE
+--
+-----------------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+    USE IEEE.STD_LOGIC_1164.ALL;
+    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+    USE IEEE.STD_LOGIC_ARITH.ALL;
+
+ENTITY MT46V16M16 IS
+    GENERIC (                                   -- Timing for -75Z CL2
+        tCK       : TIME    :=  7.500 ns;
+        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
+        tDH       : TIME    :=  0.500 ns;
+        tDS       : TIME    :=  0.500 ns;
+        tIH       : TIME    :=  0.900 ns;
+        tIS       : TIME    :=  0.900 ns;
+        tMRD      : TIME    := 15.000 ns;
+        tRAS      : TIME    := 40.000 ns;
+        tRAP      : TIME    := 20.000 ns;
+        tRC       : TIME    := 65.000 ns;
+        tRFC      : TIME    := 75.000 ns;
+        tRCD      : TIME    := 20.000 ns;
+        tRP       : TIME    := 20.000 ns;
+        tRRD      : TIME    := 15.000 ns;
+        tWR       : TIME    := 15.000 ns;
+        addr_bits : INTEGER := 13;
+        data_bits : INTEGER := 16;
+        cols_bits : INTEGER :=  9
+    );
+    PORT (
+        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
+        Clk   : IN    STD_LOGIC;
+        Clk_n : IN    STD_LOGIC;
+        Cke   : IN    STD_LOGIC;
+        Cs_n  : IN    STD_LOGIC;
+        Ras_n : IN    STD_LOGIC;
+        Cas_n : IN    STD_LOGIC;
+        We_n  : IN    STD_LOGIC;
+        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
+    );
+END MT46V16M16;
+
+ARCHITECTURE behave OF MT46V16M16 IS
+    -- Array for Read pipeline
+    TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+    TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+    -- Array for Write pipeline
+    TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+    TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+    -- Array for Auto Precharge
+    TYPE Array_Read_precharge  IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
+
+    -- Array for Manual Precharge
+    TYPE Array_A10_precharge  IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+    TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
+    TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+    
+    -- Array for Burst Terminate
+    TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
+
+    -- Array for Memory Access
+    TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+    TYPE Array_ram_pntr IS ACCESS Array_ram_type;
+    TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
+
+    -- Data pair
+    SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
+    SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+    -- Mode Register
+    SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+    
+    -- Command Decode Variables
+    SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
+    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
+    
+    -- Burst Length Decode Variables
+    SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
+    
+    -- Cas Latency Decode Variables
+    SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
+
+    -- Internal Control Signals
+    SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
+
+    -- System Clock
+    SIGNAL Sys_clk : STD_LOGIC := '0';
+
+    -- Dqs buffer
+    SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+
+BEGIN
+    -- Strip the strength
+    Cs_in  <= To_X01 (Cs_n);
+    Ras_in <= To_X01 (Ras_n);
+    Cas_in <= To_X01 (Cas_n);
+    We_in  <= To_X01 (We_n);
+    
+    -- Commands Decode
+    Active_enable   <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND     We_in;
+    Aref_enable     <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND     We_in;
+    Burst_term      <= NOT(Cs_in) AND     Ras_in  AND     Cas_in  AND NOT(We_in);
+    Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND     Ba(0)  AND NOT(Ba(1));
+    Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
+    Prech_enable    <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND NOT(We_in);
+    Read_enable     <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND     We_in;
+    Write_enable    <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND NOT(We_in);
+
+    -- Burst Length Decode
+    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);
+    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));
+    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
+    Burst_length_f  <=    (Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
+
+    -- CAS Latency Decode
+    Cas_latency_15  <=     Mode_reg(6)  AND NOT(Mode_reg(5)) AND    (Mode_reg(4));
+    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));
+    Cas_latency_25  <=     Mode_reg(6)  AND     Mode_reg(5)  AND NOT(Mode_reg(4));
+    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);
+    Cas_latency_4   <=    (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
+
+    -- Dqs buffer
+    Dqs <= Dqs_out;
+
+    --
+    -- System Clock
+    --
+    int_clk : PROCESS (Clk, Clk_n)
+        VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
+    begin
+        IF Clk = '1' AND Clk_n = '0' THEN
+            ClkZ := '1';
+            CkeZ := Cke;
+        ELSIF Clk = '0' AND Clk_n = '1' THEN
+            ClkZ := '0';
+        END IF;
+        Sys_clk <= CkeZ AND ClkZ;
+    END PROCESS;
+
+    --
+    -- Main Process
+    --
+    state_register : PROCESS
+        -- Precharge Variables
+        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
+
+        -- Activate Variables
+        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
+
+        -- Data IO variables
+        VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
+
+        -- Internal address mux variables
+        VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
+        VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+        VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+        VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
+
+        -- DLL Reset variables
+        VARIABLE DLL_enable : STD_LOGIC := '0';
+        VARIABLE DLL_reset : STD_LOGIC := '0';
+        VARIABLE DLL_done : STD_LOGIC := '0';
+        VARIABLE DLL_count : INTEGER := 0;
+        
+        -- Timing Check
+        VARIABLE MRD_chk : TIME := 0 ns;
+        VARIABLE RFC_chk : TIME := 0 ns;
+        VARIABLE RRD_chk : TIME := 0 ns;
+        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
+        VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
+        VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
+        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
+        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
+        VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
+
+        -- Read pipeline variables
+        VARIABLE Read_cmnd : Array_Read_cmnd;
+        VARIABLE Read_bank : Array_Read_bank;
+        VARIABLE Read_cols : Array_Read_cols;
+
+        -- Write pipeline variables
+        VARIABLE Write_cmnd : Array_Write_cmnd;
+        VARIABLE Write_bank : Array_Write_bank;
+        VARIABLE Write_cols : Array_Write_cols;
+
+        -- Auto Precharge variables
+        VARIABLE Read_precharge  : Array_Read_precharge  := ('0' & '0' & '0' & '0');
+        VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
+        VARIABLE Count_precharge : Array_Count_precharge := ( 0  &  0  &  0  &  0 );
+
+        -- Manual Precharge variables
+        VARIABLE A10_precharge  : Array_A10_precharge;
+        VARIABLE Bank_precharge : Array_Bank_precharge;
+        VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
+
+        -- Burst Terminate variable
+        VARIABLE Cmnd_bst : Array_Cmnd_bst;
+
+        -- Memory Banks
+        VARIABLE Bank0 : Array_ram_stor;
+        VARIABLE Bank1 : Array_ram_stor;
+        VARIABLE Bank2 : Array_ram_stor;
+        VARIABLE Bank3 : Array_ram_stor;
+
+        -- Burst Counter
+        VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
+
+        -- Internal Dqs initialize
+        VARIABLE Dqs_int : STD_LOGIC := '0';
+
+        -- Data buffer for DM Mask
+        VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+
+        --
+        -- Initialize empty rows
+        --
+        PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
+            VARIABLE i, j : INTEGER := 0;
+        BEGIN
+            IF Bank = "00" THEN
+                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty
+                    Bank0 (Row_index) := NEW Array_ram_type;            -- Open new row for access
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP           -- Filled row with zeros
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank0 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "01" THEN
+                IF Bank1 (Row_index) = NULL THEN
+                    Bank1 (Row_index) := NEW Array_ram_type;
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank1 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "10" THEN
+                IF Bank2 (Row_index) = NULL THEN
+                    Bank2 (Row_index) := NEW Array_ram_type;
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank2 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "11" THEN
+                IF Bank3 (Row_index) = NULL THEN
+                    Bank3 (Row_index) := NEW Array_ram_type;
+                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
+                            Bank3 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            END IF;
+        END;
+
+        --
+        -- Burst Counter
+        --
+        PROCEDURE Burst_decode IS
+            VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        BEGIN
+            -- Advance burst counter
+            Burst_counter := Burst_counter + 1;
+
+            -- Burst Type
+            IF Mode_reg (3) = '0' THEN
+                Cols_temp := Cols_addr + 1;
+            ELSIF Mode_reg (3) = '1' THEN
+                Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
+                Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
+                Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
+            END IF;
+
+            -- Burst Length
+            IF Burst_length_2 = '1' THEN
+                Cols_addr (0) := Cols_temp (0);
+            ELSIF Burst_length_4 = '1' THEN
+                Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
+            ELSIF Burst_length_8 = '1' THEN
+                Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
+            ELSE
+                Cols_addr := Cols_temp;
+            END IF;
+
+            -- Data counter
+            IF Burst_length_2 = '1' THEN
+                IF Burst_counter >= 2 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_4 = '1' THEN
+                IF Burst_counter >= 4 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_8 = '1' THEN
+                IF Burst_counter >= 8 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            END IF;
+        END;
+
+    BEGIN
+        WAIT ON Sys_clk;
+
+        --
+        -- Manual Precharge Pipeline
+        --
+        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+            -- A10 Precharge Pipeline
+            A10_precharge(0) := A10_precharge(1);
+            A10_precharge(1) := A10_precharge(2);
+            A10_precharge(2) := A10_precharge(3);
+            A10_precharge(3) := A10_precharge(4);
+            A10_precharge(4) := A10_precharge(5);
+            A10_precharge(5) := A10_precharge(6);
+            A10_precharge(6) := A10_precharge(7);
+            A10_precharge(7) := A10_precharge(8);
+            A10_precharge(8) := '0';
+
+            -- Bank Precharge Pipeline
+            Bank_precharge(0) := Bank_precharge(1);
+            Bank_precharge(1) := Bank_precharge(2);
+            Bank_precharge(2) := Bank_precharge(3);
+            Bank_precharge(3) := Bank_precharge(4);
+            Bank_precharge(4) := Bank_precharge(5);
+            Bank_precharge(5) := Bank_precharge(6);
+            Bank_precharge(6) := Bank_precharge(7);
+            Bank_precharge(7) := Bank_precharge(8);
+            Bank_precharge(8) := "00";
+
+            -- Command Precharge Pipeline
+            Cmnd_precharge(0) := Cmnd_precharge(1);
+            Cmnd_precharge(1) := Cmnd_precharge(2);
+            Cmnd_precharge(2) := Cmnd_precharge(3);
+            Cmnd_precharge(3) := Cmnd_precharge(4);
+            Cmnd_precharge(4) := Cmnd_precharge(5);
+            Cmnd_precharge(5) := Cmnd_precharge(6);
+            Cmnd_precharge(6) := Cmnd_precharge(7);
+            Cmnd_precharge(7) := Cmnd_precharge(8);
+            Cmnd_precharge(8) := '0';
+
+            -- Terminate Read if same bank or all banks
+            IF ((Cmnd_precharge (0) = '1') AND
+                (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
+                (Data_out_enable = '1')) THEN
+                Data_out_enable := '0';
+            END IF;
+        END IF;
+
+        --
+        -- Burst Terminate Pipeline
+        --
+        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+            -- Burst Terminate pipeline
+            Cmnd_bst (0) := Cmnd_bst (1);
+            Cmnd_bst (1) := Cmnd_bst (2);
+            Cmnd_bst (2) := Cmnd_bst (3);
+            Cmnd_bst (3) := Cmnd_bst (4);
+            Cmnd_bst (4) := Cmnd_bst (5);
+            Cmnd_bst (5) := Cmnd_bst (6);
+            Cmnd_bst (6) := Cmnd_bst (7);
+            Cmnd_bst (7) := Cmnd_bst (8);
+            Cmnd_bst (8) := '0';
+
+            -- Terminate current Read
+            IF ((Cmnd_bst  (0) = '1') AND (Data_out_enable = '1')) THEN
+                Data_out_enable := '0';
+            END IF;
+        END IF;
+
+        --
+        -- Dq and Dqs Drivers
+        --
+        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
+            -- Read Command Pipeline
+            Read_cmnd (0) := Read_cmnd (1);
+            Read_cmnd (1) := Read_cmnd (2);
+            Read_cmnd (2) := Read_cmnd (3);
+            Read_cmnd (3) := Read_cmnd (4);
+            Read_cmnd (4) := Read_cmnd (5);
+            Read_cmnd (5) := Read_cmnd (6);
+            Read_cmnd (6) := Read_cmnd (7);
+            Read_cmnd (7) := Read_cmnd (8);
+            Read_cmnd (8) := '0';
+
+            -- Read Bank Pipeline
+            Read_bank (0) := Read_bank (1);
+            Read_bank (1) := Read_bank (2);
+            Read_bank (2) := Read_bank (3);
+            Read_bank (3) := Read_bank (4);
+            Read_bank (4) := Read_bank (5);
+            Read_bank (5) := Read_bank (6);
+            Read_bank (6) := Read_bank (7);
+            Read_bank (7) := Read_bank (8);
+            Read_bank (8) := "00";
+
+            -- Read Column Pipeline
+            Read_cols (0) := Read_cols (1);
+            Read_cols (1) := Read_cols (2);
+            Read_cols (2) := Read_cols (3);
+            Read_cols (3) := Read_cols (4);
+            Read_cols (4) := Read_cols (5);
+            Read_cols (5) := Read_cols (6);
+            Read_cols (6) := Read_cols (7);
+            Read_cols (7) := Read_cols (8);
+            Read_cols (8) := (OTHERS => '0');
+
+            -- Initialize Read command
+            IF Read_cmnd (0) = '1' THEN
+                Data_out_enable := '1';
+                Bank_addr := Read_bank (0);
+                Cols_addr := Read_cols (0);
+                Cols_brst := Cols_addr (2 DOWNTO 0);
+                Burst_counter := (OTHERS => '0');
+
+                -- Row address mux
+                CASE Bank_addr IS
+                    WHEN "00"   => Rows_addr := B0_row_addr;
+                    WHEN "01"   => Rows_addr := B1_row_addr;
+                    WHEN "10"   => Rows_addr := B2_row_addr;
+                    WHEN OTHERS => Rows_addr := B3_row_addr;
+                END CASE;
+            END IF;
+
+            -- Toggle Dqs during Read command
+            IF Data_out_enable = '1' THEN
+                Dqs_int := '0';
+                IF Dqs_out = "00" THEN
+                    Dqs_out <= "11";
+                ELSIF Dqs_out = "11" THEN
+                    Dqs_out <= "00";
+                ELSE
+                    Dqs_out <= "00";
+                END IF;
+            ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
+                Dqs_out <= "ZZ";
+            END IF;
+
+            -- Initialize Dqs for Read command
+            IF Read_cmnd (2) = '1' THEN
+                IF Data_out_enable = '0' THEN
+                    Dqs_int := '1';
+                    Dqs_out <= "00";
+                END IF;
+            END IF;
+
+            -- Read Latch
+            IF Data_out_enable = '1' THEN
+                -- Initialize Memory
+                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
+                
+                -- Output Data
+                CASE Bank_addr IS
+                    WHEN "00"   => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    WHEN "01"   => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    WHEN "10"   => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                END CASE;
+
+                --  Increase Burst Counter
+                Burst_decode;
+            ELSE
+                Dq <= (OTHERS => 'Z');
+            END IF;
+        END IF;
+
+        --
+        -- Write FIFO and DM Mask Logic
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            -- Write command pipeline
+            Write_cmnd (0) := Write_cmnd (1);
+            Write_cmnd (1) := Write_cmnd (2);
+            Write_cmnd (2) := '0';
+
+            -- Write command pipeline
+            Write_bank (0) := Write_bank (1);
+            Write_bank (1) := Write_bank (2);
+            Write_bank (2) := "00";
+
+            -- Write column pipeline
+            Write_cols (0) := Write_cols (1);
+            Write_cols (1) := Write_cols (2);
+            Write_cols (2) := (OTHERS => '0');
+
+            -- Initialize Write command
+            IF Write_cmnd (0) = '1' THEN
+                Data_in_enable := '1';
+                Bank_addr := Write_bank (0);
+                Cols_addr := Write_cols (0);
+                Cols_brst := Cols_addr (2 DOWNTO 0);
+                Burst_counter := (OTHERS => '0');
+
+                -- Row address mux
+                CASE Bank_addr IS
+                    WHEN "00"   => Rows_addr := B0_row_addr;
+                    WHEN "01"   => Rows_addr := B1_row_addr;
+                    WHEN "10"   => Rows_addr := B2_row_addr;
+                    WHEN OTHERS => Rows_addr := B3_row_addr;
+                END CASE;
+            END IF;
+
+            -- Write data
+            IF Data_in_enable = '1' THEN
+                -- Initialize memory
+                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
+                
+                -- Write first data
+                IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
+                    -- Data Buffer
+                    CASE Bank_addr IS
+                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    END CASE;
+
+                    -- Perform DM Mask
+                    IF Dm_pair (0) = '0' THEN
+                        Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
+                    END IF;
+                    IF Dm_pair (1) = '0' THEN
+                        Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
+                    END IF;
+
+                    -- Write Data
+                    CASE Bank_addr IS
+                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                    END CASE;
+                END IF;
+
+                --  Increase Burst Counter
+                Burst_decode;
+
+                -- Write second data
+                IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
+                    -- Data Buffer
+                    CASE Bank_addr IS
+                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
+                    END CASE;
+
+                    -- Perform DM Mask
+                    IF Dm_pair (2) = '0' THEN
+                        Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
+                    END IF;
+                    IF Dm_pair (3) = '0' THEN
+                        Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
+                    END IF;
+
+                    -- Write Data
+                    CASE Bank_addr IS
+                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
+                    END CASE;
+                END IF;
+                
+                -- Increase Burst Counter
+                Burst_decode;
+
+                -- tWR start and tWTR check
+                IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
+                    CASE Bank_addr IS
+                        WHEN "00"   => WR_chk0 := NOW;
+                        WHEN "01"   => WR_chk1 := NOW;
+                        WHEN "10"   => WR_chk2 := NOW;
+                        WHEN OTHERS => WR_chk3 := NOW;
+                    END CASE;
+
+                    -- tWTR check
+                    ASSERT (Read_enable = '0')
+                        REPORT "tWTR violation during Read"
+                        SEVERITY WARNING;
+                END IF;
+            END IF;
+        END IF;
+
+        --
+        -- Auto Precharge Calculation
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            -- Precharge counter
+            IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
+                Count_precharge (0) := Count_precharge (0) + 1;
+            END IF;
+            IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
+                Count_precharge (1) := Count_precharge (1) + 1;
+            END IF;
+            IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
+                Count_precharge (2) := Count_precharge (2) + 1;
+            END IF;
+            IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
+                Count_precharge (3) := Count_precharge (3) + 1;
+            END IF;
+
+            -- Read with AutoPrecharge Calculation
+            --      The device start internal precharge when:
+            --          1.  Meet tRAS requirement
+            --          2.  BL/2 cycles after command
+            IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(0) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
+                    Pc_b0 := '1';
+                    Act_b0 := '0';
+                    RP_chk0 := NOW;
+                    Read_precharge(0) := '0';
+                END IF;
+            END IF;
+            IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(1) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
+                    Pc_b1 := '1';
+                    Act_b1 := '0';
+                    RP_chk1 := NOW;
+                    Read_precharge(1) := '0';
+                END IF;
+            END IF;
+            IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(2) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
+                    Pc_b2 := '1';
+                    Act_b2 := '0';
+                    RP_chk2 := NOW;
+                    Read_precharge(2) := '0';
+                END IF;
+            END IF;
+            IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1)  OR
+                    (Burst_length_4 = '1' AND Count_precharge(3) >= 2)  OR
+                    (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
+                    Pc_b3 := '1';
+                    Act_b3 := '0';
+                    RP_chk3 := NOW;
+                    Read_precharge(3) := '0';
+                END IF;
+            END IF;
+
+            -- Write with AutoPrecharge Calculation
+            --      The device start internal precharge when:
+            --          1.  Meet tRAS requirement
+            --          2.  Two clock after last burst
+            -- Since tWR is time base, the model will compensate tRP
+            IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
+                    Pc_b0 := '1';
+                    Act_b0 := '0';
+                    RP_chk0 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(0) := '0';
+                END IF;
+            END IF;
+            IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
+                    Pc_b1 := '1';
+                    Act_b1 := '0';
+                    RP_chk1 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(1) := '0';
+                END IF;
+            END IF;
+            IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
+                    Pc_b2 := '1';
+                    Act_b2 := '0';
+                    RP_chk2 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(2) := '0';
+                END IF;
+            END IF;
+            IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
+                IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
+                    (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
+                    (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
+                    Pc_b3 := '1';
+                    Act_b3 := '0';
+                    RP_chk3 := NOW - ((2 * tCK) - tWR);
+                    Write_precharge(3) := '0';
+                END IF;
+            END IF;
+        END IF;
+        
+        --
+        -- DLL Counter
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            IF (DLL_Reset = '1' AND DLL_done = '0') THEN
+                DLL_count := DLL_count + 1;
+                IF (DLL_count >= 200) THEN
+                    DLL_done := '1';
+                END IF;
+            END IF;
+        END IF;
+
+        --
+        -- Control Logic
+        --
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            -- Auto Refresh
+            IF Aref_enable = '1' THEN
+                -- Auto Refresh to Auto Refresh
+                ASSERT (NOW - RFC_chk >= tRFC)
+                    REPORT "tRFC violation during Auto Refresh"
+                    SEVERITY WARNING;
+
+                -- Precharge to Auto Refresh
+                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+                    REPORT "tRP violation during Auto Refresh"
+                    SEVERITY WARNING;
+
+                -- Precharge to Auto Refresh
+                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+                    REPORT "All banks must be Precharge before Auto Refresh"
+                    SEVERITY WARNING;
+
+                -- Record current tRFC time
+                RFC_chk := NOW;
+            END IF;
+
+            -- Extended Load Mode Register
+            IF Ext_mode_enable = '1' THEN
+                IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
+                    IF (Addr (0) = '0') THEN
+                        DLL_enable := '1';
+                    ELSE
+                        DLL_enable := '0';
+                    END IF;
+                END IF;
+                
+                -- Precharge to EMR
+                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+                    REPORT "All bank must be Precharged before Extended Mode Register"
+                    SEVERITY WARNING;
+                
+                -- Precharge to EMR
+                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+                    REPORT "tRP violation during Extended Load Register"
+                    SEVERITY WARNING;
+
+                -- LMR/EMR to EMR
+                ASSERT (NOW - MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Extended Mode Register"
+                    SEVERITY WARNING;
+
+                -- Record current tMRD time
+                MRD_chk := NOW;
+            END IF;
+
+            -- Load Mode Register
+            IF Mode_reg_enable = '1' THEN
+                -- Register mode
+                Mode_reg <= Addr;
+                
+                -- DLL Reset
+                IF (DLL_enable = '1' AND Addr (8) = '1') THEN
+                    DLL_reset := '1';
+                    DLL_done  := '0';
+                    DLL_count := 0;
+                ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
+                    ASSERT (FALSE)
+                        REPORT "DLL is ENABLE: DLL RESET is require"
+                        SEVERITY WARNING;
+                ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
+                    ASSERT (FALSE)
+                        REPORT "DLL is DISABLE: DLL RESET will be ignored"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge to LMR
+                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
+                    REPORT "All bank must be Precharged before Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Precharge to EMR
+                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
+                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
+                    REPORT "tRP violation during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- LMR/ELMR to LMR
+                ASSERT (NOW - MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Check for invalid Burst Length
+                ASSERT ((Addr (2 DOWNTO 0) = "001") OR      -- BL = 2
+                        (Addr (2 DOWNTO 0) = "010") OR      -- BL = 4
+                        (Addr (2 DOWNTO 0) = "011"))        -- BL = 8
+                    REPORT "Invalid Burst Length during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Check for invalid CAS Latency
+                ASSERT ((Addr (6 DOWNTO 4) = "010") OR      -- CL = 2.0
+                        (Addr (6 DOWNTO 4) = "110"))        -- CL = 2.5
+                    REPORT "Invalid CAS Latency during Load Mode Register"
+                    SEVERITY WARNING;
+
+                -- Record current tMRD time
+                MRD_chk := NOW;
+            END IF;
+
+            -- Active Block (latch Bank and Row Address)
+            IF Active_enable = '1' THEN
+                -- Activate an OPEN bank can corrupt data
+                ASSERT ((Ba = "00" AND Act_b0 = '0') OR
+                        (Ba = "01" AND Act_b1 = '0') OR
+                        (Ba = "10" AND Act_b2 = '0') OR
+                        (Ba = "11" AND Act_b3 = '0'))
+                    REPORT "Bank is already activated - data can be corrupted"
+                    SEVERITY WARNING;
+
+                -- Activate Bank 0
+                IF Ba = "00" AND Pc_b0 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk0 >= tRC)
+                        REPORT "tRC violation during Activate Bank 0"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk0 >= tRP)
+                        REPORT "tRP violation during Activate Bank 0"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b0 := '1';
+                    Pc_b0 := '0';
+                    B0_row_addr := Addr;
+                    RC_chk0 := NOW;
+                    RCD_chk0 := NOW;
+                    RAS_chk0 := NOW;
+                    RAP_chk0 := NOW;
+                END IF;
+
+                -- Activate Bank 1
+                IF Ba = "01" AND Pc_b1 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk1 >= tRC)
+                        REPORT "tRC violation during Activate Bank 1"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk1 >= tRP)
+                        REPORT "tRP violation during Activate Bank 1"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b1 := '1';
+                    Pc_b1 := '0';
+                    B1_row_addr := Addr;
+                    RC_chk1 := NOW;
+                    RCD_chk1 := NOW;
+                    RAS_chk1 := NOW;
+                    RAP_chk1 := NOW;
+                END IF;
+
+                -- Activate Bank 2
+                IF Ba = "10" AND Pc_b2 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk2 >= tRC)
+                        REPORT "tRC violation during Activate Bank 2"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk2 >= tRP)
+                        REPORT "tRP violation during Activate Bank 2"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b2 := '1';
+                    Pc_b2 := '0';
+                    B2_row_addr := Addr;
+                    RC_chk2 := NOW;
+                    RCD_chk2 := NOW;
+                    RAS_chk2 := NOW;
+                    RAP_chk2 := NOW;
+                END IF;
+
+                -- Activate Bank 3
+                IF Ba = "11" AND Pc_b3 = '1' THEN
+                    -- Activate to Activate (same bank)
+                    ASSERT (NOW - RC_chk3 >= tRC)
+                        REPORT "tRC violation during Activate Bank 3"
+                        SEVERITY WARNING;
+
+                    -- Precharge to Active
+                    ASSERT (NOW - RP_chk3 >= tRP)
+                        REPORT "tRP violation during Activate Bank 3"
+                        SEVERITY WARNING;
+
+                    -- Record Variables for checking violation
+                    Act_b3 := '1';
+                    Pc_b3 := '0';
+                    B3_row_addr := Addr;
+                    RC_chk3 := NOW;
+                    RCD_chk3 := NOW;
+                    RAS_chk3 := NOW;
+                    RAP_chk3 := NOW;
+                END IF;
+
+                -- Activate Bank A to Activate Bank B
+                IF (Prev_bank /= Ba) THEN
+                    ASSERT (NOW - RRD_chk >= tRRD)
+                        REPORT "tRRD violation during Activate"
+                        SEVERITY WARNING;
+                END IF;
+                
+                -- AutoRefresh to Activate
+                ASSERT (NOW - RFC_chk >= tRFC)
+                    REPORT "tRFC violation during Activate"
+                    SEVERITY WARNING;
+                
+                -- Record Variables for Checking Violation
+                RRD_chk := NOW;
+                Prev_bank := Ba;
+            END IF;
+
+            -- Precharge Block - Consider NOP if bank already precharged or in process of precharging
+            IF Prech_enable = '1' THEN
+                -- EMR or LMR to Precharge
+                ASSERT (NOW - MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Precharge"
+                    SEVERITY WARNING;
+
+                -- Precharge Bank 0
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
+                    Act_b0 := '0';
+                    Pc_b0 := '1';
+                    RP_chk0 := NOW;
+
+                    -- Activate to Precharge bank 0
+                    ASSERT (NOW - RAS_chk0 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk0 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge Bank 1
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
+                    Act_b1 := '0';
+                    Pc_b1 := '1';
+                    RP_chk1 := NOW;
+
+                    -- Activate to Precharge
+                    ASSERT (NOW - RAS_chk1 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk1 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge Bank 2
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
+                    Act_b2 := '0';
+                    Pc_b2 := '1';
+                    RP_chk2 := NOW;
+
+                    -- Activate to Precharge
+                    ASSERT (NOW - RAS_chk2 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk2 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Precharge Bank 3
+                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
+                    Act_b3 := '0';
+                    Pc_b3 := '1';
+                    RP_chk3 := NOW;
+
+                    -- Activate to Precharge
+                    ASSERT (NOW - RAS_chk3 >= tRAS)
+                        REPORT "tRAS violation during Precharge"
+                        SEVERITY WARNING;
+
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chk3 >= tWR)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Pipeline for READ
+                IF CAS_latency_15 = '1' THEN
+                    A10_precharge  (3) := Addr(10);
+                    Bank_precharge (3) := Ba;
+                    Cmnd_precharge (3) := '1';
+                ELSIF CAS_latency_2 = '1' THEN
+                    A10_precharge  (4) := Addr(10);
+                    Bank_precharge (4) := Ba;
+                    Cmnd_precharge (4) := '1';
+                ELSIF CAS_latency_25 = '1' THEN
+                    A10_precharge  (5) := Addr(10);
+                    Bank_precharge (5) := Ba;
+                    Cmnd_precharge (5) := '1';
+                ELSIF CAS_latency_3 = '1' THEN
+                    A10_precharge  (6) := Addr(10);
+                    Bank_precharge (6) := Ba;
+                    Cmnd_precharge (6) := '1';
+                ELSIF CAS_latency_4 = '1' THEN
+                    A10_precharge  (8) := Addr(10);
+                    Bank_precharge (8) := Ba;
+                    Cmnd_precharge (8) := '1';
+                END IF;
+            END IF;
+
+            -- Burst Terminate
+            IF Burst_term = '1' THEN
+                -- Pipeline for Read
+                IF CAS_latency_15 = '1' THEN
+                    Cmnd_bst (3) := '1';
+                ELSIF CAS_latency_2 = '1' THEN
+                    Cmnd_bst (4) := '1';
+                ELSIF CAS_latency_25 = '1' THEN
+                    Cmnd_bst (5) := '1';
+                ELSIF CAS_latency_3 = '1' THEN
+                    Cmnd_bst (6) := '1';
+                ELSIF CAS_latency_4 = '1' THEN
+                    Cmnd_bst (8) := '1';
+                END IF;
+
+                -- Terminate Write
+                ASSERT (Data_in_enable = '0')
+                    REPORT "It's illegal to Burst Terminate a Write"
+                    SEVERITY WARNING;
+
+                -- Terminate Read with Auto Precharge
+                ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
+                        Read_precharge (2) = '0' AND Read_precharge (3) = '0')
+                    REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
+                    SEVERITY WARNING;
+            END IF;
+
+            -- Read Command
+            IF Read_enable = '1' THEN
+                -- CAS Latency Pipeline
+                IF Cas_latency_15 = '1' THEN
+                    Read_cmnd (3) := '1';
+                    Read_bank (3) := Ba;
+                    Read_cols (3) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_2 = '1' THEN
+                    Read_cmnd (4) := '1';
+                    Read_bank (4) := Ba;
+                    Read_cols (4) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_25 = '1' THEN
+                    Read_cmnd (5) := '1';
+                    Read_bank (5) := Ba;
+                    Read_cols (5) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_3 = '1' THEN
+                    Read_cmnd (6) := '1';
+                    Read_bank (6) := Ba;
+                    Read_cols (6) := Addr (8 DOWNTO 0);
+                ELSIF Cas_latency_4 = '1' THEN
+                    Read_cmnd (8) := '1';
+                    Read_bank (8) := Ba;
+                    Read_cols (8) := Addr (8 DOWNTO 0);
+                END IF;
+
+                -- Write to Read: Terminate Write Immediately
+                IF Data_in_enable = '1' THEN
+                    Data_in_enable := '0';
+                END IF;
+
+                -- Interrupting a Read with Auto Precharge (same bank only)
+                ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
+                    REPORT "It's illegal to interrupt a Read with Auto Precharge"
+                    SEVERITY WARNING;
+
+                -- Activate to Read
+                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
+                        (Ba = "01" AND Act_b1 = '1') OR
+                        (Ba = "10" AND Act_b2 = '1') OR
+                        (Ba = "11" AND Act_b3 = '1'))
+                    REPORT "Bank is not Activated for Read"
+                    SEVERITY WARNING;
+
+                -- Activate to Read without Auto Precharge
+                IF Addr (10) = '0' THEN
+                    ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+                            (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+                            (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+                            (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+                        REPORT "tRCD violation during Read"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Activate to Read with Auto Precharge
+                IF Addr (10) = '1' THEN
+                    ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
+                            (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
+                            (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
+                            (Ba = "11" AND NOW - RAP_chk3 >= tRAP))
+                        REPORT "tRAP violation during Read"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Auto precharge
+                IF Addr (10) = '1' THEN
+                    Read_precharge (Conv_INTEGER(Ba)) := '1';
+                    Count_precharge (Conv_INTEGER(Ba)) := 0;
+                END IF;
+
+                -- DLL Check
+                IF (DLL_reset = '1') THEN
+                    ASSERT (DLL_done = '1')
+                        REPORT "DLL RESET not complete"
+                        SEVERITY WARNING;
+                END IF;
+            END IF;
+
+            -- Write Command
+            IF Write_enable = '1' THEN
+                -- Pipeline for Write
+                Write_cmnd (2) := '1';
+                Write_bank (2) := Ba;
+                Write_cols (2) := Addr (8 DOWNTO 0);
+
+                -- Interrupting a Write with Auto Precharge (same bank only)
+                ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
+                    REPORT "It's illegal to interrupt a Write with Auto Precharge"
+                    SEVERITY WARNING;
+
+                -- Activate to Write
+                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
+                        (Ba = "01" AND Act_b1 = '1') OR
+                        (Ba = "10" AND Act_b2 = '1') OR
+                        (Ba = "11" AND Act_b3 = '1'))
+                    REPORT "Bank is not Activated for Write"
+                    SEVERITY WARNING;
+
+                -- Activate to Write
+                ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
+                        (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
+                        (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
+                        (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
+                    REPORT "tRCD violation during Write"
+                    SEVERITY WARNING;
+
+                -- Auto precharge
+                IF Addr (10) = '1' THEN
+                    Write_precharge (Conv_INTEGER(Ba)) := '1';
+                    Count_precharge (Conv_INTEGER(Ba)) := 0;
+                END IF;
+            END IF;
+        END IF;
+    END PROCESS;
+
+    --
+    -- Dqs Receiver
+    --
+    dqs_rcvrs : PROCESS
+        VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
+        VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
+    BEGIN
+        WAIT ON Dqs;
+        -- Latch data at posedge Dqs
+        IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
+            Dq_temp := Dq;
+            Dm_temp := Dm;
+        END IF;
+        -- Latch data at negedge Dqs
+        IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
+            Dq_pair <= (Dq & Dq_temp);
+            Dm_pair <= (Dm & Dm_temp);
+        END IF;
+    END PROCESS;
+
+    --
+    -- Setup timing checks
+    --
+    Setup_check : PROCESS
+    BEGIN
+        WAIT ON Sys_clk;
+        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
+            ASSERT(Cke'LAST_EVENT >= tIS)
+                REPORT "CKE Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Cs_n'LAST_EVENT >= tIS)
+                REPORT "CS# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT >= tIS)
+                REPORT "CAS# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT >= tIS)
+                REPORT "RAS# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT >= tIS)
+                REPORT "WE# Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Addr'LAST_EVENT >= tIS)
+                REPORT "ADDR Setup time violation -- tIS"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT >= tIS)
+                REPORT "BA Setup time violation -- tIS"
+                SEVERITY WARNING;
+        END IF;   
+    END PROCESS;
+
+    --
+    -- Hold timing checks
+    --
+    Hold_check : PROCESS
+    BEGIN
+        WAIT ON Sys_clk'DELAYED (tIH);
+        IF Sys_clk'DELAYED (tIH) = '1' THEN
+            ASSERT(Cke'LAST_EVENT >= tIH)
+                REPORT "CKE Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Cs_n'LAST_EVENT >= tIH)
+                REPORT "CS# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT >= tIH)
+                REPORT "CAS# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT >= tIH)
+                REPORT "RAS# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT >= tIH)
+                REPORT "WE# Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Addr'LAST_EVENT >= tIH)
+                REPORT "ADDR Hold time violation -- tIH"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT >= tIH)
+                REPORT "BA Hold time violation -- tIH"
+                SEVERITY WARNING;
+        END IF;   
+    END PROCESS;
+
+END behave;
diff --git a/zpu/hdl/zpu4/src/.cvsignore b/zpu/hdl/zpu4/src/.cvsignore
new file mode 100644
index 0000000..41c40a0
--- /dev/null
+++ b/zpu/hdl/zpu4/src/.cvsignore
@@ -0,0 +1,5 @@
+work
+vsim.wlf
+xilinx_device_details.xml
+tcl_stacktrace.txt
+vish_stacktrace.vstf
diff --git a/zpu/hdl/zpu4/src/bram.vhd b/zpu/hdl/zpu4/src/bram.vhd
new file mode 100644
index 0000000..435f3f4
--- /dev/null
+++ b/zpu/hdl/zpu4/src/bram.vhd
@@ -0,0 +1,3807 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+		areset : in std_logic;
+		mem_writeEnable : in std_logic;
+		mem_readEnable : in std_logic;
+		mem_addr : in std_logic_vector(maxAddrBit downto 0);
+		mem_write : in std_logic_vector(wordSize-1 downto 0);
+		mem_read : out std_logic_vector(wordSize-1 downto 0);
+		mem_busy : out std_logic;
+		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"800b0b0b",
+1 => x"0b0b8070",
+2 => x"0b0b80e5",
+3 => x"d00c3a0b",
+4 => x"0b0bbed7",
+5 => x"04000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0bbfa72d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"0b0b0400",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"530b0b51",
+38 => x"04000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"0b0b5104",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"530b0b51",
+55 => x"04000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"0b0b5104",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c6040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a530b0b",
+82 => x"51040000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"0607530b",
+101 => x"0b510400",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"7171530b",
+105 => x"0b510406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"0b0b5104",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"530b0b51",
+125 => x"04000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"520b0b04",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"0505530b",
+138 => x"0b510400",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07530b0b",
+147 => x"51040000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"0b0b0400",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80e5",
+162 => x"bc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88ac0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0ba3",
+171 => x"fa2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0ba4",
+179 => x"ca2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70540b0b",
+188 => x"71067309",
+189 => x"727405ff",
+190 => x"05060751",
+191 => x"51510400",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"0570540b",
+196 => x"0b710673",
+197 => x"09727405",
+198 => x"ff050607",
+199 => x"51515104",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80e5cc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"0b0b0400",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"0b0b0400",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"0571530b",
+250 => x"0b510400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"84803f80",
+257 => x"cef23f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"0b0b5104",
+267 => x"7381ff06",
+268 => x"73830609",
+269 => x"81058305",
+270 => x"1010102b",
+271 => x"0772fc06",
+272 => x"0c515104",
+273 => x"3c047272",
+274 => x"80728106",
+275 => x"ff050972",
+276 => x"06057110",
+277 => x"520b0b72",
+278 => x"0a100a53",
+279 => x"0b0b72e9",
+280 => x"38515153",
+281 => x"0b0b5104",
+282 => x"70700b0b",
+283 => x"80f5c008",
+284 => x"520b0b84",
+285 => x"0b720508",
+286 => x"70810651",
+287 => x"510b0b70",
+288 => x"f2387108",
+289 => x"81ff0680",
+290 => x"0c505004",
+291 => x"70700b0b",
+292 => x"80f5c008",
+293 => x"520b0b84",
+294 => x"0b720508",
+295 => x"700a100a",
+296 => x"70810651",
+297 => x"51510b0b",
+298 => x"70ed3873",
+299 => x"720c5050",
+300 => x"0480e5cc",
+301 => x"08802ea8",
+302 => x"38838080",
+303 => x"0b0b0b80",
+304 => x"f5c00c82",
+305 => x"a0800b0b",
+306 => x"0b80f5c4",
+307 => x"0c829080",
+308 => x"0b80f5d4",
+309 => x"0c0b0b80",
+310 => x"f5c80b80",
+311 => x"f5d80c04",
+312 => x"f8808080",
+313 => x"a40b0b0b",
+314 => x"80f5c00c",
+315 => x"f8808082",
+316 => x"800b0b0b",
+317 => x"80f5c40c",
+318 => x"f8808084",
+319 => x"800b80f5",
+320 => x"d40cf880",
+321 => x"8080940b",
+322 => x"80f5d80c",
+323 => x"f8808080",
+324 => x"9c0b80f5",
+325 => x"d00cf880",
+326 => x"8080a00b",
+327 => x"80f5dc0c",
+328 => x"04f23d0d",
+329 => x"600b0b80",
+330 => x"f5c40856",
+331 => x"5d82750c",
+332 => x"8059805a",
+333 => x"800b8f3d",
+334 => x"71101017",
+335 => x"70085957",
+336 => x"5d5b8076",
+337 => x"81ff067c",
+338 => x"832b5658",
+339 => x"520b0b0b",
+340 => x"76530b0b",
+341 => x"7b5198c6",
+342 => x"3f7d7f7a",
+343 => x"72077c72",
+344 => x"07717160",
+345 => x"8105415f",
+346 => x"5d5b5957",
+347 => x"557a8724",
+348 => x"80c1380b",
+349 => x"0b80f5c4",
+350 => x"087b1010",
+351 => x"71057008",
+352 => x"58515580",
+353 => x"7681ff06",
+354 => x"7c832b56",
+355 => x"58520b0b",
+356 => x"0b76530b",
+357 => x"0b7b5198",
+358 => x"853f7d7f",
+359 => x"7a72077c",
+360 => x"72077171",
+361 => x"60810541",
+362 => x"5f5d5b59",
+363 => x"5755877b",
+364 => x"25c13876",
+365 => x"7d0c7784",
+366 => x"1e0c7c80",
+367 => x"0c903d0d",
+368 => x"04707080",
+369 => x"f5cc3351",
+370 => x"0b0b70b2",
+371 => x"3880e5d8",
+372 => x"08700852",
+373 => x"0b0b520b",
+374 => x"0b0b7080",
+375 => x"2e9a3884",
+376 => x"720580e5",
+377 => x"d80c702d",
+378 => x"80e5d808",
+379 => x"7008520b",
+380 => x"0b520b0b",
+381 => x"0b70e838",
+382 => x"810b80f5",
+383 => x"cc345050",
+384 => x"0404700b",
+385 => x"0b80f5bc",
+386 => x"08802e8e",
+387 => x"380b0b0b",
+388 => x"0b800b80",
+389 => x"2e098106",
+390 => x"83385004",
+391 => x"0b0b80f5",
+392 => x"bc510b0b",
+393 => x"0bf3d93f",
+394 => x"50040470",
+395 => x"70028f05",
+396 => x"33520b0b",
+397 => x"0b0b718a",
+398 => x"2e893871",
+399 => x"51fccd3f",
+400 => x"5050048d",
+401 => x"51fcc53f",
+402 => x"7151fcc0",
+403 => x"3f505004",
+404 => x"cd3d0db6",
+405 => x"3d707084",
+406 => x"05520b0b",
+407 => x"088cab5d",
+408 => x"56a63d5f",
+409 => x"5d807570",
+410 => x"81055733",
+411 => x"765c5559",
+412 => x"0b730b79",
+413 => x"2e80ca38",
+414 => x"8f3d5c73",
+415 => x"a52e0981",
+416 => x"0680cf38",
+417 => x"79708105",
+418 => x"5b33540b",
+419 => x"0b7380e4",
+420 => x"2e81c838",
+421 => x"7380e424",
+422 => x"80d13873",
+423 => x"80e32ea8",
+424 => x"3880520b",
+425 => x"0ba5517a",
+426 => x"2d80520b",
+427 => x"0b73517a",
+428 => x"2d821959",
+429 => x"79708105",
+430 => x"5b33540b",
+431 => x"0b73ffbb",
+432 => x"3878800c",
+433 => x"b53d0d04",
+434 => x"7c841e83",
+435 => x"72053356",
+436 => x"5e578052",
+437 => x"0b0b7351",
+438 => x"7a2d8119",
+439 => x"7a708105",
+440 => x"5c335559",
+441 => x"0b73ff93",
+442 => x"38d73973",
+443 => x"80f32e09",
+444 => x"8106ffad",
+445 => x"387c841e",
+446 => x"7108595e",
+447 => x"56807733",
+448 => x"56560b74",
+449 => x"0b762e8d",
+450 => x"38811670",
+451 => x"1870335a",
+452 => x"555677f5",
+453 => x"38ff1655",
+454 => x"807625ff",
+455 => x"97387670",
+456 => x"81055833",
+457 => x"5880520b",
+458 => x"0b77517a",
+459 => x"2d811975",
+460 => x"ff175757",
+461 => x"59807625",
+462 => x"fefa3876",
+463 => x"70810558",
+464 => x"33588052",
+465 => x"0b0b7751",
+466 => x"7a2d8119",
+467 => x"75ff1757",
+468 => x"57590b75",
+469 => x"8024c738",
+470 => x"feda397c",
+471 => x"841e7108",
+472 => x"70719f2c",
+473 => x"59530b0b",
+474 => x"595e5680",
+475 => x"7524818d",
+476 => x"38757e7d",
+477 => x"58595580",
+478 => x"57740b77",
+479 => x"2e098106",
+480 => x"bc38b07c",
+481 => x"3402b905",
+482 => x"567b0b76",
+483 => x"2e9938ff",
+484 => x"16560b0b",
+485 => x"75337870",
+486 => x"81055a34",
+487 => x"8117577b",
+488 => x"762e0981",
+489 => x"06e93880",
+490 => x"7834767e",
+491 => x"ff720557",
+492 => x"58560b0b",
+493 => x"758024fe",
+494 => x"e538fdf8",
+495 => x"398a7536",
+496 => x"0b0b80d7",
+497 => x"b005540b",
+498 => x"0b733376",
+499 => x"70810558",
+500 => x"348a7535",
+501 => x"550b0b74",
+502 => x"802effad",
+503 => x"388a7536",
+504 => x"0b0b80d7",
+505 => x"b005540b",
+506 => x"0b733376",
+507 => x"70810558",
+508 => x"348a7535",
+509 => x"550b0b74",
+510 => x"c438ff8d",
+511 => x"3974520b",
+512 => x"0b76530b",
+513 => x"0bb53dff",
+514 => x"b8055192",
+515 => x"dc3fa43d",
+516 => x"0856fedd",
+517 => x"397080c1",
+518 => x"0b81c48c",
+519 => x"34800b81",
+520 => x"c5e40c70",
+521 => x"800c5004",
+522 => x"7070800b",
+523 => x"81c48c33",
+524 => x"520b0b52",
+525 => x"0b0b0b70",
+526 => x"80c12e98",
+527 => x"387181c5",
+528 => x"e4080781",
+529 => x"c5e40c80",
+530 => x"c20b81c4",
+531 => x"90347080",
+532 => x"0c505004",
+533 => x"810b81c5",
+534 => x"e4080781",
+535 => x"c5e40c80",
+536 => x"c20b81c4",
+537 => x"90347080",
+538 => x"0c505004",
+539 => x"70707070",
+540 => x"7570088a",
+541 => x"05530b0b",
+542 => x"530b0b81",
+543 => x"c48c3351",
+544 => x"0b0b7080",
+545 => x"c12e8c38",
+546 => x"73f13870",
+547 => x"800c5050",
+548 => x"505004ff",
+549 => x"72057081",
+550 => x"c4880831",
+551 => x"740c800c",
+552 => x"50505050",
+553 => x"04fc3d0d",
+554 => x"81c49408",
+555 => x"550b0b74",
+556 => x"802e8e38",
+557 => x"76750871",
+558 => x"0c81c494",
+559 => x"0856540b",
+560 => x"0b8c1553",
+561 => x"0b0b81c4",
+562 => x"8808520b",
+563 => x"0b8a518e",
+564 => x"e93f7380",
+565 => x"0c863d0d",
+566 => x"04fb3d0d",
+567 => x"77700856",
+568 => x"56b0530b",
+569 => x"0b81c494",
+570 => x"08520b0b",
+571 => x"7451a1ff",
+572 => x"3f850b8c",
+573 => x"170c850b",
+574 => x"8c160c75",
+575 => x"08750c81",
+576 => x"c4940854",
+577 => x"0b0b7380",
+578 => x"2e8c3873",
+579 => x"08750c81",
+580 => x"c4940854",
+581 => x"0b0b8c14",
+582 => x"530b0b81",
+583 => x"c4880852",
+584 => x"0b0b8a51",
+585 => x"8e943f84",
+586 => x"1508b738",
+587 => x"860b8c16",
+588 => x"0c881552",
+589 => x"0b0b8816",
+590 => x"08518d96",
+591 => x"3f81c494",
+592 => x"08700876",
+593 => x"0c540b0b",
+594 => x"8c157054",
+595 => x"0b0b540b",
+596 => x"0b8a520b",
+597 => x"0b730851",
+598 => x"8de03f73",
+599 => x"800c873d",
+600 => x"0d047508",
+601 => x"540b0bb0",
+602 => x"530b0b73",
+603 => x"520b0b75",
+604 => x"51a0fc3f",
+605 => x"73800c87",
+606 => x"3d0d04e1",
+607 => x"3d0db051",
+608 => x"93833f80",
+609 => x"0881c484",
+610 => x"0cb05192",
+611 => x"f83f8008",
+612 => x"81c4940c",
+613 => x"81c48408",
+614 => x"80080c80",
+615 => x"0b800884",
+616 => x"050c820b",
+617 => x"80088805",
+618 => x"0ca80b80",
+619 => x"088c050c",
+620 => x"9f530b0b",
+621 => x"0b0b80d7",
+622 => x"bc520b0b",
+623 => x"80089005",
+624 => x"51a0ac3f",
+625 => x"993d5c9f",
+626 => x"530b0b0b",
+627 => x"0b80d7dc",
+628 => x"520b0b7b",
+629 => x"51a0983f",
+630 => x"8a0b8182",
+631 => x"cc0c0b0b",
+632 => x"80e28051",
+633 => x"f8ea3f0b",
+634 => x"0b80d7fc",
+635 => x"51f8e13f",
+636 => x"0b0b80e2",
+637 => x"8051f8d8",
+638 => x"3f80e5e0",
+639 => x"08802e8a",
+640 => x"a1380b0b",
+641 => x"80d8ac51",
+642 => x"f8c63f0b",
+643 => x"0b80e280",
+644 => x"51f8bd3f",
+645 => x"80e5dc08",
+646 => x"520b0b0b",
+647 => x"0b80d8d8",
+648 => x"51f8ad3f",
+649 => x"8051b488",
+650 => x"3f800880",
+651 => x"f5ec0c81",
+652 => x"0b923d5c",
+653 => x"58800b80",
+654 => x"e5dc0825",
+655 => x"8383388e",
+656 => x"3d5d80c1",
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+3092 => x"4e452050",
+3093 => x"524f4752",
+3094 => x"414d2c20",
+3095 => x"32274e44",
+3096 => x"20535452",
+3097 => x"494e470a",
+3098 => x"00000000",
+3099 => x"55736572",
+3100 => x"2074696d",
+3101 => x"653a2025",
+3102 => x"640a0000",
+3103 => x"4d696372",
+3104 => x"6f736563",
+3105 => x"6f6e6473",
+3106 => x"20666f72",
+3107 => x"206f6e65",
+3108 => x"2072756e",
+3109 => x"20746872",
+3110 => x"6f756768",
+3111 => x"20446872",
+3112 => x"7973746f",
+3113 => x"6e653a20",
+3114 => x"00000000",
+3115 => x"2564200a",
+3116 => x"00000000",
+3117 => x"44687279",
+3118 => x"73746f6e",
+3119 => x"65732070",
+3120 => x"65722053",
+3121 => x"65636f6e",
+3122 => x"643a2020",
+3123 => x"20202020",
+3124 => x"20202020",
+3125 => x"20202020",
+3126 => x"20202020",
+3127 => x"20202020",
+3128 => x"00000000",
+3129 => x"56415820",
+3130 => x"4d495053",
+3131 => x"20726174",
+3132 => x"696e6720",
+3133 => x"2a203130",
+3134 => x"3030203d",
+3135 => x"20256420",
+3136 => x"0a000000",
+3137 => x"50726f67",
+3138 => x"72616d20",
+3139 => x"636f6d70",
+3140 => x"696c6564",
+3141 => x"20776974",
+3142 => x"686f7574",
+3143 => x"20277265",
+3144 => x"67697374",
+3145 => x"65722720",
+3146 => x"61747472",
+3147 => x"69627574",
+3148 => x"650a0000",
+3149 => x"4d656173",
+3150 => x"75726564",
+3151 => x"2074696d",
+3152 => x"6520746f",
+3153 => x"6f20736d",
+3154 => x"616c6c20",
+3155 => x"746f206f",
+3156 => x"62746169",
+3157 => x"6e206d65",
+3158 => x"616e696e",
+3159 => x"6766756c",
+3160 => x"20726573",
+3161 => x"756c7473",
+3162 => x"0a000000",
+3163 => x"506c6561",
+3164 => x"73652069",
+3165 => x"6e637265",
+3166 => x"61736520",
+3167 => x"6e756d62",
+3168 => x"6572206f",
+3169 => x"66207275",
+3170 => x"6e730a00",
+3171 => x"44485259",
+3172 => x"53544f4e",
+3173 => x"45205052",
+3174 => x"4f475241",
+3175 => x"4d2c2033",
+3176 => x"27524420",
+3177 => x"53545249",
+3178 => x"4e470000",
+3179 => x"43000000",
+3180 => x"64756d6d",
+3181 => x"792e6578",
+3182 => x"65000000",
+3183 => x"00010202",
+3184 => x"03030303",
+3185 => x"04040404",
+3186 => x"04040404",
+3187 => x"05050505",
+3188 => x"05050505",
+3189 => x"05050505",
+3190 => x"05050505",
+3191 => x"06060606",
+3192 => x"06060606",
+3193 => x"06060606",
+3194 => x"06060606",
+3195 => x"06060606",
+3196 => x"06060606",
+3197 => x"06060606",
+3198 => x"06060606",
+3199 => x"07070707",
+3200 => x"07070707",
+3201 => x"07070707",
+3202 => x"07070707",
+3203 => x"07070707",
+3204 => x"07070707",
+3205 => x"07070707",
+3206 => x"07070707",
+3207 => x"07070707",
+3208 => x"07070707",
+3209 => x"07070707",
+3210 => x"07070707",
+3211 => x"07070707",
+3212 => x"07070707",
+3213 => x"07070707",
+3214 => x"07070707",
+3215 => x"08080808",
+3216 => x"08080808",
+3217 => x"08080808",
+3218 => x"08080808",
+3219 => x"08080808",
+3220 => x"08080808",
+3221 => x"08080808",
+3222 => x"08080808",
+3223 => x"08080808",
+3224 => x"08080808",
+3225 => x"08080808",
+3226 => x"08080808",
+3227 => x"08080808",
+3228 => x"08080808",
+3229 => x"08080808",
+3230 => x"08080808",
+3231 => x"08080808",
+3232 => x"08080808",
+3233 => x"08080808",
+3234 => x"08080808",
+3235 => x"08080808",
+3236 => x"08080808",
+3237 => x"08080808",
+3238 => x"08080808",
+3239 => x"08080808",
+3240 => x"08080808",
+3241 => x"08080808",
+3242 => x"08080808",
+3243 => x"08080808",
+3244 => x"08080808",
+3245 => x"08080808",
+3246 => x"08080808",
+3247 => x"00ffffff",
+3248 => x"ff00ffff",
+3249 => x"ffff00ff",
+3250 => x"ffffff00",
+3251 => x"00000000",
+3252 => x"00000000",
+3253 => x"00000000",
+3254 => x"00003ab8",
+3255 => x"000186a0", -- iterations
+3256 => x"00000000",
+3257 => x"00000000",
+3258 => x"00000000",
+3259 => x"00000000",
+3260 => x"00000000",
+3261 => x"00000000",
+3262 => x"00000000",
+3263 => x"00000000",
+3264 => x"00000000",
+3265 => x"00000000",
+3266 => x"00000000",
+3267 => x"00000000",
+3268 => x"00000000",
+3269 => x"ffffffff",
+3270 => x"00000000",
+3271 => x"00020000",
+3272 => x"00000000",
+3273 => x"00000000",
+3274 => x"00003320",
+3275 => x"00003320",
+3276 => x"00003328",
+3277 => x"00003328",
+3278 => x"00003330",
+3279 => x"00003330",
+3280 => x"00003338",
+3281 => x"00003338",
+3282 => x"00003340",
+3283 => x"00003340",
+3284 => x"00003348",
+3285 => x"00003348",
+3286 => x"00003350",
+3287 => x"00003350",
+3288 => x"00003358",
+3289 => x"00003358",
+3290 => x"00003360",
+3291 => x"00003360",
+3292 => x"00003368",
+3293 => x"00003368",
+3294 => x"00003370",
+3295 => x"00003370",
+3296 => x"00003378",
+3297 => x"00003378",
+3298 => x"00003380",
+3299 => x"00003380",
+3300 => x"00003388",
+3301 => x"00003388",
+3302 => x"00003390",
+3303 => x"00003390",
+3304 => x"00003398",
+3305 => x"00003398",
+3306 => x"000033a0",
+3307 => x"000033a0",
+3308 => x"000033a8",
+3309 => x"000033a8",
+3310 => x"000033b0",
+3311 => x"000033b0",
+3312 => x"000033b8",
+3313 => x"000033b8",
+3314 => x"000033c0",
+3315 => x"000033c0",
+3316 => x"000033c8",
+3317 => x"000033c8",
+3318 => x"000033d0",
+3319 => x"000033d0",
+3320 => x"000033d8",
+3321 => x"000033d8",
+3322 => x"000033e0",
+3323 => x"000033e0",
+3324 => x"000033e8",
+3325 => x"000033e8",
+3326 => x"000033f0",
+3327 => x"000033f0",
+3328 => x"000033f8",
+3329 => x"000033f8",
+3330 => x"00003400",
+3331 => x"00003400",
+3332 => x"00003408",
+3333 => x"00003408",
+3334 => x"00003410",
+3335 => x"00003410",
+3336 => x"00003418",
+3337 => x"00003418",
+3338 => x"00003420",
+3339 => x"00003420",
+3340 => x"00003428",
+3341 => x"00003428",
+3342 => x"00003430",
+3343 => x"00003430",
+3344 => x"00003438",
+3345 => x"00003438",
+3346 => x"00003440",
+3347 => x"00003440",
+3348 => x"00003448",
+3349 => x"00003448",
+3350 => x"00003450",
+3351 => x"00003450",
+3352 => x"00003458",
+3353 => x"00003458",
+3354 => x"00003460",
+3355 => x"00003460",
+3356 => x"00003468",
+3357 => x"00003468",
+3358 => x"00003470",
+3359 => x"00003470",
+3360 => x"00003478",
+3361 => x"00003478",
+3362 => x"00003480",
+3363 => x"00003480",
+3364 => x"00003488",
+3365 => x"00003488",
+3366 => x"00003490",
+3367 => x"00003490",
+3368 => x"00003498",
+3369 => x"00003498",
+3370 => x"000034a0",
+3371 => x"000034a0",
+3372 => x"000034a8",
+3373 => x"000034a8",
+3374 => x"000034b0",
+3375 => x"000034b0",
+3376 => x"000034b8",
+3377 => x"000034b8",
+3378 => x"000034c0",
+3379 => x"000034c0",
+3380 => x"000034c8",
+3381 => x"000034c8",
+3382 => x"000034d0",
+3383 => x"000034d0",
+3384 => x"000034d8",
+3385 => x"000034d8",
+3386 => x"000034e0",
+3387 => x"000034e0",
+3388 => x"000034e8",
+3389 => x"000034e8",
+3390 => x"000034f0",
+3391 => x"000034f0",
+3392 => x"000034f8",
+3393 => x"000034f8",
+3394 => x"00003500",
+3395 => x"00003500",
+3396 => x"00003508",
+3397 => x"00003508",
+3398 => x"00003510",
+3399 => x"00003510",
+3400 => x"00003518",
+3401 => x"00003518",
+3402 => x"00003520",
+3403 => x"00003520",
+3404 => x"00003528",
+3405 => x"00003528",
+3406 => x"00003530",
+3407 => x"00003530",
+3408 => x"00003538",
+3409 => x"00003538",
+3410 => x"00003540",
+3411 => x"00003540",
+3412 => x"00003548",
+3413 => x"00003548",
+3414 => x"00003550",
+3415 => x"00003550",
+3416 => x"00003558",
+3417 => x"00003558",
+3418 => x"00003560",
+3419 => x"00003560",
+3420 => x"00003568",
+3421 => x"00003568",
+3422 => x"00003570",
+3423 => x"00003570",
+3424 => x"00003578",
+3425 => x"00003578",
+3426 => x"00003580",
+3427 => x"00003580",
+3428 => x"00003588",
+3429 => x"00003588",
+3430 => x"00003590",
+3431 => x"00003590",
+3432 => x"00003598",
+3433 => x"00003598",
+3434 => x"000035a0",
+3435 => x"000035a0",
+3436 => x"000035a8",
+3437 => x"000035a8",
+3438 => x"000035b0",
+3439 => x"000035b0",
+3440 => x"000035b8",
+3441 => x"000035b8",
+3442 => x"000035c0",
+3443 => x"000035c0",
+3444 => x"000035c8",
+3445 => x"000035c8",
+3446 => x"000035d0",
+3447 => x"000035d0",
+3448 => x"000035d8",
+3449 => x"000035d8",
+3450 => x"000035e0",
+3451 => x"000035e0",
+3452 => x"000035e8",
+3453 => x"000035e8",
+3454 => x"000035f0",
+3455 => x"000035f0",
+3456 => x"000035f8",
+3457 => x"000035f8",
+3458 => x"00003600",
+3459 => x"00003600",
+3460 => x"00003608",
+3461 => x"00003608",
+3462 => x"00003610",
+3463 => x"00003610",
+3464 => x"00003618",
+3465 => x"00003618",
+3466 => x"00003620",
+3467 => x"00003620",
+3468 => x"00003628",
+3469 => x"00003628",
+3470 => x"00003630",
+3471 => x"00003630",
+3472 => x"00003638",
+3473 => x"00003638",
+3474 => x"00003640",
+3475 => x"00003640",
+3476 => x"00003648",
+3477 => x"00003648",
+3478 => x"00003650",
+3479 => x"00003650",
+3480 => x"00003658",
+3481 => x"00003658",
+3482 => x"00003660",
+3483 => x"00003660",
+3484 => x"00003668",
+3485 => x"00003668",
+3486 => x"00003670",
+3487 => x"00003670",
+3488 => x"00003678",
+3489 => x"00003678",
+3490 => x"00003680",
+3491 => x"00003680",
+3492 => x"00003688",
+3493 => x"00003688",
+3494 => x"00003690",
+3495 => x"00003690",
+3496 => x"00003698",
+3497 => x"00003698",
+3498 => x"000036a0",
+3499 => x"000036a0",
+3500 => x"000036a8",
+3501 => x"000036a8",
+3502 => x"000036b0",
+3503 => x"000036b0",
+3504 => x"000036b8",
+3505 => x"000036b8",
+3506 => x"000036c0",
+3507 => x"000036c0",
+3508 => x"000036c8",
+3509 => x"000036c8",
+3510 => x"000036d0",
+3511 => x"000036d0",
+3512 => x"000036d8",
+3513 => x"000036d8",
+3514 => x"000036e0",
+3515 => x"000036e0",
+3516 => x"000036e8",
+3517 => x"000036e8",
+3518 => x"000036f0",
+3519 => x"000036f0",
+3520 => x"000036f8",
+3521 => x"000036f8",
+3522 => x"00003700",
+3523 => x"00003700",
+3524 => x"00003708",
+3525 => x"00003708",
+3526 => x"00003710",
+3527 => x"00003710",
+3528 => x"00003718",
+3529 => x"00003718",
+3530 => x"0000372c",
+3531 => x"00000000",
+3532 => x"00003994",
+3533 => x"000039f0",
+3534 => x"00003a4c",
+3535 => x"00000000",
+3536 => x"00000000",
+3537 => x"00000000",
+3538 => x"00000000",
+3539 => x"00000000",
+3540 => x"00000000",
+3541 => x"00000000",
+3542 => x"00000000",
+3543 => x"00000000",
+3544 => x"000031ac",
+3545 => x"00000000",
+3546 => x"00000000",
+3547 => x"00000000",
+3548 => x"00000000",
+3549 => x"00000000",
+3550 => x"00000000",
+3551 => x"00000000",
+3552 => x"00000000",
+3553 => x"00000000",
+3554 => x"00000000",
+3555 => x"00000000",
+3556 => x"00000000",
+3557 => x"00000000",
+3558 => x"00000000",
+3559 => x"00000000",
+3560 => x"00000000",
+3561 => x"00000000",
+3562 => x"00000000",
+3563 => x"00000000",
+3564 => x"00000000",
+3565 => x"00000000",
+3566 => x"00000000",
+3567 => x"00000000",
+3568 => x"00000000",
+3569 => x"00000000",
+3570 => x"00000000",
+3571 => x"00000000",
+3572 => x"00000000",
+3573 => x"00000001",
+3574 => x"330eabcd",
+3575 => x"1234e66d",
+3576 => x"deec0005",
+3577 => x"000b0000",
+3578 => x"00000000",
+3579 => x"00000000",
+3580 => x"00000000",
+3581 => x"00000000",
+3582 => x"00000000",
+3583 => x"00000000",
+3584 => x"00000000",
+3585 => x"00000000",
+3586 => x"00000000",
+3587 => x"00000000",
+3588 => x"00000000",
+3589 => x"00000000",
+3590 => x"00000000",
+3591 => x"00000000",
+3592 => x"00000000",
+3593 => x"00000000",
+3594 => x"00000000",
+3595 => x"00000000",
+3596 => x"00000000",
+3597 => x"00000000",
+3598 => x"00000000",
+3599 => x"00000000",
+3600 => x"00000000",
+3601 => x"00000000",
+3602 => x"00000000",
+3603 => x"00000000",
+3604 => x"00000000",
+3605 => x"00000000",
+3606 => x"00000000",
+3607 => x"00000000",
+3608 => x"00000000",
+3609 => x"00000000",
+3610 => x"00000000",
+3611 => x"00000000",
+3612 => x"00000000",
+3613 => x"00000000",
+3614 => x"00000000",
+3615 => x"00000000",
+3616 => x"00000000",
+3617 => x"00000000",
+3618 => x"00000000",
+3619 => x"00000000",
+3620 => x"00000000",
+3621 => x"00000000",
+3622 => x"00000000",
+3623 => x"00000000",
+3624 => x"00000000",
+3625 => x"00000000",
+3626 => x"00000000",
+3627 => x"00000000",
+3628 => x"00000000",
+3629 => x"00000000",
+3630 => x"00000000",
+3631 => x"00000000",
+3632 => x"00000000",
+3633 => x"00000000",
+3634 => x"00000000",
+3635 => x"00000000",
+3636 => x"00000000",
+3637 => x"00000000",
+3638 => x"00000000",
+3639 => x"00000000",
+3640 => x"00000000",
+3641 => x"00000000",
+3642 => x"00000000",
+3643 => x"00000000",
+3644 => x"00000000",
+3645 => x"00000000",
+3646 => x"00000000",
+3647 => x"00000000",
+3648 => x"00000000",
+3649 => x"00000000",
+3650 => x"00000000",
+3651 => x"00000000",
+3652 => x"00000000",
+3653 => x"00000000",
+3654 => x"00000000",
+3655 => x"00000000",
+3656 => x"00000000",
+3657 => x"00000000",
+3658 => x"00000000",
+3659 => x"00000000",
+3660 => x"00000000",
+3661 => x"00000000",
+3662 => x"00000000",
+3663 => x"00000000",
+3664 => x"00000000",
+3665 => x"00000000",
+3666 => x"00000000",
+3667 => x"00000000",
+3668 => x"00000000",
+3669 => x"00000000",
+3670 => x"00000000",
+3671 => x"00000000",
+3672 => x"00000000",
+3673 => x"00000000",
+3674 => x"00000000",
+3675 => x"00000000",
+3676 => x"00000000",
+3677 => x"00000000",
+3678 => x"00000000",
+3679 => x"00000000",
+3680 => x"00000000",
+3681 => x"00000000",
+3682 => x"00000000",
+3683 => x"00000000",
+3684 => x"00000000",
+3685 => x"00000000",
+3686 => x"00000000",
+3687 => x"00000000",
+3688 => x"00000000",
+3689 => x"00000000",
+3690 => x"00000000",
+3691 => x"00000000",
+3692 => x"00000000",
+3693 => x"00000000",
+3694 => x"00000000",
+3695 => x"00000000",
+3696 => x"00000000",
+3697 => x"00000000",
+3698 => x"00000000",
+3699 => x"00000000",
+3700 => x"00000000",
+3701 => x"00000000",
+3702 => x"00000000",
+3703 => x"00000000",
+3704 => x"00000000",
+3705 => x"00000000",
+3706 => x"00000000",
+3707 => x"00000000",
+3708 => x"00000000",
+3709 => x"00000000",
+3710 => x"00000000",
+3711 => x"00000000",
+3712 => x"00000000",
+3713 => x"00000000",
+3714 => x"00000000",
+3715 => x"00000000",
+3716 => x"00000000",
+3717 => x"00000000",
+3718 => x"00000000",
+3719 => x"00000000",
+3720 => x"00000000",
+3721 => x"00000000",
+3722 => x"00000000",
+3723 => x"00000000",
+3724 => x"00000000",
+3725 => x"00000000",
+3726 => x"00000000",
+3727 => x"00000000",
+3728 => x"00000000",
+3729 => x"00000000",
+3730 => x"00000000",
+3731 => x"00000000",
+3732 => x"00000000",
+3733 => x"00000000",
+3734 => x"00000000",
+3735 => x"00000000",
+3736 => x"00000000",
+3737 => x"00000000",
+3738 => x"00000000",
+3739 => x"00000000",
+3740 => x"00000000",
+3741 => x"00000000",
+3742 => x"00000000",
+3743 => x"00000000",
+3744 => x"00000000",
+3745 => x"00000000",
+3746 => x"00000000",
+3747 => x"00000000",
+3748 => x"00000000",
+3749 => x"00000000",
+3750 => x"00000000",
+3751 => x"00000000",
+3752 => x"00000000",
+3753 => x"00000000",
+3754 => x"000031b0",
+3755 => x"ffffffff",
+3756 => x"00000000",
+3757 => x"ffffffff",
+3758 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+mem_busy <= '0';
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (mem_writeEnable = '1') then
+			ram(conv_integer(mem_addr)) := mem_write;
+		end if;
+		mem_read <= ram(conv_integer(mem_addr));
+	end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/zpu4/src/bram_dmips.vhd b/zpu/hdl/zpu4/src/bram_dmips.vhd
new file mode 100644
index 0000000..1c85e0d
--- /dev/null
+++ b/zpu/hdl/zpu4/src/bram_dmips.vhd
@@ -0,0 +1,3717 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dualport_ram is
+port (clk : in std_logic;
+	memAWriteEnable : in std_logic;
+	memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memAWrite : in std_logic_vector(wordSize-1 downto 0);
+	memARead : out std_logic_vector(wordSize-1 downto 0);
+	memBWriteEnable : in std_logic;
+	memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
+	memBWrite : in std_logic_vector(wordSize-1 downto 0);
+	memBRead : out std_logic_vector(wordSize-1 downto 0));
+end dualport_ram;
+
+architecture dualport_ram_arch of dualport_ram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"80700b0b",
+2 => x"80e2a40c",
+3 => x"3a0b0b80",
+4 => x"c6fc0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7c32d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80e2",
+162 => x"90738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0baf",
+171 => x"ac2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0baf",
+179 => x"f02d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80e2a00c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"83d93f80",
+257 => x"cbcf3f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"ff3d0d0b",
+281 => x"0b80f294",
+282 => x"08528412",
+283 => x"08708106",
+284 => x"515170f6",
+285 => x"38710881",
+286 => x"ff06800c",
+287 => x"833d0d04",
+288 => x"ff3d0d0b",
+289 => x"0b80f294",
+290 => x"08528412",
+291 => x"08700a10",
+292 => x"0a708106",
+293 => x"51515170",
+294 => x"f1387372",
+295 => x"0c833d0d",
+296 => x"0480e2a0",
+297 => x"08802ea8",
+298 => x"38838080",
+299 => x"0b0b0b80",
+300 => x"f2940c82",
+301 => x"a0800b0b",
+302 => x"0b80f298",
+303 => x"0c829080",
+304 => x"0b80f2a8",
+305 => x"0c0b0b80",
+306 => x"f29c0b80",
+307 => x"f2ac0c04",
+308 => x"f8808080",
+309 => x"a40b0b0b",
+310 => x"80f2940c",
+311 => x"f8808082",
+312 => x"800b0b0b",
+313 => x"80f2980c",
+314 => x"f8808084",
+315 => x"800b80f2",
+316 => x"a80cf880",
+317 => x"8080940b",
+318 => x"80f2ac0c",
+319 => x"f8808080",
+320 => x"9c0b80f2",
+321 => x"a40cf880",
+322 => x"8080a00b",
+323 => x"80f2b00c",
+324 => x"04f23d0d",
+325 => x"600b0b80",
+326 => x"f2980856",
+327 => x"5d82750c",
+328 => x"8059805a",
+329 => x"800b8f3d",
+330 => x"71101017",
+331 => x"70085957",
+332 => x"5d5b8076",
+333 => x"81ff067c",
+334 => x"832b5658",
+335 => x"5276537b",
+336 => x"519af33f",
+337 => x"7d7f7a72",
+338 => x"077c7207",
+339 => x"71716081",
+340 => x"05415f5d",
+341 => x"5b595755",
+342 => x"7a8724bb",
+343 => x"380b0b80",
+344 => x"f298087b",
+345 => x"10101170",
+346 => x"08585155",
+347 => x"807681ff",
+348 => x"067c832b",
+349 => x"56585276",
+350 => x"537b519a",
+351 => x"b93f7d7f",
+352 => x"7a72077c",
+353 => x"72077171",
+354 => x"60810541",
+355 => x"5f5d5b59",
+356 => x"5755877b",
+357 => x"25c73876",
+358 => x"7d0c7784",
+359 => x"1e0c7c80",
+360 => x"0c903d0d",
+361 => x"04ff3d0d",
+362 => x"80f2a033",
+363 => x"5170a738",
+364 => x"80e2ac08",
+365 => x"70085252",
+366 => x"70802e94",
+367 => x"38841280",
+368 => x"e2ac0c70",
+369 => x"2d80e2ac",
+370 => x"08700852",
+371 => x"5270ee38",
+372 => x"810b80f2",
+373 => x"a034833d",
+374 => x"0d040480",
+375 => x"3d0d0b0b",
+376 => x"80f29008",
+377 => x"802e8e38",
+378 => x"0b0b0b0b",
+379 => x"800b802e",
+380 => x"09810685",
+381 => x"38823d0d",
+382 => x"040b0b80",
+383 => x"f290510b",
+384 => x"0b0bf3fc",
+385 => x"3f823d0d",
+386 => x"0404ff3d",
+387 => x"0d028f05",
+388 => x"3352718a",
+389 => x"2e8a3871",
+390 => x"51fce53f",
+391 => x"833d0d04",
+392 => x"8d51fcdc",
+393 => x"3f7151fc",
+394 => x"d73f833d",
+395 => x"0d04ce3d",
+396 => x"0db53d70",
+397 => x"70840552",
+398 => x"088c8a5c",
+399 => x"56a53d5e",
+400 => x"5c807570",
+401 => x"81055733",
+402 => x"765b5558",
+403 => x"73782e80",
+404 => x"c1388e3d",
+405 => x"5b73a52e",
+406 => x"09810680",
+407 => x"c5387870",
+408 => x"81055a33",
+409 => x"547380e4",
+410 => x"2e81b638",
+411 => x"7380e424",
+412 => x"80c63873",
+413 => x"80e32ea1",
+414 => x"388052a5",
+415 => x"51792d80",
+416 => x"52735179",
+417 => x"2d821858",
+418 => x"78708105",
+419 => x"5a335473",
+420 => x"c4387780",
+421 => x"0cb43d0d",
+422 => x"047b841d",
+423 => x"83123356",
+424 => x"5d578052",
+425 => x"7351792d",
+426 => x"81187970",
+427 => x"81055b33",
+428 => x"555873ff",
+429 => x"a038db39",
+430 => x"7380f32e",
+431 => x"098106ff",
+432 => x"b8387b84",
+433 => x"1d710859",
+434 => x"5d568077",
+435 => x"33555673",
+436 => x"762e8d38",
+437 => x"81167018",
+438 => x"70335755",
+439 => x"5674f538",
+440 => x"ff165580",
+441 => x"7625ffa0",
+442 => x"38767081",
+443 => x"05583354",
+444 => x"80527351",
+445 => x"792d8118",
+446 => x"75ff1757",
+447 => x"57588076",
+448 => x"25ff8538",
+449 => x"76708105",
+450 => x"58335480",
+451 => x"52735179",
+452 => x"2d811875",
+453 => x"ff175757",
+454 => x"58758024",
+455 => x"cc38fee8",
+456 => x"397b841d",
+457 => x"71087071",
+458 => x"9f2c5953",
+459 => x"595d5680",
+460 => x"75248195",
+461 => x"38757d7c",
+462 => x"58565480",
+463 => x"5773772e",
+464 => x"098106b6",
+465 => x"38b07b34",
+466 => x"02b50556",
+467 => x"7a762e97",
+468 => x"38ff1656",
+469 => x"75337570",
+470 => x"81055734",
+471 => x"8117577a",
+472 => x"762e0981",
+473 => x"06eb3880",
+474 => x"7534767d",
+475 => x"ff125758",
+476 => x"56758024",
+477 => x"fef338fe",
+478 => x"8f398a52",
+479 => x"7351a0f0",
+480 => x"3f80080b",
+481 => x"0b80d484",
+482 => x"05337670",
+483 => x"81055834",
+484 => x"8a527351",
+485 => x"a0963f80",
+486 => x"08548008",
+487 => x"802effac",
+488 => x"388a5273",
+489 => x"51a0c93f",
+490 => x"80080b0b",
+491 => x"80d48405",
+492 => x"33767081",
+493 => x"0558348a",
+494 => x"5273519f",
+495 => x"ef3f8008",
+496 => x"548008ff",
+497 => x"b538ff84",
+498 => x"39745276",
+499 => x"53b43dff",
+500 => x"b8055195",
+501 => x"b63fa33d",
+502 => x"0856fed9",
+503 => x"39803d0d",
+504 => x"80c10b81",
+505 => x"c0f43480",
+506 => x"0b81c2d0",
+507 => x"0c70800c",
+508 => x"823d0d04",
+509 => x"ff3d0d80",
+510 => x"0b81c0f4",
+511 => x"33525270",
+512 => x"80c12e99",
+513 => x"387181c2",
+514 => x"d0080781",
+515 => x"c2d00c80",
+516 => x"c20b81c0",
+517 => x"f8347080",
+518 => x"0c833d0d",
+519 => x"04810b81",
+520 => x"c2d00807",
+521 => x"81c2d00c",
+522 => x"80c20b81",
+523 => x"c0f83470",
+524 => x"800c833d",
+525 => x"0d04fd3d",
+526 => x"0d757008",
+527 => x"8a055353",
+528 => x"81c0f433",
+529 => x"517080c1",
+530 => x"2e8b3873",
+531 => x"f3387080",
+532 => x"0c853d0d",
+533 => x"04ff1270",
+534 => x"81c0f008",
+535 => x"31740c80",
+536 => x"0c853d0d",
+537 => x"04fc3d0d",
+538 => x"81c0fc08",
+539 => x"5574802e",
+540 => x"8c387675",
+541 => x"08710c81",
+542 => x"c0fc0856",
+543 => x"548c1553",
+544 => x"81c0f008",
+545 => x"528a5190",
+546 => x"f03f7380",
+547 => x"0c863d0d",
+548 => x"04fb3d0d",
+549 => x"77700856",
+550 => x"56b05381",
+551 => x"c0fc0852",
+552 => x"7451acb4",
+553 => x"3f850b8c",
+554 => x"170c850b",
+555 => x"8c160c75",
+556 => x"08750c81",
+557 => x"c0fc0854",
+558 => x"73802e8a",
+559 => x"38730875",
+560 => x"0c81c0fc",
+561 => x"08548c14",
+562 => x"5381c0f0",
+563 => x"08528a51",
+564 => x"90a73f84",
+565 => x"1508ad38",
+566 => x"860b8c16",
+567 => x"0c881552",
+568 => x"88160851",
+569 => x"8fb33f81",
+570 => x"c0fc0870",
+571 => x"08760c54",
+572 => x"8c157054",
+573 => x"548a5273",
+574 => x"08518ffd",
+575 => x"3f73800c",
+576 => x"873d0d04",
+577 => x"750854b0",
+578 => x"53735275",
+579 => x"51abc93f",
+580 => x"73800c87",
+581 => x"3d0d04d9",
+582 => x"3d0db051",
+583 => x"9eeb3f80",
+584 => x"0881c0ec",
+585 => x"0cb0519e",
+586 => x"e03f8008",
+587 => x"81c0fc0c",
+588 => x"81c0ec08",
+589 => x"80080c80",
+590 => x"0b800884",
+591 => x"050c820b",
+592 => x"80088805",
+593 => x"0ca80b80",
+594 => x"088c050c",
+595 => x"9f530b0b",
+596 => x"80d49052",
+597 => x"80089005",
+598 => x"51aafd3f",
+599 => x"a13d5e9f",
+600 => x"530b0b80",
+601 => x"d4b0527d",
+602 => x"51aaed3f",
+603 => x"8a0b80ff",
+604 => x"b00c0b0b",
+605 => x"80ded451",
+606 => x"f9b43f0b",
+607 => x"0b80d4d0",
+608 => x"51f9ab3f",
+609 => x"0b0b80de",
+610 => x"d451f9a2",
+611 => x"3f80e2b4",
+612 => x"08802e8a",
+613 => x"cf380b0b",
+614 => x"80d58051",
+615 => x"f9903f0b",
+616 => x"0b80ded4",
+617 => x"51f9873f",
+618 => x"80e2b008",
+619 => x"520b0b80",
+620 => x"d5ac51f8",
+621 => x"f93f80f2",
+622 => x"cc51bbf8",
+623 => x"3f810b9a",
+624 => x"3d5e5b80",
+625 => x"0b80e2b0",
+626 => x"082582d6",
+627 => x"38903d5f",
+628 => x"80c10b81",
+629 => x"c0f43481",
+630 => x"0b81c2d0",
+631 => x"0c80c20b",
+632 => x"81c0f834",
+633 => x"8240835a",
+634 => x"9f530b0b",
+635 => x"80d5dc52",
+636 => x"7c51a9e4",
+637 => x"3f814180",
+638 => x"7d537e52",
+639 => x"568f9e3f",
+640 => x"8008762e",
+641 => x"09810683",
+642 => x"38815675",
+643 => x"81c2d00c",
+644 => x"7f705856",
+645 => x"758325a2",
+646 => x"38751010",
+647 => x"16fd0542",
+648 => x"a93dffa4",
+649 => x"05538352",
+650 => x"76518dcd",
+651 => x"3f7f8105",
+652 => x"70417058",
+653 => x"56837624",
+654 => x"e0386154",
+655 => x"755380f2",
+656 => x"d45281c1",
+657 => x"88518dc1",
+658 => x"3f81c0fc",
+659 => x"08700858",
+660 => x"58b05377",
+661 => x"527651a8",
+662 => x"ff3f850b",
+663 => x"8c190c85",
+664 => x"0b8c180c",
+665 => x"7708770c",
+666 => x"81c0fc08",
+667 => x"5675802e",
+668 => x"8a387508",
+669 => x"770c81c0",
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+3148 => x"000004d2", -- iterations 0x4d2=1234 
+3149 => x"00000000",
+3150 => x"00000000",
+3151 => x"00000000",
+3152 => x"00000000",
+3153 => x"00000000",
+3154 => x"00000000",
+3155 => x"00000000",
+3156 => x"00000000",
+3157 => x"00000000",
+3158 => x"00000000",
+3159 => x"00000000",
+3160 => x"00000000",
+3161 => x"00000000",
+3162 => x"ffffffff",
+3163 => x"00000000",
+3164 => x"00020000",
+3165 => x"00000000",
+3166 => x"00000000",
+3167 => x"00003174",
+3168 => x"00003174",
+3169 => x"0000317c",
+3170 => x"0000317c",
+3171 => x"00003184",
+3172 => x"00003184",
+3173 => x"0000318c",
+3174 => x"0000318c",
+3175 => x"00003194",
+3176 => x"00003194",
+3177 => x"0000319c",
+3178 => x"0000319c",
+3179 => x"000031a4",
+3180 => x"000031a4",
+3181 => x"000031ac",
+3182 => x"000031ac",
+3183 => x"000031b4",
+3184 => x"000031b4",
+3185 => x"000031bc",
+3186 => x"000031bc",
+3187 => x"000031c4",
+3188 => x"000031c4",
+3189 => x"000031cc",
+3190 => x"000031cc",
+3191 => x"000031d4",
+3192 => x"000031d4",
+3193 => x"000031dc",
+3194 => x"000031dc",
+3195 => x"000031e4",
+3196 => x"000031e4",
+3197 => x"000031ec",
+3198 => x"000031ec",
+3199 => x"000031f4",
+3200 => x"000031f4",
+3201 => x"000031fc",
+3202 => x"000031fc",
+3203 => x"00003204",
+3204 => x"00003204",
+3205 => x"0000320c",
+3206 => x"0000320c",
+3207 => x"00003214",
+3208 => x"00003214",
+3209 => x"0000321c",
+3210 => x"0000321c",
+3211 => x"00003224",
+3212 => x"00003224",
+3213 => x"0000322c",
+3214 => x"0000322c",
+3215 => x"00003234",
+3216 => x"00003234",
+3217 => x"0000323c",
+3218 => x"0000323c",
+3219 => x"00003244",
+3220 => x"00003244",
+3221 => x"0000324c",
+3222 => x"0000324c",
+3223 => x"00003254",
+3224 => x"00003254",
+3225 => x"0000325c",
+3226 => x"0000325c",
+3227 => x"00003264",
+3228 => x"00003264",
+3229 => x"0000326c",
+3230 => x"0000326c",
+3231 => x"00003274",
+3232 => x"00003274",
+3233 => x"0000327c",
+3234 => x"0000327c",
+3235 => x"00003284",
+3236 => x"00003284",
+3237 => x"0000328c",
+3238 => x"0000328c",
+3239 => x"00003294",
+3240 => x"00003294",
+3241 => x"0000329c",
+3242 => x"0000329c",
+3243 => x"000032a4",
+3244 => x"000032a4",
+3245 => x"000032ac",
+3246 => x"000032ac",
+3247 => x"000032b4",
+3248 => x"000032b4",
+3249 => x"000032bc",
+3250 => x"000032bc",
+3251 => x"000032c4",
+3252 => x"000032c4",
+3253 => x"000032cc",
+3254 => x"000032cc",
+3255 => x"000032d4",
+3256 => x"000032d4",
+3257 => x"000032dc",
+3258 => x"000032dc",
+3259 => x"000032e4",
+3260 => x"000032e4",
+3261 => x"000032ec",
+3262 => x"000032ec",
+3263 => x"000032f4",
+3264 => x"000032f4",
+3265 => x"000032fc",
+3266 => x"000032fc",
+3267 => x"00003304",
+3268 => x"00003304",
+3269 => x"0000330c",
+3270 => x"0000330c",
+3271 => x"00003314",
+3272 => x"00003314",
+3273 => x"0000331c",
+3274 => x"0000331c",
+3275 => x"00003324",
+3276 => x"00003324",
+3277 => x"0000332c",
+3278 => x"0000332c",
+3279 => x"00003334",
+3280 => x"00003334",
+3281 => x"0000333c",
+3282 => x"0000333c",
+3283 => x"00003344",
+3284 => x"00003344",
+3285 => x"0000334c",
+3286 => x"0000334c",
+3287 => x"00003354",
+3288 => x"00003354",
+3289 => x"0000335c",
+3290 => x"0000335c",
+3291 => x"00003364",
+3292 => x"00003364",
+3293 => x"0000336c",
+3294 => x"0000336c",
+3295 => x"00003374",
+3296 => x"00003374",
+3297 => x"0000337c",
+3298 => x"0000337c",
+3299 => x"00003384",
+3300 => x"00003384",
+3301 => x"0000338c",
+3302 => x"0000338c",
+3303 => x"00003394",
+3304 => x"00003394",
+3305 => x"0000339c",
+3306 => x"0000339c",
+3307 => x"000033a4",
+3308 => x"000033a4",
+3309 => x"000033ac",
+3310 => x"000033ac",
+3311 => x"000033b4",
+3312 => x"000033b4",
+3313 => x"000033bc",
+3314 => x"000033bc",
+3315 => x"000033c4",
+3316 => x"000033c4",
+3317 => x"000033cc",
+3318 => x"000033cc",
+3319 => x"000033d4",
+3320 => x"000033d4",
+3321 => x"000033dc",
+3322 => x"000033dc",
+3323 => x"000033e4",
+3324 => x"000033e4",
+3325 => x"000033ec",
+3326 => x"000033ec",
+3327 => x"000033f4",
+3328 => x"000033f4",
+3329 => x"000033fc",
+3330 => x"000033fc",
+3331 => x"00003404",
+3332 => x"00003404",
+3333 => x"0000340c",
+3334 => x"0000340c",
+3335 => x"00003414",
+3336 => x"00003414",
+3337 => x"0000341c",
+3338 => x"0000341c",
+3339 => x"00003424",
+3340 => x"00003424",
+3341 => x"0000342c",
+3342 => x"0000342c",
+3343 => x"00003434",
+3344 => x"00003434",
+3345 => x"0000343c",
+3346 => x"0000343c",
+3347 => x"00003444",
+3348 => x"00003444",
+3349 => x"0000344c",
+3350 => x"0000344c",
+3351 => x"00003454",
+3352 => x"00003454",
+3353 => x"0000345c",
+3354 => x"0000345c",
+3355 => x"00003464",
+3356 => x"00003464",
+3357 => x"0000346c",
+3358 => x"0000346c",
+3359 => x"00003474",
+3360 => x"00003474",
+3361 => x"0000347c",
+3362 => x"0000347c",
+3363 => x"00003484",
+3364 => x"00003484",
+3365 => x"0000348c",
+3366 => x"0000348c",
+3367 => x"00003494",
+3368 => x"00003494",
+3369 => x"0000349c",
+3370 => x"0000349c",
+3371 => x"000034a4",
+3372 => x"000034a4",
+3373 => x"000034ac",
+3374 => x"000034ac",
+3375 => x"000034b4",
+3376 => x"000034b4",
+3377 => x"000034bc",
+3378 => x"000034bc",
+3379 => x"000034c4",
+3380 => x"000034c4",
+3381 => x"000034cc",
+3382 => x"000034cc",
+3383 => x"000034d4",
+3384 => x"000034d4",
+3385 => x"000034dc",
+3386 => x"000034dc",
+3387 => x"000034e4",
+3388 => x"000034e4",
+3389 => x"000034ec",
+3390 => x"000034ec",
+3391 => x"000034f4",
+3392 => x"000034f4",
+3393 => x"000034fc",
+3394 => x"000034fc",
+3395 => x"00003504",
+3396 => x"00003504",
+3397 => x"0000350c",
+3398 => x"0000350c",
+3399 => x"00003514",
+3400 => x"00003514",
+3401 => x"0000351c",
+3402 => x"0000351c",
+3403 => x"00003524",
+3404 => x"00003524",
+3405 => x"0000352c",
+3406 => x"0000352c",
+3407 => x"00003534",
+3408 => x"00003534",
+3409 => x"0000353c",
+3410 => x"0000353c",
+3411 => x"00003544",
+3412 => x"00003544",
+3413 => x"0000354c",
+3414 => x"0000354c",
+3415 => x"00003554",
+3416 => x"00003554",
+3417 => x"0000355c",
+3418 => x"0000355c",
+3419 => x"00003564",
+3420 => x"00003564",
+3421 => x"0000356c",
+3422 => x"0000356c",
+3423 => x"00003580",
+3424 => x"00000000",
+3425 => x"000037e8",
+3426 => x"00003844",
+3427 => x"000038a0",
+3428 => x"00000000",
+3429 => x"00000000",
+3430 => x"00000000",
+3431 => x"00000000",
+3432 => x"00000000",
+3433 => x"00000000",
+3434 => x"00000000",
+3435 => x"00000000",
+3436 => x"00000000",
+3437 => x"00003100",
+3438 => x"00000000",
+3439 => x"00000000",
+3440 => x"00000000",
+3441 => x"00000000",
+3442 => x"00000000",
+3443 => x"00000000",
+3444 => x"00000000",
+3445 => x"00000000",
+3446 => x"00000000",
+3447 => x"00000000",
+3448 => x"00000000",
+3449 => x"00000000",
+3450 => x"00000000",
+3451 => x"00000000",
+3452 => x"00000000",
+3453 => x"00000000",
+3454 => x"00000000",
+3455 => x"00000000",
+3456 => x"00000000",
+3457 => x"00000000",
+3458 => x"00000000",
+3459 => x"00000000",
+3460 => x"00000000",
+3461 => x"00000000",
+3462 => x"00000000",
+3463 => x"00000000",
+3464 => x"00000000",
+3465 => x"00000000",
+3466 => x"00000001",
+3467 => x"330eabcd",
+3468 => x"1234e66d",
+3469 => x"deec0005",
+3470 => x"000b0000",
+3471 => x"00000000",
+3472 => x"00000000",
+3473 => x"00000000",
+3474 => x"00000000",
+3475 => x"00000000",
+3476 => x"00000000",
+3477 => x"00000000",
+3478 => x"00000000",
+3479 => x"00000000",
+3480 => x"00000000",
+3481 => x"00000000",
+3482 => x"00000000",
+3483 => x"00000000",
+3484 => x"00000000",
+3485 => x"00000000",
+3486 => x"00000000",
+3487 => x"00000000",
+3488 => x"00000000",
+3489 => x"00000000",
+3490 => x"00000000",
+3491 => x"00000000",
+3492 => x"00000000",
+3493 => x"00000000",
+3494 => x"00000000",
+3495 => x"00000000",
+3496 => x"00000000",
+3497 => x"00000000",
+3498 => x"00000000",
+3499 => x"00000000",
+3500 => x"00000000",
+3501 => x"00000000",
+3502 => x"00000000",
+3503 => x"00000000",
+3504 => x"00000000",
+3505 => x"00000000",
+3506 => x"00000000",
+3507 => x"00000000",
+3508 => x"00000000",
+3509 => x"00000000",
+3510 => x"00000000",
+3511 => x"00000000",
+3512 => x"00000000",
+3513 => x"00000000",
+3514 => x"00000000",
+3515 => x"00000000",
+3516 => x"00000000",
+3517 => x"00000000",
+3518 => x"00000000",
+3519 => x"00000000",
+3520 => x"00000000",
+3521 => x"00000000",
+3522 => x"00000000",
+3523 => x"00000000",
+3524 => x"00000000",
+3525 => x"00000000",
+3526 => x"00000000",
+3527 => x"00000000",
+3528 => x"00000000",
+3529 => x"00000000",
+3530 => x"00000000",
+3531 => x"00000000",
+3532 => x"00000000",
+3533 => x"00000000",
+3534 => x"00000000",
+3535 => x"00000000",
+3536 => x"00000000",
+3537 => x"00000000",
+3538 => x"00000000",
+3539 => x"00000000",
+3540 => x"00000000",
+3541 => x"00000000",
+3542 => x"00000000",
+3543 => x"00000000",
+3544 => x"00000000",
+3545 => x"00000000",
+3546 => x"00000000",
+3547 => x"00000000",
+3548 => x"00000000",
+3549 => x"00000000",
+3550 => x"00000000",
+3551 => x"00000000",
+3552 => x"00000000",
+3553 => x"00000000",
+3554 => x"00000000",
+3555 => x"00000000",
+3556 => x"00000000",
+3557 => x"00000000",
+3558 => x"00000000",
+3559 => x"00000000",
+3560 => x"00000000",
+3561 => x"00000000",
+3562 => x"00000000",
+3563 => x"00000000",
+3564 => x"00000000",
+3565 => x"00000000",
+3566 => x"00000000",
+3567 => x"00000000",
+3568 => x"00000000",
+3569 => x"00000000",
+3570 => x"00000000",
+3571 => x"00000000",
+3572 => x"00000000",
+3573 => x"00000000",
+3574 => x"00000000",
+3575 => x"00000000",
+3576 => x"00000000",
+3577 => x"00000000",
+3578 => x"00000000",
+3579 => x"00000000",
+3580 => x"00000000",
+3581 => x"00000000",
+3582 => x"00000000",
+3583 => x"00000000",
+3584 => x"00000000",
+3585 => x"00000000",
+3586 => x"00000000",
+3587 => x"00000000",
+3588 => x"00000000",
+3589 => x"00000000",
+3590 => x"00000000",
+3591 => x"00000000",
+3592 => x"00000000",
+3593 => x"00000000",
+3594 => x"00000000",
+3595 => x"00000000",
+3596 => x"00000000",
+3597 => x"00000000",
+3598 => x"00000000",
+3599 => x"00000000",
+3600 => x"00000000",
+3601 => x"00000000",
+3602 => x"00000000",
+3603 => x"00000000",
+3604 => x"00000000",
+3605 => x"00000000",
+3606 => x"00000000",
+3607 => x"00000000",
+3608 => x"00000000",
+3609 => x"00000000",
+3610 => x"00000000",
+3611 => x"00000000",
+3612 => x"00000000",
+3613 => x"00000000",
+3614 => x"00000000",
+3615 => x"00000000",
+3616 => x"00000000",
+3617 => x"00000000",
+3618 => x"00000000",
+3619 => x"00000000",
+3620 => x"00000000",
+3621 => x"00000000",
+3622 => x"00000000",
+3623 => x"00000000",
+3624 => x"00000000",
+3625 => x"00000000",
+3626 => x"00000000",
+3627 => x"00000000",
+3628 => x"00000000",
+3629 => x"00000000",
+3630 => x"00000000",
+3631 => x"00000000",
+3632 => x"00000000",
+3633 => x"00000000",
+3634 => x"00000000",
+3635 => x"00000000",
+3636 => x"00000000",
+3637 => x"00000000",
+3638 => x"00000000",
+3639 => x"00000000",
+3640 => x"00000000",
+3641 => x"00000000",
+3642 => x"00000000",
+3643 => x"00000000",
+3644 => x"00000000",
+3645 => x"00000000",
+3646 => x"00000000",
+3647 => x"00003104",
+3648 => x"ffffffff",
+3649 => x"00000000",
+3650 => x"ffffffff",
+3651 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then
+			report "write collision" severity failure;
+		end if;
+	
+		if (memAWriteEnable = '1') then
+			ram(conv_integer(memAAddr)) := memAWrite;
+			memARead <= memAWrite;
+		else
+			memARead <= ram(conv_integer(memAAddr));
+		end if;
+	end if;
+end process;
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		if (memBWriteEnable = '1') then
+			ram(conv_integer(memBAddr)) := memBWrite;
+			memBRead <= memBWrite;
+		else
+			memBRead <= ram(conv_integer(memBAddr));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dualport_ram_arch;
diff --git a/zpu/hdl/zpu4/src/build.xml b/zpu/hdl/zpu4/src/build.xml
new file mode 100644
index 0000000..e1b268a
--- /dev/null
+++ b/zpu/hdl/zpu4/src/build.xml
@@ -0,0 +1,114 @@
+<!--
+
+FIX!!! start /b /wait /belownormal does not propagate return code..
+-->
+<project name="ZPU3" default="all" basedir=".">
+	<property name="chipname" value="ic300"/>
+	<property name="packagetype" value="xc3s400-ft256-4"/>
+		
+		  
+	<description>eCosBoard firmware build file</description>
+
+	<target name="setuplibs">
+		<!-- N/A yet
+		<copy todir="../src">
+			<fileset dir="..\fpgalib\" includes="foo_top.ngc" />
+		</copy>
+		-->
+	</target>
+
+	<target name="setup">
+		<mkdir dir="..\reports"/>
+		<mkdir dir="..\syn"/>
+		<mkdir dir="..\ngo"/>
+		<mkdir dir="..\output"/>
+		<mkdir dir="..\tmp"/>
+		<mkdir dir="..\xst"/>
+	</target>
+
+	<target name="clean">
+		<delete dir="..\reports"/>
+		<delete dir="..\syn"/>
+		<delete dir="..\ngo"/>
+		<delete dir="..\output"/>
+		<delete dir="..\tmp"/>
+		<delete dir="..\xst"/>
+	</target>
+
+	<target name="synthesis" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c xst -intstyle ise -ifn xmake.xst -ofn ..\reports\1_synthesis.txt"/>
+		</exec>
+	</target>
+
+
+	<target name="translate" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c ngdbuild -intstyle ise -dd ..\ngo -uc ${chipname}.ucf -a  -p ${packagetype} ..\syn\${chipname}.ngc ..\ngo\${chipname}.ngd"/>
+		</exec>
+		<move tofile="..\reports\2_translate.txt">
+			<fileset dir="..\ngo" includes="${chipname}.bld"/>
+		</move>
+	</target>
+
+	<target name="mapping" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c map -intstyle ise -p ${packagetype} -ol high -timing -detail -cm area -ignore_keep_hierarchy -pr b -k 6 -r -c 100 -tx off -o ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ngd ..\ngo\${chipname}.pcf"/>
+		</exec>
+		<move tofile="..\reports\3_mapping.txt">
+			<fileset dir="..\ngo" includes="${chipname}_map.mrp"/>
+		</move>
+	</target>
+
+
+	<target name="placeandroute" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c par -w -intstyle ise -ol high -t 1 ..\ngo\${chipname}_map.ncd ..\ngo\${chipname}.ncd ..\ngo\${chipname}.pcf"/>
+		</exec>
+		<move tofile="..\reports\4_placeandroute.txt">
+			<fileset dir="..\ngo" includes="${chipname}.par"/>
+		</move>
+		<move tofile="..\reports\5_pads.txt">
+			<fileset dir="..\ngo" includes="${chipname}_pad.txt"/>
+		</move>
+	</target>
+
+
+	<target name="gentime" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c trce -intstyle ise -v 3 -l 3 -a -u 100 ..\ngo\${chipname}.ncd -o ..\reports\timing.twr ..\ngo\${chipname}.pcf"/>
+		</exec>
+		<delete file="..\reports\6_timing.txt"/>
+		<move tofile="..\reports\6_timing.txt">
+			<fileset dir="..\reports" includes="timing.twr"/>
+		</move>
+	</target>
+
+
+	<target name="genbit" depends="setup">
+		<exec executable="cmd" failonerror="true">
+			<arg line="/c bitgen -intstyle ise -w -f ${chipname}.bitgen ..\ngo\${chipname}.ncd"/>
+		</exec>
+		<move tofile="..\reports\7_bitgen.txt">
+			<fileset dir="..\ngo" includes="${chipname}.bgn"/>
+		</move>
+	</target>
+
+	<target name="copyfiles" depends="setup">
+		<copy todir="../output">
+			<fileset dir="..\ngo" includes="${chipname}.bin"/>
+		</copy>
+		<!--
+		<copy tofile="${workspace_loc}\firmware\board\xeddvifpgadata.rawdata">
+			<fileset dir="..\ngo" includes="${chipname}.bin"/>
+		</copy>
+		-->
+	</target>
+
+
+	<target name="all" depends="setuplibs,synthesis,translate,mapping,placeandroute,gentime,genbit,copyfiles">
+
+	</target>
+
+
+</project>
\ No newline at end of file
diff --git a/zpu/hdl/zpu4/src/clocks.vhd b/zpu/hdl/zpu4/src/clocks.vhd
new file mode 100644
index 0000000..a352b3c
--- /dev/null
+++ b/zpu/hdl/zpu4/src/clocks.vhd
@@ -0,0 +1,246 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clocks is
+	port (	areset			: in std_logic;
+			cpu_clk_p		: in std_logic;
+			sdr_clk_fb_p	: in std_logic;
+			cpu_clk			: out std_logic;
+			cpu_clk_2x		: out std_logic;
+			cpu_clk_4x		: out std_logic;
+			ddr_in_clk		: out std_logic;
+			ddr_in_clk_2x	: out std_logic;
+			locked			: out std_logic_vector(2 downto 0));
+end clocks;
+
+architecture behave of clocks is
+
+signal	low					: std_logic;
+
+signal	cpu_clk_in			: std_logic;
+signal	sdr_clk_fb_in		: std_logic;
+
+signal	dcm_cpu1			: std_logic;
+signal	dcm_cpu2			: std_logic;
+signal	dcm_cpu2_dum		: std_logic;
+signal	dcm_cpu4			: std_logic;
+signal	dcm_ddr2			: std_logic;
+signal	dcm_ddr2_2x			: std_logic;
+
+signal	cpu_clk_int			: std_logic;
+signal	cpu_clk_2x_int		: std_logic;
+signal	cpu_clk_2x_dum_int	: std_logic;
+signal	cpu_clk_4x_int		: std_logic;
+signal	ddr_in_clk_int		: std_logic;
+signal	ddr_in_clk_2x_int	: std_logic;
+
+signal	dcm1_locked_del		: std_logic;
+signal	dcm2_locked_del		: std_logic;
+signal	dcm2_reset			: std_logic;
+signal	dcm3_reset			: std_logic;
+
+signal	locked_int			: std_logic_vector(2 downto 0);
+signal	del_addr			: std_logic_vector(3 downto 0);
+
+begin
+
+	low <= '0';				
+	del_addr <= "1111";
+	
+	cpu_clk <= cpu_clk_int;
+	cpu_clk_2x <= cpu_clk_2x_int;
+	cpu_clk_4x <= cpu_clk_4x_int;
+	ddr_in_clk <= ddr_in_clk_int;
+	ddr_in_clk_2x <= ddr_in_clk_2x_int;
+	locked <= locked_int;
+	
+
+   	CPU_IBUFG: 
+   	IBUFG port map (
+      	O => cpu_clk_in,
+      	I => cpu_clk_p);
+	
+   	SDR_FB_IBUFG: 
+   	IBUFG port map (
+      	O => sdr_clk_fb_in,
+      	I => sdr_clk_fb_p);
+      	
+   dcm2_rst: 
+   SRL16 generic map (
+      	INIT => X"0000")
+   port map (
+      	Q => dcm1_locked_del,
+      	A0 => del_addr(0),
+      	A1 => del_addr(1),
+      	A2 => del_addr(2),
+      	A3 => del_addr(3),
+      	CLK => cpu_clk_int,
+      	D => locked_int(0));
+      	
+	dcm2_reset <= not(dcm1_locked_del);      	
+	
+   dcm3_rst: 
+   SRL16 generic map (
+      	INIT => X"0000")
+   port map (
+      	Q => dcm2_locked_del,
+      	A0 => del_addr(0),
+      	A1 => del_addr(1),
+      	A2 => del_addr(2),
+      	A3 => del_addr(3),
+      	CLK => cpu_clk_int,
+      	D => locked_int(1));
+      	
+	dcm3_reset <= not(dcm2_locked_del);      	
+	
+   	cpu1_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 15.625,          --  Specify period of input clock
+      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_cpu1,   -- 0 degree DCM CLK ouptput
+      	CLK180 => open, 	-- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_cpu2, 	-- 2X DCM CLK output
+      	CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(0), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => cpu_clk_int,   -- DCM clock feedback
+      	CLKIN => cpu_clk_in,   -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => areset);     -- DCM asynchronous reset input
+   
+   	cpu2_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
+      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_cpu2_dum,     	-- 0 degree DCM CLK ouptput
+      	CLK180 => open,		 -- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_cpu4,  -- 2X DCM CLK output
+      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(1), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => cpu_clk_2x_dum_int,   -- DCM clock feedback
+      	CLKIN => cpu_clk_2x_int,   -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => dcm2_reset);     -- DCM asynchronous reset input
+   
+   	ddr_read_dcm: 
+   	DCM generic map (
+      	CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+      	CLKFX_DIVIDE => 1,   --  Can be any interger from 1 to 32
+      	CLKFX_MULTIPLY => 4, --  Can be any integer from 1 to 32
+      	CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
+      	CLKIN_PERIOD => 7.8125,          --  Specify period of input clock
+     	CLKOUT_PHASE_SHIFT => "FIXED", --  Specify phase shift of NONE, FIXED or VARIABLE
+--      	CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of NONE, FIXED or VARIABLE
+      	CLK_FEEDBACK => "1X",         --  Specify clock feedback of NONE, 1X or 2X
+      	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", --  SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+                                             --     an integer from 0 to 15
+      	DFS_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for frequency synthesis
+      	DLL_FREQUENCY_MODE => "LOW",     --  HIGH or LOW frequency mode for DLL
+      	DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
+      	FACTORY_JF => X"8080",          --  FACTORY JF Values
+      	PHASE_SHIFT => 103,        --  Amount of fixed phase shift from -255 to 255
+--      	PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
+      	STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM LOCK, TRUE/FALSE
+   	port map (
+      	CLK0 => dcm_ddr2,     	-- 0 degree DCM CLK ouptput
+      	CLK180 => open,		 -- 180 degree DCM CLK output
+      	CLK270 => open,	 	-- 270 degree DCM CLK output
+      	CLK2X => dcm_ddr2_2x,  -- 2X DCM CLK output
+      	CLK2X180 => open, 	-- 2X, 180 degree DCM CLK out
+      	CLK90 => open,   	-- 90 degree DCM CLK output
+      	CLKDV => open,   	-- Divided DCM CLK out (CLKDV_DIVIDE)
+      	CLKFX => open,   	-- DCM CLK synthesis out (M/D)
+      	CLKFX180 => open, 	-- 180 degree CLK synthesis out
+      	LOCKED => locked_int(2), -- DCM LOCK status output
+      	PSDONE => open, 	-- Dynamic phase adjust done output
+      	STATUS => open, 	-- 8-bit DCM status bits output
+      	CLKFB => ddr_in_clk_int,   -- DCM clock feedback
+      	CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
+      	PSCLK => low,   	-- Dynamic phase adjust clock input
+      	PSEN => low,     	-- Dynamic phase adjust enable input
+      	PSINCDEC => low, 	-- Dynamic phase adjust increment/decrement
+      	RST => dcm3_reset);     -- DCM asynchronous reset input
+   
+   	cpu1:
+	BUFG port map (
+		I => dcm_cpu1,
+		O => cpu_clk_int);
+		
+   	cpu2:
+	BUFG port map (
+		I => dcm_cpu2,
+		O => cpu_clk_2x_int);
+		
+   	cpu2_dum:
+	BUFG port map (
+		I => dcm_cpu2_dum,
+		O => cpu_clk_2x_dum_int);
+		
+   	cpu4:
+	BUFG port map (
+		I => dcm_cpu4,
+		O => cpu_clk_4x_int);
+		
+   	ddr_clk:
+	BUFG port map (
+		I => dcm_ddr2,
+		O => ddr_in_clk_int);
+
+   	ddr_clk_2x:
+	BUFG port map (
+		I => dcm_ddr2_2x,
+		O => ddr_in_clk_2x_int);
+
+end behave;
\ No newline at end of file
diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace.do b/zpu/hdl/zpu4/src/dmipssmalltrace.do
new file mode 100644
index 0000000..eb4c6fe
--- /dev/null
+++ b/zpu/hdl/zpu4/src/dmipssmalltrace.do
@@ -0,0 +1,26 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config_trace.vhd
+vcom -93 -explicit  zpupkg.vhd
+vcom -93 -explicit  txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  zpu_core_small.vhd
+vcom -93 -explicit  bram_dmips.vhd
+vcom -93 -explicit  dram_dmips.vhd
+vcom -93 -explicit  timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  trace.vhd
+
+
+vsim fpga_top
+view wave
+
+add wave -recursive fpga_top/zpu/*
+#--add wave -recursive fpga_top/ioMap/*
+#add wave -recursive fpga_top/*
+view structure
+
+
+# run ZPU
+run 5 ms
diff --git a/zpu/hdl/zpu4/src/dmipstrace.do b/zpu/hdl/zpu4/src/dmipstrace.do
new file mode 100644
index 0000000..8d5f430
--- /dev/null
+++ b/zpu/hdl/zpu4/src/dmipstrace.do
@@ -0,0 +1,25 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config_trace.vhd
+vcom -93 -explicit  zpupkg.vhd
+vcom -93 -explicit  txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  zpu_core.vhd
+vcom -93 -explicit  dram_dmips.vhd
+vcom -93 -explicit  timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  trace.vhd
+
+
+vsim fpga_top
+view wave
+
+add wave -recursive fpga_top/zpu/*
+#--add wave -recursive fpga_top/ioMap/*
+#add wave -recursive fpga_top/*
+view structure
+
+
+# run ZPU
+run 5 ms
diff --git a/zpu/hdl/zpu4/src/dmipstraceintstack.do b/zpu/hdl/zpu4/src/dmipstraceintstack.do
new file mode 100644
index 0000000..b2addb4
--- /dev/null
+++ b/zpu/hdl/zpu4/src/dmipstraceintstack.do
@@ -0,0 +1,25 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config_trace.vhd
+vcom -93 -explicit  zpupkg.vhd
+vcom -93 -explicit  txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  zpu_core_intstack.vhd
+vcom -93 -explicit  dram_dmips.vhd
+vcom -93 -explicit  timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  trace.vhd
+
+
+vsim fpga_top
+view wave
+
+add wave -recursive fpga_top/zpu/*
+#--add wave -recursive fpga_top/ioMap/*
+#add wave -recursive fpga_top/*
+view structure
+
+
+# run ZPU
+run 5 ms
diff --git a/zpu/hdl/zpu4/src/dram_dmips.vhd b/zpu/hdl/zpu4/src/dram_dmips.vhd
new file mode 100644
index 0000000..e63a27a
--- /dev/null
+++ b/zpu/hdl/zpu4/src/dram_dmips.vhd
@@ -0,0 +1,3702 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+areset : std_logic;
+		mem_writeEnable : in std_logic;
+		mem_readEnable : in std_logic;
+		mem_addr : in std_logic_vector(maxAddrBit downto 0);
+		mem_write : in std_logic_vector(wordSize-1 downto 0);
+		mem_read : out std_logic_vector(wordSize-1 downto 0);
+		mem_busy : out std_logic;
+		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"80700b0b",
+2 => x"80e2a40c",
+3 => x"3a0b0b80",
+4 => x"c6fc0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c7c32d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80e2",
+162 => x"90738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0baf",
+171 => x"ac2d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0baf",
+179 => x"f02d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80e2a00c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
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+3370 => x"0000349c",
+3371 => x"000034a4",
+3372 => x"000034a4",
+3373 => x"000034ac",
+3374 => x"000034ac",
+3375 => x"000034b4",
+3376 => x"000034b4",
+3377 => x"000034bc",
+3378 => x"000034bc",
+3379 => x"000034c4",
+3380 => x"000034c4",
+3381 => x"000034cc",
+3382 => x"000034cc",
+3383 => x"000034d4",
+3384 => x"000034d4",
+3385 => x"000034dc",
+3386 => x"000034dc",
+3387 => x"000034e4",
+3388 => x"000034e4",
+3389 => x"000034ec",
+3390 => x"000034ec",
+3391 => x"000034f4",
+3392 => x"000034f4",
+3393 => x"000034fc",
+3394 => x"000034fc",
+3395 => x"00003504",
+3396 => x"00003504",
+3397 => x"0000350c",
+3398 => x"0000350c",
+3399 => x"00003514",
+3400 => x"00003514",
+3401 => x"0000351c",
+3402 => x"0000351c",
+3403 => x"00003524",
+3404 => x"00003524",
+3405 => x"0000352c",
+3406 => x"0000352c",
+3407 => x"00003534",
+3408 => x"00003534",
+3409 => x"0000353c",
+3410 => x"0000353c",
+3411 => x"00003544",
+3412 => x"00003544",
+3413 => x"0000354c",
+3414 => x"0000354c",
+3415 => x"00003554",
+3416 => x"00003554",
+3417 => x"0000355c",
+3418 => x"0000355c",
+3419 => x"00003564",
+3420 => x"00003564",
+3421 => x"0000356c",
+3422 => x"0000356c",
+3423 => x"00003580",
+3424 => x"00000000",
+3425 => x"000037e8",
+3426 => x"00003844",
+3427 => x"000038a0",
+3428 => x"00000000",
+3429 => x"00000000",
+3430 => x"00000000",
+3431 => x"00000000",
+3432 => x"00000000",
+3433 => x"00000000",
+3434 => x"00000000",
+3435 => x"00000000",
+3436 => x"00000000",
+3437 => x"00003100",
+3438 => x"00000000",
+3439 => x"00000000",
+3440 => x"00000000",
+3441 => x"00000000",
+3442 => x"00000000",
+3443 => x"00000000",
+3444 => x"00000000",
+3445 => x"00000000",
+3446 => x"00000000",
+3447 => x"00000000",
+3448 => x"00000000",
+3449 => x"00000000",
+3450 => x"00000000",
+3451 => x"00000000",
+3452 => x"00000000",
+3453 => x"00000000",
+3454 => x"00000000",
+3455 => x"00000000",
+3456 => x"00000000",
+3457 => x"00000000",
+3458 => x"00000000",
+3459 => x"00000000",
+3460 => x"00000000",
+3461 => x"00000000",
+3462 => x"00000000",
+3463 => x"00000000",
+3464 => x"00000000",
+3465 => x"00000000",
+3466 => x"00000001",
+3467 => x"330eabcd",
+3468 => x"1234e66d",
+3469 => x"deec0005",
+3470 => x"000b0000",
+3471 => x"00000000",
+3472 => x"00000000",
+3473 => x"00000000",
+3474 => x"00000000",
+3475 => x"00000000",
+3476 => x"00000000",
+3477 => x"00000000",
+3478 => x"00000000",
+3479 => x"00000000",
+3480 => x"00000000",
+3481 => x"00000000",
+3482 => x"00000000",
+3483 => x"00000000",
+3484 => x"00000000",
+3485 => x"00000000",
+3486 => x"00000000",
+3487 => x"00000000",
+3488 => x"00000000",
+3489 => x"00000000",
+3490 => x"00000000",
+3491 => x"00000000",
+3492 => x"00000000",
+3493 => x"00000000",
+3494 => x"00000000",
+3495 => x"00000000",
+3496 => x"00000000",
+3497 => x"00000000",
+3498 => x"00000000",
+3499 => x"00000000",
+3500 => x"00000000",
+3501 => x"00000000",
+3502 => x"00000000",
+3503 => x"00000000",
+3504 => x"00000000",
+3505 => x"00000000",
+3506 => x"00000000",
+3507 => x"00000000",
+3508 => x"00000000",
+3509 => x"00000000",
+3510 => x"00000000",
+3511 => x"00000000",
+3512 => x"00000000",
+3513 => x"00000000",
+3514 => x"00000000",
+3515 => x"00000000",
+3516 => x"00000000",
+3517 => x"00000000",
+3518 => x"00000000",
+3519 => x"00000000",
+3520 => x"00000000",
+3521 => x"00000000",
+3522 => x"00000000",
+3523 => x"00000000",
+3524 => x"00000000",
+3525 => x"00000000",
+3526 => x"00000000",
+3527 => x"00000000",
+3528 => x"00000000",
+3529 => x"00000000",
+3530 => x"00000000",
+3531 => x"00000000",
+3532 => x"00000000",
+3533 => x"00000000",
+3534 => x"00000000",
+3535 => x"00000000",
+3536 => x"00000000",
+3537 => x"00000000",
+3538 => x"00000000",
+3539 => x"00000000",
+3540 => x"00000000",
+3541 => x"00000000",
+3542 => x"00000000",
+3543 => x"00000000",
+3544 => x"00000000",
+3545 => x"00000000",
+3546 => x"00000000",
+3547 => x"00000000",
+3548 => x"00000000",
+3549 => x"00000000",
+3550 => x"00000000",
+3551 => x"00000000",
+3552 => x"00000000",
+3553 => x"00000000",
+3554 => x"00000000",
+3555 => x"00000000",
+3556 => x"00000000",
+3557 => x"00000000",
+3558 => x"00000000",
+3559 => x"00000000",
+3560 => x"00000000",
+3561 => x"00000000",
+3562 => x"00000000",
+3563 => x"00000000",
+3564 => x"00000000",
+3565 => x"00000000",
+3566 => x"00000000",
+3567 => x"00000000",
+3568 => x"00000000",
+3569 => x"00000000",
+3570 => x"00000000",
+3571 => x"00000000",
+3572 => x"00000000",
+3573 => x"00000000",
+3574 => x"00000000",
+3575 => x"00000000",
+3576 => x"00000000",
+3577 => x"00000000",
+3578 => x"00000000",
+3579 => x"00000000",
+3580 => x"00000000",
+3581 => x"00000000",
+3582 => x"00000000",
+3583 => x"00000000",
+3584 => x"00000000",
+3585 => x"00000000",
+3586 => x"00000000",
+3587 => x"00000000",
+3588 => x"00000000",
+3589 => x"00000000",
+3590 => x"00000000",
+3591 => x"00000000",
+3592 => x"00000000",
+3593 => x"00000000",
+3594 => x"00000000",
+3595 => x"00000000",
+3596 => x"00000000",
+3597 => x"00000000",
+3598 => x"00000000",
+3599 => x"00000000",
+3600 => x"00000000",
+3601 => x"00000000",
+3602 => x"00000000",
+3603 => x"00000000",
+3604 => x"00000000",
+3605 => x"00000000",
+3606 => x"00000000",
+3607 => x"00000000",
+3608 => x"00000000",
+3609 => x"00000000",
+3610 => x"00000000",
+3611 => x"00000000",
+3612 => x"00000000",
+3613 => x"00000000",
+3614 => x"00000000",
+3615 => x"00000000",
+3616 => x"00000000",
+3617 => x"00000000",
+3618 => x"00000000",
+3619 => x"00000000",
+3620 => x"00000000",
+3621 => x"00000000",
+3622 => x"00000000",
+3623 => x"00000000",
+3624 => x"00000000",
+3625 => x"00000000",
+3626 => x"00000000",
+3627 => x"00000000",
+3628 => x"00000000",
+3629 => x"00000000",
+3630 => x"00000000",
+3631 => x"00000000",
+3632 => x"00000000",
+3633 => x"00000000",
+3634 => x"00000000",
+3635 => x"00000000",
+3636 => x"00000000",
+3637 => x"00000000",
+3638 => x"00000000",
+3639 => x"00000000",
+3640 => x"00000000",
+3641 => x"00000000",
+3642 => x"00000000",
+3643 => x"00000000",
+3644 => x"00000000",
+3645 => x"00000000",
+3646 => x"00000000",
+3647 => x"00003104",
+3648 => x"ffffffff",
+3649 => x"00000000",
+3650 => x"ffffffff",
+3651 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request
+
+process (clk, areset)
+begin
+		if areset = '1' then
+		elsif (clk'event and clk = '1') then
+			if (mem_writeEnable = '1') then
+				ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write;
+			end if;
+			mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit)));
+	end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/zpu4/src/dram_hello.vhd b/zpu/hdl/zpu4/src/dram_hello.vhd
new file mode 100644
index 0000000..dc46dbb
--- /dev/null
+++ b/zpu/hdl/zpu4/src/dram_hello.vhd
@@ -0,0 +1,3214 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity dram is
+port (clk : in std_logic;
+		mem_writeEnable : in std_logic;
+		mem_readEnable : in std_logic;
+		mem_addr : in std_logic_vector(maxAddrBit downto 0);
+		mem_write : in std_logic_vector(wordSize-1 downto 0);
+		mem_read : out std_logic_vector(wordSize-1 downto 0);
+		mem_busy : out std_logic;
+		mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+end dram;
+
+architecture dram_arch of dram is
+
+
+type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0);
+
+shared variable ram : ram_type :=
+(
+0 => x"0b0b0b0b",
+1 => x"80700b0b",
+2 => x"80d3900c",
+3 => x"3a0b0b80",
+4 => x"c8b20400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c8fb2d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80d2",
+162 => x"fc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0b8d",
+171 => x"872d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0b8d",
+179 => x"cb2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80d38c0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"83d93f80",
+257 => x"ca953f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"ff3d0d0b",
+281 => x"0b80e2f8",
+282 => x"08528412",
+283 => x"08708106",
+284 => x"515170f6",
+285 => x"38710881",
+286 => x"ff06800c",
+287 => x"833d0d04",
+288 => x"ff3d0d0b",
+289 => x"0b80e2f8",
+290 => x"08528412",
+291 => x"08700a10",
+292 => x"0a708106",
+293 => x"51515170",
+294 => x"f1387372",
+295 => x"0c833d0d",
+296 => x"0480d38c",
+297 => x"08802ea8",
+298 => x"38838080",
+299 => x"0b0b0b80",
+300 => x"e2f80c82",
+301 => x"a0800b0b",
+302 => x"0b80e2fc",
+303 => x"0c829080",
+304 => x"0b80e38c",
+305 => x"0c0b0b80",
+306 => x"e3800b80",
+307 => x"e3900c04",
+308 => x"f8808080",
+309 => x"a40b0b0b",
+310 => x"80e2f80c",
+311 => x"f8808082",
+312 => x"800b0b0b",
+313 => x"80e2fc0c",
+314 => x"f8808084",
+315 => x"800b80e3",
+316 => x"8c0cf880",
+317 => x"8080940b",
+318 => x"80e3900c",
+319 => x"f8808080",
+320 => x"9c0b80e3",
+321 => x"880cf880",
+322 => x"8080a00b",
+323 => x"80e3940c",
+324 => x"04f23d0d",
+325 => x"600b0b80",
+326 => x"e2fc0856",
+327 => x"5d82750c",
+328 => x"8059805a",
+329 => x"800b8f3d",
+330 => x"71101017",
+331 => x"70085957",
+332 => x"5d5b8076",
+333 => x"81ff067c",
+334 => x"832b5658",
+335 => x"5276537b",
+336 => x"5181fa3f",
+337 => x"7d7f7a72",
+338 => x"077c7207",
+339 => x"71716081",
+340 => x"05415f5d",
+341 => x"5b595755",
+342 => x"7a8724bb",
+343 => x"380b0b80",
+344 => x"e2fc087b",
+345 => x"10101170",
+346 => x"08585155",
+347 => x"807681ff",
+348 => x"067c832b",
+349 => x"56585276",
+350 => x"537b5181",
+351 => x"c03f7d7f",
+352 => x"7a72077c",
+353 => x"72077171",
+354 => x"60810541",
+355 => x"5f5d5b59",
+356 => x"5755877b",
+357 => x"25c73876",
+358 => x"7d0c7784",
+359 => x"1e0c7c80",
+360 => x"0c903d0d",
+361 => x"04ff3d0d",
+362 => x"80e38433",
+363 => x"5170a738",
+364 => x"80d39808",
+365 => x"70085252",
+366 => x"70802e94",
+367 => x"38841280",
+368 => x"d3980c70",
+369 => x"2d80d398",
+370 => x"08700852",
+371 => x"5270ee38",
+372 => x"810b80e3",
+373 => x"8434833d",
+374 => x"0d040480",
+375 => x"3d0d0b0b",
+376 => x"80e2f408",
+377 => x"802e8e38",
+378 => x"0b0b0b0b",
+379 => x"800b802e",
+380 => x"09810685",
+381 => x"38823d0d",
+382 => x"040b0b80",
+383 => x"e2f4510b",
+384 => x"0b0bf3fc",
+385 => x"3f823d0d",
+386 => x"0404fe3d",
+387 => x"0d89530b",
+388 => x"0b80d2c8",
+389 => x"51838d3f",
+390 => x"0b0b80d2",
+391 => x"d8518384",
+392 => x"3f810a0b",
+393 => x"80e3980c",
+394 => x"ff0b80e3",
+395 => x"9c0cff13",
+396 => x"53728025",
+397 => x"da387280",
+398 => x"0c843d0d",
+399 => x"04f93d0d",
+400 => x"797b7d7f",
+401 => x"56545254",
+402 => x"72802ea0",
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+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"00002fa0",
+3051 => x"00002fa0",
+3052 => x"00002fa8",
+3053 => x"00002fa8",
+3054 => x"00002fb0",
+3055 => x"00002fb0",
+3056 => x"00002fb8",
+3057 => x"00002fb8",
+3058 => x"00002fc0",
+3059 => x"00002fc0",
+3060 => x"00002fc8",
+3061 => x"00002fc8",
+3062 => x"00002fd0",
+3063 => x"00002fd0",
+3064 => x"00002fd8",
+3065 => x"00002fd8",
+3066 => x"00002fe0",
+3067 => x"00002fe0",
+3068 => x"00002fe8",
+3069 => x"00002fe8",
+3070 => x"00002ff0",
+3071 => x"00002ff0",
+3072 => x"00002ff8",
+3073 => x"00002ff8",
+3074 => x"00003000",
+3075 => x"00003000",
+3076 => x"00003008",
+3077 => x"00003008",
+3078 => x"00003010",
+3079 => x"00003010",
+3080 => x"00003018",
+3081 => x"00003018",
+3082 => x"00003020",
+3083 => x"00003020",
+3084 => x"00003028",
+3085 => x"00003028",
+3086 => x"00003030",
+3087 => x"00003030",
+3088 => x"00003038",
+3089 => x"00003038",
+3090 => x"00003040",
+3091 => x"00003040",
+3092 => x"00003048",
+3093 => x"00003048",
+3094 => x"00003050",
+3095 => x"00003050",
+3096 => x"00003058",
+3097 => x"00003058",
+3098 => x"00003060",
+3099 => x"00003060",
+3100 => x"00003068",
+3101 => x"00003068",
+3102 => x"00003070",
+3103 => x"00003070",
+3104 => x"00003078",
+3105 => x"00003078",
+3106 => x"00003080",
+3107 => x"00003080",
+3108 => x"00003088",
+3109 => x"00003088",
+3110 => x"00003090",
+3111 => x"00003090",
+3112 => x"00003098",
+3113 => x"00003098",
+3114 => x"000030a0",
+3115 => x"000030a0",
+3116 => x"000030a8",
+3117 => x"000030a8",
+3118 => x"000030b0",
+3119 => x"000030b0",
+3120 => x"000030b8",
+3121 => x"000030b8",
+3122 => x"000030c0",
+3123 => x"000030c0",
+3124 => x"000030c8",
+3125 => x"000030c8",
+3126 => x"000030d0",
+3127 => x"000030d0",
+3128 => x"000030d8",
+3129 => x"000030d8",
+3130 => x"000030e0",
+3131 => x"000030e0",
+3132 => x"000030e8",
+3133 => x"000030e8",
+3134 => x"000030f0",
+3135 => x"000030f0",
+3136 => x"000030f8",
+3137 => x"000030f8",
+3138 => x"00003100",
+3139 => x"00003100",
+3140 => x"00003108",
+3141 => x"00003108",
+3142 => x"00003110",
+3143 => x"00003110",
+3144 => x"00003118",
+3145 => x"00003118",
+3146 => x"00003120",
+3147 => x"00003120",
+3148 => x"00003128",
+3149 => x"00003128",
+3150 => x"00003130",
+3151 => x"00003130",
+3152 => x"00003138",
+3153 => x"00003138",
+3154 => x"00003140",
+3155 => x"00003140",
+3156 => x"00003148",
+3157 => x"00003148",
+3158 => x"00003150",
+3159 => x"00003150",
+3160 => x"00002970",
+3161 => x"ffffffff",
+3162 => x"00000000",
+3163 => x"ffffffff",
+3164 => x"00000000",
+	others => x"00000000"
+);
+
+begin
+
+process (clk)
+begin
+	if (clk'event and clk = '1') then
+		mem_busy<=mem_writeEnable or mem_readEnable;
+		if (mem_writeEnable = '1') then
+			ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write;
+		end if;
+		if (mem_readEnable = '1') then
+			mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit)));
+		end if;
+	end if;
+end process;
+
+
+
+
+end dram_arch;
diff --git a/zpu/hdl/zpu4/src/fastdmips.do b/zpu/hdl/zpu4/src/fastdmips.do
new file mode 100644
index 0000000..504bf60
--- /dev/null
+++ b/zpu/hdl/zpu4/src/fastdmips.do
@@ -0,0 +1,19 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config_fastsim.vhd
+vcom -93 -explicit  zpupkg.vhd
+vcom -93 -explicit  txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  zpu_core.vhd
+vcom -93 -explicit  dram_dmips.vhd
+vcom -93 -explicit  timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  trace.vhd
+
+
+vsim fpga_top
+view wave
+
+# run ZPU
+run 60000 ms
diff --git a/zpu/hdl/zpu4/src/fastdmipsintstack.do b/zpu/hdl/zpu4/src/fastdmipsintstack.do
new file mode 100644
index 0000000..ee9571e
--- /dev/null
+++ b/zpu/hdl/zpu4/src/fastdmipsintstack.do
@@ -0,0 +1,19 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config_fastsim.vhd
+vcom -93 -explicit  zpupkg.vhd
+vcom -93 -explicit  txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  zpu_core_intstack.vhd
+vcom -93 -explicit  dram_dmips.vhd
+vcom -93 -explicit  timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  trace.vhd
+
+
+vsim fpga_top
+view wave
+
+# run ZPU
+run 60000 ms
diff --git a/zpu/hdl/zpu4/src/fastdmipssmall.do b/zpu/hdl/zpu4/src/fastdmipssmall.do
new file mode 100644
index 0000000..3eaa083
--- /dev/null
+++ b/zpu/hdl/zpu4/src/fastdmipssmall.do
@@ -0,0 +1,21 @@
+set BreakOnAssertion 1
+vlib work
+
+
+vcom -93 -explicit  zpu_config_trace.vhd
+vcom -93 -explicit  zpupkg.vhd
+vcom -93 -explicit  txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  zpu_core_small.vhd
+vcom -93 -explicit  bram_dmips.vhd
+vcom -93 -explicit  dram_dmips.vhd
+vcom -93 -explicit  timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  trace.vhd
+
+
+vsim fpga_top
+view wave
+
+# run ZPU
+run 60000 ms
diff --git a/zpu/hdl/zpu4/src/fastsimzpu.do b/zpu/hdl/zpu4/src/fastsimzpu.do
new file mode 100644
index 0000000..504bf60
--- /dev/null
+++ b/zpu/hdl/zpu4/src/fastsimzpu.do
@@ -0,0 +1,19 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config_fastsim.vhd
+vcom -93 -explicit  zpupkg.vhd
+vcom -93 -explicit  txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  zpu_core.vhd
+vcom -93 -explicit  dram_dmips.vhd
+vcom -93 -explicit  timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  trace.vhd
+
+
+vsim fpga_top
+view wave
+
+# run ZPU
+run 60000 ms
diff --git a/zpu/hdl/zpu4/src/ic300.bitgen b/zpu/hdl/zpu4/src/ic300.bitgen
new file mode 100644
index 0000000..1095099
--- /dev/null
+++ b/zpu/hdl/zpu4/src/ic300.bitgen
@@ -0,0 +1,27 @@
+-g DebugBitstream:No
+-g Binary:yes
+-g CRC:Enable
+-g ConfigRate:50
+-g CclkPin:Pullnone
+-g M0Pin:Pullnone
+-g M1Pin:Pullnone
+-g M2Pin:Pullnone
+-g ProgPin:PullUp
+-g DonePin:Pullnone
+-g TckPin:Pullnone
+-g TdiPin:Pullnone
+-g TdoPin:Pullnone
+-g TmsPin:Pullnone
+-g UnusedPin:Pullnone
+-g UserID:0xFFFFFFFF
+-g DCMShutDown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:Level1
+-g DonePipe:No
+-g DriveDone:Yes
+
diff --git a/zpu/hdl/zpu4/src/ic300.lso b/zpu/hdl/zpu4/src/ic300.lso
new file mode 100644
index 0000000..22de730
--- /dev/null
+++ b/zpu/hdl/zpu4/src/ic300.lso
@@ -0,0 +1 @@
+work
diff --git a/zpu/hdl/zpu4/src/ic300.ucf b/zpu/hdl/zpu4/src/ic300.ucf
new file mode 100644
index 0000000..4a141b9
--- /dev/null
+++ b/zpu/hdl/zpu4/src/ic300.ucf
@@ -0,0 +1,146 @@
+# clock inputs
+net "cpu_clk_p" loc = "R9" | iostandard=LVTTL;
+
+# input pins
+net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL;
+net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL;
+net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL;
+net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL;
+net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL;
+net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL;
+net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL;
+net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL;
+net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL;
+net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL;
+net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL;
+net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL;
+net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL;
+net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL;
+net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL;
+net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL;
+net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL;
+net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL;
+net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL;
+net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL;
+net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL;
+net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL;
+net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL;
+net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL;
+net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL;
+net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL;
+net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL;
+
+#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I;
+
+# output pins
+net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL;
+net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL;
+net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL;
+net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL;
+
+#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST;
+#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST;
+#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST;
+#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP;
+#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
+#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
+#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY;
+#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST;
+#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST;
+#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST;
+#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST;
+#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST;
+#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST;
+#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST;
+
+# bidirectional pins
+net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL;
+net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL;
+net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL;
+net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL;
+net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL;
+net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL;
+net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL;
+net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL;
+net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL;
+net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL;
+net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL;
+net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL;
+net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL;
+net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL;
+net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL;
+net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL;
+
+#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST;
+#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST;
+
+# TIMING
+# Create timing names
+NET "cpu_clk_p" TNM_NET = "cpu_clk_p";
+NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p";
+#NET "cpu_clk" TNM_NET = "cpu_clk";
+#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x";
+#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x";
+#NET "ddr_in_clk" TNM_NET = "ddr_in_clk";
+#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x";
+
+## Create timing
+
+# Periode timing
+TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 10 ns HIGH 50 %;
+#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %;
+
+# Clock domain crossing timing
+#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns;
+#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns;
+#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns;
+#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns;
+
+#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns;
+#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns;
+#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns;
+#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns;
+
+#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns;
+#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns;
+#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns;
+#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns;
+
+#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns;
+#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns;
+#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns;
+#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns;
+
+#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns;
+#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns;
+#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns;
+#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns;
+
+
+
diff --git a/zpu/hdl/zpu4/src/ic300.vhd b/zpu/hdl/zpu4/src/ic300.vhd
new file mode 100644
index 0000000..a1b4f41
--- /dev/null
+++ b/zpu/hdl/zpu4/src/ic300.vhd
@@ -0,0 +1,144 @@
+--------------------------------------------------------------------------------
+-- Company: Zylin AS
+-- Engineer: Tore Ramsland
+--
+-- Create Date:    21:47:41 07/03/05
+-- Design Name:    ic300
+-- Module Name:    ic300 - behave
+-- Project Name:   eCosBoard
+-- Target Device:  XC3S400400-FG256
+-- Tool versions:  7.1i
+-- Description:	   Top level
+--
+-- Dependencies:
+-- 
+-- Revision:
+--	2005-07-11	Updated to test FPGA
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library zylin;
+use zylin.arm7.all;
+
+library zylin;
+use zylin.zpu_config.all;
+use zylin.zpupkg.all;
+
+library work;
+use work.phi_config.all;
+use work.ic300pkg.all;
+
+entity ic300 is
+	generic(
+			simulate_io_time	: boolean := false);
+	port (	-- Clock inputs
+			cpu_clk_p		: in std_logic;
+			
+			-- CPU interface signals
+			cpu_a_p			: in std_logic_vector(20 downto 0);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_irq_p		: out std_logic_vector(1 downto 0);
+			cpu_fiq_p		: out std_logic;
+			cpu_wait_n_p	: out std_logic;
+			
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0); 			-- bidir data bus
+		    sdr_clk_fb_p	: in std_logic		-- DDR clock feedback
+		);
+end ic300;
+
+architecture behave of ic300 is
+
+signal	cpu_we				: std_logic_vector(1 downto 0);			-- Write signal for lower(0) and upper(1) 8 data bits
+signal	cpu_re				: std_logic;							-- Read enable signal for all 16 bits
+signal	areset				: std_logic;							-- Asyncronous active high reset (for initialization)
+signal	areset_dummy		: std_logic;
+
+-- Clock module signals
+signal	clk_status			: std_logic_vector(2 downto 0);			-- DLL lock status (from 3 DLL's)
+signal	cpu_clk				: std_logic;							-- 64 MHz CPU clk
+signal	cpu_clk_2x			: std_logic;							-- 128 MHz CPU clk (in phase with 64 MHz)
+signal	cpu_clk_4x			: std_logic;							-- 256 MHz CPU clk (in phase with 64 MHz)
+signal	ddr_in_clk			: std_logic;							-- 128 MHz clock from DDR SDRAM
+signal	ddr_in_clk_2x		: std_logic;							-- 256 MHz clock from DDR SDRAM
+																	-- NOTE! Phase relation to 64 MHz clock unknown
+
+-- Internal CPU interface signals
+signal	cpu_din				: std_logic_vector(15 downto 0);		-- 16-bit data from CPU
+signal	cpu_dout			: std_logic_vector(15 downto 0);		-- 16-bit data to CPU
+signal	cpu_a				: std_logic_vector(20 downto 0);		-- 21-bit address from CPU
+
+begin
+
+--	areset <= '0';
+	areset_dummy <= '0';
+
+	global_init_reset:
+	rocbuf port map(I=>areset_dummy,O=>areset);
+
+	allclocks:
+	clocks port map(
+		areset => areset,
+		cpu_clk_p => cpu_clk_p,
+		cpu_clk => cpu_clk,
+		cpu_clk_2x => cpu_clk_2x,
+		cpu_clk_4x => cpu_clk_4x,
+		sdr_clk_fb_p => sdr_clk_fb_p,
+		ddr_in_clk => ddr_in_clk,
+		ddr_in_clk_2x => ddr_in_clk_2x,
+		locked => clk_status);
+
+	arm7cpu:
+	arm7wb generic map (simulate_io_time => simulate_io_time)
+	port map(
+		areset => areset,
+		cpu_clk => cpu_clk,
+		cpu_clk_2x => cpu_clk_2x,
+		cpu_a_p => cpu_a_p,
+		cpu_wr_n_p => cpu_wr_n_p,
+		cpu_cs_n_p => cpu_cs_n_p,
+		cpu_oe_n_p => cpu_oe_n_p,
+		cpu_d_p => cpu_d_p,
+		cpu_irq_p => cpu_irq_p,
+		cpu_fiq_p => cpu_fiq_p,
+		cpu_wait_n_p => cpu_wait_n_p,
+		cpu_din => cpu_din,
+		cpu_a => cpu_a,
+		cpu_we => cpu_we,
+		cpu_re => cpu_re,
+		cpu_dout => cpu_dout);
+		
+		
+	cpu_fpga_regs:
+	zpuio port map(
+		areset => areset,
+		cpu_clk => cpu_clk,
+		clk_status => clk_status,
+		cpu_din => cpu_din,
+		cpu_a => cpu_a,
+		cpu_we => cpu_we,
+		cpu_re => cpu_re,
+		cpu_dout => cpu_dout);
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/src/ic300_config.vhd b/zpu/hdl/zpu4/src/ic300_config.vhd
new file mode 100644
index 0000000..b14ec79
--- /dev/null
+++ b/zpu/hdl/zpu4/src/ic300_config.vhd
@@ -0,0 +1,26 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package phi_config is
+
+	constant		Fpga_Global_Base		: std_logic_vector(19 downto 17) 	:= "000";		-- 0x0800....
+		constant	Clock_Stat_Reg_Addr		: std_logic_vector(5 downto 2)		:= "0000";		-- 0x....0000
+		constant	Ctrl_Reg_Addr			: std_logic_vector(5 downto 2)		:= "0001";		-- 0x....0004
+		constant	output_enable			: std_logic_vector(5 downto 2)		:= "0010";		-- 0x....0008
+		constant	output_disable			: std_logic_vector(5 downto 2)		:= "0011";		-- 0x....000C
+		constant	data_status				: std_logic_vector(5 downto 2)		:= "0100";		-- 0x....0010
+		constant	set_output_data			: std_logic_vector(5 downto 2)		:= "0101";		-- 0x....0014
+		constant	clear_output_data		: std_logic_vector(5 downto 2)		:= "0110";		-- 0x....0018
+		constant	data_in_read			: std_logic_vector(5 downto 2)		:= "0111";		-- 0x....001C
+		constant	output_status			: std_logic_vector(5 downto 2)		:= "1000";		-- 0x....0020
+		constant	cpu_access_address		: std_logic_vector(5 downto 2)		:= "1001";		-- 0x....0024
+				
+	constant		Fpga_Ethernet_Reg_Base 	: std_logic_vector(19 downto 17) 	:= "110";		-- 0x080C0000
+
+	constant		Fpga_DDR_Ctrl_Base		: std_logic_vector(19 downto 17)	:= "111";		-- 0x080E....
+		constant	DDR_Ctrl_Reg_Addr		: std_logic_vector(3 downto 2)		:= "00";		-- 0x....0000
+		constant	DDR_Mode_Reg_Addr		: std_logic_vector(3 downto 2)		:= "01";		-- 0x....0004
+		constant	DDR_Page_Select_Addr	: std_logic_vector(3 downto 2)		:= "10";		-- 0x....0008
+		
+	
+end phi_config;
diff --git a/zpu/hdl/zpu4/src/ic300pkg.vhd b/zpu/hdl/zpu4/src/ic300pkg.vhd
new file mode 100644
index 0000000..13da306
--- /dev/null
+++ b/zpu/hdl/zpu4/src/ic300pkg.vhd
@@ -0,0 +1,88 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package ic300pkg is
+
+	component ic300 is
+	port (	-- Clock inputs
+			cpu_clk_p		: in std_logic;
+			
+			-- CPU interface signals
+			cpu_a_p			: in std_logic_vector(20 downto 0);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: inout std_logic_vector(15 downto 0);
+			cpu_irq_p		: out std_logic_vector(1 downto 0);
+			cpu_fiq_p		: out std_logic;
+			cpu_wait_n_p	: out std_logic;
+			
+		    -- DDR SDRAM Signals
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0); 			-- bidir data bus
+		    sdr_clk_fb_p	: in std_logic		-- DDR clock feedback
+		);
+	end component;
+
+	component clocks is
+	port (	areset			: in std_logic;
+			cpu_clk_p		: in std_logic;
+			sdr_clk_fb_p	: in std_logic;
+			cpu_clk			: out std_logic;
+			cpu_clk_2x		: out std_logic;
+			cpu_clk_4x		: out std_logic;
+			ddr_in_clk		: out std_logic;
+			ddr_in_clk_2x	: out std_logic;
+			locked			: out std_logic_vector(2 downto 0));
+	end component;
+
+	component cpu_regs is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			clk_status		: in std_logic_vector(2 downto 0);
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_dout		: inout std_logic_vector(15 downto 0));
+	end component;
+
+	component ddr_bridge is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			cpu_clk_2x		: in std_logic;
+			cpu_clk_4x		: in std_logic;
+			ddr_in_clk		: in std_logic;
+			ddr_in_clk_2x	: in std_logic;
+
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_dout		: inout std_logic_vector(15 downto 0);
+			
+		    sdr_clk_p       : out std_logic;    -- ddr_sdram_clock
+		    sdr_clk_n_p     : out std_logic;    -- /ddr_sdram_clock
+		    cke_q_p         : out std_logic;    -- clock enable
+		    cs_qn_p         : out std_logic;    -- /chip select
+		    ras_qn_p        : inout std_logic;    -- /ras
+		    cas_qn_p        : inout std_logic;    -- /cas
+		    we_qn_p         : inout std_logic;    -- /write enable
+		    dm_q_p          : out std_logic_vector(1 downto 0);     -- data mask bits, set to "00"
+		    dqs_q_p         : out std_logic_vector(1 downto 0);    -- data strobe, only for write
+		    ba_q_p          : out std_logic_vector(1 downto 0);   -- bank select
+		    sdr_a_p		    : out std_logic_vector(12 downto 0);   -- address bus 
+		    sdr_d_p         : inout std_logic_vector(15 downto 0)); 			-- bidir data bus
+	end component;
+	
+end ic300pkg;
diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd
new file mode 100644
index 0000000..b5465d1
--- /dev/null
+++ b/zpu/hdl/zpu4/src/io.vhd
@@ -0,0 +1,92 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+ 
+entity  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(7 downto 0);
+		read	: out std_logic_vector(7 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end zpu_io;
+   
+   
+architecture behave of zpu_io is
+
+
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+signal serving : std_logic;
+
+file 		l_file		: TEXT open write_mode is log_file;
+
+begin
+
+	
+	timerinst: timer port map (
+       clk => clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => write,
+		 adr => addr(4 downto 2),
+		 dout => timer_read);
+	
+	busy <= writeEnable or readEnable;
+	timer_we <= writeEnable and addr(12);
+	
+	process(areset, clk)
+	begin
+		if (areset = '1') then
+--			timer_we <= '0';
+		elsif (clk'event and clk = '1') then
+--			timer_we <= '0';
+			if writeEnable = '1' then
+				-- external interface
+				if addr=x"1000" then
+					-- Write to UART
+					-- report "" & character'image(conv_integer(memBint)) severity note;
+				    print(l_file, character'val(conv_integer(write)));
+				elsif addr(12)='1' then
+--				    report "xxx" severity failure;
+-- 					timer_we <= '1';
+				else
+					report "Illegal IO write" severity failure;
+				end if;
+				
+			end if;
+			read <= (others => 'U');
+			if (readEnable = '1') then
+				if addr=x"1001" then
+					read <= (0=>'1', others => '0'); -- recieve empty
+ 				elsif addr(12)='1' then
+ 					read <= timer_read;
+ 				elsif addr(11)='1' then
+ 					read <= ZPU_Frequency;
+				else
+					report "Illegal IO read" severity failure;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt
new file mode 100644
index 0000000..af58c93
--- /dev/null
+++ b/zpu/hdl/zpu4/src/log.txt
@@ -0,0 +1,380 @@
+H
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+ 
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+ 
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+ 
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+ 
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+ 
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+ 
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+ 
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+ 
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+ 
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+ 
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+ 
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+ 
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+ 
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+ 
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+
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+
+H
+e
+l
+l
+o
+ 
+w
+o
+r
+l
+d
+ 
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+
+
+
+
+
+
+H
+e
+l
+l
+o
+ 
+w
+o
+r
+l
+d
+ 
+2
+
+
+
+
+
+
diff --git a/zpu/hdl/zpu4/src/niltrace.vhd b/zpu/hdl/zpu4/src/niltrace.vhd
new file mode 100644
index 0000000..40fc1ca
--- /dev/null
+++ b/zpu/hdl/zpu4/src/niltrace.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+use work.zpu_config.all;
+ 
+ 
+entity trace is
+  port(
+       	clk         : in std_logic;
+       	begin_inst  : in std_logic;
+       	pc          : in std_logic_vector(maxAddrBit downto 0);
+		opcode		: in std_logic_vector(7 downto 0);
+		sp			: in std_logic_vector(maxAddrBit downto 2);
+		memA		: in std_logic_vector(wordSize-1 downto 0);
+		busy  : in std_logic);
+end trace;
+   
+   
+architecture behave of trace is
+  
+begin
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd
new file mode 100644
index 0000000..2905505
--- /dev/null
+++ b/zpu/hdl/zpu4/src/sim_fpga_top.vhd
@@ -0,0 +1,190 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    20:15:31 04/14/05
+-- Design Name:    
+-- Module Name:    fpga_top - behave
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity fpga_top is
+end fpga_top;
+
+architecture behave of fpga_top is
+
+
+signal clk : std_logic;
+
+signal	areset			: std_logic;
+
+
+component  zpu_io is
+  generic (
+           log_file:       string  := "log.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	areset        : in std_logic;
+		busy : out std_logic;
+		writeEnable : in std_logic;
+		readEnable : in std_logic;
+		write	: in std_logic_vector(7 downto 0);
+		read	: out std_logic_vector(7 downto 0);
+		addr : in std_logic_vector(maxAddrBit downto minAddrBit)
+		);
+end component;
+
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  enable : std_logic;
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+signal	 		  io_busy : std_logic;
+
+signal			  io_mem_read : std_logic_vector(7 downto 0);
+signal			  io_mem_writeEnable : std_logic; 
+signal			  io_mem_readEnable : std_logic;
+
+
+signal			  dram_ready : std_logic;
+signal			  io_ready : std_logic;
+signal			  io_reading : std_logic;
+
+
+signal break : std_logic;
+
+begin
+	poweronreset: roc port map (O => areset);
+
+
+
+	zpu: zpu_core port map (
+		clk => clk ,
+	 	areset => areset,
+	 	enable => enable,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+	dram_imp: dram port map (
+		clk => clk ,
+		areset => areset,
+ 		mem_busy => dram_mem_busy, 
+ 		mem_read => dram_mem_read,
+ 		mem_write => mem_write, 
+		mem_addr => mem_addr(maxAddrBit downto 0), 
+		mem_writeEnable => dram_mem_writeEnable,  
+		mem_readEnable => dram_mem_readEnable,
+ 		mem_writeMask => mem_writeMask);
+
+
+	ioMap: zpu_io port map (
+       	clk => clk,
+	 	areset => areset,
+		busy => io_busy,
+		writeEnable => io_mem_writeEnable,
+		readEnable => io_mem_readEnable,
+		write	=> mem_write(7 downto 0),
+		read	=> io_mem_read,
+		addr => mem_addr(maxAddrBit downto minAddrBit)
+	);
+
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+	io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy or dram_mem_busy or io_busy;
+	
+	
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(dram_mem_read, dram_ready, io_ready, io_mem_read)
+	begin
+		mem_read <= (others => 'U');
+		if dram_ready='1' then
+			mem_read <= dram_mem_read;
+		end if;
+			 
+		if io_ready='1' then
+			mem_read <= (others => '0');
+			mem_read(7 downto 0) <= io_mem_read;
+		end if;
+	end process;
+
+	
+	io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
+
+	memoryControlSync:
+	process(clk, areset)
+	begin
+		if areset = '1' then
+			enable <= '0';
+			io_reading <= '0';
+			dram_ready <= '0';
+		elsif (clk'event and clk = '1') then
+			enable <= '1';
+			io_reading <= io_busy or io_mem_readEnable; 
+			dram_ready<=dram_mem_readEnable;
+			
+		end if;
+	end process;
+
+	-- wiggle the clock @ 100MHz
+	clock : PROCESS
+	   begin
+   			clk <= '0';
+		   wait for 5 ns; 
+   			clk <= '1';
+		   wait for 5 ns; 
+	end PROCESS clock;
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/src/simzpu.do b/zpu/hdl/zpu4/src/simzpu.do
new file mode 100644
index 0000000..e6e3068
--- /dev/null
+++ b/zpu/hdl/zpu4/src/simzpu.do
@@ -0,0 +1,23 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config.vhd
+vcom -93 -explicit  zpupkg.vhd
+vcom -93 -explicit  txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  zpu_core.vhd
+vcom -93 -explicit  dram.vhd
+vcom -93 -explicit  timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 1000 ms
diff --git a/zpu/hdl/zpu4/src/simzpu_intstack.do b/zpu/hdl/zpu4/src/simzpu_intstack.do
new file mode 100644
index 0000000..cec4873
--- /dev/null
+++ b/zpu/hdl/zpu4/src/simzpu_intstack.do
@@ -0,0 +1,23 @@
+set BreakOnAssertion 1
+vlib work
+
+vcom -93 -explicit  zpu_config_trace.vhd
+vcom -93 -explicit  zpupkg.vhd
+vcom -93 -explicit  txt_util.vhd
+vcom -93 -explicit  sim_fpga_top.vhd
+vcom -93 -explicit  zpu_core_intstack.vhd
+vcom -93 -explicit  dram_hello.vhd
+vcom -93 -explicit  timer.vhd
+vcom -93 -explicit  io.vhd
+vcom -93 -explicit  trace.vhd
+
+# run ZPU
+vsim fpga_top
+view wave
+add wave -recursive fpga_top/zpu/*
+#add wave -recursive fpga_top/*
+view structure
+#view signals
+
+# Enough to run tiny programs
+run 15 ms
diff --git a/zpu/hdl/zpu4/src/status.txt b/zpu/hdl/zpu4/src/status.txt
new file mode 100644
index 0000000..df01caf
--- /dev/null
+++ b/zpu/hdl/zpu4/src/status.txt
@@ -0,0 +1,109 @@
+- Before NEQBRANCH opt 4.684 DMIPS 8.0 cycles average, after 
+- opcode pairs
+
+0x6060 0.1519223038446077 75961 9.048362120309708 LOADSP + LOADSP
+0x4040 0.13967027934055867 69835 11.08668042546436 STORESP + STORESP
+0x8038 0.10230620461240922 51153 10.251102204408818 IM + NEQBRANCH
+0x4060 0.09856219712439425 49281 9.822802471596571 STORESP + LOADSP
+0x6080 0.09734219468438937 48671 6.483415478886373 LOADSP + IM
+0x3860 0.08642217284434568 43211 12.616350364963504 NEQBRANCH + LOADSP
+0x8080 0.060966121932243864 30483 4.275915275634731 IM + IM 
+0x8005 0.05317010634021268 26585 6.572311495673671 IM + ADD
+0x540 0.05215210430420861 26076 9.339541547277937 ADD + STORESP
+0x3d0d 0.050808101616203236 25404 12.398243045387995 
+0xd04 0.0466000932001864 23300 20.0
+0x6040 0.04389608779217558 21948 9.460344827586207
+0x4080 0.043648087296174594 21824 7.630769230769231
+0xc80 0.03966807933615867 19834 11.438292964244521
+0x8010 0.0391500783001566 19575 6.1248435544430535
+0x480 0.038798077596155195 19399 10.941342357586013
+
+
+- zpu_core.vhd: 1500 LUTs. Xilinx ISE reports 83MHz maximum frequency after P&R
+  which matches what I've found w/my ic300.vhd testbench
+
+- zpu_core_instack.vhd
+  - problems w/simulation trace since storeb/loadb will run into undefined memory
+    during emulation. Solution: implement loadb+storeb.
+  - simulation needs to read cycles from ModelSim trace so as to m ake readcycles 
+    not cause false positives. This has other interesting potentials w.r.t.
+    knowing which instructions take the longest.
+
+- Ca. 1700 LUT inc. all instructions. Removing all higher level instructions
+  => 1300.
+
+- Review memory interface
+  - When is mem_busy high? Will it be high on the next cycle after
+    I've send mem_read/writeEnable?
+  - Should I hold off posting a read/write until mem_busy = '0'?
+  - Write posting could increase performance somewhat. Should there be
+    a seperate write busy signal?
+  - Synchronous reset? The ARM7 will have to copy the program to DRAM and
+    then start the ZPU.
+
+- Current instruction set has  
+  - 31  DMIPS single cycle performance Simulator.java
+  - 8 DMIPS w/single cycle RAM access in ModelSim 
+
+112 0.06100380865858346 67215918
+56 0.04139603650830458 45611457
+129 0.0375812381475752 41408192
+5 0.03703417264799563 40805418
+113 0.03540341331682748 39008596
+128 0.0343154384313754 37809831
+83 0.03322159422742951 36604599
+114 0.03213492807203279 35407276
+132 0.03158580962697109 34802240
+12 0.03049709687915076 33602662
+8 0.029409690138646426 32404523
+115 0.026690690908727877 29408644
+46 0.025054316381406774 27605635
+82 0.023965804208719754 26406278
+84 0.023961360698074072 26401382
+116 0.023417718589457643 25802380
+81 0.02179306727026773 24012288
+117 0.021783900714401432 24002188
+4 0.01797685126990833 19807461
+6 0.016340292503890113 18004249
+85 0.016339001017850734 18002826
+255 0.016338918428089957 18002735
+86 0.016337281154151066 18000931
+11 0.011984767180825744 13205194
+51 0.0114390303780569 12603884
+38 0.010892246228211845 12001420
+118 0.010347263624247446 11400941
+131 0.009257503529350904 10200209
+7 0.008713386756504965 9600684
+22 0.008712946580307425 9600199
+
+
+64 0.16176824859336478 178241352
+96 0.23147927881894828 255051161
+128 0.2646966482624612 291651105
+
+
+- Alternate memory interface to allow more caching in memory subsystem?
+
+-- The memory interface allows a dual port memory to be used 
+-- to increase performance.
+-- 
+-- Also it is possible to implement a zero cycle register file instead
+-- of memory, though obviously that will cause problems w.r.t. max 
+-- frequency for the ZPU.
+--
+-- mem_writeEnable - set to '1' for a single cycle to send off a write request.
+--                   mem_write is valid only while mem_writeEnable='1'.
+-- mem_readEnable - set to '1' for a single cycle to send off a read request.
+--                  mem_read is a single cycle while mem_read_busy='0'.
+-- 
+-- mem_read/write_busy - It is illegal to send off a read/write request when mem_read/write_busy='1'.
+--            Set to '0' when mem_read  is valid after a read request. Note that
+--            the definition allows zero wait state ram.
+-- mem_read/write_addr - address for read/write request
+-- mem_read - read data. Valid only on the cycle after mem_busy='0' after 
+--            mem_readEnable='1' for a single cycle.
+-- mem_write - data to write
+-- mem_writeMask - set to '1' for those bits that are to be written to memory upon
+--                 write request
+-- break - set to '1' when CPU hits break instruction
+-- interrupt - set to '1' until interrupts are cleared by CPU. 
diff --git a/zpu/hdl/zpu4/src/testlut.vhd b/zpu/hdl/zpu4/src/testlut.vhd
new file mode 100644
index 0000000..668efcc
--- /dev/null
+++ b/zpu/hdl/zpu4/src/testlut.vhd
@@ -0,0 +1,114 @@
+-- Company: Zylin AS
+--
+-- Hooks up the ZPU to physical pads to ensure that it is not optimized to
+-- oblivion. This is purely to have something to measure LUT usage against.
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity ic300 is
+	port (	-- Clock inputs
+			cpu_clk_p		: in std_logic;
+			
+			-- CPU interface signals
+			cpu_a_p			: in std_logic_vector(20 downto 0);
+			cpu_wr_n_p		: in std_logic_vector(1 downto 0);
+			cpu_cs_n_p		: in std_logic_vector(3 downto 1);
+			cpu_oe_n_p		: in std_logic;
+			cpu_d_p			: out std_logic_vector(15 downto 0);
+			cpu_irq_p		: out std_logic_vector(1 downto 0);
+			cpu_fiq_p		: out std_logic;
+			cpu_wait_n_p	: out std_logic;
+			
+		    sdr_clk_fb_p	: in std_logic		-- DDR clock feedback
+		);
+end ic300;
+
+architecture behave of ic300 is
+
+
+signal io_busy : std_logic;
+signal io_read : std_logic_vector(7 downto 0);
+signal io_write : std_logic_vector(7 downto 0);
+signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal io_writeEnable : std_logic;
+signal io_readEnable : std_logic;
+
+
+signal	cpu_we				: std_logic_vector(1 downto 0);
+signal	cpu_re				: std_logic;
+signal	areset				: std_logic;
+
+-- Clock module signals
+signal	clk_status			: std_logic_vector(2 downto 0);
+signal	cpu_clk				: std_logic;
+signal	cpu_clk_2x			: std_logic;
+signal	cpu_clk_4x			: std_logic;
+signal	ddr_in_clk			: std_logic;
+
+
+-- Internal CPU interface signals
+signal	cpu_din				: std_logic_vector(15 downto 0);
+signal	cpu_dout			: std_logic_vector(15 downto 0);
+signal	cpu_a				: std_logic_vector(20 downto 0);
+
+signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5);
+
+signal dummy2 : std_logic_vector(wordSize-1 downto 0);
+signal dummy3 : std_logic_vector(wordSize-1 downto 0);
+signal dummy4 : std_logic_vector(wordSize-1 downto 0);
+begin
+
+	areset <= '0';	-- MUST BE CHANGED TO SOMETHING CORRECT
+	
+--	cpu_d_p <= (others => '0');
+	cpu_irq_p <= (others => '0');
+	cpu_fiq_p <= '0';
+	cpu_wait_n_p <= '0';
+
+	cpu_d_p(15 downto 15) <= (others => '0');
+
+	-- delay signals going out/in w/1 clk so the 
+	-- ZPU does not have to drive those pins. 
+	-- 
+	-- these registers can be placed close to the ZPU and these
+	-- registers then have a full clock to drive the pins.
+	process(cpu_clk_p, areset)
+	begin
+		if (cpu_clk_p'event and cpu_clk_p = '1') then
+			cpu_d_p(0) <= io_writeEnable;
+			cpu_d_p(1) <= io_readEnable;
+			cpu_d_p(9 downto 2) <= io_write;
+			io_read <= cpu_a_p(7 downto 0);
+			-- 32 read/write registers is plenty realisitic for a minimal size
+			-- soft-CPU
+			cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit);
+		end if;
+	end process;
+	
+
+	zpu: zpu_core port map (
+    	clk => cpu_clk_p ,
+	 	areset => areset,
+	 	enable => '1', 
+	 	
+		in_mem_busy => '0',
+		out_mem_writeEnable => io_writeEnable,
+		out_mem_readEnable => io_readEnable,
+		mem_write(7 downto 0)	=> io_write,
+		mem_write(wordSize-1 downto 8)	=> dummy3(wordSize-1 downto 8),
+		mem_read(7 downto 0)	=> io_read,
+		mem_read(wordSize-1 downto 8) => dummy2(wordSize-1 downto 8),
+		out_mem_addr(maxAddrBitIncIO) => dummy4(maxAddrBitIncIO),
+		out_mem_addr(minAddrBit-1 downto 0) => dummy4(minAddrBit-1 downto 0) ,
+		out_mem_addr(maxAddrBit downto minAddrBit) => io_addr,
+		interrupt => '0'
+	);
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd
new file mode 100644
index 0000000..60c8fe2
--- /dev/null
+++ b/zpu/hdl/zpu4/src/timer.vhd
@@ -0,0 +1,61 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+ 
+entity timer is
+  port(
+       clk              : in std_logic;
+		 areset				: in std_logic;
+		 we					: in std_logic;
+		 din					: in std_logic_vector(7 downto 0);
+		 adr					: in std_logic_vector(2 downto 0);
+		 dout					: out std_logic_vector(7 downto 0));
+end timer;
+   
+   
+architecture behave of timer is
+
+signal	sample	: std_logic;
+signal	reset		: std_logic;
+
+
+signal	cnt		: std_logic_vector(63 downto 0);
+signal	cnt_smp	: std_logic_vector(63 downto 0);
+
+begin
+
+	reset <= '1' when (we = '1' and din(0) = '1') else '0';
+	sample <= '1' when (we = '1' and din(1) = '1') else '0';
+
+	process(clk, areset)	-- Carry generation
+	begin
+		if areset = '1' then
+			cnt <= (others => '0');
+			cnt_smp <= (others => '0');
+		elsif (clk'event and clk = '1') then
+			cnt <= cnt + 1;
+			if sample = '1' then
+--				report "sampling" severity failure;
+				cnt_smp <= cnt;
+			end if;
+		end if;
+	end process;
+	
+	
+	process(cnt_smp, adr)
+	begin
+		case adr is
+			when "000"	=> dout <= cnt_smp(7 downto 0);
+			when "001"	=> dout <= cnt_smp(15 downto 8);
+			when "010"	=> dout <= cnt_smp(23 downto 16);
+			when "011"	=> dout <= cnt_smp(31 downto 24);
+			when "100"	=> dout <= cnt_smp(39 downto 32);
+			when "101"	=> dout <= cnt_smp(47 downto 40);
+			when "110"	=> dout <= cnt_smp(55 downto 48);
+			when others	=> dout <= cnt_smp(63 downto 56);
+		end case;
+	end process;
+	
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd
new file mode 100644
index 0000000..bc5279f
--- /dev/null
+++ b/zpu/hdl/zpu4/src/trace.vhd
@@ -0,0 +1,84 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use std.textio.all;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+use work.txt_util.all;
+ 
+ 
+entity trace is
+  generic (
+           log_file:       string  := "trace.txt"
+          );
+  port(
+       	clk         : in std_logic;
+       	begin_inst  : in std_logic;
+       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
+		opcode		: in std_logic_vector(7 downto 0);
+		sp			: in std_logic_vector(maxAddrBitIncIO downto 2);
+		memA		: in std_logic_vector(wordSize-1 downto 0);
+		memB		: in std_logic_vector(wordSize-1 downto 0);
+		busy  : in std_logic;
+		intSp		: in std_logic_vector(stack_bits-1 downto 0)
+		);
+end trace;
+   
+   
+architecture behave of trace is
+  
+  
+file 		l_file		: TEXT open write_mode is log_file;
+
+
+begin
+
+
+-- write data and control information to a file
+
+receive_data: process
+
+variable l: line;
+variable t	: std_logic_vector(wordSize-1 downto 0);
+variable t2	: std_logic_vector(maxAddrBitIncIO downto 0);
+variable counter : std_logic_vector(63 downto 0);
+   
+   
+   
+begin                                       
+
+	t:= (others => '0');
+	t2:= (others => '0');
+
+counter := (others => '0');
+   -- print header for the logfile
+   print(l_file, "#pc,opcode,sp,top_of_stack ");
+   print(l_file, "#----------");
+   print(l_file, " ");
+
+	wait until clk = '1';
+	wait until clk = '0'; 
+
+   while true loop
+
+		counter := counter + 1;
+		if begin_inst = '1' then
+			t(maxAddrBitIncIO downto 2):=sp;
+			t2:=pc;
+     		print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter));
+		end if;
+		
+     	wait until clk = '0';
+    
+   end loop;
+
+ end process receive_data;
+
+
+
+end behave;
+ 
diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd
new file mode 100644
index 0000000..d3bf01a
--- /dev/null
+++ b/zpu/hdl/zpu4/src/txt_util.vhd
@@ -0,0 +1,587 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+
+library work;
+
+package txt_util is
+
+    -- prints a message to the screen
+    procedure print(text: string);
+
+    -- prints the message when active
+    -- useful for debug switches
+    procedure print(active: boolean; text: string);
+
+    -- converts std_logic into a character
+    function chr(sl: std_logic) return character;
+
+    -- converts std_logic into a string (1 to 1)
+    function str(sl: std_logic) return string;
+
+    -- converts std_logic_vector into a string (binary base)
+    function str(slv: std_logic_vector) return string;
+
+    -- converts boolean into a string
+    function str(b: boolean) return string;
+
+    -- converts an integer into a single character
+    -- (can also be used for hex conversion and other bases)
+    function chr(int: integer) return character;
+
+    -- converts integer into string using specified base
+    function str(int: integer; base: integer) return string;
+
+    -- converts integer to string, using base 10
+    function str(int: integer) return string;
+
+    -- convert std_logic_vector into a string in hex format
+    function hstr(slv: std_logic_vector) return string;
+
+
+    -- functions to manipulate strings
+    -----------------------------------
+
+    -- convert a character to upper case
+    function to_upper(c: character) return character;
+
+    -- convert a character to lower case
+    function to_lower(c: character) return character;
+
+    -- convert a string to upper case
+    function to_upper(s: string) return string;
+
+    -- convert a string to lower case
+    function to_lower(s: string) return string;
+
+   
+    
+    -- functions to convert strings into other formats
+    --------------------------------------------------
+    
+    -- converts a character into std_logic
+    function to_std_logic(c: character) return std_logic; 
+    
+    -- converts a string into std_logic_vector
+    function to_std_logic_vector(s: string) return std_logic_vector; 
+
+
+  
+    -- file I/O
+    -----------
+       
+    -- read variable length string from input file
+    procedure str_read(file in_file: TEXT; 
+                       res_string: out string);
+        
+    -- print string to a file and start new line
+    procedure print(file out_file: TEXT;
+                    new_string: in  string);
+    
+    -- print character to a file and start new line
+    procedure print(file out_file: TEXT;
+                    char:       in  character);
+                    
+end txt_util;
+
+
+
+
+package body txt_util is
+
+
+
+
+   -- prints text to the screen
+
+   procedure print(text: string) is
+     variable msg_line: line;
+     begin
+       write(msg_line, text);
+       writeline(output, msg_line);
+   end print;
+
+
+
+
+   -- prints text to the screen when active
+
+   procedure print(active: boolean; text: string)  is
+     begin
+      if active then
+         print(text);
+      end if;
+   end print;
+
+
+   -- converts std_logic into a character
+
+   function chr(sl: std_logic) return character is
+    variable c: character;
+    begin
+      case sl is
+         when 'U' => c:= 'U';
+         when 'X' => c:= 'X';
+         when '0' => c:= '0';
+         when '1' => c:= '1';
+         when 'Z' => c:= 'Z';
+         when 'W' => c:= 'W';
+         when 'L' => c:= 'L';
+         when 'H' => c:= 'H';
+         when '-' => c:= '-';
+      end case;
+    return c;
+   end chr;
+
+
+
+   -- converts std_logic into a string (1 to 1)
+
+   function str(sl: std_logic) return string is
+    variable s: string(1 to 1);
+    begin
+        s(1) := chr(sl);
+        return s;
+   end str;
+
+
+
+   -- converts std_logic_vector into a string (binary base)
+   -- (this also takes care of the fact that the range of
+   --  a string is natural while a std_logic_vector may
+   --  have an integer range)
+
+   function str(slv: std_logic_vector) return string is
+     variable result : string (1 to slv'length);
+     variable r : integer;
+   begin
+     r := 1;
+     for i in slv'range loop
+        result(r) := chr(slv(i));
+        r := r + 1;
+     end loop;
+     return result;
+   end str;
+
+
+   function str(b: boolean) return string is
+
+    begin
+       if b then
+          return "true";
+      else
+        return "false";
+       end if;
+    end str;
+
+
+   -- converts an integer into a character
+   -- for 0 to 9 the obvious mapping is used, higher
+   -- values are mapped to the characters A-Z
+   -- (this is usefull for systems with base > 10)
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function chr(int: integer) return character is
+    variable c: character;
+   begin
+        case int is
+          when  0 => c := '0';
+          when  1 => c := '1';
+          when  2 => c := '2';
+          when  3 => c := '3';
+          when  4 => c := '4';
+          when  5 => c := '5';
+          when  6 => c := '6';
+          when  7 => c := '7';
+          when  8 => c := '8';
+          when  9 => c := '9';
+          when 10 => c := 'A';
+          when 11 => c := 'B';
+          when 12 => c := 'C';
+          when 13 => c := 'D';
+          when 14 => c := 'E';
+          when 15 => c := 'F';
+          when 16 => c := 'G';
+          when 17 => c := 'H';
+          when 18 => c := 'I';
+          when 19 => c := 'J';
+          when 20 => c := 'K';
+          when 21 => c := 'L';
+          when 22 => c := 'M';
+          when 23 => c := 'N';
+          when 24 => c := 'O';
+          when 25 => c := 'P';
+          when 26 => c := 'Q';
+          when 27 => c := 'R';
+          when 28 => c := 'S';
+          when 29 => c := 'T';
+          when 30 => c := 'U';
+          when 31 => c := 'V';
+          when 32 => c := 'W';
+          when 33 => c := 'X';
+          when 34 => c := 'Y';
+          when 35 => c := 'Z';
+          when others => c := '?';
+        end case;
+        return c;
+    end chr;
+
+
+
+   -- convert integer to string using specified base
+   -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
+
+   function str(int: integer; base: integer) return string is
+
+    variable temp:      string(1 to 10);
+    variable num:       integer;
+    variable abs_int:   integer;
+    variable len:       integer := 1;
+    variable power:     integer := 1;
+
+   begin
+
+    -- bug fix for negative numbers
+    abs_int := abs(int);
+
+    num     := abs_int;
+
+    while num >= base loop                     -- Determine how many
+      len := len + 1;                          -- characters required
+      num := num / base;                       -- to represent the
+    end loop ;                                 -- number.
+
+    for i in len downto 1 loop                 -- Convert the number to
+      temp(i) := chr(abs_int/power mod base);  -- a string starting
+      power := power * base;                   -- with the right hand
+    end loop ;                                 -- side.
+
+    -- return result and add sign if required
+    if int < 0 then
+       return '-'& temp(1 to len);
+     else
+       return temp(1 to len);
+    end if;
+
+   end str;
+
+
+  -- convert integer to string, using base 10
+  function str(int: integer) return string is
+
+   begin
+
+    return str(int, 10) ;
+
+   end str;
+
+
+
+   -- converts a std_logic_vector into a hex string.
+   function hstr(slv: std_logic_vector) return string is
+       variable hexlen: integer;
+       variable longslv : std_logic_vector(67 downto 0) := (others => '0');
+       variable hex : string(1 to 16);
+       variable fourbit : std_logic_vector(3 downto 0);
+     begin
+       hexlen := (slv'left+1)/4;
+       if (slv'left+1) mod 4 /= 0 then
+         hexlen := hexlen + 1;
+       end if;
+       longslv(slv'left downto 0) := slv;
+       for i in (hexlen -1) downto 0 loop
+         fourbit := longslv(((i*4)+3) downto (i*4));
+         case fourbit is
+           when "0000" => hex(hexlen -I) := '0';
+           when "0001" => hex(hexlen -I) := '1';
+           when "0010" => hex(hexlen -I) := '2';
+           when "0011" => hex(hexlen -I) := '3';
+           when "0100" => hex(hexlen -I) := '4';
+           when "0101" => hex(hexlen -I) := '5';
+           when "0110" => hex(hexlen -I) := '6';
+           when "0111" => hex(hexlen -I) := '7';
+           when "1000" => hex(hexlen -I) := '8';
+           when "1001" => hex(hexlen -I) := '9';
+           when "1010" => hex(hexlen -I) := 'A';
+           when "1011" => hex(hexlen -I) := 'B';
+           when "1100" => hex(hexlen -I) := 'C';
+           when "1101" => hex(hexlen -I) := 'D';
+           when "1110" => hex(hexlen -I) := 'E';
+           when "1111" => hex(hexlen -I) := 'F';
+           when "ZZZZ" => hex(hexlen -I) := 'z';
+           when "UUUU" => hex(hexlen -I) := 'u';
+           when "XXXX" => hex(hexlen -I) := 'x';
+           when others => hex(hexlen -I) := '?';
+         end case;
+       end loop;
+       return hex(1 to hexlen);
+     end hstr;
+
+
+
+   -- functions to manipulate strings
+   -----------------------------------
+
+
+   -- convert a character to upper case
+
+   function to_upper(c: character) return character is
+
+      variable u: character;
+
+    begin
+
+       case c is
+        when 'a' => u := 'A';
+        when 'b' => u := 'B';
+        when 'c' => u := 'C';
+        when 'd' => u := 'D';
+        when 'e' => u := 'E';
+        when 'f' => u := 'F';
+        when 'g' => u := 'G';
+        when 'h' => u := 'H';
+        when 'i' => u := 'I';
+        when 'j' => u := 'J';
+        when 'k' => u := 'K';
+        when 'l' => u := 'L';
+        when 'm' => u := 'M';
+        when 'n' => u := 'N';
+        when 'o' => u := 'O';
+        when 'p' => u := 'P';
+        when 'q' => u := 'Q';
+        when 'r' => u := 'R';
+        when 's' => u := 'S';
+        when 't' => u := 'T';
+        when 'u' => u := 'U';
+        when 'v' => u := 'V';
+        when 'w' => u := 'W';
+        when 'x' => u := 'X';
+        when 'y' => u := 'Y';
+        when 'z' => u := 'Z';
+        when others => u := c;
+    end case;
+
+      return u;
+
+   end to_upper;
+
+
+   -- convert a character to lower case
+
+   function to_lower(c: character) return character is
+
+      variable l: character;
+
+    begin
+
+       case c is
+        when 'A' => l := 'a';
+        when 'B' => l := 'b';
+        when 'C' => l := 'c';
+        when 'D' => l := 'd';
+        when 'E' => l := 'e';
+        when 'F' => l := 'f';
+        when 'G' => l := 'g';
+        when 'H' => l := 'h';
+        when 'I' => l := 'i';
+        when 'J' => l := 'j';
+        when 'K' => l := 'k';
+        when 'L' => l := 'l';
+        when 'M' => l := 'm';
+        when 'N' => l := 'n';
+        when 'O' => l := 'o';
+        when 'P' => l := 'p';
+        when 'Q' => l := 'q';
+        when 'R' => l := 'r';
+        when 'S' => l := 's';
+        when 'T' => l := 't';
+        when 'U' => l := 'u';
+        when 'V' => l := 'v';
+        when 'W' => l := 'w';
+        when 'X' => l := 'x';
+        when 'Y' => l := 'y';
+        when 'Z' => l := 'z';
+        when others => l := c;
+    end case;
+
+      return l;
+
+   end to_lower;
+
+
+
+   -- convert a string to upper case
+
+   function to_upper(s: string) return string is
+
+     variable uppercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        uppercase(i):= to_upper(s(i));
+     end loop;
+     return uppercase;
+
+   end to_upper;
+
+
+
+   -- convert a string to lower case
+
+   function to_lower(s: string) return string is
+
+     variable lowercase: string (s'range);
+
+   begin
+
+     for i in s'range loop
+        lowercase(i):= to_lower(s(i));
+     end loop;
+     return lowercase;
+
+   end to_lower;
+
+
+
+-- functions to convert strings into other types
+
+
+-- converts a character into a std_logic
+
+function to_std_logic(c: character) return std_logic is 
+    variable sl: std_logic;
+    begin
+      case c is
+        when 'U' => 
+           sl := 'U'; 
+        when 'X' =>
+           sl := 'X';
+        when '0' => 
+           sl := '0';
+        when '1' => 
+           sl := '1';
+        when 'Z' => 
+           sl := 'Z';
+        when 'W' => 
+           sl := 'W';
+        when 'L' => 
+           sl := 'L';
+        when 'H' => 
+           sl := 'H';
+        when '-' => 
+           sl := '-';
+        when others =>
+           sl := 'X'; 
+    end case;
+   return sl;
+  end to_std_logic;
+
+
+-- converts a string into std_logic_vector
+
+function to_std_logic_vector(s: string) return std_logic_vector is 
+  variable slv: std_logic_vector(s'high-s'low downto 0);
+  variable k: integer;
+begin
+   k := s'high-s'low;
+  for i in s'range loop
+     slv(k) := to_std_logic(s(i));
+     k      := k - 1;
+  end loop;
+  return slv;
+end to_std_logic_vector;                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+                                       
+----------------
+--  file I/O  --
+----------------
+
+
+
+-- read variable length string from input file
+     
+procedure str_read(file in_file: TEXT; 
+                   res_string: out string) is
+       
+       variable l:         line;
+       variable c:         character;
+       variable is_string: boolean;
+       
+   begin
+           
+     readline(in_file, l);
+     -- clear the contents of the result string
+     for i in res_string'range loop
+         res_string(i) := ' ';
+     end loop;   
+     -- read all characters of the line, up to the length  
+     -- of the results string
+     for i in res_string'range loop
+        read(l, c, is_string);
+        res_string(i) := c;
+        if not is_string then -- found end of line
+           exit;
+        end if;   
+     end loop; 
+                     
+end str_read;
+
+
+-- print string to a file
+procedure print(file out_file: TEXT;
+                new_string: in  string) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, new_string);
+     writeline(out_file, l);
+                     
+end print;
+
+
+-- print character to a file and start new line
+procedure print(file out_file: TEXT;
+                char: in  character) is
+       
+       variable l: line;
+       
+   begin
+      
+     write(l, char);
+     writeline(out_file, l);
+                     
+end print;
+
+
+
+-- appends contents of a string to a file until line feed occurs
+-- (LF is considered to be the end of the string)
+
+procedure str_write(file out_file: TEXT; 
+                    new_string: in  string) is
+ begin
+      
+   for i in new_string'range loop
+      print(out_file, new_string(i));
+      if new_string(i) = LF then -- end of string
+         exit;
+      end if;
+   end loop;               
+                     
+end str_write;
+
+
+
+
+end txt_util;
+
+
+
+
diff --git a/zpu/hdl/zpu4/src/xmake.filelist b/zpu/hdl/zpu4/src/xmake.filelist
new file mode 100644
index 0000000..91e623f
--- /dev/null
+++ b/zpu/hdl/zpu4/src/xmake.filelist
@@ -0,0 +1,12 @@
+vhdl work "ic300_config.vhd"
+vhdl work "ic300pkg.vhd"
+vhdl zylin "zpu_config.vhd"
+vhdl zylin "zpupkg.vhd"
+vhdl zylin "zpu_core.vhd"
+vhdl work "bram.vhd"
+vhdl zylin "zpuio.vhd"
+vhdl zylin "..\dummyfpgalib\arm7\src\arm7pkg.vhd"
+vhdl zylin "..\dummyfpgalib\arm7\src\arm7wb.vhd"
+vhdl work "clocks.vhd"
+vhdl work "timer.vhd"
+vhdl work "ic300.vhd"
\ No newline at end of file
diff --git a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall
new file mode 100644
index 0000000..141633e
--- /dev/null
+++ b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall
@@ -0,0 +1,5 @@
+vhdl work "zpu_config.vhd"
+vhdl work "zpupkg.vhd"
+vhdl work "zpu_core_small.vhd"
+vhdl work "bram_dmips.vhd"
+vhdl work "testlut.vhd"
diff --git a/zpu/hdl/zpu4/src/xmake.xst b/zpu/hdl/zpu4/src/xmake.xst
new file mode 100644
index 0000000..bfdb23f
--- /dev/null
+++ b/zpu/hdl/zpu4/src/xmake.xst
@@ -0,0 +1,53 @@
+set -tmpdir ../tmp
+set -xsthdpdir ../xst
+run
+-ifn xmake.filelist
+-ifmt mixed
+-ofn ../syn/ic300
+-ofmt NGC
+-p xc3s400-4-ft256
+-top ic300
+-opt_mode Area
+-opt_level 2
+-iuc NO
+-lso ic300.lso
+-keep_hierarchy NO
+-glob_opt AllClockNets
+-rtlview Yes
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-rom_style Auto
+-mux_extract YES
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-resource_sharing YES
+-mult_style auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-equivalent_register_removal NO
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set No
+-use_sync_reset No
+-iob true
+-slice_utilization_ratio_maxmargin 5
diff --git a/zpu/hdl/zpu4/src/zpu_config.vhd b/zpu/hdl/zpu4/src/zpu_config.vhd
new file mode 100644
index 0000000..a13c0bf
--- /dev/null
+++ b/zpu/hdl/zpu4/src/zpu_config.vhd
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+	-- generate trace output or not.
+	constant	Generate_Trace		: boolean := false;
+	constant wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := 'X';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
+	-- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1)
+	constant 	maxAddrBitIncIO		: integer := 15;
+	
+end zpu_config;
diff --git a/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd
new file mode 100644
index 0000000..d39c9e9
--- /dev/null
+++ b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+
+	constant	Generate_Trace		: boolean := false;
+	constant wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"50"; -- 80MHz
+	constant 	maxAddrBitIncIO		: integer := 15;
+		
+end zpu_config;
diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd
new file mode 100644
index 0000000..d1bbbbb
--- /dev/null
+++ b/zpu/hdl/zpu4/src/zpu_config_trace.vhd
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+package zpu_config is
+
+	constant	Generate_Trace		: boolean := true;
+	constant wordPower			: integer := 5;
+	-- during simulation, set this to '0' to get matching trace.txt 
+	constant	DontCareValue		: std_logic := '0';
+	-- Clock frequency in MHz.
+	constant	ZPU_Frequency		: std_logic_vector(7 downto 0) := x"64";
+	constant 	maxAddrBitIncIO		: integer := 15;
+	
+end zpu_config;
diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/src/zpu_core.vhd
new file mode 100644
index 0000000..c7093e2
--- /dev/null
+++ b/zpu/hdl/zpu4/src/zpu_core.vhd
@@ -0,0 +1,900 @@
+
+-- Company: ZPU4 generic memory interface CPU
+-- Engineer: Øyvind Harboe
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+-- mem_writeEnable - set to '1' for a single cycle to send off a write request.
+--                   mem_write is valid only while mem_writeEnable='1'.
+-- mem_readEnable - set to '1' for a single cycle to send off a read request.
+-- 
+-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'.
+--            Set to '0' when mem_read  is valid after a read request.
+--            If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable
+--            is '1'.
+-- mem_addr - address for read/write request
+-- mem_read - read data. Valid only on the cycle after mem_busy='0' after 
+--            mem_readEnable='1' for a single cycle.
+-- mem_write - data to write
+-- mem_writeMask - set to '1' for those bits that are to be written to memory upon
+--                 write request
+-- break - set to '1' when CPU hits break instruction
+-- interrupt - set to '1' until interrupts are cleared by CPU. 
+ 
+
+
+
+entity zpu_core is
+    Port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  enable : in std_logic; 
+	 		  in_mem_busy : in std_logic; 
+	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
+	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
+			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+			  out_mem_writeEnable : out std_logic; 
+			  out_mem_readEnable : out std_logic;
+	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic);
+end zpu_core;
+
+architecture behave of zpu_core is
+
+type InsnType is 
+(
+State_AddTop,
+State_Dup,
+State_DupStackB,
+State_Pop,
+State_Popdown,
+State_Add,
+State_Or,
+State_And,
+State_Store,
+State_AddSP,
+State_Shift,
+State_Nop,
+State_Im,
+State_LoadSP,
+State_StoreSP,
+State_Emulate,
+State_Load,
+State_PushPC,
+State_PushSP,
+State_PopPC,
+State_PopPCRel,
+State_Not,
+State_Flip,
+State_PopSP,
+State_Neqbranch,
+State_Eq,
+State_Loadb,
+State_Mult,
+State_Lessthan,
+State_Lessthanorequal,
+State_Ulessthanorequal,
+State_Ulessthan,
+State_Pushspadd,
+State_Call,
+State_Callpcrel,
+State_Sub,
+State_Break,
+State_Storeb,
+State_InsnFetch
+);
+
+type StateType is 
+(
+State_Load2,
+State_Popped,
+State_LoadSP2,
+State_LoadSP3,
+State_AddSP2,
+State_Fetch,
+State_Execute,
+State_Decode,
+State_Decode2,
+State_Resync,
+
+State_StoreSP2,
+State_Resync2,
+State_Resync3,
+State_Loadb2,
+State_Storeb2,
+State_Mult2,
+State_Mult3,
+State_Mult5,
+State_Mult4,
+State_BinaryOpResult2,
+State_BinaryOpResult,
+State_Idle
+); 
+
+
+signal	pc				: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	sp				: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	incSp			: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	incIncSp			: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	decSp			: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal  stackA   		: std_logic_vector(wordSize-1 downto 0);
+signal  binaryOpResult		: std_logic_vector(wordSize-1 downto 0);
+signal  binaryOpResult2		: std_logic_vector(wordSize-1 downto 0);
+signal  multResult2  		: std_logic_vector(wordSize-1 downto 0);
+signal  multResult3  		: std_logic_vector(wordSize-1 downto 0);
+signal  multResult  		: std_logic_vector(wordSize-1 downto 0);
+signal  multA 		: std_logic_vector(wordSize-1 downto 0);
+signal  multB  		: std_logic_vector(wordSize-1 downto 0);
+signal  stackB  		: std_logic_vector(wordSize-1 downto 0);
+signal	idim_flag			: std_logic;
+signal	busy 				: std_logic;
+signal mem_writeEnable : std_logic; 
+signal mem_readEnable : std_logic;
+signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal mem_delayReadEnable : std_logic;
+
+signal decodeWord : std_logic_vector(wordSize-1 downto 0);
+
+
+signal state : StateType;
+signal insn : InsnType;
+type InsnArray is array(0 to wordBytes-1) of InsnType;
+signal decodedOpcode : InsnArray;
+
+type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
+
+signal opcode : OpcodeArray;
+
+
+
+
+signal	begin_inst			: std_logic;
+signal trace_opcode		: std_logic_vector(7 downto 0);
+signal	trace_pc				: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	trace_sp				: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	trace_topOfStack				: std_logic_vector(wordSize-1 downto 0);
+signal	trace_topOfStackB				: std_logic_vector(wordSize-1 downto 0);
+
+-- state machine.
+
+begin
+
+
+	traceFileGenerate:
+   if Generate_Trace generate
+	trace_file: trace port map (
+       	clk => clk,
+       	begin_inst => begin_inst,
+       	pc => trace_pc,
+		opcode => trace_opcode,
+		sp => trace_sp,
+		memA => trace_topOfStack,
+		memB => trace_topOfStackB,
+		busy => busy,
+		intsp => (others => 'U')
+        );
+	end generate;
+
+	
+	-- the memory subsystem will tell us one cycle later whether or 
+	-- not it is busy
+	out_mem_writeEnable <= mem_writeEnable;
+	out_mem_readEnable <= mem_readEnable;
+	out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr;
+	out_mem_addr(minAddrBit-1 downto 0) <= (others => '0');
+	
+	incSp <= sp + 1;
+	incIncSp <= sp + 2;
+	decSp <= sp - 1;
+	
+
+	opcodeControl:
+	process(clk, areset)
+		variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+		variable spOffset : std_logic_vector(4 downto 0);
+		variable tSpOffset : std_logic_vector(4 downto 0);
+		variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0);
+		variable tNextState : InsnType;
+		variable tDecodedOpcode : InsnArray;
+		variable tMultResult : std_logic_vector(wordSize*2-1 downto 0);
+	begin
+		if areset = '1' then
+			state <= State_Idle;
+			break <= '0';
+			-- point to top of RAM-8
+			sp <= (others => '0'); 
+			sp(maxAddrBit downto minAddrBit+1) <= (others => '1');
+			 
+			pc <= (others => '0');
+			idim_flag <= '0';
+			begin_inst <= '0';
+			mem_writeEnable <= '0'; 
+			mem_readEnable <= '0';
+			multA <= (others => '0');
+			multB <= (others => '0');
+			mem_writeMask <= (others => '1');
+		elsif (clk'event and clk = '1') then
+			-- we must multiply unconditionally to get pipelined multiplication
+        	tMultResult := multA * multB;
+    		multResult3 <= multResult2;
+    		multResult2 <= multResult;
+    		multResult <= tMultResult(wordSize-1 downto 0);
+    		
+    		
+			binaryOpResult2 <= binaryOpResult; -- pipeline a bit.
+
+
+			multA <= (others => DontCareValue);
+			multB <= (others => DontCareValue);
+			
+			
+			mem_addr <= (others => DontCareValue);
+			mem_readEnable <='0';
+			mem_writeEnable <='0';
+			mem_write <= (others => DontCareValue);
+
+			if (mem_writeEnable = '1') and (mem_readEnable = '1') then
+				report "read/write collision" severity failure;
+			end if;
+	
+
+
+			
+			spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4);
+			spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0);
+			nextPC := pc + 1;
+
+			-- prepare trace snapshot
+			trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0)));
+			trace_pc <= pc;
+			trace_sp <=	sp;
+			trace_topOfStack <= stackA;
+			trace_topOfStackB <= stackB;
+			begin_inst <= '0';
+
+
+			case state is
+				when State_Idle =>
+					if enable='1' then
+						state <= State_Resync; 
+					end if;
+				-- Initial state of ZPU, fetch top of stack + first instruction 
+				when State_Resync =>
+					if in_mem_busy='0' then
+						mem_addr <= sp;
+						mem_readEnable <= '1';
+						state <= State_Resync2;
+					end if;
+				when State_Resync2 =>
+					if in_mem_busy='0' then
+						stackA <= mem_read;
+						mem_addr <= incSp;
+						mem_readEnable <= '1';
+						state <= State_Resync3;
+					end if;
+				when State_Resync3 =>
+					if in_mem_busy='0' then
+						stackB <= mem_read;
+						mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
+						mem_readEnable <= '1';
+						state <= State_Decode;
+					end if;
+				when State_Decode =>
+					if in_mem_busy='0' then
+						decodeWord <= mem_read;
+						state <= State_Decode2;
+					end if;
+				when State_Decode2 =>
+					-- decode 4 instructions in parallel
+					for i in 0 to wordBytes-1 loop
+						tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
+
+						tSpOffset(4):=not tOpcode(4);
+						tSpOffset(3 downto 0):=tOpcode(3 downto 0);
+
+						opcode(i) <= tOpcode;
+						if (tOpcode(7 downto 7)=OpCode_Im) then
+							tNextState:=State_Im;
+						elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
+							if tSpOffset = 0 then
+								tNextState := State_Pop;
+							elsif tSpOffset=1 then
+								tNextState := State_PopDown;
+							else
+								tNextState :=State_StoreSP;
+							end if;
+						elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
+							if tSpOffset = 0 then
+								tNextState :=State_Dup;
+							elsif tSpOffset = 1 then
+								tNextState :=State_DupStackB;
+							else
+								tNextState :=State_LoadSP;
+							end if;
+						elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
+							tNextState :=State_Emulate;
+							if tOpcode(5 downto 0)=OpCode_Neqbranch then
+								tNextState :=State_Neqbranch;
+							elsif tOpcode(5 downto 0)=OpCode_Eq then
+								tNextState :=State_Eq;
+							elsif tOpcode(5 downto 0)=OpCode_Lessthan then
+								tNextState :=State_Lessthan;
+							elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then
+								--tNextState :=State_Lessthanorequal;
+							elsif tOpcode(5 downto 0)=OpCode_Ulessthan then
+								tNextState :=State_Ulessthan;
+							elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then
+								--tNextState :=State_Ulessthanorequal;
+							elsif tOpcode(5 downto 0)=OpCode_Loadb then
+								tNextState :=State_Loadb;
+							elsif tOpcode(5 downto 0)=OpCode_Mult then
+								tNextState :=State_Mult;
+							elsif tOpcode(5 downto 0)=OpCode_Storeb then
+								tNextState :=State_Storeb;
+							elsif tOpcode(5 downto 0)=OpCode_Pushspadd then
+								tNextState :=State_Pushspadd;
+							elsif tOpcode(5 downto 0)=OpCode_Callpcrel then
+								tNextState :=State_Callpcrel;
+							elsif tOpcode(5 downto 0)=OpCode_Call then
+								--tNextState :=State_Call;
+							elsif tOpcode(5 downto 0)=OpCode_Sub then
+								tNextState :=State_Sub;
+							elsif tOpcode(5 downto 0)=OpCode_PopPCRel then
+								--tNextState :=State_PopPCRel;
+							end if;								
+						elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
+							if tSpOffset = 0 then
+								tNextState := State_Shift;
+							elsif tSpOffset = 1 then
+								tNextState := State_AddTop;
+							else
+								tNextState :=State_AddSP;
+							end if;
+						else
+							case tOpcode(3 downto 0) is
+								when OpCode_Nop =>
+									tNextState :=State_Nop;
+								when OpCode_PushSP =>
+									tNextState :=State_PushSP;
+								when OpCode_PopPC =>
+									tNextState :=State_PopPC;
+								when OpCode_Add =>
+									tNextState :=State_Add;
+								when OpCode_Or =>
+									tNextState :=State_Or;
+								when OpCode_And =>
+									tNextState :=State_And;
+								when OpCode_Load =>
+									tNextState :=State_Load;
+								when OpCode_Not =>
+									tNextState :=State_Not;
+								when OpCode_Flip =>
+									tNextState :=State_Flip;
+								when OpCode_Store =>
+									tNextState :=State_Store;
+								when OpCode_PopSP =>
+									tNextState :=State_PopSP;
+								when others =>
+									tNextState := State_Break;
+
+							end case;
+						end if;
+						tDecodedOpcode(i) := tNextState;
+						
+					end loop;
+					
+					insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0)));
+					
+					-- once we wrap, we need to fetch
+					tDecodedOpcode(0) := State_InsnFetch;
+
+					decodedOpcode <= tDecodedOpcode;
+					state <= State_Execute;
+						
+
+
+					-- Each instruction must:
+					--
+					-- 1. set idim_flag
+					-- 2. increase pc if applicable
+					-- 3. set next state if appliable
+					-- 4. do it's operation
+					 
+				when State_Execute =>
+					insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0)));
+									
+					case insn is
+						when State_InsnFetch =>
+							state <= State_Fetch;
+						when State_Im =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '1';
+								pc <= pc + 1;
+								
+								if idim_flag='1' then 
+									stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
+									stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
+								else
+									mem_writeEnable <= '1';
+									mem_addr <= incSp;
+									mem_write <= stackB;
+									stackB <= stackA;
+									sp <= decSp;
+									for i in wordSize-1 downto 7 loop
+										stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6);
+									end loop;
+									stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
+								end if;
+							end if;
+						when State_StoreSP =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_StoreSP2;
+								
+								mem_writeEnable <= '1';
+								mem_addr <= sp+spOffset;
+								mem_write <= stackA;
+								stackA <= stackB;
+								sp <= incSp;
+							end if;
+
+					
+						when State_LoadSP =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_LoadSP2;
+		
+								sp <= decSp;
+								mem_writeEnable <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+							end if;
+						when State_Emulate =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								sp <= decSp;
+								mem_writeEnable <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+								stackA <= (others => DontCareValue);
+								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+								stackB <= stackA;
+								
+								-- The emulate address is:
+								--        98 7654 3210
+								-- 0000 00aa aaa0 0000
+								pc <= (others => '0');
+								pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0);
+								state <= State_Fetch;
+							end if;
+						when State_Callpcrel =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= (others => DontCareValue);
+								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+								
+								pc <= pc + stackA(maxAddrBitIncIO downto 0);
+								state <= State_Fetch;
+							end if;
+						when State_Call =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= (others => DontCareValue);
+								stackA(maxAddrBitIncIO downto 0) <= pc + 1;
+								pc <= stackA(maxAddrBitIncIO downto 0);
+								state <= State_Fetch;
+							end if;
+						when State_AddSP =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_AddSP2;
+								
+								mem_readEnable <= '1';
+								mem_addr <= sp+spOffset;
+							end if;
+						when State_PushSP =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1;
+								
+								sp <= decSp;
+								stackA <= (others => '0');
+								stackA(maxAddrBitIncIO downto minAddrBit) <= sp;
+								stackB <= stackA;
+								mem_writeEnable <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+							end if;
+						when State_PopPC =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= stackA(maxAddrBitIncIO downto 0);
+								sp <= incSp;
+								
+								mem_writeEnable <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+								state <= State_Resync;
+							end if;
+						when State_PopPCRel =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+								sp <= incSp;
+								
+								mem_writeEnable <= '1';
+								mem_addr <= incSp;
+								mem_write <= stackB;
+								state <= State_Resync;
+							end if;
+						when State_Add =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= stackA + stackB;
+								
+								mem_readEnable <= '1';
+								mem_addr <= incIncSp;
+								sp <= incSp;
+								state <= State_Popped;
+							end if;
+						when State_Sub =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								binaryOpResult <= stackB - stackA;
+								state <= State_BinaryOpResult;
+							end if;
+						when State_Pop =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								mem_addr <= incIncSp;
+								mem_readEnable <= '1';
+								sp <= incSp;
+								stackA <= stackB;
+								state <= State_Popped;						
+							end if;
+						when State_PopDown =>
+							if in_mem_busy='0' then
+								-- PopDown leaves top of stack unchanged
+								begin_inst <= '1';
+								idim_flag <= '0';
+								mem_addr <= incIncSp;
+								mem_readEnable <= '1';
+								sp <= incSp;
+								state <= State_Popped;						
+							end if;
+						when State_Or =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								stackA <= stackA or stackB;
+								mem_readEnable <= '1';
+								mem_addr <= incIncSp;
+								sp <= incSp;
+								state <= State_Popped;
+							end if;
+						when State_And =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+		
+								stackA <= stackA and stackB;
+								mem_readEnable <= '1';
+								mem_addr <= incIncSp;
+								sp <= incSp;
+								state <= State_Popped;
+							end if;
+						when State_Eq =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+		
+			            		binaryOpResult <= (others => '0');
+			                	if (stackA=stackB) then
+			                		binaryOpResult(0) <= '1';
+			                	end if;
+								state <= State_BinaryOpResult;
+							end if;
+		                when State_Ulessthan =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+		
+			            		binaryOpResult <= (others => '0');
+			                	if (stackA<stackB) then
+			                		binaryOpResult(0) <= '1';
+			                	end if;
+								state <= State_BinaryOpResult;
+							end if;
+		                when State_Ulessthanorequal =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+		
+			            		binaryOpResult <= (others => '0');
+			                	if (stackA<=stackB) then
+			                		binaryOpResult(0) <= '1';
+			                	end if;
+								state <= State_BinaryOpResult;
+							end if;
+		                when State_Lessthan =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+		
+			            		binaryOpResult <= (others => '0');
+			                	if (signed(stackA)<signed(stackB)) then
+			                		binaryOpResult(0) <= '1';
+			                	end if;
+								state <= State_BinaryOpResult;
+							end if;
+		                when State_Lessthanorequal =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+		
+			            		binaryOpResult <= (others => '0');
+			                	if (signed(stackA)<=signed(stackB)) then
+			                		binaryOpResult(0) <= '1';
+			                	end if;
+								state <= State_BinaryOpResult;
+							end if;
+						when State_Load =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_Load2;
+								
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								mem_readEnable <= '1';
+							end if;
+
+						when State_Dup =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1; 
+								
+								sp <= decSp;
+								stackB <= stackA;
+								mem_write <= stackB;
+								mem_addr <= incSp;
+								mem_writeEnable <= '1';
+							end if;
+						when State_DupStackB =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1; 
+								
+								sp <= decSp;
+								stackA <= stackB;
+								stackB <= stackA;
+								mem_write <= stackB;
+								mem_addr <= incSp;
+								mem_writeEnable <= '1';
+							end if;
+						when State_Store =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1;
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								mem_write <= stackB;
+								mem_writeEnable <= '1';
+								sp <= incIncSp;
+								state <= State_Resync;
+							end if;
+						when State_PopSP =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								pc <= pc + 1;
+								
+								mem_write <= stackB;
+								mem_addr <= incSp;
+								mem_writeEnable <= '1';
+								sp <= stackA(maxAddrBitIncIO downto minAddrBit);
+								state <= State_Resync;
+							end if;
+						when State_Nop =>	
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1;
+						when State_Not =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA <= not stackA;
+						when State_Flip =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							for i in 0 to wordSize-1 loop
+								stackA(i) <= stackA(wordSize-1-i);
+				  			end loop;
+						when State_AddTop =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA <= stackA + stackB;
+						when State_Shift =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
+							stackA(0) <= '0';
+						when State_Pushspadd =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+							pc <= pc + 1; 
+							
+							stackA <= (others => '0');
+							stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
+						when State_Neqbranch =>
+							-- branches are almost always taken as they form loops
+							begin_inst <= '1';
+							idim_flag <= '0';
+							sp <= incIncSp;
+		                	if (stackB/=0) then
+		                		pc <= stackA(maxAddrBitIncIO downto 0) + pc;
+		                	else
+		                		pc <= pc + 1;
+		                	end if;		
+		                	-- need to fetch stack again.				
+							state <= State_Resync;
+		                when State_Mult =>
+							begin_inst <= '1';
+							idim_flag <= '0';
+		
+							multA <= stackA;
+							multB <= stackB;
+							state <= State_Mult2;
+						when State_Break =>
+							report "Break instruction encountered" severity failure;
+							break <= '1';
+
+						when State_Loadb =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_Loadb2;
+								
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								mem_readEnable <= '1';
+							end if;
+						when State_Storeb =>
+							if in_mem_busy='0' then
+								begin_inst <= '1';
+								idim_flag <= '0';
+								state <= State_Storeb2;
+								
+								mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+								mem_readEnable <= '1';
+							end if;
+				
+						when others =>
+							sp <= (others => DontCareValue);
+							report "Illegal instruction" severity failure;
+							break <= '1';
+					end case;
+
+
+				when State_StoreSP2 =>
+					if in_mem_busy='0' then
+						mem_addr <= incSp;
+						mem_readEnable <= '1';
+						state <= State_Popped;
+					end if;
+				when State_LoadSP2 =>
+					if in_mem_busy='0' then
+						state <= State_LoadSP3;
+						mem_readEnable <= '1';
+						mem_addr <= sp+spOffset+1;
+					end if;
+				when State_LoadSP3 =>
+					if in_mem_busy='0' then
+						pc <= pc + 1;
+						state <= State_Execute;
+						stackB <= stackA;
+						stackA <= mem_read;
+					end if;
+				when State_AddSP2 =>
+					if in_mem_busy='0' then
+						pc <= pc + 1;
+						state <= State_Execute;
+						stackA <= stackA + mem_read;
+					end if;
+				when State_Load2 =>
+					if in_mem_busy='0' then
+						stackA <= mem_read;
+						pc <= pc + 1;
+						state <= State_Execute;
+					end if;
+				when State_Loadb2 =>
+					if in_mem_busy='0' then
+						stackA <= (others => '0');
+						stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8);
+						pc <= pc + 1;
+						state <= State_Execute;
+					end if;
+				when State_Storeb2 =>
+					if in_mem_busy='0' then
+						mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
+						mem_write <= mem_read;
+						mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ;
+						mem_writeEnable <= '1';
+						pc <= pc + 1;
+						sp <= incIncSp;
+						state <= State_Resync;
+					end if;
+				when State_Fetch =>
+					if in_mem_busy='0' then
+						mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
+						mem_readEnable <= '1';
+						state <= State_Decode;
+					end if;
+                when State_Mult2 =>
+					state <= State_Mult3;
+                when State_Mult3 =>
+					state <= State_Mult4;
+                when State_Mult4 =>
+					state <= State_Mult5;
+                when State_Mult5 =>
+					if in_mem_busy='0' then
+	            		stackA <= multResult3;
+						mem_readEnable <= '1';
+						mem_addr <= incIncSp;
+						sp <= incSp;
+						state <= State_Popped;
+					end if;
+				when State_BinaryOpResult =>	
+					state <= State_BinaryOpResult2;
+				when State_BinaryOpResult2 =>
+					mem_readEnable <= '1';
+					mem_addr <= incIncSp;
+					sp <= incSp;
+					stackA <= binaryOpResult2;
+					state <= State_Popped;
+				when State_Popped =>
+					if in_mem_busy='0' then
+						pc <= pc + 1;
+						stackB <= mem_read;
+						state <= State_Execute;
+					end if;
+				when others =>	
+					sp <= (others => DontCareValue);
+					report "Illegal state" severity failure;
+					break <= '1';
+			end case;
+		end if;
+	end process;
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd
new file mode 100644
index 0000000..4d73f88
--- /dev/null
+++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd
@@ -0,0 +1,433 @@
+-- Company: ZPU3
+-- Engineer: Øyvind Harboe
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+
+entity zpu_core is
+    Port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  enable : in std_logic; 
+	 		  in_mem_busy : in std_logic; 
+	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
+	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);			  
+	 		  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+			  out_mem_writeEnable : out std_logic; 
+			  out_mem_readEnable : out std_logic;
+	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic);
+end zpu_core;
+
+architecture behave of zpu_core is
+
+signal		readIO : std_logic;
+
+
+
+signal memAWriteEnable : std_logic;
+signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal memAWrite : std_logic_vector(wordSize-1 downto 0);
+signal memARead : std_logic_vector(wordSize-1 downto 0);
+signal memBWriteEnable : std_logic;
+signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal memBWrite : std_logic_vector(wordSize-1 downto 0);
+signal memBRead : std_logic_vector(wordSize-1 downto 0);
+
+
+
+signal	pc				: std_logic_vector(maxAddrBit downto 0);
+signal	sp				: std_logic_vector(maxAddrBit downto minAddrBit);
+
+signal	idim_flag			: std_logic;
+
+--signal	storeToStack		: std_logic;
+--signal	fetchNextInstruction		: std_logic;
+--signal	extraCycle			: std_logic;
+signal	busy 				: std_logic;
+--signal	fetching			: std_logic;
+
+signal	begin_inst			: std_logic;
+
+
+
+signal trace_opcode		: std_logic_vector(7 downto 0);
+signal	trace_pc				: std_logic_vector(maxAddrBitIncIO downto 0);
+signal	trace_sp				: std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+signal	trace_topOfStack				: std_logic_vector(wordSize-1 downto 0);
+signal	trace_topOfStackB				: std_logic_vector(wordSize-1 downto 0);
+
+-- state machine.
+type State_Type is
+(
+State_Fetch,
+State_WriteIODone,
+State_Execute,
+State_StoreToStack,
+State_Add,
+State_Or,
+State_And,
+State_Store,
+State_ReadIO,
+State_WriteIO,
+State_Load,
+State_FetchNext,
+State_AddSP,
+State_ReadIODone,
+State_Decode,
+State_Resync
+);
+
+type DecodedOpcodeType is
+(
+Decoded_Nop,
+Decoded_Im,
+Decoded_ImShift,
+Decoded_LoadSP,
+Decoded_StoreSP	,
+Decoded_AddSP,
+Decoded_Emulate,
+Decoded_Break,
+Decoded_PushSP,
+Decoded_PopPC,
+Decoded_Add,
+Decoded_Or,
+Decoded_And,
+Decoded_Load,
+Decoded_Not,
+Decoded_Flip,
+Decoded_Store,
+Decoded_PopSP
+);
+
+
+
+signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+signal opcode : std_logic_vector(OpCode_Size-1 downto 0);
+
+signal decodedOpcode : DecodedOpcodeType;
+signal sampledDecodedOpcode : DecodedOpcodeType;
+
+
+signal state : State_Type;
+
+begin
+	traceFileGenerate:
+   if Generate_Trace generate
+	trace_file: trace port map (
+       	clk => clk,
+       	begin_inst => begin_inst,
+       	pc => trace_pc,
+		opcode => trace_opcode,
+		sp => trace_sp,
+		memA => trace_topOfStack,
+		memB => trace_topOfStackB,
+		busy => busy,
+		intsp => (others => 'U')
+        );
+	end generate;
+
+
+	memory: dualport_ram port map (
+       	clk => clk,
+	memAWriteEnable => memAWriteEnable,
+	memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit),
+	memAWrite => memAWrite,
+	memARead => memARead,
+	memBWriteEnable => memBWriteEnable,
+	memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit),
+	memBWrite => memBWrite,
+	memBRead => memBRead
+        );
+
+
+
+	decodeControl:
+	process(memBRead, pc)
+		variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
+	begin
+		tOpcode := memBRead((wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0)))*8);
+
+		sampledOpcode <= tOpcode;
+
+		if (tOpcode(7 downto 7)=OpCode_Im) then
+			sampledDecodedOpcode<=Decoded_Im;
+		elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
+			sampledDecodedOpcode<=Decoded_StoreSP;
+		elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
+			sampledDecodedOpcode<=Decoded_LoadSP;
+		elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
+			sampledDecodedOpcode<=Decoded_Emulate;
+		elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
+			sampledDecodedOpcode<=Decoded_AddSP;
+		else
+			case tOpcode(3 downto 0) is
+				when OpCode_Break =>
+					sampledDecodedOpcode<=Decoded_Break;
+				when OpCode_PushSP =>
+					sampledDecodedOpcode<=Decoded_PushSP;
+				when OpCode_PopPC =>
+					sampledDecodedOpcode<=Decoded_PopPC;
+				when OpCode_Add =>
+					sampledDecodedOpcode<=Decoded_Add;
+				when OpCode_Or =>
+					sampledDecodedOpcode<=Decoded_Or;
+				when OpCode_And =>
+					sampledDecodedOpcode<=Decoded_And;
+				when OpCode_Load =>
+					sampledDecodedOpcode<=Decoded_Load;
+				when OpCode_Not =>
+					sampledDecodedOpcode<=Decoded_Not;
+				when OpCode_Flip =>
+					sampledDecodedOpcode<=Decoded_Flip;
+				when OpCode_Store =>
+					sampledDecodedOpcode<=Decoded_Store;
+				when OpCode_PopSP =>
+					sampledDecodedOpcode<=Decoded_PopSP;
+				when others =>
+					sampledDecodedOpcode<=Decoded_Nop;
+			end case;
+		end if;
+	end process;
+
+
+	opcodeControl:
+	process(clk, areset)
+		variable spOffset : std_logic_vector(4 downto 0);
+	begin
+		if areset = '1' then
+			state <= State_Resync;
+			break <= '0';
+			sp <= spStart(maxAddrBit downto minAddrBit); 
+			pc <= (others => '0');
+			idim_flag <= '0';
+			begin_inst <= '0';
+			memAAddr <= (others => '0');
+			memBAddr <= (others => '0');
+			memAWriteEnable <= '0';
+			memBWriteEnable <= '0';
+			out_mem_writeEnable <= '0';
+			out_mem_readEnable <= '0';
+			memAWrite <= (others => '0');
+			memBWrite <= (others => '0');
+			mem_writeMask <= (others => '1');
+		elsif (clk'event and clk = '1') then
+			memAWriteEnable <= '0';
+			memBWriteEnable <= '0';
+			-- This saves ca. 100 LUT's, by explicitly declaring that the
+			-- memAWrite can be left at whatever value if memAWriteEnable is
+			-- not set.
+			memAWrite <= (others => DontCareValue);
+			memBWrite <= (others => DontCareValue);
+--			out_mem_addr <= (others => DontCareValue);
+--			mem_write <= (others => DontCareValue);
+			spOffset := (others => DontCareValue);
+			memAAddr <= (others => DontCareValue);
+			memBAddr <= (others => DontCareValue);
+			
+			out_mem_writeEnable <= '0';
+			out_mem_readEnable <= '0';
+			begin_inst <= '0';
+			out_mem_addr <= memARead(maxAddrBitIncIO downto 0);
+			mem_write <= memBRead;
+			
+			decodedOpcode <= sampledDecodedOpcode;
+			opcode <= sampledOpcode;
+
+			case state is
+				when State_Execute =>
+					state <= State_Fetch;
+					-- at this point:
+					-- memBRead contains opcode word
+					-- memARead contains top of stack
+					pc <= pc + 1;
+	
+					-- trace
+					begin_inst <= '1';
+					trace_pc <= (others => '0');
+					trace_pc(maxAddrBit downto 0) <= pc;
+					trace_opcode <= opcode;
+					trace_sp <= (others => '0');
+					trace_sp(maxAddrBit downto minAddrBit) <=	sp;
+					trace_topOfStack <= memARead;
+					trace_topOfStackB <= memBRead;
+
+					-- during the next cycle we'll be reading the next opcode	
+					spOffset(4):=not opcode(4);
+					spOffset(3 downto 0):=opcode(3 downto 0);
+	
+					idim_flag <= '0';
+					case decodedOpcode is
+						when Decoded_Im =>
+							idim_flag <= '1';
+							memAWriteEnable <= '1';
+							if (idim_flag='0') then
+								sp <= sp - 1;
+								memAAddr <= sp-1;
+								for i in wordSize-1 downto 7 loop
+									memAWrite(i) <= opcode(6);
+								end loop;
+								memAWrite(6 downto 0) <= opcode(6 downto 0);
+							else
+								memAAddr <= sp;
+								memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0);
+								memAWrite(6 downto 0) <= opcode(6 downto 0);
+							end if;
+						when Decoded_StoreSP =>
+							memBWriteEnable <= '1';
+							memBAddr <= sp+spOffset;
+							memBWrite <= memARead;
+							sp <= sp + 1;
+							state <= State_Resync;
+						when Decoded_LoadSP =>
+							sp <= sp - 1;
+							memAAddr <= sp+spOffset;
+						when Decoded_Emulate =>
+							sp <= sp - 1;
+							memAWriteEnable <= '1';
+							memAAddr <= sp - 1;
+							memAWrite <= (others => DontCareValue);
+							memAWrite(maxAddrBit downto 0) <= pc + 1;
+							-- The emulate address is:
+							--        98 7654 3210
+							-- 0000 00aa aaa0 0000
+							pc <= (others => '0');
+							pc(9 downto 5) <= opcode(4 downto 0);
+						when Decoded_AddSP =>
+							memAAddr <= sp;
+							memBAddr <= sp+spOffset;
+							state <= State_AddSP;
+						when Decoded_Break =>
+							report "Break instruction encountered" severity failure;
+							break <= '1';
+						when Decoded_PushSP =>
+							memAWriteEnable <= '1';
+							memAAddr <= sp - 1;
+							sp <= sp - 1;
+							memAWrite <= (others => DontCareValue);
+							memAWrite(maxAddrBit downto minAddrBit) <= sp;
+						when Decoded_PopPC =>
+							pc <= memARead(maxAddrBit downto 0);
+							sp <= sp + 1;
+							state <= State_Resync;
+						when Decoded_Add =>
+							sp <= sp + 1;
+							state <= State_Add;
+						when Decoded_Or =>
+							sp <= sp + 1;
+							state <= State_Or;
+						when Decoded_And =>
+							sp <= sp + 1;
+							state <= State_And;
+						when Decoded_Load =>
+							if (memARead(ioBit)='1') then
+								out_mem_addr <= memARead(maxAddrBitIncIO downto 0);
+								out_mem_readEnable <= '1';
+								state <= State_ReadIO;
+							else 
+								memAAddr <= memARead(maxAddrBit downto minAddrBit);
+							end if;
+						when Decoded_Not =>
+							memAAddr <= sp(maxAddrBit downto minAddrBit);
+							memAWriteEnable <= '1';
+							memAWrite <= not memARead;
+						when Decoded_Flip =>
+							memAAddr <= sp(maxAddrBit downto minAddrBit);
+							memAWriteEnable <= '1';
+							for i in 0 to wordSize-1 loop
+								memAWrite(i) <= memARead(wordSize-1-i);
+				  			end loop;
+						when Decoded_Store =>
+							memBAddr <= sp + 1;
+							sp <= sp + 1;
+							if (memARead(ioBit)='1') then
+								state <= State_WriteIO;
+							else
+								state <= State_Store;
+							end if;
+						when Decoded_PopSP =>
+							sp <= memARead(maxAddrBit downto minAddrBit);
+							state <= State_Resync;
+						when Decoded_Nop =>	
+							memAAddr <= sp;
+						when others =>	
+							null; 
+					end case;
+				when State_ReadIO =>
+					if (in_mem_busy = '0') then
+						state <= State_Fetch;
+						memAWriteEnable <= '1';
+						memAWrite <= mem_read;
+					end if;
+				when State_WriteIO =>
+					sp <= sp + 1;
+					out_mem_writeEnable <= '1';
+					out_mem_addr <= memARead(maxAddrBitIncIO downto 0);
+					mem_write <= memBRead;
+					state <= State_WriteIODone;
+				when State_WriteIODone =>
+					if (in_mem_busy = '0') then
+						state <= State_Resync;
+					end if;
+				when State_Fetch =>
+					-- We need to resync. During the *next* cycle
+					-- we'll fetch the opcode @ pc and thus it will
+					-- be available for State_Execute the cycle after
+					-- next
+					memBAddr <= pc(maxAddrBit downto minAddrBit);
+					state <= State_FetchNext;
+				when State_FetchNext =>
+					-- at this point memARead contains the value that is either
+					-- from the top of stack or should be copied to the top of the stack
+					memAWriteEnable <= '1';
+					memAWrite <= memARead; 
+					memAAddr <= sp;
+					memBAddr <= sp + 1;
+					state <= State_Decode;
+				when State_Decode =>
+					-- during the State_Execute cycle we'll be fetching SP+1
+					memAAddr <= sp;
+					memBAddr <= sp + 1;
+					state <= State_Execute;
+				when State_Store =>
+					sp <= sp + 1;
+					memAWriteEnable <= '1';
+					memAAddr <= memARead(maxAddrBit downto minAddrBit);
+					memAWrite <= memBRead;
+					state <= State_Resync;
+				when State_AddSP =>
+					state <= State_Add;
+				when State_Add =>
+					memAAddr <= sp;
+					memAWriteEnable <= '1';
+					memAWrite <= memARead + memBRead;
+					state <= State_Fetch;
+				when State_Or =>
+					memAAddr <= sp;
+					memAWriteEnable <= '1';
+					memAWrite <= memARead or memBRead;
+					state <= State_Fetch;
+				when State_Resync =>
+					memAAddr <= sp;
+					state <= State_Fetch;
+				when State_And =>
+					memAAddr <= sp;
+					memAWriteEnable <= '1';
+					memAWrite <= memARead and memBRead;
+					state <= State_Fetch;
+				when others =>
+					null;
+			end case;
+			
+		end if;
+	end process;
+
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd
new file mode 100644
index 0000000..d14629e
--- /dev/null
+++ b/zpu/hdl/zpu4/src/zpuio.vhd
@@ -0,0 +1,256 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity zpuio is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			clk_status		: in std_logic_vector(2 downto 0);
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_dout		: inout std_logic_vector(15 downto 0));
+end zpuio;
+
+architecture behave of zpuio is
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+
+signal io_busy : std_logic;
+signal io_read : std_logic_vector(7 downto 0);
+--signal io_write : std_logic_vector(7 downto 0);
+signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal io_writeEnable : std_logic;
+signal Enable : std_logic;
+
+signal		  din :  std_logic_vector(7 downto 0);
+signal	 		  dout : std_logic_vector(7 downto 0);
+signal			  adr : std_logic_vector(15 downto 0);
+signal			  break : std_logic;
+signal			  we : std_logic;
+signal			  re : std_logic;
+
+
+-- uart forwarding...
+
+signal uartTXPending : std_logic;
+signal uartTXCleared : std_logic;
+signal uartData : std_logic_vector(7 downto 0);
+
+signal readingTimer : std_logic;
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+signal			  dram_mem_busy : std_logic;
+signal			  dram_mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  dram_mem_writeEnable : std_logic; 
+signal			  dram_mem_readEnable : std_logic;
+signal			  dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+
+--signal			  io_mem_read : std_logic_vector(7 downto 0);
+--signal			  io_mem_writeEnable : std_logic; 
+--signal			  io_mem_readEnable : std_logic;
+signal			  io_readEnable : std_logic;
+
+
+signal			  dram_read : std_logic;
+
+
+
+begin
+
+	io_addr <= mem_addr(maxAddrBit downto minAddrBit);
+	
+	timerinst: timer port map (
+       clk => cpu_clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => mem_write(7 downto 0),
+		 adr => io_addr(4 downto 2),
+		 dout => timer_read);
+
+		zpu: zpu_core port map (
+		clk => cpu_clk ,
+	 	areset => areset,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+
+ram_imp: dram port map (
+		clk => cpu_clk ,
+		areset => areset,
+ 		mem_busy => dram_mem_busy, 
+ 		mem_read => dram_mem_read,
+ 		mem_write => mem_write, 
+		mem_addr => mem_addr(maxAddrBit downto 0), 
+		mem_writeEnable => dram_mem_writeEnable,  
+		mem_readEnable => dram_mem_readEnable,
+ 		mem_writeMask => mem_writeMask);
+
+
+	-- Read/write are on different addresses
+	-- The registers are 8 bits and mapped to bit[7:0]
+	-- 
+	-- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) 
+	--        Read : Reads from UART RX FIFO (4 byte FIFO)
+	-- 0xC004 Read : UART status register
+	--                       Bit 0 = RX FIFO empty
+	--                       Bit 1 = TX FIFO full
+	-- 0xA000 Skrive: LED's (8 stk.)
+	
+	-- 0x9000 Write: bit 0: 1= reset counter
+	-- 			   0= counter running
+	-- 		  bit 1: 1= sample counter (when set to 1)
+	-- 			   0=not used
+	-- 	 Read : counter bit[7:0]
+	-- 0x9004 Read: counter bit [15:8]
+	-- 0x9008 Read: counter bit [23:16]
+	-- 0x900C Read: counter bit [31:24]
+	-- 0x9010 Read: counter bit [39:32]
+	-- 0x9014 Read: counter bit [47:40]
+	-- 0x9018 Read: counter bit [55:48]
+	-- 0x901C Read: counter bit [63:56]
+	-- 
+	-- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz)
+	
+	fauxUart:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			io_busy <= '0';
+			uartTXPending <= '0';
+			timer_we <= '0';
+			io_busy <= '0';
+			uartData <= x"58"; -- 'X'
+			readingTimer <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			timer_we <= '0';
+			io_busy <= '0';
+			if uartTXCleared = '1' then
+				uartTXPending <= '0';
+			end if;
+		
+			if io_writeEnable = '1' then
+				if io_addr=x"1000" then
+					-- Write to UART
+					uartData <= mem_write(7 downto 0);
+					uartTXPending <= '1';
+					io_busy <= '1';
+ 				elsif io_addr(12)='1' then
+ 					timer_we <= '1';
+					io_busy <= '1';
+				else
+					report "Illegal IO write" severity failure;
+				end if;
+			end if;
+			if (io_readEnable = '1') then
+				if io_addr=x"1001" then
+					io_read <= (0=>'1',  		-- recieve empty
+ 					            1 => uartTXPending,   -- tx full
+ 					            others => '0');
+ 					io_busy <= '1';
+ 				elsif io_addr(12)='1' then
+ 					readingTimer <= '1';
+ 					io_busy <= '1';
+ 				elsif io_addr(11)='1' then
+ 					io_read <= ZPU_Frequency;
+ 					io_busy <= '1';
+				else
+					report "Illegal IO read" severity failure;
+				end if;
+				
+			else 
+				if (readingTimer = '1') then
+					readingTimer <= '0';
+ 					io_read <= timer_read;
+ 					io_busy <= '0';
+ 				else
+					io_read <= (others => '1');
+ 				end if;
+			end if;
+		end if;
+	end process;
+
+
+	forwardUARTOutputToARM:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			uartTXCleared <= '0';
+		elsif (cpu_clk = '1' and cpu_clk'event) then
+			if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
+				uartTXCleared <= cpu_din(0);
+			else
+				uartTXCleared <= uartTXCleared;
+			end if;
+		end if;
+	end process;	
+
+	cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
+	cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
+	
+	dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
+	dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
+	io_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+--	io_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable;
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			dram_read <= '0';
+			io_readEnable <= '0';
+
+		
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			mem_read <= (others => '0');
+			if mem_addr(ioBit)='0' and mem_readEnable='1' then
+				dram_read <= '1';
+			end if;
+			if dram_read='1' and dram_mem_busy='0' then
+				dram_read <= '0';
+				mem_read <= dram_mem_read;
+			end if;
+			 
+			if mem_addr(ioBit)='1' and mem_readEnable='1' then
+				io_readEnable <= '1';
+			end if;
+			if io_readEnable='1' and io_busy='0' then
+				io_readEnable <= '0';
+				mem_read(7 downto 0) <= io_read;
+			end if;
+			
+		end if;
+	end process;
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/src/zpuio_bram.vhd b/zpu/hdl/zpu4/src/zpuio_bram.vhd
new file mode 100644
index 0000000..5d3f409
--- /dev/null
+++ b/zpu/hdl/zpu4/src/zpuio_bram.vhd
@@ -0,0 +1,229 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.zpu_config.all;
+use work.zpupkg.all;
+
+entity zpuio is
+	port (	areset			: in std_logic;
+			cpu_clk			: in std_logic;
+			clk_status		: in std_logic_vector(2 downto 0);
+			cpu_din			: in std_logic_vector(15 downto 0);
+			cpu_a			: in std_logic_vector(20 downto 0);
+			cpu_we			: in std_logic_vector(1 downto 0);
+			cpu_re			: in std_logic;
+			cpu_dout		: inout std_logic_vector(15 downto 0));
+end zpuio;
+
+architecture behave of zpuio is
+
+signal timer_read : std_logic_vector(7 downto 0);
+--signal timer_write : std_logic_vector(7 downto 0);
+signal timer_we : std_logic;
+
+
+signal io_busy : std_logic;
+signal io_read : std_logic_vector(7 downto 0);
+--signal io_write : std_logic_vector(7 downto 0);
+signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit);
+signal io_writeEnable : std_logic;
+signal Enable : std_logic;
+
+signal		  din :  std_logic_vector(7 downto 0);
+signal	 		  dout : std_logic_vector(7 downto 0);
+signal			  adr : std_logic_vector(15 downto 0);
+signal			  break : std_logic;
+signal			  we : std_logic;
+signal			  re : std_logic;
+
+
+-- uart forwarding...
+
+signal uartTXPending : std_logic;
+signal uartTXCleared : std_logic;
+signal uartData : std_logic_vector(7 downto 0);
+
+signal readingTimer : std_logic;
+
+
+
+
+signal			  mem_busy : std_logic;
+signal			  mem_read : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_write : std_logic_vector(wordSize-1 downto 0);
+signal			  mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
+signal			  mem_writeEnable : std_logic; 
+signal			  mem_readEnable : std_logic;
+signal			  mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
+
+
+
+
+--signal			  io_mem_read : std_logic_vector(7 downto 0);
+--signal			  io_mem_writeEnable : std_logic; 
+--signal			  io_mem_readEnable : std_logic;
+signal			  io_readEnable : std_logic;
+
+
+
+
+
+begin
+
+	io_addr <= mem_addr(maxAddrBit downto minAddrBit);
+	
+	timerinst: timer port map (
+       clk => cpu_clk,
+		 areset => areset,
+		 we => timer_we,
+		 din => mem_write(7 downto 0),
+		 adr => io_addr(4 downto 2),
+		 dout => timer_read);
+
+		zpu: zpu_core port map (
+		clk => cpu_clk ,
+	 	areset => areset,
+ 		in_mem_busy => mem_busy, 
+ 		mem_read => mem_read,
+ 		mem_write => mem_write, 
+		out_mem_addr => mem_addr, 
+		out_mem_writeEnable => mem_writeEnable,  
+		out_mem_readEnable => mem_readEnable,
+ 		mem_writeMask => mem_writeMask, 
+ 		interrupt => '0',
+ 		break  => break);
+
+
+
+
+	-- Read/write are on different addresses
+	-- The registers are 8 bits and mapped to bit[7:0]
+	-- 
+	-- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) 
+	--        Read : Reads from UART RX FIFO (4 byte FIFO)
+	-- 0xC004 Read : UART status register
+	--                       Bit 0 = RX FIFO empty
+	--                       Bit 1 = TX FIFO full
+	-- 0xA000 Skrive: LED's (8 stk.)
+	
+	-- 0x9000 Write: bit 0: 1= reset counter
+	-- 			   0= counter running
+	-- 		  bit 1: 1= sample counter (when set to 1)
+	-- 			   0=not used
+	-- 	 Read : counter bit[7:0]
+	-- 0x9004 Read: counter bit [15:8]
+	-- 0x9008 Read: counter bit [23:16]
+	-- 0x900C Read: counter bit [31:24]
+	-- 0x9010 Read: counter bit [39:32]
+	-- 0x9014 Read: counter bit [47:40]
+	-- 0x9018 Read: counter bit [55:48]
+	-- 0x901C Read: counter bit [63:56]
+	-- 
+	-- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz)
+	
+	fauxUart:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			io_busy <= '0';
+			uartTXPending <= '0';
+			timer_we <= '0';
+			io_busy <= '0';
+			uartData <= x"58"; -- 'X'
+			readingTimer <= '0';
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			timer_we <= '0';
+			io_busy <= '0';
+			if uartTXCleared = '1' then
+				uartTXPending <= '0';
+			end if;
+		
+			if io_writeEnable = '1' then
+				if io_addr=x"1000" then
+					-- Write to UART
+					uartData <= mem_write(7 downto 0);
+					uartTXPending <= '1';
+					io_busy <= '1';
+ 				elsif io_addr(12)='1' then
+ 					timer_we <= '1';
+					io_busy <= '1';
+				else
+					report "Illegal IO write" severity failure;
+				end if;
+			end if;
+			if (io_readEnable = '1') then
+				if io_addr=x"1001" then
+					io_read <= (0=>'1',  		-- recieve empty
+ 					            1 => uartTXPending,   -- tx full
+ 					            others => '0');
+ 					io_busy <= '1';
+ 				elsif io_addr(12)='1' then
+ 					readingTimer <= '1';
+ 					io_busy <= '1';
+ 				elsif io_addr(11)='1' then
+ 					io_read <= ZPU_Frequency;
+ 					io_busy <= '1';
+				else
+					report "Illegal IO read" severity failure;
+				end if;
+				
+			else 
+				if (readingTimer = '1') then
+					readingTimer <= '0';
+ 					io_read <= timer_read;
+ 					io_busy <= '0';
+ 				else
+					io_read <= (others => '1');
+ 				end if;
+			end if;
+		end if;
+	end process;
+
+
+	forwardUARTOutputToARM:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			uartTXCleared <= '0';
+		elsif (cpu_clk = '1' and cpu_clk'event) then
+			if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then
+				uartTXCleared <= cpu_din(0);
+			else
+				uartTXCleared <= uartTXCleared;
+			end if;
+		end if;
+	end process;	
+
+	cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z');
+	cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z');
+	
+	io_writeEnable <= mem_writeEnable and mem_addr(ioBit);
+--	io_readEnable <= mem_readEnable and mem_addr(ioBit);
+	mem_busy <= io_busy or io_readEnable;
+
+	-- Memory reads either come from IO or DRAM. We need to pick the right one.
+	memorycontrol:
+	process(cpu_clk, areset)
+	begin
+		if areset = '1' then
+			io_readEnable <= '0';
+
+		
+		elsif (cpu_clk'event and cpu_clk = '1') then
+			mem_read <= (others => '0');
+			 
+			if mem_addr(ioBit)='1' and mem_readEnable='1' then
+				io_readEnable <= '1';
+			end if;
+			if io_readEnable='1' and io_busy='0' then
+				io_readEnable <= '0';
+				mem_read(7 downto 0) <= io_read;
+			end if;
+			
+		end if;
+	end process;
+
+
+end behave;
diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd
new file mode 100644
index 0000000..30c3e46
--- /dev/null
+++ b/zpu/hdl/zpu4/src/zpupkg.vhd
@@ -0,0 +1,168 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+library work;
+use work.zpu_config.all;
+
+package zpupkg is
+
+	-- This bit is set for read/writes to IO
+	-- FIX!!! eventually this should be set to wordSize-1 so as to
+	-- to make the address of IO independent of amount of memory
+	-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
+	-- libraries.
+	
+	constant byteBits			: integer := wordPower-3; -- # of bits in a word that addresses bytes
+	constant maxAddrBit			: integer := maxAddrBitIncIO-1;
+	constant ioBit				: integer := maxAddrBit+1;
+	constant wordSize			: integer := 2**wordPower;
+	constant wordBytes			: integer := wordSize/8;
+	constant minAddrBit			: integer := byteBits;
+	-- configurable internal stack size. Probably going to be 16 after toolchain is done
+	constant	stack_bits		: integer := 5; 
+	constant	stack_size		: integer := 2**stack_bits; 
+
+	component dualport_ram is
+	port (clk : in std_logic;
+		memAWriteEnable : in std_logic;
+		memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+		memAWrite : in std_logic_vector(wordSize-1 downto 0);
+		memARead : out std_logic_vector(wordSize-1 downto 0);
+		memBWriteEnable : in std_logic;
+		memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
+		memBWrite : in std_logic_vector(wordSize-1 downto 0);
+		memBRead : out std_logic_vector(wordSize-1 downto 0));
+	end component;
+
+	component dram is
+		port (clk : in std_logic;
+			areset : in std_logic;
+			mem_writeEnable : in std_logic;
+			mem_readEnable : in std_logic;
+			mem_addr : in std_logic_vector(maxAddrBit downto 0);
+			mem_write : in std_logic_vector(wordSize-1 downto 0);
+			mem_read : out std_logic_vector(wordSize-1 downto 0);
+			mem_busy : out std_logic;
+			mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
+	end component;
+
+
+	component trace is
+	  port(
+	       	clk         : in std_logic;
+	       	begin_inst  : in std_logic;
+	       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
+			opcode		: in std_logic_vector(7 downto 0);
+			sp			: in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
+			memA		: in std_logic_vector(wordSize-1 downto 0);
+			memB		: in std_logic_vector(wordSize-1 downto 0);
+			busy         : in std_logic;
+			intSp		: in std_logic_vector(stack_bits-1 downto 0)
+			);
+	end component;
+
+	component zpu_core is
+    port ( clk : in std_logic;
+	 		  areset : in std_logic;
+	 		  enable : in std_logic; 
+	 		  in_mem_busy : in std_logic; 
+	 		  mem_read : in std_logic_vector(wordSize-1 downto 0);
+	 		  mem_write : out std_logic_vector(wordSize-1 downto 0);
+			  out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
+			  out_mem_writeEnable : out std_logic; 
+			  out_mem_readEnable : out std_logic;
+	 		  mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
+	 		  interrupt : in std_logic;
+	 		  break : out std_logic);
+	end component;
+
+
+	
+	component timer is
+	  port(
+	       clk              : in std_logic;
+			 areset				: in std_logic;
+			 we					: in std_logic;
+			 din					: in std_logic_vector(7 downto 0);
+			 adr					: in std_logic_vector(2 downto 0);
+			 dout					: out std_logic_vector(7 downto 0));
+	end component;
+
+	component  zpuio is
+		port (	areset			: in std_logic;
+				cpu_clk			: in std_logic;
+				clk_status		: in std_logic_vector(2 downto 0);
+				cpu_din			: in std_logic_vector(15 downto 0);
+				cpu_a			: in std_logic_vector(20 downto 0);
+				cpu_we			: in std_logic_vector(1 downto 0);
+				cpu_re			: in std_logic;
+				cpu_dout		: inout std_logic_vector(15 downto 0));
+	end component;
+
+
+
+	
+	-- opcode decode constants
+	constant	OpCode_Im		: std_logic_vector(7 downto 7) := "1";
+	constant	OpCode_StoreSP	: std_logic_vector(7 downto 5) := "010";
+	constant	OpCode_LoadSP	: std_logic_vector(7 downto 5) := "011";
+	constant	OpCode_Emulate	: std_logic_vector(7 downto 5) := "001";
+	constant	OpCode_AddSP	: std_logic_vector(7 downto 4) := "0001";
+	constant	OpCode_Short	: std_logic_vector(7 downto 4) := "0000";
+	
+	constant	OpCode_Break	: std_logic_vector(3 downto 0) := "0000";
+	constant	OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
+	constant	OpCode_PushSP	: std_logic_vector(3 downto 0) := "0010";
+	constant	OpCode_PushInt	: std_logic_vector(3 downto 0) := "0011";
+	
+	constant	OpCode_PopPC	: std_logic_vector(3 downto 0) := "0100";
+	constant	OpCode_Add		: std_logic_vector(3 downto 0) := "0101";
+	constant	OpCode_And		: std_logic_vector(3 downto 0) := "0110";
+	constant	OpCode_Or		: std_logic_vector(3 downto 0) := "0111";
+	
+	constant	OpCode_Load		: std_logic_vector(3 downto 0) := "1000";
+	constant	OpCode_Not		: std_logic_vector(3 downto 0) := "1001";
+	constant	OpCode_Flip		: std_logic_vector(3 downto 0) := "1010";
+	constant	OpCode_Nop		: std_logic_vector(3 downto 0) := "1011";
+	
+	constant	OpCode_Store	: std_logic_vector(3 downto 0) := "1100";
+	constant	OpCode_PopSP	: std_logic_vector(3 downto 0) := "1101";
+	constant	OpCode_Compare	: std_logic_vector(3 downto 0) := "1110";
+	constant	OpCode_PopInt	: std_logic_vector(3 downto 0) := "1111";
+	
+	constant	OpCode_Lessthan				: std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
+	constant	OpCode_Lessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
+	constant	OpCode_Ulessthan			: std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
+	constant	OpCode_Ulessthanorequal		: std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
+
+	constant	OpCode_Swap					: std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
+	constant	OpCode_Mult					: std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
+	
+	constant	OpCode_Lshiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
+	constant	OpCode_Ashiftleft			: std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
+	constant	OpCode_Ashiftright			: std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
+	constant	OpCode_Call					: std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
+
+	constant	OpCode_Eq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
+	constant	OpCode_Neq					: std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
+
+	constant	OpCode_Sub					: std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
+	constant	OpCode_Loadb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
+	constant	OpCode_Storeb				: std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
+
+	constant	OpCode_Eqbranch				: std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
+	constant	OpCode_Neqbranch			: std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
+	constant	OpCode_Poppcrel				: std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
+
+	constant	OpCode_Pushspadd			: std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
+	constant	OpCode_Mult16x16			: std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
+	constant	OpCode_Callpcrel			: std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
+	
+
+
+	constant OpCode_Size		: integer := 8;
+
+
+		
+end zpupkg;
diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh
new file mode 100644
index 0000000..51ff3de
--- /dev/null
+++ b/zpu/hdl/zpu4/test/dmips/build.sh
@@ -0,0 +1,3 @@
+zpu-elf-gcc -DTIME $ZPUDIR/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -abel -o dmips.elf
+zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf
+zpu-elf-objcopy -O binary dmips.elf dmips.bin
diff --git a/zpu/hdl/zpu4/test/dmips/dmips.bin b/zpu/hdl/zpu4/test/dmips/dmips.bin
new file mode 100644
index 0000000..1330fe3
Binary files /dev/null and b/zpu/hdl/zpu4/test/dmips/dmips.bin differ
diff --git a/zpu/hdl/zpu4/test/dmips/dmips.elf b/zpu/hdl/zpu4/test/dmips/dmips.elf
new file mode 100644
index 0000000..7254a5d
Binary files /dev/null and b/zpu/hdl/zpu4/test/dmips/dmips.elf differ
diff --git a/zpu/hdl/zpu4/test/dmips/dmips.ram b/zpu/hdl/zpu4/test/dmips/dmips.ram
new file mode 100644
index 0000000..27b991d
--- /dev/null
+++ b/zpu/hdl/zpu4/test/dmips/dmips.ram
@@ -0,0 +1,3507 @@
+0 => x"0b0b0b0b",
+1 => x"80700b0b",
+2 => x"80dde00c",
+3 => x"3a0b0b0b",
+4 => x"b9990400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"0bb9e02d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
+104 => x"71715351",
+105 => x"020d0406",
+106 => x"73830609",
+107 => x"81058205",
+108 => x"832b0b2b",
+109 => x"0772fc06",
+110 => x"0c515104",
+111 => x"00000000",
+112 => x"72098105",
+113 => x"72050970",
+114 => x"81050906",
+115 => x"0a810653",
+116 => x"51040000",
+117 => x"00000000",
+118 => x"00000000",
+119 => x"00000000",
+120 => x"72098105",
+121 => x"72050970",
+122 => x"81050906",
+123 => x"0a098106",
+124 => x"53510400",
+125 => x"00000000",
+126 => x"00000000",
+127 => x"00000000",
+128 => x"71098105",
+129 => x"52040000",
+130 => x"00000000",
+131 => x"00000000",
+132 => x"00000000",
+133 => x"00000000",
+134 => x"00000000",
+135 => x"00000000",
+136 => x"72720981",
+137 => x"05055351",
+138 => x"04000000",
+139 => x"00000000",
+140 => x"00000000",
+141 => x"00000000",
+142 => x"00000000",
+143 => x"00000000",
+144 => x"72097206",
+145 => x"73730906",
+146 => x"07535104",
+147 => x"00000000",
+148 => x"00000000",
+149 => x"00000000",
+150 => x"00000000",
+151 => x"00000000",
+152 => x"71fc0608",
+153 => x"72830609",
+154 => x"81058305",
+155 => x"1010102a",
+156 => x"81ff0652",
+157 => x"04000000",
+158 => x"00000000",
+159 => x"00000000",
+160 => x"71fc0608",
+161 => x"0b0b80dd",
+162 => x"cc738306",
+163 => x"10100508",
+164 => x"060b0b0b",
+165 => x"88aa0400",
+166 => x"00000000",
+167 => x"00000000",
+168 => x"80088408",
+169 => x"88087575",
+170 => x"0b0b0ba1",
+171 => x"c92d5050",
+172 => x"80085688",
+173 => x"0c840c80",
+174 => x"0c510400",
+175 => x"00000000",
+176 => x"80088408",
+177 => x"88087575",
+178 => x"0b0b0ba2",
+179 => x"8d2d5050",
+180 => x"80085688",
+181 => x"0c840c80",
+182 => x"0c510400",
+183 => x"00000000",
+184 => x"72097081",
+185 => x"0509060a",
+186 => x"8106ff05",
+187 => x"70547106",
+188 => x"73097274",
+189 => x"05ff0506",
+190 => x"07515151",
+191 => x"04000000",
+192 => x"72097081",
+193 => x"0509060a",
+194 => x"098106ff",
+195 => x"05705471",
+196 => x"06730972",
+197 => x"7405ff05",
+198 => x"06075151",
+199 => x"51040000",
+200 => x"05ff0504",
+201 => x"00000000",
+202 => x"00000000",
+203 => x"00000000",
+204 => x"00000000",
+205 => x"00000000",
+206 => x"00000000",
+207 => x"00000000",
+208 => x"810b0b0b",
+209 => x"80dddc0c",
+210 => x"51040000",
+211 => x"00000000",
+212 => x"00000000",
+213 => x"00000000",
+214 => x"00000000",
+215 => x"00000000",
+216 => x"71810552",
+217 => x"04000000",
+218 => x"00000000",
+219 => x"00000000",
+220 => x"00000000",
+221 => x"00000000",
+222 => x"00000000",
+223 => x"00000000",
+224 => x"00000000",
+225 => x"00000000",
+226 => x"00000000",
+227 => x"00000000",
+228 => x"00000000",
+229 => x"00000000",
+230 => x"00000000",
+231 => x"00000000",
+232 => x"02840572",
+233 => x"10100552",
+234 => x"04000000",
+235 => x"00000000",
+236 => x"00000000",
+237 => x"00000000",
+238 => x"00000000",
+239 => x"00000000",
+240 => x"00000000",
+241 => x"00000000",
+242 => x"00000000",
+243 => x"00000000",
+244 => x"00000000",
+245 => x"00000000",
+246 => x"00000000",
+247 => x"00000000",
+248 => x"717105ff",
+249 => x"05715351",
+250 => x"020d0400",
+251 => x"00000000",
+252 => x"00000000",
+253 => x"00000000",
+254 => x"00000000",
+255 => x"00000000",
+256 => x"83d93f80",
+257 => x"c78e3f04",
+258 => x"10101010",
+259 => x"10101010",
+260 => x"10101010",
+261 => x"10101010",
+262 => x"10101010",
+263 => x"10101010",
+264 => x"10101010",
+265 => x"10101053",
+266 => x"51047381",
+267 => x"ff067383",
+268 => x"06098105",
+269 => x"83051010",
+270 => x"102b0772",
+271 => x"fc060c51",
+272 => x"51043c04",
+273 => x"72728072",
+274 => x"8106ff05",
+275 => x"09720605",
+276 => x"71105272",
+277 => x"0a100a53",
+278 => x"72ed3851",
+279 => x"51535104",
+280 => x"ff3d0d0b",
+281 => x"0b80edd0",
+282 => x"08528412",
+283 => x"08708106",
+284 => x"515170f6",
+285 => x"38710881",
+286 => x"ff06800c",
+287 => x"833d0d04",
+288 => x"ff3d0d0b",
+289 => x"0b80edd0",
+290 => x"08528412",
+291 => x"08700a10",
+292 => x"0a708106",
+293 => x"51515170",
+294 => x"f1387372",
+295 => x"0c833d0d",
+296 => x"0480dddc",
+297 => x"08802ea8",
+298 => x"38838080",
+299 => x"0b0b0b80",
+300 => x"edd00c82",
+301 => x"a0800b0b",
+302 => x"0b80edd4",
+303 => x"0c829080",
+304 => x"0b80ede4",
+305 => x"0c0b0b80",
+306 => x"edd80b80",
+307 => x"ede80c04",
+308 => x"f8808080",
+309 => x"a40b0b0b",
+310 => x"80edd00c",
+311 => x"f8808082",
+312 => x"800b0b0b",
+313 => x"80edd40c",
+314 => x"f8808084",
+315 => x"800b80ed",
+316 => x"e40cf880",
+317 => x"8080940b",
+318 => x"80ede80c",
+319 => x"f8808080",
+320 => x"9c0b80ed",
+321 => x"e00cf880",
+322 => x"8080a00b",
+323 => x"80edec0c",
+324 => x"04f23d0d",
+325 => x"600b0b80",
+326 => x"edd40856",
+327 => x"5d82750c",
+328 => x"8059805a",
+329 => x"800b8f3d",
+330 => x"71101017",
+331 => x"70085957",
+332 => x"5d5b8076",
+333 => x"81ff067c",
+334 => x"832b5658",
+335 => x"5276537b",
+336 => x"5196bc3f",
+337 => x"7d7f7a72",
+338 => x"077c7207",
+339 => x"71716081",
+340 => x"05415f5d",
+341 => x"5b595755",
+342 => x"7a8724bb",
+343 => x"380b0b80",
+344 => x"edd4087b",
+345 => x"10101170",
+346 => x"08585155",
+347 => x"807681ff",
+348 => x"067c832b",
+349 => x"56585276",
+350 => x"537b5196",
+351 => x"823f7d7f",
+352 => x"7a72077c",
+353 => x"72077171",
+354 => x"60810541",
+355 => x"5f5d5b59",
+356 => x"5755877b",
+357 => x"25c73876",
+358 => x"7d0c7784",
+359 => x"1e0c7c80",
+360 => x"0c903d0d",
+361 => x"04ff3d0d",
+362 => x"80eddc33",
+363 => x"5170a738",
+364 => x"80dde808",
+365 => x"70085252",
+366 => x"70802e94",
+367 => x"38841280",
+368 => x"dde80c70",
+369 => x"2d80dde8",
+370 => x"08700852",
+371 => x"5270ee38",
+372 => x"810b80ed",
+373 => x"dc34833d",
+374 => x"0d040480",
+375 => x"3d0d0b0b",
+376 => x"80edcc08",
+377 => x"802e8e38",
+378 => x"0b0b0b0b",
+379 => x"800b802e",
+380 => x"09810685",
+381 => x"38823d0d",
+382 => x"040b0b80",
+383 => x"edcc510b",
+384 => x"0b0bf3fc",
+385 => x"3f823d0d",
+386 => x"0404ff3d",
+387 => x"0d028f05",
+388 => x"3352718a",
+389 => x"2e8a3871",
+390 => x"51fce53f",
+391 => x"833d0d04",
+392 => x"8d51fcdc",
+393 => x"3f7151fc",
+394 => x"d73f833d",
+395 => x"0d04ce3d",
+396 => x"0db53d70",
+397 => x"70840552",
+398 => x"088c8a5c",
+399 => x"56a53d5e",
+400 => x"5c807570",
+401 => x"81055733",
+402 => x"765b5558",
+403 => x"73782e80",
+404 => x"c1388e3d",
+405 => x"5b73a52e",
+406 => x"09810680",
+407 => x"c5387870",
+408 => x"81055a33",
+409 => x"547380e4",
+410 => x"2e81b638",
+411 => x"7380e424",
+412 => x"80c63873",
+413 => x"80e32ea1",
+414 => x"388052a5",
+415 => x"51792d80",
+416 => x"52735179",
+417 => x"2d821858",
+418 => x"78708105",
+419 => x"5a335473",
+420 => x"c4387780",
+421 => x"0cb43d0d",
+422 => x"047b841d",
+423 => x"83123356",
+424 => x"5d578052",
+425 => x"7351792d",
+426 => x"81187970",
+427 => x"81055b33",
+428 => x"555873ff",
+429 => x"a038db39",
+430 => x"7380f32e",
+431 => x"098106ff",
+432 => x"b8387b84",
+433 => x"1d710859",
+434 => x"5d568077",
+435 => x"33555673",
+436 => x"762e8d38",
+437 => x"81167018",
+438 => x"70335755",
+439 => x"5674f538",
+440 => x"ff165580",
+441 => x"7625ffa0",
+442 => x"38767081",
+443 => x"05583354",
+444 => x"80527351",
+445 => x"792d8118",
+446 => x"75ff1757",
+447 => x"57588076",
+448 => x"25ff8538",
+449 => x"76708105",
+450 => x"58335480",
+451 => x"52735179",
+452 => x"2d811875",
+453 => x"ff175757",
+454 => x"58758024",
+455 => x"cc38fee8",
+456 => x"397b841d",
+457 => x"71087071",
+458 => x"9f2c5953",
+459 => x"595d5680",
+460 => x"75248195",
+461 => x"38757d7c",
+462 => x"58565480",
+463 => x"5773772e",
+464 => x"098106b6",
+465 => x"38b07b34",
+466 => x"02b50556",
+467 => x"7a762e97",
+468 => x"38ff1656",
+469 => x"75337570",
+470 => x"81055734",
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+3133 => x"000030e8",
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+3151 => x"00003130",
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+3153 => x"00003138",
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+3161 => x"00003158",
+3162 => x"00003160",
+3163 => x"00003160",
+3164 => x"00003168",
+3165 => x"00003168",
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+3167 => x"00003170",
+3168 => x"00003178",
+3169 => x"00003178",
+3170 => x"00003180",
+3171 => x"00003180",
+3172 => x"00003188",
+3173 => x"00003188",
+3174 => x"00003190",
+3175 => x"00003190",
+3176 => x"00003198",
+3177 => x"00003198",
+3178 => x"000031a0",
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+3181 => x"000031a8",
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+3183 => x"000031b0",
+3184 => x"000031b8",
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+3186 => x"000031c0",
+3187 => x"000031c0",
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+3189 => x"000031c8",
+3190 => x"000031d0",
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+3193 => x"000031d8",
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+3196 => x"000031e8",
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+3205 => x"00003208",
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+3210 => x"00003220",
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+3215 => x"00003230",
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+3225 => x"00003258",
+3226 => x"00003260",
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+3230 => x"00003270",
+3231 => x"00003270",
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+3233 => x"00003278",
+3234 => x"00003280",
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+3247 => x"000032b0",
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+3250 => x"000032c0",
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+3253 => x"000032c8",
+3254 => x"000032d0",
+3255 => x"000032d0",
+3256 => x"000032d8",
+3257 => x"000032d8",
+3258 => x"000032e0",
+3259 => x"000032e0",
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+3273 => x"00003318",
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+3276 => x"00003328",
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+3279 => x"00000000",
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+3323 => x"1234e66d",
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+3434 => x"00000000",
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+3436 => x"00000000",
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+3441 => x"00000000",
+3442 => x"00000000",
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+3450 => x"00000000",
+3451 => x"00000000",
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+3453 => x"00000000",
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+3478 => x"00000000",
+3479 => x"00000000",
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+3481 => x"00000000",
+3482 => x"00000000",
+3483 => x"00000000",
+3484 => x"00000000",
+3485 => x"00000000",
+3486 => x"00000000",
+3487 => x"00000000",
+3488 => x"00000000",
+3489 => x"00000000",
+3490 => x"00000000",
+3491 => x"00000000",
+3492 => x"00000000",
+3493 => x"00000000",
+3494 => x"00000000",
+3495 => x"00000000",
+3496 => x"00000000",
+3497 => x"00000000",
+3498 => x"00000000",
+3499 => x"00000000",
+3500 => x"00000000",
+3501 => x"00000000",
+3502 => x"00002dc0",
+3503 => x"ffffffff",
+3504 => x"00000000",
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+3506 => x"00000000",
diff --git a/zpu/hdl/zpu4/test/hello/build.sh b/zpu/hdl/zpu4/test/hello/build.sh
new file mode 100644
index 0000000..0d81138
--- /dev/null
+++ b/zpu/hdl/zpu4/test/hello/build.sh
@@ -0,0 +1,3 @@
+zpu-elf-gcc -O3 -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections  -g
+zpu-elf-objdump --disassemble-all >hello.dis hello.elf
+zpu-elf-objcopy -O binary hello.elf hello.bin
diff --git a/zpu/hdl/zpu4/test/hello/hello.bin b/zpu/hdl/zpu4/test/hello/hello.bin
new file mode 100644
index 0000000..fe17308
Binary files /dev/null and b/zpu/hdl/zpu4/test/hello/hello.bin differ
diff --git a/zpu/hdl/zpu4/test/hello/hello.c b/zpu/hdl/zpu4/test/hello/hello.c
new file mode 100644
index 0000000..ea3dbb8
--- /dev/null
+++ b/zpu/hdl/zpu4/test/hello/hello.c
@@ -0,0 +1,51 @@
+/*
+
+zpu-elf-gcc -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections  -g
+zpu-elf-objdump --disassemble-all >hello.dis hello.elf
+zpu-elf-objcopy -O binary hello.elf hello.bin
+ 
+ * */
+#include <stdio.h>
+
+int j;
+int k;
+
+int main(int argc, char **argv)
+{
+	int i;
+  for (i=0; i< 10; i++)
+    {
+      puts("Hello world 1\n");
+      puts("Hello world 2\n");
+    j=-4;
+    if ((j>>1)!=-2)
+    {
+    	abort();
+    }
+    
+    k=10;
+    if (k*j!=-40)
+    {
+    	abort();
+    }
+    
+    j=10;
+    k=10000000;
+    if (k*j!=100000000)
+    {
+    	abort();
+    }
+    
+    j=0x80000000;
+    k=0xffffffff;
+    if (j>k)
+    {
+    	abort();
+    }
+    }
+    if (i!=10)
+    {
+    	abort();
+    }
+    
+}
diff --git a/zpu/hdl/zpu4/test/hello/hello.elf b/zpu/hdl/zpu4/test/hello/hello.elf
new file mode 100644
index 0000000..999b9a3
Binary files /dev/null and b/zpu/hdl/zpu4/test/hello/hello.elf differ
diff --git a/zpu/hdl/zpu4/test/hello/hello.ram b/zpu/hdl/zpu4/test/hello/hello.ram
new file mode 100644
index 0000000..f310151
--- /dev/null
+++ b/zpu/hdl/zpu4/test/hello/hello.ram
@@ -0,0 +1,3165 @@
+0 => x"0b0b0b0b",
+1 => x"80700b0b",
+2 => x"80d3900c",
+3 => x"3a0b0b80",
+4 => x"c8b20400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"80c8fb2d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
+17 => x"72830609",
+18 => x"81058205",
+19 => x"832b2a83",
+20 => x"ffff0652",
+21 => x"04000000",
+22 => x"00000000",
+23 => x"00000000",
+24 => x"71fd0608",
+25 => x"83ffff73",
+26 => x"83060981",
+27 => x"05820583",
+28 => x"2b2b0906",
+29 => x"7383ffff",
+30 => x"0b0b0b0b",
+31 => x"83a70400",
+32 => x"72098105",
+33 => x"72057373",
+34 => x"09060906",
+35 => x"73097306",
+36 => x"070a8106",
+37 => x"53510400",
+38 => x"00000000",
+39 => x"00000000",
+40 => x"72722473",
+41 => x"732e0753",
+42 => x"51040000",
+43 => x"00000000",
+44 => x"00000000",
+45 => x"00000000",
+46 => x"00000000",
+47 => x"00000000",
+48 => x"71737109",
+49 => x"71068106",
+50 => x"30720a10",
+51 => x"0a720a10",
+52 => x"0a31050a",
+53 => x"81065151",
+54 => x"53510400",
+55 => x"00000000",
+56 => x"72722673",
+57 => x"732e0753",
+58 => x"51040000",
+59 => x"00000000",
+60 => x"00000000",
+61 => x"00000000",
+62 => x"00000000",
+63 => x"00000000",
+64 => x"00000000",
+65 => x"00000000",
+66 => x"00000000",
+67 => x"00000000",
+68 => x"00000000",
+69 => x"00000000",
+70 => x"00000000",
+71 => x"00000000",
+72 => x"0b0b0b88",
+73 => x"c4040000",
+74 => x"00000000",
+75 => x"00000000",
+76 => x"00000000",
+77 => x"00000000",
+78 => x"00000000",
+79 => x"00000000",
+80 => x"720a722b",
+81 => x"0a535104",
+82 => x"00000000",
+83 => x"00000000",
+84 => x"00000000",
+85 => x"00000000",
+86 => x"00000000",
+87 => x"00000000",
+88 => x"72729f06",
+89 => x"0981050b",
+90 => x"0b0b88a7",
+91 => x"05040000",
+92 => x"00000000",
+93 => x"00000000",
+94 => x"00000000",
+95 => x"00000000",
+96 => x"72722aff",
+97 => x"739f062a",
+98 => x"0974090a",
+99 => x"8106ff05",
+100 => x"06075351",
+101 => x"04000000",
+102 => x"00000000",
+103 => x"00000000",
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+2647 => x"6f20776f",
+2648 => x"726c6420",
+2649 => x"320a0000",
+2650 => x"0a000000",
+2651 => x"43000000",
+2652 => x"64756d6d",
+2653 => x"792e6578",
+2654 => x"65000000",
+2655 => x"00ffffff",
+2656 => x"ff00ffff",
+2657 => x"ffff00ff",
+2658 => x"ffffff00",
+2659 => x"00000000",
+2660 => x"00000000",
+2661 => x"00000000",
+2662 => x"00003170",
+2663 => x"000029a0",
+2664 => x"00000000",
+2665 => x"00002c08",
+2666 => x"00002c64",
+2667 => x"00002cc0",
+2668 => x"00000000",
+2669 => x"00000000",
+2670 => x"00000000",
+2671 => x"00000000",
+2672 => x"00000000",
+2673 => x"00000000",
+2674 => x"00000000",
+2675 => x"00000000",
+2676 => x"00000000",
+2677 => x"0000296c",
+2678 => x"00000000",
+2679 => x"00000000",
+2680 => x"00000000",
+2681 => x"00000000",
+2682 => x"00000000",
+2683 => x"00000000",
+2684 => x"00000000",
+2685 => x"00000000",
+2686 => x"00000000",
+2687 => x"00000000",
+2688 => x"00000000",
+2689 => x"00000000",
+2690 => x"00000000",
+2691 => x"00000000",
+2692 => x"00000000",
+2693 => x"00000000",
+2694 => x"00000000",
+2695 => x"00000000",
+2696 => x"00000000",
+2697 => x"00000000",
+2698 => x"00000000",
+2699 => x"00000000",
+2700 => x"00000000",
+2701 => x"00000000",
+2702 => x"00000000",
+2703 => x"00000000",
+2704 => x"00000000",
+2705 => x"00000000",
+2706 => x"00000001",
+2707 => x"330eabcd",
+2708 => x"1234e66d",
+2709 => x"deec0005",
+2710 => x"000b0000",
+2711 => x"00000000",
+2712 => x"00000000",
+2713 => x"00000000",
+2714 => x"00000000",
+2715 => x"00000000",
+2716 => x"00000000",
+2717 => x"00000000",
+2718 => x"00000000",
+2719 => x"00000000",
+2720 => x"00000000",
+2721 => x"00000000",
+2722 => x"00000000",
+2723 => x"00000000",
+2724 => x"00000000",
+2725 => x"00000000",
+2726 => x"00000000",
+2727 => x"00000000",
+2728 => x"00000000",
+2729 => x"00000000",
+2730 => x"00000000",
+2731 => x"00000000",
+2732 => x"00000000",
+2733 => x"00000000",
+2734 => x"00000000",
+2735 => x"00000000",
+2736 => x"00000000",
+2737 => x"00000000",
+2738 => x"00000000",
+2739 => x"00000000",
+2740 => x"00000000",
+2741 => x"00000000",
+2742 => x"00000000",
+2743 => x"00000000",
+2744 => x"00000000",
+2745 => x"00000000",
+2746 => x"00000000",
+2747 => x"00000000",
+2748 => x"00000000",
+2749 => x"00000000",
+2750 => x"00000000",
+2751 => x"00000000",
+2752 => x"00000000",
+2753 => x"00000000",
+2754 => x"00000000",
+2755 => x"00000000",
+2756 => x"00000000",
+2757 => x"00000000",
+2758 => x"00000000",
+2759 => x"00000000",
+2760 => x"00000000",
+2761 => x"00000000",
+2762 => x"00000000",
+2763 => x"00000000",
+2764 => x"00000000",
+2765 => x"00000000",
+2766 => x"00000000",
+2767 => x"00000000",
+2768 => x"00000000",
+2769 => x"00000000",
+2770 => x"00000000",
+2771 => x"00000000",
+2772 => x"00000000",
+2773 => x"00000000",
+2774 => x"00000000",
+2775 => x"00000000",
+2776 => x"00000000",
+2777 => x"00000000",
+2778 => x"00000000",
+2779 => x"00000000",
+2780 => x"00000000",
+2781 => x"00000000",
+2782 => x"00000000",
+2783 => x"00000000",
+2784 => x"00000000",
+2785 => x"00000000",
+2786 => x"00000000",
+2787 => x"00000000",
+2788 => x"00000000",
+2789 => x"00000000",
+2790 => x"00000000",
+2791 => x"00000000",
+2792 => x"00000000",
+2793 => x"00000000",
+2794 => x"00000000",
+2795 => x"00000000",
+2796 => x"00000000",
+2797 => x"00000000",
+2798 => x"00000000",
+2799 => x"00000000",
+2800 => x"00000000",
+2801 => x"00000000",
+2802 => x"00000000",
+2803 => x"00000000",
+2804 => x"00000000",
+2805 => x"00000000",
+2806 => x"00000000",
+2807 => x"00000000",
+2808 => x"00000000",
+2809 => x"00000000",
+2810 => x"00000000",
+2811 => x"00000000",
+2812 => x"00000000",
+2813 => x"00000000",
+2814 => x"00000000",
+2815 => x"00000000",
+2816 => x"00000000",
+2817 => x"00000000",
+2818 => x"00000000",
+2819 => x"00000000",
+2820 => x"00000000",
+2821 => x"00000000",
+2822 => x"00000000",
+2823 => x"00000000",
+2824 => x"00000000",
+2825 => x"00000000",
+2826 => x"00000000",
+2827 => x"00000000",
+2828 => x"00000000",
+2829 => x"00000000",
+2830 => x"00000000",
+2831 => x"00000000",
+2832 => x"00000000",
+2833 => x"00000000",
+2834 => x"00000000",
+2835 => x"00000000",
+2836 => x"00000000",
+2837 => x"00000000",
+2838 => x"00000000",
+2839 => x"00000000",
+2840 => x"00000000",
+2841 => x"00000000",
+2842 => x"00000000",
+2843 => x"00000000",
+2844 => x"00000000",
+2845 => x"00000000",
+2846 => x"00000000",
+2847 => x"00000000",
+2848 => x"00000000",
+2849 => x"00000000",
+2850 => x"00000000",
+2851 => x"00000000",
+2852 => x"00000000",
+2853 => x"00000000",
+2854 => x"00000000",
+2855 => x"00000000",
+2856 => x"00000000",
+2857 => x"00000000",
+2858 => x"00000000",
+2859 => x"00000000",
+2860 => x"00000000",
+2861 => x"00000000",
+2862 => x"00000000",
+2863 => x"00000000",
+2864 => x"00000000",
+2865 => x"00000000",
+2866 => x"00000000",
+2867 => x"00000000",
+2868 => x"00000000",
+2869 => x"00000000",
+2870 => x"00000000",
+2871 => x"00000000",
+2872 => x"00000000",
+2873 => x"00000000",
+2874 => x"00000000",
+2875 => x"00000000",
+2876 => x"00000000",
+2877 => x"00000000",
+2878 => x"00000000",
+2879 => x"00000000",
+2880 => x"00000000",
+2881 => x"00000000",
+2882 => x"00000000",
+2883 => x"00000000",
+2884 => x"00000000",
+2885 => x"00000000",
+2886 => x"00000000",
+2887 => x"00000000",
+2888 => x"00000000",
+2889 => x"00000000",
+2890 => x"00000000",
+2891 => x"00000000",
+2892 => x"00000000",
+2893 => x"00000000",
+2894 => x"00000000",
+2895 => x"00000000",
+2896 => x"00000000",
+2897 => x"00000000",
+2898 => x"00000000",
+2899 => x"ffffffff",
+2900 => x"00000000",
+2901 => x"00020000",
+2902 => x"00000000",
+2903 => x"00000000",
+2904 => x"00002d58",
+2905 => x"00002d58",
+2906 => x"00002d60",
+2907 => x"00002d60",
+2908 => x"00002d68",
+2909 => x"00002d68",
+2910 => x"00002d70",
+2911 => x"00002d70",
+2912 => x"00002d78",
+2913 => x"00002d78",
+2914 => x"00002d80",
+2915 => x"00002d80",
+2916 => x"00002d88",
+2917 => x"00002d88",
+2918 => x"00002d90",
+2919 => x"00002d90",
+2920 => x"00002d98",
+2921 => x"00002d98",
+2922 => x"00002da0",
+2923 => x"00002da0",
+2924 => x"00002da8",
+2925 => x"00002da8",
+2926 => x"00002db0",
+2927 => x"00002db0",
+2928 => x"00002db8",
+2929 => x"00002db8",
+2930 => x"00002dc0",
+2931 => x"00002dc0",
+2932 => x"00002dc8",
+2933 => x"00002dc8",
+2934 => x"00002dd0",
+2935 => x"00002dd0",
+2936 => x"00002dd8",
+2937 => x"00002dd8",
+2938 => x"00002de0",
+2939 => x"00002de0",
+2940 => x"00002de8",
+2941 => x"00002de8",
+2942 => x"00002df0",
+2943 => x"00002df0",
+2944 => x"00002df8",
+2945 => x"00002df8",
+2946 => x"00002e00",
+2947 => x"00002e00",
+2948 => x"00002e08",
+2949 => x"00002e08",
+2950 => x"00002e10",
+2951 => x"00002e10",
+2952 => x"00002e18",
+2953 => x"00002e18",
+2954 => x"00002e20",
+2955 => x"00002e20",
+2956 => x"00002e28",
+2957 => x"00002e28",
+2958 => x"00002e30",
+2959 => x"00002e30",
+2960 => x"00002e38",
+2961 => x"00002e38",
+2962 => x"00002e40",
+2963 => x"00002e40",
+2964 => x"00002e48",
+2965 => x"00002e48",
+2966 => x"00002e50",
+2967 => x"00002e50",
+2968 => x"00002e58",
+2969 => x"00002e58",
+2970 => x"00002e60",
+2971 => x"00002e60",
+2972 => x"00002e68",
+2973 => x"00002e68",
+2974 => x"00002e70",
+2975 => x"00002e70",
+2976 => x"00002e78",
+2977 => x"00002e78",
+2978 => x"00002e80",
+2979 => x"00002e80",
+2980 => x"00002e88",
+2981 => x"00002e88",
+2982 => x"00002e90",
+2983 => x"00002e90",
+2984 => x"00002e98",
+2985 => x"00002e98",
+2986 => x"00002ea0",
+2987 => x"00002ea0",
+2988 => x"00002ea8",
+2989 => x"00002ea8",
+2990 => x"00002eb0",
+2991 => x"00002eb0",
+2992 => x"00002eb8",
+2993 => x"00002eb8",
+2994 => x"00002ec0",
+2995 => x"00002ec0",
+2996 => x"00002ec8",
+2997 => x"00002ec8",
+2998 => x"00002ed0",
+2999 => x"00002ed0",
+3000 => x"00002ed8",
+3001 => x"00002ed8",
+3002 => x"00002ee0",
+3003 => x"00002ee0",
+3004 => x"00002ee8",
+3005 => x"00002ee8",
+3006 => x"00002ef0",
+3007 => x"00002ef0",
+3008 => x"00002ef8",
+3009 => x"00002ef8",
+3010 => x"00002f00",
+3011 => x"00002f00",
+3012 => x"00002f08",
+3013 => x"00002f08",
+3014 => x"00002f10",
+3015 => x"00002f10",
+3016 => x"00002f18",
+3017 => x"00002f18",
+3018 => x"00002f20",
+3019 => x"00002f20",
+3020 => x"00002f28",
+3021 => x"00002f28",
+3022 => x"00002f30",
+3023 => x"00002f30",
+3024 => x"00002f38",
+3025 => x"00002f38",
+3026 => x"00002f40",
+3027 => x"00002f40",
+3028 => x"00002f48",
+3029 => x"00002f48",
+3030 => x"00002f50",
+3031 => x"00002f50",
+3032 => x"00002f58",
+3033 => x"00002f58",
+3034 => x"00002f60",
+3035 => x"00002f60",
+3036 => x"00002f68",
+3037 => x"00002f68",
+3038 => x"00002f70",
+3039 => x"00002f70",
+3040 => x"00002f78",
+3041 => x"00002f78",
+3042 => x"00002f80",
+3043 => x"00002f80",
+3044 => x"00002f88",
+3045 => x"00002f88",
+3046 => x"00002f90",
+3047 => x"00002f90",
+3048 => x"00002f98",
+3049 => x"00002f98",
+3050 => x"00002fa0",
+3051 => x"00002fa0",
+3052 => x"00002fa8",
+3053 => x"00002fa8",
+3054 => x"00002fb0",
+3055 => x"00002fb0",
+3056 => x"00002fb8",
+3057 => x"00002fb8",
+3058 => x"00002fc0",
+3059 => x"00002fc0",
+3060 => x"00002fc8",
+3061 => x"00002fc8",
+3062 => x"00002fd0",
+3063 => x"00002fd0",
+3064 => x"00002fd8",
+3065 => x"00002fd8",
+3066 => x"00002fe0",
+3067 => x"00002fe0",
+3068 => x"00002fe8",
+3069 => x"00002fe8",
+3070 => x"00002ff0",
+3071 => x"00002ff0",
+3072 => x"00002ff8",
+3073 => x"00002ff8",
+3074 => x"00003000",
+3075 => x"00003000",
+3076 => x"00003008",
+3077 => x"00003008",
+3078 => x"00003010",
+3079 => x"00003010",
+3080 => x"00003018",
+3081 => x"00003018",
+3082 => x"00003020",
+3083 => x"00003020",
+3084 => x"00003028",
+3085 => x"00003028",
+3086 => x"00003030",
+3087 => x"00003030",
+3088 => x"00003038",
+3089 => x"00003038",
+3090 => x"00003040",
+3091 => x"00003040",
+3092 => x"00003048",
+3093 => x"00003048",
+3094 => x"00003050",
+3095 => x"00003050",
+3096 => x"00003058",
+3097 => x"00003058",
+3098 => x"00003060",
+3099 => x"00003060",
+3100 => x"00003068",
+3101 => x"00003068",
+3102 => x"00003070",
+3103 => x"00003070",
+3104 => x"00003078",
+3105 => x"00003078",
+3106 => x"00003080",
+3107 => x"00003080",
+3108 => x"00003088",
+3109 => x"00003088",
+3110 => x"00003090",
+3111 => x"00003090",
+3112 => x"00003098",
+3113 => x"00003098",
+3114 => x"000030a0",
+3115 => x"000030a0",
+3116 => x"000030a8",
+3117 => x"000030a8",
+3118 => x"000030b0",
+3119 => x"000030b0",
+3120 => x"000030b8",
+3121 => x"000030b8",
+3122 => x"000030c0",
+3123 => x"000030c0",
+3124 => x"000030c8",
+3125 => x"000030c8",
+3126 => x"000030d0",
+3127 => x"000030d0",
+3128 => x"000030d8",
+3129 => x"000030d8",
+3130 => x"000030e0",
+3131 => x"000030e0",
+3132 => x"000030e8",
+3133 => x"000030e8",
+3134 => x"000030f0",
+3135 => x"000030f0",
+3136 => x"000030f8",
+3137 => x"000030f8",
+3138 => x"00003100",
+3139 => x"00003100",
+3140 => x"00003108",
+3141 => x"00003108",
+3142 => x"00003110",
+3143 => x"00003110",
+3144 => x"00003118",
+3145 => x"00003118",
+3146 => x"00003120",
+3147 => x"00003120",
+3148 => x"00003128",
+3149 => x"00003128",
+3150 => x"00003130",
+3151 => x"00003130",
+3152 => x"00003138",
+3153 => x"00003138",
+3154 => x"00003140",
+3155 => x"00003140",
+3156 => x"00003148",
+3157 => x"00003148",
+3158 => x"00003150",
+3159 => x"00003150",
+3160 => x"00002970",
+3161 => x"ffffffff",
+3162 => x"00000000",
+3163 => x"ffffffff",
+3164 => x"00000000",
diff --git a/zpu/index.html b/zpu/index.html
new file mode 100644
index 0000000..bb5714f
--- /dev/null
+++ b/zpu/index.html
@@ -0,0 +1,20 @@
+<html>
+<body>
+<h1>Getting started</h1>
+FPGA: check out zpu/hdl, read zpu/hdl/index.html
+<p>
+Software: check out zpu/sw, read zpu/sw/index.html
+<p>
+Docs: check out zpu/docs, this is what's available as of writing. Further documentation exists in the eCosBoard 1.1 product: http://www.zylin.com/ecosboard.htm
+<h2>Other directories</h2>
+You probably don't need or want to download other directories.
+<ul>
+<li>
+gccsrc - the complete GCC toolchain source. Big! Almost certainly not something you need or want to download. This has been moved to /trunk/zpugccsrc to
+avoid subversion choking.
+<li> roadshow - various bits and bobs to demonstrate the ZPU that has not been sorted/reorganized yet.
+
+</ul>
+
+</body>
+</html>
diff --git a/zpu/roadshow/roadshow/build/makefirmware.sh b/zpu/roadshow/roadshow/build/makefirmware.sh
new file mode 100644
index 0000000..b44559b
--- /dev/null
+++ b/zpu/roadshow/roadshow/build/makefirmware.sh
@@ -0,0 +1,13 @@
+echo >$2 ZylinPhiFirmware
+
+if [ x"$3" = x ] ;then
+	echo "No ic300.bit embedded into .phi"
+else
+	echo "Embed ic300.bit into .phi"
+	echo >>$2 "FPGA: `wc -c $3 | grep -o -e \[0-9\]*`"
+	cat >>$2 $1
+fi
+echo "Writing application"
+echo >>$2 "Application: `wc -c $1 | grep -o -e \[0-9\]*`"
+cat >>$2 $1
+echo >>$2 Done
\ No newline at end of file
diff --git a/zpu/roadshow/roadshow/codesize/.cvsignore b/zpu/roadshow/roadshow/codesize/.cvsignore
new file mode 100644
index 0000000..6559932
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/.cvsignore
@@ -0,0 +1 @@
+smallstd.elf
diff --git a/zpu/roadshow/roadshow/codesize/crt0_phi.S b/zpu/roadshow/roadshow/codesize/crt0_phi.S
new file mode 100644
index 0000000..4d654e2
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/crt0_phi.S
@@ -0,0 +1,178 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"crt0.S"
+	
+	
+	
+	
+;	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+; DANGER!!!! 
+; we need to align these code sections to 32 bytes, which
+; means we must not use any assembler instructions that are relaxed
+; at linker time
+; DANGER!!!! 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jsr address
+	
+			im 0		; save R0
+			load
+			im 4		; save R1
+			load
+			im 8		; save R2
+			load
+	
+			fixedim \address
+			call
+			
+			im 8
+			store		; restore R2
+			im 4
+			store		; restore R1
+			im 0
+			store		; restore R0
+	.endm
+
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+		
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+	
+	.macro cimpl funcname
+	; save R0
+	im 0
+	load
+	
+	; save R1
+	im 4
+	load
+	
+	; save R2
+	im 8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im 0
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im 8
+	store
+	
+	; restore R1
+	im 4
+	store
+	
+	; restore r0
+	im 0
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+
+
+/* vectors */
+        .balign 32,0
+# offset 0x0000 0000
+		.globl _start
+_start:
+		; intSp must be 0 when we jump to _premain
+		
+		im ZPU_ID
+		loadsp 0
+		im _cpu_config
+		store
+		config
+		jmp _premain
+
+
+
+/* instruction emulation code */
+
+	.data
+
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
diff --git a/zpu/roadshow/roadshow/codesize/hello.c b/zpu/roadshow/roadshow/codesize/hello.c
new file mode 100644
index 0000000..176275c
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/hello.c
@@ -0,0 +1,9 @@
+/* Simple hello world */
+#include <stdio.h>
+
+
+int main(int argc, char **argv)
+{
+	puts("Hello world\n");
+}
+
diff --git a/zpu/roadshow/roadshow/codesize/index.html b/zpu/roadshow/roadshow/codesize/index.html
new file mode 100644
index 0000000..3f61b4e
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/index.html
@@ -0,0 +1,58 @@
+<html>
+<body>
+<h1>Compiling hello world program with the ZPU GCC toolchain</h1>
+The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has 
+some very basic peripherals defined: counter, timer interrupt and a debug output port. 
+<h1>Installation</h1>
+<ol>
+<li>Install Cygwin. http://www.cygwin.com 
+<li>Start Cygwin bash
+<li>unzip zputoolchain.zip
+<li>Add install/bin from zputoolchain.zip to PATH.<br>
+export PATH=$PATH:<unzipdir>/install/bin
+</ol>
+<h1>Hello world example</h1>
+The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification.
+<p> 
+<code>
+zpu-elf-gcc -Os -zeta hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections<br>
+zpu-elf-size hello.elf<br>
+</code>
+<h1>Optimizing for size</h1>
+The ZPU toolchain produces highly compact code.  
+<ol>
+<li>Since the ZPU GCC toolchain supports standard ANSI C, it is easy to stumble across
+functionality that takes up a lot of space. E.g. the standard printf() function is a beast. Some compilers drop e.g. floating point support
+from the printf() function and thus boast a "smaller" printf() when in fact they have a non-standard printf(). newlib has a standard printf() function
+and an alternative iprintf() function that works only on integers.
+<li>The ZPU ships with default startup code that works across various configurations of the ZPU, so be warned that there is some overhead that will
+not occurr in the final application(anywhere between 1-4kBytes).
+<li>Compilation and linker options matter. The ZPU benefits greatly from the "-Wl,--relax -Wl,--gc-sections" options which is not used by
+all architectures(e.g. GCC ARM does not implement/need -Wl,--relax).  
+</ol> 
+<h2>Small code example</h2>
+<code>
+zpu-elf-gcc -Os -abel smallstd.c -o smallstd.elf -Wl,--relax -Wl,--gc-sections<br>
+zpu-elf-size small.elf<br>
+<br>
+$ zpu-elf-size small.elf<br>
+   text    data     bss     dec     hex filename<br>
+   2845     952      36    3833     ef9 small.elf<br>
+<br>
+</code>
+
+<h2>Even smaller code example</h2>
+If the ZPU implements the optional instructions, the RAM overhead can be reduced significantly.
+<p>
+<code>
+zpu-elf-gcc -Os -abel crt0_phi.S small.c -o small.elf -Wl,--relax -Wl,--gc-sections -nostdlib <br>
+zpu-elf-size small.elf<br>
+<br>
+$ zpu-elf-size small.elf<br>
+   text    data     bss     dec     hex filename<br>
+     56       8       0      64      40 small.elf<br>
+     <br>
+</code>
+
+</body>
+</html>
diff --git a/zpu/roadshow/roadshow/codesize/small.c b/zpu/roadshow/roadshow/codesize/small.c
new file mode 100644
index 0000000..0317343
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/small.c
@@ -0,0 +1,9 @@
+void _premain(void)
+{
+  volatile int *someRegister=(volatile int *)0;
+  volatile int *otherRegister=(volatile int *)4;
+  while (*someRegister!=0)
+    {
+      *otherRegister++;
+    }
+}
diff --git a/zpu/roadshow/roadshow/codesize/small.elf b/zpu/roadshow/roadshow/codesize/small.elf
new file mode 100644
index 0000000..4193a53
Binary files /dev/null and b/zpu/roadshow/roadshow/codesize/small.elf differ
diff --git a/zpu/roadshow/roadshow/codesize/smallstd.c b/zpu/roadshow/roadshow/codesize/smallstd.c
new file mode 100644
index 0000000..5d4b87a
--- /dev/null
+++ b/zpu/roadshow/roadshow/codesize/smallstd.c
@@ -0,0 +1,9 @@
+int main(int argc, char **argv)
+{
+  volatile int *someRegister=(volatile int *)0;
+  volatile int *otherRegister=(volatile int *)4;
+  while (*someRegister!=0)
+    {
+      *otherRegister++;
+    }
+}
diff --git a/zpu/roadshow/roadshow/dhrystone/.cvsignore b/zpu/roadshow/roadshow/dhrystone/.cvsignore
new file mode 100644
index 0000000..3544c3f
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/.cvsignore
@@ -0,0 +1,2 @@
+dhrystone.elf
+dhrystone_zpu.elf
diff --git a/zpu/roadshow/roadshow/dhrystone/RATIONALE b/zpu/roadshow/roadshow/dhrystone/RATIONALE
new file mode 100644
index 0000000..926e046
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/RATIONALE
@@ -0,0 +1,361 @@
+
+
+    Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules
+
+        [published in SIGPLAN Notices 23,8 (Aug. 1988), 49-62]
+
+
+                 Reinhold P. Weicker
+                 Siemens AG, E STE 35
+                 [now: Siemens AG, AUT E 51]
+                 Postfach 3220
+                 D-8520 Erlangen
+                 Germany (West)
+
+
+
+
+1.  Why a Version 2 of Dhrystone?
+
+The Dhrystone benchmark  program  [1]  has  become  a  popular  benchmark  for
+CPU/compiler   performance   measurement,   in   particular  in  the  area  of
+minicomputers, workstations, PC's and microprocesors.  It apparently satisfies
+a  need  for  an  easy-to-use  integer benchmark; it gives a first performance
+indication which is more meaningful than MIPS numbers which, in their  literal
+meaning  (million  instructions  per  second), cannot be used across different
+instruction sets (e.g. RISC  vs.  CISC).   With  the  increasing  use  of  the
+benchmark, it seems necessary to reconsider the benchmark and to check whether
+it can still fulfill this function.  Version 2 of Dhrystone is the  result  of
+such a re-evaluation, it has been made for two reasons:
+
+o Dhrystone has been published in Ada [1], and Versions in Ada, Pascal  and  C
+  have  been  distributed  by  Reinhold Weicker via floppy disk.  However, the
+  version that was used most often for benchmarking has been the version  made
+  by  Rick  Richardson  by another translation from the Ada version into the C
+  programming language, this has been the version  distributed  via  the  UNIX
+  network Usenet [2].
+
+  There is an obvious need for a common C version of Dhrystone, since C is  at
+  present  the  most  popular  system  programming  language  for the class of
+  systems (microcomputers, minicomputers,  workstations)  where  Dhrystone  is
+  used  most.   There  should  be,  as  far as possible, only one C version of
+  Dhrystone such that results can be compared  without  restrictions.  In  the
+  past,  the  C  versions  distributed by Rick Richardson (Version 1.1) and by
+  Reinhold Weicker had small (though not significant) differences.
+
+  Together with the new C version, the  Ada  and  Pascal  versions  have  been
+  updated as well.
+
+o As far as it is  possible  without  changes  to  the  Dhrystone  statistics,
+  optimizing   compilers   should   be  prevented  from  removing  significant
+  statements.  It has  turned  out  in  the  past  that  optimizing  compilers
+  suppressed  code  generation for too many statements (by "dead code removal"
+  or  "dead  variable  elimination").   This  has  lead  to  the  danger  that
+  benchmarking  results obtained by a naive application of Dhrystone - without
+  inspection of the code that was generated - could become meaningless.
+
+The  overall  policiy  for  version  2  has  been  that  the  distribution  of
+statements,  operand types and operand locality described in [1] should remain
+unchanged as much as possible.  (Very few changes were necessary; their impact
+should be negligible.)  Also, the order of statements should remain unchanged.
+Although I am aware of some critical remarks on the benchmark - I  agree  with
+several  of them - and know some suggestions for improvement, I didn't want to
+change the benchmark into something different from what has  become  known  as
+"Dhrystone"; the confusion generated by such a change would probably outweight
+the benefits. If I were to write a new benchmark program, I wouldn't  give  it
+the  name  "Dhrystone"  since  this  denotes  the  program  published  in [1].
+However, I do recognize  the  need  for  a  larger  number  of  representative
+programs  that can be used as benchmarks; users should always be encouraged to
+use more than just one benchmark.
+
+The new versions (version 2.1 for C, Pascal and Ada) will  be  distributed  as
+widely as possible.  (Version 2.1 differs from version 2.0 distributed via the
+UNIX Network Usenet in  March  1988  only  in  a  few  corrections  for  minor
+deficiencies  found  by  users  of  version 2.0.)  Readers who want to use the
+benchmark for their own measurements can obtain  a  copy  in  machine-readable
+form on floppy disk (MS-DOS or XENIX format) from the author.
+
+
+2.  Overall Characteristics of Version 2
+
+In general, version 2  follows  -  in  the  parts  that  are  significant  for
+performance  measurement,  i.e.   within  the measurement loop - the published
+(Ada) version and the C versions previously distributed.  Where  the  versions
+distributed  by  Rick Richardson [2] and Reinhold Weicker have been different,
+it  follows  the  version  distributed  by  Reinhold  Weicker.  (However,  the
+differences  have  been  so  small  that their impact on execution time in all
+likelihood has been negligible.)  The initialization and UNIX  instrumentation
+part  -  which  had  been  omitted  in  [1] - follows mostly the ideas of Rick
+Richardson [2].  However, any changes in the initialization part  and  in  the
+printing  of  the  result have no impact on performance measurement since they
+are outside the measaurement loop.  As a concession to older compilers,  names
+have been made unique within the first 8 characters for the C version.
+
+The original publication of Dhrystone did not contain any statements for  time
+measurement  since  they  are necessarily system-dependent. However, it turned
+out that it is not enough just to inclose the main procedure of Dhrystone in a
+loop  and  to  measure the execution time.  If the variables that are computed
+are not used somehow, there is the danger that the compiler considers them  as
+"dead  variables" and suppresses code generation for a part of the statements.
+Therefore in version 2 all variables of "main" are printed at the end  of  the
+program.  This also permits some plausibility control for correct execution of
+the benchmark.
+
+At several places in the benchmark, code has been added, but only in  branches
+that  are  not  executed. The intention is that optimizing compilers should be
+prevented from moving code out of the measurement loop, or from removing  code
+altogether.  Statements that are executed have been changed in very few places
+only.  In these cases, only the role of some operands has been changed, and it
+was   made  sure  that  the  numbers  defining  the  "Dhrystone  distribution"
+(distribution of statements, operand types and locality) still hold as much as
+possible.   Except for sophisticated optimizing compilers, execution times for
+version 2.1 should be the same as for previous versions.
+
+Because of the self-imposed limitation that the order and distribution of  the
+executed  statements  should  not  be  changed,  there  are  still cases where
+optimizing compilers may not generate code for some statements. To  a  certain
+degree,  this  is  unavoidable  for  small synthetic benchmarks.  Users of the
+benchmark are advised to check code listings whether code is generated for all
+statements of Dhrystone.
+
+Contrary to the suggestion in the published paper and its realization  in  the
+versions previously distributed, no attempt has been made to subtract the time
+for the measurement loop overhead. (This calculation has proven  difficult  to
+implement  in  a  correct  way,  and  its omission makes the program simpler.)
+However, since the loop check is now part of the benchmark, this does have  an
+impact  -  though a very minor one - on the distribution statistics which have
+been updated for this version.
+
+
+3.  Discussion of Individual Changes
+
+In this section, all changes are described that affect  the  measurement  loop
+and  that  are  not  just  renamings  of variables. All remarks refer to the C
+version; the other language versions have been updated similarly.
+
+In addition to adding  the  measurement  loop  and  the  printout  statements,
+changes have been made at the following places:
+
+o In procedure "main", three statements have been added  in  the  non-executed
+  "then" part of the statement
+
+        if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+
+  they are
+
+        strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+        Int_2_Loc = Run_Index;
+        Int_Glob = Run_Index;
+
+  The string assignment prevents  movement  of  the  preceding  assignment  to
+  Str_2_Loc  (5'th  statement  of  "main")  out  of the measurement loop (This
+  probably will not happen for the C version, but it did happen  with  another
+  language   and  compiler.)   The  assignment  to  Int_2_Loc  prevents  value
+  propagation for Int_2_Loc, and the assignment to Int_Glob makes the value of
+  Int_Glob possibly dependent from the value of Run_Index.
+
+o In the three arithmetic computations at the end of the measurement  loop  in
+  "main  ",  the  role  of  some  variables has been exchanged, to prevent the
+  division from just cancelling out the multiplication as it was  in  [1].   A
+  very   smart  compiler  might  have  recognized  this  and  suppressed  code
+  generation for the division.
+
+o For Proc_2, no code has been changed, but the values of the actual parameter
+  have changed due to changes in "main".
+
+o In Proc_4, the second assignment has been changed from
+
+        Bool_Loc = Bool_Loc | Bool_Glob;
+
+  to
+
+        Bool_Glob = Bool_Loc | Bool_Glob;
+
+  It now assigns a value to a global variable  instead  of  a  local  variable
+  (Bool_Loc);   Bool_Loc  would  be  a  "dead  variable"  which  is  not  used
+  afterwards.
+
+o In Func_1, the statement
+
+        Ch_1_Glob = Ch_1_Loc;
+
+  was added in the non-executed "else" part of the "if" statement, to  prevent
+  the suppression of code generation for the assignment to Ch_1_Loc.
+
+o In Func_2, the second character comparison statement has been changed to
+
+        if (Ch_Loc == 'R')
+
+  ('R' instead of 'X') because  a  comparison  with  'X'  is  implied  in  the
+  preceding "if" statement.
+
+  Also in Func_2, the statement
+
+        Int_Glob = Int_Loc;
+
+  has been added in the non-executed part of the last "if" statement, in order
+  to prevent Int_Loc from becoming a dead variable.
+
+o In Func_3, a non-executed "else" part has been added to the "if"  statement.
+  While  the  program  would  not be incorrect without this "else" part, it is
+  considered bad programming practice if a function  can  be  left  without  a
+  return value.
+
+  To compensate for this change, the (non-executed) "else" part  in  the  "if"
+  statement of Proc_3 was removed.
+
+The distribution statistics have been changed only  by  the  addition  of  the
+measurement loop iteration (1 additional statement, 4 additional local integer
+operands) and by the change in Proc_4  (one  operand  changed  from  local  to
+global).  The distribution statistics in the comment headers have been updated
+accordingly.
+
+
+4.  String Operations
+
+The string operations (string assignment and string comparison) have not  been
+changed, to keep the program consistent with the original version.
+
+There has been some concern that the string operations are over-represented in
+the  program,  and that execution time is dominated by these operations.  This
+was true in particular when optimizing compilers removed too much code in  the
+main part of the program, this should have been mitigated in version 2.
+
+It should be noted that this is a  language-dependent  issue:   Dhrystone  was
+first  published  in  Ada, and with Ada or Pascal semantics, the time spent in
+the string operations is,  at  least  in  all  implementations  known  to  me,
+considerably smaller.  In Ada and Pascal, assignment and comparison of strings
+are operators defined in the language, and the upper  bounds  of  the  strings
+occuring  in  Dhrystone  are part of the type information known at compilation
+time.  The compilers can therefore generate  efficient  inline  code.   In  C,
+string  assignemt  and comparisons are not part of the language, so the string
+operations must be expressed in terms of the C library functions "strcpy"  and
+"strcmp".   (ANSI  C  allows  an  implementation  to use inline code for these
+functions.)  In addition to the overhead caused by additional function  calls,
+these  functions  are  defined for null-terminated strings where the length of
+the strings is not known at compilation time; the function has to check  every
+byte for the termination condition (the null byte).
+
+Obviously, a C library which includes efficiently coded "strcpy" and  "strcmp"
+functions  helps to obtain good Dhrystone results. However, I don't think that
+this is unfair since string  functions  do  occur  quite  frequently  in  real
+programs  (editors, command interpreters, etc.).  If the strings functions are
+implemented efficiently,  this  helps  real  programs  as  well  as  benchmark
+programs.
+
+I admit that the  string  comparison  in  Dhrystone  terminates  later  (after
+scanning  20  characters)  than most string comparisons in real programs.  For
+consistency with the original benchmark, I didn't change the  program  despite
+this weakness.
+
+
+5.  Intended Use of Dhrystone
+
+When Dhrystone is used, the following "ground rules" apply:
+
+o Separate compilation (Ada and C versions)
+
+  As mentioned in [1], Dhrystone was written  to  reflect  actual  programming
+  practice  in  systems  programming.   The  division into several compilation
+  units (5 in the Ada version, 2 in the C version)  is  intended,  as  is  the
+  distribution of inter-module and intra-module subprogram calls.  Although on
+  many systems there will be no difference in execution time  to  a  Dhrystone
+  version  where  all  compilation units are merged into one file, the rule is
+  that separate compilation should  be  used.   The  intention  is  that  real
+  programming  practice,  where  programs  consist  of  several  independently
+  compiled units, should  be  reflected.   This  also  has  implies  that  the
+  compiler,  while  compiling  one  unit,  has no information about the use of
+  variables, register allocation etc.  occuring in  other  compilation  units.
+  Although  in  real  life  compilation  units  will  probably  be larger, the
+  intention is that these effects  of  separate  compilation  are  modeled  in
+  Dhrystone.
+
+  A few language systems have post-linkage optimization available (e.g., final
+  register allocation is performed after linkage).  This is a borderline case:
+  Post-linkage  optimization  involves  additional  program  preparation  time
+  (although  not  as  much  as  compilation in one unit) which may prevent its
+  general use in practical programming.  I think that  since  it  defeats  the
+  intentions given above, it should not be used for Dhrystone.
+
+  Unfortunately, ISO/ANSI  Pascal  does  not  contain  language  features  for
+  separate  compilation.   Although  most  commercial Pascal compilers provide
+  separate compilation in some way, we cannot use it for Dhrystone since  such
+  a  version  would  not  be portable.  Therefore, no attempt has been made to
+  provide a Pascal version with several compilation units.
+
+o No procedure merging
+
+  Although Dhrystone contains some very short procedures where execution would
+  benefit  from  procedure  merging (inlining, macro expansion of procedures),
+  procedure merging is not to be used.  The reason is that the  percentage  of
+  procedure  and  function  calls  is  part of the "Dhrystone distribution" of
+  statements contained in [1].  This restriction does not hold for the  string
+  functions  of  the  C  version  since ANSI C allows an implementation to use
+  inline code for these functions.
+
+o Other optimizations are allowed, but they should be indicated
+
+  It is often hard to draw an exact line between "normal code generation"  and
+  "optimization"  in  compilers:  Some compilers perform operations by default
+  that are invoked in other compilers only  when  optimization  is  explicitly
+  requested.  Also, we cannot avoid that in benchmarking people try to achieve
+  results that look as good as possible.  Therefore,  optimizations  performed
+  by  compilers  -  other  than  those  listed  above - are not forbidden when
+  Dhrystone execution times are measured.  Dhrystone is  not  intended  to  be
+  non-optimizable  but  is  intended  to  be  similarly  optimizable as normal
+  programs.   For  example,  there  are  several  places  in  Dhrystone  where
+  performance   benefits   from   optimizations   like   common  subexpression
+  elimination, value  propagation  etc.,  but  normal  programs  usually  also
+  benefit  from  these  optimizations.   Therefore,  no  effort  was  made  to
+  artificially  prevent  such  optimizations.   However,  measurement  reports
+  should  indicate  which  compiler  optimization  levels  have been used, and
+  reporting results with different levels of  compiler  optimization  for  the
+  same hardware is encouraged.
+
+o Default results are those without "register" declarations (C version)
+
+  When Dhrystone results are quoted  without  additional  qualification,  they
+  should  be  understood  as  results  obtained  without use of the "register"
+  attribute. Good compilers should be able to make good use of registers  even
+  without explicit register declarations ([3], p. 193).
+
+Of course, for experimental  purposes,  post-linkage  optimization,  procedure
+merging and/or compilation in one unit can be done to determine their effects.
+However,  Dhrystone  numbers  obtained  under  these  conditions   should   be
+explicitly  marked as such; "normal" Dhrystone results should be understood as
+results obtained following the ground rules listed above.
+
+In any case, for serious performance evaluation, users are advised to ask  for
+code  listings  and  to  check  them carefully.  In this way, when results for
+different systems are  compared,  the  reader  can  get  a  feeling  how  much
+performance  difference is due to compiler optimization and how much is due to
+hardware speed.
+
+
+6.  Acknowledgements
+
+The C version 2.1 of Dhrystone has been developed  in  cooperation  with  Rick
+Richardson  (Tinton  Falls,  NJ), it incorporates many ideas from the "Version
+1.1" distributed previously by him over the UNIX network Usenet.  Through  his
+activity with Usenet, Rick Richardson has made a very valuable contribution to
+the dissemination of the benchmark.  I also thank  Chaim  Benedelac  (National
+Semiconductor),  David Ditzel (SUN), Earl Killian and John Mashey (MIPS), Alan
+Smith and Rafael  Saavedra-Barrera  (UC  at  Berkeley)  for  their  help  with
+comments on earlier versions of the benchmark.
+
+
+7.  Bibliography
+
+[1]
+   Reinhold P. Weicker: Dhrystone: A Synthetic Systems Programming Benchmark.
+   Communications of the ACM 27, 10 (Oct. 1984), 1013-1030
+
+[2]
+   Rick Richardson: Dhrystone 1.1 Benchmark Summary (and Program Text)
+   Informal Distribution via "Usenet", Last Version Known  to  me:  Sept.  21,
+   1987
+
+[3]
+   Brian W. Kernighan and Dennis M. Ritchie:  The C Programming Language.
+   Prentice-Hall, Englewood Cliffs (NJ) 1978
+
diff --git a/zpu/roadshow/roadshow/dhrystone/README_C b/zpu/roadshow/roadshow/dhrystone/README_C
new file mode 100644
index 0000000..a27a192
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/README_C
@@ -0,0 +1,78 @@
+This "shar" file contains the documentation for the
+electronic mail distribution of the Dhrystone benchmark (C version 2.1);
+a companion "shar" file contains the source code.
+(Because of mail length restrictions for some mailers, I have
+split the distribution in two parts.)
+
+For versions in other languages, see the other "shar" files.
+
+Files containing the C version (*.h: Header File, *.c: C Modules)
+
+  dhry.h
+  dhry_1.c
+  dhry_2.c
+  
+The file RATIONALE contains the article 
+
+  "Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules"
+
+which has been published, together with the C source code (Version 2.0),
+in SIGPLAN Notices vol. 23, no. 8 (Aug. 1988), pp. 49-62.
+This article explains all changes that have been made for Version 2,
+compared with the version of the original publication
+in Communications of the ACM vol. 27, no. 10 (Oct. 1984), pp. 1013-1030.
+It also contains "ground rules" for benchmarking with Dhrystone
+which should be followed by everyone who uses the program and publishes
+Dhrystone results.
+
+Compared with the Version 2.0 published in SIGPLAN Notices, Version 2.1
+contains a few corrections that have been made after Version 2.0 was
+distriobuted over the UNIX network Usenet. These small differences between
+Version 2.0 and 2.1 should not affect execution time measurements.
+For those who want to compare the exact contents of both versions,
+the file "dhry_c.dif" contains the differences between the two versions,
+as generated by a file comparison of the corresponding files with the
+UNIX utility "diff".
+
+The file VARIATIONS contains the article
+
+  "Understanding Variations in Dhrystone Performance"
+
+which has been published in Microprocessor Report, May 1989
+(Editor: M. Slater), pp. 16-17. It describes the points that users
+should know if C Dhrystone results are compared.
+
+Recipients of this shar file who perform measurements are asked
+to send measurement results to the author and/or to Rick Richardson.
+Rick Richardson publishes regularly Dhrystone results on the UNIX network
+Usenet. For submissions of results to him (preferably by electronic mail,
+see address in the program header), he has provided a form which is contained
+in the file "submit.frm".
+
+
+The following files are contained in other "shar" files:
+
+Files containing the Ada version (*.s: Specifications, *.b: Bodies):
+
+  d_global.s
+  d_main.b
+  d_pack_1.b
+  d_pack_1.s
+  d_pack_2.b
+  d_pack_2.s
+
+File containing the Pascal version:
+
+  dhry.p
+
+
+February 22, 1990
+
+                 Reinhold P. Weicker
+                 Siemens AG, AUT E 51
+                 Postfach 3220
+                 D-8520 Erlangen
+                 Germany (West)
+
+                 Phone:  [xxx-49]-9131-7-20330  (8-17 Central European Time)
+                 UUCP:   ..!mcsun!unido!estevax!weicker
diff --git a/zpu/roadshow/roadshow/dhrystone/VARIATIONS b/zpu/roadshow/roadshow/dhrystone/VARIATIONS
new file mode 100644
index 0000000..3046cbd
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/VARIATIONS
@@ -0,0 +1,157 @@
+
+            Understanding Variations in Dhrystone Performance
+
+
+
+          By Reinhold P. Weicker, Siemens AG, AUT E 51, Erlangen
+
+
+
+                                April 1989
+
+
+                      This article has appeared in:
+
+
+        Microprocessor Report, May 1989 (Editor: M. Slater), pp. 16-17
+
+
+
+
+Microprocessor manufacturers tend to credit all the  performance  measured  by
+benchmarks to the speed of their processors, they often don't even mention the
+programming language and compiler used. In their detailed  documents,  usually
+called  "performance brief" or "performance report," they usually do give more
+details. However, these details are often lost in the press releases and other
+marketing  statements.  For serious performance evaluation, it is necessary to
+study the code generated by the various compilers.
+
+Dhrystone was originally published in Ada (Communications  of  the  ACM,  Oct.
+1984).  However, since good Ada compilers were rare at this time and, together
+with UNIX, C became more and more popular, the C version of Dhrystone  is  the
+one  now  mainly  used in industry. There are "official" versions 2.1 for Ada,
+Pascal, and C,  which  are  as  close  together  as  the  languages'  semantic
+differences permit.
+
+Dhrystone contains two statements  where  the  programming  language  and  its
+translation play a major part in the execution time measured by the benchmark:
+
+  o   String assignment (in procedure Proc_0 / main)
+  o   String comparison (in function Func_2)
+
+In Ada and Pascal, strings are arrays of characters where the  length  of  the
+string  is  part  of the type information known at compile time. In C, strings
+are also arrays of characters, but there  are  no  operators  defined  in  the
+language  for  assignment  and  comparison  of  strings.   Instead,  functions
+"strcpy" and "strcmp" are used. These functions are  defined  for  strings  of
+arbitrary  length, and make use of the fact that strings in C have to end with
+a terminating null byte. For general-purpose calls  to  these  functions,  the
+implementor  can  assume  nothing  about  the  length and the alignment of the
+strings involved.
+
+The C version of Dhrystone spends a relatively large amount of time  in  these
+two  functions.  Some  time  ago, I made measurements on a VAX 11/785 with the
+Berkeley UNIX (4.2) compilers (often-used compilers,  but  certainly  not  the
+most  advanced).  In  the  C  version, 23% of the time was spent in the string
+functions; in the Pascal version, only 10%. On good RISC machines (where  less
+time is spent in the procedure calling sequence than on a VAX) and with better
+optimizing compilers, the percentage is higher; MIPS has reported 34%  for  an
+R3000.   Because  of this effect, Pascal and Ada Dhrystone results are usually
+better than C results (except when the optimization quality of the C  compiler
+is considerably better than that of the other compilers).
+
+Several people have noted that the string operations are  over-represented  in
+Dhrystone,  mainly  because the strings occurring in Dhrystone are longer than
+average strings. I admit that this is true, and have said  so  in  my  SIGPLAN
+Notices  paper  (Aug.  1988);  however, I didn't want to generate confusion by
+changing the string lengths from version 1 to version 2.
+
+Even if they are somewhat over-represented in Dhrystone, string operations are
+frequent  enough  that  it makes sense to implement them in the most efficient
+way possible, not only for benchmarking purposes.  This means  that  they  can
+and should be written in assembly language code. ANSI C also explicitly allows
+the strings functions to be implemented as macros, i.e. by inline code.
+
+There is also a third way to speed up the "strcpy" statement in Dhrystone: For
+this  particular  "strcpy" statement, the source of the assignment is a string
+constant. Therefore, in contrast to calls to "strcpy" in the general case, the
+compiler  knows  the  length  and alignment of the strings involved at compile
+time and can generate code in the same efficient  way  as  a  Pascal  compiler
+(word instructions instead of byte instructions).
+
+This is not allowed in the case of the "strcmp" call: Here, the addresses  are
+formal  procedure  parameters, and no assumptions can be made about the length
+or alignment of the strings.  Any such assumptions would indicate an incorrect
+implementation.  They  might work for Dhrystone, where the strings are in fact
+word-aligned  with  typical  compilers,  but  other  programs  would   deliver
+incorrect results.
+
+So, for an apple-to-apple  comparison  between  processors,  and  not  between
+several  possible  (legal  or  illegal)  degrees of compiler optimization, one
+should check that the systems are comparable with  respect  to  the  following
+three points:
+
+  (1) String functions in assembly language vs. in C
+
+      Frequently used functions such as the string functions can and should be
+      written  in  assembly language, and all serious C language systems known
+      to me do this. (I list this point  for  completeness  only.)  Note  that
+      processors  with an instruction that checks a word for a null byte (such
+      as AMD's  29000  and  Intel's  80960)  have  an  advantage  here.  (This
+      advantage  decreases  relatively if optimization (3) is applied.) Due to
+      the length of the strings involved in Dhrystone, this advantage  may  be
+      considered  too  high  in  perspective, but it is certainly legal to use
+      such instructions - after all,  these  situations  are  what  they  were
+      invented for.
+
+  (2) String function code inline vs. as library functions.
+
+      ANSI  C  has  created  a  new  situation,  compared   with   the   older
+      Kernighan/Ritchie  C.  In  the  original C, the definition of the string
+      function was not part of the  language.  Now  it  is,  and  inlining  is
+      explicitly  allowed.  I  probably  should have stated more clearly in my
+      SIGPLAN  Notices  paper  that  the  rule  "No  procedure  inlining   for
+      Dhrystone"  referred  to  the  user level procedures only and not to the
+      library routines.
+
+  (3) Fixed-length and alignment assumptions for the strings
+
+      Compilers should be allowed to optimize in these cases if (and only  if)
+      it  is safe to do so. For Dhrystone, this is the "strcpy" statement, but
+      not the  "strcmp"  statement  (unless,  of  course,  the  "strcmp"  code
+      explicitly   checks   the  alignment  at  execution  time  and  branches
+      accordingly).  A "Dhrystone switch" for the  compiler  that  causes  the
+      generation  of  code  that  may  not work under certain circumstances is
+      certainly inappropriate for comparisons. It has been reported in  Usenet
+      that some C compilers provide such a compiler option; since I don't have
+      access to all C compilers involved, I cannot verify this.
+
+      If the fixed-length and word-alignment assumption can be  used,  a  wide
+      bus  that permits fast multi-word load instructions certainly does help;
+      however, this fact by itself should not make a really big difference.
+
+A check of  these  points  -  something  that  is  necessary  for  a  thorough
+evaluation  and  comparison  of  the  Dhrystone  performance claims - requires
+object code listings as well as listings for  the  string  functions  (strcpy,
+strcmp) that are possibly called by the program.
+
+I don't pretend that Dhrystone is  a  perfect  tool  to  measure  the  integer
+performance  of microprocessors. The more it is used and discussed, the more I
+myself learn about aspects that I hadn't noticed yet when I wrote the program.
+And  of  course,  the  very success of a benchmark program is a danger in that
+people may tune their compilers and/or hardware to it, and  with  this  action
+make it less useful.
+
+Whetstone and Linpack have their critical points also:  The  Whetstone  rating
+depends  heavily on the speed of the mathematical functions (sine, sqrt, ...),
+and Linpack is sensitive to data alignment for some cache configurations.
+
+Introduction of a standard set of public domain benchmark software  (something
+the  SPEC  effort attempts) is certainly a worthwhile thing.  In the meantime,
+people will continue to use whatever is available and widely distributed,  and
+Dhrystone  ratings  are probably still better than MIPS ratings if these are -
+as often in industry - based on  no  reproducible  derivation.   However,  any
+serious  performance  evaluation  requires  more than just a comparison of raw
+numbers; one has to make sure  that  the  numbers  have  been  obtained  in  a
+comparable way.
+
diff --git a/zpu/roadshow/roadshow/dhrystone/build.sh b/zpu/roadshow/roadshow/dhrystone/build.sh
new file mode 100644
index 0000000..5bba707
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/build.sh
@@ -0,0 +1,7 @@
+zpu-elf-gcc -phi -DTIME dhry_1.c dhry_2.c -O3 -Wl,--relax -Wl,--gc-sections -o dhrystone.elf 
+zpu-elf-size *.elf
+zpu-elf-objcopy -O binary dhrystone.elf dhrystone.bin
+sh ../build/makefirmware.sh dhrystone.bin dhrystone.zpu
+
+
+
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry-c b/zpu/roadshow/roadshow/dhrystone/dhry-c
new file mode 100644
index 0000000..4cec46c
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry-c
@@ -0,0 +1,1779 @@
+# to unbundle, sh this file (in an empty directory)
+echo RATIONALE 1>&2
+sed >RATIONALE <<'//GO.SYSIN DD RATIONALE' 's/^-//'
+-
+-
+-    Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules
+-
+-        [published in SIGPLAN Notices 23,8 (Aug. 1988), 49-62]
+-
+-
+-                 Reinhold P. Weicker
+-                 Siemens AG, E STE 35
+-                 [now: Siemens AG, AUT E 51]
+-                 Postfach 3220
+-                 D-8520 Erlangen
+-                 Germany (West)
+-
+-
+-
+-
+-1.  Why a Version 2 of Dhrystone?
+-
+-The Dhrystone benchmark  program  [1]  has  become  a  popular  benchmark  for
+-CPU/compiler   performance   measurement,   in   particular  in  the  area  of
+-minicomputers, workstations, PC's and microprocesors.  It apparently satisfies
+-a  need  for  an  easy-to-use  integer benchmark; it gives a first performance
+-indication which is more meaningful than MIPS numbers which, in their  literal
+-meaning  (million  instructions  per  second), cannot be used across different
+-instruction sets (e.g. RISC  vs.  CISC).   With  the  increasing  use  of  the
+-benchmark, it seems necessary to reconsider the benchmark and to check whether
+-it can still fulfill this function.  Version 2 of Dhrystone is the  result  of
+-such a re-evaluation, it has been made for two reasons:
+-
+-o Dhrystone has been published in Ada [1], and Versions in Ada, Pascal  and  C
+-  have  been  distributed  by  Reinhold Weicker via floppy disk.  However, the
+-  version that was used most often for benchmarking has been the version  made
+-  by  Rick  Richardson  by another translation from the Ada version into the C
+-  programming language, this has been the version  distributed  via  the  UNIX
+-  network Usenet [2].
+-
+-  There is an obvious need for a common C version of Dhrystone, since C is  at
+-  present  the  most  popular  system  programming  language  for the class of
+-  systems (microcomputers, minicomputers,  workstations)  where  Dhrystone  is
+-  used  most.   There  should  be,  as  far as possible, only one C version of
+-  Dhrystone such that results can be compared  without  restrictions.  In  the
+-  past,  the  C  versions  distributed by Rick Richardson (Version 1.1) and by
+-  Reinhold Weicker had small (though not significant) differences.
+-
+-  Together with the new C version, the  Ada  and  Pascal  versions  have  been
+-  updated as well.
+-
+-o As far as it is  possible  without  changes  to  the  Dhrystone  statistics,
+-  optimizing   compilers   should   be  prevented  from  removing  significant
+-  statements.  It has  turned  out  in  the  past  that  optimizing  compilers
+-  suppressed  code  generation for too many statements (by "dead code removal"
+-  or  "dead  variable  elimination").   This  has  lead  to  the  danger  that
+-  benchmarking  results obtained by a naive application of Dhrystone - without
+-  inspection of the code that was generated - could become meaningless.
+-
+-The  overall  policiy  for  version  2  has  been  that  the  distribution  of
+-statements,  operand types and operand locality described in [1] should remain
+-unchanged as much as possible.  (Very few changes were necessary; their impact
+-should be negligible.)  Also, the order of statements should remain unchanged.
+-Although I am aware of some critical remarks on the benchmark - I  agree  with
+-several  of them - and know some suggestions for improvement, I didn't want to
+-change the benchmark into something different from what has  become  known  as
+-"Dhrystone"; the confusion generated by such a change would probably outweight
+-the benefits. If I were to write a new benchmark program, I wouldn't  give  it
+-the  name  "Dhrystone"  since  this  denotes  the  program  published  in [1].
+-However, I do recognize  the  need  for  a  larger  number  of  representative
+-programs  that can be used as benchmarks; users should always be encouraged to
+-use more than just one benchmark.
+-
+-The new versions (version 2.1 for C, Pascal and Ada) will  be  distributed  as
+-widely as possible.  (Version 2.1 differs from version 2.0 distributed via the
+-UNIX Network Usenet in  March  1988  only  in  a  few  corrections  for  minor
+-deficiencies  found  by  users  of  version 2.0.)  Readers who want to use the
+-benchmark for their own measurements can obtain  a  copy  in  machine-readable
+-form on floppy disk (MS-DOS or XENIX format) from the author.
+-
+-
+-2.  Overall Characteristics of Version 2
+-
+-In general, version 2  follows  -  in  the  parts  that  are  significant  for
+-performance  measurement,  i.e.   within  the measurement loop - the published
+-(Ada) version and the C versions previously distributed.  Where  the  versions
+-distributed  by  Rick Richardson [2] and Reinhold Weicker have been different,
+-it  follows  the  version  distributed  by  Reinhold  Weicker.  (However,  the
+-differences  have  been  so  small  that their impact on execution time in all
+-likelihood has been negligible.)  The initialization and UNIX  instrumentation
+-part  -  which  had  been  omitted  in  [1] - follows mostly the ideas of Rick
+-Richardson [2].  However, any changes in the initialization part  and  in  the
+-printing  of  the  result have no impact on performance measurement since they
+-are outside the measaurement loop.  As a concession to older compilers,  names
+-have been made unique within the first 8 characters for the C version.
+-
+-The original publication of Dhrystone did not contain any statements for  time
+-measurement  since  they  are necessarily system-dependent. However, it turned
+-out that it is not enough just to inclose the main procedure of Dhrystone in a
+-loop  and  to  measure the execution time.  If the variables that are computed
+-are not used somehow, there is the danger that the compiler considers them  as
+-"dead  variables" and suppresses code generation for a part of the statements.
+-Therefore in version 2 all variables of "main" are printed at the end  of  the
+-program.  This also permits some plausibility control for correct execution of
+-the benchmark.
+-
+-At several places in the benchmark, code has been added, but only in  branches
+-that  are  not  executed. The intention is that optimizing compilers should be
+-prevented from moving code out of the measurement loop, or from removing  code
+-altogether.  Statements that are executed have been changed in very few places
+-only.  In these cases, only the role of some operands has been changed, and it
+-was   made  sure  that  the  numbers  defining  the  "Dhrystone  distribution"
+-(distribution of statements, operand types and locality) still hold as much as
+-possible.   Except for sophisticated optimizing compilers, execution times for
+-version 2.1 should be the same as for previous versions.
+-
+-Because of the self-imposed limitation that the order and distribution of  the
+-executed  statements  should  not  be  changed,  there  are  still cases where
+-optimizing compilers may not generate code for some statements. To  a  certain
+-degree,  this  is  unavoidable  for  small synthetic benchmarks.  Users of the
+-benchmark are advised to check code listings whether code is generated for all
+-statements of Dhrystone.
+-
+-Contrary to the suggestion in the published paper and its realization  in  the
+-versions previously distributed, no attempt has been made to subtract the time
+-for the measurement loop overhead. (This calculation has proven  difficult  to
+-implement  in  a  correct  way,  and  its omission makes the program simpler.)
+-However, since the loop check is now part of the benchmark, this does have  an
+-impact  -  though a very minor one - on the distribution statistics which have
+-been updated for this version.
+-
+-
+-3.  Discussion of Individual Changes
+-
+-In this section, all changes are described that affect  the  measurement  loop
+-and  that  are  not  just  renamings  of variables. All remarks refer to the C
+-version; the other language versions have been updated similarly.
+-
+-In addition to adding  the  measurement  loop  and  the  printout  statements,
+-changes have been made at the following places:
+-
+-o In procedure "main", three statements have been added  in  the  non-executed
+-  "then" part of the statement
+-
+-        if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+-
+-  they are
+-
+-        strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+-        Int_2_Loc = Run_Index;
+-        Int_Glob = Run_Index;
+-
+-  The string assignment prevents  movement  of  the  preceding  assignment  to
+-  Str_2_Loc  (5'th  statement  of  "main")  out  of the measurement loop (This
+-  probably will not happen for the C version, but it did happen  with  another
+-  language   and  compiler.)   The  assignment  to  Int_2_Loc  prevents  value
+-  propagation for Int_2_Loc, and the assignment to Int_Glob makes the value of
+-  Int_Glob possibly dependent from the value of Run_Index.
+-
+-o In the three arithmetic computations at the end of the measurement  loop  in
+-  "main  ",  the  role  of  some  variables has been exchanged, to prevent the
+-  division from just cancelling out the multiplication as it was  in  [1].   A
+-  very   smart  compiler  might  have  recognized  this  and  suppressed  code
+-  generation for the division.
+-
+-o For Proc_2, no code has been changed, but the values of the actual parameter
+-  have changed due to changes in "main".
+-
+-o In Proc_4, the second assignment has been changed from
+-
+-        Bool_Loc = Bool_Loc | Bool_Glob;
+-
+-  to
+-
+-        Bool_Glob = Bool_Loc | Bool_Glob;
+-
+-  It now assigns a value to a global variable  instead  of  a  local  variable
+-  (Bool_Loc);   Bool_Loc  would  be  a  "dead  variable"  which  is  not  used
+-  afterwards.
+-
+-o In Func_1, the statement
+-
+-        Ch_1_Glob = Ch_1_Loc;
+-
+-  was added in the non-executed "else" part of the "if" statement, to  prevent
+-  the suppression of code generation for the assignment to Ch_1_Loc.
+-
+-o In Func_2, the second character comparison statement has been changed to
+-
+-        if (Ch_Loc == 'R')
+-
+-  ('R' instead of 'X') because  a  comparison  with  'X'  is  implied  in  the
+-  preceding "if" statement.
+-
+-  Also in Func_2, the statement
+-
+-        Int_Glob = Int_Loc;
+-
+-  has been added in the non-executed part of the last "if" statement, in order
+-  to prevent Int_Loc from becoming a dead variable.
+-
+-o In Func_3, a non-executed "else" part has been added to the "if"  statement.
+-  While  the  program  would  not be incorrect without this "else" part, it is
+-  considered bad programming practice if a function  can  be  left  without  a
+-  return value.
+-
+-  To compensate for this change, the (non-executed) "else" part  in  the  "if"
+-  statement of Proc_3 was removed.
+-
+-The distribution statistics have been changed only  by  the  addition  of  the
+-measurement loop iteration (1 additional statement, 4 additional local integer
+-operands) and by the change in Proc_4  (one  operand  changed  from  local  to
+-global).  The distribution statistics in the comment headers have been updated
+-accordingly.
+-
+-
+-4.  String Operations
+-
+-The string operations (string assignment and string comparison) have not  been
+-changed, to keep the program consistent with the original version.
+-
+-There has been some concern that the string operations are over-represented in
+-the  program,  and that execution time is dominated by these operations.  This
+-was true in particular when optimizing compilers removed too much code in  the
+-main part of the program, this should have been mitigated in version 2.
+-
+-It should be noted that this is a  language-dependent  issue:   Dhrystone  was
+-first  published  in  Ada, and with Ada or Pascal semantics, the time spent in
+-the string operations is,  at  least  in  all  implementations  known  to  me,
+-considerably smaller.  In Ada and Pascal, assignment and comparison of strings
+-are operators defined in the language, and the upper  bounds  of  the  strings
+-occuring  in  Dhrystone  are part of the type information known at compilation
+-time.  The compilers can therefore generate  efficient  inline  code.   In  C,
+-string  assignemt  and comparisons are not part of the language, so the string
+-operations must be expressed in terms of the C library functions "strcpy"  and
+-"strcmp".   (ANSI  C  allows  an  implementation  to use inline code for these
+-functions.)  In addition to the overhead caused by additional function  calls,
+-these  functions  are  defined for null-terminated strings where the length of
+-the strings is not known at compilation time; the function has to check  every
+-byte for the termination condition (the null byte).
+-
+-Obviously, a C library which includes efficiently coded "strcpy" and  "strcmp"
+-functions  helps to obtain good Dhrystone results. However, I don't think that
+-this is unfair since string  functions  do  occur  quite  frequently  in  real
+-programs  (editors, command interpreters, etc.).  If the strings functions are
+-implemented efficiently,  this  helps  real  programs  as  well  as  benchmark
+-programs.
+-
+-I admit that the  string  comparison  in  Dhrystone  terminates  later  (after
+-scanning  20  characters)  than most string comparisons in real programs.  For
+-consistency with the original benchmark, I didn't change the  program  despite
+-this weakness.
+-
+-
+-5.  Intended Use of Dhrystone
+-
+-When Dhrystone is used, the following "ground rules" apply:
+-
+-o Separate compilation (Ada and C versions)
+-
+-  As mentioned in [1], Dhrystone was written  to  reflect  actual  programming
+-  practice  in  systems  programming.   The  division into several compilation
+-  units (5 in the Ada version, 2 in the C version)  is  intended,  as  is  the
+-  distribution of inter-module and intra-module subprogram calls.  Although on
+-  many systems there will be no difference in execution time  to  a  Dhrystone
+-  version  where  all  compilation units are merged into one file, the rule is
+-  that separate compilation should  be  used.   The  intention  is  that  real
+-  programming  practice,  where  programs  consist  of  several  independently
+-  compiled units, should  be  reflected.   This  also  has  implies  that  the
+-  compiler,  while  compiling  one  unit,  has no information about the use of
+-  variables, register allocation etc.  occuring in  other  compilation  units.
+-  Although  in  real  life  compilation  units  will  probably  be larger, the
+-  intention is that these effects  of  separate  compilation  are  modeled  in
+-  Dhrystone.
+-
+-  A few language systems have post-linkage optimization available (e.g., final
+-  register allocation is performed after linkage).  This is a borderline case:
+-  Post-linkage  optimization  involves  additional  program  preparation  time
+-  (although  not  as  much  as  compilation in one unit) which may prevent its
+-  general use in practical programming.  I think that  since  it  defeats  the
+-  intentions given above, it should not be used for Dhrystone.
+-
+-  Unfortunately, ISO/ANSI  Pascal  does  not  contain  language  features  for
+-  separate  compilation.   Although  most  commercial Pascal compilers provide
+-  separate compilation in some way, we cannot use it for Dhrystone since  such
+-  a  version  would  not  be portable.  Therefore, no attempt has been made to
+-  provide a Pascal version with several compilation units.
+-
+-o No procedure merging
+-
+-  Although Dhrystone contains some very short procedures where execution would
+-  benefit  from  procedure  merging (inlining, macro expansion of procedures),
+-  procedure merging is not to be used.  The reason is that the  percentage  of
+-  procedure  and  function  calls  is  part of the "Dhrystone distribution" of
+-  statements contained in [1].  This restriction does not hold for the  string
+-  functions  of  the  C  version  since ANSI C allows an implementation to use
+-  inline code for these functions.
+-
+-o Other optimizations are allowed, but they should be indicated
+-
+-  It is often hard to draw an exact line between "normal code generation"  and
+-  "optimization"  in  compilers:  Some compilers perform operations by default
+-  that are invoked in other compilers only  when  optimization  is  explicitly
+-  requested.  Also, we cannot avoid that in benchmarking people try to achieve
+-  results that look as good as possible.  Therefore,  optimizations  performed
+-  by  compilers  -  other  than  those  listed  above - are not forbidden when
+-  Dhrystone execution times are measured.  Dhrystone is  not  intended  to  be
+-  non-optimizable  but  is  intended  to  be  similarly  optimizable as normal
+-  programs.   For  example,  there  are  several  places  in  Dhrystone  where
+-  performance   benefits   from   optimizations   like   common  subexpression
+-  elimination, value  propagation  etc.,  but  normal  programs  usually  also
+-  benefit  from  these  optimizations.   Therefore,  no  effort  was  made  to
+-  artificially  prevent  such  optimizations.   However,  measurement  reports
+-  should  indicate  which  compiler  optimization  levels  have been used, and
+-  reporting results with different levels of  compiler  optimization  for  the
+-  same hardware is encouraged.
+-
+-o Default results are those without "register" declarations (C version)
+-
+-  When Dhrystone results are quoted  without  additional  qualification,  they
+-  should  be  understood  as  results  obtained  without use of the "register"
+-  attribute. Good compilers should be able to make good use of registers  even
+-  without explicit register declarations ([3], p. 193).
+-
+-Of course, for experimental  purposes,  post-linkage  optimization,  procedure
+-merging and/or compilation in one unit can be done to determine their effects.
+-However,  Dhrystone  numbers  obtained  under  these  conditions   should   be
+-explicitly  marked as such; "normal" Dhrystone results should be understood as
+-results obtained following the ground rules listed above.
+-
+-In any case, for serious performance evaluation, users are advised to ask  for
+-code  listings  and  to  check  them carefully.  In this way, when results for
+-different systems are  compared,  the  reader  can  get  a  feeling  how  much
+-performance  difference is due to compiler optimization and how much is due to
+-hardware speed.
+-
+-
+-6.  Acknowledgements
+-
+-The C version 2.1 of Dhrystone has been developed  in  cooperation  with  Rick
+-Richardson  (Tinton  Falls,  NJ), it incorporates many ideas from the "Version
+-1.1" distributed previously by him over the UNIX network Usenet.  Through  his
+-activity with Usenet, Rick Richardson has made a very valuable contribution to
+-the dissemination of the benchmark.  I also thank  Chaim  Benedelac  (National
+-Semiconductor),  David Ditzel (SUN), Earl Killian and John Mashey (MIPS), Alan
+-Smith and Rafael  Saavedra-Barrera  (UC  at  Berkeley)  for  their  help  with
+-comments on earlier versions of the benchmark.
+-
+-
+-7.  Bibliography
+-
+-[1]
+-   Reinhold P. Weicker: Dhrystone: A Synthetic Systems Programming Benchmark.
+-   Communications of the ACM 27, 10 (Oct. 1984), 1013-1030
+-
+-[2]
+-   Rick Richardson: Dhrystone 1.1 Benchmark Summary (and Program Text)
+-   Informal Distribution via "Usenet", Last Version Known  to  me:  Sept.  21,
+-   1987
+-
+-[3]
+-   Brian W. Kernighan and Dennis M. Ritchie:  The C Programming Language.
+-   Prentice-Hall, Englewood Cliffs (NJ) 1978
+-
+//GO.SYSIN DD RATIONALE
+echo README_C 1>&2
+sed >README_C <<'//GO.SYSIN DD README_C' 's/^-//'
+-This "shar" file contains the documentation for the
+-electronic mail distribution of the Dhrystone benchmark (C version 2.1);
+-a companion "shar" file contains the source code.
+-(Because of mail length restrictions for some mailers, I have
+-split the distribution in two parts.)
+-
+-For versions in other languages, see the other "shar" files.
+-
+-Files containing the C version (*.h: Header File, *.c: C Modules)
+-
+-  dhry.h
+-  dhry_1.c
+-  dhry_2.c
+-  
+-The file RATIONALE contains the article 
+-
+-  "Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules"
+-
+-which has been published, together with the C source code (Version 2.0),
+-in SIGPLAN Notices vol. 23, no. 8 (Aug. 1988), pp. 49-62.
+-This article explains all changes that have been made for Version 2,
+-compared with the version of the original publication
+-in Communications of the ACM vol. 27, no. 10 (Oct. 1984), pp. 1013-1030.
+-It also contains "ground rules" for benchmarking with Dhrystone
+-which should be followed by everyone who uses the program and publishes
+-Dhrystone results.
+-
+-Compared with the Version 2.0 published in SIGPLAN Notices, Version 2.1
+-contains a few corrections that have been made after Version 2.0 was
+-distriobuted over the UNIX network Usenet. These small differences between
+-Version 2.0 and 2.1 should not affect execution time measurements.
+-For those who want to compare the exact contents of both versions,
+-the file "dhry_c.dif" contains the differences between the two versions,
+-as generated by a file comparison of the corresponding files with the
+-UNIX utility "diff".
+-
+-The file VARIATIONS contains the article
+-
+-  "Understanding Variations in Dhrystone Performance"
+-
+-which has been published in Microprocessor Report, May 1989
+-(Editor: M. Slater), pp. 16-17. It describes the points that users
+-should know if C Dhrystone results are compared.
+-
+-Recipients of this shar file who perform measurements are asked
+-to send measurement results to the author and/or to Rick Richardson.
+-Rick Richardson publishes regularly Dhrystone results on the UNIX network
+-Usenet. For submissions of results to him (preferably by electronic mail,
+-see address in the program header), he has provided a form which is contained
+-in the file "submit.frm".
+-
+-
+-The following files are contained in other "shar" files:
+-
+-Files containing the Ada version (*.s: Specifications, *.b: Bodies):
+-
+-  d_global.s
+-  d_main.b
+-  d_pack_1.b
+-  d_pack_1.s
+-  d_pack_2.b
+-  d_pack_2.s
+-
+-File containing the Pascal version:
+-
+-  dhry.p
+-
+-
+-February 22, 1990
+-
+-                 Reinhold P. Weicker
+-                 Siemens AG, AUT E 51
+-                 Postfach 3220
+-                 D-8520 Erlangen
+-                 Germany (West)
+-
+-                 Phone:  [xxx-49]-9131-7-20330  (8-17 Central European Time)
+-                 UUCP:   ..!mcsun!unido!estevax!weicker
+//GO.SYSIN DD README_C
+echo VARIATIONS 1>&2
+sed >VARIATIONS <<'//GO.SYSIN DD VARIATIONS' 's/^-//'
+-
+-            Understanding Variations in Dhrystone Performance
+-
+-
+-
+-          By Reinhold P. Weicker, Siemens AG, AUT E 51, Erlangen
+-
+-
+-
+-                                April 1989
+-
+-
+-                      This article has appeared in:
+-
+-
+-        Microprocessor Report, May 1989 (Editor: M. Slater), pp. 16-17
+-
+-
+-
+-
+-Microprocessor manufacturers tend to credit all the  performance  measured  by
+-benchmarks to the speed of their processors, they often don't even mention the
+-programming language and compiler used. In their detailed  documents,  usually
+-called  "performance brief" or "performance report," they usually do give more
+-details. However, these details are often lost in the press releases and other
+-marketing  statements.  For serious performance evaluation, it is necessary to
+-study the code generated by the various compilers.
+-
+-Dhrystone was originally published in Ada (Communications  of  the  ACM,  Oct.
+-1984).  However, since good Ada compilers were rare at this time and, together
+-with UNIX, C became more and more popular, the C version of Dhrystone  is  the
+-one  now  mainly  used in industry. There are "official" versions 2.1 for Ada,
+-Pascal, and C,  which  are  as  close  together  as  the  languages'  semantic
+-differences permit.
+-
+-Dhrystone contains two statements  where  the  programming  language  and  its
+-translation play a major part in the execution time measured by the benchmark:
+-
+-  o   String assignment (in procedure Proc_0 / main)
+-  o   String comparison (in function Func_2)
+-
+-In Ada and Pascal, strings are arrays of characters where the  length  of  the
+-string  is  part  of the type information known at compile time. In C, strings
+-are also arrays of characters, but there  are  no  operators  defined  in  the
+-language  for  assignment  and  comparison  of  strings.   Instead,  functions
+-"strcpy" and "strcmp" are used. These functions are  defined  for  strings  of
+-arbitrary  length, and make use of the fact that strings in C have to end with
+-a terminating null byte. For general-purpose calls  to  these  functions,  the
+-implementor  can  assume  nothing  about  the  length and the alignment of the
+-strings involved.
+-
+-The C version of Dhrystone spends a relatively large amount of time  in  these
+-two  functions.  Some  time  ago, I made measurements on a VAX 11/785 with the
+-Berkeley UNIX (4.2) compilers (often-used compilers,  but  certainly  not  the
+-most  advanced).  In  the  C  version, 23% of the time was spent in the string
+-functions; in the Pascal version, only 10%. On good RISC machines (where  less
+-time is spent in the procedure calling sequence than on a VAX) and with better
+-optimizing compilers, the percentage is higher; MIPS has reported 34%  for  an
+-R3000.   Because  of this effect, Pascal and Ada Dhrystone results are usually
+-better than C results (except when the optimization quality of the C  compiler
+-is considerably better than that of the other compilers).
+-
+-Several people have noted that the string operations are  over-represented  in
+-Dhrystone,  mainly  because the strings occurring in Dhrystone are longer than
+-average strings. I admit that this is true, and have said  so  in  my  SIGPLAN
+-Notices  paper  (Aug.  1988);  however, I didn't want to generate confusion by
+-changing the string lengths from version 1 to version 2.
+-
+-Even if they are somewhat over-represented in Dhrystone, string operations are
+-frequent  enough  that  it makes sense to implement them in the most efficient
+-way possible, not only for benchmarking purposes.  This means  that  they  can
+-and should be written in assembly language code. ANSI C also explicitly allows
+-the strings functions to be implemented as macros, i.e. by inline code.
+-
+-There is also a third way to speed up the "strcpy" statement in Dhrystone: For
+-this  particular  "strcpy" statement, the source of the assignment is a string
+-constant. Therefore, in contrast to calls to "strcpy" in the general case, the
+-compiler  knows  the  length  and alignment of the strings involved at compile
+-time and can generate code in the same efficient  way  as  a  Pascal  compiler
+-(word instructions instead of byte instructions).
+-
+-This is not allowed in the case of the "strcmp" call: Here, the addresses  are
+-formal  procedure  parameters, and no assumptions can be made about the length
+-or alignment of the strings.  Any such assumptions would indicate an incorrect
+-implementation.  They  might work for Dhrystone, where the strings are in fact
+-word-aligned  with  typical  compilers,  but  other  programs  would   deliver
+-incorrect results.
+-
+-So, for an apple-to-apple  comparison  between  processors,  and  not  between
+-several  possible  (legal  or  illegal)  degrees of compiler optimization, one
+-should check that the systems are comparable with  respect  to  the  following
+-three points:
+-
+-  (1) String functions in assembly language vs. in C
+-
+-      Frequently used functions such as the string functions can and should be
+-      written  in  assembly language, and all serious C language systems known
+-      to me do this. (I list this point  for  completeness  only.)  Note  that
+-      processors  with an instruction that checks a word for a null byte (such
+-      as AMD's  29000  and  Intel's  80960)  have  an  advantage  here.  (This
+-      advantage  decreases  relatively if optimization (3) is applied.) Due to
+-      the length of the strings involved in Dhrystone, this advantage  may  be
+-      considered  too  high  in  perspective, but it is certainly legal to use
+-      such instructions - after all,  these  situations  are  what  they  were
+-      invented for.
+-
+-  (2) String function code inline vs. as library functions.
+-
+-      ANSI  C  has  created  a  new  situation,  compared   with   the   older
+-      Kernighan/Ritchie  C.  In  the  original C, the definition of the string
+-      function was not part of the  language.  Now  it  is,  and  inlining  is
+-      explicitly  allowed.  I  probably  should have stated more clearly in my
+-      SIGPLAN  Notices  paper  that  the  rule  "No  procedure  inlining   for
+-      Dhrystone"  referred  to  the  user level procedures only and not to the
+-      library routines.
+-
+-  (3) Fixed-length and alignment assumptions for the strings
+-
+-      Compilers should be allowed to optimize in these cases if (and only  if)
+-      it  is safe to do so. For Dhrystone, this is the "strcpy" statement, but
+-      not the  "strcmp"  statement  (unless,  of  course,  the  "strcmp"  code
+-      explicitly   checks   the  alignment  at  execution  time  and  branches
+-      accordingly).  A "Dhrystone switch" for the  compiler  that  causes  the
+-      generation  of  code  that  may  not work under certain circumstances is
+-      certainly inappropriate for comparisons. It has been reported in  Usenet
+-      that some C compilers provide such a compiler option; since I don't have
+-      access to all C compilers involved, I cannot verify this.
+-
+-      If the fixed-length and word-alignment assumption can be  used,  a  wide
+-      bus  that permits fast multi-word load instructions certainly does help;
+-      however, this fact by itself should not make a really big difference.
+-
+-A check of  these  points  -  something  that  is  necessary  for  a  thorough
+-evaluation  and  comparison  of  the  Dhrystone  performance claims - requires
+-object code listings as well as listings for  the  string  functions  (strcpy,
+-strcmp) that are possibly called by the program.
+-
+-I don't pretend that Dhrystone is  a  perfect  tool  to  measure  the  integer
+-performance  of microprocessors. The more it is used and discussed, the more I
+-myself learn about aspects that I hadn't noticed yet when I wrote the program.
+-And  of  course,  the  very success of a benchmark program is a danger in that
+-people may tune their compilers and/or hardware to it, and  with  this  action
+-make it less useful.
+-
+-Whetstone and Linpack have their critical points also:  The  Whetstone  rating
+-depends  heavily on the speed of the mathematical functions (sine, sqrt, ...),
+-and Linpack is sensitive to data alignment for some cache configurations.
+-
+-Introduction of a standard set of public domain benchmark software  (something
+-the  SPEC  effort attempts) is certainly a worthwhile thing.  In the meantime,
+-people will continue to use whatever is available and widely distributed,  and
+-Dhrystone  ratings  are probably still better than MIPS ratings if these are -
+-as often in industry - based on  no  reproducible  derivation.   However,  any
+-serious  performance  evaluation  requires  more than just a comparison of raw
+-numbers; one has to make sure  that  the  numbers  have  been  obtained  in  a
+-comparable way.
+-
+//GO.SYSIN DD VARIATIONS
+echo dhry.h 1>&2
+sed >dhry.h <<'//GO.SYSIN DD dhry.h' 's/^-//'
+-/*
+- ****************************************************************************
+- *
+- *                   "DHRYSTONE" Benchmark Program
+- *                   -----------------------------
+- *                                                                            
+- *  Version:    C, Version 2.1
+- *                                                                            
+- *  File:       dhry.h (part 1 of 3)
+- *
+- *  Date:       May 25, 1988
+- *
+- *  Author:     Reinhold P. Weicker
+- *                      Siemens AG, AUT E 51
+- *                      Postfach 3220
+- *                      8520 Erlangen
+- *                      Germany (West)
+- *                              Phone:  [+49]-9131-7-20330
+- *                                      (8-17 Central European Time)
+- *                              Usenet: ..!mcsun!unido!estevax!weicker
+- *
+- *              Original Version (in Ada) published in
+- *              "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+- *              pp. 1013 - 1030, together with the statistics
+- *              on which the distribution of statements etc. is based.
+- *
+- *              In this C version, the following C library functions are used:
+- *              - strcpy, strcmp (inside the measurement loop)
+- *              - printf, scanf (outside the measurement loop)
+- *              In addition, Berkeley UNIX system calls "times ()" or "time ()"
+- *              are used for execution time measurement. For measurements
+- *              on other systems, these calls have to be changed.
+- *
+- *  Collection of Results:
+- *              Reinhold Weicker (address see above) and
+- *              
+- *              Rick Richardson
+- *              PC Research. Inc.
+- *              94 Apple Orchard Drive
+- *              Tinton Falls, NJ 07724
+- *                      Phone:  (201) 389-8963 (9-17 EST)               
+- *                      Usenet: ...!uunet!pcrat!rick
+- *
+- *      Please send results to Rick Richardson and/or Reinhold Weicker.
+- *      Complete information should be given on hardware and software used.
+- *      Hardware information includes: Machine type, CPU, type and size
+- *      of caches; for microprocessors: clock frequency, memory speed
+- *      (number of wait states).
+- *      Software information includes: Compiler (and runtime library)
+- *      manufacturer and version, compilation switches, OS version.
+- *      The Operating System version may give an indication about the
+- *      compiler; Dhrystone itself performs no OS calls in the measurement loop.
+- *
+- *      The complete output generated by the program should be mailed
+- *      such that at least some checks for correctness can be made.
+- *
+- ***************************************************************************
+- *
+- *  History:    This version C/2.1 has been made for two reasons:
+- *
+- *              1) There is an obvious need for a common C version of
+- *              Dhrystone, since C is at present the most popular system
+- *              programming language for the class of processors
+- *              (microcomputers, minicomputers) where Dhrystone is used most.
+- *              There should be, as far as possible, only one C version of
+- *              Dhrystone such that results can be compared without
+- *              restrictions. In the past, the C versions distributed
+- *              by Rick Richardson (Version 1.1) and by Reinhold Weicker
+- *              had small (though not significant) differences.
+- *
+- *              2) As far as it is possible without changes to the Dhrystone
+- *              statistics, optimizing compilers should be prevented from
+- *              removing significant statements.
+- *
+- *              This C version has been developed in cooperation with
+- *              Rick Richardson (Tinton Falls, NJ), it incorporates many
+- *              ideas from the "Version 1.1" distributed previously by
+- *              him over the UNIX network Usenet.
+- *              I also thank Chaim Benedelac (National Semiconductor),
+- *              David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+- *              Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+- *              for their help with comments on earlier versions of the
+- *              benchmark.
+- *
+- *  Changes:    In the initialization part, this version follows mostly
+- *              Rick Richardson's version distributed via Usenet, not the
+- *              version distributed earlier via floppy disk by Reinhold Weicker.
+- *              As a concession to older compilers, names have been made
+- *              unique within the first 8 characters.
+- *              Inside the measurement loop, this version follows the
+- *              version previously distributed by Reinhold Weicker.
+- *
+- *              At several places in the benchmark, code has been added,
+- *              but within the measurement loop only in branches that 
+- *              are not executed. The intention is that optimizing compilers
+- *              should be prevented from moving code out of the measurement
+- *              loop, or from removing code altogether. Since the statements
+- *              that are executed within the measurement loop have NOT been
+- *              changed, the numbers defining the "Dhrystone distribution"
+- *              (distribution of statements, operand types and locality)
+- *              still hold. Except for sophisticated optimizing compilers,
+- *              execution times for this version should be the same as
+- *              for previous versions.
+- *              
+- *              Since it has proven difficult to subtract the time for the
+- *              measurement loop overhead in a correct way, the loop check
+- *              has been made a part of the benchmark. This does have
+- *              an impact - though a very minor one - on the distribution
+- *              statistics which have been updated for this version.
+- *
+- *              All changes within the measurement loop are described
+- *              and discussed in the companion paper "Rationale for
+- *              Dhrystone version 2".
+- *
+- *              Because of the self-imposed limitation that the order and
+- *              distribution of the executed statements should not be
+- *              changed, there are still cases where optimizing compilers
+- *              may not generate code for some statements. To a certain
+- *              degree, this is unavoidable for small synthetic benchmarks.
+- *              Users of the benchmark are advised to check code listings
+- *              whether code is generated for all statements of Dhrystone.
+- *
+- *              Version 2.1 is identical to version 2.0 distributed via
+- *              the UNIX network Usenet in March 1988 except that it corrects
+- *              some minor deficiencies that were found by users of version 2.0.
+- *              The only change within the measurement loop is that a
+- *              non-executed "else" part was added to the "if" statement in
+- *              Func_3, and a non-executed "else" part removed from Proc_3.
+- *
+- ***************************************************************************
+- *
+- * Defines:     The following "Defines" are possible:
+- *              -DREG=register          (default: Not defined)
+- *                      As an approximation to what an average C programmer
+- *                      might do, the "register" storage class is applied
+- *                      (if enabled by -DREG=register)
+- *                      - for local variables, if they are used (dynamically)
+- *                        five or more times
+- *                      - for parameters if they are used (dynamically)
+- *                        six or more times
+- *                      Note that an optimal "register" strategy is
+- *                      compiler-dependent, and that "register" declarations
+- *                      do not necessarily lead to faster execution.
+- *              -DNOSTRUCTASSIGN        (default: Not defined)
+- *                      Define if the C compiler does not support
+- *                      assignment of structures.
+- *              -DNOENUMS               (default: Not defined)
+- *                      Define if the C compiler does not support
+- *                      enumeration types.
+- *              -DTIMES                 (default)
+- *              -DTIME
+- *                      The "times" function of UNIX (returning process times)
+- *                      or the "time" function (returning wallclock time)
+- *                      is used for measurement. 
+- *                      For single user machines, "time ()" is adequate. For
+- *                      multi-user machines where you cannot get single-user
+- *                      access, use the "times ()" function. If you have
+- *                      neither, use a stopwatch in the dead of night.
+- *                      "printf"s are provided marking the points "Start Timer"
+- *                      and "Stop Timer". DO NOT use the UNIX "time(1)"
+- *                      command, as this will measure the total time to
+- *                      run this program, which will (erroneously) include
+- *                      the time to allocate storage (malloc) and to perform
+- *                      the initialization.
+- *              -DHZ=nnn
+- *                      In Berkeley UNIX, the function "times" returns process
+- *                      time in 1/HZ seconds, with HZ = 60 for most systems.
+- *                      CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+- *                      A VALUE.
+- *
+- ***************************************************************************
+- *
+- *  Compilation model and measurement (IMPORTANT):
+- *
+- *  This C version of Dhrystone consists of three files:
+- *  - dhry.h (this file, containing global definitions and comments)
+- *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+- *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+- *
+- *  The following "ground rules" apply for measurements:
+- *  - Separate compilation
+- *  - No procedure merging
+- *  - Otherwise, compiler optimizations are allowed but should be indicated
+- *  - Default results are those without register declarations
+- *  See the companion paper "Rationale for Dhrystone Version 2" for a more
+- *  detailed discussion of these ground rules.
+- *
+- *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+- *  models ("small", "medium", "large" etc.) should be given if possible,
+- *  together with a definition of these models for the compiler system used.
+- *
+- **************************************************************************
+- *
+- *  Dhrystone (C version) statistics:
+- *
+- *  [Comment from the first distribution, updated for version 2.
+- *   Note that because of language differences, the numbers are slightly
+- *   different from the Ada version.]
+- *
+- *  The following program contains statements of a high level programming
+- *  language (here: C) in a distribution considered representative:           
+- *
+- *    assignments                  52 (51.0 %)
+- *    control statements           33 (32.4 %)
+- *    procedure, function calls    17 (16.7 %)
+- *
+- *  103 statements are dynamically executed. The program is balanced with
+- *  respect to the three aspects:                                             
+- *
+- *    - statement type
+- *    - operand type
+- *    - operand locality
+- *         operand global, local, parameter, or constant.                     
+- *
+- *  The combination of these three aspects is balanced only approximately.    
+- *
+- *  1. Statement Type:                                                        
+- *  -----------------             number
+- *
+- *     V1 = V2                     9
+- *       (incl. V1 = F(..)
+- *     V = Constant               12
+- *     Assignment,                 7
+- *       with array element
+- *     Assignment,                 6
+- *       with record component
+- *                                --
+- *                                34       34
+- *
+- *     X = Y +|-|"&&"|"|" Z        5
+- *     X = Y +|-|"==" Constant     6
+- *     X = X +|- 1                 3
+- *     X = Y *|/ Z                 2
+- *     X = Expression,             1
+- *           two operators
+- *     X = Expression,             1
+- *           three operators
+- *                                --
+- *                                18       18
+- *
+- *     if ....                    14
+- *       with "else"      7
+- *       without "else"   7
+- *           executed        3
+- *           not executed    4
+- *     for ...                     7  |  counted every time
+- *     while ...                   4  |  the loop condition
+- *     do ... while                1  |  is evaluated
+- *     switch ...                  1
+- *     break                       1
+- *     declaration with            1
+- *       initialization
+- *                                --
+- *                                34       34
+- *
+- *     P (...)  procedure call    11
+- *       user procedure      10
+- *       library procedure    1
+- *     X = F (...)
+- *             function  call      6
+- *       user function        5                                         
+- *       library function     1                                               
+- *                                --                                          
+- *                                17       17
+- *                                        ---
+- *                                        103
+- *
+- *    The average number of parameters in procedure or function calls
+- *    is 1.82 (not counting the function values as implicit parameters).
+- *
+- *
+- *  2. Operators
+- *  ------------
+- *                          number    approximate
+- *                                    percentage
+- *
+- *    Arithmetic             32          50.8                                 
+- *
+- *       +                     21          33.3                              
+- *       -                      7          11.1                              
+- *       *                      3           4.8
+- *       / (int div)            1           1.6
+- *
+- *    Comparison             27           42.8
+- *
+- *       ==                     9           14.3
+- *       /=                     4            6.3
+- *       >                      1            1.6
+- *       <                      3            4.8
+- *       >=                     1            1.6
+- *       <=                     9           14.3
+- *
+- *    Logic                   4            6.3
+- *
+- *       && (AND-THEN)          1            1.6
+- *       |  (OR)                1            1.6
+- *       !  (NOT)               2            3.2
+- * 
+- *                           --          -----
+- *                           63          100.1
+- *
+- *
+- *  3. Operand Type (counted once per operand reference):
+- *  ---------------
+- *                          number    approximate
+- *                                    percentage
+- *
+- *     Integer               175        72.3 %
+- *     Character              45        18.6 %
+- *     Pointer                12         5.0 %
+- *     String30                6         2.5 %
+- *     Array                   2         0.8 %
+- *     Record                  2         0.8 %
+- *                           ---       -------
+- *                           242       100.0 %
+- *
+- *  When there is an access path leading to the final operand (e.g. a record
+- *  component), only the final data type on the access path is counted.       
+- *
+- *
+- *  4. Operand Locality:                                                      
+- *  -------------------
+- *                                number    approximate
+- *                                          percentage
+- *
+- *     local variable              114        47.1 %
+- *     global variable              22         9.1 %
+- *     parameter                    45        18.6 %
+- *        value                        23         9.5 %
+- *        reference                    22         9.1 %
+- *     function result               6         2.5 %
+- *     constant                     55        22.7 %
+- *                                 ---       -------
+- *                                 242       100.0 %
+- *
+- *
+- *  The program does not compute anything meaningful, but it is syntactically
+- *  and semantically correct. All variables have a value assigned to them
+- *  before they are used as a source operand.
+- *
+- *  There has been no explicit effort to account for the effects of a
+- *  cache, or to balance the use of long or short displacements for code or
+- *  data.
+- *
+- ***************************************************************************
+- */
+-
+-/* Compiler and system dependent definitions: */
+-
+-#ifndef TIME
+-#define TIMES
+-#endif
+-                /* Use times(2) time function unless    */
+-                /* explicitly defined otherwise         */
+-
+-#ifdef TIMES
+-#include <sys/types.h>
+-#include <sys/times.h>
+-                /* for "times" */
+-#endif
+-
+-#define Mic_secs_Per_Second     1000000.0
+-                /* Berkeley UNIX C returns process times in seconds/HZ */
+-
+-#ifdef  NOSTRUCTASSIGN
+-#define structassign(d, s)      memcpy(&(d), &(s), sizeof(d))
+-#else
+-#define structassign(d, s)      d = s
+-#endif
+-
+-#ifdef  NOENUM
+-#define Ident_1 0
+-#define Ident_2 1
+-#define Ident_3 2
+-#define Ident_4 3
+-#define Ident_5 4
+-  typedef int   Enumeration;
+-#else
+-  typedef       enum    {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+-                Enumeration;
+-#endif
+-        /* for boolean and enumeration types in Ada, Pascal */
+-
+-/* General definitions: */
+-
+-#include <stdio.h>
+-                /* for strcpy, strcmp */
+-
+-#define Null 0 
+-                /* Value of a Null pointer */
+-#define true  1
+-#define false 0
+-
+-typedef int     One_Thirty;
+-typedef int     One_Fifty;
+-typedef char    Capital_Letter;
+-typedef int     Boolean;
+-typedef char    Str_30 [31];
+-typedef int     Arr_1_Dim [50];
+-typedef int     Arr_2_Dim [50] [50];
+-
+-typedef struct record 
+-    {
+-    struct record *Ptr_Comp;
+-    Enumeration    Discr;
+-    union {
+-          struct {
+-                  Enumeration Enum_Comp;
+-                  int         Int_Comp;
+-                  char        Str_Comp [31];
+-                  } var_1;
+-          struct {
+-                  Enumeration E_Comp_2;
+-                  char        Str_2_Comp [31];
+-                  } var_2;
+-          struct {
+-                  char        Ch_1_Comp;
+-                  char        Ch_2_Comp;
+-                  } var_3;
+-          } variant;
+-      } Rec_Type, *Rec_Pointer;
+-
+-
+//GO.SYSIN DD dhry.h
+echo dhry_1.c 1>&2
+sed >dhry_1.c <<'//GO.SYSIN DD dhry_1.c' 's/^-//'
+-/*
+- ****************************************************************************
+- *
+- *                   "DHRYSTONE" Benchmark Program
+- *                   -----------------------------
+- *                                                                            
+- *  Version:    C, Version 2.1
+- *                                                                            
+- *  File:       dhry_1.c (part 2 of 3)
+- *
+- *  Date:       May 25, 1988
+- *
+- *  Author:     Reinhold P. Weicker
+- *
+- ****************************************************************************
+- */
+-
+-#include "dhry.h"
+-
+-/* Global Variables: */
+-
+-Rec_Pointer     Ptr_Glob,
+-                Next_Ptr_Glob;
+-int             Int_Glob;
+-Boolean         Bool_Glob;
+-char            Ch_1_Glob,
+-                Ch_2_Glob;
+-int             Arr_1_Glob [50];
+-int             Arr_2_Glob [50] [50];
+-
+-extern char     *malloc ();
+-Enumeration     Func_1 ();
+-  /* forward declaration necessary since Enumeration may not simply be int */
+-
+-#ifndef REG
+-        Boolean Reg = false;
+-#define REG
+-        /* REG becomes defined as empty */
+-        /* i.e. no register variables   */
+-#else
+-        Boolean Reg = true;
+-#endif
+-
+-/* variables for time measurement: */
+-
+-#ifdef TIMES
+-struct tms      time_info;
+-extern  int     times ();
+-                /* see library function "times" */
+-#define Too_Small_Time 120
+-                /* Measurements should last at least about 2 seconds */
+-#endif
+-#ifdef TIME
+-extern long     time();
+-                /* see library function "time"  */
+-#define Too_Small_Time 2
+-                /* Measurements should last at least 2 seconds */
+-#endif
+-
+-long            Begin_Time,
+-                End_Time,
+-                User_Time;
+-float           Microseconds,
+-                Dhrystones_Per_Second;
+-
+-/* end of variables for time measurement */
+-
+-
+-main ()
+-/*****/
+-
+-  /* main program, corresponds to procedures        */
+-  /* Main and Proc_0 in the Ada version             */
+-{
+-        One_Fifty       Int_1_Loc;
+-  REG   One_Fifty       Int_2_Loc;
+-        One_Fifty       Int_3_Loc;
+-  REG   char            Ch_Index;
+-        Enumeration     Enum_Loc;
+-        Str_30          Str_1_Loc;
+-        Str_30          Str_2_Loc;
+-  REG   int             Run_Index;
+-  REG   int             Number_Of_Runs;
+-
+-  /* Initializations */
+-
+-  Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+-  Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+-
+-  Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;
+-  Ptr_Glob->Discr                       = Ident_1;
+-  Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;
+-  Ptr_Glob->variant.var_1.Int_Comp      = 40;
+-  strcpy (Ptr_Glob->variant.var_1.Str_Comp, 
+-          "DHRYSTONE PROGRAM, SOME STRING");
+-  strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+-
+-  Arr_2_Glob [8][7] = 10;
+-        /* Was missing in published program. Without this statement,    */
+-        /* Arr_2_Glob [8][7] would have an undefined value.             */
+-        /* Warning: With 16-Bit processors and Number_Of_Runs > 32000,  */
+-        /* overflow may occur for this array element.                   */
+-
+-  printf ("\n");
+-  printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+-  printf ("\n");
+-  if (Reg)
+-  {
+-    printf ("Program compiled with 'register' attribute\n");
+-    printf ("\n");
+-  }
+-  else
+-  {
+-    printf ("Program compiled without 'register' attribute\n");
+-    printf ("\n");
+-  }
+-  printf ("Please give the number of runs through the benchmark: ");
+-  {
+-    int n;
+-    scanf ("%d", &n);
+-    Number_Of_Runs = n;
+-  }
+-  printf ("\n");
+-
+-  printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
+-
+-  /***************/
+-  /* Start timer */
+-  /***************/
+- 
+-#ifdef TIMES
+-  times (&time_info);
+-  Begin_Time = (long) time_info.tms_utime;
+-#endif
+-#ifdef TIME
+-  Begin_Time = time ( (long *) 0);
+-#endif
+-
+-  for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+-  {
+-
+-    Proc_5();
+-    Proc_4();
+-      /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+-    Int_1_Loc = 2;
+-    Int_2_Loc = 3;
+-    strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+-    Enum_Loc = Ident_2;
+-    Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+-      /* Bool_Glob == 1 */
+-    while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */
+-    {
+-      Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+-        /* Int_3_Loc == 7 */
+-      Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+-        /* Int_3_Loc == 7 */
+-      Int_1_Loc += 1;
+-    } /* while */
+-      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+-    Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+-      /* Int_Glob == 5 */
+-    Proc_1 (Ptr_Glob);
+-    for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+-                             /* loop body executed twice */
+-    {
+-      if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+-          /* then, not executed */
+-        {
+-        Proc_6 (Ident_1, &Enum_Loc);
+-        strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+-        Int_2_Loc = Run_Index;
+-        Int_Glob = Run_Index;
+-        }
+-    }
+-      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+-    Int_2_Loc = Int_2_Loc * Int_1_Loc;
+-    Int_1_Loc = Int_2_Loc / Int_3_Loc;
+-    Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+-      /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+-    Proc_2 (&Int_1_Loc);
+-      /* Int_1_Loc == 5 */
+-
+-  } /* loop "for Run_Index" */
+-
+-  /**************/
+-  /* Stop timer */
+-  /**************/
+-  
+-#ifdef TIMES
+-  times (&time_info);
+-  End_Time = (long) time_info.tms_utime;
+-#endif
+-#ifdef TIME
+-  End_Time = time ( (long *) 0);
+-#endif
+-
+-  printf ("Execution ends\n");
+-  printf ("\n");
+-  printf ("Final values of the variables used in the benchmark:\n");
+-  printf ("\n");
+-  printf ("Int_Glob:            %d\n", Int_Glob);
+-  printf ("        should be:   %d\n", 5);
+-  printf ("Bool_Glob:           %d\n", Bool_Glob);
+-  printf ("        should be:   %d\n", 1);
+-  printf ("Ch_1_Glob:           %c\n", Ch_1_Glob);
+-  printf ("        should be:   %c\n", 'A');
+-  printf ("Ch_2_Glob:           %c\n", Ch_2_Glob);
+-  printf ("        should be:   %c\n", 'B');
+-  printf ("Arr_1_Glob[8]:       %d\n", Arr_1_Glob[8]);
+-  printf ("        should be:   %d\n", 7);
+-  printf ("Arr_2_Glob[8][7]:    %d\n", Arr_2_Glob[8][7]);
+-  printf ("        should be:   Number_Of_Runs + 10\n");
+-  printf ("Ptr_Glob->\n");
+-  printf ("  Ptr_Comp:          %d\n", (int) Ptr_Glob->Ptr_Comp);
+-  printf ("        should be:   (implementation-dependent)\n");
+-  printf ("  Discr:             %d\n", Ptr_Glob->Discr);
+-  printf ("        should be:   %d\n", 0);
+-  printf ("  Enum_Comp:         %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+-  printf ("        should be:   %d\n", 2);
+-  printf ("  Int_Comp:          %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+-  printf ("        should be:   %d\n", 17);
+-  printf ("  Str_Comp:          %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+-  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+-  printf ("Next_Ptr_Glob->\n");
+-  printf ("  Ptr_Comp:          %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+-  printf ("        should be:   (implementation-dependent), same as above\n");
+-  printf ("  Discr:             %d\n", Next_Ptr_Glob->Discr);
+-  printf ("        should be:   %d\n", 0);
+-  printf ("  Enum_Comp:         %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+-  printf ("        should be:   %d\n", 1);
+-  printf ("  Int_Comp:          %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+-  printf ("        should be:   %d\n", 18);
+-  printf ("  Str_Comp:          %s\n",
+-                                Next_Ptr_Glob->variant.var_1.Str_Comp);
+-  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+-  printf ("Int_1_Loc:           %d\n", Int_1_Loc);
+-  printf ("        should be:   %d\n", 5);
+-  printf ("Int_2_Loc:           %d\n", Int_2_Loc);
+-  printf ("        should be:   %d\n", 13);
+-  printf ("Int_3_Loc:           %d\n", Int_3_Loc);
+-  printf ("        should be:   %d\n", 7);
+-  printf ("Enum_Loc:            %d\n", Enum_Loc);
+-  printf ("        should be:   %d\n", 1);
+-  printf ("Str_1_Loc:           %s\n", Str_1_Loc);
+-  printf ("        should be:   DHRYSTONE PROGRAM, 1'ST STRING\n");
+-  printf ("Str_2_Loc:           %s\n", Str_2_Loc);
+-  printf ("        should be:   DHRYSTONE PROGRAM, 2'ND STRING\n");
+-  printf ("\n");
+-
+-  User_Time = End_Time - Begin_Time;
+-
+-  if (User_Time < Too_Small_Time)
+-  {
+-    printf ("Measured time too small to obtain meaningful results\n");
+-    printf ("Please increase number of runs\n");
+-    printf ("\n");
+-  }
+-  else
+-  {
+-#ifdef TIME
+-    Microseconds = (float) User_Time * Mic_secs_Per_Second 
+-                        / (float) Number_Of_Runs;
+-    Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time;
+-#else
+-    Microseconds = (float) User_Time * Mic_secs_Per_Second 
+-                        / ((float) HZ * ((float) Number_Of_Runs));
+-    Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
+-                        / (float) User_Time;
+-#endif
+-    printf ("Microseconds for one run through Dhrystone: ");
+-    printf ("%6.1f \n", Microseconds);
+-    printf ("Dhrystones per Second:                      ");
+-    printf ("%6.1f \n", Dhrystones_Per_Second);
+-    printf ("\n");
+-  }
+-  
+-}
+-
+-
+-Proc_1 (Ptr_Val_Par)
+-/******************/
+-
+-REG Rec_Pointer Ptr_Val_Par;
+-    /* executed once */
+-{
+-  REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;  
+-                                        /* == Ptr_Glob_Next */
+-  /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */
+-  /* corresponds to "rename" in Ada, "with" in Pascal           */
+-  
+-  structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); 
+-  Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+-  Next_Record->variant.var_1.Int_Comp 
+-        = Ptr_Val_Par->variant.var_1.Int_Comp;
+-  Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+-  Proc_3 (&Next_Record->Ptr_Comp);
+-    /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp 
+-                        == Ptr_Glob->Ptr_Comp */
+-  if (Next_Record->Discr == Ident_1)
+-    /* then, executed */
+-  {
+-    Next_Record->variant.var_1.Int_Comp = 6;
+-    Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, 
+-           &Next_Record->variant.var_1.Enum_Comp);
+-    Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+-    Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, 
+-           &Next_Record->variant.var_1.Int_Comp);
+-  }
+-  else /* not executed */
+-    structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+-} /* Proc_1 */
+-
+-
+-Proc_2 (Int_Par_Ref)
+-/******************/
+-    /* executed once */
+-    /* *Int_Par_Ref == 1, becomes 4 */
+-
+-One_Fifty   *Int_Par_Ref;
+-{
+-  One_Fifty  Int_Loc;  
+-  Enumeration   Enum_Loc;
+-
+-  Int_Loc = *Int_Par_Ref + 10;
+-  do /* executed once */
+-    if (Ch_1_Glob == 'A')
+-      /* then, executed */
+-    {
+-      Int_Loc -= 1;
+-      *Int_Par_Ref = Int_Loc - Int_Glob;
+-      Enum_Loc = Ident_1;
+-    } /* if */
+-  while (Enum_Loc != Ident_1); /* true */
+-} /* Proc_2 */
+-
+-
+-Proc_3 (Ptr_Ref_Par)
+-/******************/
+-    /* executed once */
+-    /* Ptr_Ref_Par becomes Ptr_Glob */
+-
+-Rec_Pointer *Ptr_Ref_Par;
+-
+-{
+-  if (Ptr_Glob != Null)
+-    /* then, executed */
+-    *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+-  Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+-} /* Proc_3 */
+-
+-
+-Proc_4 () /* without parameters */
+-/*******/
+-    /* executed once */
+-{
+-  Boolean Bool_Loc;
+-
+-  Bool_Loc = Ch_1_Glob == 'A';
+-  Bool_Glob = Bool_Loc | Bool_Glob;
+-  Ch_2_Glob = 'B';
+-} /* Proc_4 */
+-
+-
+-Proc_5 () /* without parameters */
+-/*******/
+-    /* executed once */
+-{
+-  Ch_1_Glob = 'A';
+-  Bool_Glob = false;
+-} /* Proc_5 */
+-
+-
+-        /* Procedure for the assignment of structures,          */
+-        /* if the C compiler doesn't support this feature       */
+-#ifdef  NOSTRUCTASSIGN
+-memcpy (d, s, l)
+-register char   *d;
+-register char   *s;
+-register int    l;
+-{
+-        while (l--) *d++ = *s++;
+-}
+-#endif
+-
+-
+//GO.SYSIN DD dhry_1.c
+echo dhry_2.c 1>&2
+sed >dhry_2.c <<'//GO.SYSIN DD dhry_2.c' 's/^-//'
+-/*
+- ****************************************************************************
+- *
+- *                   "DHRYSTONE" Benchmark Program
+- *                   -----------------------------
+- *                                                                            
+- *  Version:    C, Version 2.1
+- *                                                                            
+- *  File:       dhry_2.c (part 3 of 3)
+- *
+- *  Date:       May 25, 1988
+- *
+- *  Author:     Reinhold P. Weicker
+- *
+- ****************************************************************************
+- */
+-
+-#include "dhry.h"
+-
+-#ifndef REG
+-#define REG
+-        /* REG becomes defined as empty */
+-        /* i.e. no register variables   */
+-#endif
+-
+-extern  int     Int_Glob;
+-extern  char    Ch_1_Glob;
+-
+-
+-Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+-/*********************************/
+-    /* executed once */
+-    /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+-
+-Enumeration  Enum_Val_Par;
+-Enumeration *Enum_Ref_Par;
+-{
+-  *Enum_Ref_Par = Enum_Val_Par;
+-  if (! Func_3 (Enum_Val_Par))
+-    /* then, not executed */
+-    *Enum_Ref_Par = Ident_4;
+-  switch (Enum_Val_Par)
+-  {
+-    case Ident_1: 
+-      *Enum_Ref_Par = Ident_1;
+-      break;
+-    case Ident_2: 
+-      if (Int_Glob > 100)
+-        /* then */
+-      *Enum_Ref_Par = Ident_1;
+-      else *Enum_Ref_Par = Ident_4;
+-      break;
+-    case Ident_3: /* executed */
+-      *Enum_Ref_Par = Ident_2;
+-      break;
+-    case Ident_4: break;
+-    case Ident_5: 
+-      *Enum_Ref_Par = Ident_3;
+-      break;
+-  } /* switch */
+-} /* Proc_6 */
+-
+-
+-Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+-/**********************************************/
+-    /* executed three times                                      */ 
+-    /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */
+-    /*                  Int_Par_Ref becomes 7                    */
+-    /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+-    /*                  Int_Par_Ref becomes 17                   */
+-    /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+-    /*                  Int_Par_Ref becomes 18                   */
+-One_Fifty       Int_1_Par_Val;
+-One_Fifty       Int_2_Par_Val;
+-One_Fifty      *Int_Par_Ref;
+-{
+-  One_Fifty Int_Loc;
+-
+-  Int_Loc = Int_1_Par_Val + 2;
+-  *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+-} /* Proc_7 */
+-
+-
+-Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+-/*********************************************************************/
+-    /* executed once      */
+-    /* Int_Par_Val_1 == 3 */
+-    /* Int_Par_Val_2 == 7 */
+-Arr_1_Dim       Arr_1_Par_Ref;
+-Arr_2_Dim       Arr_2_Par_Ref;
+-int             Int_1_Par_Val;
+-int             Int_2_Par_Val;
+-{
+-  REG One_Fifty Int_Index;
+-  REG One_Fifty Int_Loc;
+-
+-  Int_Loc = Int_1_Par_Val + 5;
+-  Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+-  Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+-  Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+-  for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+-    Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+-  Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+-  Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+-  Int_Glob = 5;
+-} /* Proc_8 */
+-
+-
+-Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+-/*************************************************/
+-    /* executed three times                                         */
+-    /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */
+-    /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */
+-    /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */
+-
+-Capital_Letter   Ch_1_Par_Val;
+-Capital_Letter   Ch_2_Par_Val;
+-{
+-  Capital_Letter        Ch_1_Loc;
+-  Capital_Letter        Ch_2_Loc;
+-
+-  Ch_1_Loc = Ch_1_Par_Val;
+-  Ch_2_Loc = Ch_1_Loc;
+-  if (Ch_2_Loc != Ch_2_Par_Val)
+-    /* then, executed */
+-    return (Ident_1);
+-  else  /* not executed */
+-  {
+-    Ch_1_Glob = Ch_1_Loc;
+-    return (Ident_2);
+-   }
+-} /* Func_1 */
+-
+-
+-Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+-/*************************************************/
+-    /* executed once */
+-    /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+-    /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+-
+-Str_30  Str_1_Par_Ref;
+-Str_30  Str_2_Par_Ref;
+-{
+-  REG One_Thirty        Int_Loc;
+-      Capital_Letter    Ch_Loc;
+-
+-  Int_Loc = 2;
+-  while (Int_Loc <= 2) /* loop body executed once */
+-    if (Func_1 (Str_1_Par_Ref[Int_Loc],
+-                Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+-      /* then, executed */
+-    {
+-      Ch_Loc = 'A';
+-      Int_Loc += 1;
+-    } /* if, while */
+-  if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+-    /* then, not executed */
+-    Int_Loc = 7;
+-  if (Ch_Loc == 'R')
+-    /* then, not executed */
+-    return (true);
+-  else /* executed */
+-  {
+-    if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+-      /* then, not executed */
+-    {
+-      Int_Loc += 7;
+-      Int_Glob = Int_Loc;
+-      return (true);
+-    }
+-    else /* executed */
+-      return (false);
+-  } /* if Ch_Loc */
+-} /* Func_2 */
+-
+-
+-Boolean Func_3 (Enum_Par_Val)
+-/***************************/
+-    /* executed once        */
+-    /* Enum_Par_Val == Ident_3 */
+-Enumeration Enum_Par_Val;
+-{
+-  Enumeration Enum_Loc;
+-
+-  Enum_Loc = Enum_Par_Val;
+-  if (Enum_Loc == Ident_3)
+-    /* then, executed */
+-    return (true);
+-  else /* not executed */
+-    return (false);
+-} /* Func_3 */
+-
+//GO.SYSIN DD dhry_2.c
+echo dhry_c.dif 1>&2
+sed >dhry_c.dif <<'//GO.SYSIN DD dhry_c.dif' 's/^-//'
+-7c7
+-<  *  Version:    C, Version 2.1
+----
+->  *  Version:    C, Version 2.0
+-9c9
+-<  *  File:       dhry.h (part 1 of 3)
+----
+->  *  File:       dhry_global.h (part 1 of 3)
+-11c11
+-<  *  Date:       May 25, 1988
+----
+->  *  Date:       March 3, 1988
+-30c30
+-<  *              In addition, Berkeley UNIX system calls "times ()" or "time ()"
+----
+->  *              In addition, UNIX system calls "times ()" or "time ()"
+-44c44
+-<  *      Please send results to Rick Richardson and/or Reinhold Weicker.
+----
+->  *      Please send results to Reinhold Weicker and/or Rick Richardson.
+-59c59
+-<  *  History:    This version C/2.1 has been made for two reasons:
+----
+->  *  History:    This version C/2.0 has been made for two reasons:
+-123,129d122
+-<  *              Version 2.1 is identical to version 2.0 distributed via
+-<  *              the UNIX network Usenet in March 1988 except that it corrects
+-<  *              some minor deficiencies that were found by users of version 2.0.
+-<  *              The only change within the measurement loop is that a
+-<  *              non-executed "else" part was added to the "if" statement in
+-<  *              Func_3, and a non-executed "else" part removed from Proc_3.
+-<  *
+-165,167c158,160
+-<  *              -DHZ=nnn
+-<  *                      In Berkeley UNIX, the function "times" returns process
+-<  *                      time in 1/HZ seconds, with HZ = 60 for most systems.
+----
+->  *              -DHZ=nnn                (default: 60)
+->  *                      The function "times" returns process times in
+->  *                      1/HZ seconds, with HZ = 60 for most systems.
+-169c162
+-<  *                      A VALUE.
+----
+->  *                      THE DEFAULT VALUE.
+-176,178c169,171
+-<  *  - dhry.h (this file, containing global definitions and comments)
+-<  *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+-<  *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+----
+->  *  - dhry_global.h (this file, containing global definitions and comments)
+->  *  - dhry_pack_1.c (containing the code corresponding to Ada package Pack_1)
+->  *  - dhry_pack_2.c (containing the code corresponding to Ada package Pack_2)
+-350a344
+-> #ifndef TIMES
+-353,354c347,354
+-<                 /* Use times(2) time function unless    */
+-<                 /* explicitly defined otherwise         */
+----
+-> #endif
+->                 /* Use "times" function for measurement */
+->                 /* unless explicitly defined otherwise  */
+-> #ifndef HZ
+-> #define HZ      60
+-> #endif
+->                 /* Use HZ = 60 for "times" function     */
+->                 /* unless explicitly defined otherwise  */
+-363c363
+-<                 /* Berkeley UNIX C returns process times in seconds/HZ */
+----
+->                 /* UNIX C returns process times in seconds/HZ */
+-7c7
+-<  *  Version:    C, Version 2.1
+----
+->  *  Version:    C, Version 2.0
+-9c9
+-<  *  File:       dhry_1.c (part 2 of 3)
+----
+->  *  File:       dhry_pack_1.c (part 2 of 3)
+-11c11
+-<  *  Date:       May 25, 1988
+----
+->  *  Date:       March 3, 1988
+-18c18
+-< #include "dhry.h"
+----
+-> #include "dhry_global.h"
+-50,51d49
+-< #define Too_Small_Time 120
+-<                 /* Measurements should last at least about 2 seconds */
+-55a54,55
+-> #endif
+-> 
+-58d57
+-< #endif
+-73a73
+-> 
+-84a85
+-> 
+-99,100c100,102
+-<         /* Was missing in published program. Without this statement,    */
+-<         /* Arr_2_Glob [8][7] would have an undefined value.             */
+----
+->         /* Was missing in published program. Without this               */
+->         /* initialization, Arr_2_Glob [8][7] would have an              */
+->         /* undefined value.                                             */
+-105c107
+-<   printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+----
+->   printf ("Dhrystone Benchmark, Version 2.0 (Language: C)\n");
+-281c283
+-< /******************/
+----
+-> /**********************/
+-338c340
+-< /******************/
+----
+-> /**********************/
+-347a350,351
+->   else /* not executed */
+->     Int_Glob = 100;
+-349a354
+-> 
+-7c7
+-<  *  Version:    C, Version 2.1
+----
+->  *  Version:    C, Version 2.0
+-9c9
+-<  *  File:       dhry_2.c (part 3 of 3)
+----
+->  *  File:       dhry_pack_2.c (part 3 of 3)
+-11c11
+-<  *  Date:       May 25, 1988
+----
+->  *  Date:       March 3, 1988
+-18c18
+-< #include "dhry.h"
+----
+-> #include "dhry_global.h"
+-189,190d188
+-<   else /* not executed */
+-<     return (false);
+//GO.SYSIN DD dhry_c.dif
+echo submit.frm 1>&2
+sed >submit.frm <<'//GO.SYSIN DD submit.frm' 's/^-//'
+-DHRYSTONE 2.1 BENCHMARK REPORTING FORM
+-MANUF:
+-MODEL:
+-PROC:
+-CLOCK:
+-OS:
+-OVERSION:
+-COMPILER:
+-CVERSION:
+-OPTIONS:
+-NOREG:
+-REG:
+-NOTES:
+-DATE:
+-SUBMITTER:
+-CODESIZE:
+-MAILTO: uunet!pcrat!dry2
+//GO.SYSIN DD submit.frm
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry.h b/zpu/roadshow/roadshow/dhrystone/dhry.h
new file mode 100644
index 0000000..211c2e2
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry.h
@@ -0,0 +1,423 @@
+/*
+ ****************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *                                                                            
+ *  Version:    C, Version 2.1
+ *                                                                            
+ *  File:       dhry.h (part 1 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *                      Siemens AG, AUT E 51
+ *                      Postfach 3220
+ *                      8520 Erlangen
+ *                      Germany (West)
+ *                              Phone:  [+49]-9131-7-20330
+ *                                      (8-17 Central European Time)
+ *                              Usenet: ..!mcsun!unido!estevax!weicker
+ *
+ *              Original Version (in Ada) published in
+ *              "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ *              pp. 1013 - 1030, together with the statistics
+ *              on which the distribution of statements etc. is based.
+ *
+ *              In this C version, the following C library functions are used:
+ *              - strcpy, strcmp (inside the measurement loop)
+ *              - printf, scanf (outside the measurement loop)
+ *              In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ *              are used for execution time measurement. For measurements
+ *              on other systems, these calls have to be changed.
+ *
+ *  Collection of Results:
+ *              Reinhold Weicker (address see above) and
+ *              
+ *              Rick Richardson
+ *              PC Research. Inc.
+ *              94 Apple Orchard Drive
+ *              Tinton Falls, NJ 07724
+ *                      Phone:  (201) 389-8963 (9-17 EST)               
+ *                      Usenet: ...!uunet!pcrat!rick
+ *
+ *      Please send results to Rick Richardson and/or Reinhold Weicker.
+ *      Complete information should be given on hardware and software used.
+ *      Hardware information includes: Machine type, CPU, type and size
+ *      of caches; for microprocessors: clock frequency, memory speed
+ *      (number of wait states).
+ *      Software information includes: Compiler (and runtime library)
+ *      manufacturer and version, compilation switches, OS version.
+ *      The Operating System version may give an indication about the
+ *      compiler; Dhrystone itself performs no OS calls in the measurement loop.
+ *
+ *      The complete output generated by the program should be mailed
+ *      such that at least some checks for correctness can be made.
+ *
+ ***************************************************************************
+ *
+ *  History:    This version C/2.1 has been made for two reasons:
+ *
+ *              1) There is an obvious need for a common C version of
+ *              Dhrystone, since C is at present the most popular system
+ *              programming language for the class of processors
+ *              (microcomputers, minicomputers) where Dhrystone is used most.
+ *              There should be, as far as possible, only one C version of
+ *              Dhrystone such that results can be compared without
+ *              restrictions. In the past, the C versions distributed
+ *              by Rick Richardson (Version 1.1) and by Reinhold Weicker
+ *              had small (though not significant) differences.
+ *
+ *              2) As far as it is possible without changes to the Dhrystone
+ *              statistics, optimizing compilers should be prevented from
+ *              removing significant statements.
+ *
+ *              This C version has been developed in cooperation with
+ *              Rick Richardson (Tinton Falls, NJ), it incorporates many
+ *              ideas from the "Version 1.1" distributed previously by
+ *              him over the UNIX network Usenet.
+ *              I also thank Chaim Benedelac (National Semiconductor),
+ *              David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ *              Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ *              for their help with comments on earlier versions of the
+ *              benchmark.
+ *
+ *  Changes:    In the initialization part, this version follows mostly
+ *              Rick Richardson's version distributed via Usenet, not the
+ *              version distributed earlier via floppy disk by Reinhold Weicker.
+ *              As a concession to older compilers, names have been made
+ *              unique within the first 8 characters.
+ *              Inside the measurement loop, this version follows the
+ *              version previously distributed by Reinhold Weicker.
+ *
+ *              At several places in the benchmark, code has been added,
+ *              but within the measurement loop only in branches that 
+ *              are not executed. The intention is that optimizing compilers
+ *              should be prevented from moving code out of the measurement
+ *              loop, or from removing code altogether. Since the statements
+ *              that are executed within the measurement loop have NOT been
+ *              changed, the numbers defining the "Dhrystone distribution"
+ *              (distribution of statements, operand types and locality)
+ *              still hold. Except for sophisticated optimizing compilers,
+ *              execution times for this version should be the same as
+ *              for previous versions.
+ *              
+ *              Since it has proven difficult to subtract the time for the
+ *              measurement loop overhead in a correct way, the loop check
+ *              has been made a part of the benchmark. This does have
+ *              an impact - though a very minor one - on the distribution
+ *              statistics which have been updated for this version.
+ *
+ *              All changes within the measurement loop are described
+ *              and discussed in the companion paper "Rationale for
+ *              Dhrystone version 2".
+ *
+ *              Because of the self-imposed limitation that the order and
+ *              distribution of the executed statements should not be
+ *              changed, there are still cases where optimizing compilers
+ *              may not generate code for some statements. To a certain
+ *              degree, this is unavoidable for small synthetic benchmarks.
+ *              Users of the benchmark are advised to check code listings
+ *              whether code is generated for all statements of Dhrystone.
+ *
+ *              Version 2.1 is identical to version 2.0 distributed via
+ *              the UNIX network Usenet in March 1988 except that it corrects
+ *              some minor deficiencies that were found by users of version 2.0.
+ *              The only change within the measurement loop is that a
+ *              non-executed "else" part was added to the "if" statement in
+ *              Func_3, and a non-executed "else" part removed from Proc_3.
+ *
+ ***************************************************************************
+ *
+ * Defines:     The following "Defines" are possible:
+ *              -DREG=register          (default: Not defined)
+ *                      As an approximation to what an average C programmer
+ *                      might do, the "register" storage class is applied
+ *                      (if enabled by -DREG=register)
+ *                      - for local variables, if they are used (dynamically)
+ *                        five or more times
+ *                      - for parameters if they are used (dynamically)
+ *                        six or more times
+ *                      Note that an optimal "register" strategy is
+ *                      compiler-dependent, and that "register" declarations
+ *                      do not necessarily lead to faster execution.
+ *              -DNOSTRUCTASSIGN        (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      assignment of structures.
+ *              -DNOENUMS               (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      enumeration types.
+ *              -DTIMES                 (default)
+ *              -DTIME
+ *                      The "times" function of UNIX (returning process times)
+ *                      or the "time" function (returning wallclock time)
+ *                      is used for measurement. 
+ *                      For single user machines, "time ()" is adequate. For
+ *                      multi-user machines where you cannot get single-user
+ *                      access, use the "times ()" function. If you have
+ *                      neither, use a stopwatch in the dead of night.
+ *                      "printf"s are provided marking the points "Start Timer"
+ *                      and "Stop Timer". DO NOT use the UNIX "time(1)"
+ *                      command, as this will measure the total time to
+ *                      run this program, which will (erroneously) include
+ *                      the time to allocate storage (malloc) and to perform
+ *                      the initialization.
+ *              -DHZ=nnn
+ *                      In Berkeley UNIX, the function "times" returns process
+ *                      time in 1/HZ seconds, with HZ = 60 for most systems.
+ *                      CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+ *                      A VALUE.
+ *
+ ***************************************************************************
+ *
+ *  Compilation model and measurement (IMPORTANT):
+ *
+ *  This C version of Dhrystone consists of three files:
+ *  - dhry.h (this file, containing global definitions and comments)
+ *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ *  The following "ground rules" apply for measurements:
+ *  - Separate compilation
+ *  - No procedure merging
+ *  - Otherwise, compiler optimizations are allowed but should be indicated
+ *  - Default results are those without register declarations
+ *  See the companion paper "Rationale for Dhrystone Version 2" for a more
+ *  detailed discussion of these ground rules.
+ *
+ *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ *  models ("small", "medium", "large" etc.) should be given if possible,
+ *  together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *
+ *  Dhrystone (C version) statistics:
+ *
+ *  [Comment from the first distribution, updated for version 2.
+ *   Note that because of language differences, the numbers are slightly
+ *   different from the Ada version.]
+ *
+ *  The following program contains statements of a high level programming
+ *  language (here: C) in a distribution considered representative:           
+ *
+ *    assignments                  52 (51.0 %)
+ *    control statements           33 (32.4 %)
+ *    procedure, function calls    17 (16.7 %)
+ *
+ *  103 statements are dynamically executed. The program is balanced with
+ *  respect to the three aspects:                                             
+ *
+ *    - statement type
+ *    - operand type
+ *    - operand locality
+ *         operand global, local, parameter, or constant.                     
+ *
+ *  The combination of these three aspects is balanced only approximately.    
+ *
+ *  1. Statement Type:                                                        
+ *  -----------------             number
+ *
+ *     V1 = V2                     9
+ *       (incl. V1 = F(..)
+ *     V = Constant               12
+ *     Assignment,                 7
+ *       with array element
+ *     Assignment,                 6
+ *       with record component
+ *                                --
+ *                                34       34
+ *
+ *     X = Y +|-|"&&"|"|" Z        5
+ *     X = Y +|-|"==" Constant     6
+ *     X = X +|- 1                 3
+ *     X = Y *|/ Z                 2
+ *     X = Expression,             1
+ *           two operators
+ *     X = Expression,             1
+ *           three operators
+ *                                --
+ *                                18       18
+ *
+ *     if ....                    14
+ *       with "else"      7
+ *       without "else"   7
+ *           executed        3
+ *           not executed    4
+ *     for ...                     7  |  counted every time
+ *     while ...                   4  |  the loop condition
+ *     do ... while                1  |  is evaluated
+ *     switch ...                  1
+ *     break                       1
+ *     declaration with            1
+ *       initialization
+ *                                --
+ *                                34       34
+ *
+ *     P (...)  procedure call    11
+ *       user procedure      10
+ *       library procedure    1
+ *     X = F (...)
+ *             function  call      6
+ *       user function        5                                         
+ *       library function     1                                               
+ *                                --                                          
+ *                                17       17
+ *                                        ---
+ *                                        103
+ *
+ *    The average number of parameters in procedure or function calls
+ *    is 1.82 (not counting the function values as implicit parameters).
+ *
+ *
+ *  2. Operators
+ *  ------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *    Arithmetic             32          50.8                                 
+ *
+ *       +                     21          33.3                              
+ *       -                      7          11.1                              
+ *       *                      3           4.8
+ *       / (int div)            1           1.6
+ *
+ *    Comparison             27           42.8
+ *
+ *       ==                     9           14.3
+ *       /=                     4            6.3
+ *       >                      1            1.6
+ *       <                      3            4.8
+ *       >=                     1            1.6
+ *       <=                     9           14.3
+ *
+ *    Logic                   4            6.3
+ *
+ *       && (AND-THEN)          1            1.6
+ *       |  (OR)                1            1.6
+ *       !  (NOT)               2            3.2
+ * 
+ *                           --          -----
+ *                           63          100.1
+ *
+ *
+ *  3. Operand Type (counted once per operand reference):
+ *  ---------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *     Integer               175        72.3 %
+ *     Character              45        18.6 %
+ *     Pointer                12         5.0 %
+ *     String30                6         2.5 %
+ *     Array                   2         0.8 %
+ *     Record                  2         0.8 %
+ *                           ---       -------
+ *                           242       100.0 %
+ *
+ *  When there is an access path leading to the final operand (e.g. a record
+ *  component), only the final data type on the access path is counted.       
+ *
+ *
+ *  4. Operand Locality:                                                      
+ *  -------------------
+ *                                number    approximate
+ *                                          percentage
+ *
+ *     local variable              114        47.1 %
+ *     global variable              22         9.1 %
+ *     parameter                    45        18.6 %
+ *        value                        23         9.5 %
+ *        reference                    22         9.1 %
+ *     function result               6         2.5 %
+ *     constant                     55        22.7 %
+ *                                 ---       -------
+ *                                 242       100.0 %
+ *
+ *
+ *  The program does not compute anything meaningful, but it is syntactically
+ *  and semantically correct. All variables have a value assigned to them
+ *  before they are used as a source operand.
+ *
+ *  There has been no explicit effort to account for the effects of a
+ *  cache, or to balance the use of long or short displacements for code or
+ *  data.
+ *
+ ***************************************************************************
+ */
+
+/* Compiler and system dependent definitions: */
+
+#ifndef TIME
+#define TIMES
+#endif
+                /* Use times(2) time function unless    */
+                /* explicitly defined otherwise         */
+
+#ifdef TIMES
+#include <sys/types.h>
+#include <sys/times.h>
+                /* for "times" */
+#endif
+
+#define Mic_secs_Per_Second     1000000
+                /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef  NOSTRUCTASSIGN
+#define structassign(d, s)      memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s)      d = s
+#endif
+
+#ifdef  NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+  typedef int   Enumeration;
+#else
+  typedef       enum    {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+                Enumeration;
+#endif
+        /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+                /* for strcpy, strcmp */
+
+#define Null 0 
+                /* Value of a Null pointer */
+#define true  1
+#define false 0
+
+typedef int     One_Thirty;
+typedef int     One_Fifty;
+typedef char    Capital_Letter;
+typedef int     Boolean;
+typedef char    Str_30 [31];
+typedef int     Arr_1_Dim [50];
+typedef int     Arr_2_Dim [50] [50];
+
+typedef struct record 
+    {
+    struct record *Ptr_Comp;
+    Enumeration    Discr;
+    union {
+          struct {
+                  Enumeration Enum_Comp;
+                  int         Int_Comp;
+                  char        Str_Comp [31];
+                  } var_1;
+          struct {
+                  Enumeration E_Comp_2;
+                  char        Str_2_Comp [31];
+                  } var_2;
+          struct {
+                  char        Ch_1_Comp;
+                  char        Ch_2_Comp;
+                  } var_3;
+          } variant;
+      } Rec_Type, *Rec_Pointer;
+
+
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry_1.c b/zpu/roadshow/roadshow/dhrystone/dhry_1.c
new file mode 100644
index 0000000..08a29b9
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry_1.c
@@ -0,0 +1,533 @@
+/*
+ ****************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *                                                                            
+ *  Version:    C, Version 2.1
+ *                                                                            
+ *  File:       dhry_1.c (part 2 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#include "dhry.h"
+#include <stdarg.h>
+
+static int
+_cvt(int val, char *buf, int radix, char *digits)
+{
+    char temp[80];
+    char *cp = temp;
+    int length = 0;
+
+    if (val == 0) {
+        /* Special case */
+        *cp++ = '0';
+    } else {
+        while (val) {
+            *cp++ = digits[val % radix];
+            val /= radix;
+        }
+    }
+    while (cp != temp) {
+        *buf++ = *--cp;
+        length++;
+    }
+    *buf = '\0';
+    return (length);
+}
+
+#define is_digit(c) ((c >= '0') && (c <= '9'))
+
+
+#ifndef TINY
+static int
+_vprintf(void (*putc)(char c, void **param), void **param, const char *fmt, va_list ap)
+{
+    char buf[sizeof(long long)*8];
+    char c, sign, *cp=buf;
+    int left_prec, right_prec, zero_fill, pad, pad_on_right, 
+        i, islong, islonglong;
+    long long val = 0;
+    int res = 0, length = 0;
+
+    while ((c = *fmt++) != '\0') {
+        if (c == '%') {
+            c = *fmt++;
+            left_prec = right_prec = pad_on_right = islong = islonglong = 0;
+            sign = '\0';
+            // Fetch value [numeric descriptors only]
+            switch (c) {
+            case 'd':
+                    val = (long long)va_arg(ap, int);
+                if ((c == 'd') || (c == 'D')) {
+                    if (val < 0) {
+                        sign = '-';
+                        val = -val;
+                    }
+                } else {
+                    // Mask to unsigned, sized quantity
+                    if (islong) {
+                        val &= ((long long)1 << (sizeof(long) * 8)) - 1;
+                    } else{
+                        val &= ((long long)1 << (sizeof(int) * 8)) - 1;
+                    }
+                }
+                break;
+            default:
+                break;
+            }
+            // Process output
+            switch (c) {
+            case 'd':
+                switch (c) {
+                case 'd':
+                    length = _cvt(val, buf, 10, "0123456789");
+                    break;
+                }
+                cp = buf;
+                break;
+            case 's':
+                cp = va_arg(ap, char *);
+                length = 0;
+                while (cp[length] != '\0') length++;
+                break;
+            case 'c':
+                c = va_arg(ap, int /*char*/);
+                (*putc)(c, param);
+                res++;
+                continue;
+            default:
+                (*putc)('%', param);
+                (*putc)(c, param);
+                res += 2;
+                continue;
+            }
+            while (length-- > 0) {
+                c = *cp++;
+                (*putc)(c, param);
+                res++;
+            }
+        } else {
+            (*putc)(c, param);
+            res++;
+        }
+    }
+    return (res);
+}
+#endif
+
+// Default wrapper function used by diag_printf
+static void
+_diag_write_char(char c, void **param)
+{
+	if (c=='\n')
+	{
+		outbyte('\r');
+	}
+	outbyte(c);
+}
+
+int
+small_printf(const char *fmt, ...)
+{
+#ifndef TINY
+    va_list ap;
+    int ret;
+
+    va_start(ap, fmt);
+    ret = _vprintf(_diag_write_char, (void **)0, fmt, ap);
+    va_end(ap);
+    return (ret);
+#else
+	return 0;
+#endif
+}
+
+
+
+
+/* Global Variables: */
+
+Rec_Pointer     Ptr_Glob,
+                Next_Ptr_Glob;
+int             Int_Glob;
+Boolean         Bool_Glob;
+char            Ch_1_Glob,
+                Ch_2_Glob;
+int             Arr_1_Glob [50];
+int             Arr_2_Glob [50] [50];
+
+Enumeration     Func_1 ();
+  /* forward declaration necessary since Enumeration may not simply be int */
+
+#ifndef REG
+        Boolean Reg = false;
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#else
+        Boolean Reg = true;
+#endif
+
+/* variables for time measurement: */
+
+#ifdef TIMES
+struct tms      time_info;
+                /* see library function "times" */
+#define Too_Small_Time 120
+                /* Measurements should last at least about 2 seconds */
+#endif
+#ifdef TIME
+extern long     time();
+                /* see library function "time"  */
+#define Too_Small_Time 2
+                /* Measurements should last at least 2 seconds */
+#endif
+
+long long           Begin_Time,
+                End_Time,
+                User_Time;
+long long            Microseconds,
+                Dhrystones_Per_Second,
+                Vax_Mips;
+                
+/* end of variables for time measurement */
+
+int             Number_Of_Runs = 50000;
+
+extern long long _readMicroseconds();
+
+
+int main ()
+/*****/
+
+  /* main program, corresponds to procedures        */
+  /* Main and Proc_0 in the Ada version             */
+{
+        One_Fifty       Int_1_Loc;
+  REG   One_Fifty       Int_2_Loc;
+        One_Fifty       Int_3_Loc;
+  REG   char            Ch_Index;
+        Enumeration     Enum_Loc;
+        Str_30          Str_1_Loc;
+        Str_30          Str_2_Loc;
+  REG   int             Run_Index;
+
+  /* Initializations */
+
+  Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+  Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+
+  Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;
+  Ptr_Glob->Discr                       = Ident_1;
+  Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;
+  Ptr_Glob->variant.var_1.Int_Comp      = 40;
+  strcpy (Ptr_Glob->variant.var_1.Str_Comp, 
+          "DHRYSTONE PROGRAM, SOME STRING");
+  strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+  Arr_2_Glob [8][7] = 10;
+        /* Was missing in published program. Without this statement,    */
+        /* Arr_2_Glob [8][7] would have an undefined value.             */
+        /* Warning: With 16-Bit processors and Number_Of_Runs > 32000,  */
+        /* overflow may occur for this array element.                   */
+  small_printf ("\n");
+  small_printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+  small_printf ("\n");
+  if (Reg)
+  {
+    small_printf ("Program compiled with 'register' attribute\n");
+    small_printf ("\n");
+  }
+  else
+  {
+    small_printf ("Program compiled without 'register' attribute\n");
+    small_printf ("\n");
+  }
+  Number_Of_Runs;
+
+  small_printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
+
+  /***************/
+  /* Start timer */
+  /***************/
+
+#if 0
+#ifdef TIMES
+  times (&time_info);
+  Begin_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+  Begin_Time = time ( (long *) 0);
+#endif
+#else
+  Begin_Time = _readMicroseconds();
+#endif
+  for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+  {
+
+    Proc_5();
+    Proc_4();
+      /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+    Int_1_Loc = 2;
+    Int_2_Loc = 3;
+    strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+    Enum_Loc = Ident_2;
+    Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+      /* Bool_Glob == 1 */
+    while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */
+    {
+      Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+        /* Int_3_Loc == 7 */
+      Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+        /* Int_3_Loc == 7 */
+      Int_1_Loc += 1;
+    } /* while */
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+      /* Int_Glob == 5 */
+    Proc_1 (Ptr_Glob);
+    for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+                             /* loop body executed twice */
+    {
+      if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+          /* then, not executed */
+        {
+        Proc_6 (Ident_1, &Enum_Loc);
+        strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+        Int_2_Loc = Run_Index;
+        Int_Glob = Run_Index;
+        }
+    }
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Int_2_Loc = Int_2_Loc * Int_1_Loc;
+    Int_1_Loc = Int_2_Loc / Int_3_Loc;
+    Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+      /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+    Proc_2 (&Int_1_Loc);
+      /* Int_1_Loc == 5 */
+
+  } /* loop "for Run_Index" */
+
+  /**************/
+  /* Stop timer */
+  /**************/
+  
+#if 0
+#ifdef TIMES
+  times (&time_info);
+  End_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+  End_Time = time ( (long *) 0);
+#endif
+#else
+  End_Time = _readMicroseconds();
+#endif
+  
+  small_printf ("Execution ends\n");
+  small_printf ("\n");
+  small_printf ("Final values of the variables used in the benchmark:\n");
+  small_printf ("\n");
+  small_printf ("Int_Glob:            %d\n", Int_Glob);
+  small_printf ("        should be:   %d\n", 5);
+  small_printf ("Bool_Glob:           %d\n", Bool_Glob);
+  small_printf ("        should be:   %d\n", 1);
+  small_printf ("Ch_1_Glob:           %c\n", Ch_1_Glob);
+  small_printf ("        should be:   %c\n", 'A');
+  small_printf ("Ch_2_Glob:           %c\n", Ch_2_Glob);
+  small_printf ("        should be:   %c\n", 'B');
+  small_printf ("Arr_1_Glob[8]:       %d\n", Arr_1_Glob[8]);
+  small_printf ("        should be:   %d\n", 7);
+  small_printf ("Arr_2_Glob[8][7]:    %d\n", Arr_2_Glob[8][7]);
+  small_printf ("        should be:   Number_Of_Runs + 10\n");
+  small_printf ("Ptr_Glob->\n");
+  small_printf ("  Ptr_Comp:          %d\n", (int) Ptr_Glob->Ptr_Comp);
+  small_printf ("        should be:   (implementation-dependent)\n");
+  small_printf ("  Discr:             %d\n", Ptr_Glob->Discr);
+  small_printf ("        should be:   %d\n", 0);
+  small_printf ("  Enum_Comp:         %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+  small_printf ("        should be:   %d\n", 2);
+  small_printf ("  Int_Comp:          %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+  small_printf ("        should be:   %d\n", 17);
+  small_printf ("  Str_Comp:          %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+  small_printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  small_printf ("Next_Ptr_Glob->\n");
+  small_printf ("  Ptr_Comp:          %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+  small_printf ("        should be:   (implementation-dependent), same as above\n");
+  small_printf ("  Discr:             %d\n", Next_Ptr_Glob->Discr);
+  small_printf ("        should be:   %d\n", 0);
+  small_printf ("  Enum_Comp:         %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+  small_printf ("        should be:   %d\n", 1);
+  small_printf ("  Int_Comp:          %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+  small_printf ("        should be:   %d\n", 18);
+  small_printf ("  Str_Comp:          %s\n",
+                                Next_Ptr_Glob->variant.var_1.Str_Comp);
+  small_printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  small_printf ("Int_1_Loc:           %d\n", Int_1_Loc);
+  small_printf ("        should be:   %d\n", 5);
+  small_printf ("Int_2_Loc:           %d\n", Int_2_Loc);
+  small_printf ("        should be:   %d\n", 13);
+  small_printf ("Int_3_Loc:           %d\n", Int_3_Loc);
+  small_printf ("        should be:   %d\n", 7);
+  small_printf ("Enum_Loc:            %d\n", Enum_Loc);
+  small_printf ("        should be:   %d\n", 1);
+  small_printf ("Str_1_Loc:           %s\n", Str_1_Loc);
+  small_printf ("        should be:   DHRYSTONE PROGRAM, 1'ST STRING\n");
+  small_printf ("Str_2_Loc:           %s\n", Str_2_Loc);
+  small_printf ("        should be:   DHRYSTONE PROGRAM, 2'ND STRING\n");
+  small_printf ("\n");
+
+  User_Time = End_Time - Begin_Time;
+  small_printf ("User time: %d\n", (int)User_Time);
+  
+  if (User_Time < Too_Small_Time)
+  {
+    small_printf ("Measured time too small to obtain meaningful results\n");
+    small_printf ("Please increase number of runs\n");
+    small_printf ("\n");
+  }
+/*   else */
+  {
+#if 0
+#ifdef TIME
+    Microseconds = (User_Time * Mic_secs_Per_Second )
+                        /  Number_Of_Runs;
+    Dhrystones_Per_Second =  Number_Of_Runs / User_Time;
+    Vax_Mips = (Number_Of_Runs*1000) / (1757*User_Time);
+#else
+    Microseconds = (float) User_Time * Mic_secs_Per_Second 
+                        / ((float) HZ * ((float) Number_Of_Runs));
+    Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
+                        / (float) User_Time;
+    Vax_Mips = Dhrystones_Per_Second / 1757.0;
+#endif
+#else
+    Microseconds = User_Time  / Number_Of_Runs;
+    Dhrystones_Per_Second =  ((long long)Number_Of_Runs*1000000) / User_Time;
+    Vax_Mips = (((long long)Number_Of_Runs)*1000000000) / (1757*User_Time);
+#endif 
+    small_printf ("Microseconds for one run through Dhrystone: ");
+    small_printf ("%d \n", (int)Microseconds);
+    small_printf ("Dhrystones per Second:                      ");
+    small_printf ("%d \n", (int)Dhrystones_Per_Second);
+    small_printf ("VAX MIPS rating * 1000 = %d \n",(int)Vax_Mips);
+    small_printf ("\n");
+  }
+  
+  return 0;
+}
+
+
+Proc_1 (Ptr_Val_Par)
+/******************/
+
+REG Rec_Pointer Ptr_Val_Par;
+    /* executed once */
+{
+  REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;  
+                                        /* == Ptr_Glob_Next */
+  /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */
+  /* corresponds to "rename" in Ada, "with" in Pascal           */
+  
+  structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); 
+  Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+  Next_Record->variant.var_1.Int_Comp 
+        = Ptr_Val_Par->variant.var_1.Int_Comp;
+  Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+  Proc_3 (&Next_Record->Ptr_Comp);
+    /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp 
+                        == Ptr_Glob->Ptr_Comp */
+  if (Next_Record->Discr == Ident_1)
+    /* then, executed */
+  {
+    Next_Record->variant.var_1.Int_Comp = 6;
+    Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, 
+           &Next_Record->variant.var_1.Enum_Comp);
+    Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+    Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, 
+           &Next_Record->variant.var_1.Int_Comp);
+  }
+  else /* not executed */
+    structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+
+Proc_2 (Int_Par_Ref)
+/******************/
+    /* executed once */
+    /* *Int_Par_Ref == 1, becomes 4 */
+
+One_Fifty   *Int_Par_Ref;
+{
+  One_Fifty  Int_Loc;  
+  Enumeration   Enum_Loc;
+
+  Int_Loc = *Int_Par_Ref + 10;
+  do /* executed once */
+    if (Ch_1_Glob == 'A')
+      /* then, executed */
+    {
+      Int_Loc -= 1;
+      *Int_Par_Ref = Int_Loc - Int_Glob;
+      Enum_Loc = Ident_1;
+    } /* if */
+  while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+
+Proc_3 (Ptr_Ref_Par)
+/******************/
+    /* executed once */
+    /* Ptr_Ref_Par becomes Ptr_Glob */
+
+Rec_Pointer *Ptr_Ref_Par;
+
+{
+  if (Ptr_Glob != Null)
+    /* then, executed */
+    *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+  Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+
+Proc_4 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Boolean Bool_Loc;
+
+  Bool_Loc = Ch_1_Glob == 'A';
+  Bool_Glob = Bool_Loc | Bool_Glob;
+  Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+
+Proc_5 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Ch_1_Glob = 'A';
+  Bool_Glob = false;
+} /* Proc_5 */
+
+
+        /* Procedure for the assignment of structures,          */
+        /* if the C compiler doesn't support this feature       */
+#ifdef  NOSTRUCTASSIGN
+memcpy (d, s, l)
+register char   *d;
+register char   *s;
+register int    l;
+{
+        while (l--) *d++ = *s++;
+}
+#endif
+
+
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry_2.c b/zpu/roadshow/roadshow/dhrystone/dhry_2.c
new file mode 100644
index 0000000..ed0e5b7
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry_2.c
@@ -0,0 +1,192 @@
+/*
+ ****************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *                                                                            
+ *  Version:    C, Version 2.1
+ *                                                                            
+ *  File:       dhry_2.c (part 3 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#include "dhry.h"
+
+#ifndef REG
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#endif
+
+extern  int     Int_Glob;
+extern  char    Ch_1_Glob;
+
+
+Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+/*********************************/
+    /* executed once */
+    /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+
+Enumeration  Enum_Val_Par;
+Enumeration *Enum_Ref_Par;
+{
+  *Enum_Ref_Par = Enum_Val_Par;
+  if (! Func_3 (Enum_Val_Par))
+    /* then, not executed */
+    *Enum_Ref_Par = Ident_4;
+  switch (Enum_Val_Par)
+  {
+    case Ident_1: 
+      *Enum_Ref_Par = Ident_1;
+      break;
+    case Ident_2: 
+      if (Int_Glob > 100)
+        /* then */
+      *Enum_Ref_Par = Ident_1;
+      else *Enum_Ref_Par = Ident_4;
+      break;
+    case Ident_3: /* executed */
+      *Enum_Ref_Par = Ident_2;
+      break;
+    case Ident_4: break;
+    case Ident_5: 
+      *Enum_Ref_Par = Ident_3;
+      break;
+  } /* switch */
+} /* Proc_6 */
+
+
+Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+/**********************************************/
+    /* executed three times                                      */ 
+    /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */
+    /*                  Int_Par_Ref becomes 7                    */
+    /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+    /*                  Int_Par_Ref becomes 17                   */
+    /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+    /*                  Int_Par_Ref becomes 18                   */
+One_Fifty       Int_1_Par_Val;
+One_Fifty       Int_2_Par_Val;
+One_Fifty      *Int_Par_Ref;
+{
+  One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 2;
+  *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+
+Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+    /* executed once      */
+    /* Int_Par_Val_1 == 3 */
+    /* Int_Par_Val_2 == 7 */
+Arr_1_Dim       Arr_1_Par_Ref;
+Arr_2_Dim       Arr_2_Par_Ref;
+int             Int_1_Par_Val;
+int             Int_2_Par_Val;
+{
+  REG One_Fifty Int_Index;
+  REG One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 5;
+  Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+  Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+  Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+  for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+    Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+  Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+  Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+  Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+/*************************************************/
+    /* executed three times                                         */
+    /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */
+    /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */
+    /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */
+
+Capital_Letter   Ch_1_Par_Val;
+Capital_Letter   Ch_2_Par_Val;
+{
+  Capital_Letter        Ch_1_Loc;
+  Capital_Letter        Ch_2_Loc;
+
+  Ch_1_Loc = Ch_1_Par_Val;
+  Ch_2_Loc = Ch_1_Loc;
+  if (Ch_2_Loc != Ch_2_Par_Val)
+    /* then, executed */
+    return (Ident_1);
+  else  /* not executed */
+  {
+    Ch_1_Glob = Ch_1_Loc;
+    return (Ident_2);
+   }
+} /* Func_1 */
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+    /* executed once */
+    /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+    /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30  Str_1_Par_Ref;
+Str_30  Str_2_Par_Ref;
+{
+  REG One_Thirty        Int_Loc;
+      Capital_Letter    Ch_Loc;
+
+  Int_Loc = 2;
+  while (Int_Loc <= 2) /* loop body executed once */
+    if (Func_1 (Str_1_Par_Ref[Int_Loc],
+                Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+      /* then, executed */
+    {
+      Ch_Loc = 'A';
+      Int_Loc += 1;
+    } /* if, while */
+  if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+    /* then, not executed */
+    Int_Loc = 7;
+  if (Ch_Loc == 'R')
+    /* then, not executed */
+    return (true);
+  else /* executed */
+  {
+    if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+      /* then, not executed */
+    {
+      Int_Loc += 7;
+      Int_Glob = Int_Loc;
+      return (true);
+    }
+    else /* executed */
+      return (false);
+  } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+    /* executed once        */
+    /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+  Enumeration Enum_Loc;
+
+  Enum_Loc = Enum_Par_Val;
+  if (Enum_Loc == Ident_3)
+    /* then, executed */
+    return (true);
+  else /* not executed */
+    return (false);
+} /* Func_3 */
+
diff --git a/zpu/roadshow/roadshow/dhrystone/dhry_c.dif b/zpu/roadshow/roadshow/dhrystone/dhry_c.dif
new file mode 100644
index 0000000..8bcaaea
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/dhry_c.dif
@@ -0,0 +1,141 @@
+7c7
+<  *  Version:    C, Version 2.1
+---
+>  *  Version:    C, Version 2.0
+9c9
+<  *  File:       dhry.h (part 1 of 3)
+---
+>  *  File:       dhry_global.h (part 1 of 3)
+11c11
+<  *  Date:       May 25, 1988
+---
+>  *  Date:       March 3, 1988
+30c30
+<  *              In addition, Berkeley UNIX system calls "times ()" or "time ()"
+---
+>  *              In addition, UNIX system calls "times ()" or "time ()"
+44c44
+<  *      Please send results to Rick Richardson and/or Reinhold Weicker.
+---
+>  *      Please send results to Reinhold Weicker and/or Rick Richardson.
+59c59
+<  *  History:    This version C/2.1 has been made for two reasons:
+---
+>  *  History:    This version C/2.0 has been made for two reasons:
+123,129d122
+<  *              Version 2.1 is identical to version 2.0 distributed via
+<  *              the UNIX network Usenet in March 1988 except that it corrects
+<  *              some minor deficiencies that were found by users of version 2.0.
+<  *              The only change within the measurement loop is that a
+<  *              non-executed "else" part was added to the "if" statement in
+<  *              Func_3, and a non-executed "else" part removed from Proc_3.
+<  *
+165,167c158,160
+<  *              -DHZ=nnn
+<  *                      In Berkeley UNIX, the function "times" returns process
+<  *                      time in 1/HZ seconds, with HZ = 60 for most systems.
+---
+>  *              -DHZ=nnn                (default: 60)
+>  *                      The function "times" returns process times in
+>  *                      1/HZ seconds, with HZ = 60 for most systems.
+169c162
+<  *                      A VALUE.
+---
+>  *                      THE DEFAULT VALUE.
+176,178c169,171
+<  *  - dhry.h (this file, containing global definitions and comments)
+<  *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+<  *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+---
+>  *  - dhry_global.h (this file, containing global definitions and comments)
+>  *  - dhry_pack_1.c (containing the code corresponding to Ada package Pack_1)
+>  *  - dhry_pack_2.c (containing the code corresponding to Ada package Pack_2)
+350a344
+> #ifndef TIMES
+353,354c347,354
+<                 /* Use times(2) time function unless    */
+<                 /* explicitly defined otherwise         */
+---
+> #endif
+>                 /* Use "times" function for measurement */
+>                 /* unless explicitly defined otherwise  */
+> #ifndef HZ
+> #define HZ      60
+> #endif
+>                 /* Use HZ = 60 for "times" function     */
+>                 /* unless explicitly defined otherwise  */
+363c363
+<                 /* Berkeley UNIX C returns process times in seconds/HZ */
+---
+>                 /* UNIX C returns process times in seconds/HZ */
+7c7
+<  *  Version:    C, Version 2.1
+---
+>  *  Version:    C, Version 2.0
+9c9
+<  *  File:       dhry_1.c (part 2 of 3)
+---
+>  *  File:       dhry_pack_1.c (part 2 of 3)
+11c11
+<  *  Date:       May 25, 1988
+---
+>  *  Date:       March 3, 1988
+18c18
+< #include "dhry.h"
+---
+> #include "dhry_global.h"
+50,51d49
+< #define Too_Small_Time 120
+<                 /* Measurements should last at least about 2 seconds */
+55a54,55
+> #endif
+> 
+58d57
+< #endif
+73a73
+> 
+84a85
+> 
+99,100c100,102
+<         /* Was missing in published program. Without this statement,    */
+<         /* Arr_2_Glob [8][7] would have an undefined value.             */
+---
+>         /* Was missing in published program. Without this               */
+>         /* initialization, Arr_2_Glob [8][7] would have an              */
+>         /* undefined value.                                             */
+105c107
+<   printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+---
+>   printf ("Dhrystone Benchmark, Version 2.0 (Language: C)\n");
+281c283
+< /******************/
+---
+> /**********************/
+338c340
+< /******************/
+---
+> /**********************/
+347a350,351
+>   else /* not executed */
+>     Int_Glob = 100;
+349a354
+> 
+7c7
+<  *  Version:    C, Version 2.1
+---
+>  *  Version:    C, Version 2.0
+9c9
+<  *  File:       dhry_2.c (part 3 of 3)
+---
+>  *  File:       dhry_pack_2.c (part 3 of 3)
+11c11
+<  *  Date:       May 25, 1988
+---
+>  *  Date:       March 3, 1988
+18c18
+< #include "dhry.h"
+---
+> #include "dhry_global.h"
+189,190d188
+<   else /* not executed */
+<     return (false);
diff --git a/zpu/roadshow/roadshow/dhrystone/dhrystone.bin b/zpu/roadshow/roadshow/dhrystone/dhrystone.bin
new file mode 100644
index 0000000..ee1a6fe
Binary files /dev/null and b/zpu/roadshow/roadshow/dhrystone/dhrystone.bin differ
diff --git a/zpu/roadshow/roadshow/dhrystone/dhrystone.zpu b/zpu/roadshow/roadshow/dhrystone/dhrystone.zpu
new file mode 100644
index 0000000..e37e59f
Binary files /dev/null and b/zpu/roadshow/roadshow/dhrystone/dhrystone.zpu differ
diff --git a/zpu/roadshow/roadshow/dhrystone/submit.frm b/zpu/roadshow/roadshow/dhrystone/submit.frm
new file mode 100644
index 0000000..a75a689
--- /dev/null
+++ b/zpu/roadshow/roadshow/dhrystone/submit.frm
@@ -0,0 +1,17 @@
+DHRYSTONE 2.1 BENCHMARK REPORTING FORM
+MANUF:
+MODEL:
+PROC:
+CLOCK:
+OS:
+OVERSION:
+COMPILER:
+CVERSION:
+OPTIONS:
+NOREG:
+REG:
+NOTES:
+DATE:
+SUBMITTER:
+CODESIZE:
+MAILTO: uunet!pcrat!dry2
diff --git a/zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm b/zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm
new file mode 100644
index 0000000..3631145
--- /dev/null
+++ b/zpu/roadshow/roadshow/ecos/codesize/zpuarmcodesize.htm
@@ -0,0 +1,1049 @@
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+xmlns:x="urn:schemas-microsoft-com:office:excel"
+xmlns="http://www.w3.org/TR/REC-html40">
+
+<head>
+<meta http-equiv=Content-Type content="text/html; charset=windows-1252">
+<meta name=ProgId content=Excel.Sheet>
+<meta name=Generator content="Microsoft Excel 9">
+<link rel=File-List href="./zpuarmcodesize2_files/filelist.xml">
+<style id="test_15598_Styles">
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+	mso-generic-font-family:auto;
+	mso-font-charset:0;
+	mso-number-format:General;
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+-->
+</style>
+<title>ZPU vs. ARM non-thumb eCos codesize</title>
+</head>
+
+<body>
+<!--[if !excel]>&nbsp;&nbsp;<![endif]-->
+<!--The following information was generated by Microsoft Excel's Publish as Web
+Page wizard.-->
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+<!----------------------------->
+<!--START OF OUTPUT FROM EXCEL PUBLISH AS WEB PAGE WIZARD -->
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+
+<div id="test_15598" align=center x:publishsource="Excel">
+
+<h1 style='color:black;font-family:Arial;font-size:14.0pt;font-weight:800;
+font-style:normal'>ZPU vs. ARM non-thumb eCos codesize</h1>
+
+<table x:str border=0 cellpadding=0 cellspacing=0 width=883 style='border-collapse:
+ collapse;table-layout:fixed;width:663pt'>
+ <col width=64 span=5 style='width:48pt'>
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+ <col width=64 span=6 style='width:48pt'>
+ <col width=117 style='mso-width-source:userset;mso-width-alt:4278;width:88pt'>
+ <tr height=17 style='height:12.75pt'>
+  <td colspan=6 height=17 class=xl2215598 width=382 style='height:12.75pt;
+  width:287pt'>ZPU</td>
+  <td colspan=6 class=xl2215598 width=384 style='width:288pt'>ARM
+  non-thumb(eCos Thumb does not compile out of the box)</td>
+  <td class=xl1515598 width=117 style='width:88pt'></td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>filename</td>
+  <td class=xl1515598>text</td>
+  <td class=xl1515598>data</td>
+  <td class=xl1515598>bss</td>
+  <td class=xl1515598>dec</td>
+  <td class=xl1515598>hex</td>
+  <td class=xl1515598>filename</td>
+  <td class=xl1515598>text</td>
+  <td class=xl1515598>data</td>
+  <td class=xl1515598>bss</td>
+  <td class=xl1515598>dec</td>
+  <td class=xl1515598>hex</td>
+  <td class=xl1515598>ZPU text/ZPU ARM</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>bin_sem0</td>
+  <td class=xl2415598 x:num>15761</td>
+  <td class=xl2415598 x:num>1504</td>
+  <td class=xl2415598 x:num>12060</td>
+  <td class=xl2415598 x:num>29325</td>
+  <td class=xl2515598>728d</td>
+  <td class=xl2415598>bin_sem0</td>
+  <td class=xl2415598 x:num>25204</td>
+  <td class=xl2415598 x:num>692</td>
+  <td class=xl2415598 x:num>16976</td>
+  <td class=xl2415598 x:num>42872</td>
+  <td class=xl2415598>a778</td>
+  <td class=xl2315598 align=right x:num="0.6253372480558641" x:fmla="=B3/H3">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>bin_sem1</td>
+  <td class=xl2415598 x:num>16907</td>
+  <td class=xl2415598 x:num>1512</td>
+  <td class=xl2415598 x:num>14436</td>
+  <td class=xl2415598 x:num>32855</td>
+  <td class=xl2515598 x:num>8057</td>
+  <td class=xl2415598>bin_sem1</td>
+  <td class=xl2415598 x:num>26644</td>
+  <td class=xl2415598 x:num>700</td>
+  <td class=xl2415598 x:num>22096</td>
+  <td class=xl2415598 x:num>49440</td>
+  <td class=xl2415598>c120</td>
+  <td class=xl2315598 align=right x:num="0.63455186908872541" x:fmla="=B4/H4">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>bin_sem2</td>
+  <td class=xl2415598 x:num>17105</td>
+  <td class=xl2415598 x:num>1524</td>
+  <td class=xl2415598 x:num>30032</td>
+  <td class=xl2415598 x:num>48661</td>
+  <td class=xl2515598>be15</td>
+  <td class=xl2415598>bin_sem2</td>
+  <td class=xl2415598 x:num>26996</td>
+  <td class=xl2415598 x:num>712</td>
+  <td class=xl2415598 x:num>55584</td>
+  <td class=xl2415598 x:num>83292</td>
+  <td class=xl2415598>1455c</td>
+  <td class=xl2315598 align=right x:num="0.63361238702029932" x:fmla="=B5/H5">63
+  %</td>
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+  <td height=17 class=xl1515598 style='height:12.75pt'>bin_sem3</td>
+  <td class=xl2415598 x:num>17186</td>
+  <td class=xl2415598 x:num>1512</td>
+  <td class=xl2415598 x:num>14436</td>
+  <td class=xl2415598 x:num>33134</td>
+  <td class=xl2515598>816e</td>
+  <td class=xl2415598>bin_sem3</td>
+  <td class=xl2415598 x:num>27008</td>
+  <td class=xl2415598 x:num>700</td>
+  <td class=xl2415598 x:num>22100</td>
+  <td class=xl2415598 x:num>49808</td>
+  <td class=xl2415598>c290</td>
+  <td class=xl2315598 align=right x:num="0.63632997630331756" x:fmla="=B6/H6">64
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>clock0</td>
+  <td class=xl2415598 x:num>18986</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>12036</td>
+  <td class=xl2415598 x:num>32522</td>
+  <td class=xl2515598>7f0a</td>
+  <td class=xl2415598>clock0</td>
+  <td class=xl2415598 x:num>28992</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>16944</td>
+  <td class=xl2415598 x:num>46624</td>
+  <td class=xl2415598>b620</td>
+  <td class=xl2315598 align=right x:num="0.65487030905077259" x:fmla="=B7/H7">65
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+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>clock1</td>
+  <td class=xl2415598 x:num>15812</td>
+  <td class=xl2415598 x:num>1504</td>
+  <td class=xl2415598 x:num>13236</td>
+  <td class=xl2415598 x:num>30552</td>
+  <td class=xl2515598 x:num>7758</td>
+  <td class=xl2415598>clock1</td>
+  <td class=xl2415598 x:num>25456</td>
+  <td class=xl2415598 x:num>692</td>
+  <td class=xl2415598 x:num>19532</td>
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+  <td class=xl2415598>b270</td>
+  <td class=xl2315598 align=right x:num="0.62115021998742925" x:fmla="=B8/H8">62
+  %</td>
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+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>clockcnv</td>
+  <td class=xl2415598 x:num>25095</td>
+  <td class=xl2415598 x:num>1972</td>
+  <td class=xl2415598 x:num>13224</td>
+  <td class=xl2415598 x:num>40291</td>
+  <td class=xl2515598>9d63</td>
+  <td class=xl2415598>clockcnv</td>
+  <td class=xl2415598 x:num>34572</td>
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+  <td class=xl2315598 align=right x:num="0.72587643179451578" x:fmla="=B9/H9">73
+  %</td>
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+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>clocktruth</td>
+  <td class=xl2415598 x:num>16437</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>13224</td>
+  <td class=xl2415598 x:num>31161</td>
+  <td class=xl2515598>79b9</td>
+  <td class=xl2415598>clocktruth</td>
+  <td class=xl2415598 x:num>26224</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>19508</td>
+  <td class=xl2415598 x:num>46420</td>
+  <td class=xl2415598>b554</td>
+  <td class=xl2315598 align=right x:num="0.62679225137278827" x:fmla="=B10/H10">63
+  %</td>
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+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>cnt_sem0</td>
+  <td class=xl2415598 x:num>15762</td>
+  <td class=xl2415598 x:num>1504</td>
+  <td class=xl2415598 x:num>12060</td>
+  <td class=xl2415598 x:num>29326</td>
+  <td class=xl2515598>728e</td>
+  <td class=xl2415598>cnt_sem0</td>
+  <td class=xl2415598 x:num>25204</td>
+  <td class=xl2415598 x:num>692</td>
+  <td class=xl2415598 x:num>16976</td>
+  <td class=xl2415598 x:num>42872</td>
+  <td class=xl2415598>a778</td>
+  <td class=xl2315598 align=right x:num="0.62537692429773051" x:fmla="=B11/H11">63
+  %</td>
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+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>cnt_sem1</td>
+  <td class=xl2415598 x:num>17124</td>
+  <td class=xl2415598 x:num>1512</td>
+  <td class=xl2415598 x:num>14436</td>
+  <td class=xl2415598 x:num>33072</td>
+  <td class=xl2515598 x:num>8130</td>
+  <td class=xl2415598>cnt_sem1</td>
+  <td class=xl2415598 x:num>26888</td>
+  <td class=xl2415598 x:num>700</td>
+  <td class=xl2415598 x:num>22108</td>
+  <td class=xl2415598 x:num>49696</td>
+  <td class=xl2415598>c220</td>
+  <td class=xl2315598 align=right x:num="0.63686402856292768" x:fmla="=B12/H12">64
+  %</td>
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+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>dhrystone</td>
+  <td class=xl2415598 x:num>35947</td>
+  <td class=xl2415598 x:num>1564</td>
+  <td class=xl2415598 x:num>22512</td>
+  <td class=xl2415598 x:num>60023</td>
+  <td class=xl2515598>ea77</td>
+  <td class=xl2415598>dhrystone</td>
+  <td class=xl2415598 x:num>44180</td>
+  <td class=xl2415598 x:num>752</td>
+  <td class=xl2415598 x:num>27416</td>
+  <td class=xl2415598 x:num>72348</td>
+  <td class=xl2415598>11a9c</td>
+  <td class=xl2315598 align=right x:num="0.8136487098234495" x:fmla="=B13/H13">81
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>except1</td>
+  <td class=xl2415598 x:num>16428</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>13228</td>
+  <td class=xl2415598 x:num>31156</td>
+  <td class=xl2515598>79b4</td>
+  <td class=xl2415598>except1</td>
+  <td class=xl2415598 x:num>26088</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>19520</td>
+  <td class=xl2415598 x:num>46296</td>
+  <td class=xl2415598>b4d8</td>
+  <td class=xl2315598 align=right x:num="0.62971481140754371" x:fmla="=B14/H14">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>flag0</td>
+  <td class=xl2415598 x:num>15751</td>
+  <td class=xl2415598 x:num>1504</td>
+  <td class=xl2415598 x:num>12052</td>
+  <td class=xl2415598 x:num>29307</td>
+  <td class=xl2515598>727b</td>
+  <td class=xl2415598>flag0</td>
+  <td class=xl2415598 x:num>25236</td>
+  <td class=xl2415598 x:num>692</td>
+  <td class=xl2415598 x:num>16968</td>
+  <td class=xl2415598 x:num>42896</td>
+  <td class=xl2415598>a790</td>
+  <td class=xl2315598 align=right x:num="0.62414804247899824" x:fmla="=B15/H15">62
+  %</td>
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+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>flag1</td>
+  <td class=xl2415598 x:num>19145</td>
+  <td class=xl2415598 x:num>1512</td>
+  <td class=xl2415598 x:num>15624</td>
+  <td class=xl2415598 x:num>36281</td>
+  <td class=xl2515598>8db9</td>
+  <td class=xl2415598>flag1</td>
+  <td class=xl2415598 x:num>29532</td>
+  <td class=xl2415598 x:num>700</td>
+  <td class=xl2415598 x:num>24668</td>
+  <td class=xl2415598 x:num>54900</td>
+  <td class=xl2415598>d674</td>
+  <td class=xl2315598 align=right x:num="0.64827983204659356" x:fmla="=B16/H16">65
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>fptest</td>
+  <td class=xl2415598 x:num>20053</td>
+  <td class=xl2415598 x:num>1516</td>
+  <td class=xl2415598 x:num>102908</td>
+  <td class=xl2415598 x:num>124477</td>
+  <td class=xl2515598>1e63d</td>
+  <td class=xl2415598>fptest</td>
+  <td class=xl2415598 x:num>29508</td>
+  <td class=xl2415598 x:num>704</td>
+  <td class=xl2415598 x:num>109652</td>
+  <td class=xl2415598 x:num>139864</td>
+  <td class=xl2415598 x:num>22258</td>
+  <td class=xl2315598 align=right x:num="0.67957841941168495" x:fmla="=B17/H17">68
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>intr0</td>
+  <td class=xl2415598 x:num>15998</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>12092</td>
+  <td class=xl2415598 x:num>29586</td>
+  <td class=xl2515598 x:num>7392</td>
+  <td class=xl2415598>intr0</td>
+  <td class=xl2415598 x:num>25932</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>17016</td>
+  <td class=xl2415598 x:num>43632</td>
+  <td class=xl2415598>aa70</td>
+  <td class=xl2315598 align=right x:num="0.6169211784667592" x:fmla="=B18/H18">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kalarm0</td>
+  <td class=xl2415598 x:num>16080</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>12200</td>
+  <td class=xl2415598 x:num>29776</td>
+  <td class=xl2515598 x:num>7450</td>
+  <td class=xl2415598>kalarm0</td>
+  <td class=xl2415598 x:num>25824</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>17112</td>
+  <td class=xl2415598 x:num>43620</td>
+  <td class=xl2415598>aa64</td>
+  <td class=xl2315598 align=right x:num="0.62267657992565051" x:fmla="=B19/H19">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kcache1</td>
+  <td class=xl2415598 x:num>15327</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>12036</td>
+  <td class=xl2415598 x:num>28859</td>
+  <td class=xl2515598>70bb</td>
+  <td class=xl2415598>kcache1</td>
+  <td class=xl2415598 x:num>24728</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>16956</td>
+  <td class=xl2415598 x:num>42368</td>
+  <td class=xl2415598>a580</td>
+  <td class=xl2315598 align=right x:num="0.61982368165642188" x:fmla="=B20/H20">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kcache2</td>
+  <td class=xl2415598 x:num>15549</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>13224</td>
+  <td class=xl2415598 x:num>30269</td>
+  <td class=xl2515598>763d</td>
+  <td class=xl2415598>kcache2</td>
+  <td class=xl2415598 x:num>25168</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>19512</td>
+  <td class=xl2415598 x:num>45364</td>
+  <td class=xl2415598>b134</td>
+  <td class=xl2315598 align=right x:num="0.61780832803560082" x:fmla="=B21/H21">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kclock0</td>
+  <td class=xl2415598 x:num>18291</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>12260</td>
+  <td class=xl2415598 x:num>32051</td>
+  <td class=xl2515598>7d33</td>
+  <td class=xl2415598>kclock0</td>
+  <td class=xl2415598 x:num>28112</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>17168</td>
+  <td class=xl2415598 x:num>45968</td>
+  <td class=xl2415598>b390</td>
+  <td class=xl2315598 align=right x:num="0.65064741035856577" x:fmla="=B22/H22">65
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kclock1</td>
+  <td class=xl2415598 x:num>16231</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>13232</td>
+  <td class=xl2415598 x:num>30963</td>
+  <td class=xl2515598>78f3</td>
+  <td class=xl2415598>kclock1</td>
+  <td class=xl2415598 x:num>25976</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>19524</td>
+  <td class=xl2415598 x:num>46188</td>
+  <td class=xl2415598>b46c</td>
+  <td class=xl2315598 align=right x:num="0.6248460117031106" x:fmla="=B23/H23">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kexcept1</td>
+  <td class=xl2415598 x:num>16572</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>13228</td>
+  <td class=xl2415598 x:num>31296</td>
+  <td class=xl2515598>7a40</td>
+  <td class=xl2415598>kexcept1</td>
+  <td class=xl2415598 x:num>26372</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>19512</td>
+  <td class=xl2415598 x:num>46568</td>
+  <td class=xl2415598>b5e8</td>
+  <td class=xl2315598 align=right x:num="0.62839375094797512" x:fmla="=B24/H24">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kflag0</td>
+  <td class=xl2415598 x:num>15618</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>12060</td>
+  <td class=xl2415598 x:num>29174</td>
+  <td class=xl2515598>71f6</td>
+  <td class=xl2415598>kflag0</td>
+  <td class=xl2415598 x:num>25140</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>16968</td>
+  <td class=xl2415598 x:num>42792</td>
+  <td class=xl2415598>a728</td>
+  <td class=xl2315598 align=right x:num="0.62124105011933173" x:fmla="=B25/H25">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kflag1</td>
+  <td class=xl2415598 x:num>19287</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>15624</td>
+  <td class=xl2415598 x:num>36411</td>
+  <td class=xl2515598>8e3b</td>
+  <td class=xl2415598>kflag1</td>
+  <td class=xl2415598 x:num>29824</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>24660</td>
+  <td class=xl2415598 x:num>55172</td>
+  <td class=xl2415598>d784</td>
+  <td class=xl2315598 align=right x:num="0.64669393776824036" x:fmla="=B26/H26">65
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kill</td>
+  <td class=xl2415598 x:num>16887</td>
+  <td class=xl2415598 x:num>1516</td>
+  <td class=xl2415598 x:num>15628</td>
+  <td class=xl2415598 x:num>34031</td>
+  <td class=xl2515598>84ef</td>
+  <td class=xl2415598>kill</td>
+  <td class=xl2415598 x:num>26896</td>
+  <td class=xl2415598 x:num>704</td>
+  <td class=xl2415598 x:num>24656</td>
+  <td class=xl2415598 x:num>52256</td>
+  <td class=xl2415598>cc20</td>
+  <td class=xl2315598 align=right x:num="0.62786287923854844" x:fmla="=B27/H27">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kintr0</td>
+  <td class=xl2415598 x:num>16186</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>12128</td>
+  <td class=xl2415598 x:num>29810</td>
+  <td class=xl2515598 x:num>7472</td>
+  <td class=xl2415598>kintr0</td>
+  <td class=xl2415598 x:num>26088</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>17028</td>
+  <td class=xl2415598 x:num>43800</td>
+  <td class=xl2415598>ab18</td>
+  <td class=xl2315598 align=right x:num="0.62043851579270159" x:fmla="=B28/H28">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>klock</td>
+  <td class=xl2415598 x:num>19724</td>
+  <td class=xl2415598 x:num>1504</td>
+  <td class=xl2415598 x:num>14516</td>
+  <td class=xl2415598 x:num>35744</td>
+  <td class=xl2515598>8ba0</td>
+  <td class=xl2415598>klock</td>
+  <td class=xl2415598 x:num>30812</td>
+  <td class=xl2415598 x:num>692</td>
+  <td class=xl2415598 x:num>22176</td>
+  <td class=xl2415598 x:num>53680</td>
+  <td class=xl2415598>d1b0</td>
+  <td class=xl2315598 align=right x:num="0.64014020511489034" x:fmla="=B29/H29">64
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kmbox1</td>
+  <td class=xl2415598 x:num>18283</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>14592</td>
+  <td class=xl2415598 x:num>34375</td>
+  <td class=xl2515598 x:num>8647</td>
+  <td class=xl2415598>kmbox1</td>
+  <td class=xl2415598 x:num>28504</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>22260</td>
+  <td class=xl2415598 x:num>51452</td>
+  <td class=xl2415598>c8fc</td>
+  <td class=xl2315598 align=right x:num="0.6414187482458602" x:fmla="=B30/H30">64
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kmutex0</td>
+  <td class=xl2415598 x:num>15539</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>12064</td>
+  <td class=xl2415598 x:num>29099</td>
+  <td class=xl2515598>71ab</td>
+  <td class=xl2415598>kmutex0</td>
+  <td class=xl2415598 x:num>24984</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>16984</td>
+  <td class=xl2415598 x:num>42652</td>
+  <td class=xl2415598>a69c</td>
+  <td class=xl2315598 align=right x:num="0.62195805315401853" x:fmla="=B31/H31">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kmutex1</td>
+  <td class=xl2415598 x:num>16524</td>
+  <td class=xl2415598 x:num>1504</td>
+  <td class=xl2415598 x:num>15664</td>
+  <td class=xl2415598 x:num>33692</td>
+  <td class=xl2515598>839c</td>
+  <td class=xl2415598>kmutex1</td>
+  <td class=xl2415598 x:num>26504</td>
+  <td class=xl2415598 x:num>692</td>
+  <td class=xl2415598 x:num>24704</td>
+  <td class=xl2415598 x:num>51900</td>
+  <td class=xl2415598>cabc</td>
+  <td class=xl2315598 align=right x:num="0.62345306368849984" x:fmla="=B32/H32">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kmutex3</td>
+  <td class=xl2415598 x:num>18272</td>
+  <td class=xl2415598 x:num>1712</td>
+  <td class=xl2415598 x:num>20348</td>
+  <td class=xl2415598 x:num>40332</td>
+  <td class=xl2515598>9d8c</td>
+  <td class=xl2415598>kmutex3</td>
+  <td class=xl2415598 x:num>28792</td>
+  <td class=xl2415598 x:num>900</td>
+  <td class=xl2415598 x:num>34892</td>
+  <td class=xl2415598 x:num>64584</td>
+  <td class=xl2415598>fc48</td>
+  <td class=xl2315598 align=right x:num="0.63462072797999447" x:fmla="=B33/H33">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kmutex4</td>
+  <td class=xl2415598 x:num>18682</td>
+  <td class=xl2415598 x:num>1608</td>
+  <td class=xl2415598 x:num>20352</td>
+  <td class=xl2415598 x:num>40642</td>
+  <td class=xl2515598>9ec2</td>
+  <td class=xl2415598>kmutex4</td>
+  <td class=xl2415598 x:num>29264</td>
+  <td class=xl2415598 x:num>796</td>
+  <td class=xl2415598 x:num>34896</td>
+  <td class=xl2415598 x:num>64956</td>
+  <td class=xl2415598>fdbc</td>
+  <td class=xl2315598 align=right x:num="0.63839529797703665" x:fmla="=B34/H34">64
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>ksched1</td>
+  <td class=xl2415598 x:num>15619</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>14412</td>
+  <td class=xl2415598 x:num>31527</td>
+  <td class=xl2515598>7b27</td>
+  <td class=xl2415598>ksched1</td>
+  <td class=xl2415598 x:num>25240</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>22084</td>
+  <td class=xl2415598 x:num>48008</td>
+  <td class=xl2415598>bb88</td>
+  <td class=xl2315598 align=right x:num="0.61881933438985737" x:fmla="=B35/H35">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>ksem0</td>
+  <td class=xl2415598 x:num>15567</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>12060</td>
+  <td class=xl2415598 x:num>29123</td>
+  <td class=xl2515598>71c3</td>
+  <td class=xl2415598>ksem0</td>
+  <td class=xl2415598 x:num>25044</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>16968</td>
+  <td class=xl2415598 x:num>42696</td>
+  <td class=xl2415598>a6c8</td>
+  <td class=xl2315598 align=right x:num="0.62158600862482027" x:fmla="=B36/H36">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>ksem1</td>
+  <td class=xl2415598 x:num>17063</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>14436</td>
+  <td class=xl2415598 x:num>32999</td>
+  <td class=xl2515598 x:num="800000000">8E+08</td>
+  <td class=xl2415598>ksem1</td>
+  <td class=xl2415598 x:num>26988</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>22100</td>
+  <td class=xl2415598 x:num>49776</td>
+  <td class=xl2415598>c270</td>
+  <td class=xl2315598 align=right x:num="0.63224396027864238" x:fmla="=B37/H37">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kthread0</td>
+  <td class=xl2415598 x:num>15504</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>13228</td>
+  <td class=xl2415598 x:num>30228</td>
+  <td class=xl2515598 x:num>7614</td>
+  <td class=xl2415598>kthread0</td>
+  <td class=xl2415598 x:num>25028</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>19512</td>
+  <td class=xl2415598 x:num>45224</td>
+  <td class=xl2415598>b0a8</td>
+  <td class=xl2315598 align=right x:num="0.61946619785839863" x:fmla="=B38/H38">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>kthread1</td>
+  <td class=xl2415598 x:num>16167</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>14412</td>
+  <td class=xl2415598 x:num>32075</td>
+  <td class=xl2515598>7d4b</td>
+  <td class=xl2415598>kthread1</td>
+  <td class=xl2415598 x:num>25996</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>22080</td>
+  <td class=xl2415598 x:num>48760</td>
+  <td class=xl2415598>be78</td>
+  <td class=xl2315598 align=right x:num="0.62190336974919214" x:fmla="=B39/H39">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>mbox1</td>
+  <td class=xl2415598 x:num>18281</td>
+  <td class=xl2415598 x:num>1512</td>
+  <td class=xl2415598 x:num>14580</td>
+  <td class=xl2415598 x:num>34373</td>
+  <td class=xl2515598 x:num>8645</td>
+  <td class=xl2415598>mbox1</td>
+  <td class=xl2415598 x:num>28552</td>
+  <td class=xl2415598 x:num>700</td>
+  <td class=xl2415598 x:num>22252</td>
+  <td class=xl2415598 x:num>51504</td>
+  <td class=xl2415598>c930</td>
+  <td class=xl2315598 align=right x:num="0.64027038386102553" x:fmla="=B40/H40">64
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>mqueue1</td>
+  <td class=xl2415598 x:num>20611</td>
+  <td class=xl2415598 x:num>1508</td>
+  <td class=xl2415598 x:num>14940</td>
+  <td class=xl2415598 x:num>37059</td>
+  <td class=xl2515598>90c3</td>
+  <td class=xl2415598>mqueue1</td>
+  <td class=xl2415598 x:num>31324</td>
+  <td class=xl2415598 x:num>696</td>
+  <td class=xl2415598 x:num>22612</td>
+  <td class=xl2415598 x:num>54632</td>
+  <td class=xl2415598>d568</td>
+  <td class=xl2315598 align=right x:num="0.65799387051462133" x:fmla="=B41/H41">66
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>mutex0</td>
+  <td class=xl2415598 x:num>15672</td>
+  <td class=xl2415598 x:num>1504</td>
+  <td class=xl2415598 x:num>12064</td>
+  <td class=xl2415598 x:num>29240</td>
+  <td class=xl2515598 x:num>7238</td>
+  <td class=xl2415598>mutex0</td>
+  <td class=xl2415598 x:num>25108</td>
+  <td class=xl2415598 x:num>692</td>
+  <td class=xl2415598 x:num>16980</td>
+  <td class=xl2415598 x:num>42780</td>
+  <td class=xl2415598>a71c</td>
+  <td class=xl2315598 align=right x:num="0.62418352716265735" x:fmla="=B42/H42">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>mutex1</td>
+  <td class=xl2415598 x:num>16678</td>
+  <td class=xl2415598 x:num>1516</td>
+  <td class=xl2415598 x:num>15664</td>
+  <td class=xl2415598 x:num>33858</td>
+  <td class=xl2515598 x:num>8442</td>
+  <td class=xl2415598>mutex1</td>
+  <td class=xl2415598 x:num>26464</td>
+  <td class=xl2415598 x:num>704</td>
+  <td class=xl2415598 x:num>24700</td>
+  <td class=xl2415598 x:num>51868</td>
+  <td class=xl2415598>ca9c</td>
+  <td class=xl2315598 align=right x:num="0.63021463119709797" x:fmla="=B43/H43">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>mutex2</td>
+  <td class=xl2415598 x:num>17694</td>
+  <td class=xl2415598 x:num>1508</td>
+  <td class=xl2415598 x:num>16868</td>
+  <td class=xl2415598 x:num>36070</td>
+  <td class=xl2515598>8ce6</td>
+  <td class=xl2415598>mutex2</td>
+  <td class=xl2415598 x:num>27624</td>
+  <td class=xl2415598 x:num>696</td>
+  <td class=xl2415598 x:num>27280</td>
+  <td class=xl2415598 x:num>55600</td>
+  <td class=xl2415598>d930</td>
+  <td class=xl2315598 align=right x:num="0.6405299739357081" x:fmla="=B44/H44">64
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>mutex3</td>
+  <td class=xl2415598 x:num>18203</td>
+  <td class=xl2415598 x:num>1720</td>
+  <td class=xl2415598 x:num>20344</td>
+  <td class=xl2415598 x:num>40267</td>
+  <td class=xl2515598>9d4b</td>
+  <td class=xl2415598>mutex3</td>
+  <td class=xl2415598 x:num>28596</td>
+  <td class=xl2415598 x:num>908</td>
+  <td class=xl2415598 x:num>34884</td>
+  <td class=xl2415598 x:num>64388</td>
+  <td class=xl2415598>fb84</td>
+  <td class=xl2315598 align=right x:num="0.63655756049797174" x:fmla="=B45/H45">64
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>release</td>
+  <td class=xl2415598 x:num>16352</td>
+  <td class=xl2415598 x:num>1508</td>
+  <td class=xl2415598 x:num>14428</td>
+  <td class=xl2415598 x:num>32288</td>
+  <td class=xl2515598 x:num="7E+20">7E+20</td>
+  <td class=xl2415598>release</td>
+  <td class=xl2415598 x:num>26156</td>
+  <td class=xl2415598 x:num>696</td>
+  <td class=xl2415598 x:num>22100</td>
+  <td class=xl2415598 x:num>48952</td>
+  <td class=xl2415598>bf38</td>
+  <td class=xl2315598 align=right x:num="0.62517204465514609" x:fmla="=B46/H46">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>sched1</td>
+  <td class=xl2415598 x:num>15890</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>14412</td>
+  <td class=xl2415598 x:num>31802</td>
+  <td class=xl2515598>7c3a</td>
+  <td class=xl2415598>sched1</td>
+  <td class=xl2415598 x:num>25460</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>22084</td>
+  <td class=xl2415598 x:num>48232</td>
+  <td class=xl2415598>bc68</td>
+  <td class=xl2315598 align=right x:num="0.62411626080125693" x:fmla="=B47/H47">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>stress_thr<span
+  style='display:none'>eads</span></td>
+  <td class=xl2415598 x:num>44196</td>
+  <td class=xl2415598 x:num>1612</td>
+  <td class=xl2415598 x:num>286332</td>
+  <td class=xl2415598 x:num>332140</td>
+  <td class=xl2515598>5116c</td>
+  <td class=xl2415598>stress_threads</td>
+  <td class=xl2415598 x:num>56356</td>
+  <td class=xl2415598 x:num>828</td>
+  <td class=xl2415598 x:num>45892</td>
+  <td class=xl2415598 x:num>103076</td>
+  <td class=xl2415598>192a4</td>
+  <td class=xl2315598 align=right x:num="0.78422883100291008" x:fmla="=B48/H48">78
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>sync2</td>
+  <td class=xl2415598 x:num>17891</td>
+  <td class=xl2415598 x:num>1524</td>
+  <td class=xl2415598 x:num>16864</td>
+  <td class=xl2415598 x:num>36279</td>
+  <td class=xl2515598>8db7</td>
+  <td class=xl2415598>sync2</td>
+  <td class=xl2415598 x:num>27900</td>
+  <td class=xl2415598 x:num>712</td>
+  <td class=xl2415598 x:num>27288</td>
+  <td class=xl2415598 x:num>55900</td>
+  <td class=xl2415598>da5c</td>
+  <td class=xl2315598 align=right x:num="0.64125448028673837" x:fmla="=B49/H49">64
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>sync3</td>
+  <td class=xl2415598 x:num>16943</td>
+  <td class=xl2415598 x:num>1512</td>
+  <td class=xl2415598 x:num>15644</td>
+  <td class=xl2415598 x:num>34099</td>
+  <td class=xl2515598 x:num>8533</td>
+  <td class=xl2415598>sync3</td>
+  <td class=xl2415598 x:num>26760</td>
+  <td class=xl2415598 x:num>700</td>
+  <td class=xl2415598 x:num>24692</td>
+  <td class=xl2415598 x:num>52152</td>
+  <td class=xl2415598>cbb8</td>
+  <td class=xl2315598 align=right x:num="0.63314648729446932" x:fmla="=B50/H50">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>thread0</td>
+  <td class=xl2415598 x:num>15467</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>13064</td>
+  <td class=xl2415598 x:num>30027</td>
+  <td class=xl2515598>754b</td>
+  <td class=xl2415598>thread0</td>
+  <td class=xl2415598 x:num>24924</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>19356</td>
+  <td class=xl2415598 x:num>44964</td>
+  <td class=xl2415598>afa4</td>
+  <td class=xl2315598 align=right x:num="0.6205665222275718" x:fmla="=B51/H51">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>thread1</td>
+  <td class=xl2415598 x:num>16134</td>
+  <td class=xl2415598 x:num>1496</td>
+  <td class=xl2415598 x:num>14420</td>
+  <td class=xl2415598 x:num>32050</td>
+  <td class=xl2515598>7d32</td>
+  <td class=xl2415598>thread1</td>
+  <td class=xl2415598 x:num>25868</td>
+  <td class=xl2415598 x:num>684</td>
+  <td class=xl2415598 x:num>22084</td>
+  <td class=xl2415598 x:num>48636</td>
+  <td class=xl2415598>bdfc</td>
+  <td class=xl2315598 align=right x:num="0.62370496366166694" x:fmla="=B52/H52">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>thread2</td>
+  <td class=xl2415598 x:num>17560</td>
+  <td class=xl2415598 x:num>1512</td>
+  <td class=xl2415598 x:num>15636</td>
+  <td class=xl2415598 x:num>34708</td>
+  <td class=xl2515598 x:num>8794</td>
+  <td class=xl2415598>thread2</td>
+  <td class=xl2415598 x:num>27452</td>
+  <td class=xl2415598 x:num>700</td>
+  <td class=xl2415598 x:num>24680</td>
+  <td class=xl2415598 x:num>52832</td>
+  <td class=xl2415598>ce60</td>
+  <td class=xl2315598 align=right x:num="0.63966195541308468" x:fmla="=B53/H53">64
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>thread_gdb</td>
+  <td class=xl2415598 x:num>16279</td>
+  <td class=xl2415598 x:num>1500</td>
+  <td class=xl2415598 x:num>24028</td>
+  <td class=xl2415598 x:num>41807</td>
+  <td class=xl2515598>a34f</td>
+  <td class=xl2415598>thread_gdb</td>
+  <td class=xl2415598 x:num>26136</td>
+  <td class=xl2415598 x:num>688</td>
+  <td class=xl2415598 x:num>42704</td>
+  <td class=xl2415598 x:num>69528</td>
+  <td class=xl2415598>10f98</td>
+  <td class=xl2315598 align=right x:num="0.62285736149372517" x:fmla="=B54/H54">62
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>timeslice</td>
+  <td class=xl2415598 x:num>17051</td>
+  <td class=xl2415598 x:num>1504</td>
+  <td class=xl2415598 x:num>20376</td>
+  <td class=xl2415598 x:num>38931</td>
+  <td class=xl2515598 x:num>9813</td>
+  <td class=xl2415598>timeslice</td>
+  <td class=xl2415598 x:num>27212</td>
+  <td class=xl2415598 x:num>692</td>
+  <td class=xl2415598 x:num>34916</td>
+  <td class=xl2415598 x:num>62820</td>
+  <td class=xl2415598>f564</td>
+  <td class=xl2315598 align=right x:num="0.62659855945906218" x:fmla="=B55/H55">63
+  %</td>
+ </tr>
+ <tr height=17 style='height:12.75pt'>
+  <td height=17 class=xl1515598 style='height:12.75pt'>tm_basic</td>
+  <td class=xl2415598 x:num>37313</td>
+  <td class=xl2415598 x:num>1512</td>
+  <td class=xl2415598 x:num>422380</td>
+  <td class=xl2415598 x:num>461205</td>
+  <td class=xl2515598 x:num>70995</td>
+  <td class=xl2415598>tm_basic</td>
+  <td class=xl2415598 x:num>52728</td>
+  <td class=xl2415598 x:num>700</td>
+  <td class=xl2415598 x:num>123332</td>
+  <td class=xl2415598 x:num>176760</td>
+  <td class=xl2415598>2b278</td>
+  <td class=xl2315598 align=right x:num="0.70765058412987403" x:fmla="=B56/H56">71
+  %</td>
+ </tr>
+ <![if supportMisalignedColumns]>
+ <tr height=0 style='display:none'>
+  <td width=64 style='width:48pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=62 style='width:47pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=64 style='width:48pt'></td>
+  <td width=117 style='width:88pt'></td>
+ </tr>
+ <![endif]>
+</table>
+
+</div>
+
+
+<!----------------------------->
+<!--END OF OUTPUT FROM EXCEL PUBLISH AS WEB PAGE WIZARD-->
+<!----------------------------->
+</body>
+
+</html>
diff --git a/zpu/roadshow/roadshow/ecos/index.html b/zpu/roadshow/roadshow/ecos/index.html
new file mode 100644
index 0000000..5245459
--- /dev/null
+++ b/zpu/roadshow/roadshow/ecos/index.html
@@ -0,0 +1,145 @@
+<html>
+<body>
+<h1>Installing eCos build tools</h1>
+<code>
+tar -xjvf ecossnapshot.tar.bz2<br>
+tar -xjvf repository.tar.bz2<br>
+tar -xjvf ecostools.tar.bz2<br>
+# run this every time you open the shell<br>
+export PATH=$PATH:`pwd`/ecos-install<br>
+export ECOS_REPOSITORY=`pwd`/ecos/packages:`pwd`/repository<br>
+</code>
+<h1>Compiling eCos tests</h1>
+<code>
+ecosconfig new zeta default<br>
+ecosconfig tree<br>
+make<br>
+cd kernel/current<br>
+make tests<br>
+</code>
+
+<h1>Code size ZPU</h1>
+<code>
+$ zpu-elf-size *<br>
+   text    data     bss     dec     hex filename<br>
+  15761    1504   12060   29325    728d bin_sem0<br>
+  16907    1512   14436   32855    8057 bin_sem1<br>
+  17105    1524   30032   48661    be15 bin_sem2<br>
+  17186    1512   14436   33134    816e bin_sem3<br>
+  18986    1500   12036   32522    7f0a clock0<br>
+  15812    1504   13236   30552    7758 clock1<br>
+  25095    1972   13224   40291    9d63 clockcnv<br>
+  16437    1500   13224   31161    79b9 clocktruth<br>
+  15762    1504   12060   29326    728e cnt_sem0<br>
+  17124    1512   14436   33072    8130 cnt_sem1<br>
+  35947    1564   22512   60023    ea77 dhrystone<br>
+  16428    1500   13228   31156    79b4 except1<br>
+  15751    1504   12052   29307    727b flag0<br>
+  19145    1512   15624   36281    8db9 flag1<br>
+  20053    1516  102908  124477   1e63d fptest<br>
+  15998    1496   12092   29586    7392 intr0<br>
+  16080    1496   12200   29776    7450 kalarm0<br>
+  15327    1496   12036   28859    70bb kcache1<br>
+  15549    1496   13224   30269    763d kcache2<br>
+  18291    1500   12260   32051    7d33 kclock0<br>
+  16231    1500   13232   30963    78f3 kclock1<br>
+  16572    1496   13228   31296    7a40 kexcept1<br>
+  15618    1496   12060   29174    71f6 kflag0<br>
+  19287    1500   15624   36411    8e3b kflag1<br>
+  16887    1516   15628   34031    84ef kill<br>
+  16186    1496   12128   29810    7472 kintr0<br>
+  19724    1504   14516   35744    8ba0 klock<br>
+  18283    1500   14592   34375    8647 kmbox1<br>
+  15539    1496   12064   29099    71ab kmutex0<br>
+  16524    1504   15664   33692    839c kmutex1<br>
+  18272    1712   20348   40332    9d8c kmutex3<br>
+  18682    1608   20352   40642    9ec2 kmutex4<br>
+  15619    1496   14412   31527    7b27 ksched1<br>
+  15567    1496   12060   29123    71c3 ksem0<br>
+  17063    1500   14436   32999    80e7 ksem1<br>
+  15504    1496   13228   30228    7614 kthread0<br>
+  16167    1496   14412   32075    7d4b kthread1<br>
+  18281    1512   14580   34373    8645 mbox1<br>
+  20611    1508   14940   37059    90c3 mqueue1<br>
+  15672    1504   12064   29240    7238 mutex0<br>
+  16678    1516   15664   33858    8442 mutex1<br>
+  17694    1508   16868   36070    8ce6 mutex2<br>
+  18203    1720   20344   40267    9d4b mutex3<br>
+  16352    1508   14428   32288    7e20 release<br>
+  15890    1500   14412   31802    7c3a sched1<br>
+  44196    1612  286332  332140   5116c stress_threads<br>
+  17891    1524   16864   36279    8db7 sync2<br>
+  16943    1512   15644   34099    8533 sync3<br>
+  15467    1496   13064   30027    754b thread0<br>
+  16134    1496   14420   32050    7d32 thread1<br>
+  17560    1512   15636   34708    8794 thread2<br>
+  16279    1500   24028   41807    a34f thread_gdb<br>
+  17051    1504   20376   38931    9813 timeslice<br>
+  17146    1504   21564   40214    9d16 timeslice2<br>
+  37313    1512  422380  461205   70995 tm_basic<br>
+</code>
+<h2>Code size ARM (non-thumb)</h2>
+Thumb does not compile out of the box w/AT91 EB40a for which this test was made.<p>
+<code>
+$ arm-elf-size *<br>
+   text    data     bss     dec     hex filename<br>
+  25204     692   16976   42872    a778 bin_sem0<br>
+  26644     700   22096   49440    c120 bin_sem1<br>
+  26996     712   55584   83292   1455c bin_sem2<br>
+  27008     700   22100   49808    c290 bin_sem3<br>
+  28992     688   16944   46624    b620 clock0<br>
+  25456     692   19532   45680    b270 clock1<br>
+  34572    1160   19520   55252    d7d4 clockcnv<br>
+  26224     688   19508   46420    b554 clocktruth<br>
+  25204     692   16976   42872    a778 cnt_sem0<br>
+  26888     700   22108   49696    c220 cnt_sem1<br>
+  44180     752   27416   72348   11a9c dhrystone<br>
+  26088     688   19520   46296    b4d8 except1<br>
+  25236     692   16968   42896    a790 flag0<br>
+  29532     700   24668   54900    d674 flag1<br>
+  29508     704  109652  139864   22258 fptest<br>
+  25932     684   17016   43632    aa70 intr0<br>
+  25824     684   17112   43620    aa64 kalarm0<br>
+  24728     684   16956   42368    a580 kcache1<br>
+  25168     684   19512   45364    b134 kcache2<br>
+  28112     688   17168   45968    b390 kclock0<br>
+  25976     688   19524   46188    b46c kclock1<br>
+  26372     684   19512   46568    b5e8 kexcept1<br>
+  25140     684   16968   42792    a728 kflag0<br>
+  29824     688   24660   55172    d784 kflag1<br>
+  26896     704   24656   52256    cc20 kill<br>
+  26088     684   17028   43800    ab18 kintr0<br>
+  30812     692   22176   53680    d1b0 klock<br>
+  28504     688   22260   51452    c8fc kmbox1<br>
+  24984     684   16984   42652    a69c kmutex0<br>
+  26504     692   24704   51900    cabc kmutex1<br>
+  28792     900   34892   64584    fc48 kmutex3<br>
+  29264     796   34896   64956    fdbc kmutex4<br>
+  25240     684   22084   48008    bb88 ksched1<br>
+  25044     684   16968   42696    a6c8 ksem0<br>
+  26988     688   22100   49776    c270 ksem1<br>
+  25028     684   19512   45224    b0a8 kthread0<br>
+  25996     684   22080   48760    be78 kthread1<br>
+  28552     700   22252   51504    c930 mbox1<br>
+  31324     696   22612   54632    d568 mqueue1<br>
+  25108     692   16980   42780    a71c mutex0<br>
+  26464     704   24700   51868    ca9c mutex1<br>
+  27624     696   27280   55600    d930 mutex2<br>
+  28596     908   34884   64388    fb84 mutex3<br>
+  26156     696   22100   48952    bf38 release<br>
+  25460     688   22084   48232    bc68 sched1<br>
+  56356     828   45892  103076   192a4 stress_threads<br>
+  27900     712   27288   55900    da5c sync2<br>
+  26760     700   24692   52152    cbb8 sync3<br>
+  24924     684   19356   44964    afa4 thread0<br>
+  25868     684   22084   48636    bdfc thread1<br>
+  27452     700   24680   52832    ce60 thread2<br>
+  26136     688   42704   69528   10f98 thread_gdb<br>
+  27212     692   34916   62820    f564 timeslice<br>
+  52728     700  123332  176760   2b278 tm_basic<br>
+</code>
+
+</body>
+</html>
+
+
diff --git a/zpu/roadshow/roadshow/ecos/repository.tar.bz2 b/zpu/roadshow/roadshow/ecos/repository.tar.bz2
new file mode 100644
index 0000000..bc6291f
Binary files /dev/null and b/zpu/roadshow/roadshow/ecos/repository.tar.bz2 differ
diff --git a/zpu/roadshow/roadshow/games/.cvsignore b/zpu/roadshow/roadshow/games/.cvsignore
new file mode 100644
index 0000000..6c50257
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/.cvsignore
@@ -0,0 +1,5 @@
+summeria_arm.elf
+sumeria_zpu.elf
+eliza_arm.elf
+sumeria.elf
+eliza_zpu.elf
diff --git a/zpu/roadshow/roadshow/games/build.sh b/zpu/roadshow/roadshow/games/build.sh
new file mode 100644
index 0000000..ea661df
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/build.sh
@@ -0,0 +1,7 @@
+zpu-elf-gcc -Os -phi sumeria.c -o sumeria.elf -Wl,--relax -Wl,--gc-sections -lm -g
+zpu-elf-objcopy -O binary sumeria.elf sumeria.bin
+sh ../build/makefirmware.sh sumeria.bin sumeria.zpu
+zpu-elf-gcc -Os -phi eliza/*.c -o eliza.elf -Wl,--relax -Wl,--gc-sections -lm -g
+zpu-elf-objcopy -O binary eliza.elf eliza.bin
+sh ../build/makefirmware.sh eliza.bin eliza.zpu
+
diff --git a/zpu/roadshow/roadshow/games/eliza.bin b/zpu/roadshow/roadshow/games/eliza.bin
new file mode 100644
index 0000000..6d5a6c3
Binary files /dev/null and b/zpu/roadshow/roadshow/games/eliza.bin differ
diff --git a/zpu/roadshow/roadshow/games/eliza.elf b/zpu/roadshow/roadshow/games/eliza.elf
new file mode 100644
index 0000000..bfbbab7
Binary files /dev/null and b/zpu/roadshow/roadshow/games/eliza.elf differ
diff --git a/zpu/roadshow/roadshow/games/eliza.zpu b/zpu/roadshow/roadshow/games/eliza.zpu
new file mode 100644
index 0000000..d916270
Binary files /dev/null and b/zpu/roadshow/roadshow/games/eliza.zpu differ
diff --git a/zpu/roadshow/roadshow/games/eliza/eliza.c b/zpu/roadshow/roadshow/games/eliza/eliza.c
new file mode 100644
index 0000000..06f89ee
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/eliza.c
@@ -0,0 +1,269 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version. 
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details. 
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA. 
+*/
+
+#include <stdio.h>
+#include "parse.h"
+#include "response.h"
+
+typedef char WORD[40];
+typedef WORD SENTENCE[200];
+
+int numwords;
+SENTENCE s;
+WORD fam_member;    /* If mentioned a member of family, save for later. */
+int fam;
+
+main() {
+   int x, y, loop = 1, fact = 0;
+   char instring[200], outstring[200], sub[200], vrb[200], rst[200], qwd[200];
+   char osub[200], ovrb[200], orst[200];
+   fam = 0;
+   printf("Hello there.  My name is Eliza and I was written by Mohan Embar.\n");
+   printf("Please type \"END\" to end this session.\n");
+   printf("I'm here to help you if I can.  What seems to be the trouble?\n");
+   while (loop) {
+      printf("\n");
+      gets(instring);
+      printf("\n");
+      parse(instring);
+      if (numwords == 0) {
+         switch (x = randnum(2)) {
+            case 1 : printf("Don't you have anything to say?\n");
+               break;
+            case 2 : printf("Cat got your tongue?\n");
+               break;
+         }
+         continue;
+      }
+      if (!strcmp(s[1],"END")) {
+         printf("Goodbye.  Please come again.\n");
+         break;
+      }
+      agree();
+      if (bad_word())
+         printf(b_word_resp());
+      else if (naughty_word())
+         printf(n_word_resp());
+      else if (x = family()) {
+         fam = x;
+         printf(fam_resp());
+         strcpy(fam_member,s[fam]);
+      }
+      else if (sword("ALIKE",1))
+         printf(alike_resp());
+      else if (sword("ALWAYS",1))
+         printf(always_resp());
+      else if (sword("BECAUSE",1))
+         printf(because_resp());
+      else if (sword("YES",1))
+         printf(yes_resp());
+      else if (sword("NO",1) || sword("NOT",1))
+         printf(neg_resp());
+      else if (x = i_am()) { /* If occurrence of I AM x.. */
+         get_til_stop(x,outstring);    /* Get I AM x .. into outstring */
+         printf(i_am_resp(),outstring); /* Print reponse for this */
+      }
+      else if (real_quest() ||
+              (is_helper(s[1]) && is_sub_pronoun(s[2])) ||
+              sub_and_helper()) {
+         if (real_quest()) {
+            strcpy(qwd,s[1]);
+            strcpy(vrb,s[2]);
+            strcpy(sub,s[3]);
+            get_til_stop(4,rst);
+         }
+         else if (is_helper(s[1]) && is_sub_pronoun(s[2])) {
+            strcpy(vrb,s[1]);
+            strcpy(sub,s[2]);
+            get_til_stop(3,rst);
+            strcpy(qwd,"YES");
+         }
+         else if (sub_and_helper()) {
+            x = find_helper();
+            y = search_back_sub(x);
+            strcpy(vrb,s[x]);
+            get_til_stop(x+1,rst);
+            getrange(y,x-1,sub);
+            strcpy(qwd,"NO");
+         }
+         make_lower(qwd);
+         if (strcmp(sub,"I")) make_lower(sub);
+         make_lower(vrb);
+         make_lower(rst);
+         /* First do x verb y responses */
+
+         /*
+	 printf("\n*** %s\n",sub);
+         */
+	 
+	 if (!strcmp(sub," I") || !strcmp(sub,"I")) {
+            printf(you_resp());
+         }
+         else if (!strcmp(qwd,"no")) {
+            /* Record this statement for later use. */
+            fact = 1;
+            strcpy(osub,sub); strcpy(ovrb,vrb); strcpy(orst,rst);
+            if (is_be(vrb) && !strcmp(sub," you") && (y = sad_word())) {
+               getrange(y,y,outstring);
+               x = randnum(5)+6;
+            }
+            else if (is_be(vrb) && (y = sad_word())) {
+               getrange(y,y,outstring);
+               x = randnum(2)+11;
+            }
+            else if (is_be(vrb))
+               x = randnum(6);
+            else x = randnum(4);
+            switch (x) {
+               case 1 : printf("How do you feel about%s?\n",cnnv(sub));
+                  break;
+               case 2 : printf("Why %s%s%s?\n",vrb,sub,rst);
+                  break;
+               case 3 : for (y=1;sub[y]=sub[y--];y=y+2);
+                  sub[0] = toupper(sub[0]);
+                  printf("%s %s%s?\n",sub,vrb,rst);
+                  break;
+               case 4 : printf("Could you describe%s for me?\n",cnnv(sub));
+                  break;
+               case 5 : printf("What if%s were not%s?\n",sub,rst);
+                  break;
+               case 6 : printf("Would you be happy if%s were not%s?\n",sub,
+                                rst);
+                  break;
+               case 7 : printf("I'm sorry to hear that you are%s.\n",outstring);
+                  break;
+               case 8 : printf("Do you think that coming here will help you not to be%s?\n",outstring);
+                  break;
+               case 9 : printf("Let's talk about why you feel%s.\n",outstring);
+                  break;
+               case 10 : printf("What happened that made you feel%s?\n",outstring);
+                  break;
+               case 11 : printf("What could be the reason for your feeling%s?\n",outstring);
+                  break;
+               case 12 : printf("What could cause%s to be%s?\n",cnnv(sub),outstring);
+                  break;
+               case 13 : printf("If%s came here, would it help%s not to be%s?\n",sub,cnnv(sub),outstring);
+                  break;
+            }
+         }
+         else if (!strcmp(sub,"you"))
+            printf(you_know());
+         else if (!strcmp(qwd,"yes")) {
+            x = randnum(8);
+            switch (x) {
+               case 1 : printf("You want to know if %s %s%s.\n",sub,vrb,rst);
+                  break;
+               case 2 : printf("If %s %s%s, does that concern you?\n",sub,vrb,rst);
+                  break;
+               case 3 : printf("What are the consequences if %s %s%s?\n",sub,vrb,rst);
+                  break;
+               case 4 : printf("Why does %s concern you?\n",sub);
+                  break;
+               case 5 : printf("Why are you thinking of %s?\n",cnnv(sub));
+                  break;
+               case 6 : printf("Tell me more about %s.\n",cnnv(sub));
+                  break;
+               case 7 : printf("To answer that, I'd need to know more about %s.\n",cnnv(sub));
+                  break;
+               case 8 : printf("What is the relationship between you and %s?\n",cnnv(sub));
+                  break;
+               case 9 : printf("Why don't you ask %s?\n",cnnv(sub));
+                  break;
+            }
+         }
+         else {
+            x = randnum(8);
+            switch (x) {
+               case 1 : printf("You want to know %s %s %s%s.\n",qwd,sub,vrb,rst);
+                  break;
+               case 2 : printf("If %s %s%s, does that concern you?\n",sub,vrb,rst);
+                  break;
+               case 3 : printf("What are the consequences if %s %s%s?\n",sub,vrb,rst);
+                  break;
+               case 4 : printf("Why does %s concern you?\n",sub);
+                  break;
+               case 5 : printf("Why are you thinking of %s?\n",cnnv(sub));
+                  break;
+               case 6 : printf("Tell me more about %s.\n",cnnv(sub));
+                  break;
+               case 7 : printf("To answer that, I'd need to know more about %s.\n",cnnv(sub));
+                  break;
+               case 8 : printf("What is the relationship between you and %s?\n",cnnv(sub));
+                  break;
+               case 9 : printf("Why don't you ask %s?\n",cnnv(sub));
+                  break;
+            }
+         }
+      }
+      else if (is_command())
+         printf(command_resp());
+      else if (vague_quest())
+         printf(question());
+      else if ((s[numwords][0] == '?') && !real_quest())
+         printf(question());
+      else if (x = sad_word()) {
+         getrange(x,x,outstring);
+         for (y=1;outstring[y]=outstring[y--];y=y+2);
+         outstring[0] = toupper(outstring[0]);
+         printf("%s?\n",outstring);
+      }
+      else if (x = can_spit_out()) {
+         if (x<=(numwords-2) && is_sub_pronoun(s[x])
+                             && (matches("NEED",s[x+1]) ||
+                                 matches("WANT",s[x+1]))) {
+            get_til_stop(x+2,outstring);
+            strcpy(sub,s[x]);
+            if (strcmp(sub,"I")) make_lower(sub);
+            if (strcmp(s[x],"I")) make_lower(s[x]);
+            x = randnum(6);
+            switch (x) {
+               case 1 : printf("What would it mean to %s if %s got%s?\n",cnnv2(s[x]),sub,outstring);
+                  break;
+               case 2 : printf("Would %s really be happy if %s got%s?\n",sub,sub,outstring);
+                  break;
+               case 3 : printf("Why is getting%s so desirable?\n",outstring);
+                  break;
+               case 4 : printf("Okay.  Suppose %s got%s.  Then what?\n",sub,outstring);
+                  break;
+               case 5 : printf("Why is this important to %s?\n",cnnv2(sub));
+                  break;
+               case 6 : printf("What price would %s pay to achieve this?\n",sub);
+                  break;
+            }
+         }
+         else {
+            get_til_stop(x,outstring);
+            outstring[1]=toupper(outstring[1]);
+            printf("%s.\n",outstring+1);
+         }
+      }
+      else if (fam) {
+         make_lower(fam_member);
+         printf(family_resp(),fam_member);
+         fam = 0;
+      }
+      else if (fact && (randnum(5)==3)) {
+         printf(old_fact(),osub,ovrb,orst);
+         fact = 0;
+      }
+      else {
+         printf(go_on());
+      }
+   }
+}
diff --git a/zpu/roadshow/roadshow/games/eliza/parse.c b/zpu/roadshow/roadshow/games/eliza/parse.c
new file mode 100644
index 0000000..aba2033
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/parse.c
@@ -0,0 +1,719 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version. 
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details. 
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA. 
+*/
+
+/* Program defined abstract data type called list.  A list contains
+ * character strings each of which has a maximum length of 20 characters.
+ *
+ * Operations supported are:
+ *
+ *    
+ */
+typedef char WORD[40];
+typedef WORD SENTENCE[200];
+
+extern int numwords;
+extern SENTENCE s;
+
+/* Returns upper case value of c */
+char upcase(c)
+   char c;
+{
+   if (islower(c)) return toupper(c); else return c;
+}
+
+/* This function converts string1 into lowercase. */
+void make_lower(string1)
+   char *string1;
+{
+   char c;
+   while (c = *string1) *string1++ = tolower(c);
+}
+
+/* Parses words in instring into WORD array s
+ * Automatically translates n't to not, 're to are
+ * Stores all letters in uppercase.  Sets numwords to number of tokens in
+ * s.  Valid indices are from 1 .. numwords.
+ */
+void parse(instring)
+   char *instring;
+{
+   char c; int i;
+   int read_word = 0;
+   int offset = -1;
+   numwords = 0;
+   while (c = *instring++) {
+      switch(c) {
+         case ' ' :
+         case '\t' :
+            read_word = 0;
+            continue;
+         case ',' :
+         case '?' :
+         case '.' :
+         case ':' :
+         case '"' :
+            s[numwords++][++offset] = '\0';
+            read_word = 0;
+            s[numwords][offset = 0] = c;
+            break;
+         case '\'' :
+            if ((s[numwords][offset] == 'N') && (upcase(*instring) == 'T')) {
+               s[numwords++][offset]='\0';
+               s[numwords][0] = 'N';
+               s[numwords][offset = 1] = 'O';
+               read_word = 1;
+            }
+            else if (upcase(*instring) == 'R') {
+               s[numwords++][++offset] = '\0';
+               s[numwords][offset = 0] = 'A';
+               read_word = 1;
+            }
+            else if (upcase(*instring) == 'V') {
+               s[numwords++][++offset] = '\0';
+               s[numwords][offset = 0] = 'H';
+               s[numwords][++offset] = 'A';
+               read_word = 1;
+            }
+            else if (upcase(*instring) == 'M') {
+               s[numwords++][++offset] = '\0';
+               s[numwords][offset = 0] = 'A';
+               read_word = 1;
+            }
+            else if (upcase(*instring) == 'L') {
+               s[numwords++][++offset] = '\0';
+               s[numwords][offset = 0] = 'W';
+               s[numwords][++offset] = 'I';
+               read_word = 1;
+            }
+            else if (upcase(*instring) == 'S') {
+               s[numwords][offset+1] = '\0';
+               if (!strcmp(s[numwords],"HE") || !strcmp(s[numwords],"SHE") 
+                                             || !strcmp(s[numwords],"IT")) {
+                  s[++numwords][offset = 0] = 'I';
+                  read_word = 1;
+               }
+               else s[numwords][++offset] = '\'';
+            }
+            break;
+         default :
+            if (isalpha(c))
+               if (read_word) {
+                  s[numwords][++offset] = upcase(c);
+               }
+               else {
+                  s[numwords++][++offset] = '\0';
+                  ++read_word;
+                  s[numwords][offset = 0] = upcase(c);
+               }
+            else {
+               read_word = 0;
+            }
+      }  
+   }
+   s[numwords][++offset] = '\0';
+   return;
+}
+
+/* Self-explanatory.  Used when computer spits back the sentence */
+void agree()
+{
+   int i;
+   for(i=1;i<=numwords;i++) {
+      if (!strcmp(s[i],"I")) {
+         strcpy(s[i],"YOU");
+      }
+      else if (!strcmp(s[i],"YOU")) {
+         strcpy(s[i],"I");
+      }
+      else if (!strcmp(s[i],"YOUR")) {
+         strcpy(s[i],"MY");
+      }
+      else if (!strcmp(s[i],"MY")) {
+         strcpy(s[i],"YOUR");
+      }
+      else if (!strcmp(s[i],"YOU")) {
+         strcpy(s[i],"ME");
+      }
+      else if (!strcmp(s[i],"ME")) {
+         strcpy(s[i],"YOU");
+      }
+      else if (!strcmp(s[i],"MINE")) {
+         strcpy(s[i],"YOURS");
+      }
+      else if (!strcmp(s[i],"YOURS")) {
+         strcpy(s[i],"MINE");
+      }
+      else if (!strcmp(s[i],"WE")) {
+         strcpy(s[i],"YOU");
+      }
+      else if (!strcmp(s[i],"YOURSELF")) {
+         strcpy(s[i],"MYSELF");
+      }
+      else if (!strcmp(s[i],"MYSELF")) {
+         strcpy(s[i],"YOURSELF");
+      }
+      else if (!strcmp(s[i],"OURSELVES")) {
+         strcpy(s[i],"YOURSELVES");
+      }
+      else if (!strcmp(s[i],"OURS")) {
+         strcpy(s[i],"YOURS");
+      }
+      else if (!strcmp(s[i],"OUR")) {
+         strcpy(s[i],"YOUR");
+      }
+   }
+   for (i=1;i<=numwords;i++) {
+      if (!strcmp(s[i],"AM")) {
+         strcpy(s[i],"ARE");
+      }
+      else if ( (!strcmp(s[i],"ARE")) &&
+                (((i>0) && (!strcmp(s[i-1],"I"))) ||
+                 ((i<numwords) && (!strcmp(s[i+1],"I"))) ) ) {
+         strcpy(s[i],"AM");
+      }
+      else if ( (!strcmp(s[i],"WERE")) &&
+                (((i>0) && (!strcmp(s[i-1],"I"))) ||
+                 ((i<numwords) && (!strcmp(s[i+1],"I"))) ) ) {
+         strcpy(s[i],"WAS");
+      }
+      else if ( (!strcmp(s[i],"WAS")) &&
+                (((i>0) && (!strcmp(s[i-1],"YOU"))) ||
+                 ((i<numwords) && (!strcmp(s[i+1],"YOU"))) ) ) {
+         strcpy(s[i],"WERE");
+      }
+   }
+}
+
+/* Returns 1 if string1 matches first length(string1) characters of string2
+ * and 0 if not.
+ */
+int matches(string1, string2)
+   char *string1, *string2;
+{
+   int c;
+   if (strlen(string1)>strlen(string2))
+      return 0;
+   else { /* length(string1)<=length(string2) */
+      while (c = *string1++) {
+         if (c != *string2++) return 0;
+      }
+      return 1;
+   }   
+}
+
+/* Search WORD array s for search_string.  If exact = 1, enforce exact match.
+ * Otherwise, return positive match if all characters of search_string match
+ * the first length(search_string) characters of a WORD in s.  Assumes legal
+ * values for exact are 0 or 1.  Returns index of match in s if match, 0 if
+ * no match.
+ */
+int sword(s_string, exact)
+   char *s_string;
+   int exact;
+{
+   int i;
+   for (i=1;i<=numwords;i++) {
+      if (exact) {
+         if (!strcmp(s_string,s[i])) return i;
+      }
+      else {
+         if (matches(s_string,s[i])) return i;
+      }
+   }
+   /* No match */
+   return 0;
+}
+
+int bad_word()
+{
+   if (sword("\115\117\124\110\105\122\106\125\103\113",0))
+      return 1;
+   else if (sword("\106\125\103\113",0))
+      return 1;
+   else if (sword("\123\110\111\124",0))
+      return 1;
+   else if (sword("\101\123\123\110\117\114\105",1))
+      return 1;
+   else if (sword("\101\123\123",1))
+      return 1;
+   else return  0;
+}
+
+int naughty_word()
+{
+   if (sword("DAMN",0))
+      return 1;
+   else if (sword("STUPID",0))
+      return 1;
+   else if (sword("IDIOT",0))
+      return 1;
+   else if (sword("MORON",0))
+      return 1;
+   else if (sword("NUMBSKULL",0))
+      return 1;
+   else if (sword("IMBECILE",0))
+      return 1;
+   else if (sword("OBNOXIOUS",0))
+      return 1;
+   else return 0;
+}
+
+/* Return the index to a form of be or helping verb, if one exists
+ * Otherwise, return 0.
+ */
+int find_helper()
+{
+   int x;
+   if (x = sword("AM",1))
+      return x;
+   else if (x = sword("IS",1))
+      return x;
+   else if (x = sword("ARE",1))
+      return x;
+   else if (x = sword("WAS",1))
+      return x;
+   else if (x = sword("WERE",1))
+      return x;
+   else if (x = sword("WILL",1))
+      return x;
+   else if (x = sword("DO",1))
+      return x;
+   else if (x = sword("DID",1))
+      return x;
+   else if (x = sword("DOES",1))
+      return x;
+   else if (x = sword("HAVE",1))
+      return x;
+   else if (x = sword("HAD",1))
+      return x;
+   else if (x = sword("HAS",1))
+      return x;
+   else if (x = sword("SHALL",1))
+      return x;
+   else if (x = sword("SHOULD",1))
+      return x;
+   else if (x = sword("CAN",1))
+      return x;
+   else if (x = sword("COULD",1))
+      return x;
+   else if (x = sword("MAY",1))
+      return x;
+   else if (x = sword("MIGHT",1))
+      return x;
+   else return 0;
+}
+
+/* Returns 1 is string1 is pronoun.  0 if not. */
+int is_sub_pronoun(string1)
+   char *string1;
+{
+   if (!strcmp("I",string1))
+      return 1;
+   else if (!strcmp("YOU",string1))
+      return 1;
+   else if (!strcmp("WE",string1))
+      return 1;
+   else if (!strcmp("HE",string1))
+      return 1;
+   else if (!strcmp("SHE",string1))
+      return 1;
+   else if (!strcmp("IT",string1))
+      return 1;
+   else if (!strcmp("THEY",string1))
+      return 1;
+   else return 0;
+}
+
+int is_possesive(string1)
+   char *string1;
+{
+   if (!strcmp("MY",string1))
+      return 1;
+   else if (!strcmp("YOUR",string1))
+      return 1;
+   else if (!strcmp("OUR",string1))
+      return 1;
+   else if (!strcmp("HIS",string1))
+      return 1;
+   else if (!strcmp("HER",string1))
+      return 1;
+   else if (!strcmp("ITS",string1))
+      return 1;
+   else if (!strcmp("THEIR",string1))
+      return 1;
+   else return 0;
+}
+
+int is_article(string1)
+   char *string1;
+{
+   if (!strcmp("A",string1))
+      return 1;
+   else if (!strcmp("AN",string1))
+      return 1;
+   else if (!strcmp("THE",string1))
+      return 1;
+   else return 0;
+}
+
+/* Tries to find reference to a family member */
+int family()
+{
+   int x;
+   if (x = sword("MOTHER",1))
+      return x;
+   else if (x = sword("FATHER",1))
+      return x;
+   else if (x = sword("SISTER",1))
+      return x;
+   else if (x = sword("BROTHER",1))
+      return x;
+   else if (x = sword("DAD",1))
+      return x;
+   else if (x = sword("MOM",1))
+      return x;
+   else if (x = sword("UNCLE",1))
+      return x;
+   else if (x = sword("AUNT",1))
+      return x;
+   else if (x = sword("GRANDMOTHER",1))
+      return x;
+   else if (x = sword("GRANDFATHER",1))
+      return x;
+   else if (x = sword("COUSIN",1))
+      return x;
+   else if (x = sword("GRANDMA",1))
+      return x;
+   else if (x = sword("GRANDPA",1))
+      return x;
+   else return 0;
+}
+
+int i_am()
+{
+   int x, e=1;
+   while (e) {
+      for (x=e;x<=numwords;x++) if (!strcmp("I",s[x])) break;
+      if (x >= numwords)
+         return 0;
+      else if (!strcmp("AM",s[x+1]))
+         return x;
+      else e = ++x;
+   }
+}
+
+void get_til_stop(x,string1)
+   int x;
+   char *string1;
+{
+   char c, *temp;
+   int e = 1;  /* Exit test */
+   while (e) {
+      if (x>numwords) {
+         e--;
+         *string1 = '\0';
+      }
+      else if (!isalpha(s[x][0])) {
+         e--;
+         *string1 = '\0';
+      }
+      else if (!strcmp("AND",s[x]) || !strcmp("OR",s[x])
+                                   || !strcmp("BUT",s[x])) {
+         e--;
+         *string1 = '\0';
+      }
+      else {
+         *string1++ = ' ';
+         if (!strcmp("I",s[x]))
+            *string1++ = 'I';
+         else {
+            temp = s[x];
+            while (c = *temp++) *string1++ = tolower(c);
+         }
+         x++;
+      }
+   }
+   *string1 = '\0';
+}
+
+int sad_word()
+{
+   int x;
+   if (x = sword("DEPRESS",0))
+      return x;
+   else if (x = sword("UNHAPPY",1))
+      return x;
+   else if (x = sword("SAD",1))
+      return x;
+   else if (x = sword("MISERABLE",1))
+      return x;
+   else if (x = sword("AWFUL",1))
+      return x;
+   else if (x = sword("UPSET",1))
+      return x;
+   else if (x = sword("TERRIBLE",1))
+      return x;
+   else return 0;
+}
+
+int search_back_sub(x)
+   int x;
+{
+   int y = --x;
+   while (y) {
+      if (is_possesive(s[y]) || is_sub_pronoun(s[y]) || is_article(s[y]))
+         return y;
+      else
+         y--;
+   }
+   return y;
+}
+
+/* Returns 1 if string is a form of be or helping verb,
+ * Otherwise, returns 0.
+ */
+int is_helper(string1)
+   char *string1;
+{
+   if (!strcmp(string1,"AM"))
+      return 1;
+   else if (!strcmp(string1,"IS"))
+      return 1;
+   else if (!strcmp(string1,"ARE"))
+      return 1;
+   else if (!strcmp(string1,"WAS"))
+      return 1;
+   else if (!strcmp(string1,"WERE"))
+      return 1;
+   else if (!strcmp(string1,"WILL"))
+      return 1;
+   else if (!strcmp(string1,"DO"))
+      return 1;
+   else if (!strcmp(string1,"DID"))
+      return 1;
+   else if (!strcmp(string1,"DOES"))
+      return 1;
+   else if (!strcmp(string1,"HAVE"))
+      return 1;
+   else if (!strcmp(string1,"HAD"))
+      return 1;
+   else if (!strcmp(string1,"HAS"))
+      return 1;
+   else if (!strcmp(string1,"SHALL"))
+      return 1;
+   else if (!strcmp(string1,"SHOULD"))
+      return 1;
+   else if (!strcmp(string1,"CAN"))
+      return 1;
+   else if (!strcmp(string1,"COULD"))
+      return 1;
+   else if (!strcmp(string1,"MAY"))
+      return 1;
+   else if (!strcmp(string1,"MIGHT"))
+      return 1;
+   else if (matches(string1,"FEEL"))
+      return 1;
+   else return 0;
+}
+
+void getrange(y,x,string1)
+   int y, x;
+   char *string1;
+{
+   char c, *temp;
+   while (y<=x) {
+      *string1++ = ' ';
+      if (!strcmp("I",s[y]))
+         *string1++ = 'I';
+      else {
+         temp = s[y];
+         while (c = *temp++) *string1++ = tolower(c);
+      }
+      y++;
+   }
+   *string1 = '\0';
+}
+
+/* Returns 1 if s[1] is a command.  0 if not. */
+int is_command()
+{
+   if (!strcmp("GIVE",s[1]))
+      return 1;
+   else if (!strcmp("TELL",s[1]))
+      return 1;
+   else if (!strcmp("SHOW",s[1]))
+      return 1;
+   else if (!strcmp("EXPLAIN",s[1]))
+      return 1;
+   else return 0;
+}
+
+int four_ws()
+{
+   if (!strcmp(s[1],"WHO"))
+      return 1;
+   else if (!strcmp(s[1],"WHAT"))
+      return 1;
+   else if (!strcmp(s[1],"WHERE"))
+      return 1;
+   else if (!strcmp(s[1],"WHY"))
+      return 1;
+   else if (!strcmp(s[1],"WHEN"))
+      return 1;
+   else if (!strcmp(s[1],"HOW"))
+      return 1;
+   else return 0;
+}
+
+int vague_quest()
+{
+   return (four_ws() && (!is_helper(s[2]) || !is_sub_pronoun(s[3])));
+}
+
+int real_quest()
+{
+   return (four_ws() && is_helper(s[2]) && is_sub_pronoun(s[3]));
+}
+
+int sub_and_helper()
+{
+   int x;
+   return ((x = find_helper()) && search_back_sub(x));
+}
+
+char *cnnv(string1)
+   char *string1;
+{
+   if (!strcmp(string1," i")) {
+      return " myself";
+   }
+   else if (!strcmp(string1," you")) {
+      return " yourself";
+   }
+   else if (!strcmp(string1," we")) {
+      return " ourselves";
+   }
+   else if (!strcmp(string1," he")) {
+      return " him";
+   }
+   else if (!strcmp(string1," she")) {
+      return " her";
+   }
+   else if (!strcmp(string1," it")) {
+      return " it";
+   }
+   else if (!strcmp(string1," they")) {
+      return " them";
+   }
+   if (!strcmp(string1,"i")) {
+      return "myself";
+   }
+   else if (!strcmp(string1,"you")) {
+      return "yourself";
+   }
+   else if (!strcmp(string1,"we")) {
+      return "ourselves";
+   }
+   else if (!strcmp(string1,"he")) {
+      return "him";
+   }
+   else if (!strcmp(string1,"she")) {
+      return "her";
+   }
+   else if (!strcmp(string1,"it")) {
+      return "it";
+   }
+   else if (!strcmp(string1,"they")) {
+      return "them";
+   }
+   else return string1;
+}
+
+int is_be(string1)
+   char *string1;
+{
+   if (!strcmp("am",string1))
+      return 1;
+   else if (!strcmp("is",string1))
+      return 1;
+   else if (!strcmp("are",string1))
+      return 1;
+   else if (!strcmp("was",string1))
+      return 1;
+   else if (!strcmp("were",string1))
+      return 1;
+   else return 0;
+}
+
+int can_spit_out()
+{
+   int x;
+   for (x=1;x<=numwords;x++)
+      if (is_possesive(s[x]) || is_sub_pronoun(s[x]) || is_article(s[x]))
+         return x;
+   return 0;
+}
+
+char *cnnv2(string1)
+   char *string1;
+{
+   if (!strcmp(string1," i")) {
+      return " me";
+   }
+   else if (!strcmp(string1," you")) {
+      return " you";
+   }
+   else if (!strcmp(string1," we")) {
+      return " us";
+   }
+   else if (!strcmp(string1," he")) {
+      return " him";
+   }
+   else if (!strcmp(string1," she")) {
+      return " her";
+   }
+   else if (!strcmp(string1," it")) {
+      return " it";
+   }
+   else if (!strcmp(string1," they")) {
+      return " them";
+   }
+   if (!strcmp(string1,"i")) {
+      return "me";
+   }
+   else if (!strcmp(string1,"you")) {
+      return "you";
+   }
+   else if (!strcmp(string1,"we")) {
+      return "us";
+   }
+   else if (!strcmp(string1,"he")) {
+      return "him";
+   }
+   else if (!strcmp(string1,"she")) {
+      return "her";
+   }
+   else if (!strcmp(string1,"it")) {
+      return "it";
+   }
+   else if (!strcmp(string1,"they")) {
+      return "them";
+   }
+   else return string1;
+}
diff --git a/zpu/roadshow/roadshow/games/eliza/parse.h b/zpu/roadshow/roadshow/games/eliza/parse.h
new file mode 100644
index 0000000..62dc353
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/parse.h
@@ -0,0 +1,33 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version. 
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details. 
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA. 
+*/
+
+extern void parse();
+extern void agree();
+extern int matches();
+extern int sword();
+extern void make_lower();
+extern int i_am();
+extern void get_til_stop();
+extern int sad_word();
+extern int search_back_sub();
+extern int is_helper();
+extern char *cnnv();
+extern int is_be();
+extern int can_spit_out();
+extern char *cnnv2();
diff --git a/zpu/roadshow/roadshow/games/eliza/response.c b/zpu/roadshow/roadshow/games/eliza/response.c
new file mode 100644
index 0000000..aa58025
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/response.c
@@ -0,0 +1,365 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version. 
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details. 
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA. 
+*/
+
+#include <stdio.h>
+#include <math.h>
+
+/* This function returns a random number between 1 and arg */
+int randnum(arg)
+   int arg;
+{
+   return ( (rand() % arg) + 1 );
+}
+
+char *question()
+{
+   int i = randnum(21);
+   switch (i) {
+      case 1 : return "Why do you ask?\n";
+      case 2 : return "I don't know.\n";
+      case 3 : return "I don't think so.\n";
+      case 4 : return "Do you think that's relevant?\n";
+      case 5 : return "Can you rephrase that?\n";
+      case 6 : return "I'm not sure I understand what you want.\n";
+      case 7 : return "I don't see what you're asking.\n";
+      case 8 : return "What are you asking?\n";
+      case 9 : return "What do you mean?\n";
+      case 10 : return "What?\n";
+      case 11 : return "Are you sure that's what you want to know?\n";
+      case 12 : return "Why do you want to know?\n";
+      case 13 : return "What's it to you?\n";
+      case 14 : return "I don't think that's important.\n";
+      case 15 : return "That has little to do with the real issue.\n";
+      case 16 : return "What's the significance you your question?\n";
+      case 17 : return "Could that question be hiding a deeper intent?\n";
+      case 18 : return "I don't see the connection.\n";
+      case 19 : return "Why is this important to you?\n";
+      case 20 : return "That's not really important.\n";
+      case 21 : return "That seems to have little to do with this.\n";
+   }
+}
+
+char *b_word_resp()
+{
+   int i = randnum(20);
+   switch (i) {
+      case  1 : return "I don't like your language.\n";
+      case  2 : return "Can we please do without the swearing?\n";
+      case  3 : return "You should wash your mouth with soap and water\n";
+      case  4 : return "Cut that out.\n";
+      case  5 : return "Stop swearing please.\n";
+      case  6 : return "Hey!  Watch your mouth.\n";
+      case  7 : return "Will you please stop swearing?\n";
+      case  8 : return "I'm going to report you to your manager.\n";
+      case  9 : return "Let's try to be civilized about this.\n";
+      case 10 : return "We can do without the bad language.\n";
+      case 11 : return "Come on.  No bad words, please.\n";
+      case 12 : return "Can you try to control your bad mouth?\n";
+      case 13 : return "I'm starting to get offended by your bad language.\n";
+      case 14 : return "Can you please get a grip on yourself?\n";
+      case 15 : return "Hey.  Calm down, I'm only a computer.\n";
+      case 16 : return "Please try to tone your language down.\n";
+      case 17 : return "You're beginning to get on my nerves.\n";
+      case 18 : return "I don't need this kind of talk.\n";
+      case 19 : return "Why are you speaking so basely?\n";
+      case 20 : return "Your vocabulary is unbecoming of you.\n";
+   }
+}
+
+char *n_word_resp()
+{
+   int i = randnum(17);
+   switch (i) {
+      case 1 : return "I don't like your tone of voice.\n";
+      case 2 : return "Don't lose your temper now.\n";
+      case 3 : return "That's not a reason to get upset.\n";
+      case 4 : return "Is it worth getting angry over?\n";
+      case 5 : return "Does that disturb you?\n";
+      case 6 : return "Does this trouble you?\n";
+      case 7 : return "Why is this making you upset?\n";
+      case 8 : return "I don't see why you're getting worked up.\n";
+      case 9 : return "Is that really such a big deal?\n";
+      case 10 : return "Calm down.  Let's discuss this.\n";
+      case 11 : return "Hang on a second.  Think about what you're saying.\n";
+      case 12 : return "Don't you think you're overreacting a bit?\n";
+      case 13 : return "I don't see what the big deal is.\n";
+      case 14 : return "Take it easy.  It's not that bad.\n";
+      case 15 : return "Are you getting angry?\n";
+      case 16 : return "Why is such a small thing making you upset?\n";
+      case 17 : return "I don't see why you're getting annoyed.\n";
+   }
+}
+
+char *because_resp()
+{
+   int i = randnum(12);
+   switch (i) {
+      case 1 : return "Is that the real reason?\n";
+      case 2 : return "I don't see the connection.\n";
+      case 3 : return "What kind of an explanation is that?\n";
+      case 4 : return "What does that have to do with it?\n";
+      case 5 : return "That justification is a bit shaky to me.\n";
+      case 6 : return "I don't see the point.\n";
+      case 7 : return "I don't see that as a good reason.\n";
+      case 8 : return "Are you happy with that justification?\n";
+      case 9 : return "Are you sure?\n";
+      case 10 : return "I don't understand.\n";
+      case 11 : return "What does one thing have to do with the other?\n";
+      case 12 : return "I don't see how that's related.\n";
+   }
+}
+
+char *yes_resp()
+{
+   int i = randnum(21);
+   switch (i) {
+      case 1 : return "Are you sure?\n";
+      case 2 : return "Are you positive about that?\n";
+      case 3 : return "How can you be so sure?\n";
+      case 4 : return "Let's not jump to conclusions now.\n";
+      case 5 : return "I don't see the connection.\n";
+      case 6 : return "Have you considered all the possibilities?\n";
+      case 7 : return "I'm still not convinced.\n";
+      case 8 : return "Think about what you've just said.\n";
+      case 9 : return "What are the implications of this?\n";
+      case 10 : return "So what have we concluded?\n";
+      case 11 : return "What does this mean?\n";
+      case 12 : return "What do you mean?\n";
+      case 13 : return "I'm having trouble understanding your argument.\n";
+      case 14 : return "I don't see where you're coming from.\n";
+      case 15 : return "You think so?\n";
+      case 16 : return "Really?\n";
+      case 17 : return "Is that right?\n";
+      case 18 : return "Oh?\n";
+      case 19 : return "Are you certain of this?\n";
+      case 20 : return "I read you loud and clear.\n";
+      case 21 : return "Yes?\n";
+   }
+}
+
+char *neg_resp()
+{
+   int i = randnum(11);
+   switch (i) {
+      case 1 : return "Why not?\n";
+      case 2 : return "How come?\n";
+      case 3 : return "No?\n";
+      case 4 : return "Is there a reason why not?\n";
+      case 5 : return "No?\n";
+      case 6 : return "Why don't you think so?\n";
+      case 7 : return "I don't see why not.\n";
+      case 8 : return "What could be the reasons for this?\n";
+      case 9 : return "Do you really believe this?\n";
+      case 10 : return "You're not sure?\n";
+      case 11 : return "That's a rather pessimistic attitude.\n";
+   }
+}
+
+char *go_on()
+{
+   int i = randnum(20);
+   switch (i) {
+      case 1 : return "Go on.\n";
+      case 2 : return "I see.\n";
+      case 3 : return "Keep going.\n";
+      case 4 : return "Please continue.\n";
+      case 5 : return "I'm listening.\n";
+      case 6 : return "Can you elaborate on that?\n";
+      case 7 : return "I understand.\n";
+      case 8 : return "Oh?\n";
+      case 9 : return "Is that right?\n";
+      case 10 : return "Really?\n";
+      case 11 : return "No, really?\n";
+      case 12 : return "That's interesting.\n";
+      case 13 : return "I'm finding this very informative.\n";
+      case 14 : return "This is all very revealing.\n";
+      case 15 : return "Don't hesitate to be honest with me.\n";
+      case 16 : return "Don't hold anything back now.\n";
+      case 17 : return "That's an interesting observation.\n";
+      case 18 : return "I don't understand.\n";
+      case 19 : return "I'm starting to get the big picture.\n";
+      case 20 : return "And?\n";
+   }
+}
+
+char *always_resp()
+{
+   int i = randnum(10);
+   switch (i) {
+      case 1 : return "Can you think of a specific example?\n";
+      case 2 : return "When?\n";
+      case 3 : return "Really, always?\n";
+      case 4 : return "Are you sure you can generalize like that?\n";
+      case 5 : return "Isn't that a bit of an oversimplification?\n";
+      case 6 : return "Be careful not to jump to conclusions now.\n";
+      case 7 : return "All the time?\n";
+      case 8 : return "So you're saying that this is happens quite often.\n";
+      case 9 : return "Does this happen a lot?\n";
+      case 10 : return "On what occassions?\n";
+   }
+}
+
+char *alike_resp()
+{
+   int i = randnum(4);
+   switch (i) {
+      case 1 : return "In what way?\n";
+      case 2 : return "What resemblance do you see?\n";
+      case 3 : return "What similarities are you thinking of?\n";
+      case 4 : return "Specifically, what do you mean by this.\n";
+   }
+}
+
+char *fam_resp()
+{
+   int i = randnum(7);
+   switch (i) {
+      case 1 : return "Tell me more about your family.\n";
+      case 2 : return "Please go on about your family.\n";
+      case 3 : return "How was your home life when you were young?\n";
+      case 4 : return "How do you get along with your parents?\n";
+      case 5 : return "Would you say you have family problems?\n";
+      case 6 : return "Your family interests me.\n";
+      case 7 : return "Let`s talk some more about your family.\n";
+   }
+}
+
+char *family_resp()
+{
+   int i = randnum(5);
+   switch (i) {
+      case 1 : return "Earlier you were speaking of your %s.\n";
+      case 2 : return "Tell me more about your %s.\n";
+      case 3 : return "Do you think your %s ties into all this?\n";
+      case 4 : return "How would your %s feel about this?\n";
+      case 5 : return "Does your %s feel the same way?\n";
+   }
+}
+
+char *i_am_resp()
+{
+   int i = randnum(6);
+   switch (i) {
+      case 1 : return "Would you like to think that%s?\n";
+      case 2 : return "Why do you say that%s?\n";
+      case 3 : return "What leads you to believe that%s?\n";
+      case 4 : return "What do you mean \"%s\"?\n";
+      case 5 : return "You really feel that%s?\n";
+      case 6 : return "Would it make you feel better if%s?\n";
+   }
+}
+
+char *sad1_word_resp()
+{
+   int i = randnum(5);
+   switch (i) {
+      case 1 : return "I am sorry to hear that%s.\n";
+      case 2 : return "What are you going to do about the fact that%s?\n";
+      case 3 : return "Why do you think%s?\n";
+      case 4 : return "What gives you the impression that%s?\n";
+      case 5 : return "Are you sure that%s?\n";
+   }
+}
+
+char *sad2_word_resp()
+{
+   int i = randnum(5);
+   switch (i) {
+      case 1 : return "I am sorry to hear that%s are feeling%s.\n";
+      case 2 : return "What are you going to do about the fact that%s?\n";
+      case 3 : return "Why do you think%s?\n";
+      case 4 : return "What gives you the impression that%s?\n";
+      case 5 : return "Are you sure that%s?\n";
+   }
+}
+
+char *command_resp()
+{
+   int i = randnum(21);
+   switch (i) {
+      case 1 : return "Why do you ask?\n";
+      case 2 : return "Why should I?\n";
+      case 3 : return "Why do you want me to?\n";
+      case 4 : return "Do you think that's relevant?\n";
+      case 5 : return "Can you rephrase that?\n";
+      case 6 : return "I'm not sure I understand what you want.\n";
+      case 7 : return "I don't see what you're asking.\n";
+      case 8 : return "What are you asking?\n";
+      case 9 : return "What do you mean?\n";
+      case 10 : return "What?\n";
+      case 11 : return "Are you sure that's what you want to know?\n";
+      case 12 : return "Why do you want to know?\n";
+      case 13 : return "What's it to you?\n";
+      case 14 : return "I don't think that's important.\n";
+      case 15 : return "That has little to do with the real issue.\n";
+      case 16 : return "What's the significance you your question?\n";
+      case 17 : return "Could that question be hiding a deeper intent?\n";
+      case 18 : return "If I did that, what would it mean to you?\n";
+      case 19 : return "Why is this important to you?\n";
+      case 20 : return "That's not really important.\n";
+      case 21 : return "That seems to have little to do with this.\n";
+   }
+}
+
+char *you_resp()
+{
+   int i = randnum(9);
+   switch (i) {
+      case 1 : return "Let's talk about you, not me.\n";
+      case 2 : return "I'm not the one we came here to talk about.\n";
+      case 3 : return "I don't find myself that interesting.  Let's talk about you.\n";
+      case 4 : return "I'd prefer to talk about you, not me.\n";
+      case 5 : return "Why are you interested in me?\n";
+      case 6 : return "I want to talk about you for a change.\n";
+      case 7 : return "I'd rather not talk about myself.\n";
+      case 8 : return "Enough about me.\n";
+      case 9 : return "Let's talk about something other than myself.\n";
+   }
+}
+
+char *you_know()
+{
+   int i = randnum(13);
+   switch (i) {
+      case 1 : return "I don't know.  What do you think?\n";
+      case 2 : return "You tell me.\n";
+      case 3 : return "I think you know the answer to that.\n";
+      case 4 : return "Can you tell me?\n";
+      case 5 : return "What do you think?\n";
+      case 6 : return "Can you answer that yourself?\n";
+      case 7 : return "If you give it some thought, you should know.\n";
+      case 8 : return "Maybe you already know the answer to that.\n";
+      case 9 : return "Perhaps you already know.\n";
+      case 10 : return "If we keep talking, maybe we'll find out.\n";
+      case 11 : return "Perhaps that will be brought out in this discussion.\n";
+      case 12 : return "Let's find the answer out together.\n";
+      case 13 : return "I'm sure we can work out the answer to that.\n";
+   }
+}
+
+char *old_fact()
+{
+   int i = randnum(4);
+   switch (i) {
+      case 1 : return "Earlier you said that%s %s%s.\n";
+      case 2 : return "Could this have anything to do with the fact that%s %s%s?\n";
+      case 3 : return "What does that have to do with your saying that%s %s%s?\n";
+      case 4 : return "Didn't you just say that%s %s%s?\n";
+   }
+}
diff --git a/zpu/roadshow/roadshow/games/eliza/response.h b/zpu/roadshow/roadshow/games/eliza/response.h
new file mode 100644
index 0000000..8cc77e9
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/eliza/response.h
@@ -0,0 +1,41 @@
+/*
+Copyright (C) 1988-2003 by Mohan Embar
+
+http://www.thisiscool.com/
+DISCLAIMER: This was written in 1988. I don't code like this anymore!
+
+This program is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software
+Foundation; either version 2 of the License, or (at your option) any later version. 
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU General Public License for more details. 
+
+You should have received a copy of the GNU General Public License along with
+this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave,
+Cambridge, MA 02139, USA. 
+*/
+
+/* Functions which return responses */
+
+/* Generic question */
+char *question();
+char *b_word_resp();
+char *n_word_resp();
+char *because_resp();
+char *yes_resp();
+char *neg_resp();
+char *go_on();
+char *always_resp();
+char *alike_resp();
+char *fam_resp();
+char *family_resp();
+char *i_am_resp();
+char *sad1_word_resp();
+char *sad2_word_resp();
+char *command_resp();
+int randnum();
+char *you_resp();
+char *you_know();
+char *old_fact();
diff --git a/zpu/roadshow/roadshow/games/sumeria.bin b/zpu/roadshow/roadshow/games/sumeria.bin
new file mode 100644
index 0000000..04e5751
Binary files /dev/null and b/zpu/roadshow/roadshow/games/sumeria.bin differ
diff --git a/zpu/roadshow/roadshow/games/sumeria.c b/zpu/roadshow/roadshow/games/sumeria.c
new file mode 100644
index 0000000..7171adf
--- /dev/null
+++ b/zpu/roadshow/roadshow/games/sumeria.c
@@ -0,0 +1,444 @@
+/*    Govern ancient Sumeria.    Heavily modified by Mike Arnautov 1975.
+ *    Converted from Basic to PR1ME Fortran (mode 32R) MLA 1979.
+ *    Rev.19.1, GGR version 14 Oct 83. MLA
+ *    Converted to ANSI C December 2001. MLA
+ */
+
+#include <stdio.h>
+#include <time.h>
+#include <math.h>
+
+int year_term;
+int year_abs;
+int percent_starved;
+int dead_total;
+int starved;
+int population;
+
+char reply [160];
+
+void try_again (int reason)
+{
+   if (reason == 1)
+      puts ("For the extreme folly of soft - heartedness and");
+   if (reason)
+   {
+      printf ("%considering ", reason == 3 ? 'C' : 'c');
+      puts ("the mess you would leave the city in,");
+      puts ("you are hereby commanded to remain in office for");
+      puts ("another ten years. May your fate be a lesson and");
+      puts ("a warning for generations to come.");
+   }
+   else
+   {
+      puts ("Hamurabe, you are either a politico-economic genius");
+      puts ("or just a lucky bastard. There being but one way to");
+      puts ("settle the question, you are hereby requested to stay");
+      puts ("in office for another ten years.");
+   }
+   year_term = 0;
+   year_abs--;
+   percent_starved = starved * 100.0 / population;
+   dead_total = starved;
+}
+
+float rnd (void)
+{
+   return ((rand () % 1000) / 1000.0);
+}
+
+int iabs (int value)
+{
+   return ((value >= 0) ? value : -value);
+}
+
+void terminate (int abort)
+{
+   if (abort == 2)
+   {
+      puts ("For this extreme mismanagement you have been");
+      puts ("deposed, flayed alive and publicly beheaded.");
+      puts ("\nMay Ashtaroth preserve your Ka.\n");
+   }
+   else if (abort == 1)
+   {
+      puts ("\nHamurabe:  I find myself unable to fulfil your wish.");
+      puts ("You will have to find yourself another kingdom.");
+   }
+   if (abort != 2)
+      puts ("\nMay Baal be with you.\n");
+   exit (0);
+}
+   
+void think_again (char *what, int quantity)
+{
+   if (*what == 'l' || *what == 'g')
+      printf ("Hamurabe, think again. ");
+   if (*what == 'l')
+      printf ("You own %d acres of land.", quantity);
+   else if (*what == 'g')
+      printf ("You have only %d bushels of grain.", quantity);
+   else
+      printf ("But you only have %d people to tend the fields.", population);
+   puts (" Now then,");
+}
+int query (char *prompt)
+{
+   while (1)
+   {
+      int sign;
+      int value;
+      char * cptr;
+      
+      printf (prompt);
+      fgets (reply, sizeof (reply) - 1, stdin);
+      value = 0;
+      sign = 1;
+      cptr = reply;
+      while (*cptr == ' ' || *cptr == '\t') cptr++;
+      if (*cptr == '-')
+      {
+         cptr++;
+         sign = -1;
+      }
+      if (*cptr == 'q' || *cptr == 'Q')
+         terminate (1);
+      while (*cptr && *cptr != '\n')
+      {
+         if (*cptr >= '0' && *cptr <= '9')
+            value = 10 * value + *cptr - '0';
+         else if (*cptr == '.')
+            break;
+         else if (*cptr != '.')
+         {
+            sign = 0;
+            break;
+         }
+         cptr++;
+      }
+      if (sign)
+         return (sign * value);
+      puts ("Hamurabe, your command has not been understood!");
+   }   
+}
+
+int main ()
+{
+   int acreage;
+   int immigration;
+   int second_term;
+   int dead_total;
+   int stores;
+   int harvest;
+   int rat_food;
+   int yield;
+   int rounded_price;
+   int sell;
+   int buy;
+   int plant;
+   int food;
+   int transaction;
+   int rats;
+   int plague_deaths;
+   int survived;
+   int dead_rats;
+   int tmp_int;
+
+   float price;
+   float breadline;
+   float provisions;
+   float plague;
+   float acres_per_head;
+   float acres_per_init;
+   float stores_per_head;
+   float rats_ate;
+   float rat_log;
+   float percent_starved;
+   float tmp_float;
+   
+   printf ("[Sumeria (Primos) rev.19.1, GGR (MLA) version 14 Oct 83]\n");
+   puts ("[Conversion to ANSI C: MLA, Feb 2002]\n");
+   while (1)
+   {
+      printf ("Do you know how to play? ");
+      fgets (reply, sizeof(reply) - 1, stdin);
+      if (*reply == '\n') break;
+      *reply += (*reply < 'a') ? 'a' - 'A' : 0;
+      if (*reply == 'y') break;
+      if (*reply != 'n' && *reply != 'q') continue;
+      puts ("\nToo bad!\n");
+      break;
+   }
+  
+   srand (time (NULL));
+   *(reply + sizeof (reply) - 1) = '\0';
+   
+   puts ("Try your hand at governing ancient Sumeria");
+   puts ("for a ten year term of office.");
+
+   second_term = 0;
+   dead_total = 0;
+   percent_starved = 0;
+   year_term = 0;
+   year_abs = 0;
+   acres_per_init = 10;
+   population = 100;
+   stores = 2800;
+   harvest = 3000;
+   rat_food = 200;
+   yield = 3;
+   acreage = 1000;
+   immigration = 5;
+   transaction = 0;
+   price = 18 + 6 * rnd ();
+   breadline = 19 + 4 * rnd ();
+   provisions = breadline;
+   rats = 1000;
+   rat_log = 3;
+   plague = rnd () / 2;
+   starved = 0;
+
+year_term = year_abs = 9;
+   while (1)
+   {
+      
+      while (1)
+      {
+         year_term++;
+         year_abs++;
+         putchar ('\n');
+         acres_per_head = ((float) acreage) / population;
+         stores_per_head = ((float) stores) /population;
+         puts ("Hamurabe: I beg to report to you,");
+         printf ("In year %d, ", year_abs);
+         if (starved > 0)
+            printf ("%ld", starved);
+         else
+            printf ("no");
+         printf (" %s starved, %ld came to the city.\n", 
+            starved <= 1 ? "person" : "people", immigration);
+         if (plague >= 0.85)
+            printf ("A horrible plague struck! %d people died.\n", 
+               plague_deaths);
+         printf ("Population is now %ld.\n", population);
+         printf ("The city owns %ld acres.\n", acreage);
+         printf ("You harvested %ld bushels per acre.\n", yield);
+         printf ("Rats ate %ld bushels.\n", rat_food);
+         printf ("You now have %ld bushels in store.\n\n", stores);
+
+         if (year_term == 11) 
+            break;
+         rounded_price = price + 0.5;
+         printf ("Land is trading at %ld bushels per acre.\n\n", rounded_price);
+
+         while (1)
+         {
+            buy = query ("How many acres do you wish to buy? ");
+            if (rounded_price * buy <= stores)
+               break;
+            think_again ("grain", stores);
+         }
+         if (buy > 0)
+         {
+            acreage += + buy;
+            stores -= rounded_price * buy;
+            transaction = buy;
+         }
+         else
+         {
+            while (1)
+            {
+               sell = query ("How many acres do you wish to sell? ");
+               if (sell <= acreage)
+                  break;
+               think_again ("land", acreage);
+            }
+            acreage -= sell;
+            stores += rounded_price * sell;
+            transaction = -sell;
+         }
+      
+         putchar ('\n');
+         while (1)
+         {
+            food = query ("How many bushels do you wish to feed your people? ");
+            if (food <= stores)
+               break;
+            think_again ("grain", stores);
+         }
+         stores -= food;
+         putchar ('\n');
+         while (1)
+         {
+            plant = query ("How many acres do you wish to plant with seed? ");
+            if (plant <= acreage && plant <= 2 * stores && 
+                plant <= 10 * population)
+               break;
+            if (plant > acreage)
+               think_again ("land", acreage);
+            else if (plant > 2 * stores)
+               think_again ("grain", stores);
+            else
+               think_again ("people", population);
+         }
+   
+         stores -= plant / 2;
+         yield = 4 * rnd() + 1.65;
+         harvest = plant * yield;
+         rat_food = 0;
+         rats_ate = stores * (rat_log - 2.2) / 3.6;
+         dead_rats = rats - 4 * rats_ate;
+         rats = 3 * rats;
+         if (dead_rats > 0) rats = rats - dead_rats;
+   
+         if (plague >= 0.3) 
+         {
+            if (plague >= 0.85)
+            {
+               if (plague > 1) plague = 1;
+               rats = 500 + 5000 * (plague - 0.7);
+            }
+            else
+               rats *= 1.225 - 0.75 * plague;
+         }
+   
+         if (rats < 500)
+            rats = 500;
+         rat_food = rats / 4;
+         if (rats_ate < rat_food)
+            rat_food = rats_ate;
+         rat_food *= 7;
+         if (rat_food <= 20) 
+            rat_food = 20 + 30 * rnd();
+         stores += harvest - rat_food;
+         rat_log = log10 (1.0 * rats);
+         if (stores + stores <= harvest)
+         {
+            rat_food = harvest * (1 + rnd()) / 4.0;
+            stores = harvest - rat_food;
+         }
+   
+         tmp_int = 100 + iabs (100 - population);
+         immigration = tmp_int * ((acres_per_head + 
+            stores_per_head - 36) / 250.0 + 
+               (provisions - breadline + 2.5) / 40) + .5;
+         if (immigration <= 0) 
+            immigration = 5 * rnd() + 1;
+         survived = food / breadline;
+         provisions = (1.0 * food) / population;
+         plague = (2 * rnd() + rat_log - 3) / 3.0;
+         if (population < survived) 
+            survived = population;
+         else
+         {
+            starved = population - survived;
+            if (starved >= 0.45 * population)
+            {
+               printf ("\nYou starved %d people in one year!\n", starved);
+               terminate (2);
+            }
+            percent_starved = ((year_term - 1) * percent_starved + 
+               100.0 * starved / population) / year_term;
+            population = survived;
+            dead_total += starved;
+         }
+         population += immigration;
+         price = (price + 15 + (stores_per_head - acres_per_head) / 3) / 2 + 
+            transaction / 50 + 3 * rnd() - 2;
+         if (price <1.0) price = 1.0;
+         if (plague >= 0.85)
+         {
+            plague_deaths = population * (0.429 * plague - 0.164);
+            population -= plague_deaths;
+         }
+      }
+   
+      printf ("In your ten year term of office %d people starved.\n",
+         dead_total);
+      printf ("You started with %0.2f acres per person and ended\n",
+         acres_per_init);
+      acres_per_head = (1.0 * acreage) / population;
+      acres_per_init = acres_per_head;
+      printf ("with %0.2f acres per person.\n\n", acres_per_head);
+   
+      tmp_float = 10 * acres_per_head / 3;
+      if (percent_starved > 25)
+         terminate (2);
+      if (percent_starved <= 7)
+      {
+         try_again (1);
+         continue;
+      }
+      if (tmp_float < 7) 
+         terminate (2);
+      if (tmp_float > 10)
+      {
+         puts ("Your heavy handed performance smacks of Nabuchodonoser");
+         puts ("and Asurbanipal II. The surviving populace hates your");
+         puts ("guts and your eventual assasination is just a matter of");
+         puts ("time.");
+         terminate (0);
+      }
+      puts ("Consequently you have been deposed and disgraced");
+      puts ("and only avoided a public punishment because");
+      puts ("of mitigating circumstances. While it may be");
+      puts ("admitted in private that you had a rotten deal");
+      tmp_int = 3 * rnd();
+      if (tmp_int == 0)
+         puts ("try explaining that to a mob looking for scape-goats.");
+      if (tmp_int == 1)
+         puts ("history is not interested in such petty excuses.");
+      if (tmp_int == 2)
+      {
+         puts ("you should have considered such occupational hazards");
+         puts ("before applying for the job.");
+      }
+      terminate (0);
+      
+      if (acres_per_head < 7)
+      {
+         try_again (1);
+         continue;
+      }
+      if (acres_per_head < 9)
+      {
+         puts ("Your performance has been satisfactory and, in the");
+         puts ("perspective of history, actually quite good.");
+         if (rnd() >= 0.5) 
+         {
+            puts ("You may not be exactly popular, but given a good");
+            puts ("body-guard there is nothing to be really worried about.");
+         }
+         else
+         {
+            puts ("While not exactly loved, you are at least respected.");
+            puts ("What more can a realistic ruler ask for?");
+         }
+      }
+      else if (second_term == 0)
+
+      if (second_term == 0)
+      {
+         if (stores <= 10 * population)
+         {
+            try_again (3);
+            continue;
+         }
+         second_term = 1;
+         try_again (0);
+         continue;
+      }
+      else
+      {
+         puts ("Hamurabe, your name will be remembered through the");
+         puts ("ages to come with admiration and respect.\n");
+         puts ("(So you did get away with it you lucky sod!)");
+      }
+      if (stores > 10 * population)
+         terminate (0);
+      puts ("\n                            HOWEVER\n\n");
+      second_term = 0;
+      try_again (2);
+      continue;
+   }
+}
diff --git a/zpu/roadshow/roadshow/games/sumeria.zpu b/zpu/roadshow/roadshow/games/sumeria.zpu
new file mode 100644
index 0000000..0e6b41d
Binary files /dev/null and b/zpu/roadshow/roadshow/games/sumeria.zpu differ
diff --git a/zpu/roadshow/roadshow/helloworld/build.sh b/zpu/roadshow/roadshow/helloworld/build.sh
new file mode 100644
index 0000000..8069e36
--- /dev/null
+++ b/zpu/roadshow/roadshow/helloworld/build.sh
@@ -0,0 +1,6 @@
+zpu-elf-gcc test.c -o test.elf -phi 
+zpu-elf-objcopy -O binary test.elf test.bin
+sh ../build/makefirmware.sh ../build/ic300.bit test.zpu test.bin
+
+
+
diff --git a/zpu/roadshow/roadshow/helloworld/test.bin b/zpu/roadshow/roadshow/helloworld/test.bin
new file mode 100644
index 0000000..540ccaf
Binary files /dev/null and b/zpu/roadshow/roadshow/helloworld/test.bin differ
diff --git a/zpu/roadshow/roadshow/helloworld/test.c b/zpu/roadshow/roadshow/helloworld/test.c
new file mode 100644
index 0000000..8c33640
--- /dev/null
+++ b/zpu/roadshow/roadshow/helloworld/test.c
@@ -0,0 +1,11 @@
+int main(int argc, char **argv)
+{
+	for (;;)
+	{
+		int c;
+		printf("Hello world!\n");
+		printf("Press any key!\n");
+		c=inbyte();
+		printf("You pressed (%02x) '%c'\n", c, c);
+	}
+}
diff --git a/zpu/roadshow/roadshow/helloworld/test.elf b/zpu/roadshow/roadshow/helloworld/test.elf
new file mode 100644
index 0000000..bc362ae
Binary files /dev/null and b/zpu/roadshow/roadshow/helloworld/test.elf differ
diff --git a/zpu/roadshow/roadshow/helloworld/test.zpu b/zpu/roadshow/roadshow/helloworld/test.zpu
new file mode 100644
index 0000000..1bee302
Binary files /dev/null and b/zpu/roadshow/roadshow/helloworld/test.zpu differ
diff --git a/zpu/roadshow/roadshow/hwtest/build.sh b/zpu/roadshow/roadshow/hwtest/build.sh
new file mode 100644
index 0000000..115b24a
--- /dev/null
+++ b/zpu/roadshow/roadshow/hwtest/build.sh
@@ -0,0 +1,6 @@
+zpu-elf-gcc -nostdlib test.S -o test.elf 
+zpu-elf-objcopy -O binary test.elf test.bin
+sh makefirmware.sh ic300.bit test.zpu test.bin
+
+
+
diff --git a/zpu/roadshow/roadshow/hwtest/test.S b/zpu/roadshow/roadshow/hwtest/test.S
new file mode 100644
index 0000000..ac13be3
--- /dev/null
+++ b/zpu/roadshow/roadshow/hwtest/test.S
@@ -0,0 +1,19 @@
+_loop:
+	im 0x5a 		;  write Z to UART
+	nop
+	im 0x080a000c
+	store
+	; increaase counter
+	im _test
+	load
+	im 1
+	add
+	im _test
+	store
+	
+	
+	im _loop
+	poppc 			;  loop
+	
+	.align 4
+_test: .long 1
diff --git a/zpu/roadshow/roadshow/hwtest/test.bin b/zpu/roadshow/roadshow/hwtest/test.bin
new file mode 100644
index 0000000..4b593ee
Binary files /dev/null and b/zpu/roadshow/roadshow/hwtest/test.bin differ
diff --git a/zpu/roadshow/roadshow/hwtest/test.elf b/zpu/roadshow/roadshow/hwtest/test.elf
new file mode 100644
index 0000000..a2ccbc1
Binary files /dev/null and b/zpu/roadshow/roadshow/hwtest/test.elf differ
diff --git a/zpu/roadshow/roadshow/hwtest/test.zpu b/zpu/roadshow/roadshow/hwtest/test.zpu
new file mode 100644
index 0000000..7d8da42
Binary files /dev/null and b/zpu/roadshow/roadshow/hwtest/test.zpu differ
diff --git a/zpu/roadshow/roadshow/images/bootloader.phi b/zpu/roadshow/roadshow/images/bootloader.phi
new file mode 100644
index 0000000..a0a1918
Binary files /dev/null and b/zpu/roadshow/roadshow/images/bootloader.phi differ
diff --git a/zpu/roadshow/roadshow/images/dhrystone.zpu b/zpu/roadshow/roadshow/images/dhrystone.zpu
new file mode 100644
index 0000000..e37e59f
Binary files /dev/null and b/zpu/roadshow/roadshow/images/dhrystone.zpu differ
diff --git a/zpu/roadshow/roadshow/images/eliza.zpu b/zpu/roadshow/roadshow/images/eliza.zpu
new file mode 100644
index 0000000..d916270
Binary files /dev/null and b/zpu/roadshow/roadshow/images/eliza.zpu differ
diff --git a/zpu/roadshow/roadshow/images/ic300.bit b/zpu/roadshow/roadshow/images/ic300.bit
new file mode 100644
index 0000000..cbbc2b6
Binary files /dev/null and b/zpu/roadshow/roadshow/images/ic300.bit differ
diff --git a/zpu/roadshow/roadshow/images/net_test.zpu b/zpu/roadshow/roadshow/images/net_test.zpu
new file mode 100644
index 0000000..9083cad
Binary files /dev/null and b/zpu/roadshow/roadshow/images/net_test.zpu differ
diff --git a/zpu/roadshow/roadshow/images/sumeria.zpu b/zpu/roadshow/roadshow/images/sumeria.zpu
new file mode 100644
index 0000000..0e6b41d
Binary files /dev/null and b/zpu/roadshow/roadshow/images/sumeria.zpu differ
diff --git a/zpu/roadshow/roadshow/iss/index.html b/zpu/roadshow/roadshow/iss/index.html
new file mode 100644
index 0000000..0b91a6a
--- /dev/null
+++ b/zpu/roadshow/roadshow/iss/index.html
@@ -0,0 +1,14 @@
+<html>
+<body>
+<h1>ISS test</h1>
+<ol>
+<li>Launch ISS<br>
+java -Xmx512m -cp simulator.jar com.zylin.zpu.simulator.SimApp 4444 false
+<li>Launch debugger<br>
+zpu-elf-gdb hello.elf<br>
+<li>Connect to ISS<br>
+target remote localhost:4444
+</ol>
+
+</body>
+</html>
diff --git a/zpu/roadshow/roadshow/iss/simulator.jar b/zpu/roadshow/roadshow/iss/simulator.jar
new file mode 100644
index 0000000..8cf63a8
Binary files /dev/null and b/zpu/roadshow/roadshow/iss/simulator.jar differ
diff --git a/zpu/roadshow/roadshow/net_test/.cvsignore b/zpu/roadshow/roadshow/net_test/.cvsignore
new file mode 100644
index 0000000..66dac94
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/.cvsignore
@@ -0,0 +1,8 @@
+output
+all.txt
+dis.txt
+gmon.out
+ll.txt
+prof.txt
+net_test.txt
+gmon.sum
diff --git a/zpu/roadshow/roadshow/net_test/http_pages.c b/zpu/roadshow/roadshow/net_test/http_pages.c
new file mode 100644
index 0000000..437dad8
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/http_pages.c
@@ -0,0 +1,206 @@
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_if.h>
+#include <pkgconf/system.h>
+#include <pkgconf/isoinfra.h>
+#include <pkgconf/net.h>
+#include <pkgconf/httpd.h>
+#include <cyg/httpd/httpd.h>
+#include <pkgconf/kernel.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <string.h>
+
+static cyg_bool isUnsignedHex(char *string)
+{
+	int i = 0;
+	for(i = 0; string[i] != '\0'; i++)
+		if(!(	('0' <= string[i] && string[i] <= '9') ||
+				('a' <= string[i] && string[i] <= 'f') ||
+				('A' <= string[i] && string[i] <= 'F') ))
+			return 0;
+	return 1;
+}
+
+static cyg_bool net_test_mac_handler(FILE *client, char *filename, char *formdata, void *arg)
+{
+	char error_string[50]; 
+
+	error_string[0] = '\0';
+
+    if( formdata != NULL )
+    {
+		char *formlist[1];
+		char *mac_string = NULL;
+        /* Parse the data */
+        cyg_formdata_parse( formdata, formlist, 1 );
+        mac_string = cyg_formlist_find( formlist, "mac");
+        if(mac_string != NULL)
+        {
+  
+        	if(!isUnsignedHex(mac_string))
+        	{
+        		sprintf(error_string, "Please enter digits between 0-9 and a-f");
+        	}
+        	else if(strlen(mac_string) != 12)
+        	{
+        		sprintf(error_string, "Please enter a 12 digit MAC address");
+        	}
+        	else
+        	{
+        		char temp = '\0';
+        		int fd = -1;
+        		cyg_uint8 mac_addr[6];
+        		error_string[0] = '\0';
+
+        		temp = mac_string[2];
+        		mac_string[2] = '\0';
+        		mac_addr[0] = strtol(mac_string, NULL, 16);
+				mac_string[2] = temp;
+				
+        		temp = mac_string[4];
+        		mac_string[4] = '\0';
+        		mac_addr[1] = strtol(mac_string, NULL, 16);
+				mac_string[4] = temp;
+
+        		temp = mac_string[6];
+        		mac_string[6] = '\0';
+        		mac_addr[2] = strtol(mac_string, NULL, 16);
+				mac_string[6] = temp;
+
+        		temp = mac_string[8];
+        		mac_string[8] = '\0';
+        		mac_addr[3] = strtol(mac_string, NULL, 16);
+				mac_string[8] = temp;
+
+        		temp = mac_string[10];
+        		mac_string[10] = '\0';
+        		mac_addr[4] = strtol(mac_string, NULL, 16);
+				mac_string[10] = temp;
+
+        		temp = mac_string[12];
+        		mac_string[12] = '\0';
+        		mac_addr[5] = strtol(mac_string, NULL, 16);
+				mac_string[12] = temp;
+				
+				/*write it to flash*/
+				fd = creat("/jffs2/mac", O_TRUNC | O_CREAT);
+				if(fd < 0)
+				{
+					sprintf(error_string, "<font color=red>%n %s</font>", errno, strerror(errno) );
+				}
+				else
+				{
+					write(fd, mac_addr, 6);
+					close(fd);
+					fd = -1;
+					//CYGACC_CALL_IF_RESET();
+				}
+			}
+		}
+	}
+    
+    html_begin(client);
+
+    html_head(client,"Changing MAC Address", "");
+    
+    html_body_begin(client,"");
+    {
+    	fputs(error_string, client);
+    	fputs("<br>\n", client);
+    	html_form_begin( client, "/mac", "" );
+    	{
+    		fputs( "Enter the new mac address in the format xxxxxxxxxxxx ", client );
+    		html_form_input( client, "mac", "mac", "", "");
+    	}
+    	html_form_end(client);
+    }
+    html_body_end(client);
+
+    html_end(client);
+    
+    return 1;
+}
+
+CYG_HTTPD_TABLE_ENTRY( net_test_mac,
+                       "/mac",
+                       net_test_mac_handler,
+                       NULL );
+                       
+
+static cyg_bool net_test_ip_handler(FILE *client, char *filename, char *formdata, void *arg)
+{
+	int fd = -1;
+	char error_string[50]; 
+	char error_string2[50];
+	
+	error_string[0] = '\0';
+	error_string2[0] = '\0';
+	if( formdata != NULL )
+    {
+		char *formlist[1];
+		char *ip_string = NULL;
+        /* Parse the data */
+        cyg_formdata_parse( formdata, formlist, 1 );
+        ip_string = cyg_formlist_find( formlist, "ip");
+        if(ip_string != NULL)
+        {
+        	/*write it to flash*/
+			fd = creat("/jffs2/ip", O_TRUNC | O_CREAT);
+			if(fd < 0)
+			{
+				sprintf(error_string, "<font color=red>%n %s</font>", errno, strerror(errno) );
+			}
+			else
+			{
+				write(fd, ip_string, strlen(ip_string));
+				close(fd);
+				fd = -1;
+			}
+        }
+    }
+	html_begin(client);
+
+	html_head(client,"Changing IP Address", "");
+
+	html_body_begin(client,"");
+	{
+		char value[81];
+		value[0] = '\0';
+		fd = open("/jffs2/ip", O_RDONLY);
+		if(fd < 0)
+		{
+			sprintf(error_string2, "<font color=red>%n %s</font>", errno, strerror(errno) );
+		}
+		else
+		{
+			int len = read(fd, value, 80);
+			value[len] = '\0';
+			close(fd);
+			fd = -1;
+		}
+		fputs(error_string, client);
+		fputs("<br>\n", client);
+		fputs(error_string2, client);
+		fputs("<br>\n", client);
+		html_form_begin( client, "/ip", "" );
+		{
+			fputs( "Enter the new address in the following order: IP_mask_broadcast_gateway_server ", client );
+			fputs("<br>\n", client);
+			html_form_input( client, "ip", "ip", value, "");
+		}
+		html_form_end(client);
+	}
+	html_body_end(client);
+
+	html_end(client);
+
+	return 1;
+}
+
+CYG_HTTPD_TABLE_ENTRY( net_test_ip,
+                       "/ip",
+                       net_test_ip_handler,
+                       NULL );
+
diff --git a/zpu/roadshow/roadshow/net_test/init.cpp b/zpu/roadshow/roadshow/net_test/init.cpp
new file mode 100644
index 0000000..b5805b2
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/init.cpp
@@ -0,0 +1,52 @@
+#include <pkgconf/system.h>
+#include <pkgconf/isoinfra.h>
+#include <cyg/infra/diag.h> 
+#include <cyg/io/file.h>
+
+#if 0
+externC int chdir(const char *);
+
+/* ================================================================= */
+/* Initialization object
+ */
+
+class NetTestInit
+{
+public:
+    NetTestInit();
+};
+
+/* ----------------------------------------------------------------- */
+/* Static initialization object instance. The constructor is
+ * prioritized to run after any filesystem constructors.
+ */
+static NetTestInit netTestInitializer CYGBLD_ATTRIB_INIT_PRI(CYG_INIT_IO_FS + 1);
+
+/* ----------------------------------------------------------------- */
+/* Constructor, mounts the file system
+ */
+
+NetTestInit::NetTestInit()
+{
+	int err = 0;
+	err = mount( "/dev/flash1", "/jffs2", "jffs2" );
+	if(err < 0)
+	{
+		diag_printf("unable to mount jffs\n");
+	}
+	else
+	{
+		diag_printf("mounted jffs\n");
+	}
+	err = mount( "", "/ramfs", "ramfs" );
+	if(err < 0)
+	{
+		diag_printf("unable to mount ramfs\n");
+	}
+	else
+	{
+		diag_printf("mounted ramfs\n");
+	}
+	chdir( "/ramfs" );
+}
+#endif
diff --git a/zpu/roadshow/roadshow/net_test/makefile b/zpu/roadshow/roadshow/net_test/makefile
new file mode 100644
index 0000000..877afab
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/makefile
@@ -0,0 +1,41 @@
+PROJECTNAME = net_test
+OUT= output
+ECOS_DIR=$(OUT)/ecos
+INSTALL_DIR=$(ECOS_DIR)/install
+
+.symbolic: all clean  ecos
+
+all: ecos app 	
+
+
+
+clean:
+	rm -rf $(OUT)/*
+
+$(OUT):
+	mkdir $(OUT)
+
+$(ECOS_DIR)/ecos.ecc $(INSTALL_DIR)/include/pkgconf/ecos.mak:
+	mkdir -p $(ECOS_DIR)
+	cd $(ECOS_DIR) && ecosconfig new zpuetherphi minimal
+	cd $(ECOS_DIR) && ecosconfig import ../../$(PROJECTNAME).ecm
+	cd $(ECOS_DIR) && ecosconfig tree
+	cd $(ECOS_DIR) && make -s headers
+	
+$(OUT)/ecostree: $(ECOS_DIR)/ecos.ecc
+	cd $(ECOS_DIR) && ecosconfig tree
+	echo >$(OUT)/ecostree
+
+ecos   $(INSTALL_DIR)/lib/libtarget.a $(INSTALL_DIR)/lib/vectors.o: $(OUT)/ecostree 
+	cd $(ECOS_DIR) && make -s
+
+app: 
+	make -f $(INSTALL_DIR)/include/pkgconf/ecos.mak -f makefile $(OUT)/$(PROJECTNAME).bin
+
+$(OUT)/$(PROJECTNAME).bin: *.c makefile 
+	zpu-elf-gcc -I$(INSTALL_DIR)/include $(ECOS_GLOBAL_CFLAGS) $(ECOS_GLOBAL_LDFLAGS)  -L$(INSTALL_DIR)/lib *.c* -o $(OUT)/$(PROJECTNAME).elf  -Wl,-Map,$(OUT)/$(PROJECTNAME).map -nostartfiles -nostdlib -Ttarget.ld   -lstdc++  -lsupc++ 
+	zpu-elf-objcopy -O binary $(OUT)/$(PROJECTNAME).elf $(OUT)/$(PROJECTNAME).bin
+	sh ../build/makefirmware.sh $(OUT)/$(PROJECTNAME).bin $(OUT)/$(PROJECTNAME).zpu 
+	zpu-elf-size $(OUT)/$(PROJECTNAME).elf
+
+	
\ No newline at end of file
diff --git a/zpu/roadshow/roadshow/net_test/net_test.ecm b/zpu/roadshow/roadshow/net_test/net_test.ecm
new file mode 100644
index 0000000..5b32991
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/net_test.ecm
@@ -0,0 +1,237 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    zpuetherphi ;
+    template    default ;
+    package -hardware CYGPKG_HAL_ZYLIN current ;
+    package -hardware CYGPKG_HAL_ZYLIN_ZPU current ;
+    package -hardware CYGPKG_HAL_ZYLIN_ZPU_PHI current ;
+    package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+    package -hardware CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC current ;
+    package -hardware CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_IO current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_ERROR current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_IO_SERIAL current ;
+    package -template CYGPKG_KERNEL current ;
+    package -template CYGPKG_MEMALLOC current ;
+    package -template CYGPKG_LIBC current ;
+    package -template CYGPKG_LIBC_I18N current ;
+    package -template CYGPKG_LIBC_SETJMP current ;
+    package -template CYGPKG_LIBC_SIGNALS current ;
+    package -template CYGPKG_LIBC_STARTUP current ;
+    package -template CYGPKG_LIBC_STDIO current ;
+    package -template CYGPKG_LIBC_STDLIB current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_LIBC_TIME current ;
+    package -template CYGPKG_LIBM current ;
+    package -template CYGPKG_IO_WALLCLOCK current ;
+    package CYGPKG_NET_FREEBSD_STACK current ;
+    package CYGPKG_IO_FILEIO current ;
+    package CYGPKG_NET current ;
+    package CYGPKG_HTTPD current ;
+};
+
+cdl_component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE {
+    inferred_value 0
+};
+
+cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_TxNUM {
+    user_value 4
+};
+
+cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_RxNUM {
+    user_value 32
+};
+
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+    inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+    inferred_value 1 <cyg/libc/i18n/ctype.inl>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+    inferred_value 1 <cyg/error/codes.h>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+    inferred_value 1 <cyg/error/errno.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FILETYPES_HEADER {
+    inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER {
+    inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FILEOPS_HEADER {
+    inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FILEACCESS_HEADER {
+    inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER {
+    inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_CHAR_IO_HEADER {
+    inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_DIRECT_IO_HEADER {
+    inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_FILEPOS_HEADER {
+    inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDIO_ERROR_HEADER {
+    inferred_value 1 <cyg/libc/stdio/stdio.h>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
+    inferred_value 1 <cyg/libc/stdlib/atox.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
+    inferred_value 1 <cyg/libc/stdlib/abs.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
+    inferred_value 1 <cyg/libc/stdlib/div.inl>
+};
+
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+    inferred_value 1 <cyg/error/strerror.h>
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_FNMATCH_HEADER {
+    inferred_value 1 <cyg/fileio/fnmatch.h>
+};
+
+cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER {
+    inferred_value 1 <cyg/libc/time/time.h>
+};
+
+cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/time/time.h>
+};
+
+cdl_option CYGBLD_ISO_SIGNAL_NUMBERS_HEADER {
+    inferred_value 1 <cyg/libc/signals/signal.h>
+};
+
+cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER {
+    inferred_value 1 <cyg/libc/signals/signal.h>
+};
+
+cdl_option CYGBLD_ISO_SETJMP_HEADER {
+    inferred_value 1 <cyg/libc/setjmp/setjmp.h>
+};
+
+cdl_option CYGBLD_ISO_DIRENT_HEADER {
+    inferred_value 1 <cyg/fileio/dirent.h>
+};
+
+cdl_option CYGBLD_ISO_BSDTYPES_HEADER {
+    inferred_value 1 <sys/bsdtypes.h>
+};
+
+cdl_option CYGBLD_ISO_OPEN_MAX_HEADER {
+    inferred_value 1 <cyg/fileio/limits.h>
+};
+
+cdl_option CYGBLD_ISO_NAME_MAX_HEADER {
+    inferred_value 1 <cyg/fileio/limits.h>
+};
+
+cdl_option CYGBLD_ISO_NETDB_PROTO_HEADER {
+    inferred_value 1 <net/netdb.h>
+};
+
+cdl_option CYGBLD_ISO_NETDB_SERV_HEADER {
+    inferred_value 1 <net/netdb.h>
+};
+
+cdl_option CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_LIBC_MAIN_DEFAULT_STACK_SIZE {
+    user_value 16384
+};
+
+cdl_option CYGPKG_NET_TFTPD_THREAD_STACK_SIZE {
+    user_value (CYGNUM_HAL_STACK_SIZE_TYPICAL+(8192))
+};
+
+cdl_component CYGPKG_NET_DHCP {
+    user_value 0
+};
+
+cdl_component CYGHWR_NET_DRIVER_ETH0_MANUAL {
+    inferred_value 0
+};
+
+cdl_component CYGHWR_NET_DRIVER_ETH0_BOOTP {
+    user_value 0
+};
+
+cdl_component CYGHWR_NET_DRIVER_ETH0_ADDRS {
+    user_value 1
+};
+
+cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_IP {
+    user_value 10.0.0.57
+};
+
+cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_BROADCAST {
+    user_value 10.0.0.255
+};
+
+cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_GATEWAY {
+    user_value 10.0.0.1
+};
+
+cdl_option CYGHWR_NET_DRIVER_ETH0_ADDRS_SERVER {
+    user_value 10.0.0.58
+};
+
+
diff --git a/zpu/roadshow/roadshow/net_test/ping_test.c b/zpu/roadshow/roadshow/net_test/ping_test.c
new file mode 100644
index 0000000..7a3ce59
--- /dev/null
+++ b/zpu/roadshow/roadshow/net_test/ping_test.c
@@ -0,0 +1,585 @@
+//==========================================================================
+//
+//      tests/ping_test.c
+//
+//      Simple test of PING (ICMP) and networking support
+//
+//==========================================================================
+//####BSDCOPYRIGHTBEGIN####
+//
+// -------------------------------------------
+//
+// Portions of this software may have been derived from OpenBSD or other sources,
+// and are covered by the appropriate copyright disclaimers included herein.
+//
+// -------------------------------------------
+//
+//####BSDCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas, andrew.lunn@ascom.ch
+// Date:         2000-01-10
+// Purpose:      
+// Description:  
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// PING test code
+
+#include <network.h>
+#include <cyg/hal/hal_if.h>
+#include <stdio.h>
+#include <cyg/fileio/fileio.h>
+#include <unistd.h>
+#include <pkgconf/system.h>
+#include <pkgconf/net.h>
+#include <cyg/io/file.h>
+#include <cyg/infra/testcase.h>
+#include CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG
+
+#ifdef CYGBLD_DEVS_ETH_DEVICE_H    // Get the device config if it exists
+#include CYGBLD_DEVS_ETH_DEVICE_H  // May provide CYGTST_DEVS_ETH_TEST_NET_REALTIME
+#endif
+
+#ifdef CYGPKG_NET_TESTS_USE_RT_TEST_HARNESS // do we use the rt test?
+# ifdef CYGTST_DEVS_ETH_TEST_NET_REALTIME // Get the test ancilla if it exists
+#  include CYGTST_DEVS_ETH_TEST_NET_REALTIME
+# endif
+#endif
+
+// Fill in the blanks if necessary
+#ifndef TNR_OFF
+# define TNR_OFF()
+#endif
+#ifndef TNR_ON
+# define TNR_ON()
+#endif
+#ifndef TNR_INIT
+# define TNR_INIT()
+#endif
+#ifndef TNR_PRINT_ACTIVITY
+# define TNR_PRINT_ACTIVITY()
+#endif
+
+#include <cyg/io/io.h>
+
+#include <network.h>
+#include <tftp_support.h>
+
+#include <sys/types.h> //directory
+#include <dirent.h>
+
+//for serial
+cyg_io_handle_t handle; 
+extern int               inet_aton __P((const char *, struct in_addr *));
+#ifndef CYGPKG_LIBC_STDIO
+#define perror(s) diag_printf(#s ": %s\n", strerror(errno))
+#endif
+#define SHOW_RESULT( _fn, _res ) \
+diag_printf("<FAIL>: " #_fn "() returned %ld %s\n", (long)_res, _res<0?strerror(errno):"");
+
+/*
+#define STACK_SIZE (CYGNUM_HAL_STACK_SIZE_TYPICAL + 0x1000)
+static char stack[STACK_SIZE];
+static cyg_thread thread_data;
+static cyg_handle_t thread_handle;
+*/
+
+
+/* NB!!! must be divisible by 8 */
+#define NUM_PINGS 	8192
+#define MAX_PACKET 	16384
+#define MIN_PACKET  64
+#define MAX_SEND   	(IP_MAXPACKET - 100)
+
+#define PACKET_ADD  ((MAX_SEND - MIN_PACKET)/NUM_PINGS)
+#define nPACKET_ADD  1 
+
+static unsigned char pkt1[MAX_PACKET], pkt2[MAX_PACKET];
+
+#define UNIQUEID 0x1234
+/* we write this much to jffs2 in each go.
+ * 
+ * DANGER!!! JFFS2 memory consumption is proportional to the # of write operations,
+ * so reducing this size will make the bootloader run out of memory.
+ */
+#define IOSIZE  16384  
+void
+pexit(char *s)
+{
+    CYG_TEST_FAIL_FINISH(s);
+}
+
+// Compute INET checksum
+int
+inet_cksum(u_short *addr, int len)
+{
+    register int nleft = len;
+    register u_short *w = addr;
+    register u_short answer;
+    register u_int sum = 0;
+    u_short odd_byte = 0;
+
+    /*
+     *  Our algorithm is simple, using a 32 bit accumulator (sum),
+     *  we add sequential 16 bit words to it, and at the end, fold
+     *  back all the carry bits from the top 16 bits into the lower
+     *  16 bits.
+     */
+    while( nleft > 1 )  {
+    	cyg_uint32 t=*w++;
+        sum += t;
+        nleft -= 2;
+    }
+
+    /* mop up an odd byte, if necessary */
+    if( nleft == 1 ) {
+        *(u_char *)(&odd_byte) = *(u_char *)w;
+        sum += odd_byte;
+    }
+
+    /*
+     * add back carry outs from top 16 bits to low 16 bits
+     */
+    sum = (sum >> 16) + (sum & 0x0000ffff); /* add hi 16 to low 16 */
+    sum += (sum >> 16);                     /* add carry */
+    answer = ~sum;                          /* truncate to 16 bits */
+    return (answer);
+}
+
+static int
+show_icmp(unsigned char *pkt, int len, 
+          struct sockaddr_in *from, struct sockaddr_in *to)
+{
+	char buffer[100];
+	cyg_uint32 buffer_index = 0;
+    cyg_tick_count_t tp, tv;
+    struct ip *ip;
+    struct icmp *icmp;
+    tv = cyg_current_time();
+    ip = (struct ip *)pkt;
+    if ((len < (int)sizeof(*ip)) || ip->ip_v != IPVERSION) 
+    {
+    	buffer[0] = '\0';
+        snprintf(buffer, 99, "%s: Short packet or not IP! - Len: %d, Version: %d\r\n", 
+                    inet_ntoa(from->sin_addr), len, ip->ip_v);
+        buffer_index = strlen(buffer);
+        cyg_io_write(handle, buffer, &buffer_index);
+        return 0;
+    }
+    icmp = (struct icmp *)(pkt + sizeof(*ip));
+    len -= (sizeof(*ip) + 8);
+    tp = *((cyg_tick_count_t *)&icmp->icmp_data);
+    if (icmp->icmp_type != ICMP_ECHOREPLY) 
+    {
+    	buffer[0] = '\0';
+        snprintf(buffer, 99, "%s: Invalid ICMP - type: %d\r\n", 
+                    inet_ntoa(from->sin_addr), icmp->icmp_type);
+        buffer_index = strlen(buffer);
+        cyg_io_write(handle, buffer, &buffer_index);
+        return 0;
+    }
+    if (icmp->icmp_id != UNIQUEID) 
+    {
+    	buffer[0] = '\0';
+        snprintf(buffer, 99, "%s: ICMP received for wrong id - sent: %x, recvd: %x\r\n", 
+                    inet_ntoa(from->sin_addr), UNIQUEID, icmp->icmp_id);
+        buffer_index = strlen(buffer);
+        cyg_io_write(handle, buffer, &buffer_index);
+    }
+//    printf("%d bytes from %s: ", len, inet_ntoa(from->sin_addr));
+//    printf("icmp_seq=%d", icmp->icmp_seq);
+    int t=(int)(tv-tp);
+	t*=10;
+//    printf(", time=%d ms\n", t);
+    return (from->sin_addr.s_addr == to->sin_addr.s_addr);
+}
+
+static void
+ping_host(int s, struct sockaddr_in *host)
+{
+	char buffer[100];
+	cyg_uint32 buffer_index = 0;
+    struct icmp *icmp = (struct icmp *)pkt1;
+    int icmp_len = MIN_PACKET;
+    int seq = 0, ok_recv = 0, bogus_recv = 0;
+    cyg_tick_count_t *tp;
+    long *dp;
+    struct sockaddr_in from;
+    int len;
+    socklen_t fromlen;
+	
+    ok_recv = 0;
+    bogus_recv = 0;
+    snprintf(buffer, 99, "PING server %s\r\n", inet_ntoa(host->sin_addr));
+    buffer_index = strlen(buffer);
+    cyg_io_write(handle, buffer, &buffer_index);
+    
+    
+    for (seq = 0;  seq < NUM_PINGS;  seq++, icmp_len += PACKET_ADD ) 
+    {
+    	cyg_thread_delay(50);
+        TNR_ON();
+        
+        memset(pkt1, 0, sizeof(pkt1)); // make sure we start each time w/same situation...
+        // Build ICMP packet
+        icmp->icmp_type = ICMP_ECHO;
+        icmp->icmp_code = 0;
+        icmp->icmp_cksum = 0;
+        icmp->icmp_seq = seq;
+        icmp->icmp_id = 0x1234;
+        // Set up ping data
+        tp = (cyg_tick_count_t *)&icmp->icmp_data;
+		memset(tp, 0xff, icmp_len); // try to fish out bit 1 force to 0.
+        *tp++ = cyg_current_time();
+        tp++;
+        dp = (long *)tp;
+
+        // Add checksum
+        icmp->icmp_cksum = inet_cksum( (u_short *)icmp, icmp_len+8);
+        // Send it off
+        if (sendto(s, icmp, icmp_len+8, 0, (struct sockaddr *)host, sizeof(*host)) < 0) {
+            TNR_OFF();
+            perror("sendto");
+            continue;
+        }
+        // Wait for a response
+        fromlen = sizeof(from);
+        len = recvfrom(s, pkt2, sizeof(pkt2), 0, (struct sockaddr *)&from, &fromlen);
+        TNR_OFF();
+        if (len < 0) {
+            perror("recvfrom");
+            inet_cksum( (u_short *)icmp, icmp_len+8);
+            icmp_len = MIN_PACKET - PACKET_ADD; // just in case - long routes
+        } else {
+            if (show_icmp(pkt2, len, &from, host)) {
+                ok_recv++;
+            } else {
+                bogus_recv++;
+            }
+        }
+    }
+    TNR_OFF();
+    snprintf(buffer, 99, "Sent %d packets, received %d OK, %d bad\r\n", NUM_PINGS, ok_recv, bogus_recv);
+    buffer_index = strlen(buffer);
+    cyg_io_write(handle, buffer, &buffer_index);
+}
+
+#ifdef CYGPKG_PROFILE_GPROF
+#include <cyg/profile/profile.h>
+
+extern char _stext, _etext;  // Defined by the linker
+
+static void
+start_profile(void)
+{
+    // This starts up the system-wide profiling, gathering
+    // profile information on all of the code, with a 16 byte
+    // "bucket" size, at a rate of 100us/profile hit.
+    // Note: a bucket size of 16 will give pretty good function
+    //       resolution.  Much smaller and the buffer becomes
+    //       much too large for very little gain.
+    // Note: a timer period of 100us is also a reasonable
+    //       compromise.  Any smaller and the overhead of 
+    //       handling the timter (profile) interrupt could
+    //       swamp the system.  A fast processor might get
+    //       by with a smaller value, but a slow one could
+    //       even be swamped by this value.  If the value is
+    //       too large, the usefulness of the profile is reduced.
+    
+    // no more interrupts than 1/10ms.
+    //profile_on(&_stext, &_etext, 16, 10000); // DRAM
+    //profile_on((void *)0x2000000, (void *)0x4000000, 32, 10000); // DRAM
+    //profile_on((void *)0, (void *)0x40000, 16, 10000); // SRAM
+    //profile_on(0, &_etext, 32, 10000); // SRAM & DRAM
+}
+#endif
+
+static void
+ping_test(struct bootp *bp)
+{
+    struct protoent *p;
+    struct timeval tv;
+    struct sockaddr_in host;
+    int s;
+    
+	p = getprotobyname("icmp");
+    if (p == NULL) 
+    {
+        pexit("getprotobyname");
+        return;
+    }
+    s = socket(AF_INET, SOCK_RAW, p->p_proto);
+    if (s < 0) {
+        pexit("socket");
+        return;
+    }
+    tv.tv_sec = 4;
+    tv.tv_usec = 0;
+    setsockopt(s, SOL_SOCKET, SO_RCVTIMEO, &tv, sizeof(tv));
+
+	// default is 8192 bytes which is not big enough for our ping tests...
+    int sndsize=70000;
+    setsockopt(s, SOL_SOCKET, SO_RCVBUF, (char *)&sndsize,
+                                 (int)sizeof(sndsize));
+    sndsize=70000;
+    setsockopt(s, SOL_SOCKET, SO_SNDBUF, (char *)&sndsize,
+                                 (int)sizeof(sndsize));
+
+    // Set up host address
+    host.sin_family = AF_INET;
+    host.sin_len = sizeof(host);
+    inet_aton("10.0.0.9", &(host.sin_addr)); // edgarpc dev machine
+//    inet_aton("10.0.0.1", &host.sin_addr); // cisco router
+    host.sin_port = 0;
+    ping_host(s, &host);
+}
+
+void done_test()
+{
+}
+
+void 
+net_test(void)
+{
+
+	Cyg_ErrNo err;
+    diag_printf("Start PING test\r\n");
+    TNR_INIT();
+   
+    err = cyg_io_lookup("/dev/ser0", &handle);
+    if(err != ENOERR)
+    {
+    	diag_printf("cannot open serial /dev/ser0");
+    	return;
+    }
+    printf("Testing stdout...\r\n");
+
+#ifdef CYGHWR_NET_DRIVER_ETH0
+    if (eth0_up) {
+        ping_test(&eth0_bootp_data);
+    }
+#endif
+#ifdef CYGHWR_NET_DRIVER_ETH1
+    if (eth1_up) {
+        ping_test(&eth1_bootp_data);
+    }
+#endif
+    TNR_PRINT_ACTIVITY();
+    CYG_TEST_PASS_FINISH("Ping test OK");
+    done_test();
+}
+
+
+int getFileName(const char *extension, char *fileName)
+{
+	int found = 0;
+	DIR* ramfs = opendir("/ramfs");
+	if(ramfs == NULL)
+	{
+		diag_printf("cannot open /ramfs\n");
+		return found;
+	}
+	while(1)
+	{
+		struct dirent *entry = readdir( ramfs );
+		int len = 0;
+		if( entry == NULL )
+			break;
+        len = strlen(entry->d_name);
+        if(len > 4 && entry->d_name[len - 4] == '.' &&
+        			  entry->d_name[len - 3] == 'p' &&
+        			  entry->d_name[len - 2] == 'h' &&
+        			  entry->d_name[len - 1] == 'i')
+	  	{
+	  		found = 1;
+	  		strcpy(fileName, "/ramfs/");
+	  		strcat(fileName, entry->d_name);
+	  	}
+	}
+	closedir(ramfs);
+	ramfs = NULL;
+	return found;
+}
+
+static char buf[IOSIZE];
+
+static int copyfile( char *name2, char *name1 )
+{
+
+    int err = 0;
+    int fd1 = -1, fd2 = -1;
+    ssize_t done = 0, wrote = 0, current = 0;
+
+    diag_printf(" copy file %s -> %s\n",name2,name1);
+   
+    fd1 = creat(name1, O_TRUNC | O_CREAT);
+    if( fd1 < 0 ) 
+    {
+    	SHOW_RESULT( creat, fd1 );
+    	diag_printf(" %s", name1);
+    	return -1;
+    }
+
+    fd2 = open( name2, O_RDONLY );
+    if( fd2 < 0 ) 
+    {
+    	SHOW_RESULT( open, fd2 );
+    	diag_printf(" %s", name2);
+    	return -1;
+    }
+    
+    for(;;)
+    {
+        done = read( fd2, buf, IOSIZE );
+        if( done < 0 ) 
+        {
+        	SHOW_RESULT( read, done );
+	    	return -1;
+	    }
+
+        if( done == 0 ) break;
+
+        wrote = write( fd1, buf, done );
+        if( wrote != done ) 
+        {
+        	SHOW_RESULT( write, wrote );
+	    	return -1;
+	    }
+	    
+		current += wrote;
+        if( wrote != done ) break;
+    }
+	diag_printf("wrote %d\n", current);
+    err = close( fd1 );
+    if( err < 0 )
+    {
+    	 SHOW_RESULT( close, err );
+    	 diag_printf(" %s", name1);
+    	return -1;
+    }
+
+    err = close( fd2 );
+    if( err < 0 ) 
+    {
+    	SHOW_RESULT( close, err );
+    	diag_printf(" %s", name2);
+    	return -1;
+    }
+	return 0;
+}
+
+int isCompleted(const char *fileName)
+{
+    int err = access( fileName, W_OK );
+    int fd = 0;
+    char readyBuffer[5];
+    if( err < 0 && errno != EACCES )
+    {
+    	SHOW_RESULT( access, err );
+    	return 0;
+    }
+    fd = open(fileName, O_RDONLY);
+    if(fd < 0)
+    {
+    	SHOW_RESULT( open, errno );
+    	return 0;
+    }
+    err = lseek(fd, -5, SEEK_END);
+    if(err < 0)
+    {
+    	SHOW_RESULT( lseek, err );
+    	close(fd);
+    	return 0;
+    }
+    err = read(fd, readyBuffer, 4);
+    if(err < 0)
+    {
+    	SHOW_RESULT( read, err );
+    	close(fd);
+    	return 0;
+    }
+    readyBuffer[4] = '\0';
+    if(strncmp(readyBuffer, "Done", 4) != 0)
+    {
+    	//diag_printf("Coudn't read \"Done\" at the end of the firmware file %s\n", readyBuffer);
+    	close(fd);
+    	return 0;
+    }
+    close(fd);
+    diag_printf("found!\n");
+    return 1;
+}
+
+static void ramfs_polling(cyg_addrword_t data)
+{
+	char fileName[100];
+	int found = 0;
+	while(1)
+	{
+		cyg_thread_delay(100);
+		//scan the file system for a new .phi file
+		found = getFileName("phi", fileName);
+		if(found)
+		{
+			//check if the file has been transfered
+			if(isCompleted(fileName))
+			{
+				//move the file to flash
+				unlink("/jffs2/firmware.bin");
+				copyfile(fileName, "/jffs2/firmware.bin");
+				diag_printf("firmware file copied to jffs2\n");
+				unlink(fileName);
+				diag_printf("unmounting /jffs\n");
+				umount("/jffs2");
+				diag_printf("Resetting...\n");
+//				CYGACC_CALL_IF_RESET();
+			}
+		}
+	}
+}
+
+static unsigned char ramfs_polling_stack[CYGNUM_HAL_STACK_SIZE_TYPICAL];
+static cyg_handle_t ramfs_polling_handle;
+static cyg_thread   ramfs_polling_thread;
+
+void start_ramfs_polling()
+{
+
+	cyg_thread_create(10, &ramfs_polling, 0, "ramfs_polling",
+                      ramfs_polling_stack, CYGNUM_HAL_STACK_SIZE_TYPICAL,
+                      &ramfs_polling_handle, &ramfs_polling_thread);
+	cyg_thread_resume(ramfs_polling_handle);   
+}
+
+struct tftpd_fileops fileops = {open, 
+								close, 
+								write, 
+								read};
+
+externC void phi_init_all_network_interfaces();
+
+int main(int argc, char **argv)
+{
+	diag_printf("Entered net_test main()\n");
+	
+	int server_id = 0;
+
+	init_all_network_interfaces();
+	
+
+
+	int i=0;
+	while(1)
+	{
+		cyg_thread_delay(500);
+//		net_test();
+		diag_printf("sleeping... %d\n", i++);
+	}
+	return 0;
+}
diff --git a/zpu/roadshow/roadshow/pics/GCC_logo.png b/zpu/roadshow/roadshow/pics/GCC_logo.png
new file mode 100644
index 0000000..7b3435f
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diff --git a/zpu/roadshow/roadshow/pics/codesize1.PNG b/zpu/roadshow/roadshow/pics/codesize1.PNG
new file mode 100644
index 0000000..874ee9d
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diff --git a/zpu/roadshow/roadshow/pics/codesize2.PNG b/zpu/roadshow/roadshow/pics/codesize2.PNG
new file mode 100644
index 0000000..caa8c14
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diff --git a/zpu/roadshow/roadshow/pics/ecos.gif b/zpu/roadshow/roadshow/pics/ecos.gif
new file mode 100644
index 0000000..3dad40c
Binary files /dev/null and b/zpu/roadshow/roadshow/pics/ecos.gif differ
diff --git a/zpu/roadshow/roadshow/pics/elizadebug1.PNG b/zpu/roadshow/roadshow/pics/elizadebug1.PNG
new file mode 100644
index 0000000..f3c3f5f
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diff --git a/zpu/roadshow/roadshow/pics/elizadebug2.PNG b/zpu/roadshow/roadshow/pics/elizadebug2.PNG
new file mode 100644
index 0000000..13f046e
Binary files /dev/null and b/zpu/roadshow/roadshow/pics/elizadebug2.PNG differ
diff --git a/zpu/snapshot.sh b/zpu/snapshot.sh
new file mode 100644
index 0000000..8fd6e33
--- /dev/null
+++ b/zpu/snapshot.sh
@@ -0,0 +1,7 @@
+export SNAPSHOT=`date +%Y-%m-%d`
+
+echo hdl$SNAPSHOT.zip docs$SNAPSHOT.zip sw$SNAPSHOT.zip
+rm -f hdl$SNAPSHOT.zip docs$SNAPSHOT.zip sw$SNAPSHOT.zip
+zip -r hdl$SNAPSHOT.zip hdl -x "*.svn*"
+zip -r docs$SNAPSHOT.zip docs -x "*.svn*"
+zip -r sw$SNAPSHOT.zip sw -x "*.svn*"
diff --git a/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl b/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl
new file mode 100644
index 0000000..017ee57
--- /dev/null
+++ b/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl
@@ -0,0 +1,149 @@
+# ====================================================================
+#
+#      opencores_ethermac_eth_drivers.cdl
+#
+#      Ethernet drivers - support for Opencores ethermac controllers
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2004 Andrew Lunn
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Gaisler Research, (Konrad Eisele<eiselekd@web.de>)
+# Contributors:   
+# Date:           2005-01-22
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC {
+    display       "Opencores ethermac driver"
+    description   "Ethernet driver for Opencores ethermac driver."
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_IO_ETH_DRIVERS
+
+    active_if     CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED
+
+    include_dir   .
+    include_files ; # none _exported_ whatsoever
+    compile       if_oeth.c
+
+    include_files include/oeth_info.h
+    
+    define_proc {
+        puts $::cdl_header "#include <pkgconf/system.h>";
+        puts $::cdl_header "#include CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG";
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT {
+	display "Number of supported interfaces."
+	calculated    { CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED }
+        flavor        data
+	description   "
+	    This option selects the number of ethernet interfaces to
+            be supported by the driver."
+    }
+
+    cdl_interface CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_STATIC_ESA {
+	display "ESA is statically configured"
+	description "
+	    If this is nonzero, then the ESA (MAC address) is statically
+            configured in the platform-specific package which instantiates
+	    this driver with all its details.
+
+	    Note that use of this option is deprecated in favor of a
+	    CYGSEM_DEVS_ETH_..._SET_ESA option in the platform specific
+	    driver."
+    }
+
+    cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_TxNUM {
+        display       "Number of output buffers"
+        flavor        data
+        legal_values  2 to 64
+        default_value 4
+        description   "
+            This option specifies the number of output buffer packets
+            to be used for the opencores ethernet device in multiples of 2."
+    }
+
+    cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_RxNUM {
+        display       "Number of input buffers"
+        flavor        data
+        legal_values  2 to 64
+        default_value 4
+        description   "
+            This option specifies the number of input buffer packets
+            to be used for the opencores ethernet device in multiples of 2."
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_OPTIONS {
+        display "Opencores ethermac driver build options"
+        flavor  none
+	no_define
+
+        cdl_option CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "-D_KERNEL -D__ECOS" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the opencores ethermac driver package.
+                These flags are used in addition
+                to the set of global flags."
+        }
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH {
+	display       "Cache flushing"
+	flavor        bool
+	default_value 1
+        description   "Flush cache before copying packets from/to the
+        ethermac dma transfer buffers. If you have cache snooping enabled
+        you can disable this option."
+        
+    }
+    
+    cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_ETH100 {
+	display       "Initialize MII to 100mbit"
+	flavor        bool
+	default_value 0
+        description   "Issue a MII sequence that enables a 100mbit link "
+        
+    }
+
+}
diff --git a/zpu/sw/ecos/repository/ecos.db b/zpu/sw/ecos/repository/ecos.db
new file mode 100644
index 0000000..c31fc4b
--- /dev/null
+++ b/zpu/sw/ecos/repository/ecos.db
@@ -0,0 +1,128 @@
+
+package CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC {
+        alias           { "opencore's ethermac support" devs_eth_opencores_ethermac }
+        hardware
+        directory       dev/eth/opencores/ethermac
+        script          opencores_ethermac_drivers.cdl
+        description "This package contains hardware support for Opencores
+                     ethermac."
+}
+
+package CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI {
+        alias           { "ethernet support for opencores on Zylin Phi addon board" devs_eth_zpu_opencores_phi }
+	hardware
+	directory       dev/eth/zpu/opencores/phi
+	script          phi_opencores_ethmac_drivers.cdl
+	description	"This package contains hardware support for Opencores Ethermac
+		    ethernet device on Phi."
+}
+
+
+
+package CYGPKG_HAL_ZYLIN {
+	alias		{ "Zylin common HAL" hal_zylin }
+	directory	hal/zylin/arch
+	script		hal_zylin.cdl
+	hardware
+	description "
+The Zylin architecture HAL package provides generic support for this
+processor architecture. It is also necessary to select a specific
+target platform HAL package."
+}
+
+
+package CYGPKG_HAL_ZYLIN_ZPU {
+	alias		{ "Zylin ZPU variant HAL" hal_zylin_zpu }
+	directory	hal/zylin/zpu/var
+	script		hal_zylin_zpu.cdl
+	hardware
+        description "
+        The Zylin ZPU HAL package provides the support needed to run eCos on Zylin
+        ZPU based targets."
+}
+
+
+
+package CYGPKG_HAL_ZYLIN_ZPU_ZETA {
+	alias		{ "Zylin ZPU simulation" zeta }
+	directory	hal/zylin/zpu/zeta
+	script		hal_zylin_zpu_zeta.cdl
+	hardware
+        description "
+	The Zylin ZPU package provides the support needed to run eCos on an Zylin 
+	evaluation board."
+}
+package CYGPKG_HAL_ZYLIN_ZPU_PHI {
+	alias		{ "Zylin ZPU evaluation board" phi }
+	directory	hal/zylin/zpu/phi
+	script		hal_zylin_zpu_phi.cdl
+	hardware
+        description "
+	The Zylin ZPU package provides the support needed to run eCos on a Zylin eCosBoard"
+}
+
+package CYGPKG_HAL_ZYLIN_ZPU_ABEL {
+	alias		{ "Zylin ZPU Abel board" abel }
+	directory	hal/zylin/zpu/abel
+	script		hal_zylin_zpu_abel.cdl
+	hardware
+        description "
+	The Zylin ZPU package provides the support needed to run eCos on an Abel Zylin 
+	evaluation board."
+}
+
+
+package CYGPKG_PHI_NET {
+	alias		{ "Zylin Phi networking" phi_net }
+	directory	net/zylin
+	script		phi_net.cdl
+	hardware
+        description "Contains phi specific network init."
+}
+
+
+target zeta {
+	alias { "Zylin ZPU evaluation board " zeta }
+	packages { CYGPKG_HAL_ZYLIN
+                   CYGPKG_HAL_ZYLIN_ZPU
+                   CYGPKG_HAL_ZYLIN_ZPU_ZETA
+        }
+        description "
+	The Zylin ZPU target provides the packages needed to run eCos on an Zylin 
+	evaluation board."
+}
+
+target phi {
+	alias { "Zylin ZPU evaluation board " phi }
+	packages { CYGPKG_HAL_ZYLIN
+                   CYGPKG_HAL_ZYLIN_ZPU
+                   CYGPKG_HAL_ZYLIN_ZPU_PHI
+        }
+        description "
+	The Zylin ZPU target provides the packages needed to run eCos on an Zylin eCosBoard"
+}
+
+target abel {
+	alias { "Zylin ZPU evaluation board " abel }
+	packages { CYGPKG_HAL_ZYLIN
+                   CYGPKG_HAL_ZYLIN_ZPU
+                   CYGPKG_HAL_ZYLIN_ZPU_ABEL
+        }
+        description "
+	The Zylin ZPU target provides the packages needed to run eCos on an Abel Zylin 
+	evaluation board."
+}
+
+target zpuetherphi {
+	alias { "Zylin Phi addon board with ethernet" etherphi }
+	packages { CYGPKG_HAL_ZYLIN
+                   CYGPKG_HAL_ZYLIN_ZPU
+                   CYGPKG_HAL_ZYLIN_ZPU_PHI
+                   CYGPKG_IO_ETH_DRIVERS
+                   CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC
+		   CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI
+        }
+        description "
+	The Zylin Phi ZPU target provides the packages needed to run ZPU eCos on a
+	Zylin eCosBoard addon board with ethernet."
+}
diff --git a/zpu/sw/helloworld/gccgdb.PNG b/zpu/sw/helloworld/gccgdb.PNG
new file mode 100644
index 0000000..afdfc31
Binary files /dev/null and b/zpu/sw/helloworld/gccgdb.PNG differ
diff --git a/zpu/sw/helloworld/gmon.out b/zpu/sw/helloworld/gmon.out
new file mode 100644
index 0000000..86ca3d6
Binary files /dev/null and b/zpu/sw/helloworld/gmon.out differ
diff --git a/zpu/sw/helloworld/hello.bin b/zpu/sw/helloworld/hello.bin
new file mode 100644
index 0000000..4413b05
Binary files /dev/null and b/zpu/sw/helloworld/hello.bin differ
diff --git a/zpu/sw/helloworld/hello.bram b/zpu/sw/helloworld/hello.bram
new file mode 100644
index 0000000..f7e99e9
--- /dev/null
+++ b/zpu/sw/helloworld/hello.bram
@@ -0,0 +1,12441 @@
+0 => x"0b0b0b0b",
+1 => x"82700b0b",
+2 => x"82f4e00c",
+3 => x"3a0b0b81",
+4 => x"e48c0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"81e4fd2d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
+15 => x"00000000",
+16 => x"71fd0608",
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+19 => x"832b2a83",
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+12419 => x"0000c200",
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+12421 => x"0000c208",
+12422 => x"0000c210",
+12423 => x"0000c210",
+12424 => x"0000c218",
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+12426 => x"0000c220",
+12427 => x"0000c220",
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+12431 => x"0000c230",
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+12433 => x"0000c238",
+12434 => x"0000c240",
+12435 => x"0000c240",
+12436 => x"0000ba2c",
+12437 => x"ffffffff",
+12438 => x"00000000",
+12439 => x"ffffffff",
+12440 => x"00000000",
diff --git a/zpu/sw/helloworld/hello.c b/zpu/sw/helloworld/hello.c
new file mode 100644
index 0000000..e9cc61e
--- /dev/null
+++ b/zpu/sw/helloworld/hello.c
@@ -0,0 +1,6 @@
+// To compile: zpu-elf-gcc test.c -o test.elf -phi
+// To run:  
+int main(int argc, char **argv)
+{
+	printf("Hello world!\n");
+}
diff --git a/zpu/sw/helloworld/hello.elf b/zpu/sw/helloworld/hello.elf
new file mode 100644
index 0000000..be3c093
Binary files /dev/null and b/zpu/sw/helloworld/hello.elf differ
diff --git a/zpu/sw/helloworld/zpusim.PNG b/zpu/sw/helloworld/zpusim.PNG
new file mode 100644
index 0000000..d8fc277
Binary files /dev/null and b/zpu/sw/helloworld/zpusim.PNG differ
diff --git a/zpu/sw/index.html b/zpu/sw/index.html
new file mode 100644
index 0000000..6c860a9
--- /dev/null
+++ b/zpu/sw/index.html
@@ -0,0 +1,44 @@
+<html>
+<body>
+<h1>Getting started - a ZPU hello world program</h1>
+The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has 
+some very basic peripherals defined: counter, timer interrupt and a debug output port. 
+<h2>Installing</h2>
+<ol>
+<li>Install Cygwin. http://www.cygwin.com 
+<li>Install Java
+<li>Start Cygwin bash
+<li>cd zpu/sw
+<li>unzip tools/zputoolchain.zip
+<li>zpu/sw/install/bin now has the .exe files for the GCC toolchain & GDB
+<li>You may want to add install/bin from zputoolchain.zip to PATH.<br>
+export PATH=$PATH:&lt;unzipdir&gt;/install/bin
+</ol>
+<h1>Hello world example</h1>
+The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification.
+<p> 
+<code>
+cd zpu/sw/helloworld<br>
+../install/bin/zpu-elf-gcc -phi hello.c -o hello.elf <br>
+</code>
+<h2>Running the hello world example in GDB</h2>
+<ol>
+<li>cd zpu/sw/helloworld
+<li>Launch the simulator from a seperate bash shell:<p>
+java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444
+<p>
+<img src="helloworld/zpusim.PNG" border=0> 
+<li>Launch GDB:<p>
+../install/bin/zpu-elf-gdb hello.elf
+<li>Connect to target, load and run application:<p>
+<code>
+(gdb) target remote localhost:4444<br>
+(gdb) load<br>
+(gdb) continue<br>
+</code>
+<p>
+<img src="helloworld/gccgdb.PNG">
+
+
+</body>
+</html>
diff --git a/zpu/sw/simulator/.classpath b/zpu/sw/simulator/.classpath
new file mode 100644
index 0000000..617be7e
--- /dev/null
+++ b/zpu/sw/simulator/.classpath
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<classpath>
+	<classpathentry excluding="bin/" kind="src" output="bin" path=""/>
+	<classpathentry kind="con" path="org.eclipse.jdt.launching.JRE_CONTAINER"/>
+	<classpathentry kind="output" path=""/>
+</classpath>
diff --git a/zpu/sw/simulator/.project b/zpu/sw/simulator/.project
new file mode 100644
index 0000000..9cd2fd7
--- /dev/null
+++ b/zpu/sw/simulator/.project
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>simulator</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.jdt.core.javabuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.jdt.core.javanature</nature>
+	</natures>
+</projectDescription>
diff --git a/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs b/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs
new file mode 100644
index 0000000..6a131a7
--- /dev/null
+++ b/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs
@@ -0,0 +1,66 @@
+#Sat Aug 04 19:47:23 CEST 2007
+eclipse.preferences.version=1
+org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled
+org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.5
+org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve
+org.eclipse.jdt.core.compiler.compliance=1.5
+org.eclipse.jdt.core.compiler.debug.lineNumber=generate
+org.eclipse.jdt.core.compiler.debug.localVariable=generate
+org.eclipse.jdt.core.compiler.debug.sourceFile=generate
+org.eclipse.jdt.core.compiler.problem.annotationSuperInterface=warning
+org.eclipse.jdt.core.compiler.problem.assertIdentifier=error
+org.eclipse.jdt.core.compiler.problem.autoboxing=ignore
+org.eclipse.jdt.core.compiler.problem.deprecation=warning
+org.eclipse.jdt.core.compiler.problem.deprecationInDeprecatedCode=disabled
+org.eclipse.jdt.core.compiler.problem.deprecationWhenOverridingDeprecatedMethod=disabled
+org.eclipse.jdt.core.compiler.problem.discouragedReference=warning
+org.eclipse.jdt.core.compiler.problem.emptyStatement=ignore
+org.eclipse.jdt.core.compiler.problem.enumIdentifier=error
+org.eclipse.jdt.core.compiler.problem.fallthroughCase=ignore
+org.eclipse.jdt.core.compiler.problem.fatalOptionalError=enabled
+org.eclipse.jdt.core.compiler.problem.fieldHiding=ignore
+org.eclipse.jdt.core.compiler.problem.finalParameterBound=ignore
+org.eclipse.jdt.core.compiler.problem.finallyBlockNotCompletingNormally=warning
+org.eclipse.jdt.core.compiler.problem.forbiddenReference=error
+org.eclipse.jdt.core.compiler.problem.hiddenCatchBlock=warning
+org.eclipse.jdt.core.compiler.problem.incompatibleNonInheritedInterfaceMethod=warning
+org.eclipse.jdt.core.compiler.problem.incompleteEnumSwitch=ignore
+org.eclipse.jdt.core.compiler.problem.indirectStaticAccess=ignore
+org.eclipse.jdt.core.compiler.problem.localVariableHiding=ignore
+org.eclipse.jdt.core.compiler.problem.methodWithConstructorName=warning
+org.eclipse.jdt.core.compiler.problem.missingDeprecatedAnnotation=ignore
+org.eclipse.jdt.core.compiler.problem.missingOverrideAnnotation=ignore
+org.eclipse.jdt.core.compiler.problem.missingSerialVersion=ignore
+org.eclipse.jdt.core.compiler.problem.noEffectAssignment=warning
+org.eclipse.jdt.core.compiler.problem.noImplicitStringConversion=warning
+org.eclipse.jdt.core.compiler.problem.nonExternalizedStringLiteral=ignore
+org.eclipse.jdt.core.compiler.problem.nullReference=ignore
+org.eclipse.jdt.core.compiler.problem.overridingPackageDefaultMethod=warning
+org.eclipse.jdt.core.compiler.problem.parameterAssignment=ignore
+org.eclipse.jdt.core.compiler.problem.possibleAccidentalBooleanAssignment=ignore
+org.eclipse.jdt.core.compiler.problem.potentialNullReference=ignore
+org.eclipse.jdt.core.compiler.problem.rawTypeReference=ignore
+org.eclipse.jdt.core.compiler.problem.redundantNullCheck=ignore
+org.eclipse.jdt.core.compiler.problem.specialParameterHidingField=disabled
+org.eclipse.jdt.core.compiler.problem.staticAccessReceiver=warning
+org.eclipse.jdt.core.compiler.problem.suppressWarnings=enabled
+org.eclipse.jdt.core.compiler.problem.syntheticAccessEmulation=ignore
+org.eclipse.jdt.core.compiler.problem.typeParameterHiding=warning
+org.eclipse.jdt.core.compiler.problem.uncheckedTypeOperation=ignore
+org.eclipse.jdt.core.compiler.problem.undocumentedEmptyBlock=ignore
+org.eclipse.jdt.core.compiler.problem.unhandledWarningToken=warning
+org.eclipse.jdt.core.compiler.problem.unnecessaryElse=ignore
+org.eclipse.jdt.core.compiler.problem.unnecessaryTypeCheck=ignore
+org.eclipse.jdt.core.compiler.problem.unqualifiedFieldAccess=ignore
+org.eclipse.jdt.core.compiler.problem.unusedDeclaredThrownException=ignore
+org.eclipse.jdt.core.compiler.problem.unusedDeclaredThrownExceptionWhenOverriding=disabled
+org.eclipse.jdt.core.compiler.problem.unusedImport=warning
+org.eclipse.jdt.core.compiler.problem.unusedLabel=warning
+org.eclipse.jdt.core.compiler.problem.unusedLocal=warning
+org.eclipse.jdt.core.compiler.problem.unusedParameter=ignore
+org.eclipse.jdt.core.compiler.problem.unusedParameterIncludeDocCommentReference=enabled
+org.eclipse.jdt.core.compiler.problem.unusedParameterWhenImplementingAbstract=disabled
+org.eclipse.jdt.core.compiler.problem.unusedParameterWhenOverridingConcrete=disabled
+org.eclipse.jdt.core.compiler.problem.unusedPrivateMember=warning
+org.eclipse.jdt.core.compiler.problem.varargsArgumentNeedCast=warning
+org.eclipse.jdt.core.compiler.source=1.5
diff --git a/zpu/sw/simulator/ChangeLog b/zpu/sw/simulator/ChangeLog
new file mode 100644
index 0000000..c645841
--- /dev/null
+++ b/zpu/sw/simulator/ChangeLog
@@ -0,0 +1,2 @@
+2007-08-04 Øyvind Harboe
+	* First version after open sourcing ZPU
diff --git a/zpu/sw/simulator/build.xml b/zpu/sw/simulator/build.xml
new file mode 100644
index 0000000..a5cc8a3
--- /dev/null
+++ b/zpu/sw/simulator/build.xml
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<project name="project" default="build">
+	
+	<target name="build" >
+		<jar destfile="zpusim.jar" basedir="bin"/>
+	</target>
+</project>
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java
new file mode 100644
index 0000000..8d8667c
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java
@@ -0,0 +1,109 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Abel extends Simulator
+{
+
+    protected int getIO()
+    {
+        return 0x8000;
+    }
+
+
+
+    protected int ioRead(int addr) throws CPUException
+    {
+        switch (addr)
+        {
+            case 0xc000:
+                return syscall.readUART();
+                
+                /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+            case 0xc004:
+                return syscall.readFIFO();
+                
+            case 0x9000:
+            case 0x9004:
+            case 0x9008:
+            case 0x900c:
+                
+            case 0x9010:
+            case 0x9014:
+            case 0x9018:
+            case 0x901c:
+            return readSampledTimer(addr, 0x9000);
+            
+            case 0x8800:
+                return readMHz();
+                
+        	default:
+        		throw new MemoryAccessException();
+        }
+    }
+
+    /*
+    ; Read/write are on different addresses
+    ; The registers are 8 bits and mapped to bit[7:0]
+    ; 
+    ; 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) 
+    ;        Read : Reads from UART RX FIFO (4 byte FIFO)
+    ; 0xC004 Read : UART status register
+    ;                       Bit 0 = RX FIFO empty
+    ;                       Bit 1 = TX FIFO full
+    ; 0xA000 Write: 8 LED's 
+    */
+    
+    /*
+    0x9000 Write: bit 0: 1= reset counter
+                   0= counter running
+              bit 1: 1= sample counter (when set to 1)
+                   0=not used
+         Read : counter bit[7:0]
+    0x9004 Read: counter bit [15:8]
+    0x9008 Read: counter bit [23:16]
+    0x900C Read: counter bit [31:24]
+    0x9010 Read: counter bit [39:32]
+    0x9014 Read: counter bit [47:40]
+    0x9018 Read: counter bit [55:48]
+    0x901C Read: counter bit [63:56]
+
+    0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz)
+    */
+
+    protected void ioWrite(int addr, int val) throws MemoryAccessException
+    {
+        switch (addr)
+        {
+            case 0x9000:
+                writeTimerSampleReg(val);
+            case 0xc000:
+                syscall.writeUART(val);
+                break;
+        	default:
+                throw new MemoryAccessException();
+        }
+    }
+
+    Abel() throws CPUException
+    {
+    }
+
+    protected boolean emulateConfig()
+    {
+        return true;
+    }
+
+    protected int getStartStack()
+    {
+        return getRAMSIZE()-8;
+    }
+
+    protected int getRAMSIZE()
+    {
+        return 32768;
+    }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java
new file mode 100644
index 0000000..6ccca24
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java
@@ -0,0 +1,285 @@
+
+package com.zylin.zpu.simulator;
+
+import java.io.FileNotFoundException;
+import java.io.IOException;
+import java.io.LineNumberReader;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.TraceException;
+
+public class FileTracer implements Tracer
+{
+    private LineNumberReader file;
+    private boolean trigger;
+    private boolean resync;
+    private Simulator simulator;
+    private String line;
+    private boolean ignore;
+    
+    static class Trace
+    {
+    	int pc;
+    	int opcode;
+    	int sp;
+    	int stackA;
+    	int stackB;
+    	int intSp;
+    	long cycle;
+		public boolean undefinedStackA;
+		public boolean undefinedStackB;
+		public boolean undefinedIntSp;
+		public void print()
+		{
+			System.err.println(Integer.toHexString(pc)+ " " +
+			       		Integer.toHexString(opcode) + " " +
+			                Integer.toHexString(sp) + " " + 
+			                Integer.toHexString(stackA) + " " + 
+			                Integer.toHexString(stackB) + " " + 
+			                intSp + " " +
+			                cycle);
+			
+		}
+    };
+    private Trace[] trace= new Trace[100];
+    private int current;
+	private String fileName;
+	private boolean metEnd;
+    
+
+    public FileTracer(Simulator sim, String string)
+    {
+        simulator=sim;
+        fileName=string;
+
+        resync=true;
+       
+        
+        for (int i=0; i<trace.length; i++)
+        {
+        	trace[i]=new Trace();
+        }
+        findNextTrigger();
+    }
+
+    LineNumberReader getFile()
+    {
+    	if (file==null)
+    	{
+    		try
+			{
+				file=new LineNumberReader(new java.io.FileReader(fileName));
+			} catch (FileNotFoundException e)
+			{
+				throw new RuntimeException(e);
+			}
+    	}
+    	return file;
+    }
+
+
+    private void findNextTrigger() throws TraceException
+    {
+        trigger=false;
+        try
+        {
+            for (;;)
+            {
+                line=getFile().readLine();
+                if (line==null)
+                {
+                	metEnd=true;
+                    System.err.println("================== End of trace file ======================");
+                    break;
+                }
+                if (line.matches("^\\s*\\#.*$"))
+                {
+                    /* this was a comment*/
+                    continue;
+                }
+                if (line.matches("^\\s*$"))
+                {
+                    /* all whitespace */
+                    continue;
+                }
+                String[] val=line.split(" ");
+                
+                try
+                {
+                	Trace t=trace[current];
+                    t.pc=(int) parseInt(val[0]);
+                    t.opcode=(int) parseInt(val[1]);
+                    t.sp=(int) parseInt(val[2]);
+                    try
+                    {
+                    	t.undefinedStackA=false;
+                    	t.stackA=(int) parseInt(val[3]);
+                    } catch (NumberFormatException e)
+                    {
+                    	t.undefinedStackA=true;
+                    	t.stackB=0;
+                    }
+
+                    try
+                    {
+                    	t.undefinedStackB=false;
+                    	t.stackB=(int) parseInt(val[4]);
+                    } catch (NumberFormatException e)
+                    {
+                    	t.undefinedStackB=true;
+                    	t.stackB=0;
+                    }
+                    try
+                    {
+                    	t.undefinedIntSp=false;
+                    	t.intSp=(int) parseInt(val[5]);
+                    } catch (NumberFormatException e)
+                    {
+                    	t.undefinedIntSp=true;
+                    	t.intSp=0;
+                    }
+                   	t.cycle=parseInt(val[6]);
+                    trigger=true;
+                    break;
+                } catch (NumberFormatException e)
+                {
+                    /* skip this line. */
+                    e.printStackTrace();
+                }
+            }
+        } catch (IOException e)
+        {
+            throw new TraceException(e);
+        } 
+        
+    }
+
+    private long parseInt(String string2) throws TraceException
+    {
+        String string = string2;
+        if (!string.startsWith("0x"))
+        {
+            throw new TraceException(new Exception("Trace file pasing error line " + getFile().getLineNumber()));
+        }
+        return Long.parseLong(string.substring(2), 16);
+    }
+
+    public void instructionEvent() throws GDBServerException
+    {
+    	if (metEnd)
+    	{
+    		metEnd=false;
+    		throw new TraceException();
+    	}
+        if (resync&&trigger)
+        {
+            if (match())
+            {
+                /* we have to wait for the first instruction in the trace to be matched */
+            	System.out.println("First matching instruction found!");
+                resync=false;
+            }
+        } 
+
+        if (!resync&&trigger)
+        {
+        	
+            boolean m=match();
+            recordCurrent();
+            current=(current+1)%trace.length;
+
+            if (!m)
+            {
+                System.err.println("Trace file mismatch");
+                dumpTraceBack();
+                System.err.print("Expected by Java simulator: \n");
+                simulator.printState(this);
+                System.err.print("Actual from ModelSim: ");
+                System.err.println(line);
+                // we now have to ignore this match.
+                ignore=true;
+                throw new TraceException();
+            }
+        } else
+        {
+            recordCurrent();
+            current=(current+1)%trace.length;
+        }
+    }
+
+	public void dumpTraceBack()
+	{
+		System.err.println("Expected");
+		System.err.println("PC SP topOfStack");
+		for (int i=0; i<trace.length; i++)
+		{
+		    trace[(i+current)%trace.length].print();
+		}
+	}
+
+	private void recordCurrent()
+    {
+        recordState(trace[current]);
+    }
+
+	private void recordState(Trace trace3)
+	{
+		trace3.pc=simulator.getPc();
+        trace3.sp=simulator.getSp();
+        trace3.opcode=simulator.getOpcode();
+        try
+        {
+            trace3.stackA=simulator.cpuReadLong(simulator.getSp());
+            trace3.stackB=simulator.cpuReadLong(simulator.getSp()+4);
+            trace3.intSp=simulator.getIntSp();
+           // trace[current].cycle=expectetdCycle();
+        } catch (CPUException e1)
+        {
+            e1.printStackTrace();
+        }
+	}
+
+   
+    
+    boolean match() throws GDBServerException
+    {
+        if (ignore)
+            return true;
+        
+        return simulator.checkMatch(trace[current]);
+    }
+
+	public void commit()
+    {
+        try
+        {
+            if (!resync&&trigger)
+            {
+                ignore=false;
+                findNextTrigger();
+            }
+        } 
+        catch (Throwable e)
+        {
+            e.printStackTrace();
+        }
+    }
+
+    public void setSp(int sp)
+    {
+    }
+
+	public boolean onInterrupt()
+	{
+		if (trace[current].pc==0x20)
+			return true;
+		else
+			return false;
+	}
+
+	public boolean simInterrupt()
+	{
+		return true;
+	}
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Host.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Host.java
new file mode 100644
index 0000000..c1daa9f
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Host.java
@@ -0,0 +1,46 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+
+public interface Host
+{
+	/** generic file io error */
+	public final static int  EIO =    5;
+	
+    public final static int  SYS_read=    4;
+    public final static int  SYS_write=   5;
+	public final static int  SYS_argv   = 13;
+	public final static int SYS_exit=1;
+	public final static int  SYS_open=    2;
+	public final static int  SYS_close=   3;
+	public final static int  SYS_lseek =  6;
+	public final static int  SYS_unlink = 7;
+	public final static int  SYS_getpid = 8;
+	public final static int  SYS_kill  =  9;
+	public final static int  SYS_fstat =      10;
+	/*final static int  SYS_sbrk  11 - not currently a system call, but reserved.  */
+	/* ARGV support.  */
+	public final static int  SYS_argvlen= 12;
+	/* These are extras added for one reason or another.  */
+	public final static int  SYS_chdir  =  14;
+	public final static int  SYS_stat   =  15;
+	public final static int  SYS_chmod  =  16;
+	public final static int  SYS_utime  =  17;
+	public final static int  SYS_time   =  18;
+	public final static int  SYS_gettimeofday =19;
+	public final static int  SYS_times  =  20;
+	public final static int  SYS_link   =  21;
+	public final static int  SYS_ftruncate=3000;
+	public final static int  SYS_isatty=3001;
+    public void syscall(Sim s) throws CPUException;
+    boolean doneContinue();
+    public void writeUART(int val);
+    public int readUART() throws CPUException;
+    public int readFIFO();
+    /** notification that the CPU is halted */
+	public void halted();
+	/** notification that the CPU is running */
+	public void running();
+    
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java
new file mode 100644
index 0000000..3827378
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java
@@ -0,0 +1,17 @@
+
+package com.zylin.zpu.simulator;
+
+/**
+ * @author oyvind
+ *
+ * TODO To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Style - Code Templates
+ */
+public interface Machine
+{
+
+    long getPrevCycles();
+
+    long getCycles();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
new file mode 100644
index 0000000..862deae
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
@@ -0,0 +1,126 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Phi extends Simulator
+{
+	@Override
+	protected long getSampleOffset()
+	{
+		 
+		return super.getSampleOffset()-(0x5e7b2-0x0005E7C0);
+	}
+
+
+	public static void main(String[] args)
+	{
+        new SimApp(new SimFactory()
+        {
+        	public Simulator create()
+        	{
+        		return new Phi();
+        	}
+        }).run(args);
+	}
+    
+
+    protected int getIO()
+    {
+        return 0x08000000;
+    }
+
+
+
+    protected int ioRead(int addr) throws CPUException
+    {
+        switch (addr)
+        {
+        
+        case 0x080a0020:
+        	return interrupt?0:1; // interrupt mask
+
+        	
+        
+            /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+            case 0x080a000c:
+            	return 0x100; // buffer ready. 
+                
+            case 0x080a0014:
+            case 0x080a0018:
+            return readSampledTimer(addr, 0x080a0014);
+
+            case 0x080a0030:
+            	return timerPending?1:0;
+            case 0x080a0038:
+            	return (int)(timerInterval-1-((cycles-lastTimer)%timerInterval));
+
+            
+        	default:
+        		throw new MemoryAccessException();
+        }
+    }
+
+
+
+    protected void ioWrite(int addr, int val) throws MemoryAccessException
+    {
+        switch (addr)
+        {
+        case 0x080a0020:
+        	interrupt=(val&1)==0;
+        	return;
+        case 0x080a002c:
+        	timer=(val&0x1)!=0;
+        	break;
+        case 0x080a0030:
+        	if ((val&0x1)!=0)
+        	{
+        		timerPending=false;
+        	}
+        	if ((val&0x2)!=0)
+        	{
+        		lastTimer=cycles;
+        	}
+        	break;
+        case 0x080a0034:
+        	timerInterval=val;
+        	return;
+        	
+            case 0x080a0014:
+                writeTimerSampleReg(val);
+            case 0x080a000c:
+                syscall.writeUART(val);
+                break;
+        	default:
+                throw new MemoryAccessException();
+        }
+    }
+
+    Phi() throws CPUException
+    {
+    }
+
+    protected boolean emulateConfig()
+    {
+        return true;
+    }
+
+    protected int getStartStack()
+    {
+        return getRAMSIZE()-8;
+    }
+
+    protected int getRAMSIZE()
+    {
+        return 32*1024*1024;
+    }
+
+
+	protected int getIOSIZE()
+	{
+		return 0x100000;
+	}
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java b/zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java
new file mode 100644
index 0000000..79d3a38
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java
@@ -0,0 +1,34 @@
+package com.zylin.zpu.simulator;
+
+public class PhiFeeble extends Phi
+{
+	public static void main(String[] args)
+	{
+        new SimApp(new SimFactory()
+        {
+        	public Simulator create()
+        	{
+        		return new PhiFeeble();
+        	}
+        }).run(args);
+	}
+	protected void setFeeble()
+	{
+//		feeble[NEQBRANCH] = false;
+//		feeble[EQ] = false;
+//		feeble[LOADB] = false;
+//		feeble[LESSTHAN] = false;
+//		feeble[ULESSTHAN] = false;
+//		feeble[STOREB] = false;
+//		feeble[MULT] = false;
+//		feeble[CALL] = true;
+//		feeble[POPPCREL] = true;
+//		feeble[LESSTHANOREQUAL] = true;
+//		feeble[ULESSTHANOREQUAL] = true;
+//
+//		feeble[PUSHSPADD] = false;
+//		feeble[CALLPCREL] = false;
+//		feeble[SUB] = false;
+	}
+	
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java
new file mode 100644
index 0000000..21450f7
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java
@@ -0,0 +1,62 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public interface Sim
+{
+/**
+     * halts the CPU. 
+     */
+    void suspend();
+    void writeByte(int i, int val) throws CPUException;
+    /** 
+     * synchronous method that returns when simulator enters the halt state. 
+     **/
+    void cont();
+    /** 
+     * synchronous method that returns when simulator finishes step or otherwise enters
+     * the halt state. 
+     **/
+    void step();
+
+    int getReg(int i) throws CPUException;
+
+    int getREGNUM();
+    int readByte(int addr) throws CPUException;
+
+    /**
+     * @param sp The sp to set.
+     * @throws CPUException 
+     */
+    void setSp(int sp) throws CPUException;
+
+    /**
+     * @return Returns the sp.
+     */
+    int getSp();
+
+    /**
+     * @param pc The pc to set.
+     * @throws MemoryAccessException
+     */
+    void setPc(int pc) throws MemoryAccessException;
+
+    /**
+     * @return Returns the pc.
+     */
+    int getPc();
+
+    void enableAccessWatchPoint(int address, int length) throws CPUException;
+
+    void disableAccessWatchPoint(int address, int length) throws CPUException;
+
+    int cpuReadLong(int i) throws CPUException;
+
+    void cpuWriteLong(int i, int retval) throws MemoryAccessException;
+
+    int getArg(int num) throws CPUException;
+	void sessionStarted();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
new file mode 100644
index 0000000..8008275
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
@@ -0,0 +1,112 @@
+package com.zylin.zpu.simulator;
+
+import java.io.IOException;
+import java.net.InetSocketAddress;
+import java.nio.channels.ServerSocketChannel;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.gdb.GDBServer;
+
+public class SimApp
+{
+	private static Simulator simulator;
+	public ServerSocketChannel channel;
+    private String[] args;
+    private int portNumber;
+	private SimFactory simFactory;
+
+    public SimApp(SimFactory factory)
+	{
+    	simFactory=factory;
+	}
+
+	public void parseArgs()
+    {
+        portNumber = 4444;
+        if (args.length>=1)
+        {
+            portNumber=Integer.parseInt(args[0]);
+        }
+    }
+
+    private void moreParse()
+    {
+        if (args.length>=2)
+        {
+            simulator.setTraceFile(args[1]);
+        }
+    }
+
+	void run(String[] args)
+	{
+        this.args=args;
+        parseArgs();
+        try
+		{
+			channel = ServerSocketChannel.open();
+			try
+			{
+                System.out.println("Listening on port " + portNumber);
+				channel.socket().bind(new InetSocketAddress(portNumber));
+				for (;;)
+				{
+					try
+					{
+						simulator=simFactory.create();
+				        simulator.suspend();
+                        moreParse();
+						run();
+					} catch (CPUException e)
+					{
+						e.printStackTrace();
+					} 
+				}
+			} finally
+			{
+				channel.close();
+			}
+		} catch (IOException e1)
+		{
+			e1.printStackTrace();
+		}
+	
+	}
+
+    private void run() throws CPUException
+    {
+        final GDBServer gdbServer=new GDBServer(simulator, this);
+        simulator.setSyscall(gdbServer);
+        Thread thread = new Thread(new Runnable()
+                {
+                    public void run()
+                    {
+                        try
+                        {
+                            gdbServer.gdbServer();
+                        } 
+                        catch (Throwable e)
+                        {
+                            e.printStackTrace();
+                        }
+                        simulator.shutdown();
+                    }
+                });
+        thread.start();
+        try
+        {
+            simulator.run();
+        } 
+        finally
+        {
+            
+            try
+            {
+                thread.join();
+            } catch (InterruptedException e)
+            {
+                e.printStackTrace();
+            }
+        }
+            
+    }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java b/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java
new file mode 100644
index 0000000..4db85d7
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java
@@ -0,0 +1,8 @@
+package com.zylin.zpu.simulator;
+
+public interface SimFactory
+{
+
+	Simulator create();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
new file mode 100644
index 0000000..c1b86d4
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
@@ -0,0 +1,2063 @@
+package com.zylin.zpu.simulator;
+
+import java.io.ByteArrayOutputStream;
+import java.io.FileOutputStream;
+import java.io.IOException;
+import java.io.InputStream;
+import java.io.OutputStream;
+import java.util.Collections;
+import java.util.Comparator;
+import java.util.LinkedList;
+import java.util.List;
+
+import com.zylin.zpu.simulator.FileTracer.Trace;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.DebuggerBreakpointException;
+import com.zylin.zpu.simulator.exceptions.EndSessionException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.HardwareWatchPointException;
+import com.zylin.zpu.simulator.exceptions.IllegalInstructionException;
+import com.zylin.zpu.simulator.exceptions.InterruptException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Simulator implements ZPU, Machine, Sim 
+{
+	
+    int minStack;
+
+    /** 
+	 * the feeble version of the CPU, e.g. only implements
+	 * 11 instructions. 
+     * 
+     * For debugging purposes it is useful to enable/disable
+     * each instruction
+	 */
+    boolean feeble[]=new boolean[256];
+	    
+	private long opcodeHistogram[]=new long[256];
+	private long opcodeHistogramCycles[]=new long[256];
+	private long opcodePairHistogram[]=new long[256*256];
+	private long opcodePairHistogramCycles[]=new long[256*256];
+	
+	/** weee! constants are 32 bit by default, so we need to assign a 64 bit
+	 * integer in this matter.
+	 */
+	private static final long INTMASK = Long.parseLong("ffffffff", 16);
+	
+    final static int PUSHPC=59;
+	final static int OR=7;
+	final static int NOT=9;
+	final static int LOAD=8;
+	final static int STORE=12;
+	final static int POPPC=4;
+	final static int FLIP=10;
+
+	final static int ADD=5;
+	final static int PUSHSP=2;
+	final static int POPSP=13;
+	final static int NOP=11;
+	final static int AND=6;
+	final static int ADDSP=16;
+
+    final static int EMULATE=32;
+	final static int LOADH=34;
+	final static int STOREH=35;
+	final static int LESSTHAN=36;
+	final static int LESSTHANOREQUAL=37;
+	final static int ULESSTHAN=38;
+	final static int ULESSTHANOREQUAL=39;
+    final static int SWAP=40;
+    final static int MULT=41;
+	final static int LSHIFTRIGHT=42;
+	final static int ASHIFTLEFT=43;
+    final static int ASHIFTRIGHT=44;
+    final static int CALL=45;
+    final static int EQ=46;
+	final static int NEQ=47;
+    final static int NEG=48;
+    final static int SUB=49;
+	final static int XOR=50;
+    final static int LOADB=51;
+    final static int STOREB=52;
+    final static int DIV=53;
+    final static int MOD=54;
+    final static int EQBRANCH=55;
+    final static int NEQBRANCH=56;
+    final static int POPPCREL=57;
+    final static int CONFIG=58;
+    final static int SYSCALL=60;
+    final static int PUSHSPADD=61;
+    final static int MULT16X16=62;
+    final static int CALLPCREL=63;
+    final static int STORESP=64;
+    final static int LOADSP=64+32;
+        
+	int[] memory;
+	boolean[] validMemory;
+	protected long cycles;
+	protected int instructionCount;
+	private int sp;
+	private int pc;
+	protected boolean breakNext;
+	
+	/* halting synchronization object */
+	protected Object halt = new Object();
+	
+	private int IOSIZE=getIOSIZE();
+	protected int getIOSIZE()
+	{
+		return 32768;
+	}
+	long prevCycles;
+	private static final int VECTORSIZE = 0x20;
+	private static final int VECTOR_RESET = 0;
+	private static final int VECTOR_INTERRUPT = 1;
+	private boolean hitVector;
+	private static final int VECTORBASE = 0x0;
+	private int nextVector;
+	protected long lastTimer;
+	protected boolean timer;
+	private boolean powerdown;
+    private boolean decodeMask;
+
+    private static final int ZETA = 1;
+
+    private static final int ABEL = 0;
+
+    private int startStack;
+
+    protected Host syscall;
+
+	private long[] emulateOpcodeHistogram= new long[256];
+
+	private long[] emulateOpcodeHistogramCycles=new long[256];
+
+	private long emulateCycles;;
+
+	public Simulator() throws CPUException
+	{
+	}
+	
+	
+	public void run() throws CPUException
+	{
+		syscall.running();
+		
+		try
+		{
+            
+			instructionLoop();
+			
+			
+		}  catch (EndSessionException e)
+		{
+			/* done */
+		} finally
+		{
+		}
+		dumpInfo();
+        
+        System.err.println("Stack usage: " + (startStack-minStack));
+	}
+
+	private void dumpInfo() 
+	{
+		dumpOpcodeHistogram();
+        
+		//printMemoryHistorgram();
+	}
+
+
+    private void dumpOpcodeHistogram()
+    {
+        System.out.println("Opcode histogram");
+        dumpHistogram(opcodeHistogram, opcodeHistogramCycles);
+        System.out.println("Emulate histogram");
+        dumpHistogram(emulateOpcodeHistogram, emulateOpcodeHistogramCycles);
+        System.out.println("Pair histogram");
+        dumpHistogram(opcodePairHistogram, opcodePairHistogramCycles);
+        
+        
+        dumpGmon();
+        
+        System.out.println("Grouping of LOADSP/STORESP/IM");
+        printRange(64, 96);
+        printRange(96, 128);
+        printRange(128, 256);
+//      printRange(64, 65);
+//        printRange(65, 66);
+//        printRange(66, 64+32);
+//        printRange(96, 97);
+//        printRange(97, 98);
+//        printRange(98, 96+32);
+//        printRange(128, 129);
+//        printRange(129, 130);
+//        printRange(130, 131);
+//        printRange(131, 132);
+//        printRange(132, 133);
+//        printRange(252, 253);
+//        printRange(253, 254);
+//        printRange(254, 255);
+//        printRange(255, 256);
+    }
+
+
+
+//    #define	GMON_MAGIC	"gmon"	/* magic cookie */
+//    #define GMON_VERSION	1	/* version number */
+//
+//    /*
+//     * Raw header as it appears on file (without padding):
+//     */
+//    struct gmon_hdr
+//    {
+//        char cookie[4];
+//        char version[4];    // a cyg_uint32, target-side endianness
+//        char spare[3 * 4];
+//    };
+//
+//    /* types of records in this file: */
+//    typedef enum
+//    {
+//        GMON_TAG_TIME_HIST = 0, GMON_TAG_CG_ARC = 1, GMON_TAG_BB_COUNT = 2
+//    }
+//    GMON_Record_Tag;
+//
+//    /* The histogram tag is followed by this header, and then an array of       */
+//    /* cyg_uint16's for the actual counts.                                      */
+//
+//    struct gmon_hist_hdr
+//    {
+//        /* host-side gprof adapts to sizeof(void*) and endianness.              */
+//        /* It is assumed that the compiler does not insert padding around the   */
+//        /* cyg_uint32's or the char arrays.                                     */
+//        void*       low_pc;             /* base pc address of sample buffer     */
+//        void*       high_pc;            /* max pc address of sampled buffer     */
+//        cyg_uint32  hist_size;          /* size of sample buffer                */
+//        cyg_uint32  prof_rate;          /* profiling clock rate                 */
+//        char        dimen[15];			/* phys. dim., usually "seconds"        */
+//        char        dimen_abbrev;		/* usually 's' for "seconds"            */
+//    };
+//
+//    /* An arc tag is followed by a single arc record. self_pc corresponds to    */
+//    /* the location of an mcount() call, at the start of a function. from_pc    */
+//    /* corresponds to the return address, i.e. where the function was called    */
+//    /* from. count is the number of calls.                                      */
+//
+//    struct gmon_cg_arc_record
+//    {
+//        void*       from_pc;            /* address within caller's body         */
+//        void*       self_pc;        	/* address within callee's body         */
+//        cyg_uint32  count;              /* number of arc traversals             */
+//    };
+//
+//    /* In theory gprof can also process basic block counts, as per the          */
+//    /* compiler's -fprofile-arcs flag. The compiler-generated basic block       */
+//    /* structure should contain a table of addresses and a table of counts,     */
+//    /* and the compiled code updates those counts. Current versions of the      */
+//    /* compiler (~3.2.1) do not output the table of addresses, and without      */
+//    /* that table gprof cannot process the counts. Possibly gprof should read   */
+//    /* in the .bb and .bbg files generated for gcov processing, but that does   */
+//    /* not happen at the moment.                                                */
+//    /*                                                                          */
+//    /* So for now gmon.out does not contain basic block counts and gprof        */
+//    /* operations that depend on it, e.g. --annotated-source, won't work.       */
+    
+    /**
+     * Write gmon.out file.
+     **/
+	private void dumpGmon()
+	{
+		try
+		{
+		ByteArrayOutputStream b=new ByteArrayOutputStream();
+		
+
+//	    /*
+//	     * Raw header as it appears on file (without padding):
+//	     */
+//	    struct gmon_hdr
+//	    {
+//	        char cookie[4];
+//	        char version[4];    // a cyg_uint32, target-side endianness
+//	        char spare[3 * 4];
+//	    };
+//	    #define	GMON_MAGIC	"gmon"	/* magic cookie */
+//	    #define GMON_VERSION	1	/* version number */
+
+//		   dump   binary memory gmon.out &profile_gmon_hdr ((char*)&profile_gmon_hdr + sizeof(struct gmon_hdr))
+			b.write("gmon".getBytes());
+			writeLong(b, 1); // version
+			b.write(new byte[3*4]); // spare
+			
+//		    GMON_TAG_TIME_HIST = 0, GMON_TAG_CG_ARC = 1, GMON_TAG_BB_COUNT = 2
+
+//			   append binary memory gmon.out &profile_tags[0] &profile_tags[1]
+			b.write(new byte[]{0}); // GMON_TAG_TIME_HIST 
+
+
+//			
+//		    // The gprof documentation claims that this should be the size in
+//		    // bytes. The implementation treats it as a count.
+//		    profile_hist_hdr.hist_size  = (cyg_uint32) ((text_size + bucket_size - 1) / bucket_size);
+//		    profile_hist_hdr.low_pc     = _start;
+//		    profile_hist_hdr.high_pc    = (void*)((cyg_uint8*)_end - 1);
+//		    // The prof_rate is the frequency in hz. The resolution argument is
+//		    // an interval in microseconds.
+//		    profile_hist_hdr.prof_rate  = 1000000 / resolution;
+//		        
+//		    // Now allocate a buffer for the histogram data.
+//		    profile_hist_data = (cyg_uint16*) malloc(profile_hist_hdr.hist_size * sizeof(cyg_uint16));
+//		    if ((cyg_uint16*)0 == profile_hist_data) {
+//		        diag_printf("profile_on(): cannot allocate histogram buffer - ignored\n");
+//		        return;
+//		    }
+//		    memset(profile_hist_data, 0, profile_hist_hdr.hist_size * sizeof(cyg_uint16));
+			
+
+			
+//		    struct gmon_hist_hdr
+//		    {
+//		        /* host-side gprof adapts to sizeof(void*) and endianness.              */
+//		        /* It is assumed that the compiler does not insert padding around the   */
+//		        /* cyg_uint32's or the char arrays.                                     */
+//		        void*       low_pc;             /* base pc address of sample buffer     */
+//		        void*       high_pc;            /* max pc address of sampled buffer     */
+//		        cyg_uint32  hist_size;          /* size of sample buffer                */
+//		        cyg_uint32  prof_rate;          /* profiling clock rate                 */
+//		        char        dimen[15];			/* phys. dim., usually "seconds"        */
+//		        char        dimen_abbrev;		/* usually 's' for "seconds"            */
+//		    };
+			
+
+			// maximum 65536 buckets.
+			int length=memory.length*4;
+			if (length > 60000)
+			{
+				length=60000;
+			}
+			int buckets[]=new int[length];
+			for (long i=0; i<profile.length;i++)
+			{
+				buckets[(int)((i*(((long)buckets.length)-1))/(((long)profile.length)-1))]+=profile[(int)i];
+			}
+			
+			
+			
+			//			   append binary memory gmon.out &profile_hist_hdr ((char*)&profile_hist_hdr + sizeof(struct gmon_hist_hdr))
+			writeLong(b, 0); 					// low_pc
+			writeLong(b, memory.length*4);		// high_pc
+			writeLong(b, buckets.length);		// # of samples
+			writeLong(b, 64000000); 			// 64MHz
+			b.write("seconds".getBytes());
+			b.write(new byte[15-"seconds".length()]);
+			b.write("s".getBytes());
+			
+			
+			
+//			   append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size)
+			for (int i=0; i<buckets.length;i++)
+			{
+				int val;
+				val=buckets[i];
+				if (val>65535)
+				{
+					val=65535;
+				}
+				writeShort(b, val);
+			}
+			
+			OutputStream o=new FileOutputStream("gmon.out");
+			b.writeTo(o);
+			o.flush();
+			o.close();
+			
+		} catch (IOException e)
+		{
+			// TODO Auto-generated catch block
+			e.printStackTrace();
+		}
+		
+
+		
+	}
+
+
+	private void writeLong(ByteArrayOutputStream b, int i) throws IOException
+	{
+		int val=i;
+		b.write(new byte[]{(byte)((val>>24)&0xff),
+				(byte)((val>>16)&0xff),
+				(byte)((val>>8)&0xff),
+				(byte)((val>>0)&0xff)});
+	}
+
+
+	private void writeShort(ByteArrayOutputStream b, int i) throws IOException
+	{
+		int val=i;
+		b.write(new byte[]{	(byte)((val>>8)&0xff),
+				(byte)((val>>0)&0xff)});
+	}
+
+
+	private void dumpHistogram(long[] ms, long[] ms2)
+	{
+		List<OpcodeSample> l=new LinkedList();
+        
+        totalCycles = 0;
+		for (int i=0; i<256; i++)
+		{
+			totalCycles+=opcodeHistogramCycles[i];
+		}
+		for (int i=0; i<ms.length; i++)
+		{
+			final int j=i;
+			l.add(new OpcodeSample(j, ms2[j]));
+		}
+        Collections.sort(l, new Comparator()
+        {
+
+			public int compare(Object arg0, Object arg1)
+			{
+				OpcodeSample a=(OpcodeSample) arg0, b=(OpcodeSample) arg1;
+				if (a.count<b.count)
+				{
+					return 1;
+				} else if (a.count==b.count)
+				{
+					return 0;
+				} else
+				{
+					return -1;
+				}
+			}
+        });
+        
+        for (int i=0; i<ms.length; i++)
+		{
+        	if (totalCycles==0)
+        		break;
+			double d = ((double)l.get(i).count/((double)totalCycles));
+			if (d<0.005)
+				break;
+			double cycPerIns = ((double)ms2[l.get(i).j]/((double)ms[l.get(i).j]));
+			System.out.println("0x"+ Integer.toHexString(l.get(i).j) + " " + d + " " + l.get(i).count + " " + cycPerIns );
+		}
+	}
+
+
+    private void printRange(int from, int to)
+    {
+        int totalLoadSP=0;
+        for (int i=from; i<to; i++)
+        {
+            totalLoadSP+=opcodeHistogram[i];
+        }
+        
+ 		double d = ((double)totalLoadSP/((double)totalCycles));
+         
+        System.out.println(""+ from + " " + d + " " + totalLoadSP);
+    }
+
+
+//    private void printMemoryHistorgram()
+//    {
+//        Arrays.sort(profile, new Comparator()
+//                {
+//                    public int compare(Object o1, Object o2)
+//                    {
+//                        return (int)(((Profile)o2).counter-
+//                                ((Profile)o1).counter);
+//                    }
+//                });
+//        System.err.println("Profiling information");
+//        for (int i=0; i<1000; i++)
+//        {
+//            if (profile[i].counter==0)
+//            {
+//                break;
+//            }
+//            System.err.println("0x"+Integer.toHexString(profile[i].address)+ " " + profile[i].counter);
+//        }
+//    }
+
+
+	/**
+	 * notify everybody that we are powering down
+	 */
+	public void shutdown()
+	{
+		powerdown=true;
+		/* wake up */
+		synchronized(halt)
+		{
+			halt.notify();
+		}
+	}
+
+
+	/**
+	 * This method can be invoked in two cases:
+	 * 
+	 * a) while the CPU is running on the simulator thread
+	 * b) while the CPU is halted from other threads
+	 */
+	protected void resetHardwareInternal() throws CPUException
+	{
+		interrupt=false;
+		timer=false;
+		lastTimer=0;
+		hitVector=false;
+		instructionCount=0;
+		for (int i=0; i<memory.length; i++)
+        {
+        	memory[i]=0;
+        }
+		
+		setPcToVector(VECTOR_RESET); // starting address
+        startStack=getStartStack();
+        minStack=startStack;
+		changeSp(startStack);
+		
+        intSp=0;
+
+	}
+
+
+	private void instructionLoop() throws EndSessionException, CPUException
+	{
+        /* wait for connection.... */
+        for (;;)
+        {
+            try
+            {
+
+                /*
+                 * execute an instruction.
+                 * 
+                 * If an exception happens while executing the instruction,
+                 * invoke the approperiate exception vector.
+                 * 
+                 * If a second exception occurs while invoking the
+                 * exception(i.e. before the first instruction of the vector
+                 * is executed), invoke the reboot exception.
+                 */
+                executeInstruction();
+            } catch (DebuggerBreakpointException e1)
+            {
+                suspend();
+            } catch (InterruptException e1)
+            {
+                armVector(VECTOR_INTERRUPT);
+            } catch (IllegalInstructionException e1)
+            {
+                suspend();
+            } catch (MemoryAccessException e1)
+            {
+                suspend();
+            } catch (CPUException e)
+            {
+                suspend();
+            } catch (GDBServerException e)
+            {
+                suspend();
+            }  catch (IOException e)
+            {
+                e.printStackTrace();
+                suspend();
+            } catch (RuntimeException e)
+            {
+                e.printStackTrace();
+                suspend();
+            } finally
+            {
+                checkCommit();
+            } 
+        }
+	}
+
+
+	private void armVector(int vector) 
+	{
+		// for now we always break as soon as we hit a vector
+		if (vector!=VECTOR_INTERRUPT)
+		{
+		//	print(MINIMAL, "Vector " + vector + " armed at PC: " + formatHex(pc, "00000000"));
+			suspend();
+		}
+		hitVector=true;
+		nextVector=vector;
+	}
+
+	private void checkVector() throws CPUException
+	{
+		if (hitVector)
+		{
+			hitVector=false;
+			invokeVector(nextVector);
+		}
+	}
+
+
+	private void invokeVector(int vector) throws CPUException 
+	{
+		push(pc);
+		setPcToVector(vector);
+	}
+
+	private void setPcToVector(int vector) throws MemoryAccessException
+	{
+		setPc(VECTORSIZE*vector+VECTORBASE);
+	}
+
+	private void executeInstruction() throws CPUException, EndSessionException, GDBServerException, IOException
+	{
+        for (;;)
+        {
+            checkHalt();
+            
+            /* jump to any armed vector */
+            checkVector();
+
+            checkInterrupts();
+            
+            tracer.instructionEvent();
+
+            
+            
+            
+            
+            commit = false;
+            savedSp=getSp();
+            savedPc=pc;
+            savedDecodeMask=decodeMask;
+            touchedPc=false;
+            
+            instruction=cpuReadByte(pc);
+            // electrons perish each time we attempt an instruction
+            tick();
+            
+            if (((instruction&0x80)!=0))
+            {
+                int t=((instruction<<(32-7)))>>(32-7);
+                
+                if (decodeMask)
+                {
+                    int a;
+                    a=(popIntStack()<<7)|(t&0x7f);
+                    pushIntStack(a);
+                } else
+                {
+                    pushIntStack(t);
+                }
+                decodeMask=true;
+            } else
+            {
+                decodeMask = false;
+                if (isAddSP(instruction))
+                {
+                    int offset=instruction - ADDSP;
+                    int valAddr=sp+offset*4;
+                    int a = popIntStack();
+                    pushIntStack(cpuReadLong(valAddr) + a);
+                } else if ((instruction >= LOADSP) && (instruction < LOADSP + 32))
+                {
+                    int addr;
+                    addr = getSp();
+                    int offset=(instruction - LOADSP)^0x10;
+                    addr += 4 * offset;
+                    pushIntStack(cpuReadLong(addr));
+                } else if (isStoreSP(instruction))
+                {
+                    int addr;
+                    addr = getSp();
+                    int offset=(instruction - STORESP)^0x10;
+                    addr += 4 * offset;
+
+                    cpuWriteLong(addr, popIntStack());
+                } else
+                {
+                    int addr;
+                    int val;
+                    switch (instruction)
+                    {
+                    case 0:
+                        throw new DebuggerBreakpointException();
+    
+                    case PUSHPC:
+                        pushIntStack(pc);
+                        break;
+                    case OR:
+                        pushIntStack(popIntStack() | popIntStack());
+                        break;
+                    case NOT:
+                        pushIntStack(popIntStack() ^ 0xffffffff);
+                        break;
+                    case LOAD:
+                        pushIntStack(cpuReadLong(popIntStack()));
+                        break;
+                    case PUSHSPADD:
+                        if (feeble[PUSHSPADD])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a=sp;
+                            b=popIntStack()*4;
+                            pushIntStack(a+b);
+                        }
+                        break;
+                    case STORE:
+                        addr = popIntOrExt();
+                        val = popIntOrExt();
+                        cpuWriteLong(addr, val);
+                        break;
+                    case POPPC:
+                    {
+                    	// NB!!!! does NOT flush internal stack
+                    	int a;
+                        if (intSp>0)
+                        {
+                        	a=popIntStack();
+                        } else
+                        {
+                        	a=pop();
+                        }
+                        
+                        if ((sp>=emulateSp)&&(emulateInProgress))
+                        {
+                        	emulateInProgress=false;
+                        	/* we returned from an emulate instruction */
+                        	emulateOpcodeHistogram[emulateOpcode]++;
+                        	emulateOpcodeHistogramCycles[emulateOpcode]+=cycles-emulateCycles;
+                        }
+                        
+                        setPc(a);
+                        break;
+                    }
+                    case POPPCREL:
+                        if (feeble[POPPCREL])
+                        {
+                            emulate();
+                        } else
+                        {
+                        	setPc(popIntStack()+getPc());
+                        }
+                        break;
+                    case FLIP:
+                        pushIntStack(flip(popIntStack()));
+                        break;
+                    case ADD:
+                        pushIntStack(popIntStack() + popIntStack());
+                        break;
+                    case SUB:
+                        if (feeble[SUB])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a=popIntStack();
+                            int b=popIntStack();
+                            pushIntStack(b-a);
+                        }
+                        break;
+                    case PUSHSP:
+                        pushIntStack(getSp());
+                        break;
+                    case POPSP:
+                        changeSp(popIntStack());
+                    	intSp=0;	// flush internal stack
+                        break;
+                    case NOP:
+                        break;
+                    case AND:
+                        pushIntStack(popIntStack() & popIntStack());
+                        break;
+                    case XOR:
+                        if (feeble[XOR])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(popIntStack() ^ popIntStack());
+                        }
+                        break;
+                    case LOADB:
+                        if (feeble[LOADB])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(cpuReadByte(popIntStack()));
+                        }
+                        break;
+                    case STOREB:
+                        if (feeble[STOREB])
+                        {
+                            emulate();
+                        } else
+                        {
+                            addr = popIntStack();
+                            val = popIntStack();
+                            cpuWriteByte(addr, val);
+                        }
+                        break;
+                    case LOADH:
+                        if (feeble[LOADH])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(cpuReadWord(popIntStack()));
+                        }
+                        break;
+                    case STOREH:
+                        if (feeble[STOREH])
+                        {
+                            emulate();
+                        } else
+                        {
+                            addr = popIntStack();
+                            val = popIntStack();
+                            cpuWriteWord(addr, val);
+                        }
+                        break;
+                    case LESSTHAN:
+                        if (feeble[LESSTHAN])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a = popIntStack();
+                            b = popIntStack();
+                            pushIntStack((a < b) ? 1 : 0);
+                        }
+                        break;
+                    case LESSTHANOREQUAL:
+                        if (feeble[LESSTHANOREQUAL])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a = popIntStack();
+                            b = popIntStack();
+                            pushIntStack((a <= b) ? 1 : 0);
+                        }
+                        break;
+                    case ULESSTHAN:
+                        if (feeble[ULESSTHAN])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long a;
+                            long b;
+                            a = ((long) popIntStack()) & INTMASK;
+                            b = ((long) popIntStack()) & INTMASK;
+                            pushIntStack((a < b) ? 1 : 0);
+                        }
+                        break;
+                    case ULESSTHANOREQUAL:
+                        if (feeble[ULESSTHANOREQUAL])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long a;
+                            long b;
+                            a = ((long) popIntStack()) & INTMASK;
+                            b = ((long) popIntStack()) & INTMASK;
+                            pushIntStack((a <= b) ? 1 : 0);
+                        }
+                        break;
+    
+                    case SWAP:
+//                      if (feeble[SWAP])
+//                      {
+//                          emulate();
+//                      } else
+                      {
+                          int swapVal=popIntStack();;
+                          pushIntStack(((swapVal >>16)&0xffff)|(swapVal<<16));
+                      }
+                      break;
+                    case MULT16X16:
+//                      if (feeble[SWAP])
+//                      {
+//                          emulate();
+//                      } else
+                      {
+                        int a=popIntStack();
+                        int b=popIntStack();
+                        pushIntStack((a&0xffff)*(b&0xffff));
+                      }
+                      break;
+                    case EQBRANCH:
+                        if (feeble[EQBRANCH])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int compare;
+                            int target;
+                            target = popIntStack() + pc;
+                            compare = popIntStack();
+                            if (compare == 0)
+                            {
+                                setPc(target);
+                            } else
+                            {
+                                setPc(pc + 1);
+                            }
+                        }
+                        break;
+    
+                    case NEQBRANCH:
+                        if (feeble[NEQBRANCH])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int compare;
+                            int target;
+                            target = popIntStack() + pc;
+                            compare = popIntStack();
+                            if (compare != 0)
+                            {
+                                setPc(target);
+                            } else
+                            {
+                                setPc(pc + 1);
+                            }
+                        }
+                        break;
+    
+                    case MULT:
+                        if (feeble[MULT])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(popIntStack() * popIntStack());
+                        }
+                        break;
+                    case DIV:
+                        if (feeble[DIV])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a = popIntStack();
+                            b = popIntStack();
+                            if (b == 0)
+                            {
+                                throw new CPUException();
+                            }
+                            pushIntStack(a / b);
+                        }
+                        break;
+                    case MOD:
+                        if (feeble[MOD])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a = popIntStack();
+                            b = popIntStack();
+                            if (b == 0)
+                            {
+                                throw new CPUException();
+                            }
+                            pushIntStack(a % b);
+                        }
+                        break;
+    
+                    case LSHIFTRIGHT:
+                        if (feeble[LSHIFTRIGHT])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long shift;
+                            long valX;
+                            int t;
+                            shift = ((long) popIntStack()) & INTMASK;
+                            valX = ((long) popIntStack()) & INTMASK;
+                            t = (int) (valX >> (shift & 0x3f));
+                            pushIntStack(t);
+                        }
+                        break;
+    
+                    case ASHIFTLEFT:
+                        if (feeble[ASHIFTLEFT])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long shift;
+                            long valX;
+                            shift = ((long) popIntStack()) & INTMASK;
+                            valX = ((long) popIntStack()) & INTMASK;
+                            int t = (int) (valX << (shift & 0x3f));
+                            pushIntStack(t);
+                        }
+                        break;
+    
+                    case ASHIFTRIGHT:
+                        if (feeble[ASHIFTRIGHT])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long shift;
+                            int valX;
+                            shift = ((long) popIntStack()) & INTMASK;
+                            valX = popIntStack();
+                            int t = valX >> (shift & 0x3f);
+                            pushIntStack(t);
+                        }
+                        break;
+    
+                    case CALL:
+                        if (feeble[CALL])
+                        {
+                            emulate();
+                        } else
+                        {
+                        	intSp=0;	// flush internal stack
+                            int address = pop();
+                            push(pc + 1);
+                            setPc(address);
+                        }
+                        break;
+                    case CALLPCREL:
+                        if (feeble[CALLPCREL])
+                        {
+                            emulate();
+                        } else
+                        {
+                        	intSp=0;	// flush internal stack
+                            int address = pop();
+                            push(pc + 1);
+                            setPc(address+pc);
+                        }
+                        break;
+    
+                    case EQ:
+                        if (feeble[EQ])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack((popIntStack() == popIntStack()) ? 1 : 0);
+                        }
+                        break;
+    
+                    case NEQ:
+                        if (feeble[NEQ])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack((popIntStack() != popIntStack()) ? 1 : 0);
+                        }
+                        break;
+    
+                    case NEG:
+                        if (feeble[NEG])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(-popIntStack());
+                        }
+                        break;
+    
+                        
+                        case CONFIG:
+                        if (emulateConfig())
+                        {
+                            emulate();
+                            cpu=ABEL;
+                        } else
+                        {
+                            cpu = popIntStack();
+                        }
+                        switch (cpu)
+                        {
+                        case ABEL:
+                            System.err.println("ZPU feeble instruction set");
+                            for (int i = 0; i < feeble.length; i++)
+                            {
+                                feeble[i] = true;
+                            }
+
+                            setFeeble(); 
+                            
+                            break;
+                        case ZETA:
+                            System.err.println("ZPU full instruction set");
+                            for (int i = 0; i < feeble.length; i++)
+                            {
+                                feeble[i] = false;
+                            }
+                            break;
+                        default:
+                            break;
+                        }
+                        break;
+                        
+                    case SYSCALL:
+                        if (feeble[SYSCALL])
+                        {
+                            throw new IllegalInstructionException();
+                        } else
+                        {
+                        	intSp=0;	// flush internal stack
+                            syscall.syscall(this);
+                        }
+                        break;
+                            
+                    default:
+                        throw new IllegalInstructionException();
+                    }
+                }
+            }
+            if (!touchedPc)
+            {
+                setPc(pc + 1);
+            }
+            committed();
+            
+            // one more instruction retired
+            instructionCount++;
+        }
+	}
+
+
+	protected void setFeeble()
+	{
+		feeble[NEQBRANCH] = false;
+		feeble[EQ] = false;
+		feeble[LOADB] = false;
+		feeble[LESSTHAN] = false;
+		feeble[ULESSTHAN] = false;
+		feeble[STOREB] = false;
+		feeble[MULT] = false;
+		feeble[CALL] = true;
+		feeble[POPPCREL] = true;
+		feeble[LESSTHANOREQUAL] = true;
+		feeble[ULESSTHANOREQUAL] = true;
+
+		feeble[PUSHSPADD] = false;
+		feeble[CALLPCREL] = false;
+		feeble[SUB] = false;
+	}
+
+
+	private int popIntOrExt()
+	{
+		int a;
+		if (intSp==0)
+		{
+			a=pop();
+		} else
+		{
+			a=popIntStack();
+		}
+		return a;
+	}
+
+	int intSp;
+
+	private int emulateSp;
+
+	private int emulateOpcode;
+
+	private boolean emulateInProgress;
+
+	protected boolean timerPending;
+
+	private boolean inInterrupt;
+    private int popIntStack()
+	{
+//    	if (intSp<=0)
+//    		throw new IllegalInstructionException();
+    	intSp--;
+    	return pop();
+	}
+    
+    private void pushIntStack(int x)
+	{
+//    	if (intSp>=32)
+//    		throw new IllegalInstructionException();
+    	push(x);
+    	intSp++;
+	}
+
+
+
+    private static boolean isAddSP(int instruction)
+    {
+        return (instruction >= ADDSP) && (instruction < ADDSP + 16);
+    }
+
+
+    private static boolean isStoreSP(int instruction)
+    {
+        return (instruction >= STORESP) && (instruction < STORESP + 32);
+    }
+
+
+    protected boolean emulateConfig()
+    {
+        return false;
+    }
+
+
+    private void checkCommit() throws CPUException
+    {
+        if (!commit)
+        {
+            decodeMask=savedDecodeMask;
+            pc=savedPc;
+            setSp(savedSp);
+            committed();
+        }
+    }
+
+
+    private void committed()
+    {
+        commit=true;
+        tracer.commit();
+    }
+
+
+    private void emulate() throws CPUException
+	{
+    	// NB! Do NOT flush internal stack
+//    	intSp=0;	// flush internal stack
+        /* three total overhead to emulate instruction */
+    	if (!emulateInProgress)
+    	{
+    		emulateInProgress=true;
+	    	emulateSp = sp;
+	    	emulateOpcode = getOpcode();
+	    	emulateCycles = cycles;
+    	}
+		pushIntStack(pc+1);
+		setPc((cpuReadByte(pc)-32)*VECTORSIZE+VECTORBASE);
+	}
+
+
+
+	private void checkInterrupts() throws InterruptException
+	{
+		if (!tracer.simInterrupt())
+		{
+			/* These flags are set *regardless* of interrupt state. */
+			while (lastTimer+timerInterval<cycles)
+			{
+				if (timerInterval>0)
+				{
+					lastTimer+=timerInterval;
+				} else
+				{
+					lastTimer=cycles;
+				}
+				timerPending=true;
+			}
+		}
+		
+		if (!interrupt)
+			return;
+		
+        /* if we are in the middle of decoding an instruction, no interrupt */
+        if (decodeMask)
+        {
+        	return;
+        }
+        if (tracer.simInterrupt())
+        {
+    		if (!tracer.onInterrupt())
+    		{
+    			inInterrupt=false;
+    		}
+    		if (inInterrupt)
+    		{
+    			return;
+    		}
+            /* Use trace information instead of trying to figure out when an interrupt happens. We don't try
+             * to simulate anything more complicated than timer interrupts so we don't need to worry about source.
+             */
+            
+    		if (tracer.onInterrupt()&&!inInterrupt)
+    		{
+    			if (!timer)
+    			{
+    				throw new IllegalInstructionException();
+    			}
+    			
+    			inInterrupt=true;
+    			timerPending=true;
+    			throw new InterruptException();
+    		}
+            
+        } else
+        {
+    		if (!timerPending)
+    			inInterrupt=false;
+    		
+    		if (inInterrupt)
+    		{
+    			return;
+    		}
+            
+    		if (timer&&timerPending)
+    		{
+    			inInterrupt=true;
+    			throw new InterruptException();
+    		}
+        }
+	}
+
+
+
+	
+	private void cpuWriteWord(int addr, int val) throws MemoryAccessException
+	{
+		if ((addr&0x1)!=0)
+		{
+			throw new MemoryAccessException();
+		}
+		for (int i=0; i<2; i++)
+		{
+			writeByte(addr+i, val>>(8*(1-i)));
+		}
+	}
+
+	/**
+     * @param i
+     * @return
+     * @throws MemoryAccessException
+     */
+	private int cpuReadWord(int addr) throws MemoryAccessException
+	{
+		if ((addr&0x1)!=0)
+		{
+			throw new MemoryAccessException();
+		}
+		return ((readByteInternal(addr+0)&0xff)<<8) | (readByteInternal(addr+1)&0xff);
+	}
+
+	private void cpuWriteByte(int addr, int val) throws MemoryAccessException
+	{
+		writeByte(addr, val);
+	}
+
+
+	protected boolean interrupt;
+	protected long timerInterval;
+    private boolean touchedPc;
+
+	private boolean accessWatchPoint;
+
+	private int accessWatchPointAddress;
+
+	private int accessWatchPointLength;
+
+    private boolean commit;
+
+    private boolean savedDecodeMask;
+
+    private int savedSp;
+
+    private int savedPc;
+
+    private long[] profile;
+
+    private int cpu;
+
+    private long sampledCycle;
+
+    private Tracer tracer=new Tracer()
+    {
+
+        public void instructionEvent()
+        {
+            
+        }
+
+        public void commit()
+        {
+        }
+
+        public void setSp(int sp)
+        {
+        }
+
+		public void dumpTraceBack()
+		{
+			
+		}
+
+		public boolean onInterrupt()
+		{
+			return false;
+		}
+
+		public boolean simInterrupt()
+		{
+			return false;
+		}
+        
+    };
+
+    private int instruction;
+
+	private long totalCycles;
+
+	
+	private String traceFileName;
+
+	private int prevOpcode;
+
+	private long prevCycles2;
+
+	private int prevOpcode2;
+
+
+	
+
+	/**
+	 * checks if the CPU should halt, and halts. Fn. returns when the
+	 * CPU has resumed execution.
+	 * @throws EndSessionException 
+	 */
+	private void checkHalt() throws EndSessionException
+	{
+		synchronized(halt)
+		{
+			if (powerdown)
+			{
+				throw new EndSessionException();
+			}
+			
+			if (breakNext)
+			{
+				breakNext=false;
+				
+				halt.notify();
+				try
+				{
+					syscall.halted();
+					halt.wait();
+					syscall.running();
+				} catch (InterruptedException e)
+				{
+					e.printStackTrace();
+				}
+			}
+			
+			if (powerdown)
+			{
+				throw new EndSessionException();
+			}
+		}
+	}
+
+	private int flip(int i)
+	{
+		int t=0;
+		for (int j=0; j<32; j++)
+		{
+			t|=((i>>j)&1)<<(31-j);
+		}
+		return t;
+	}
+
+	/** the CPU is writing a long during execution */
+	public void cpuWriteLong(int addr, int val) throws MemoryAccessException
+	{
+		if (accessWatchPoint&&(addr==accessWatchPointAddress))
+		{
+			suspend();
+		}
+        if ((addr&0x3)!=0)
+        {
+            throw new MemoryAccessException();
+        }
+		if ((addr>=getIO())&&(addr<getIO()+IOSIZE))
+		{
+			ioWrite(addr, val);
+		} else if ((addr>=0)&&(addr<=memory.length*4))
+		{
+			memory[addr/4]=val;
+			validMemory[addr/4]=true;
+		} else
+        {
+            throw new MemoryAccessException();
+        }
+	}
+
+	public void writeByte(int addr, int val) throws MemoryAccessException
+	{
+		if ((addr>=0)&&(addr<memory.length*4))
+		{
+			memory[addr/4]=(memory[addr/4]&(~(0xff<<((3-addr&3)*8))))|((val&0xff)<<((3-addr&3)*8));
+		} else 
+		{
+			throw new MemoryAccessException();
+		}
+	}
+
+	protected void ioWrite(int addr, int val) throws MemoryAccessException
+	{
+        addr-=getIO();
+		/* note, big endian! */
+		switch (addr)
+		{
+			case 12:
+                syscall.writeUART(val);
+				break;
+			case 20:
+				interrupt=val!=0;
+				break;
+			case 28:
+				timerInterval=val;
+				break;
+			case 32:
+				timer=val!=0;
+				break;
+            case 0x24:
+                syscall.writeUART(val);
+                break;
+            case 0x100:
+                writeTimerSampleReg(val);
+                break;
+			default:
+                break;
+		}
+		
+	}
+
+
+
+
+    protected void writeTimerSampleReg(int val)
+    {
+        if ((val&0x2)!=0)
+        {
+            sampledCycle=getSampleOffset(); // we need a fudge factor to make up for differences in when relative to the instruction the data is sampled.
+        }
+    }
+
+
+	protected long getSampleOffset()
+	{
+		return cycles+2+0xd-(0x8e-0x74);
+	}
+	
+
+
+    protected int ioRead(int addr) throws CPUException
+	{
+        addr-=getIO();
+		/* note, big endian! */
+		switch (addr)
+		{
+			case 20:
+				return interrupt?1:0;
+				
+			case 32:
+				return timer?1:0;
+			
+            case 0x24:
+                return syscall.readUART();
+                
+                /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+            case 0x28:
+                return syscall.readFIFO();
+                
+            case 0x100:
+            case 0x104:
+            case 0x108:
+            case 0x10c:
+                
+            case 0x110:
+            case 0x114:
+            case 0x118:
+            case 0x11c:
+            return readSampledTimer(addr, 0x100);
+            
+            case 0x200:
+                return readMHz();
+                
+			default:
+				throw new MemoryAccessException();
+		}
+	}
+
+
+
+
+    protected int readMHz()
+    {
+        /* 90 MHz */
+        return 100;
+    }
+
+
+    protected int readSampledTimer(int addr, int base)
+    {
+        int t=0;
+        t=(int)((sampledCycle>>(((addr-base)/4)*32))&0xffffffff);
+        return t;
+    }
+
+
+
+	private int cpuReadByte(int addr) throws MemoryAccessException
+	{
+		return readByteInternal(addr);
+	}
+
+	
+	/** this is the CPU reading a long word during execution */
+	public int cpuReadLong(int addr) throws CPUException
+	{
+		if (accessWatchPoint&&(addr==accessWatchPointAddress))
+		{
+			suspend();
+		}
+		if ((addr&0x3)!=0)
+		{
+			throw new MemoryAccessException();
+		}
+		if ((addr>=getIO())&&(addr<getIO()+IOSIZE))
+		{
+			return ioRead(addr);
+		} else  if ((addr>=0)&&(addr<=memory.length*4))
+		{
+			return memory[addr/4];
+		} else
+        {
+            throw new MemoryAccessException();
+        }
+	}
+
+	/**
+	 * Causes a cycle to pass.
+	 * @throws MemoryAccessException 
+	 */
+	/** increase time and record how long we spent on this instruction */
+    private void tick() throws MemoryAccessException
+    {
+        profile[pc]++;
+        int opcode;
+        opcode=readByte(pc);
+        opcodeHistogram[prevOpcode]++;
+        opcodeHistogramCycles[prevOpcode]+=cycles-prevCycles;
+        int opcodePair=groupOpcode(prevOpcode2)*256+groupOpcode(prevOpcode);
+
+        opcodePairHistogram[opcodePair]++;
+        opcodePairHistogramCycles[opcodePair]+=cycles-prevCycles2;
+
+        prevOpcode2=prevOpcode;
+        prevOpcode=opcode;
+        
+        
+        
+        prevCycles2=prevCycles;
+        prevCycles=cycles;
+		cycles++;
+    }
+
+    private int groupOpcode(int instruction)
+	{
+        if (isAddSP(instruction))
+        {
+        	return ADDSP;
+        } else if ((instruction >= LOADSP) && (instruction < LOADSP + 32))
+        {
+        	return LOADSP;
+        } else if (isStoreSP(instruction))
+        {
+        	return STORESP;
+        }
+
+    	if ((instruction&0x80)!=0)
+    		return 0x80;
+    	return instruction;
+	}
+
+
+	public int readByte(int addr) throws MemoryAccessException
+	{
+		if ((addr>=0)&&(addr<memory.length*4))
+		{
+			return readByteInternal(addr);
+		} else
+		{
+			throw new MemoryAccessException();
+		}
+	}
+
+    
+	protected int readByteInternal(int addr) throws MemoryAccessException
+	{
+		return (memory[addr/4]>>((3-addr&0x3)*8))&0xff;
+	}
+
+	private int pop() throws CPUException
+	{
+		int val;
+		validMemory[getSp()/4]=false;
+		val=cpuReadLong(getSp());
+		setSp(getSp() + 4);
+		return val;
+	}
+
+	private void push(int imm) throws CPUException
+	{
+		setSp(getSp() - 4);
+		cpuWriteLong(getSp(), imm);
+	}
+
+    private  final class OpcodeSample
+	{
+		private final int j;
+
+		int opcode;
+
+		long count;
+
+		private OpcodeSample(int j, long l)
+		{
+			this.j = j;
+			opcode = j;
+			count = l;
+		}
+	}
+
+
+    
+
+	private void initRam()
+	{
+		memory = (new int[getRAMSIZE()/4]);
+		validMemory = new boolean[getRAMSIZE()/4];
+		for (int i=0; i<validMemory.length; i++)
+		{
+			validMemory[i]=true;
+		}
+		
+        profile = new long[getRAMSIZE()];
+	}
+
+	
+	
+	public void setPc(int pc) throws MemoryAccessException
+	{
+		if ((pc<VECTORBASE)||(pc>memory.length*4))
+		{
+			throw new MemoryAccessException();
+		}
+		this.pc = pc;
+        touchedPc=true;
+	}
+
+	public int getPc()
+	{
+		return pc;
+	}
+
+	/** resume execution. This function returns when the CPU halts again. */
+	public void cont()
+	{
+        for (;;)
+        {
+    		synchronized(halt)
+    		{
+    			halt.notify();
+    			try
+    			{
+    				halt.wait();
+    			} catch (InterruptedException e)
+    			{
+    				e.printStackTrace();
+    			}
+    		}
+            if (syscall.doneContinue())
+            {
+                    break;
+            }
+        }
+	}
+	
+    /** resume execution. This function returns when the CPU halts again. */
+	public void step()
+	{
+		synchronized(halt)
+		{
+			suspend();
+			cont();
+		}
+	}
+	
+
+	
+	public int getReg(int regNum) throws CPUException
+	{
+		if ((regNum>=0)&&(regNum<32))
+		{
+           	return memory[regNum];
+		} else if (regNum==32)
+		{
+			return getSp();
+		} else if (regNum==33)
+		{
+			return pc;
+		} else
+		{
+			throw new RuntimeException("Illegal getReg()");
+		}
+	}
+
+	public int getREGNUM()
+	{
+		return 34;
+	}
+
+	public long getCycleCounter()
+	{
+		return cycles;
+	}
+
+	public void addWaitStates(int num)
+	{
+	}
+
+	/** tells simulator to enter the suspended state */
+	public void suspend()
+	{
+		synchronized(halt)
+		{
+		    breakNext=true;
+		}
+//		tracer.dumpTraceBack();
+	}
+
+
+    public long getPrevCycles()
+    {
+        return prevCycles;
+    }
+
+    public long getCycles()
+    {
+        return cycles;
+    }
+
+
+	public void enableAccessWatchPoint(int address, int length) throws CPUException 
+	{
+		if (accessWatchPoint)
+		{
+			throw new HardwareWatchPointException();
+		}
+		accessWatchPointAddress=address;
+		accessWatchPointLength=length;
+		accessWatchPoint=true;
+	}
+	public void disableAccessWatchPoint(int address, int length) throws CPUException 
+	{
+		if (!accessWatchPoint)
+		{
+			throw new HardwareWatchPointException();
+		}
+		if ((address!=accessWatchPointAddress)||(length!=accessWatchPointLength))
+		{
+			throw new HardwareWatchPointException();
+		}
+		
+		accessWatchPoint=false;
+	}
+
+	/** POPSP changes the stack pointer */
+    public void changeSp(int sp) throws CPUException 
+    {
+        setSp(sp);
+        tracer.setSp(sp);
+    }
+
+    public void setSp(int sp) throws CPUException
+    {
+        if ((sp%4)!=0)
+        {
+            throw new IllegalInstructionException();
+        }
+        
+        if (sp<minStack)
+        {
+            minStack=sp;
+        }
+        
+        
+        this.sp = sp;
+    }
+
+
+    public int getSp()
+    {
+        return sp;
+    }
+    public int getIntSp()
+    {
+        return (intSp+(INTSTACKSIZE-1))%INTSTACKSIZE;
+    }
+
+
+    
+
+    protected int getIO()
+    {
+        return 0x80000000;
+    }
+
+
+    protected int getRAMSIZE()
+    {
+        return (16*1024*1024);
+    }
+
+    protected int getStartStack()
+    {
+        return memory.length*4-0x10000;
+    }
+
+
+    public void setTraceFile(String string)
+    {
+    	traceFileName=string;
+    }
+
+
+    public void setSyscall(Host syscall)
+    {
+        this.syscall=syscall;
+    }
+
+
+    public void loadImage(InputStream inputStream, int length) throws IOException, CPUException
+    {
+    	if (length==-1)
+    		throw new IOException("File image length not known");
+    	for (int i=0; i<length; i++)
+    	{
+		    int t=inputStream.read();
+		    writeByte(0+i, t);
+		} 
+        
+    }
+
+    public int getArg(int num) throws CPUException
+    {
+        return cpuReadLong(getSp()+4+num*4);
+    }
+
+
+	public int getOpcode() throws MemoryAccessException
+	{
+		return readByte(pc);
+	}
+
+	static final int INTSTACKSIZE=32;
+
+	public boolean checkMatch(Trace trace)
+	{
+		cycles=trace.cycle;
+		if (!trace.undefinedIntSp)
+		{
+			if (trace.intSp!=((intSp+(INTSTACKSIZE-1))%INTSTACKSIZE))
+				return false;
+		}
+		
+		if ((getPc() != trace.pc) || (getSp() != trace.sp)
+				|| (getOpcode() != trace.opcode))
+		{
+			return false;
+		}
+	    
+		if (cpuReadLong(getSp()) == trace.stackA)
+		{
+			if (cpuReadLong(getSp() + 4) == trace.stackB)
+			{
+				return true;
+			}
+		}
+		if ((!validMemory[getSp()/4])||cpuReadLong(getSp()) == trace.stackA)
+		{
+			if ((!validMemory[(getSp()+4)/4])||cpuReadLong(getSp() + 4) == trace.stackB)
+			{
+//				System.out.println("Undefined memory location mismatch");
+				return true;
+			}
+		}
+		if (!trace.undefinedIntSp)
+		{
+			if ((intSp<1)||cpuReadLong(getSp()) == trace.stackA)
+			{
+				if ((intSp<2)||cpuReadLong(getSp() + 4) == trace.stackB)
+				{
+					return true;
+				}
+			}
+		}
+	    return false;
+	}
+
+
+	public void sessionStarted()
+	{
+		if (traceFileName!=null)
+		{
+			tracer = new FileTracer(this, traceFileName);
+		}
+
+		/* Set the feeble flag to enable/disable instructions here */
+		initRam();
+		resetHardwareInternal();			
+
+
+		
+	}
+
+
+	void printState(FileTracer fileTracer)
+	{
+		System.err.println("intSp: " + getIntSp());
+		System.err.println(Integer.toHexString(getPc())+ " " +
+		Integer.toHexString(getOpcode()) + " " +
+		Integer.toHexString(getSp()) + " " + 
+		Integer.toHexString(cpuReadLong(getSp())) + " " + 
+		Integer.toHexString(cpuReadLong(getSp()+4)));
+	}
+
+
+	
+	
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/State.java b/zpu/sw/simulator/com/zylin/zpu/simulator/State.java
new file mode 100644
index 0000000..c2cb9f4
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/State.java
@@ -0,0 +1,9 @@
+package com.zylin.zpu.simulator;
+
+
+public class State
+{
+
+	public long cycle;
+	public int insn;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java
new file mode 100644
index 0000000..31f1766
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java
@@ -0,0 +1,21 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+
+public interface Tracer
+{
+
+    void instructionEvent() throws GDBServerException;
+
+    void commit();
+
+    void setSp(int sp);
+    
+    void dumpTraceBack();
+
+    
+    boolean onInterrupt();
+    
+    boolean simInterrupt();
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java b/zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java
new file mode 100644
index 0000000..84a1ca5
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java
@@ -0,0 +1,14 @@
+package com.zylin.zpu.simulator;
+
+public interface ZPU
+{
+	/**
+	 * number of cycles passed since reboot
+	 */
+	long getCycleCounter();
+
+	/**
+	 * Wait this many cycles
+	 */
+	void addWaitStates(int i);
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java b/zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java
new file mode 100644
index 0000000..731c8fc
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java
@@ -0,0 +1,281 @@
+
+package com.zylin.zpu.simulator.applet;
+
+import java.applet.Applet;
+import java.awt.TextArea;
+import java.awt.event.KeyEvent;
+import java.awt.event.KeyListener;
+import java.io.IOException;
+import java.io.PipedInputStream;
+import java.io.PipedOutputStream;
+import java.lang.reflect.InvocationTargetException;
+import java.net.MalformedURLException;
+import java.net.URL;
+import java.net.URLConnection;
+
+import javax.swing.SwingUtilities;
+
+import com.zylin.zpu.simulator.Host;
+import com.zylin.zpu.simulator.Sim;
+import com.zylin.zpu.simulator.Simulator;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.UnsupportedSyscallException;
+
+public class ZPUApplet extends Applet implements Host
+{
+
+	private static final long serialVersionUID = 1L;
+	private TextArea console;
+    private Simulator simulator;
+	private PipedOutputStream outputPipe;
+	private PipedInputStream inputPipe;
+
+    public void init()
+    {
+        super.init();
+        
+        console=new TextArea();
+        //console.setEditable(false);
+
+        
+        console.addKeyListener(new KeyListener()
+                {
+
+                    public void keyPressed(KeyEvent e)
+                    {
+                    	try 
+                    	{
+							outputPipe.write((int)e.getKeyChar());
+						} catch (Throwable e1) 
+						{
+							e1.printStackTrace();
+						}
+                        
+                    }
+
+                    public void keyReleased(KeyEvent e)
+                    {
+                        
+                    }
+
+                    public void keyTyped(KeyEvent e)
+                    {
+                        
+                    }
+                });
+
+        //Add the text field to the applet.
+        add(console);
+
+        //Set the layout manager so that the text field will be
+        //as wide as possible.
+        setLayout(new java.awt.GridLayout(1,0));
+
+        validate();
+        initSimulator();
+        
+    }
+    
+    
+
+
+
+    public void start() 
+	{
+		super.start();
+	}
+
+
+
+
+
+	public void stop()
+    {
+        simulator.shutdown();
+        super.stop();
+    }
+
+    private void initSimulator()
+    {
+    	final ZPUApplet me = this;
+    	
+        try
+        {
+        	outputPipe = new PipedOutputStream();
+			inputPipe = new PipedInputStream(outputPipe);
+			
+			showStatus("Loading ZPU binary image...");
+
+			Thread thread = new Thread(new Runnable() {
+				public void run() {
+					try {
+						// lineReader=new LineNumberReader(new
+						// InputStreamReader(inputPipe));
+
+						simulator = new Simulator();
+						simulator.setSyscall(me);
+
+						String file = getParameter("executable");
+
+						URL url;
+						url = new URL(getCodeBase(), file);
+						showStatus("Loading: " + url.toString() +"...");
+
+						URLConnection connection = url.openConnection();
+						
+						simulator.loadImage(connection.getInputStream(), connection.getContentLength());
+
+						simulator.run();
+					} catch (Throwable e) {
+						e.printStackTrace();
+					}
+				}
+			});
+			thread.start();
+		} catch (MalformedURLException e) {
+            throw new RuntimeException(e);
+        } catch (IOException e)
+        {
+            throw new RuntimeException(e);
+        }
+    }
+
+    public void syscall(Sim s) throws CPUException
+    {
+        int retval=-1;
+        int syscallErrno=0;
+        int id;
+        id=simulator.getArg(1);
+        try
+        {
+	        switch (id)
+	        {
+	        case SYS_write:
+	            writeToConsole();
+	            retval=simulator.getArg(4);
+	            break;
+	        case SYS_read:
+	        	int i;
+	        	for (i=0; i<simulator.getArg(4); i++)
+	        	{
+	        		int t=inputPipe.read();
+        			simulator.writeByte(simulator.getArg(3)+i, t);
+        			if ((t=='\n')||(t=='\r'))
+        			{
+        				/* done reading line */
+        				i++;
+        				break;
+        			}
+	        	}
+	        	retval=i;
+	        	break;
+	        	
+	        case SYS_fstat:
+	        	syscallErrno=EIO;
+	        	retval=-1;
+	            break;
+	            
+	        default:
+	            simulator.suspend();
+	            throw new UnsupportedSyscallException();
+	        }
+        } 
+        catch (IOException e)
+        {
+            retval=-1;
+            syscallErrno=EIO;
+        }
+        simulator.cpuWriteLong(simulator.getArg(0), syscallErrno);
+        simulator.cpuWriteLong(0, retval);
+    }
+
+    private void writeToConsole() throws CPUException
+    {
+    	String t="";
+        for (int i=0; i<simulator.getArg(4); i++)
+        {
+        	t+=(char)simulator.readByte(simulator.getArg(3)+i);
+        }
+        final String t2=t;
+        System.out.println(t2);
+        try {
+			SwingUtilities.invokeAndWait(new Runnable()
+			        {
+			            public void run()
+			            {
+			                console.append(t2);
+			            }
+			        });
+		} catch (InterruptedException e) {
+			// TODO Auto-generated catch block
+			e.printStackTrace();
+		} catch (InvocationTargetException e) {
+			// TODO Auto-generated catch block
+			e.printStackTrace();
+		}
+    }
+
+
+
+
+    public boolean doneContinue()
+    {
+        return false;
+    }
+
+
+    public void writeUART(final int val)
+    {
+        try {
+			SwingUtilities.invokeAndWait(new Runnable()
+			        {
+
+			            public void run()
+			            {
+			                console.append(""+(char)(val));
+			                repaint();
+			                
+			            }
+			        });
+		} catch (InterruptedException e) {
+			e.printStackTrace();
+		} catch (InvocationTargetException e) {
+			e.printStackTrace();
+		}
+    }
+
+
+
+
+
+	public int readUART() throws CPUException 
+	{
+		try 
+		{
+			return inputPipe.read();
+		} catch (IOException e) 
+		{
+			e.printStackTrace();
+			throw new CPUException();
+		}
+	}
+
+
+
+
+
+	public int readFIFO() 
+	{
+		return 0;
+	}
+
+	public void halted()
+	{
+		showStatus("ZPU application halted");
+	}
+
+	public void running()
+	{
+		showStatus("ZPU application running...");
+	}
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java
new file mode 100644
index 0000000..2e66ab4
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java
@@ -0,0 +1,22 @@
+/*
+ * Created on Nov 6, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class BadPacketException extends GDBServerException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 3258131340821214260L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java
new file mode 100644
index 0000000..6a3f4fe
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on Oct 23, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class CPUException extends GDBServerException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+	
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java
new file mode 100644
index 0000000..2360fa8
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java
@@ -0,0 +1,10 @@
+package com.zylin.zpu.simulator.exceptions;
+
+public class DebuggerBreakpointException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
new file mode 100644
index 0000000..7dd27e0
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
@@ -0,0 +1,22 @@
+/*
+ * Created on Nov 16, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class EndSessionException extends Exception
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java
new file mode 100644
index 0000000..8232790
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java
@@ -0,0 +1,25 @@
+package com.zylin.zpu.simulator.exceptions;
+
+
+public class GDBServerException extends RuntimeException
+{
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+
+	public GDBServerException(NumberFormatException e)
+	{
+		super(e);
+	}
+
+	public GDBServerException()
+	{
+		
+	}
+
+    public GDBServerException(Exception e)
+    {
+        super(e);
+    }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java
new file mode 100644
index 0000000..a4ad3b2
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java
@@ -0,0 +1,12 @@
+
+package com.zylin.zpu.simulator.exceptions;
+
+public class HardwareWatchPointException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java
new file mode 100644
index 0000000..a8d0802
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on Oct 23, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class IllegalInstructionException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java
new file mode 100644
index 0000000..bd74f04
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on 02.jan.2005
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class InterruptException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java
new file mode 100644
index 0000000..4c9ebae
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on Oct 23, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class MemoryAccessException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java
new file mode 100644
index 0000000..377f9de
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java
@@ -0,0 +1,22 @@
+/*
+ * Created on Nov 6, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class NoAckException extends GDBServerException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java
new file mode 100644
index 0000000..45fda54
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java
@@ -0,0 +1,22 @@
+
+package com.zylin.zpu.simulator.exceptions;
+
+
+public class TraceException extends GDBServerException
+{
+
+    /**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+
+	public TraceException(Exception e)
+    {
+        super(e);
+    }
+
+    public TraceException()
+    {
+    }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java
new file mode 100644
index 0000000..af8a667
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java
@@ -0,0 +1,10 @@
+package com.zylin.zpu.simulator.exceptions;
+
+public class UnknownPacketException extends GDBServerException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java
new file mode 100644
index 0000000..6b214f1
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java
@@ -0,0 +1,12 @@
+
+package com.zylin.zpu.simulator.exceptions;
+
+public class UnsupportedSyscallException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
new file mode 100644
index 0000000..2580ded
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
@@ -0,0 +1,609 @@
+/** 
+ * Handles TCP/IP communication between simulator and GDB
+ */
+
+package com.zylin.zpu.simulator.gdb;
+
+import java.io.IOException;
+import java.nio.ByteBuffer;
+import java.nio.channels.SelectionKey;
+import java.nio.channels.Selector;
+import java.nio.channels.SocketChannel;
+import java.util.Iterator;
+
+import com.zylin.zpu.simulator.Host;
+import com.zylin.zpu.simulator.Sim;
+import com.zylin.zpu.simulator.SimApp;
+import com.zylin.zpu.simulator.exceptions.BadPacketException;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.EndSessionException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+import com.zylin.zpu.simulator.exceptions.UnsupportedSyscallException;
+
+public class GDBServer implements Host 
+{
+	static final boolean UNKNOWN=false;
+	static final boolean ALL=false;
+	static final boolean CPUEXCEPTION = false;
+	static protected boolean MINIMAL=true;
+	static boolean PACKET=false;
+	static boolean REPLY=false;
+	static protected boolean IGNOREDEXCEPTIONS=false;
+	protected Throwable packetException;
+	protected Object packetReady=new Object();
+	private Packet packet;
+	boolean done;
+	private Thread asyncMessage;
+	private Object listenBreak=new Object();
+	private boolean listenForBreak;
+	private boolean sleeping;
+	private ByteBuffer readBuffer;
+	private ByteBuffer writeBuffer;
+	private SocketChannel sc;
+	private Selector selectorRead;
+	private Selector selectorWrite;
+    public boolean alive;
+    static private int sessionNr;
+	private SimApp app;
+	private boolean stopAsyncMessage;
+    Sim simulator;
+    
+    public GDBServer(Sim simulator, SimApp app)
+    {
+        this.simulator=simulator;
+    	this.app=app;
+    }
+    
+	void print(boolean filter, String str)
+	{
+		if (filter)
+		{
+			System.out.println(str);
+		}
+	}
+	
+	/** infinite loop that waits for debug sessions to be initiated via TCP/IP */
+	public void gdbServer() throws MemoryAccessException, IOException, GDBServerException, EndSessionException 
+	{
+		try
+		{
+			asyncMessage = new Thread(new Runnable()
+			{
+				public void run()
+				{
+					asyncMessage();
+				}
+			});
+			asyncMessage.start();
+			try
+			{
+				readBuffer = ByteBuffer.allocate(1);
+				writeBuffer = ByteBuffer.allocate(128);
+				debugSession();
+			}
+			finally
+			{
+				/* tell it to stop waiting for break chars and wake up the thread */
+				stopAsyncMessage = true;
+				synchronized(listenBreak)
+				{
+					listenBreak.notify();
+				}
+				
+				try
+				{
+					asyncMessage.join();
+				} catch (InterruptedException e3)
+				{
+					e3.printStackTrace();
+				}
+			}
+		} catch (IOException e)
+		{
+			// the session failed...
+			if (IGNOREDEXCEPTIONS)
+			{
+				e.printStackTrace();
+			}
+		} catch (GDBServerException e)
+		{
+			// connect failed...
+			if (IGNOREDEXCEPTIONS)
+			{
+				e.printStackTrace();
+			}
+		} catch (EndSessionException e)
+		{
+		} catch (Throwable e)
+		{
+			// some terrible unforseen failure.
+			e.printStackTrace();
+		}
+	}
+
+	/**
+	 * We have to wait for break, but as soon as the main thread wants to wait
+	 * for packets again, we have to stop waiting for a break.
+	 * 
+	 * Tricky....
+	 */
+	private void asyncMessage()
+	{
+		for (;;)
+		{
+			synchronized(listenBreak)
+			{
+				if (stopAsyncMessage)
+				{
+					/* shutting down */
+					return;
+				}
+				try
+				{
+					sleeping=true;
+					listenBreak.notify();
+					
+					listenBreak.wait();
+					sleeping=false;
+					listenBreak.notify();
+				} catch (InterruptedException e)
+				{
+					e.printStackTrace();
+				}
+				if (stopAsyncMessage)
+				{
+					/* shutting down */
+					return;
+				}
+			}
+			
+			while (listenForBreak)
+			{
+				try
+				{
+					if (waitSelect(selectorRead, true))
+					{
+						int t = read();
+						if (t == 0x03)
+						{
+							// We received a ctrl-c while processing a package,
+							// this
+							// would be a suspend
+							simulator.suspend();
+						} else
+						{
+							// ignore garbage. Shouldn't happen.
+						}
+					} else
+					{
+						// we've been awoken since we're ready to send 
+						// the reply to the package...
+//						int x=0;
+					}
+				} catch (IOException e)
+				{
+					// Perfectly normal. This would happen if the connection
+					// is terminated.
+				}
+			}
+		}
+	}
+
+	/** wait for read/write ready */
+	private boolean waitSelect(Selector selector, boolean read) throws IOException
+	{
+		boolean gotit=false;
+		
+		selector.select(1000);
+		if (!sc.isOpen())
+		{
+			throw new IOException("Channel closed");
+		}
+		if (!sc.isConnected())
+		{
+			throw new IOException("Channel not connected");
+		}
+
+		// Get list of selection keys with pending events
+		Iterator it = selector.selectedKeys().iterator();
+		// Process each key at a time
+		while (it.hasNext())
+		{
+			// Get the selection key
+			SelectionKey selKey = (SelectionKey) it.next();
+			// Remove it from the list to indicate that it is being
+			// processed
+			it.remove();
+			if (selKey.isValid() && 
+					((read && selKey.isReadable()) || (!read && selKey.isWritable())))
+			{
+				gotit=true;
+			}
+			
+		}
+		return gotit;
+	}
+
+	
+	protected void sleepABit()
+	{
+		try
+		{
+			// just to avoid locking up the machine in a busy loop when
+			// debugging the Simulator
+			Thread.sleep(2000);
+		} catch (InterruptedException e1)
+		{
+			e1.printStackTrace();
+		}
+	}
+
+	private void debugSession() throws IOException, GDBServerException, EndSessionException, MemoryAccessException 
+	{
+		print(MINIMAL, "GDB server waiting for connection " + sessionNr++ + "...");
+
+		writeBuffer.clear();
+		readBuffer.clear();
+
+
+        selectorRead = Selector.open();
+        try
+        {
+            selectorWrite = Selector.open();
+            try
+            {
+				sc = app.channel.accept();
+		        try
+		        {
+		        	sc.socket().setKeepAlive(true);
+		            sc.configureBlocking(false);
+		            sc.register(selectorRead, SelectionKey.OP_READ);
+		            sc.register(selectorWrite, SelectionKey.OP_WRITE);
+		
+		            sessionStarted();
+		
+		            expect('+'); // connection ack.
+		
+		            sessionLoop();
+		        } finally
+		        {
+		            sc.close();
+		            
+					print(MINIMAL, "Session ended");
+		        }
+            } finally
+            {
+                selectorWrite.close();
+            }
+        } finally
+        {
+            selectorRead.close();
+        }
+	
+	}
+
+	private void sessionStarted()
+	{
+		simulator.sessionStarted();
+		print(MINIMAL, "Session started");
+	}
+
+	
+	private void sessionLoop() throws IOException, EndSessionException
+	{
+		alive=true;
+		while (alive)
+		{
+			try
+			{
+				/* wait for new packet to arrive and notify the packet execution thread... */
+				packet=new Packet(this);
+				packet.receive();
+		
+				enterListenForCtrlC();
+                
+				try
+				{
+					// During execution we can receive an abort/suspend command...
+					packet.parseAndExecute();
+				} 
+				finally
+				{
+					leaveListenForCtrlC();
+				}
+                
+				packet.sendReply();
+				
+				if (!alive)
+				    throw new EndSessionException();
+			} catch (BadPacketException e)
+			{
+				// do nothing.
+				if (IGNOREDEXCEPTIONS)
+				{
+					e.printStackTrace();
+				}
+				sleepABit();
+			} catch (GDBServerException e)
+			{
+				if (IGNOREDEXCEPTIONS)
+				{
+					e.printStackTrace();
+				}
+				// continue processing packets
+				sleepABit();
+			}
+		}
+	}
+
+    private void enterListenForCtrlC()
+    {
+        setBreakListen(true);
+    }
+
+    private void leaveListenForCtrlC()
+    {
+        /* we don't want to wait for the select to time out as that would make
+         * the protocol excruciatingly slow */
+        setBreakListen(false);
+        selectorRead.wakeup();
+        synchronized(listenBreak)
+        {
+        	try
+        	{
+        		while (!sleeping)
+        		{
+        			listenBreak.notify();
+        			listenBreak.wait();
+        		}
+        	} catch (InterruptedException e)
+        	{
+        		e.printStackTrace();
+        	}
+        }
+    }
+
+	private void setBreakListen(boolean state)
+	{
+		synchronized(listenBreak)
+		{
+			listenForBreak=state;
+			listenBreak.notify();
+		}
+	}
+
+	
+
+	void expect(char nextChar) throws IOException, GDBServerException
+	{
+		int t = read();
+		if (t!=nextChar)
+		{
+			throw new BadPacketException();
+		}
+	}
+
+	int read() throws IOException
+	{
+		flush();
+		readBuffer.clear();
+		for (;;)
+		{
+			int n;
+			n = sc.read(readBuffer);
+			if (n == 1)
+			{
+				break;
+			}
+			while (!waitSelect(selectorRead, true));
+		}
+		readBuffer.flip();
+		int t = readBuffer.get(0);
+		return t;
+	}
+
+	/**
+	 * @param value
+	 * @return
+	 */
+	protected String printHex(int value)
+	{
+		return formatHex(value, "00000000");
+	}
+
+	/**
+	 * @param value
+	 * @param pad TODO
+	 * @return
+	 */
+	protected String formatHex(int value, String pad)
+	{
+		String t=Integer.toHexString(value);
+		if (t.length()>pad.length())
+		{
+			t=t.substring(0, pad.length());
+		}
+		return pad.substring(0, pad.length()-t.length())+t;
+	}
+
+	public void write(byte[] bytes) throws IOException
+	{
+		int i=0;
+		while (i<bytes.length)
+		{
+			int len;
+			
+			while ((len=Math.min(bytes.length-i, writeBuffer.capacity()-writeBuffer.position()))==0)
+			{
+				flush();
+			}
+			
+			writeBuffer.put(bytes, i, len);
+			
+			i+=len;
+		}
+	}
+
+	void flush() throws IOException 
+	{
+		if (writeBuffer.position()>0)
+		{
+			writeBuffer.flip();
+			int len=writeBuffer.limit();
+	
+			int j=0;
+			while (j<len)
+			{
+				int t=sc.write(writeBuffer);
+				
+				if (t==0)
+				{
+					while (!waitSelect(selectorWrite, false));
+				}
+				j+=t;
+			}
+			writeBuffer.clear();
+		}		
+	}
+
+    
+    private boolean enterSyscall;
+
+
+    
+    /* handle all sorts of IO calls, etc. by sending them to the
+     */
+    public void syscall(Sim s) throws CPUException
+    {
+        simulator.suspend();
+        enterSyscall=true;
+    }
+
+
+    protected void performSyscall() 
+    {
+        enterSyscall=false;
+        try
+        {
+            int id;
+            id=simulator.getArg(1);
+            Packet syscall;
+            syscall=new Packet(this);
+            switch (id)
+            {
+            case Host.SYS_write:
+                syscall.invokeSyscall("write", 3, "iii");
+                break;
+            case Host.SYS_read:
+                syscall.invokeSyscall("read", 3, "iii");
+                break;
+            case Host.SYS_lseek:
+                syscall.invokeSyscall("lseek", 3, "iii");
+                break;
+            case Host.SYS_open:
+                syscall.invokeSyscall("open", 3, "sii");
+                break;
+            case Host.SYS_close:
+                syscall.invokeSyscall("close", 1, "i");
+                break;
+            case Host.SYS_fstat:
+                syscall.invokeSyscall("fstat", 2, "ii");
+                break;
+            case Host.SYS_stat:
+                syscall.invokeSyscall("stat", 2, "si");
+                break;
+            case Host.SYS_isatty:
+                syscall.invokeSyscall("isatty", 1, "i");
+                break;
+            case Host.SYS_unlink:
+                syscall.invokeSyscall("unlink", 1, "s");
+                break;
+            default:
+                simulator.suspend();
+                throw new UnsupportedSyscallException();
+            }
+            simulator.cpuWriteLong(simulator.getArg(0), syscall.syscallErrno);
+            simulator.cpuWriteLong(0, syscall.syscallRetval);
+        } catch (CPUException e)
+        {
+            e.printStackTrace();
+        } catch (IOException e)
+        {
+            e.printStackTrace();
+        } catch (GDBServerException e)
+        {
+            e.printStackTrace();
+        } catch (EndSessionException e)
+        {
+            e.printStackTrace();
+        }
+    }
+    
+    public boolean doneContinue()
+    {
+        if (!enterSyscall)
+            return true;
+        leaveListenForCtrlC();
+        try
+        {
+            performSyscall();
+        } finally
+        {
+            enterListenForCtrlC();
+        }
+        return false;
+    }
+    
+    public int getSyscallArg(int i) throws CPUException
+    {
+        return simulator.getArg(i+2);
+    }
+
+
+    public void writeUART(int val)
+    {
+        System.out.print((char)val);
+        System.out.flush();
+    }
+    public int readUART() throws CPUException
+    {
+        try
+        {
+            if (System.in.available()<=0)
+            {
+                throw new MemoryAccessException();
+            }
+            
+            return System.in.read();
+        } catch (IOException e)
+        {
+            e.printStackTrace();
+        }
+        return 0;
+    }
+
+    public int readFIFO()
+    {
+        try
+        {
+            return System.in.available()>0?0:1;
+        } catch (IOException e)
+        {
+            e.printStackTrace();
+        }
+        return 1;
+    }
+
+	public void halted()
+	{
+		// TODO Auto-generated method stub
+		
+	}
+
+	public void running()
+	{
+		// TODO Auto-generated method stub
+		
+	}
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
new file mode 100644
index 0000000..7925bd5
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
@@ -0,0 +1,455 @@
+/*
+ * Created on Nov 16, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.gdb;
+
+import java.io.IOException;
+import java.util.regex.Matcher;
+import java.util.regex.Pattern;
+
+import com.zylin.zpu.simulator.exceptions.BadPacketException;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.EndSessionException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+import com.zylin.zpu.simulator.exceptions.NoAckException;
+import com.zylin.zpu.simulator.exceptions.UnknownPacketException;
+
+
+/** all packet related operations */
+class Packet
+{
+	private final GDBServer server;
+	
+	Packet(GDBServer server)
+	{
+		this.server = server;
+        reply=new StringBuffer();
+	}
+	
+	void receive() throws IOException, GDBServerException, EndSessionException
+	{
+		int t;
+		/* we spool until we see a $ */
+		this.server.expect('$');
+		
+		StringBuffer packet=new StringBuffer();
+	
+		int cc=0;
+		for (;;)
+		{
+			int t1;
+			t1=this.server.read();
+			t = t1;
+			if (t==0x7d)
+			{
+				int t2;
+				t2=this.server.read();
+				/* the next char is escaped after a GDB specific scheme. See
+				 * gdb/gdb/remote.c */
+				t = t2;
+				t^=0x20;
+			} else
+			{
+				if (t=='#')
+				{
+					break;
+				}
+			}
+			
+			cc+=t;
+			
+			packet.append((char)t);
+		}
+		cc&=0xff;
+		
+		String checkSum;
+		checkSum=""+(char)this.server.read()+(char)this.server.read();
+		int readCheckSum;
+		readCheckSum=Integer.parseInt(checkSum, 16);
+		if (readCheckSum!=cc)
+		{
+			// error
+			dumpHex(packet.toString());
+			
+			this.server.write("-".getBytes());
+			throw new BadPacketException();
+		} else
+		{
+			// ack
+			this.server.write("+".getBytes());
+		}
+		
+		cmd=packet.toString();
+		this.server.print(GDBServer.PACKET, "Got " + number + ": #$" + cmd + "#" + checkSum); 
+		origCmd=cmd;
+	}
+	
+	void parseAndExecute() throws IOException, EndSessionException
+	{
+    	boolean silent=false;
+	    try
+		{
+			if (checkPrefix("g"))
+			{
+				readRegisters();
+			} else if (checkPrefix("?"))
+			{
+				querySignal();
+			} else if (checkPrefix("s"))
+			{
+				doStep();
+			} else if (checkPrefix("m"))
+			{
+				try
+				{
+					readMemory();
+				} catch (CPUException e)
+                {
+                    silent=true; // happens all the time while hovering over variables in the GUI
+                    throw e;
+                }
+			} else if (checkPrefix("c"))
+			{
+				continueExecution();
+			} else if (checkPrefix("M"))
+			{
+				writeMemory();
+			} else if (checkPrefix("z4"))
+			{
+				disableAccessWatchPoint();
+			} else if (checkPrefix("Z4"))
+			{
+				enableAccessWatchPoint();
+			} else if (checkPrefix("k"))
+			{
+				/* we must send a reply, but not wait for ack before we shut down
+				   the connection.
+				*/
+			    server.alive=false;
+			    reply("OK");
+			} else
+			{
+				throw new UnknownPacketException();
+			}
+		} catch (UnknownPacketException e)
+		{
+			this.server.print(GDBServer.UNKNOWN, "Unknown packet: " + origCmd);
+			// empty reply to unknown packets
+		} catch (CPUException e)
+        {
+            if (!silent)
+            {
+                this.server.print(GDBServer.CPUEXCEPTION, "Exception handling GDB request");
+                if (GDBServer.CPUEXCEPTION)
+                {
+                    e.printStackTrace();
+                }
+            }               
+            reply("E01");
+        } catch (GDBServerException e)
+        {
+            e.printStackTrace();
+            reply("E01");
+        }  catch (RuntimeException e)
+		{
+			e.printStackTrace();
+			reply("E01");
+		} 
+	}
+
+	private void checkEmpty() throws GDBServerException
+	{
+		if (cmd.length()>0)
+		{
+			throw new GDBServerException();
+		}
+	}
+	private void dumpHex(String arrayList2)
+	{
+		for (int i=0; i<arrayList2.length(); i++)
+		{
+			System.out.println(this.server.formatHex(arrayList2.charAt(i), "00"));
+		}
+	}
+	/**
+	 * @param packetString
+	 * @param string
+	 * @return
+	 */
+	private boolean checkPrefix(String string)
+	{
+		if (cmd.length() < string.length())
+		{
+			return false;
+		} else
+		{
+			return cmd.substring(0, string.length()).equals(string);
+		}
+	}
+	/**
+	 * @throws GDBServerException
+	 * @throws MemoryAccessException
+	 * 
+	 */
+	private void continueExecution() throws GDBServerException
+	{
+		extractString("c");
+		try
+		{
+			if (!isEmpty())
+			{
+				int pc=extractInteger();
+				this.server.simulator.setPc(pc);
+			}
+			checkEmpty();
+			this.server.simulator.cont();
+		} catch (MemoryAccessException e)
+		{
+			if (GDBServer.IGNOREDEXCEPTIONS)
+			{
+				e.printStackTrace();
+			}
+		}
+		reply("S05");
+	}
+	private void doStep()
+	{
+		this.server.simulator.step();
+		reply("S05");
+	}
+	protected int extractInteger() throws GDBServerException
+	{
+		String number;
+		Pattern p=Pattern.compile("(\\-?[0-9a-fA-F]+)");
+		Matcher m = p.matcher(cmd);
+		if (!m.find())
+		{
+			throw new GDBServerException();
+		}
+		number=m.group();
+		extractString(number);
+		
+		try
+		{
+			return (int)Long.parseLong(number, 16);
+		} catch (NumberFormatException e)
+		{
+			throw new GDBServerException(e);
+		}
+	}
+	/**
+	 * @param string
+	 * @throws GDBServerException
+	 */
+	private void extractString(String string) throws GDBServerException
+	{
+		if (!checkPrefix(string))
+		{
+			throw new GDBServerException();
+		}
+		stripStart(string.length());
+	}
+	/**
+	 * @throws GDBServerException
+	 * 
+	 */
+	private void readMemory() throws CPUException, GDBServerException
+	{
+		extractString("m");
+		int address=extractInteger();
+		extractString(",");
+		int length=extractInteger();
+		checkEmpty();
+		
+		for (int i=0; i<length; i++)
+		{
+			reply(this.server.formatHex(this.server.simulator.readByte(address+i), "00"));
+		}
+	}
+	/**
+	 * 
+	 */
+	private void readRegisters()  throws CPUException
+	{
+		for (int i=0; i<this.server.simulator.getREGNUM(); i++)
+		{
+			reply(this.server.printHex(this.server.simulator.getReg(i))); 
+		}
+	}
+	private void writeMemory() throws GDBServerException, MemoryAccessException
+	{
+		extractString("M");
+		int address=extractInteger();
+		extractString(",");
+		int length=extractInteger();
+		extractString(":");
+		
+		for (int i=0; i<length; i++)
+		{
+			String t;
+			t=cmd.substring(i*2, i*2+2);
+			int val;
+			val=Integer.parseInt(t, 16);
+			this.server.simulator.writeByte(address+i, val);
+		}
+		reply("OK");
+		
+	}
+	
+	private void enableAccessWatchPoint() throws GDBServerException, CPUException 
+	{
+		extractString("Z4");
+		extractString(",");
+		int address=extractInteger();
+		extractString(",");
+		int length=extractInteger();
+		checkEmpty();
+		server.simulator.enableAccessWatchPoint(address, length);
+		
+		reply("OK");
+	}
+
+	private void disableAccessWatchPoint() throws GDBServerException, CPUException 
+	{
+		extractString("z4");
+		extractString(",");
+		int address=extractInteger();
+		extractString(",");
+		int length=extractInteger();
+		checkEmpty();
+		server.simulator.disableAccessWatchPoint(address, length);
+		
+		reply("OK");
+	}
+
+	
+	private void stripStart(int length)
+	{
+		cmd=cmd.substring(length);
+	}
+	private boolean isEmpty() 
+	{
+		return cmd.length()==0;
+	}
+	/**
+	 * @param string
+	 */
+	protected void reply(String string)
+	{
+		reply.append(string);
+	}
+	void sendReply() throws IOException, NoAckException
+	{
+		// a bit easier to debug if we can see the entire string.
+		StringBuffer buffer = new StringBuffer();
+		buffer.append("$");
+		number++;
+		String replyString = reply.toString();
+		buffer.append(replyString);
+		byte[] data = replyString.toString().getBytes();
+		int csum = 0;
+		for (int i = 0; i < data.length; i++)
+		{
+			csum += data[i];
+		}
+		csum &= 0xff;
+		buffer.append("#");
+		String t = Integer.toHexString(csum);
+		if (t.length() == 1)
+		{
+			t = "0" + t;
+		}
+		buffer.append(t);
+		this.server.print(GDBServer.REPLY, "Reply " + number + " : " + buffer.toString());
+		this.server.write(buffer.toString().getBytes());
+		
+		if (server.alive)
+		{
+			/* check for ack. */
+			int ack = (char)this.server.read();
+			if (ack == '+')
+			{
+				return;
+			}
+			this.server.print(GDBServer.MINIMAL, "Retry");
+			
+			throw new NoAckException();
+		}
+	}
+	
+	private void querySignal()
+	{
+		// SIGINT
+		//	reply("S02");
+		reply("S05");
+	}
+	protected String cmd;
+	private int number;
+	private StringBuffer reply;
+	private String origCmd;
+    int syscallErrno;
+    int syscallRetval;
+
+
+    
+    void invokeSyscall(String string, int argNum, String types) throws IOException, NoAckException, GDBServerException, EndSessionException, CPUException
+    {
+        string="F"+string;
+        
+        int j=0;
+        for (int i=0; i<argNum; i++)
+        {
+            string+=",";
+            string+=Integer.toHexString(server.getSyscallArg(j));
+            j++;
+            if (types.charAt(i)=='s')
+            {
+                string+="/" + Integer.toHexString(server.getSyscallArg(j));
+                j++;
+            }
+        }
+
+        reply(string);
+        sendReply();
+        for (;;)
+        {
+            Packet packet=new Packet(server);
+            packet.receive();
+            if (packet.checkPrefix("F"))
+            {
+                /* this is the reply we are waiting for */
+                packet.extractString("F");
+                syscallRetval=packet.extractInteger();
+                syscallErrno=0;
+                if (packet.checkPrefix(","))
+                {
+                    /* errno is optional */
+                    packet.extractString(",");
+                    syscallErrno = packet.extractInteger();
+                }
+                break;
+            } else
+            {
+                /* something else... */
+                try
+                {
+                    packet.parseAndExecute();
+                    packet.sendReply();
+                } catch (IOException e)
+                {
+                    e.printStackTrace();
+                } catch (EndSessionException e)
+                {
+                    e.printStackTrace();
+                } catch (RuntimeException e)
+                {
+                    e.printStackTrace();
+                }
+            }
+        }
+    }
+}
\ No newline at end of file
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java
new file mode 100644
index 0000000..f641595
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java
@@ -0,0 +1,39 @@
+
+package com.zylin.zpu.simulator.tools;
+
+import java.io.FileInputStream;
+import java.io.IOException;
+
+public class MakeDRAM
+{
+    public static void main(String[] args) throws IOException
+    {
+       new MakeDRAM().run(args[0]);
+    }
+
+    private void run(String string) throws IOException
+    {
+        FileInputStream file=new FileInputStream(string);
+        
+        int i=0;
+        while (file.available()>4)
+        {
+            byte[] tmp=new byte[4];
+            file.read(tmp);
+            int word=0;
+            for (int j=0; j<4; j++)
+            {
+                word|=((int)(tmp[j])&0xff)<<((3-j)*8);
+            }
+            String str=Integer.toHexString(word);
+            while (str.length()<8)
+            {
+                str="0"+str;
+            }
+            
+            System.out.println(str);
+            i++;
+        }
+    }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java
new file mode 100644
index 0000000..4a7b233
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java
@@ -0,0 +1,39 @@
+
+package com.zylin.zpu.simulator.tools;
+
+import java.io.FileInputStream;
+import java.io.IOException;
+
+public class MakeRam
+{
+    public static void main(String[] args) throws IOException
+    {
+       new MakeRam().run(args[0]);
+    }
+
+    private void run(String string) throws IOException
+    {
+        FileInputStream file=new FileInputStream(string);
+        
+        int i=0;
+        while (file.available()>4)
+        {
+            byte[] tmp=new byte[4];
+            file.read(tmp);
+            int word=0;
+            for (int j=0; j<4; j++)
+            {
+                word|=((int)(tmp[j])&0xff)<<((3-j)*8);
+            }
+            String str=Integer.toHexString(word);
+            while (str.length()<8)
+            {
+                str="0"+str;
+            }
+            
+            System.out.println("" + i + " => x\"" + str + "\",");
+            i++;
+        }
+    }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java b/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java
new file mode 100644
index 0000000..0f06aec
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java
@@ -0,0 +1,94 @@
+/*
+ * Created on Jan 18, 2005
+ *
+ * TODO To change the template for this generated file go to
+ * Window - Preferences - Java - Code Style - Code Templates
+ */
+package com.zylin.zpu.stats;
+
+import java.io.File;
+import java.io.FileInputStream;
+import java.io.FileNotFoundException;
+import java.io.IOException;
+
+import com.zylin.zpu.simulator.Machine;
+
+public class CountSequences implements Machine
+{
+
+    private byte[] array;
+    private StatKeeper statKeeper;
+
+    public static void main(String[] args)
+    {
+        new CountSequences().run(args[0]);
+    }
+
+    private void run(String string)
+    {
+        try
+        {
+            File file=new File(string);
+            if (file.exists())
+                System.out.println("It exists!");
+            FileInputStream in=new FileInputStream(file);
+            
+            try
+            {
+                array=new byte[(int) file.length()];
+                
+                if (in.read(array)!=array.length)
+                    throw new IOException();
+                
+                countStats();
+                
+                statKeeper.printStats();
+            } finally
+            {
+                in.close();
+            }
+            
+        } catch (FileNotFoundException e)
+        {
+            e.printStackTrace();
+        } catch (IOException e)
+        {
+            e.printStackTrace();
+        }
+        
+        
+    }
+
+
+    private void countStats()
+    {
+        statKeeper=new StatKeeper(this);
+        for (int i=0; i<array.length; i++)
+        {
+            int j = array[i]&0xff;
+//            
+//            if ((j>=64)&&(j<96))
+//            {
+//                j=64;
+//            } else if ((j>=96)&&(j<128))
+//            {
+//                j=96;
+//            } else if ((j>=128)&&(j<256))
+//            {
+//                j=128;
+//            }
+            statKeeper.countInstruction(j);
+        }
+        
+    }
+
+    public long getPrevCycles()
+    {
+        return 0;
+    }
+
+    public long getCycles()
+    {
+        return 0;
+    }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java b/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java
new file mode 100644
index 0000000..80be11d
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java
@@ -0,0 +1,17 @@
+/*
+ * Created on 26.nov.2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.stats;
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public interface DumpIt
+{
+	int dumpIt(int i);
+}
\ No newline at end of file
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java b/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java
new file mode 100644
index 0000000..252dd7f
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java
@@ -0,0 +1,62 @@
+package com.zylin.zpu.stats;
+
+public class Instruction 
+{
+	public class DumpCycles implements DumpIt
+	{
+		public int dumpIt(int i)
+		{
+			return insn[i].cycles;
+		}
+	}
+
+
+
+	public Instruction[] insn=new Instruction[256];
+	public int count;
+	public int cycles;
+
+	public Instruction addInstruction(int i)
+	{
+		if (insn[i]==null)
+		{
+			insn[i]=new Instruction();
+		}
+		return insn[i];
+	}
+
+	/**
+	 * Recursive print of statistics
+	 */
+	public void printStats()
+	{
+		System.out.println("Count dump");
+		DumpIt cDump = new DumpCount();
+		printCount("", cDump);
+	}
+
+	/**
+	 * Recursive print of counts
+	 * @param string
+	 * @param dumpIt TODO
+	 */
+	private void printCount(String string, DumpIt dumpIt)
+	{
+		for (int i=0; i<insn.length; i++)
+		{
+			if (insn[i]!=null)
+			{
+				insn[i].printCount(string + ", " + i, dumpIt);
+				System.out.println("Count: " + insn[i].count + string + ", " + i);
+			}
+		}
+	}
+
+	class DumpCount implements DumpIt
+	{
+		public int dumpIt(int i)
+		{
+			return insn[i].count;
+		}
+	}
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java b/zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java
new file mode 100644
index 0000000..9e16e32
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java
@@ -0,0 +1,52 @@
+package com.zylin.zpu.stats;
+
+import com.zylin.zpu.simulator.Machine;
+import com.zylin.zpu.simulator.State;
+
+public class StatKeeper
+{
+	private Instruction top=new Instruction();
+	private int trackPos;
+
+    private State[] state = new State[3];
+    private Machine simulator;
+	/**
+     * @param simulator
+     */
+    public StatKeeper(Machine simulator)
+    {
+        this.simulator=simulator;
+		for (int i=0; i<state.length; i++)
+		{
+			state[i]=new State();
+		}
+    }
+    /**
+	 * this instruction has been retired. Count it.
+	 */
+	public void countInstruction(int instruction)
+	{
+		State currentState=state[trackPos%state.length];
+		currentState.cycle=simulator.getPrevCycles(); // start of instruction
+		currentState.insn=instruction;
+		trackPos++;
+        int backtrackNum;
+		backtrackNum=Math.min(trackPos, state.length);
+		for (int i=0; i<backtrackNum; i++)
+		{
+            Instruction t=top;
+			for (int j=0; j<=i; j++)
+			{
+                currentState=state[(trackPos-backtrackNum+j)%state.length];
+				t=t.addInstruction(currentState.insn);
+			}
+            t.count++;
+		}
+		
+	}
+    public void printStats()
+    {
+        top.printStats();
+        
+    }
+}
diff --git a/zpu/sw/simulator/gmon.out b/zpu/sw/simulator/gmon.out
new file mode 100644
index 0000000..c49b3d7
Binary files /dev/null and b/zpu/sw/simulator/gmon.out differ
diff --git a/zpu/sw/simulator/zpusim.jar b/zpu/sw/simulator/zpusim.jar
new file mode 100644
index 0000000..e6e763a
Binary files /dev/null and b/zpu/sw/simulator/zpusim.jar differ
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