From f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Wed, 2 Jan 2008 21:52:27 +0000
Subject: Initial import from www.ecosforge.net

---
 .../current/cdl/opencores_ethermac_drivers.cdl     |   149 +
 zpu/sw/ecos/repository/ecos.db                     |   128 +
 zpu/sw/helloworld/gccgdb.PNG                       |   Bin 0 -> 34473 bytes
 zpu/sw/helloworld/gmon.out                         |   Bin 0 -> 120053 bytes
 zpu/sw/helloworld/hello.bin                        |   Bin 0 -> 49768 bytes
 zpu/sw/helloworld/hello.bram                       | 12441 +++++++++++++++++++
 zpu/sw/helloworld/hello.c                          |     6 +
 zpu/sw/helloworld/hello.elf                        |   Bin 0 -> 279938 bytes
 zpu/sw/helloworld/zpusim.PNG                       |   Bin 0 -> 17817 bytes
 zpu/sw/index.html                                  |    44 +
 zpu/sw/simulator/.classpath                        |     6 +
 zpu/sw/simulator/.project                          |    17 +
 .../simulator/.settings/org.eclipse.jdt.core.prefs |    66 +
 zpu/sw/simulator/ChangeLog                         |     2 +
 zpu/sw/simulator/build.xml                         |     7 +
 zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java |   109 +
 .../com/zylin/zpu/simulator/FileTracer.java        |   285 +
 zpu/sw/simulator/com/zylin/zpu/simulator/Host.java |    46 +
 .../simulator/com/zylin/zpu/simulator/Machine.java |    17 +
 zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java  |   126 +
 .../com/zylin/zpu/simulator/PhiFeeble.java         |    34 +
 zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java  |    62 +
 .../simulator/com/zylin/zpu/simulator/SimApp.java  |   112 +
 .../com/zylin/zpu/simulator/SimFactory.java        |     8 +
 .../com/zylin/zpu/simulator/Simulator.java         |  2063 +++
 .../simulator/com/zylin/zpu/simulator/State.java   |     9 +
 .../simulator/com/zylin/zpu/simulator/Tracer.java  |    21 +
 zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java  |    14 +
 .../com/zylin/zpu/simulator/applet/ZPUApplet.java  |   281 +
 .../simulator/exceptions/BadPacketException.java   |    22 +
 .../zpu/simulator/exceptions/CPUException.java     |    23 +
 .../exceptions/DebuggerBreakpointException.java    |    10 +
 .../simulator/exceptions/EndSessionException.java  |    22 +
 .../simulator/exceptions/GDBServerException.java   |    25 +
 .../exceptions/HardwareWatchPointException.java    |    12 +
 .../exceptions/IllegalInstructionException.java    |    23 +
 .../simulator/exceptions/InterruptException.java   |    23 +
 .../exceptions/MemoryAccessException.java          |    23 +
 .../zpu/simulator/exceptions/NoAckException.java   |    22 +
 .../zpu/simulator/exceptions/TraceException.java   |    22 +
 .../exceptions/UnknownPacketException.java         |    10 +
 .../exceptions/UnsupportedSyscallException.java    |    12 +
 .../com/zylin/zpu/simulator/gdb/GDBServer.java     |   609 +
 .../com/zylin/zpu/simulator/gdb/Packet.java        |   455 +
 .../com/zylin/zpu/simulator/tools/MakeDRAM.java    |    39 +
 .../com/zylin/zpu/simulator/tools/MakeRam.java     |    39 +
 .../com/zylin/zpu/stats/CountSequences.java        |    94 +
 zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java   |    17 +
 .../simulator/com/zylin/zpu/stats/Instruction.java |    62 +
 .../simulator/com/zylin/zpu/stats/StatKeeper.java  |    52 +
 zpu/sw/simulator/gmon.out                          |   Bin 0 -> 120053 bytes
 zpu/sw/simulator/zpusim.jar                        |   Bin 0 -> 68039 bytes
 52 files changed, 17669 insertions(+)
 create mode 100644 zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl
 create mode 100644 zpu/sw/ecos/repository/ecos.db
 create mode 100644 zpu/sw/helloworld/gccgdb.PNG
 create mode 100644 zpu/sw/helloworld/gmon.out
 create mode 100644 zpu/sw/helloworld/hello.bin
 create mode 100644 zpu/sw/helloworld/hello.bram
 create mode 100644 zpu/sw/helloworld/hello.c
 create mode 100644 zpu/sw/helloworld/hello.elf
 create mode 100644 zpu/sw/helloworld/zpusim.PNG
 create mode 100644 zpu/sw/index.html
 create mode 100644 zpu/sw/simulator/.classpath
 create mode 100644 zpu/sw/simulator/.project
 create mode 100644 zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs
 create mode 100644 zpu/sw/simulator/ChangeLog
 create mode 100644 zpu/sw/simulator/build.xml
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Host.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/State.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java
 create mode 100644 zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java
 create mode 100644 zpu/sw/simulator/gmon.out
 create mode 100644 zpu/sw/simulator/zpusim.jar

(limited to 'zpu/sw')

diff --git a/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl b/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl
new file mode 100644
index 0000000..017ee57
--- /dev/null
+++ b/zpu/sw/ecos/repository/dev/eth/opencores/ethermac/current/cdl/opencores_ethermac_drivers.cdl
@@ -0,0 +1,149 @@
+# ====================================================================
+#
+#      opencores_ethermac_eth_drivers.cdl
+#
+#      Ethernet drivers - support for Opencores ethermac controllers
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2004 Andrew Lunn
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Gaisler Research, (Konrad Eisele<eiselekd@web.de>)
+# Contributors:   
+# Date:           2005-01-22
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC {
+    display       "Opencores ethermac driver"
+    description   "Ethernet driver for Opencores ethermac driver."
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_IO_ETH_DRIVERS
+
+    active_if     CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED
+
+    include_dir   .
+    include_files ; # none _exported_ whatsoever
+    compile       if_oeth.c
+
+    include_files include/oeth_info.h
+    
+    define_proc {
+        puts $::cdl_header "#include <pkgconf/system.h>";
+        puts $::cdl_header "#include CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG";
+    }
+
+    cdl_option CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT {
+	display "Number of supported interfaces."
+	calculated    { CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED }
+        flavor        data
+	description   "
+	    This option selects the number of ethernet interfaces to
+            be supported by the driver."
+    }
+
+    cdl_interface CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_STATIC_ESA {
+	display "ESA is statically configured"
+	description "
+	    If this is nonzero, then the ESA (MAC address) is statically
+            configured in the platform-specific package which instantiates
+	    this driver with all its details.
+
+	    Note that use of this option is deprecated in favor of a
+	    CYGSEM_DEVS_ETH_..._SET_ESA option in the platform specific
+	    driver."
+    }
+
+    cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_TxNUM {
+        display       "Number of output buffers"
+        flavor        data
+        legal_values  2 to 64
+        default_value 4
+        description   "
+            This option specifies the number of output buffer packets
+            to be used for the opencores ethernet device in multiples of 2."
+    }
+
+    cdl_option CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_RxNUM {
+        display       "Number of input buffers"
+        flavor        data
+        legal_values  2 to 64
+        default_value 4
+        description   "
+            This option specifies the number of input buffer packets
+            to be used for the opencores ethernet device in multiples of 2."
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_OPTIONS {
+        display "Opencores ethermac driver build options"
+        flavor  none
+	no_define
+
+        cdl_option CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "-D_KERNEL -D__ECOS" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the opencores ethermac driver package.
+                These flags are used in addition
+                to the set of global flags."
+        }
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH {
+	display       "Cache flushing"
+	flavor        bool
+	default_value 1
+        description   "Flush cache before copying packets from/to the
+        ethermac dma transfer buffers. If you have cache snooping enabled
+        you can disable this option."
+        
+    }
+    
+    cdl_component CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_ETH100 {
+	display       "Initialize MII to 100mbit"
+	flavor        bool
+	default_value 0
+        description   "Issue a MII sequence that enables a 100mbit link "
+        
+    }
+
+}
diff --git a/zpu/sw/ecos/repository/ecos.db b/zpu/sw/ecos/repository/ecos.db
new file mode 100644
index 0000000..c31fc4b
--- /dev/null
+++ b/zpu/sw/ecos/repository/ecos.db
@@ -0,0 +1,128 @@
+
+package CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC {
+        alias           { "opencore's ethermac support" devs_eth_opencores_ethermac }
+        hardware
+        directory       dev/eth/opencores/ethermac
+        script          opencores_ethermac_drivers.cdl
+        description "This package contains hardware support for Opencores
+                     ethermac."
+}
+
+package CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI {
+        alias           { "ethernet support for opencores on Zylin Phi addon board" devs_eth_zpu_opencores_phi }
+	hardware
+	directory       dev/eth/zpu/opencores/phi
+	script          phi_opencores_ethmac_drivers.cdl
+	description	"This package contains hardware support for Opencores Ethermac
+		    ethernet device on Phi."
+}
+
+
+
+package CYGPKG_HAL_ZYLIN {
+	alias		{ "Zylin common HAL" hal_zylin }
+	directory	hal/zylin/arch
+	script		hal_zylin.cdl
+	hardware
+	description "
+The Zylin architecture HAL package provides generic support for this
+processor architecture. It is also necessary to select a specific
+target platform HAL package."
+}
+
+
+package CYGPKG_HAL_ZYLIN_ZPU {
+	alias		{ "Zylin ZPU variant HAL" hal_zylin_zpu }
+	directory	hal/zylin/zpu/var
+	script		hal_zylin_zpu.cdl
+	hardware
+        description "
+        The Zylin ZPU HAL package provides the support needed to run eCos on Zylin
+        ZPU based targets."
+}
+
+
+
+package CYGPKG_HAL_ZYLIN_ZPU_ZETA {
+	alias		{ "Zylin ZPU simulation" zeta }
+	directory	hal/zylin/zpu/zeta
+	script		hal_zylin_zpu_zeta.cdl
+	hardware
+        description "
+	The Zylin ZPU package provides the support needed to run eCos on an Zylin 
+	evaluation board."
+}
+package CYGPKG_HAL_ZYLIN_ZPU_PHI {
+	alias		{ "Zylin ZPU evaluation board" phi }
+	directory	hal/zylin/zpu/phi
+	script		hal_zylin_zpu_phi.cdl
+	hardware
+        description "
+	The Zylin ZPU package provides the support needed to run eCos on a Zylin eCosBoard"
+}
+
+package CYGPKG_HAL_ZYLIN_ZPU_ABEL {
+	alias		{ "Zylin ZPU Abel board" abel }
+	directory	hal/zylin/zpu/abel
+	script		hal_zylin_zpu_abel.cdl
+	hardware
+        description "
+	The Zylin ZPU package provides the support needed to run eCos on an Abel Zylin 
+	evaluation board."
+}
+
+
+package CYGPKG_PHI_NET {
+	alias		{ "Zylin Phi networking" phi_net }
+	directory	net/zylin
+	script		phi_net.cdl
+	hardware
+        description "Contains phi specific network init."
+}
+
+
+target zeta {
+	alias { "Zylin ZPU evaluation board " zeta }
+	packages { CYGPKG_HAL_ZYLIN
+                   CYGPKG_HAL_ZYLIN_ZPU
+                   CYGPKG_HAL_ZYLIN_ZPU_ZETA
+        }
+        description "
+	The Zylin ZPU target provides the packages needed to run eCos on an Zylin 
+	evaluation board."
+}
+
+target phi {
+	alias { "Zylin ZPU evaluation board " phi }
+	packages { CYGPKG_HAL_ZYLIN
+                   CYGPKG_HAL_ZYLIN_ZPU
+                   CYGPKG_HAL_ZYLIN_ZPU_PHI
+        }
+        description "
+	The Zylin ZPU target provides the packages needed to run eCos on an Zylin eCosBoard"
+}
+
+target abel {
+	alias { "Zylin ZPU evaluation board " abel }
+	packages { CYGPKG_HAL_ZYLIN
+                   CYGPKG_HAL_ZYLIN_ZPU
+                   CYGPKG_HAL_ZYLIN_ZPU_ABEL
+        }
+        description "
+	The Zylin ZPU target provides the packages needed to run eCos on an Abel Zylin 
+	evaluation board."
+}
+
+target zpuetherphi {
+	alias { "Zylin Phi addon board with ethernet" etherphi }
+	packages { CYGPKG_HAL_ZYLIN
+                   CYGPKG_HAL_ZYLIN_ZPU
+                   CYGPKG_HAL_ZYLIN_ZPU_PHI
+                   CYGPKG_IO_ETH_DRIVERS
+                   CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC
+		   CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI
+        }
+        description "
+	The Zylin Phi ZPU target provides the packages needed to run ZPU eCos on a
+	Zylin eCosBoard addon board with ethernet."
+}
diff --git a/zpu/sw/helloworld/gccgdb.PNG b/zpu/sw/helloworld/gccgdb.PNG
new file mode 100644
index 0000000..afdfc31
Binary files /dev/null and b/zpu/sw/helloworld/gccgdb.PNG differ
diff --git a/zpu/sw/helloworld/gmon.out b/zpu/sw/helloworld/gmon.out
new file mode 100644
index 0000000..86ca3d6
Binary files /dev/null and b/zpu/sw/helloworld/gmon.out differ
diff --git a/zpu/sw/helloworld/hello.bin b/zpu/sw/helloworld/hello.bin
new file mode 100644
index 0000000..4413b05
Binary files /dev/null and b/zpu/sw/helloworld/hello.bin differ
diff --git a/zpu/sw/helloworld/hello.bram b/zpu/sw/helloworld/hello.bram
new file mode 100644
index 0000000..f7e99e9
--- /dev/null
+++ b/zpu/sw/helloworld/hello.bram
@@ -0,0 +1,12441 @@
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+1 => x"82700b0b",
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+3 => x"3a0b0b81",
+4 => x"e48c0400",
+5 => x"00000000",
+6 => x"00000000",
+7 => x"00000000",
+8 => x"80088408",
+9 => x"88080b0b",
+10 => x"81e4fd2d",
+11 => x"880c840c",
+12 => x"800c0400",
+13 => x"00000000",
+14 => x"00000000",
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+16 => x"71fd0608",
+17 => x"72830609",
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+19 => x"832b2a83",
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+24 => x"71fd0608",
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+26 => x"83060981",
+27 => x"05820583",
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+57 => x"732e0753",
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+59 => x"00000000",
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+73 => x"c9040000",
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diff --git a/zpu/sw/helloworld/hello.c b/zpu/sw/helloworld/hello.c
new file mode 100644
index 0000000..e9cc61e
--- /dev/null
+++ b/zpu/sw/helloworld/hello.c
@@ -0,0 +1,6 @@
+// To compile: zpu-elf-gcc test.c -o test.elf -phi
+// To run:  
+int main(int argc, char **argv)
+{
+	printf("Hello world!\n");
+}
diff --git a/zpu/sw/helloworld/hello.elf b/zpu/sw/helloworld/hello.elf
new file mode 100644
index 0000000..be3c093
Binary files /dev/null and b/zpu/sw/helloworld/hello.elf differ
diff --git a/zpu/sw/helloworld/zpusim.PNG b/zpu/sw/helloworld/zpusim.PNG
new file mode 100644
index 0000000..d8fc277
Binary files /dev/null and b/zpu/sw/helloworld/zpusim.PNG differ
diff --git a/zpu/sw/index.html b/zpu/sw/index.html
new file mode 100644
index 0000000..6c860a9
--- /dev/null
+++ b/zpu/sw/index.html
@@ -0,0 +1,44 @@
+<html>
+<body>
+<h1>Getting started - a ZPU hello world program</h1>
+The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has 
+some very basic peripherals defined: counter, timer interrupt and a debug output port. 
+<h2>Installing</h2>
+<ol>
+<li>Install Cygwin. http://www.cygwin.com 
+<li>Install Java
+<li>Start Cygwin bash
+<li>cd zpu/sw
+<li>unzip tools/zputoolchain.zip
+<li>zpu/sw/install/bin now has the .exe files for the GCC toolchain & GDB
+<li>You may want to add install/bin from zputoolchain.zip to PATH.<br>
+export PATH=$PATH:&lt;unzipdir&gt;/install/bin
+</ol>
+<h1>Hello world example</h1>
+The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification.
+<p> 
+<code>
+cd zpu/sw/helloworld<br>
+../install/bin/zpu-elf-gcc -phi hello.c -o hello.elf <br>
+</code>
+<h2>Running the hello world example in GDB</h2>
+<ol>
+<li>cd zpu/sw/helloworld
+<li>Launch the simulator from a seperate bash shell:<p>
+java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444
+<p>
+<img src="helloworld/zpusim.PNG" border=0> 
+<li>Launch GDB:<p>
+../install/bin/zpu-elf-gdb hello.elf
+<li>Connect to target, load and run application:<p>
+<code>
+(gdb) target remote localhost:4444<br>
+(gdb) load<br>
+(gdb) continue<br>
+</code>
+<p>
+<img src="helloworld/gccgdb.PNG">
+
+
+</body>
+</html>
diff --git a/zpu/sw/simulator/.classpath b/zpu/sw/simulator/.classpath
new file mode 100644
index 0000000..617be7e
--- /dev/null
+++ b/zpu/sw/simulator/.classpath
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<classpath>
+	<classpathentry excluding="bin/" kind="src" output="bin" path=""/>
+	<classpathentry kind="con" path="org.eclipse.jdt.launching.JRE_CONTAINER"/>
+	<classpathentry kind="output" path=""/>
+</classpath>
diff --git a/zpu/sw/simulator/.project b/zpu/sw/simulator/.project
new file mode 100644
index 0000000..9cd2fd7
--- /dev/null
+++ b/zpu/sw/simulator/.project
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>simulator</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.jdt.core.javabuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.jdt.core.javanature</nature>
+	</natures>
+</projectDescription>
diff --git a/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs b/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs
new file mode 100644
index 0000000..6a131a7
--- /dev/null
+++ b/zpu/sw/simulator/.settings/org.eclipse.jdt.core.prefs
@@ -0,0 +1,66 @@
+#Sat Aug 04 19:47:23 CEST 2007
+eclipse.preferences.version=1
+org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled
+org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.5
+org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve
+org.eclipse.jdt.core.compiler.compliance=1.5
+org.eclipse.jdt.core.compiler.debug.lineNumber=generate
+org.eclipse.jdt.core.compiler.debug.localVariable=generate
+org.eclipse.jdt.core.compiler.debug.sourceFile=generate
+org.eclipse.jdt.core.compiler.problem.annotationSuperInterface=warning
+org.eclipse.jdt.core.compiler.problem.assertIdentifier=error
+org.eclipse.jdt.core.compiler.problem.autoboxing=ignore
+org.eclipse.jdt.core.compiler.problem.deprecation=warning
+org.eclipse.jdt.core.compiler.problem.deprecationInDeprecatedCode=disabled
+org.eclipse.jdt.core.compiler.problem.deprecationWhenOverridingDeprecatedMethod=disabled
+org.eclipse.jdt.core.compiler.problem.discouragedReference=warning
+org.eclipse.jdt.core.compiler.problem.emptyStatement=ignore
+org.eclipse.jdt.core.compiler.problem.enumIdentifier=error
+org.eclipse.jdt.core.compiler.problem.fallthroughCase=ignore
+org.eclipse.jdt.core.compiler.problem.fatalOptionalError=enabled
+org.eclipse.jdt.core.compiler.problem.fieldHiding=ignore
+org.eclipse.jdt.core.compiler.problem.finalParameterBound=ignore
+org.eclipse.jdt.core.compiler.problem.finallyBlockNotCompletingNormally=warning
+org.eclipse.jdt.core.compiler.problem.forbiddenReference=error
+org.eclipse.jdt.core.compiler.problem.hiddenCatchBlock=warning
+org.eclipse.jdt.core.compiler.problem.incompatibleNonInheritedInterfaceMethod=warning
+org.eclipse.jdt.core.compiler.problem.incompleteEnumSwitch=ignore
+org.eclipse.jdt.core.compiler.problem.indirectStaticAccess=ignore
+org.eclipse.jdt.core.compiler.problem.localVariableHiding=ignore
+org.eclipse.jdt.core.compiler.problem.methodWithConstructorName=warning
+org.eclipse.jdt.core.compiler.problem.missingDeprecatedAnnotation=ignore
+org.eclipse.jdt.core.compiler.problem.missingOverrideAnnotation=ignore
+org.eclipse.jdt.core.compiler.problem.missingSerialVersion=ignore
+org.eclipse.jdt.core.compiler.problem.noEffectAssignment=warning
+org.eclipse.jdt.core.compiler.problem.noImplicitStringConversion=warning
+org.eclipse.jdt.core.compiler.problem.nonExternalizedStringLiteral=ignore
+org.eclipse.jdt.core.compiler.problem.nullReference=ignore
+org.eclipse.jdt.core.compiler.problem.overridingPackageDefaultMethod=warning
+org.eclipse.jdt.core.compiler.problem.parameterAssignment=ignore
+org.eclipse.jdt.core.compiler.problem.possibleAccidentalBooleanAssignment=ignore
+org.eclipse.jdt.core.compiler.problem.potentialNullReference=ignore
+org.eclipse.jdt.core.compiler.problem.rawTypeReference=ignore
+org.eclipse.jdt.core.compiler.problem.redundantNullCheck=ignore
+org.eclipse.jdt.core.compiler.problem.specialParameterHidingField=disabled
+org.eclipse.jdt.core.compiler.problem.staticAccessReceiver=warning
+org.eclipse.jdt.core.compiler.problem.suppressWarnings=enabled
+org.eclipse.jdt.core.compiler.problem.syntheticAccessEmulation=ignore
+org.eclipse.jdt.core.compiler.problem.typeParameterHiding=warning
+org.eclipse.jdt.core.compiler.problem.uncheckedTypeOperation=ignore
+org.eclipse.jdt.core.compiler.problem.undocumentedEmptyBlock=ignore
+org.eclipse.jdt.core.compiler.problem.unhandledWarningToken=warning
+org.eclipse.jdt.core.compiler.problem.unnecessaryElse=ignore
+org.eclipse.jdt.core.compiler.problem.unnecessaryTypeCheck=ignore
+org.eclipse.jdt.core.compiler.problem.unqualifiedFieldAccess=ignore
+org.eclipse.jdt.core.compiler.problem.unusedDeclaredThrownException=ignore
+org.eclipse.jdt.core.compiler.problem.unusedDeclaredThrownExceptionWhenOverriding=disabled
+org.eclipse.jdt.core.compiler.problem.unusedImport=warning
+org.eclipse.jdt.core.compiler.problem.unusedLabel=warning
+org.eclipse.jdt.core.compiler.problem.unusedLocal=warning
+org.eclipse.jdt.core.compiler.problem.unusedParameter=ignore
+org.eclipse.jdt.core.compiler.problem.unusedParameterIncludeDocCommentReference=enabled
+org.eclipse.jdt.core.compiler.problem.unusedParameterWhenImplementingAbstract=disabled
+org.eclipse.jdt.core.compiler.problem.unusedParameterWhenOverridingConcrete=disabled
+org.eclipse.jdt.core.compiler.problem.unusedPrivateMember=warning
+org.eclipse.jdt.core.compiler.problem.varargsArgumentNeedCast=warning
+org.eclipse.jdt.core.compiler.source=1.5
diff --git a/zpu/sw/simulator/ChangeLog b/zpu/sw/simulator/ChangeLog
new file mode 100644
index 0000000..c645841
--- /dev/null
+++ b/zpu/sw/simulator/ChangeLog
@@ -0,0 +1,2 @@
+2007-08-04 Øyvind Harboe
+	* First version after open sourcing ZPU
diff --git a/zpu/sw/simulator/build.xml b/zpu/sw/simulator/build.xml
new file mode 100644
index 0000000..a5cc8a3
--- /dev/null
+++ b/zpu/sw/simulator/build.xml
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<project name="project" default="build">
+	
+	<target name="build" >
+		<jar destfile="zpusim.jar" basedir="bin"/>
+	</target>
+</project>
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java
new file mode 100644
index 0000000..8d8667c
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Abel.java
@@ -0,0 +1,109 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Abel extends Simulator
+{
+
+    protected int getIO()
+    {
+        return 0x8000;
+    }
+
+
+
+    protected int ioRead(int addr) throws CPUException
+    {
+        switch (addr)
+        {
+            case 0xc000:
+                return syscall.readUART();
+                
+                /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+            case 0xc004:
+                return syscall.readFIFO();
+                
+            case 0x9000:
+            case 0x9004:
+            case 0x9008:
+            case 0x900c:
+                
+            case 0x9010:
+            case 0x9014:
+            case 0x9018:
+            case 0x901c:
+            return readSampledTimer(addr, 0x9000);
+            
+            case 0x8800:
+                return readMHz();
+                
+        	default:
+        		throw new MemoryAccessException();
+        }
+    }
+
+    /*
+    ; Read/write are on different addresses
+    ; The registers are 8 bits and mapped to bit[7:0]
+    ; 
+    ; 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) 
+    ;        Read : Reads from UART RX FIFO (4 byte FIFO)
+    ; 0xC004 Read : UART status register
+    ;                       Bit 0 = RX FIFO empty
+    ;                       Bit 1 = TX FIFO full
+    ; 0xA000 Write: 8 LED's 
+    */
+    
+    /*
+    0x9000 Write: bit 0: 1= reset counter
+                   0= counter running
+              bit 1: 1= sample counter (when set to 1)
+                   0=not used
+         Read : counter bit[7:0]
+    0x9004 Read: counter bit [15:8]
+    0x9008 Read: counter bit [23:16]
+    0x900C Read: counter bit [31:24]
+    0x9010 Read: counter bit [39:32]
+    0x9014 Read: counter bit [47:40]
+    0x9018 Read: counter bit [55:48]
+    0x901C Read: counter bit [63:56]
+
+    0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz)
+    */
+
+    protected void ioWrite(int addr, int val) throws MemoryAccessException
+    {
+        switch (addr)
+        {
+            case 0x9000:
+                writeTimerSampleReg(val);
+            case 0xc000:
+                syscall.writeUART(val);
+                break;
+        	default:
+                throw new MemoryAccessException();
+        }
+    }
+
+    Abel() throws CPUException
+    {
+    }
+
+    protected boolean emulateConfig()
+    {
+        return true;
+    }
+
+    protected int getStartStack()
+    {
+        return getRAMSIZE()-8;
+    }
+
+    protected int getRAMSIZE()
+    {
+        return 32768;
+    }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java
new file mode 100644
index 0000000..6ccca24
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/FileTracer.java
@@ -0,0 +1,285 @@
+
+package com.zylin.zpu.simulator;
+
+import java.io.FileNotFoundException;
+import java.io.IOException;
+import java.io.LineNumberReader;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.TraceException;
+
+public class FileTracer implements Tracer
+{
+    private LineNumberReader file;
+    private boolean trigger;
+    private boolean resync;
+    private Simulator simulator;
+    private String line;
+    private boolean ignore;
+    
+    static class Trace
+    {
+    	int pc;
+    	int opcode;
+    	int sp;
+    	int stackA;
+    	int stackB;
+    	int intSp;
+    	long cycle;
+		public boolean undefinedStackA;
+		public boolean undefinedStackB;
+		public boolean undefinedIntSp;
+		public void print()
+		{
+			System.err.println(Integer.toHexString(pc)+ " " +
+			       		Integer.toHexString(opcode) + " " +
+			                Integer.toHexString(sp) + " " + 
+			                Integer.toHexString(stackA) + " " + 
+			                Integer.toHexString(stackB) + " " + 
+			                intSp + " " +
+			                cycle);
+			
+		}
+    };
+    private Trace[] trace= new Trace[100];
+    private int current;
+	private String fileName;
+	private boolean metEnd;
+    
+
+    public FileTracer(Simulator sim, String string)
+    {
+        simulator=sim;
+        fileName=string;
+
+        resync=true;
+       
+        
+        for (int i=0; i<trace.length; i++)
+        {
+        	trace[i]=new Trace();
+        }
+        findNextTrigger();
+    }
+
+    LineNumberReader getFile()
+    {
+    	if (file==null)
+    	{
+    		try
+			{
+				file=new LineNumberReader(new java.io.FileReader(fileName));
+			} catch (FileNotFoundException e)
+			{
+				throw new RuntimeException(e);
+			}
+    	}
+    	return file;
+    }
+
+
+    private void findNextTrigger() throws TraceException
+    {
+        trigger=false;
+        try
+        {
+            for (;;)
+            {
+                line=getFile().readLine();
+                if (line==null)
+                {
+                	metEnd=true;
+                    System.err.println("================== End of trace file ======================");
+                    break;
+                }
+                if (line.matches("^\\s*\\#.*$"))
+                {
+                    /* this was a comment*/
+                    continue;
+                }
+                if (line.matches("^\\s*$"))
+                {
+                    /* all whitespace */
+                    continue;
+                }
+                String[] val=line.split(" ");
+                
+                try
+                {
+                	Trace t=trace[current];
+                    t.pc=(int) parseInt(val[0]);
+                    t.opcode=(int) parseInt(val[1]);
+                    t.sp=(int) parseInt(val[2]);
+                    try
+                    {
+                    	t.undefinedStackA=false;
+                    	t.stackA=(int) parseInt(val[3]);
+                    } catch (NumberFormatException e)
+                    {
+                    	t.undefinedStackA=true;
+                    	t.stackB=0;
+                    }
+
+                    try
+                    {
+                    	t.undefinedStackB=false;
+                    	t.stackB=(int) parseInt(val[4]);
+                    } catch (NumberFormatException e)
+                    {
+                    	t.undefinedStackB=true;
+                    	t.stackB=0;
+                    }
+                    try
+                    {
+                    	t.undefinedIntSp=false;
+                    	t.intSp=(int) parseInt(val[5]);
+                    } catch (NumberFormatException e)
+                    {
+                    	t.undefinedIntSp=true;
+                    	t.intSp=0;
+                    }
+                   	t.cycle=parseInt(val[6]);
+                    trigger=true;
+                    break;
+                } catch (NumberFormatException e)
+                {
+                    /* skip this line. */
+                    e.printStackTrace();
+                }
+            }
+        } catch (IOException e)
+        {
+            throw new TraceException(e);
+        } 
+        
+    }
+
+    private long parseInt(String string2) throws TraceException
+    {
+        String string = string2;
+        if (!string.startsWith("0x"))
+        {
+            throw new TraceException(new Exception("Trace file pasing error line " + getFile().getLineNumber()));
+        }
+        return Long.parseLong(string.substring(2), 16);
+    }
+
+    public void instructionEvent() throws GDBServerException
+    {
+    	if (metEnd)
+    	{
+    		metEnd=false;
+    		throw new TraceException();
+    	}
+        if (resync&&trigger)
+        {
+            if (match())
+            {
+                /* we have to wait for the first instruction in the trace to be matched */
+            	System.out.println("First matching instruction found!");
+                resync=false;
+            }
+        } 
+
+        if (!resync&&trigger)
+        {
+        	
+            boolean m=match();
+            recordCurrent();
+            current=(current+1)%trace.length;
+
+            if (!m)
+            {
+                System.err.println("Trace file mismatch");
+                dumpTraceBack();
+                System.err.print("Expected by Java simulator: \n");
+                simulator.printState(this);
+                System.err.print("Actual from ModelSim: ");
+                System.err.println(line);
+                // we now have to ignore this match.
+                ignore=true;
+                throw new TraceException();
+            }
+        } else
+        {
+            recordCurrent();
+            current=(current+1)%trace.length;
+        }
+    }
+
+	public void dumpTraceBack()
+	{
+		System.err.println("Expected");
+		System.err.println("PC SP topOfStack");
+		for (int i=0; i<trace.length; i++)
+		{
+		    trace[(i+current)%trace.length].print();
+		}
+	}
+
+	private void recordCurrent()
+    {
+        recordState(trace[current]);
+    }
+
+	private void recordState(Trace trace3)
+	{
+		trace3.pc=simulator.getPc();
+        trace3.sp=simulator.getSp();
+        trace3.opcode=simulator.getOpcode();
+        try
+        {
+            trace3.stackA=simulator.cpuReadLong(simulator.getSp());
+            trace3.stackB=simulator.cpuReadLong(simulator.getSp()+4);
+            trace3.intSp=simulator.getIntSp();
+           // trace[current].cycle=expectetdCycle();
+        } catch (CPUException e1)
+        {
+            e1.printStackTrace();
+        }
+	}
+
+   
+    
+    boolean match() throws GDBServerException
+    {
+        if (ignore)
+            return true;
+        
+        return simulator.checkMatch(trace[current]);
+    }
+
+	public void commit()
+    {
+        try
+        {
+            if (!resync&&trigger)
+            {
+                ignore=false;
+                findNextTrigger();
+            }
+        } 
+        catch (Throwable e)
+        {
+            e.printStackTrace();
+        }
+    }
+
+    public void setSp(int sp)
+    {
+    }
+
+	public boolean onInterrupt()
+	{
+		if (trace[current].pc==0x20)
+			return true;
+		else
+			return false;
+	}
+
+	public boolean simInterrupt()
+	{
+		return true;
+	}
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Host.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Host.java
new file mode 100644
index 0000000..c1daa9f
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Host.java
@@ -0,0 +1,46 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+
+public interface Host
+{
+	/** generic file io error */
+	public final static int  EIO =    5;
+	
+    public final static int  SYS_read=    4;
+    public final static int  SYS_write=   5;
+	public final static int  SYS_argv   = 13;
+	public final static int SYS_exit=1;
+	public final static int  SYS_open=    2;
+	public final static int  SYS_close=   3;
+	public final static int  SYS_lseek =  6;
+	public final static int  SYS_unlink = 7;
+	public final static int  SYS_getpid = 8;
+	public final static int  SYS_kill  =  9;
+	public final static int  SYS_fstat =      10;
+	/*final static int  SYS_sbrk  11 - not currently a system call, but reserved.  */
+	/* ARGV support.  */
+	public final static int  SYS_argvlen= 12;
+	/* These are extras added for one reason or another.  */
+	public final static int  SYS_chdir  =  14;
+	public final static int  SYS_stat   =  15;
+	public final static int  SYS_chmod  =  16;
+	public final static int  SYS_utime  =  17;
+	public final static int  SYS_time   =  18;
+	public final static int  SYS_gettimeofday =19;
+	public final static int  SYS_times  =  20;
+	public final static int  SYS_link   =  21;
+	public final static int  SYS_ftruncate=3000;
+	public final static int  SYS_isatty=3001;
+    public void syscall(Sim s) throws CPUException;
+    boolean doneContinue();
+    public void writeUART(int val);
+    public int readUART() throws CPUException;
+    public int readFIFO();
+    /** notification that the CPU is halted */
+	public void halted();
+	/** notification that the CPU is running */
+	public void running();
+    
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java
new file mode 100644
index 0000000..3827378
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Machine.java
@@ -0,0 +1,17 @@
+
+package com.zylin.zpu.simulator;
+
+/**
+ * @author oyvind
+ *
+ * TODO To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Style - Code Templates
+ */
+public interface Machine
+{
+
+    long getPrevCycles();
+
+    long getCycles();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
new file mode 100644
index 0000000..862deae
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
@@ -0,0 +1,126 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Phi extends Simulator
+{
+	@Override
+	protected long getSampleOffset()
+	{
+		 
+		return super.getSampleOffset()-(0x5e7b2-0x0005E7C0);
+	}
+
+
+	public static void main(String[] args)
+	{
+        new SimApp(new SimFactory()
+        {
+        	public Simulator create()
+        	{
+        		return new Phi();
+        	}
+        }).run(args);
+	}
+    
+
+    protected int getIO()
+    {
+        return 0x08000000;
+    }
+
+
+
+    protected int ioRead(int addr) throws CPUException
+    {
+        switch (addr)
+        {
+        
+        case 0x080a0020:
+        	return interrupt?0:1; // interrupt mask
+
+        	
+        
+            /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+            case 0x080a000c:
+            	return 0x100; // buffer ready. 
+                
+            case 0x080a0014:
+            case 0x080a0018:
+            return readSampledTimer(addr, 0x080a0014);
+
+            case 0x080a0030:
+            	return timerPending?1:0;
+            case 0x080a0038:
+            	return (int)(timerInterval-1-((cycles-lastTimer)%timerInterval));
+
+            
+        	default:
+        		throw new MemoryAccessException();
+        }
+    }
+
+
+
+    protected void ioWrite(int addr, int val) throws MemoryAccessException
+    {
+        switch (addr)
+        {
+        case 0x080a0020:
+        	interrupt=(val&1)==0;
+        	return;
+        case 0x080a002c:
+        	timer=(val&0x1)!=0;
+        	break;
+        case 0x080a0030:
+        	if ((val&0x1)!=0)
+        	{
+        		timerPending=false;
+        	}
+        	if ((val&0x2)!=0)
+        	{
+        		lastTimer=cycles;
+        	}
+        	break;
+        case 0x080a0034:
+        	timerInterval=val;
+        	return;
+        	
+            case 0x080a0014:
+                writeTimerSampleReg(val);
+            case 0x080a000c:
+                syscall.writeUART(val);
+                break;
+        	default:
+                throw new MemoryAccessException();
+        }
+    }
+
+    Phi() throws CPUException
+    {
+    }
+
+    protected boolean emulateConfig()
+    {
+        return true;
+    }
+
+    protected int getStartStack()
+    {
+        return getRAMSIZE()-8;
+    }
+
+    protected int getRAMSIZE()
+    {
+        return 32*1024*1024;
+    }
+
+
+	protected int getIOSIZE()
+	{
+		return 0x100000;
+	}
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java b/zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java
new file mode 100644
index 0000000..79d3a38
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/PhiFeeble.java
@@ -0,0 +1,34 @@
+package com.zylin.zpu.simulator;
+
+public class PhiFeeble extends Phi
+{
+	public static void main(String[] args)
+	{
+        new SimApp(new SimFactory()
+        {
+        	public Simulator create()
+        	{
+        		return new PhiFeeble();
+        	}
+        }).run(args);
+	}
+	protected void setFeeble()
+	{
+//		feeble[NEQBRANCH] = false;
+//		feeble[EQ] = false;
+//		feeble[LOADB] = false;
+//		feeble[LESSTHAN] = false;
+//		feeble[ULESSTHAN] = false;
+//		feeble[STOREB] = false;
+//		feeble[MULT] = false;
+//		feeble[CALL] = true;
+//		feeble[POPPCREL] = true;
+//		feeble[LESSTHANOREQUAL] = true;
+//		feeble[ULESSTHANOREQUAL] = true;
+//
+//		feeble[PUSHSPADD] = false;
+//		feeble[CALLPCREL] = false;
+//		feeble[SUB] = false;
+	}
+	
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java
new file mode 100644
index 0000000..21450f7
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Sim.java
@@ -0,0 +1,62 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public interface Sim
+{
+/**
+     * halts the CPU. 
+     */
+    void suspend();
+    void writeByte(int i, int val) throws CPUException;
+    /** 
+     * synchronous method that returns when simulator enters the halt state. 
+     **/
+    void cont();
+    /** 
+     * synchronous method that returns when simulator finishes step or otherwise enters
+     * the halt state. 
+     **/
+    void step();
+
+    int getReg(int i) throws CPUException;
+
+    int getREGNUM();
+    int readByte(int addr) throws CPUException;
+
+    /**
+     * @param sp The sp to set.
+     * @throws CPUException 
+     */
+    void setSp(int sp) throws CPUException;
+
+    /**
+     * @return Returns the sp.
+     */
+    int getSp();
+
+    /**
+     * @param pc The pc to set.
+     * @throws MemoryAccessException
+     */
+    void setPc(int pc) throws MemoryAccessException;
+
+    /**
+     * @return Returns the pc.
+     */
+    int getPc();
+
+    void enableAccessWatchPoint(int address, int length) throws CPUException;
+
+    void disableAccessWatchPoint(int address, int length) throws CPUException;
+
+    int cpuReadLong(int i) throws CPUException;
+
+    void cpuWriteLong(int i, int retval) throws MemoryAccessException;
+
+    int getArg(int num) throws CPUException;
+	void sessionStarted();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
new file mode 100644
index 0000000..8008275
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
@@ -0,0 +1,112 @@
+package com.zylin.zpu.simulator;
+
+import java.io.IOException;
+import java.net.InetSocketAddress;
+import java.nio.channels.ServerSocketChannel;
+
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.gdb.GDBServer;
+
+public class SimApp
+{
+	private static Simulator simulator;
+	public ServerSocketChannel channel;
+    private String[] args;
+    private int portNumber;
+	private SimFactory simFactory;
+
+    public SimApp(SimFactory factory)
+	{
+    	simFactory=factory;
+	}
+
+	public void parseArgs()
+    {
+        portNumber = 4444;
+        if (args.length>=1)
+        {
+            portNumber=Integer.parseInt(args[0]);
+        }
+    }
+
+    private void moreParse()
+    {
+        if (args.length>=2)
+        {
+            simulator.setTraceFile(args[1]);
+        }
+    }
+
+	void run(String[] args)
+	{
+        this.args=args;
+        parseArgs();
+        try
+		{
+			channel = ServerSocketChannel.open();
+			try
+			{
+                System.out.println("Listening on port " + portNumber);
+				channel.socket().bind(new InetSocketAddress(portNumber));
+				for (;;)
+				{
+					try
+					{
+						simulator=simFactory.create();
+				        simulator.suspend();
+                        moreParse();
+						run();
+					} catch (CPUException e)
+					{
+						e.printStackTrace();
+					} 
+				}
+			} finally
+			{
+				channel.close();
+			}
+		} catch (IOException e1)
+		{
+			e1.printStackTrace();
+		}
+	
+	}
+
+    private void run() throws CPUException
+    {
+        final GDBServer gdbServer=new GDBServer(simulator, this);
+        simulator.setSyscall(gdbServer);
+        Thread thread = new Thread(new Runnable()
+                {
+                    public void run()
+                    {
+                        try
+                        {
+                            gdbServer.gdbServer();
+                        } 
+                        catch (Throwable e)
+                        {
+                            e.printStackTrace();
+                        }
+                        simulator.shutdown();
+                    }
+                });
+        thread.start();
+        try
+        {
+            simulator.run();
+        } 
+        finally
+        {
+            
+            try
+            {
+                thread.join();
+            } catch (InterruptedException e)
+            {
+                e.printStackTrace();
+            }
+        }
+            
+    }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java b/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java
new file mode 100644
index 0000000..4db85d7
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/SimFactory.java
@@ -0,0 +1,8 @@
+package com.zylin.zpu.simulator;
+
+public interface SimFactory
+{
+
+	Simulator create();
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
new file mode 100644
index 0000000..c1b86d4
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
@@ -0,0 +1,2063 @@
+package com.zylin.zpu.simulator;
+
+import java.io.ByteArrayOutputStream;
+import java.io.FileOutputStream;
+import java.io.IOException;
+import java.io.InputStream;
+import java.io.OutputStream;
+import java.util.Collections;
+import java.util.Comparator;
+import java.util.LinkedList;
+import java.util.List;
+
+import com.zylin.zpu.simulator.FileTracer.Trace;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.DebuggerBreakpointException;
+import com.zylin.zpu.simulator.exceptions.EndSessionException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.HardwareWatchPointException;
+import com.zylin.zpu.simulator.exceptions.IllegalInstructionException;
+import com.zylin.zpu.simulator.exceptions.InterruptException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+
+public class Simulator implements ZPU, Machine, Sim 
+{
+	
+    int minStack;
+
+    /** 
+	 * the feeble version of the CPU, e.g. only implements
+	 * 11 instructions. 
+     * 
+     * For debugging purposes it is useful to enable/disable
+     * each instruction
+	 */
+    boolean feeble[]=new boolean[256];
+	    
+	private long opcodeHistogram[]=new long[256];
+	private long opcodeHistogramCycles[]=new long[256];
+	private long opcodePairHistogram[]=new long[256*256];
+	private long opcodePairHistogramCycles[]=new long[256*256];
+	
+	/** weee! constants are 32 bit by default, so we need to assign a 64 bit
+	 * integer in this matter.
+	 */
+	private static final long INTMASK = Long.parseLong("ffffffff", 16);
+	
+    final static int PUSHPC=59;
+	final static int OR=7;
+	final static int NOT=9;
+	final static int LOAD=8;
+	final static int STORE=12;
+	final static int POPPC=4;
+	final static int FLIP=10;
+
+	final static int ADD=5;
+	final static int PUSHSP=2;
+	final static int POPSP=13;
+	final static int NOP=11;
+	final static int AND=6;
+	final static int ADDSP=16;
+
+    final static int EMULATE=32;
+	final static int LOADH=34;
+	final static int STOREH=35;
+	final static int LESSTHAN=36;
+	final static int LESSTHANOREQUAL=37;
+	final static int ULESSTHAN=38;
+	final static int ULESSTHANOREQUAL=39;
+    final static int SWAP=40;
+    final static int MULT=41;
+	final static int LSHIFTRIGHT=42;
+	final static int ASHIFTLEFT=43;
+    final static int ASHIFTRIGHT=44;
+    final static int CALL=45;
+    final static int EQ=46;
+	final static int NEQ=47;
+    final static int NEG=48;
+    final static int SUB=49;
+	final static int XOR=50;
+    final static int LOADB=51;
+    final static int STOREB=52;
+    final static int DIV=53;
+    final static int MOD=54;
+    final static int EQBRANCH=55;
+    final static int NEQBRANCH=56;
+    final static int POPPCREL=57;
+    final static int CONFIG=58;
+    final static int SYSCALL=60;
+    final static int PUSHSPADD=61;
+    final static int MULT16X16=62;
+    final static int CALLPCREL=63;
+    final static int STORESP=64;
+    final static int LOADSP=64+32;
+        
+	int[] memory;
+	boolean[] validMemory;
+	protected long cycles;
+	protected int instructionCount;
+	private int sp;
+	private int pc;
+	protected boolean breakNext;
+	
+	/* halting synchronization object */
+	protected Object halt = new Object();
+	
+	private int IOSIZE=getIOSIZE();
+	protected int getIOSIZE()
+	{
+		return 32768;
+	}
+	long prevCycles;
+	private static final int VECTORSIZE = 0x20;
+	private static final int VECTOR_RESET = 0;
+	private static final int VECTOR_INTERRUPT = 1;
+	private boolean hitVector;
+	private static final int VECTORBASE = 0x0;
+	private int nextVector;
+	protected long lastTimer;
+	protected boolean timer;
+	private boolean powerdown;
+    private boolean decodeMask;
+
+    private static final int ZETA = 1;
+
+    private static final int ABEL = 0;
+
+    private int startStack;
+
+    protected Host syscall;
+
+	private long[] emulateOpcodeHistogram= new long[256];
+
+	private long[] emulateOpcodeHistogramCycles=new long[256];
+
+	private long emulateCycles;;
+
+	public Simulator() throws CPUException
+	{
+	}
+	
+	
+	public void run() throws CPUException
+	{
+		syscall.running();
+		
+		try
+		{
+            
+			instructionLoop();
+			
+			
+		}  catch (EndSessionException e)
+		{
+			/* done */
+		} finally
+		{
+		}
+		dumpInfo();
+        
+        System.err.println("Stack usage: " + (startStack-minStack));
+	}
+
+	private void dumpInfo() 
+	{
+		dumpOpcodeHistogram();
+        
+		//printMemoryHistorgram();
+	}
+
+
+    private void dumpOpcodeHistogram()
+    {
+        System.out.println("Opcode histogram");
+        dumpHistogram(opcodeHistogram, opcodeHistogramCycles);
+        System.out.println("Emulate histogram");
+        dumpHistogram(emulateOpcodeHistogram, emulateOpcodeHistogramCycles);
+        System.out.println("Pair histogram");
+        dumpHistogram(opcodePairHistogram, opcodePairHistogramCycles);
+        
+        
+        dumpGmon();
+        
+        System.out.println("Grouping of LOADSP/STORESP/IM");
+        printRange(64, 96);
+        printRange(96, 128);
+        printRange(128, 256);
+//      printRange(64, 65);
+//        printRange(65, 66);
+//        printRange(66, 64+32);
+//        printRange(96, 97);
+//        printRange(97, 98);
+//        printRange(98, 96+32);
+//        printRange(128, 129);
+//        printRange(129, 130);
+//        printRange(130, 131);
+//        printRange(131, 132);
+//        printRange(132, 133);
+//        printRange(252, 253);
+//        printRange(253, 254);
+//        printRange(254, 255);
+//        printRange(255, 256);
+    }
+
+
+
+//    #define	GMON_MAGIC	"gmon"	/* magic cookie */
+//    #define GMON_VERSION	1	/* version number */
+//
+//    /*
+//     * Raw header as it appears on file (without padding):
+//     */
+//    struct gmon_hdr
+//    {
+//        char cookie[4];
+//        char version[4];    // a cyg_uint32, target-side endianness
+//        char spare[3 * 4];
+//    };
+//
+//    /* types of records in this file: */
+//    typedef enum
+//    {
+//        GMON_TAG_TIME_HIST = 0, GMON_TAG_CG_ARC = 1, GMON_TAG_BB_COUNT = 2
+//    }
+//    GMON_Record_Tag;
+//
+//    /* The histogram tag is followed by this header, and then an array of       */
+//    /* cyg_uint16's for the actual counts.                                      */
+//
+//    struct gmon_hist_hdr
+//    {
+//        /* host-side gprof adapts to sizeof(void*) and endianness.              */
+//        /* It is assumed that the compiler does not insert padding around the   */
+//        /* cyg_uint32's or the char arrays.                                     */
+//        void*       low_pc;             /* base pc address of sample buffer     */
+//        void*       high_pc;            /* max pc address of sampled buffer     */
+//        cyg_uint32  hist_size;          /* size of sample buffer                */
+//        cyg_uint32  prof_rate;          /* profiling clock rate                 */
+//        char        dimen[15];			/* phys. dim., usually "seconds"        */
+//        char        dimen_abbrev;		/* usually 's' for "seconds"            */
+//    };
+//
+//    /* An arc tag is followed by a single arc record. self_pc corresponds to    */
+//    /* the location of an mcount() call, at the start of a function. from_pc    */
+//    /* corresponds to the return address, i.e. where the function was called    */
+//    /* from. count is the number of calls.                                      */
+//
+//    struct gmon_cg_arc_record
+//    {
+//        void*       from_pc;            /* address within caller's body         */
+//        void*       self_pc;        	/* address within callee's body         */
+//        cyg_uint32  count;              /* number of arc traversals             */
+//    };
+//
+//    /* In theory gprof can also process basic block counts, as per the          */
+//    /* compiler's -fprofile-arcs flag. The compiler-generated basic block       */
+//    /* structure should contain a table of addresses and a table of counts,     */
+//    /* and the compiled code updates those counts. Current versions of the      */
+//    /* compiler (~3.2.1) do not output the table of addresses, and without      */
+//    /* that table gprof cannot process the counts. Possibly gprof should read   */
+//    /* in the .bb and .bbg files generated for gcov processing, but that does   */
+//    /* not happen at the moment.                                                */
+//    /*                                                                          */
+//    /* So for now gmon.out does not contain basic block counts and gprof        */
+//    /* operations that depend on it, e.g. --annotated-source, won't work.       */
+    
+    /**
+     * Write gmon.out file.
+     **/
+	private void dumpGmon()
+	{
+		try
+		{
+		ByteArrayOutputStream b=new ByteArrayOutputStream();
+		
+
+//	    /*
+//	     * Raw header as it appears on file (without padding):
+//	     */
+//	    struct gmon_hdr
+//	    {
+//	        char cookie[4];
+//	        char version[4];    // a cyg_uint32, target-side endianness
+//	        char spare[3 * 4];
+//	    };
+//	    #define	GMON_MAGIC	"gmon"	/* magic cookie */
+//	    #define GMON_VERSION	1	/* version number */
+
+//		   dump   binary memory gmon.out &profile_gmon_hdr ((char*)&profile_gmon_hdr + sizeof(struct gmon_hdr))
+			b.write("gmon".getBytes());
+			writeLong(b, 1); // version
+			b.write(new byte[3*4]); // spare
+			
+//		    GMON_TAG_TIME_HIST = 0, GMON_TAG_CG_ARC = 1, GMON_TAG_BB_COUNT = 2
+
+//			   append binary memory gmon.out &profile_tags[0] &profile_tags[1]
+			b.write(new byte[]{0}); // GMON_TAG_TIME_HIST 
+
+
+//			
+//		    // The gprof documentation claims that this should be the size in
+//		    // bytes. The implementation treats it as a count.
+//		    profile_hist_hdr.hist_size  = (cyg_uint32) ((text_size + bucket_size - 1) / bucket_size);
+//		    profile_hist_hdr.low_pc     = _start;
+//		    profile_hist_hdr.high_pc    = (void*)((cyg_uint8*)_end - 1);
+//		    // The prof_rate is the frequency in hz. The resolution argument is
+//		    // an interval in microseconds.
+//		    profile_hist_hdr.prof_rate  = 1000000 / resolution;
+//		        
+//		    // Now allocate a buffer for the histogram data.
+//		    profile_hist_data = (cyg_uint16*) malloc(profile_hist_hdr.hist_size * sizeof(cyg_uint16));
+//		    if ((cyg_uint16*)0 == profile_hist_data) {
+//		        diag_printf("profile_on(): cannot allocate histogram buffer - ignored\n");
+//		        return;
+//		    }
+//		    memset(profile_hist_data, 0, profile_hist_hdr.hist_size * sizeof(cyg_uint16));
+			
+
+			
+//		    struct gmon_hist_hdr
+//		    {
+//		        /* host-side gprof adapts to sizeof(void*) and endianness.              */
+//		        /* It is assumed that the compiler does not insert padding around the   */
+//		        /* cyg_uint32's or the char arrays.                                     */
+//		        void*       low_pc;             /* base pc address of sample buffer     */
+//		        void*       high_pc;            /* max pc address of sampled buffer     */
+//		        cyg_uint32  hist_size;          /* size of sample buffer                */
+//		        cyg_uint32  prof_rate;          /* profiling clock rate                 */
+//		        char        dimen[15];			/* phys. dim., usually "seconds"        */
+//		        char        dimen_abbrev;		/* usually 's' for "seconds"            */
+//		    };
+			
+
+			// maximum 65536 buckets.
+			int length=memory.length*4;
+			if (length > 60000)
+			{
+				length=60000;
+			}
+			int buckets[]=new int[length];
+			for (long i=0; i<profile.length;i++)
+			{
+				buckets[(int)((i*(((long)buckets.length)-1))/(((long)profile.length)-1))]+=profile[(int)i];
+			}
+			
+			
+			
+			//			   append binary memory gmon.out &profile_hist_hdr ((char*)&profile_hist_hdr + sizeof(struct gmon_hist_hdr))
+			writeLong(b, 0); 					// low_pc
+			writeLong(b, memory.length*4);		// high_pc
+			writeLong(b, buckets.length);		// # of samples
+			writeLong(b, 64000000); 			// 64MHz
+			b.write("seconds".getBytes());
+			b.write(new byte[15-"seconds".length()]);
+			b.write("s".getBytes());
+			
+			
+			
+//			   append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size)
+			for (int i=0; i<buckets.length;i++)
+			{
+				int val;
+				val=buckets[i];
+				if (val>65535)
+				{
+					val=65535;
+				}
+				writeShort(b, val);
+			}
+			
+			OutputStream o=new FileOutputStream("gmon.out");
+			b.writeTo(o);
+			o.flush();
+			o.close();
+			
+		} catch (IOException e)
+		{
+			// TODO Auto-generated catch block
+			e.printStackTrace();
+		}
+		
+
+		
+	}
+
+
+	private void writeLong(ByteArrayOutputStream b, int i) throws IOException
+	{
+		int val=i;
+		b.write(new byte[]{(byte)((val>>24)&0xff),
+				(byte)((val>>16)&0xff),
+				(byte)((val>>8)&0xff),
+				(byte)((val>>0)&0xff)});
+	}
+
+
+	private void writeShort(ByteArrayOutputStream b, int i) throws IOException
+	{
+		int val=i;
+		b.write(new byte[]{	(byte)((val>>8)&0xff),
+				(byte)((val>>0)&0xff)});
+	}
+
+
+	private void dumpHistogram(long[] ms, long[] ms2)
+	{
+		List<OpcodeSample> l=new LinkedList();
+        
+        totalCycles = 0;
+		for (int i=0; i<256; i++)
+		{
+			totalCycles+=opcodeHistogramCycles[i];
+		}
+		for (int i=0; i<ms.length; i++)
+		{
+			final int j=i;
+			l.add(new OpcodeSample(j, ms2[j]));
+		}
+        Collections.sort(l, new Comparator()
+        {
+
+			public int compare(Object arg0, Object arg1)
+			{
+				OpcodeSample a=(OpcodeSample) arg0, b=(OpcodeSample) arg1;
+				if (a.count<b.count)
+				{
+					return 1;
+				} else if (a.count==b.count)
+				{
+					return 0;
+				} else
+				{
+					return -1;
+				}
+			}
+        });
+        
+        for (int i=0; i<ms.length; i++)
+		{
+        	if (totalCycles==0)
+        		break;
+			double d = ((double)l.get(i).count/((double)totalCycles));
+			if (d<0.005)
+				break;
+			double cycPerIns = ((double)ms2[l.get(i).j]/((double)ms[l.get(i).j]));
+			System.out.println("0x"+ Integer.toHexString(l.get(i).j) + " " + d + " " + l.get(i).count + " " + cycPerIns );
+		}
+	}
+
+
+    private void printRange(int from, int to)
+    {
+        int totalLoadSP=0;
+        for (int i=from; i<to; i++)
+        {
+            totalLoadSP+=opcodeHistogram[i];
+        }
+        
+ 		double d = ((double)totalLoadSP/((double)totalCycles));
+         
+        System.out.println(""+ from + " " + d + " " + totalLoadSP);
+    }
+
+
+//    private void printMemoryHistorgram()
+//    {
+//        Arrays.sort(profile, new Comparator()
+//                {
+//                    public int compare(Object o1, Object o2)
+//                    {
+//                        return (int)(((Profile)o2).counter-
+//                                ((Profile)o1).counter);
+//                    }
+//                });
+//        System.err.println("Profiling information");
+//        for (int i=0; i<1000; i++)
+//        {
+//            if (profile[i].counter==0)
+//            {
+//                break;
+//            }
+//            System.err.println("0x"+Integer.toHexString(profile[i].address)+ " " + profile[i].counter);
+//        }
+//    }
+
+
+	/**
+	 * notify everybody that we are powering down
+	 */
+	public void shutdown()
+	{
+		powerdown=true;
+		/* wake up */
+		synchronized(halt)
+		{
+			halt.notify();
+		}
+	}
+
+
+	/**
+	 * This method can be invoked in two cases:
+	 * 
+	 * a) while the CPU is running on the simulator thread
+	 * b) while the CPU is halted from other threads
+	 */
+	protected void resetHardwareInternal() throws CPUException
+	{
+		interrupt=false;
+		timer=false;
+		lastTimer=0;
+		hitVector=false;
+		instructionCount=0;
+		for (int i=0; i<memory.length; i++)
+        {
+        	memory[i]=0;
+        }
+		
+		setPcToVector(VECTOR_RESET); // starting address
+        startStack=getStartStack();
+        minStack=startStack;
+		changeSp(startStack);
+		
+        intSp=0;
+
+	}
+
+
+	private void instructionLoop() throws EndSessionException, CPUException
+	{
+        /* wait for connection.... */
+        for (;;)
+        {
+            try
+            {
+
+                /*
+                 * execute an instruction.
+                 * 
+                 * If an exception happens while executing the instruction,
+                 * invoke the approperiate exception vector.
+                 * 
+                 * If a second exception occurs while invoking the
+                 * exception(i.e. before the first instruction of the vector
+                 * is executed), invoke the reboot exception.
+                 */
+                executeInstruction();
+            } catch (DebuggerBreakpointException e1)
+            {
+                suspend();
+            } catch (InterruptException e1)
+            {
+                armVector(VECTOR_INTERRUPT);
+            } catch (IllegalInstructionException e1)
+            {
+                suspend();
+            } catch (MemoryAccessException e1)
+            {
+                suspend();
+            } catch (CPUException e)
+            {
+                suspend();
+            } catch (GDBServerException e)
+            {
+                suspend();
+            }  catch (IOException e)
+            {
+                e.printStackTrace();
+                suspend();
+            } catch (RuntimeException e)
+            {
+                e.printStackTrace();
+                suspend();
+            } finally
+            {
+                checkCommit();
+            } 
+        }
+	}
+
+
+	private void armVector(int vector) 
+	{
+		// for now we always break as soon as we hit a vector
+		if (vector!=VECTOR_INTERRUPT)
+		{
+		//	print(MINIMAL, "Vector " + vector + " armed at PC: " + formatHex(pc, "00000000"));
+			suspend();
+		}
+		hitVector=true;
+		nextVector=vector;
+	}
+
+	private void checkVector() throws CPUException
+	{
+		if (hitVector)
+		{
+			hitVector=false;
+			invokeVector(nextVector);
+		}
+	}
+
+
+	private void invokeVector(int vector) throws CPUException 
+	{
+		push(pc);
+		setPcToVector(vector);
+	}
+
+	private void setPcToVector(int vector) throws MemoryAccessException
+	{
+		setPc(VECTORSIZE*vector+VECTORBASE);
+	}
+
+	private void executeInstruction() throws CPUException, EndSessionException, GDBServerException, IOException
+	{
+        for (;;)
+        {
+            checkHalt();
+            
+            /* jump to any armed vector */
+            checkVector();
+
+            checkInterrupts();
+            
+            tracer.instructionEvent();
+
+            
+            
+            
+            
+            commit = false;
+            savedSp=getSp();
+            savedPc=pc;
+            savedDecodeMask=decodeMask;
+            touchedPc=false;
+            
+            instruction=cpuReadByte(pc);
+            // electrons perish each time we attempt an instruction
+            tick();
+            
+            if (((instruction&0x80)!=0))
+            {
+                int t=((instruction<<(32-7)))>>(32-7);
+                
+                if (decodeMask)
+                {
+                    int a;
+                    a=(popIntStack()<<7)|(t&0x7f);
+                    pushIntStack(a);
+                } else
+                {
+                    pushIntStack(t);
+                }
+                decodeMask=true;
+            } else
+            {
+                decodeMask = false;
+                if (isAddSP(instruction))
+                {
+                    int offset=instruction - ADDSP;
+                    int valAddr=sp+offset*4;
+                    int a = popIntStack();
+                    pushIntStack(cpuReadLong(valAddr) + a);
+                } else if ((instruction >= LOADSP) && (instruction < LOADSP + 32))
+                {
+                    int addr;
+                    addr = getSp();
+                    int offset=(instruction - LOADSP)^0x10;
+                    addr += 4 * offset;
+                    pushIntStack(cpuReadLong(addr));
+                } else if (isStoreSP(instruction))
+                {
+                    int addr;
+                    addr = getSp();
+                    int offset=(instruction - STORESP)^0x10;
+                    addr += 4 * offset;
+
+                    cpuWriteLong(addr, popIntStack());
+                } else
+                {
+                    int addr;
+                    int val;
+                    switch (instruction)
+                    {
+                    case 0:
+                        throw new DebuggerBreakpointException();
+    
+                    case PUSHPC:
+                        pushIntStack(pc);
+                        break;
+                    case OR:
+                        pushIntStack(popIntStack() | popIntStack());
+                        break;
+                    case NOT:
+                        pushIntStack(popIntStack() ^ 0xffffffff);
+                        break;
+                    case LOAD:
+                        pushIntStack(cpuReadLong(popIntStack()));
+                        break;
+                    case PUSHSPADD:
+                        if (feeble[PUSHSPADD])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a=sp;
+                            b=popIntStack()*4;
+                            pushIntStack(a+b);
+                        }
+                        break;
+                    case STORE:
+                        addr = popIntOrExt();
+                        val = popIntOrExt();
+                        cpuWriteLong(addr, val);
+                        break;
+                    case POPPC:
+                    {
+                    	// NB!!!! does NOT flush internal stack
+                    	int a;
+                        if (intSp>0)
+                        {
+                        	a=popIntStack();
+                        } else
+                        {
+                        	a=pop();
+                        }
+                        
+                        if ((sp>=emulateSp)&&(emulateInProgress))
+                        {
+                        	emulateInProgress=false;
+                        	/* we returned from an emulate instruction */
+                        	emulateOpcodeHistogram[emulateOpcode]++;
+                        	emulateOpcodeHistogramCycles[emulateOpcode]+=cycles-emulateCycles;
+                        }
+                        
+                        setPc(a);
+                        break;
+                    }
+                    case POPPCREL:
+                        if (feeble[POPPCREL])
+                        {
+                            emulate();
+                        } else
+                        {
+                        	setPc(popIntStack()+getPc());
+                        }
+                        break;
+                    case FLIP:
+                        pushIntStack(flip(popIntStack()));
+                        break;
+                    case ADD:
+                        pushIntStack(popIntStack() + popIntStack());
+                        break;
+                    case SUB:
+                        if (feeble[SUB])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a=popIntStack();
+                            int b=popIntStack();
+                            pushIntStack(b-a);
+                        }
+                        break;
+                    case PUSHSP:
+                        pushIntStack(getSp());
+                        break;
+                    case POPSP:
+                        changeSp(popIntStack());
+                    	intSp=0;	// flush internal stack
+                        break;
+                    case NOP:
+                        break;
+                    case AND:
+                        pushIntStack(popIntStack() & popIntStack());
+                        break;
+                    case XOR:
+                        if (feeble[XOR])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(popIntStack() ^ popIntStack());
+                        }
+                        break;
+                    case LOADB:
+                        if (feeble[LOADB])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(cpuReadByte(popIntStack()));
+                        }
+                        break;
+                    case STOREB:
+                        if (feeble[STOREB])
+                        {
+                            emulate();
+                        } else
+                        {
+                            addr = popIntStack();
+                            val = popIntStack();
+                            cpuWriteByte(addr, val);
+                        }
+                        break;
+                    case LOADH:
+                        if (feeble[LOADH])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(cpuReadWord(popIntStack()));
+                        }
+                        break;
+                    case STOREH:
+                        if (feeble[STOREH])
+                        {
+                            emulate();
+                        } else
+                        {
+                            addr = popIntStack();
+                            val = popIntStack();
+                            cpuWriteWord(addr, val);
+                        }
+                        break;
+                    case LESSTHAN:
+                        if (feeble[LESSTHAN])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a = popIntStack();
+                            b = popIntStack();
+                            pushIntStack((a < b) ? 1 : 0);
+                        }
+                        break;
+                    case LESSTHANOREQUAL:
+                        if (feeble[LESSTHANOREQUAL])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a = popIntStack();
+                            b = popIntStack();
+                            pushIntStack((a <= b) ? 1 : 0);
+                        }
+                        break;
+                    case ULESSTHAN:
+                        if (feeble[ULESSTHAN])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long a;
+                            long b;
+                            a = ((long) popIntStack()) & INTMASK;
+                            b = ((long) popIntStack()) & INTMASK;
+                            pushIntStack((a < b) ? 1 : 0);
+                        }
+                        break;
+                    case ULESSTHANOREQUAL:
+                        if (feeble[ULESSTHANOREQUAL])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long a;
+                            long b;
+                            a = ((long) popIntStack()) & INTMASK;
+                            b = ((long) popIntStack()) & INTMASK;
+                            pushIntStack((a <= b) ? 1 : 0);
+                        }
+                        break;
+    
+                    case SWAP:
+//                      if (feeble[SWAP])
+//                      {
+//                          emulate();
+//                      } else
+                      {
+                          int swapVal=popIntStack();;
+                          pushIntStack(((swapVal >>16)&0xffff)|(swapVal<<16));
+                      }
+                      break;
+                    case MULT16X16:
+//                      if (feeble[SWAP])
+//                      {
+//                          emulate();
+//                      } else
+                      {
+                        int a=popIntStack();
+                        int b=popIntStack();
+                        pushIntStack((a&0xffff)*(b&0xffff));
+                      }
+                      break;
+                    case EQBRANCH:
+                        if (feeble[EQBRANCH])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int compare;
+                            int target;
+                            target = popIntStack() + pc;
+                            compare = popIntStack();
+                            if (compare == 0)
+                            {
+                                setPc(target);
+                            } else
+                            {
+                                setPc(pc + 1);
+                            }
+                        }
+                        break;
+    
+                    case NEQBRANCH:
+                        if (feeble[NEQBRANCH])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int compare;
+                            int target;
+                            target = popIntStack() + pc;
+                            compare = popIntStack();
+                            if (compare != 0)
+                            {
+                                setPc(target);
+                            } else
+                            {
+                                setPc(pc + 1);
+                            }
+                        }
+                        break;
+    
+                    case MULT:
+                        if (feeble[MULT])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(popIntStack() * popIntStack());
+                        }
+                        break;
+                    case DIV:
+                        if (feeble[DIV])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a = popIntStack();
+                            b = popIntStack();
+                            if (b == 0)
+                            {
+                                throw new CPUException();
+                            }
+                            pushIntStack(a / b);
+                        }
+                        break;
+                    case MOD:
+                        if (feeble[MOD])
+                        {
+                            emulate();
+                        } else
+                        {
+                            int a;
+                            int b;
+                            a = popIntStack();
+                            b = popIntStack();
+                            if (b == 0)
+                            {
+                                throw new CPUException();
+                            }
+                            pushIntStack(a % b);
+                        }
+                        break;
+    
+                    case LSHIFTRIGHT:
+                        if (feeble[LSHIFTRIGHT])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long shift;
+                            long valX;
+                            int t;
+                            shift = ((long) popIntStack()) & INTMASK;
+                            valX = ((long) popIntStack()) & INTMASK;
+                            t = (int) (valX >> (shift & 0x3f));
+                            pushIntStack(t);
+                        }
+                        break;
+    
+                    case ASHIFTLEFT:
+                        if (feeble[ASHIFTLEFT])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long shift;
+                            long valX;
+                            shift = ((long) popIntStack()) & INTMASK;
+                            valX = ((long) popIntStack()) & INTMASK;
+                            int t = (int) (valX << (shift & 0x3f));
+                            pushIntStack(t);
+                        }
+                        break;
+    
+                    case ASHIFTRIGHT:
+                        if (feeble[ASHIFTRIGHT])
+                        {
+                            emulate();
+                        } else
+                        {
+                            long shift;
+                            int valX;
+                            shift = ((long) popIntStack()) & INTMASK;
+                            valX = popIntStack();
+                            int t = valX >> (shift & 0x3f);
+                            pushIntStack(t);
+                        }
+                        break;
+    
+                    case CALL:
+                        if (feeble[CALL])
+                        {
+                            emulate();
+                        } else
+                        {
+                        	intSp=0;	// flush internal stack
+                            int address = pop();
+                            push(pc + 1);
+                            setPc(address);
+                        }
+                        break;
+                    case CALLPCREL:
+                        if (feeble[CALLPCREL])
+                        {
+                            emulate();
+                        } else
+                        {
+                        	intSp=0;	// flush internal stack
+                            int address = pop();
+                            push(pc + 1);
+                            setPc(address+pc);
+                        }
+                        break;
+    
+                    case EQ:
+                        if (feeble[EQ])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack((popIntStack() == popIntStack()) ? 1 : 0);
+                        }
+                        break;
+    
+                    case NEQ:
+                        if (feeble[NEQ])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack((popIntStack() != popIntStack()) ? 1 : 0);
+                        }
+                        break;
+    
+                    case NEG:
+                        if (feeble[NEG])
+                        {
+                            emulate();
+                        } else
+                        {
+                            pushIntStack(-popIntStack());
+                        }
+                        break;
+    
+                        
+                        case CONFIG:
+                        if (emulateConfig())
+                        {
+                            emulate();
+                            cpu=ABEL;
+                        } else
+                        {
+                            cpu = popIntStack();
+                        }
+                        switch (cpu)
+                        {
+                        case ABEL:
+                            System.err.println("ZPU feeble instruction set");
+                            for (int i = 0; i < feeble.length; i++)
+                            {
+                                feeble[i] = true;
+                            }
+
+                            setFeeble(); 
+                            
+                            break;
+                        case ZETA:
+                            System.err.println("ZPU full instruction set");
+                            for (int i = 0; i < feeble.length; i++)
+                            {
+                                feeble[i] = false;
+                            }
+                            break;
+                        default:
+                            break;
+                        }
+                        break;
+                        
+                    case SYSCALL:
+                        if (feeble[SYSCALL])
+                        {
+                            throw new IllegalInstructionException();
+                        } else
+                        {
+                        	intSp=0;	// flush internal stack
+                            syscall.syscall(this);
+                        }
+                        break;
+                            
+                    default:
+                        throw new IllegalInstructionException();
+                    }
+                }
+            }
+            if (!touchedPc)
+            {
+                setPc(pc + 1);
+            }
+            committed();
+            
+            // one more instruction retired
+            instructionCount++;
+        }
+	}
+
+
+	protected void setFeeble()
+	{
+		feeble[NEQBRANCH] = false;
+		feeble[EQ] = false;
+		feeble[LOADB] = false;
+		feeble[LESSTHAN] = false;
+		feeble[ULESSTHAN] = false;
+		feeble[STOREB] = false;
+		feeble[MULT] = false;
+		feeble[CALL] = true;
+		feeble[POPPCREL] = true;
+		feeble[LESSTHANOREQUAL] = true;
+		feeble[ULESSTHANOREQUAL] = true;
+
+		feeble[PUSHSPADD] = false;
+		feeble[CALLPCREL] = false;
+		feeble[SUB] = false;
+	}
+
+
+	private int popIntOrExt()
+	{
+		int a;
+		if (intSp==0)
+		{
+			a=pop();
+		} else
+		{
+			a=popIntStack();
+		}
+		return a;
+	}
+
+	int intSp;
+
+	private int emulateSp;
+
+	private int emulateOpcode;
+
+	private boolean emulateInProgress;
+
+	protected boolean timerPending;
+
+	private boolean inInterrupt;
+    private int popIntStack()
+	{
+//    	if (intSp<=0)
+//    		throw new IllegalInstructionException();
+    	intSp--;
+    	return pop();
+	}
+    
+    private void pushIntStack(int x)
+	{
+//    	if (intSp>=32)
+//    		throw new IllegalInstructionException();
+    	push(x);
+    	intSp++;
+	}
+
+
+
+    private static boolean isAddSP(int instruction)
+    {
+        return (instruction >= ADDSP) && (instruction < ADDSP + 16);
+    }
+
+
+    private static boolean isStoreSP(int instruction)
+    {
+        return (instruction >= STORESP) && (instruction < STORESP + 32);
+    }
+
+
+    protected boolean emulateConfig()
+    {
+        return false;
+    }
+
+
+    private void checkCommit() throws CPUException
+    {
+        if (!commit)
+        {
+            decodeMask=savedDecodeMask;
+            pc=savedPc;
+            setSp(savedSp);
+            committed();
+        }
+    }
+
+
+    private void committed()
+    {
+        commit=true;
+        tracer.commit();
+    }
+
+
+    private void emulate() throws CPUException
+	{
+    	// NB! Do NOT flush internal stack
+//    	intSp=0;	// flush internal stack
+        /* three total overhead to emulate instruction */
+    	if (!emulateInProgress)
+    	{
+    		emulateInProgress=true;
+	    	emulateSp = sp;
+	    	emulateOpcode = getOpcode();
+	    	emulateCycles = cycles;
+    	}
+		pushIntStack(pc+1);
+		setPc((cpuReadByte(pc)-32)*VECTORSIZE+VECTORBASE);
+	}
+
+
+
+	private void checkInterrupts() throws InterruptException
+	{
+		if (!tracer.simInterrupt())
+		{
+			/* These flags are set *regardless* of interrupt state. */
+			while (lastTimer+timerInterval<cycles)
+			{
+				if (timerInterval>0)
+				{
+					lastTimer+=timerInterval;
+				} else
+				{
+					lastTimer=cycles;
+				}
+				timerPending=true;
+			}
+		}
+		
+		if (!interrupt)
+			return;
+		
+        /* if we are in the middle of decoding an instruction, no interrupt */
+        if (decodeMask)
+        {
+        	return;
+        }
+        if (tracer.simInterrupt())
+        {
+    		if (!tracer.onInterrupt())
+    		{
+    			inInterrupt=false;
+    		}
+    		if (inInterrupt)
+    		{
+    			return;
+    		}
+            /* Use trace information instead of trying to figure out when an interrupt happens. We don't try
+             * to simulate anything more complicated than timer interrupts so we don't need to worry about source.
+             */
+            
+    		if (tracer.onInterrupt()&&!inInterrupt)
+    		{
+    			if (!timer)
+    			{
+    				throw new IllegalInstructionException();
+    			}
+    			
+    			inInterrupt=true;
+    			timerPending=true;
+    			throw new InterruptException();
+    		}
+            
+        } else
+        {
+    		if (!timerPending)
+    			inInterrupt=false;
+    		
+    		if (inInterrupt)
+    		{
+    			return;
+    		}
+            
+    		if (timer&&timerPending)
+    		{
+    			inInterrupt=true;
+    			throw new InterruptException();
+    		}
+        }
+	}
+
+
+
+	
+	private void cpuWriteWord(int addr, int val) throws MemoryAccessException
+	{
+		if ((addr&0x1)!=0)
+		{
+			throw new MemoryAccessException();
+		}
+		for (int i=0; i<2; i++)
+		{
+			writeByte(addr+i, val>>(8*(1-i)));
+		}
+	}
+
+	/**
+     * @param i
+     * @return
+     * @throws MemoryAccessException
+     */
+	private int cpuReadWord(int addr) throws MemoryAccessException
+	{
+		if ((addr&0x1)!=0)
+		{
+			throw new MemoryAccessException();
+		}
+		return ((readByteInternal(addr+0)&0xff)<<8) | (readByteInternal(addr+1)&0xff);
+	}
+
+	private void cpuWriteByte(int addr, int val) throws MemoryAccessException
+	{
+		writeByte(addr, val);
+	}
+
+
+	protected boolean interrupt;
+	protected long timerInterval;
+    private boolean touchedPc;
+
+	private boolean accessWatchPoint;
+
+	private int accessWatchPointAddress;
+
+	private int accessWatchPointLength;
+
+    private boolean commit;
+
+    private boolean savedDecodeMask;
+
+    private int savedSp;
+
+    private int savedPc;
+
+    private long[] profile;
+
+    private int cpu;
+
+    private long sampledCycle;
+
+    private Tracer tracer=new Tracer()
+    {
+
+        public void instructionEvent()
+        {
+            
+        }
+
+        public void commit()
+        {
+        }
+
+        public void setSp(int sp)
+        {
+        }
+
+		public void dumpTraceBack()
+		{
+			
+		}
+
+		public boolean onInterrupt()
+		{
+			return false;
+		}
+
+		public boolean simInterrupt()
+		{
+			return false;
+		}
+        
+    };
+
+    private int instruction;
+
+	private long totalCycles;
+
+	
+	private String traceFileName;
+
+	private int prevOpcode;
+
+	private long prevCycles2;
+
+	private int prevOpcode2;
+
+
+	
+
+	/**
+	 * checks if the CPU should halt, and halts. Fn. returns when the
+	 * CPU has resumed execution.
+	 * @throws EndSessionException 
+	 */
+	private void checkHalt() throws EndSessionException
+	{
+		synchronized(halt)
+		{
+			if (powerdown)
+			{
+				throw new EndSessionException();
+			}
+			
+			if (breakNext)
+			{
+				breakNext=false;
+				
+				halt.notify();
+				try
+				{
+					syscall.halted();
+					halt.wait();
+					syscall.running();
+				} catch (InterruptedException e)
+				{
+					e.printStackTrace();
+				}
+			}
+			
+			if (powerdown)
+			{
+				throw new EndSessionException();
+			}
+		}
+	}
+
+	private int flip(int i)
+	{
+		int t=0;
+		for (int j=0; j<32; j++)
+		{
+			t|=((i>>j)&1)<<(31-j);
+		}
+		return t;
+	}
+
+	/** the CPU is writing a long during execution */
+	public void cpuWriteLong(int addr, int val) throws MemoryAccessException
+	{
+		if (accessWatchPoint&&(addr==accessWatchPointAddress))
+		{
+			suspend();
+		}
+        if ((addr&0x3)!=0)
+        {
+            throw new MemoryAccessException();
+        }
+		if ((addr>=getIO())&&(addr<getIO()+IOSIZE))
+		{
+			ioWrite(addr, val);
+		} else if ((addr>=0)&&(addr<=memory.length*4))
+		{
+			memory[addr/4]=val;
+			validMemory[addr/4]=true;
+		} else
+        {
+            throw new MemoryAccessException();
+        }
+	}
+
+	public void writeByte(int addr, int val) throws MemoryAccessException
+	{
+		if ((addr>=0)&&(addr<memory.length*4))
+		{
+			memory[addr/4]=(memory[addr/4]&(~(0xff<<((3-addr&3)*8))))|((val&0xff)<<((3-addr&3)*8));
+		} else 
+		{
+			throw new MemoryAccessException();
+		}
+	}
+
+	protected void ioWrite(int addr, int val) throws MemoryAccessException
+	{
+        addr-=getIO();
+		/* note, big endian! */
+		switch (addr)
+		{
+			case 12:
+                syscall.writeUART(val);
+				break;
+			case 20:
+				interrupt=val!=0;
+				break;
+			case 28:
+				timerInterval=val;
+				break;
+			case 32:
+				timer=val!=0;
+				break;
+            case 0x24:
+                syscall.writeUART(val);
+                break;
+            case 0x100:
+                writeTimerSampleReg(val);
+                break;
+			default:
+                break;
+		}
+		
+	}
+
+
+
+
+    protected void writeTimerSampleReg(int val)
+    {
+        if ((val&0x2)!=0)
+        {
+            sampledCycle=getSampleOffset(); // we need a fudge factor to make up for differences in when relative to the instruction the data is sampled.
+        }
+    }
+
+
+	protected long getSampleOffset()
+	{
+		return cycles+2+0xd-(0x8e-0x74);
+	}
+	
+
+
+    protected int ioRead(int addr) throws CPUException
+	{
+        addr-=getIO();
+		/* note, big endian! */
+		switch (addr)
+		{
+			case 20:
+				return interrupt?1:0;
+				
+			case 32:
+				return timer?1:0;
+			
+            case 0x24:
+                return syscall.readUART();
+                
+                /* FIFO empty? bit 0, FIFO full bit 1(never the case) */
+            case 0x28:
+                return syscall.readFIFO();
+                
+            case 0x100:
+            case 0x104:
+            case 0x108:
+            case 0x10c:
+                
+            case 0x110:
+            case 0x114:
+            case 0x118:
+            case 0x11c:
+            return readSampledTimer(addr, 0x100);
+            
+            case 0x200:
+                return readMHz();
+                
+			default:
+				throw new MemoryAccessException();
+		}
+	}
+
+
+
+
+    protected int readMHz()
+    {
+        /* 90 MHz */
+        return 100;
+    }
+
+
+    protected int readSampledTimer(int addr, int base)
+    {
+        int t=0;
+        t=(int)((sampledCycle>>(((addr-base)/4)*32))&0xffffffff);
+        return t;
+    }
+
+
+
+	private int cpuReadByte(int addr) throws MemoryAccessException
+	{
+		return readByteInternal(addr);
+	}
+
+	
+	/** this is the CPU reading a long word during execution */
+	public int cpuReadLong(int addr) throws CPUException
+	{
+		if (accessWatchPoint&&(addr==accessWatchPointAddress))
+		{
+			suspend();
+		}
+		if ((addr&0x3)!=0)
+		{
+			throw new MemoryAccessException();
+		}
+		if ((addr>=getIO())&&(addr<getIO()+IOSIZE))
+		{
+			return ioRead(addr);
+		} else  if ((addr>=0)&&(addr<=memory.length*4))
+		{
+			return memory[addr/4];
+		} else
+        {
+            throw new MemoryAccessException();
+        }
+	}
+
+	/**
+	 * Causes a cycle to pass.
+	 * @throws MemoryAccessException 
+	 */
+	/** increase time and record how long we spent on this instruction */
+    private void tick() throws MemoryAccessException
+    {
+        profile[pc]++;
+        int opcode;
+        opcode=readByte(pc);
+        opcodeHistogram[prevOpcode]++;
+        opcodeHistogramCycles[prevOpcode]+=cycles-prevCycles;
+        int opcodePair=groupOpcode(prevOpcode2)*256+groupOpcode(prevOpcode);
+
+        opcodePairHistogram[opcodePair]++;
+        opcodePairHistogramCycles[opcodePair]+=cycles-prevCycles2;
+
+        prevOpcode2=prevOpcode;
+        prevOpcode=opcode;
+        
+        
+        
+        prevCycles2=prevCycles;
+        prevCycles=cycles;
+		cycles++;
+    }
+
+    private int groupOpcode(int instruction)
+	{
+        if (isAddSP(instruction))
+        {
+        	return ADDSP;
+        } else if ((instruction >= LOADSP) && (instruction < LOADSP + 32))
+        {
+        	return LOADSP;
+        } else if (isStoreSP(instruction))
+        {
+        	return STORESP;
+        }
+
+    	if ((instruction&0x80)!=0)
+    		return 0x80;
+    	return instruction;
+	}
+
+
+	public int readByte(int addr) throws MemoryAccessException
+	{
+		if ((addr>=0)&&(addr<memory.length*4))
+		{
+			return readByteInternal(addr);
+		} else
+		{
+			throw new MemoryAccessException();
+		}
+	}
+
+    
+	protected int readByteInternal(int addr) throws MemoryAccessException
+	{
+		return (memory[addr/4]>>((3-addr&0x3)*8))&0xff;
+	}
+
+	private int pop() throws CPUException
+	{
+		int val;
+		validMemory[getSp()/4]=false;
+		val=cpuReadLong(getSp());
+		setSp(getSp() + 4);
+		return val;
+	}
+
+	private void push(int imm) throws CPUException
+	{
+		setSp(getSp() - 4);
+		cpuWriteLong(getSp(), imm);
+	}
+
+    private  final class OpcodeSample
+	{
+		private final int j;
+
+		int opcode;
+
+		long count;
+
+		private OpcodeSample(int j, long l)
+		{
+			this.j = j;
+			opcode = j;
+			count = l;
+		}
+	}
+
+
+    
+
+	private void initRam()
+	{
+		memory = (new int[getRAMSIZE()/4]);
+		validMemory = new boolean[getRAMSIZE()/4];
+		for (int i=0; i<validMemory.length; i++)
+		{
+			validMemory[i]=true;
+		}
+		
+        profile = new long[getRAMSIZE()];
+	}
+
+	
+	
+	public void setPc(int pc) throws MemoryAccessException
+	{
+		if ((pc<VECTORBASE)||(pc>memory.length*4))
+		{
+			throw new MemoryAccessException();
+		}
+		this.pc = pc;
+        touchedPc=true;
+	}
+
+	public int getPc()
+	{
+		return pc;
+	}
+
+	/** resume execution. This function returns when the CPU halts again. */
+	public void cont()
+	{
+        for (;;)
+        {
+    		synchronized(halt)
+    		{
+    			halt.notify();
+    			try
+    			{
+    				halt.wait();
+    			} catch (InterruptedException e)
+    			{
+    				e.printStackTrace();
+    			}
+    		}
+            if (syscall.doneContinue())
+            {
+                    break;
+            }
+        }
+	}
+	
+    /** resume execution. This function returns when the CPU halts again. */
+	public void step()
+	{
+		synchronized(halt)
+		{
+			suspend();
+			cont();
+		}
+	}
+	
+
+	
+	public int getReg(int regNum) throws CPUException
+	{
+		if ((regNum>=0)&&(regNum<32))
+		{
+           	return memory[regNum];
+		} else if (regNum==32)
+		{
+			return getSp();
+		} else if (regNum==33)
+		{
+			return pc;
+		} else
+		{
+			throw new RuntimeException("Illegal getReg()");
+		}
+	}
+
+	public int getREGNUM()
+	{
+		return 34;
+	}
+
+	public long getCycleCounter()
+	{
+		return cycles;
+	}
+
+	public void addWaitStates(int num)
+	{
+	}
+
+	/** tells simulator to enter the suspended state */
+	public void suspend()
+	{
+		synchronized(halt)
+		{
+		    breakNext=true;
+		}
+//		tracer.dumpTraceBack();
+	}
+
+
+    public long getPrevCycles()
+    {
+        return prevCycles;
+    }
+
+    public long getCycles()
+    {
+        return cycles;
+    }
+
+
+	public void enableAccessWatchPoint(int address, int length) throws CPUException 
+	{
+		if (accessWatchPoint)
+		{
+			throw new HardwareWatchPointException();
+		}
+		accessWatchPointAddress=address;
+		accessWatchPointLength=length;
+		accessWatchPoint=true;
+	}
+	public void disableAccessWatchPoint(int address, int length) throws CPUException 
+	{
+		if (!accessWatchPoint)
+		{
+			throw new HardwareWatchPointException();
+		}
+		if ((address!=accessWatchPointAddress)||(length!=accessWatchPointLength))
+		{
+			throw new HardwareWatchPointException();
+		}
+		
+		accessWatchPoint=false;
+	}
+
+	/** POPSP changes the stack pointer */
+    public void changeSp(int sp) throws CPUException 
+    {
+        setSp(sp);
+        tracer.setSp(sp);
+    }
+
+    public void setSp(int sp) throws CPUException
+    {
+        if ((sp%4)!=0)
+        {
+            throw new IllegalInstructionException();
+        }
+        
+        if (sp<minStack)
+        {
+            minStack=sp;
+        }
+        
+        
+        this.sp = sp;
+    }
+
+
+    public int getSp()
+    {
+        return sp;
+    }
+    public int getIntSp()
+    {
+        return (intSp+(INTSTACKSIZE-1))%INTSTACKSIZE;
+    }
+
+
+    
+
+    protected int getIO()
+    {
+        return 0x80000000;
+    }
+
+
+    protected int getRAMSIZE()
+    {
+        return (16*1024*1024);
+    }
+
+    protected int getStartStack()
+    {
+        return memory.length*4-0x10000;
+    }
+
+
+    public void setTraceFile(String string)
+    {
+    	traceFileName=string;
+    }
+
+
+    public void setSyscall(Host syscall)
+    {
+        this.syscall=syscall;
+    }
+
+
+    public void loadImage(InputStream inputStream, int length) throws IOException, CPUException
+    {
+    	if (length==-1)
+    		throw new IOException("File image length not known");
+    	for (int i=0; i<length; i++)
+    	{
+		    int t=inputStream.read();
+		    writeByte(0+i, t);
+		} 
+        
+    }
+
+    public int getArg(int num) throws CPUException
+    {
+        return cpuReadLong(getSp()+4+num*4);
+    }
+
+
+	public int getOpcode() throws MemoryAccessException
+	{
+		return readByte(pc);
+	}
+
+	static final int INTSTACKSIZE=32;
+
+	public boolean checkMatch(Trace trace)
+	{
+		cycles=trace.cycle;
+		if (!trace.undefinedIntSp)
+		{
+			if (trace.intSp!=((intSp+(INTSTACKSIZE-1))%INTSTACKSIZE))
+				return false;
+		}
+		
+		if ((getPc() != trace.pc) || (getSp() != trace.sp)
+				|| (getOpcode() != trace.opcode))
+		{
+			return false;
+		}
+	    
+		if (cpuReadLong(getSp()) == trace.stackA)
+		{
+			if (cpuReadLong(getSp() + 4) == trace.stackB)
+			{
+				return true;
+			}
+		}
+		if ((!validMemory[getSp()/4])||cpuReadLong(getSp()) == trace.stackA)
+		{
+			if ((!validMemory[(getSp()+4)/4])||cpuReadLong(getSp() + 4) == trace.stackB)
+			{
+//				System.out.println("Undefined memory location mismatch");
+				return true;
+			}
+		}
+		if (!trace.undefinedIntSp)
+		{
+			if ((intSp<1)||cpuReadLong(getSp()) == trace.stackA)
+			{
+				if ((intSp<2)||cpuReadLong(getSp() + 4) == trace.stackB)
+				{
+					return true;
+				}
+			}
+		}
+	    return false;
+	}
+
+
+	public void sessionStarted()
+	{
+		if (traceFileName!=null)
+		{
+			tracer = new FileTracer(this, traceFileName);
+		}
+
+		/* Set the feeble flag to enable/disable instructions here */
+		initRam();
+		resetHardwareInternal();			
+
+
+		
+	}
+
+
+	void printState(FileTracer fileTracer)
+	{
+		System.err.println("intSp: " + getIntSp());
+		System.err.println(Integer.toHexString(getPc())+ " " +
+		Integer.toHexString(getOpcode()) + " " +
+		Integer.toHexString(getSp()) + " " + 
+		Integer.toHexString(cpuReadLong(getSp())) + " " + 
+		Integer.toHexString(cpuReadLong(getSp()+4)));
+	}
+
+
+	
+	
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/State.java b/zpu/sw/simulator/com/zylin/zpu/simulator/State.java
new file mode 100644
index 0000000..c2cb9f4
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/State.java
@@ -0,0 +1,9 @@
+package com.zylin.zpu.simulator;
+
+
+public class State
+{
+
+	public long cycle;
+	public int insn;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java
new file mode 100644
index 0000000..31f1766
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Tracer.java
@@ -0,0 +1,21 @@
+
+package com.zylin.zpu.simulator;
+
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+
+public interface Tracer
+{
+
+    void instructionEvent() throws GDBServerException;
+
+    void commit();
+
+    void setSp(int sp);
+    
+    void dumpTraceBack();
+
+    
+    boolean onInterrupt();
+    
+    boolean simInterrupt();
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java b/zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java
new file mode 100644
index 0000000..84a1ca5
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/ZPU.java
@@ -0,0 +1,14 @@
+package com.zylin.zpu.simulator;
+
+public interface ZPU
+{
+	/**
+	 * number of cycles passed since reboot
+	 */
+	long getCycleCounter();
+
+	/**
+	 * Wait this many cycles
+	 */
+	void addWaitStates(int i);
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java b/zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java
new file mode 100644
index 0000000..731c8fc
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/applet/ZPUApplet.java
@@ -0,0 +1,281 @@
+
+package com.zylin.zpu.simulator.applet;
+
+import java.applet.Applet;
+import java.awt.TextArea;
+import java.awt.event.KeyEvent;
+import java.awt.event.KeyListener;
+import java.io.IOException;
+import java.io.PipedInputStream;
+import java.io.PipedOutputStream;
+import java.lang.reflect.InvocationTargetException;
+import java.net.MalformedURLException;
+import java.net.URL;
+import java.net.URLConnection;
+
+import javax.swing.SwingUtilities;
+
+import com.zylin.zpu.simulator.Host;
+import com.zylin.zpu.simulator.Sim;
+import com.zylin.zpu.simulator.Simulator;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.UnsupportedSyscallException;
+
+public class ZPUApplet extends Applet implements Host
+{
+
+	private static final long serialVersionUID = 1L;
+	private TextArea console;
+    private Simulator simulator;
+	private PipedOutputStream outputPipe;
+	private PipedInputStream inputPipe;
+
+    public void init()
+    {
+        super.init();
+        
+        console=new TextArea();
+        //console.setEditable(false);
+
+        
+        console.addKeyListener(new KeyListener()
+                {
+
+                    public void keyPressed(KeyEvent e)
+                    {
+                    	try 
+                    	{
+							outputPipe.write((int)e.getKeyChar());
+						} catch (Throwable e1) 
+						{
+							e1.printStackTrace();
+						}
+                        
+                    }
+
+                    public void keyReleased(KeyEvent e)
+                    {
+                        
+                    }
+
+                    public void keyTyped(KeyEvent e)
+                    {
+                        
+                    }
+                });
+
+        //Add the text field to the applet.
+        add(console);
+
+        //Set the layout manager so that the text field will be
+        //as wide as possible.
+        setLayout(new java.awt.GridLayout(1,0));
+
+        validate();
+        initSimulator();
+        
+    }
+    
+    
+
+
+
+    public void start() 
+	{
+		super.start();
+	}
+
+
+
+
+
+	public void stop()
+    {
+        simulator.shutdown();
+        super.stop();
+    }
+
+    private void initSimulator()
+    {
+    	final ZPUApplet me = this;
+    	
+        try
+        {
+        	outputPipe = new PipedOutputStream();
+			inputPipe = new PipedInputStream(outputPipe);
+			
+			showStatus("Loading ZPU binary image...");
+
+			Thread thread = new Thread(new Runnable() {
+				public void run() {
+					try {
+						// lineReader=new LineNumberReader(new
+						// InputStreamReader(inputPipe));
+
+						simulator = new Simulator();
+						simulator.setSyscall(me);
+
+						String file = getParameter("executable");
+
+						URL url;
+						url = new URL(getCodeBase(), file);
+						showStatus("Loading: " + url.toString() +"...");
+
+						URLConnection connection = url.openConnection();
+						
+						simulator.loadImage(connection.getInputStream(), connection.getContentLength());
+
+						simulator.run();
+					} catch (Throwable e) {
+						e.printStackTrace();
+					}
+				}
+			});
+			thread.start();
+		} catch (MalformedURLException e) {
+            throw new RuntimeException(e);
+        } catch (IOException e)
+        {
+            throw new RuntimeException(e);
+        }
+    }
+
+    public void syscall(Sim s) throws CPUException
+    {
+        int retval=-1;
+        int syscallErrno=0;
+        int id;
+        id=simulator.getArg(1);
+        try
+        {
+	        switch (id)
+	        {
+	        case SYS_write:
+	            writeToConsole();
+	            retval=simulator.getArg(4);
+	            break;
+	        case SYS_read:
+	        	int i;
+	        	for (i=0; i<simulator.getArg(4); i++)
+	        	{
+	        		int t=inputPipe.read();
+        			simulator.writeByte(simulator.getArg(3)+i, t);
+        			if ((t=='\n')||(t=='\r'))
+        			{
+        				/* done reading line */
+        				i++;
+        				break;
+        			}
+	        	}
+	        	retval=i;
+	        	break;
+	        	
+	        case SYS_fstat:
+	        	syscallErrno=EIO;
+	        	retval=-1;
+	            break;
+	            
+	        default:
+	            simulator.suspend();
+	            throw new UnsupportedSyscallException();
+	        }
+        } 
+        catch (IOException e)
+        {
+            retval=-1;
+            syscallErrno=EIO;
+        }
+        simulator.cpuWriteLong(simulator.getArg(0), syscallErrno);
+        simulator.cpuWriteLong(0, retval);
+    }
+
+    private void writeToConsole() throws CPUException
+    {
+    	String t="";
+        for (int i=0; i<simulator.getArg(4); i++)
+        {
+        	t+=(char)simulator.readByte(simulator.getArg(3)+i);
+        }
+        final String t2=t;
+        System.out.println(t2);
+        try {
+			SwingUtilities.invokeAndWait(new Runnable()
+			        {
+			            public void run()
+			            {
+			                console.append(t2);
+			            }
+			        });
+		} catch (InterruptedException e) {
+			// TODO Auto-generated catch block
+			e.printStackTrace();
+		} catch (InvocationTargetException e) {
+			// TODO Auto-generated catch block
+			e.printStackTrace();
+		}
+    }
+
+
+
+
+    public boolean doneContinue()
+    {
+        return false;
+    }
+
+
+    public void writeUART(final int val)
+    {
+        try {
+			SwingUtilities.invokeAndWait(new Runnable()
+			        {
+
+			            public void run()
+			            {
+			                console.append(""+(char)(val));
+			                repaint();
+			                
+			            }
+			        });
+		} catch (InterruptedException e) {
+			e.printStackTrace();
+		} catch (InvocationTargetException e) {
+			e.printStackTrace();
+		}
+    }
+
+
+
+
+
+	public int readUART() throws CPUException 
+	{
+		try 
+		{
+			return inputPipe.read();
+		} catch (IOException e) 
+		{
+			e.printStackTrace();
+			throw new CPUException();
+		}
+	}
+
+
+
+
+
+	public int readFIFO() 
+	{
+		return 0;
+	}
+
+	public void halted()
+	{
+		showStatus("ZPU application halted");
+	}
+
+	public void running()
+	{
+		showStatus("ZPU application running...");
+	}
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java
new file mode 100644
index 0000000..2e66ab4
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/BadPacketException.java
@@ -0,0 +1,22 @@
+/*
+ * Created on Nov 6, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class BadPacketException extends GDBServerException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 3258131340821214260L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java
new file mode 100644
index 0000000..6a3f4fe
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/CPUException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on Oct 23, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class CPUException extends GDBServerException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+	
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java
new file mode 100644
index 0000000..2360fa8
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/DebuggerBreakpointException.java
@@ -0,0 +1,10 @@
+package com.zylin.zpu.simulator.exceptions;
+
+public class DebuggerBreakpointException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
new file mode 100644
index 0000000..7dd27e0
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
@@ -0,0 +1,22 @@
+/*
+ * Created on Nov 16, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class EndSessionException extends Exception
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java
new file mode 100644
index 0000000..8232790
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/GDBServerException.java
@@ -0,0 +1,25 @@
+package com.zylin.zpu.simulator.exceptions;
+
+
+public class GDBServerException extends RuntimeException
+{
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+
+	public GDBServerException(NumberFormatException e)
+	{
+		super(e);
+	}
+
+	public GDBServerException()
+	{
+		
+	}
+
+    public GDBServerException(Exception e)
+    {
+        super(e);
+    }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java
new file mode 100644
index 0000000..a4ad3b2
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/HardwareWatchPointException.java
@@ -0,0 +1,12 @@
+
+package com.zylin.zpu.simulator.exceptions;
+
+public class HardwareWatchPointException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java
new file mode 100644
index 0000000..a8d0802
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/IllegalInstructionException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on Oct 23, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class IllegalInstructionException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java
new file mode 100644
index 0000000..bd74f04
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/InterruptException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on 02.jan.2005
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class InterruptException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java
new file mode 100644
index 0000000..4c9ebae
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/MemoryAccessException.java
@@ -0,0 +1,23 @@
+/*
+ * Created on Oct 23, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class MemoryAccessException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java
new file mode 100644
index 0000000..377f9de
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/NoAckException.java
@@ -0,0 +1,22 @@
+/*
+ * Created on Nov 6, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.exceptions;
+
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public class NoAckException extends GDBServerException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java
new file mode 100644
index 0000000..45fda54
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/TraceException.java
@@ -0,0 +1,22 @@
+
+package com.zylin.zpu.simulator.exceptions;
+
+
+public class TraceException extends GDBServerException
+{
+
+    /**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+
+	public TraceException(Exception e)
+    {
+        super(e);
+    }
+
+    public TraceException()
+    {
+    }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java
new file mode 100644
index 0000000..af8a667
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnknownPacketException.java
@@ -0,0 +1,10 @@
+package com.zylin.zpu.simulator.exceptions;
+
+public class UnknownPacketException extends GDBServerException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java
new file mode 100644
index 0000000..6b214f1
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/UnsupportedSyscallException.java
@@ -0,0 +1,12 @@
+
+package com.zylin.zpu.simulator.exceptions;
+
+public class UnsupportedSyscallException extends CPUException
+{
+
+	/**
+	 * 
+	 */
+	private static final long serialVersionUID = 1L;
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
new file mode 100644
index 0000000..2580ded
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
@@ -0,0 +1,609 @@
+/** 
+ * Handles TCP/IP communication between simulator and GDB
+ */
+
+package com.zylin.zpu.simulator.gdb;
+
+import java.io.IOException;
+import java.nio.ByteBuffer;
+import java.nio.channels.SelectionKey;
+import java.nio.channels.Selector;
+import java.nio.channels.SocketChannel;
+import java.util.Iterator;
+
+import com.zylin.zpu.simulator.Host;
+import com.zylin.zpu.simulator.Sim;
+import com.zylin.zpu.simulator.SimApp;
+import com.zylin.zpu.simulator.exceptions.BadPacketException;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.EndSessionException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+import com.zylin.zpu.simulator.exceptions.UnsupportedSyscallException;
+
+public class GDBServer implements Host 
+{
+	static final boolean UNKNOWN=false;
+	static final boolean ALL=false;
+	static final boolean CPUEXCEPTION = false;
+	static protected boolean MINIMAL=true;
+	static boolean PACKET=false;
+	static boolean REPLY=false;
+	static protected boolean IGNOREDEXCEPTIONS=false;
+	protected Throwable packetException;
+	protected Object packetReady=new Object();
+	private Packet packet;
+	boolean done;
+	private Thread asyncMessage;
+	private Object listenBreak=new Object();
+	private boolean listenForBreak;
+	private boolean sleeping;
+	private ByteBuffer readBuffer;
+	private ByteBuffer writeBuffer;
+	private SocketChannel sc;
+	private Selector selectorRead;
+	private Selector selectorWrite;
+    public boolean alive;
+    static private int sessionNr;
+	private SimApp app;
+	private boolean stopAsyncMessage;
+    Sim simulator;
+    
+    public GDBServer(Sim simulator, SimApp app)
+    {
+        this.simulator=simulator;
+    	this.app=app;
+    }
+    
+	void print(boolean filter, String str)
+	{
+		if (filter)
+		{
+			System.out.println(str);
+		}
+	}
+	
+	/** infinite loop that waits for debug sessions to be initiated via TCP/IP */
+	public void gdbServer() throws MemoryAccessException, IOException, GDBServerException, EndSessionException 
+	{
+		try
+		{
+			asyncMessage = new Thread(new Runnable()
+			{
+				public void run()
+				{
+					asyncMessage();
+				}
+			});
+			asyncMessage.start();
+			try
+			{
+				readBuffer = ByteBuffer.allocate(1);
+				writeBuffer = ByteBuffer.allocate(128);
+				debugSession();
+			}
+			finally
+			{
+				/* tell it to stop waiting for break chars and wake up the thread */
+				stopAsyncMessage = true;
+				synchronized(listenBreak)
+				{
+					listenBreak.notify();
+				}
+				
+				try
+				{
+					asyncMessage.join();
+				} catch (InterruptedException e3)
+				{
+					e3.printStackTrace();
+				}
+			}
+		} catch (IOException e)
+		{
+			// the session failed...
+			if (IGNOREDEXCEPTIONS)
+			{
+				e.printStackTrace();
+			}
+		} catch (GDBServerException e)
+		{
+			// connect failed...
+			if (IGNOREDEXCEPTIONS)
+			{
+				e.printStackTrace();
+			}
+		} catch (EndSessionException e)
+		{
+		} catch (Throwable e)
+		{
+			// some terrible unforseen failure.
+			e.printStackTrace();
+		}
+	}
+
+	/**
+	 * We have to wait for break, but as soon as the main thread wants to wait
+	 * for packets again, we have to stop waiting for a break.
+	 * 
+	 * Tricky....
+	 */
+	private void asyncMessage()
+	{
+		for (;;)
+		{
+			synchronized(listenBreak)
+			{
+				if (stopAsyncMessage)
+				{
+					/* shutting down */
+					return;
+				}
+				try
+				{
+					sleeping=true;
+					listenBreak.notify();
+					
+					listenBreak.wait();
+					sleeping=false;
+					listenBreak.notify();
+				} catch (InterruptedException e)
+				{
+					e.printStackTrace();
+				}
+				if (stopAsyncMessage)
+				{
+					/* shutting down */
+					return;
+				}
+			}
+			
+			while (listenForBreak)
+			{
+				try
+				{
+					if (waitSelect(selectorRead, true))
+					{
+						int t = read();
+						if (t == 0x03)
+						{
+							// We received a ctrl-c while processing a package,
+							// this
+							// would be a suspend
+							simulator.suspend();
+						} else
+						{
+							// ignore garbage. Shouldn't happen.
+						}
+					} else
+					{
+						// we've been awoken since we're ready to send 
+						// the reply to the package...
+//						int x=0;
+					}
+				} catch (IOException e)
+				{
+					// Perfectly normal. This would happen if the connection
+					// is terminated.
+				}
+			}
+		}
+	}
+
+	/** wait for read/write ready */
+	private boolean waitSelect(Selector selector, boolean read) throws IOException
+	{
+		boolean gotit=false;
+		
+		selector.select(1000);
+		if (!sc.isOpen())
+		{
+			throw new IOException("Channel closed");
+		}
+		if (!sc.isConnected())
+		{
+			throw new IOException("Channel not connected");
+		}
+
+		// Get list of selection keys with pending events
+		Iterator it = selector.selectedKeys().iterator();
+		// Process each key at a time
+		while (it.hasNext())
+		{
+			// Get the selection key
+			SelectionKey selKey = (SelectionKey) it.next();
+			// Remove it from the list to indicate that it is being
+			// processed
+			it.remove();
+			if (selKey.isValid() && 
+					((read && selKey.isReadable()) || (!read && selKey.isWritable())))
+			{
+				gotit=true;
+			}
+			
+		}
+		return gotit;
+	}
+
+	
+	protected void sleepABit()
+	{
+		try
+		{
+			// just to avoid locking up the machine in a busy loop when
+			// debugging the Simulator
+			Thread.sleep(2000);
+		} catch (InterruptedException e1)
+		{
+			e1.printStackTrace();
+		}
+	}
+
+	private void debugSession() throws IOException, GDBServerException, EndSessionException, MemoryAccessException 
+	{
+		print(MINIMAL, "GDB server waiting for connection " + sessionNr++ + "...");
+
+		writeBuffer.clear();
+		readBuffer.clear();
+
+
+        selectorRead = Selector.open();
+        try
+        {
+            selectorWrite = Selector.open();
+            try
+            {
+				sc = app.channel.accept();
+		        try
+		        {
+		        	sc.socket().setKeepAlive(true);
+		            sc.configureBlocking(false);
+		            sc.register(selectorRead, SelectionKey.OP_READ);
+		            sc.register(selectorWrite, SelectionKey.OP_WRITE);
+		
+		            sessionStarted();
+		
+		            expect('+'); // connection ack.
+		
+		            sessionLoop();
+		        } finally
+		        {
+		            sc.close();
+		            
+					print(MINIMAL, "Session ended");
+		        }
+            } finally
+            {
+                selectorWrite.close();
+            }
+        } finally
+        {
+            selectorRead.close();
+        }
+	
+	}
+
+	private void sessionStarted()
+	{
+		simulator.sessionStarted();
+		print(MINIMAL, "Session started");
+	}
+
+	
+	private void sessionLoop() throws IOException, EndSessionException
+	{
+		alive=true;
+		while (alive)
+		{
+			try
+			{
+				/* wait for new packet to arrive and notify the packet execution thread... */
+				packet=new Packet(this);
+				packet.receive();
+		
+				enterListenForCtrlC();
+                
+				try
+				{
+					// During execution we can receive an abort/suspend command...
+					packet.parseAndExecute();
+				} 
+				finally
+				{
+					leaveListenForCtrlC();
+				}
+                
+				packet.sendReply();
+				
+				if (!alive)
+				    throw new EndSessionException();
+			} catch (BadPacketException e)
+			{
+				// do nothing.
+				if (IGNOREDEXCEPTIONS)
+				{
+					e.printStackTrace();
+				}
+				sleepABit();
+			} catch (GDBServerException e)
+			{
+				if (IGNOREDEXCEPTIONS)
+				{
+					e.printStackTrace();
+				}
+				// continue processing packets
+				sleepABit();
+			}
+		}
+	}
+
+    private void enterListenForCtrlC()
+    {
+        setBreakListen(true);
+    }
+
+    private void leaveListenForCtrlC()
+    {
+        /* we don't want to wait for the select to time out as that would make
+         * the protocol excruciatingly slow */
+        setBreakListen(false);
+        selectorRead.wakeup();
+        synchronized(listenBreak)
+        {
+        	try
+        	{
+        		while (!sleeping)
+        		{
+        			listenBreak.notify();
+        			listenBreak.wait();
+        		}
+        	} catch (InterruptedException e)
+        	{
+        		e.printStackTrace();
+        	}
+        }
+    }
+
+	private void setBreakListen(boolean state)
+	{
+		synchronized(listenBreak)
+		{
+			listenForBreak=state;
+			listenBreak.notify();
+		}
+	}
+
+	
+
+	void expect(char nextChar) throws IOException, GDBServerException
+	{
+		int t = read();
+		if (t!=nextChar)
+		{
+			throw new BadPacketException();
+		}
+	}
+
+	int read() throws IOException
+	{
+		flush();
+		readBuffer.clear();
+		for (;;)
+		{
+			int n;
+			n = sc.read(readBuffer);
+			if (n == 1)
+			{
+				break;
+			}
+			while (!waitSelect(selectorRead, true));
+		}
+		readBuffer.flip();
+		int t = readBuffer.get(0);
+		return t;
+	}
+
+	/**
+	 * @param value
+	 * @return
+	 */
+	protected String printHex(int value)
+	{
+		return formatHex(value, "00000000");
+	}
+
+	/**
+	 * @param value
+	 * @param pad TODO
+	 * @return
+	 */
+	protected String formatHex(int value, String pad)
+	{
+		String t=Integer.toHexString(value);
+		if (t.length()>pad.length())
+		{
+			t=t.substring(0, pad.length());
+		}
+		return pad.substring(0, pad.length()-t.length())+t;
+	}
+
+	public void write(byte[] bytes) throws IOException
+	{
+		int i=0;
+		while (i<bytes.length)
+		{
+			int len;
+			
+			while ((len=Math.min(bytes.length-i, writeBuffer.capacity()-writeBuffer.position()))==0)
+			{
+				flush();
+			}
+			
+			writeBuffer.put(bytes, i, len);
+			
+			i+=len;
+		}
+	}
+
+	void flush() throws IOException 
+	{
+		if (writeBuffer.position()>0)
+		{
+			writeBuffer.flip();
+			int len=writeBuffer.limit();
+	
+			int j=0;
+			while (j<len)
+			{
+				int t=sc.write(writeBuffer);
+				
+				if (t==0)
+				{
+					while (!waitSelect(selectorWrite, false));
+				}
+				j+=t;
+			}
+			writeBuffer.clear();
+		}		
+	}
+
+    
+    private boolean enterSyscall;
+
+
+    
+    /* handle all sorts of IO calls, etc. by sending them to the
+     */
+    public void syscall(Sim s) throws CPUException
+    {
+        simulator.suspend();
+        enterSyscall=true;
+    }
+
+
+    protected void performSyscall() 
+    {
+        enterSyscall=false;
+        try
+        {
+            int id;
+            id=simulator.getArg(1);
+            Packet syscall;
+            syscall=new Packet(this);
+            switch (id)
+            {
+            case Host.SYS_write:
+                syscall.invokeSyscall("write", 3, "iii");
+                break;
+            case Host.SYS_read:
+                syscall.invokeSyscall("read", 3, "iii");
+                break;
+            case Host.SYS_lseek:
+                syscall.invokeSyscall("lseek", 3, "iii");
+                break;
+            case Host.SYS_open:
+                syscall.invokeSyscall("open", 3, "sii");
+                break;
+            case Host.SYS_close:
+                syscall.invokeSyscall("close", 1, "i");
+                break;
+            case Host.SYS_fstat:
+                syscall.invokeSyscall("fstat", 2, "ii");
+                break;
+            case Host.SYS_stat:
+                syscall.invokeSyscall("stat", 2, "si");
+                break;
+            case Host.SYS_isatty:
+                syscall.invokeSyscall("isatty", 1, "i");
+                break;
+            case Host.SYS_unlink:
+                syscall.invokeSyscall("unlink", 1, "s");
+                break;
+            default:
+                simulator.suspend();
+                throw new UnsupportedSyscallException();
+            }
+            simulator.cpuWriteLong(simulator.getArg(0), syscall.syscallErrno);
+            simulator.cpuWriteLong(0, syscall.syscallRetval);
+        } catch (CPUException e)
+        {
+            e.printStackTrace();
+        } catch (IOException e)
+        {
+            e.printStackTrace();
+        } catch (GDBServerException e)
+        {
+            e.printStackTrace();
+        } catch (EndSessionException e)
+        {
+            e.printStackTrace();
+        }
+    }
+    
+    public boolean doneContinue()
+    {
+        if (!enterSyscall)
+            return true;
+        leaveListenForCtrlC();
+        try
+        {
+            performSyscall();
+        } finally
+        {
+            enterListenForCtrlC();
+        }
+        return false;
+    }
+    
+    public int getSyscallArg(int i) throws CPUException
+    {
+        return simulator.getArg(i+2);
+    }
+
+
+    public void writeUART(int val)
+    {
+        System.out.print((char)val);
+        System.out.flush();
+    }
+    public int readUART() throws CPUException
+    {
+        try
+        {
+            if (System.in.available()<=0)
+            {
+                throw new MemoryAccessException();
+            }
+            
+            return System.in.read();
+        } catch (IOException e)
+        {
+            e.printStackTrace();
+        }
+        return 0;
+    }
+
+    public int readFIFO()
+    {
+        try
+        {
+            return System.in.available()>0?0:1;
+        } catch (IOException e)
+        {
+            e.printStackTrace();
+        }
+        return 1;
+    }
+
+	public void halted()
+	{
+		// TODO Auto-generated method stub
+		
+	}
+
+	public void running()
+	{
+		// TODO Auto-generated method stub
+		
+	}
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
new file mode 100644
index 0000000..7925bd5
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
@@ -0,0 +1,455 @@
+/*
+ * Created on Nov 16, 2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.simulator.gdb;
+
+import java.io.IOException;
+import java.util.regex.Matcher;
+import java.util.regex.Pattern;
+
+import com.zylin.zpu.simulator.exceptions.BadPacketException;
+import com.zylin.zpu.simulator.exceptions.CPUException;
+import com.zylin.zpu.simulator.exceptions.EndSessionException;
+import com.zylin.zpu.simulator.exceptions.GDBServerException;
+import com.zylin.zpu.simulator.exceptions.MemoryAccessException;
+import com.zylin.zpu.simulator.exceptions.NoAckException;
+import com.zylin.zpu.simulator.exceptions.UnknownPacketException;
+
+
+/** all packet related operations */
+class Packet
+{
+	private final GDBServer server;
+	
+	Packet(GDBServer server)
+	{
+		this.server = server;
+        reply=new StringBuffer();
+	}
+	
+	void receive() throws IOException, GDBServerException, EndSessionException
+	{
+		int t;
+		/* we spool until we see a $ */
+		this.server.expect('$');
+		
+		StringBuffer packet=new StringBuffer();
+	
+		int cc=0;
+		for (;;)
+		{
+			int t1;
+			t1=this.server.read();
+			t = t1;
+			if (t==0x7d)
+			{
+				int t2;
+				t2=this.server.read();
+				/* the next char is escaped after a GDB specific scheme. See
+				 * gdb/gdb/remote.c */
+				t = t2;
+				t^=0x20;
+			} else
+			{
+				if (t=='#')
+				{
+					break;
+				}
+			}
+			
+			cc+=t;
+			
+			packet.append((char)t);
+		}
+		cc&=0xff;
+		
+		String checkSum;
+		checkSum=""+(char)this.server.read()+(char)this.server.read();
+		int readCheckSum;
+		readCheckSum=Integer.parseInt(checkSum, 16);
+		if (readCheckSum!=cc)
+		{
+			// error
+			dumpHex(packet.toString());
+			
+			this.server.write("-".getBytes());
+			throw new BadPacketException();
+		} else
+		{
+			// ack
+			this.server.write("+".getBytes());
+		}
+		
+		cmd=packet.toString();
+		this.server.print(GDBServer.PACKET, "Got " + number + ": #$" + cmd + "#" + checkSum); 
+		origCmd=cmd;
+	}
+	
+	void parseAndExecute() throws IOException, EndSessionException
+	{
+    	boolean silent=false;
+	    try
+		{
+			if (checkPrefix("g"))
+			{
+				readRegisters();
+			} else if (checkPrefix("?"))
+			{
+				querySignal();
+			} else if (checkPrefix("s"))
+			{
+				doStep();
+			} else if (checkPrefix("m"))
+			{
+				try
+				{
+					readMemory();
+				} catch (CPUException e)
+                {
+                    silent=true; // happens all the time while hovering over variables in the GUI
+                    throw e;
+                }
+			} else if (checkPrefix("c"))
+			{
+				continueExecution();
+			} else if (checkPrefix("M"))
+			{
+				writeMemory();
+			} else if (checkPrefix("z4"))
+			{
+				disableAccessWatchPoint();
+			} else if (checkPrefix("Z4"))
+			{
+				enableAccessWatchPoint();
+			} else if (checkPrefix("k"))
+			{
+				/* we must send a reply, but not wait for ack before we shut down
+				   the connection.
+				*/
+			    server.alive=false;
+			    reply("OK");
+			} else
+			{
+				throw new UnknownPacketException();
+			}
+		} catch (UnknownPacketException e)
+		{
+			this.server.print(GDBServer.UNKNOWN, "Unknown packet: " + origCmd);
+			// empty reply to unknown packets
+		} catch (CPUException e)
+        {
+            if (!silent)
+            {
+                this.server.print(GDBServer.CPUEXCEPTION, "Exception handling GDB request");
+                if (GDBServer.CPUEXCEPTION)
+                {
+                    e.printStackTrace();
+                }
+            }               
+            reply("E01");
+        } catch (GDBServerException e)
+        {
+            e.printStackTrace();
+            reply("E01");
+        }  catch (RuntimeException e)
+		{
+			e.printStackTrace();
+			reply("E01");
+		} 
+	}
+
+	private void checkEmpty() throws GDBServerException
+	{
+		if (cmd.length()>0)
+		{
+			throw new GDBServerException();
+		}
+	}
+	private void dumpHex(String arrayList2)
+	{
+		for (int i=0; i<arrayList2.length(); i++)
+		{
+			System.out.println(this.server.formatHex(arrayList2.charAt(i), "00"));
+		}
+	}
+	/**
+	 * @param packetString
+	 * @param string
+	 * @return
+	 */
+	private boolean checkPrefix(String string)
+	{
+		if (cmd.length() < string.length())
+		{
+			return false;
+		} else
+		{
+			return cmd.substring(0, string.length()).equals(string);
+		}
+	}
+	/**
+	 * @throws GDBServerException
+	 * @throws MemoryAccessException
+	 * 
+	 */
+	private void continueExecution() throws GDBServerException
+	{
+		extractString("c");
+		try
+		{
+			if (!isEmpty())
+			{
+				int pc=extractInteger();
+				this.server.simulator.setPc(pc);
+			}
+			checkEmpty();
+			this.server.simulator.cont();
+		} catch (MemoryAccessException e)
+		{
+			if (GDBServer.IGNOREDEXCEPTIONS)
+			{
+				e.printStackTrace();
+			}
+		}
+		reply("S05");
+	}
+	private void doStep()
+	{
+		this.server.simulator.step();
+		reply("S05");
+	}
+	protected int extractInteger() throws GDBServerException
+	{
+		String number;
+		Pattern p=Pattern.compile("(\\-?[0-9a-fA-F]+)");
+		Matcher m = p.matcher(cmd);
+		if (!m.find())
+		{
+			throw new GDBServerException();
+		}
+		number=m.group();
+		extractString(number);
+		
+		try
+		{
+			return (int)Long.parseLong(number, 16);
+		} catch (NumberFormatException e)
+		{
+			throw new GDBServerException(e);
+		}
+	}
+	/**
+	 * @param string
+	 * @throws GDBServerException
+	 */
+	private void extractString(String string) throws GDBServerException
+	{
+		if (!checkPrefix(string))
+		{
+			throw new GDBServerException();
+		}
+		stripStart(string.length());
+	}
+	/**
+	 * @throws GDBServerException
+	 * 
+	 */
+	private void readMemory() throws CPUException, GDBServerException
+	{
+		extractString("m");
+		int address=extractInteger();
+		extractString(",");
+		int length=extractInteger();
+		checkEmpty();
+		
+		for (int i=0; i<length; i++)
+		{
+			reply(this.server.formatHex(this.server.simulator.readByte(address+i), "00"));
+		}
+	}
+	/**
+	 * 
+	 */
+	private void readRegisters()  throws CPUException
+	{
+		for (int i=0; i<this.server.simulator.getREGNUM(); i++)
+		{
+			reply(this.server.printHex(this.server.simulator.getReg(i))); 
+		}
+	}
+	private void writeMemory() throws GDBServerException, MemoryAccessException
+	{
+		extractString("M");
+		int address=extractInteger();
+		extractString(",");
+		int length=extractInteger();
+		extractString(":");
+		
+		for (int i=0; i<length; i++)
+		{
+			String t;
+			t=cmd.substring(i*2, i*2+2);
+			int val;
+			val=Integer.parseInt(t, 16);
+			this.server.simulator.writeByte(address+i, val);
+		}
+		reply("OK");
+		
+	}
+	
+	private void enableAccessWatchPoint() throws GDBServerException, CPUException 
+	{
+		extractString("Z4");
+		extractString(",");
+		int address=extractInteger();
+		extractString(",");
+		int length=extractInteger();
+		checkEmpty();
+		server.simulator.enableAccessWatchPoint(address, length);
+		
+		reply("OK");
+	}
+
+	private void disableAccessWatchPoint() throws GDBServerException, CPUException 
+	{
+		extractString("z4");
+		extractString(",");
+		int address=extractInteger();
+		extractString(",");
+		int length=extractInteger();
+		checkEmpty();
+		server.simulator.disableAccessWatchPoint(address, length);
+		
+		reply("OK");
+	}
+
+	
+	private void stripStart(int length)
+	{
+		cmd=cmd.substring(length);
+	}
+	private boolean isEmpty() 
+	{
+		return cmd.length()==0;
+	}
+	/**
+	 * @param string
+	 */
+	protected void reply(String string)
+	{
+		reply.append(string);
+	}
+	void sendReply() throws IOException, NoAckException
+	{
+		// a bit easier to debug if we can see the entire string.
+		StringBuffer buffer = new StringBuffer();
+		buffer.append("$");
+		number++;
+		String replyString = reply.toString();
+		buffer.append(replyString);
+		byte[] data = replyString.toString().getBytes();
+		int csum = 0;
+		for (int i = 0; i < data.length; i++)
+		{
+			csum += data[i];
+		}
+		csum &= 0xff;
+		buffer.append("#");
+		String t = Integer.toHexString(csum);
+		if (t.length() == 1)
+		{
+			t = "0" + t;
+		}
+		buffer.append(t);
+		this.server.print(GDBServer.REPLY, "Reply " + number + " : " + buffer.toString());
+		this.server.write(buffer.toString().getBytes());
+		
+		if (server.alive)
+		{
+			/* check for ack. */
+			int ack = (char)this.server.read();
+			if (ack == '+')
+			{
+				return;
+			}
+			this.server.print(GDBServer.MINIMAL, "Retry");
+			
+			throw new NoAckException();
+		}
+	}
+	
+	private void querySignal()
+	{
+		// SIGINT
+		//	reply("S02");
+		reply("S05");
+	}
+	protected String cmd;
+	private int number;
+	private StringBuffer reply;
+	private String origCmd;
+    int syscallErrno;
+    int syscallRetval;
+
+
+    
+    void invokeSyscall(String string, int argNum, String types) throws IOException, NoAckException, GDBServerException, EndSessionException, CPUException
+    {
+        string="F"+string;
+        
+        int j=0;
+        for (int i=0; i<argNum; i++)
+        {
+            string+=",";
+            string+=Integer.toHexString(server.getSyscallArg(j));
+            j++;
+            if (types.charAt(i)=='s')
+            {
+                string+="/" + Integer.toHexString(server.getSyscallArg(j));
+                j++;
+            }
+        }
+
+        reply(string);
+        sendReply();
+        for (;;)
+        {
+            Packet packet=new Packet(server);
+            packet.receive();
+            if (packet.checkPrefix("F"))
+            {
+                /* this is the reply we are waiting for */
+                packet.extractString("F");
+                syscallRetval=packet.extractInteger();
+                syscallErrno=0;
+                if (packet.checkPrefix(","))
+                {
+                    /* errno is optional */
+                    packet.extractString(",");
+                    syscallErrno = packet.extractInteger();
+                }
+                break;
+            } else
+            {
+                /* something else... */
+                try
+                {
+                    packet.parseAndExecute();
+                    packet.sendReply();
+                } catch (IOException e)
+                {
+                    e.printStackTrace();
+                } catch (EndSessionException e)
+                {
+                    e.printStackTrace();
+                } catch (RuntimeException e)
+                {
+                    e.printStackTrace();
+                }
+            }
+        }
+    }
+}
\ No newline at end of file
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java
new file mode 100644
index 0000000..f641595
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeDRAM.java
@@ -0,0 +1,39 @@
+
+package com.zylin.zpu.simulator.tools;
+
+import java.io.FileInputStream;
+import java.io.IOException;
+
+public class MakeDRAM
+{
+    public static void main(String[] args) throws IOException
+    {
+       new MakeDRAM().run(args[0]);
+    }
+
+    private void run(String string) throws IOException
+    {
+        FileInputStream file=new FileInputStream(string);
+        
+        int i=0;
+        while (file.available()>4)
+        {
+            byte[] tmp=new byte[4];
+            file.read(tmp);
+            int word=0;
+            for (int j=0; j<4; j++)
+            {
+                word|=((int)(tmp[j])&0xff)<<((3-j)*8);
+            }
+            String str=Integer.toHexString(word);
+            while (str.length()<8)
+            {
+                str="0"+str;
+            }
+            
+            System.out.println(str);
+            i++;
+        }
+    }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java
new file mode 100644
index 0000000..4a7b233
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/tools/MakeRam.java
@@ -0,0 +1,39 @@
+
+package com.zylin.zpu.simulator.tools;
+
+import java.io.FileInputStream;
+import java.io.IOException;
+
+public class MakeRam
+{
+    public static void main(String[] args) throws IOException
+    {
+       new MakeRam().run(args[0]);
+    }
+
+    private void run(String string) throws IOException
+    {
+        FileInputStream file=new FileInputStream(string);
+        
+        int i=0;
+        while (file.available()>4)
+        {
+            byte[] tmp=new byte[4];
+            file.read(tmp);
+            int word=0;
+            for (int j=0; j<4; j++)
+            {
+                word|=((int)(tmp[j])&0xff)<<((3-j)*8);
+            }
+            String str=Integer.toHexString(word);
+            while (str.length()<8)
+            {
+                str="0"+str;
+            }
+            
+            System.out.println("" + i + " => x\"" + str + "\",");
+            i++;
+        }
+    }
+
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java b/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java
new file mode 100644
index 0000000..0f06aec
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/CountSequences.java
@@ -0,0 +1,94 @@
+/*
+ * Created on Jan 18, 2005
+ *
+ * TODO To change the template for this generated file go to
+ * Window - Preferences - Java - Code Style - Code Templates
+ */
+package com.zylin.zpu.stats;
+
+import java.io.File;
+import java.io.FileInputStream;
+import java.io.FileNotFoundException;
+import java.io.IOException;
+
+import com.zylin.zpu.simulator.Machine;
+
+public class CountSequences implements Machine
+{
+
+    private byte[] array;
+    private StatKeeper statKeeper;
+
+    public static void main(String[] args)
+    {
+        new CountSequences().run(args[0]);
+    }
+
+    private void run(String string)
+    {
+        try
+        {
+            File file=new File(string);
+            if (file.exists())
+                System.out.println("It exists!");
+            FileInputStream in=new FileInputStream(file);
+            
+            try
+            {
+                array=new byte[(int) file.length()];
+                
+                if (in.read(array)!=array.length)
+                    throw new IOException();
+                
+                countStats();
+                
+                statKeeper.printStats();
+            } finally
+            {
+                in.close();
+            }
+            
+        } catch (FileNotFoundException e)
+        {
+            e.printStackTrace();
+        } catch (IOException e)
+        {
+            e.printStackTrace();
+        }
+        
+        
+    }
+
+
+    private void countStats()
+    {
+        statKeeper=new StatKeeper(this);
+        for (int i=0; i<array.length; i++)
+        {
+            int j = array[i]&0xff;
+//            
+//            if ((j>=64)&&(j<96))
+//            {
+//                j=64;
+//            } else if ((j>=96)&&(j<128))
+//            {
+//                j=96;
+//            } else if ((j>=128)&&(j<256))
+//            {
+//                j=128;
+//            }
+            statKeeper.countInstruction(j);
+        }
+        
+    }
+
+    public long getPrevCycles()
+    {
+        return 0;
+    }
+
+    public long getCycles()
+    {
+        return 0;
+    }
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java b/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java
new file mode 100644
index 0000000..80be11d
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/DumpIt.java
@@ -0,0 +1,17 @@
+/*
+ * Created on 26.nov.2004
+ *
+ * To change the template for this generated file go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+package com.zylin.zpu.stats;
+/**
+ * @author oyvind
+ *
+ * To change the template for this generated type comment go to
+ * Window - Preferences - Java - Code Generation - Code and Comments
+ */
+public interface DumpIt
+{
+	int dumpIt(int i);
+}
\ No newline at end of file
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java b/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java
new file mode 100644
index 0000000..252dd7f
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/Instruction.java
@@ -0,0 +1,62 @@
+package com.zylin.zpu.stats;
+
+public class Instruction 
+{
+	public class DumpCycles implements DumpIt
+	{
+		public int dumpIt(int i)
+		{
+			return insn[i].cycles;
+		}
+	}
+
+
+
+	public Instruction[] insn=new Instruction[256];
+	public int count;
+	public int cycles;
+
+	public Instruction addInstruction(int i)
+	{
+		if (insn[i]==null)
+		{
+			insn[i]=new Instruction();
+		}
+		return insn[i];
+	}
+
+	/**
+	 * Recursive print of statistics
+	 */
+	public void printStats()
+	{
+		System.out.println("Count dump");
+		DumpIt cDump = new DumpCount();
+		printCount("", cDump);
+	}
+
+	/**
+	 * Recursive print of counts
+	 * @param string
+	 * @param dumpIt TODO
+	 */
+	private void printCount(String string, DumpIt dumpIt)
+	{
+		for (int i=0; i<insn.length; i++)
+		{
+			if (insn[i]!=null)
+			{
+				insn[i].printCount(string + ", " + i, dumpIt);
+				System.out.println("Count: " + insn[i].count + string + ", " + i);
+			}
+		}
+	}
+
+	class DumpCount implements DumpIt
+	{
+		public int dumpIt(int i)
+		{
+			return insn[i].count;
+		}
+	}
+}
diff --git a/zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java b/zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java
new file mode 100644
index 0000000..9e16e32
--- /dev/null
+++ b/zpu/sw/simulator/com/zylin/zpu/stats/StatKeeper.java
@@ -0,0 +1,52 @@
+package com.zylin.zpu.stats;
+
+import com.zylin.zpu.simulator.Machine;
+import com.zylin.zpu.simulator.State;
+
+public class StatKeeper
+{
+	private Instruction top=new Instruction();
+	private int trackPos;
+
+    private State[] state = new State[3];
+    private Machine simulator;
+	/**
+     * @param simulator
+     */
+    public StatKeeper(Machine simulator)
+    {
+        this.simulator=simulator;
+		for (int i=0; i<state.length; i++)
+		{
+			state[i]=new State();
+		}
+    }
+    /**
+	 * this instruction has been retired. Count it.
+	 */
+	public void countInstruction(int instruction)
+	{
+		State currentState=state[trackPos%state.length];
+		currentState.cycle=simulator.getPrevCycles(); // start of instruction
+		currentState.insn=instruction;
+		trackPos++;
+        int backtrackNum;
+		backtrackNum=Math.min(trackPos, state.length);
+		for (int i=0; i<backtrackNum; i++)
+		{
+            Instruction t=top;
+			for (int j=0; j<=i; j++)
+			{
+                currentState=state[(trackPos-backtrackNum+j)%state.length];
+				t=t.addInstruction(currentState.insn);
+			}
+            t.count++;
+		}
+		
+	}
+    public void printStats()
+    {
+        top.printStats();
+        
+    }
+}
diff --git a/zpu/sw/simulator/gmon.out b/zpu/sw/simulator/gmon.out
new file mode 100644
index 0000000..c49b3d7
Binary files /dev/null and b/zpu/sw/simulator/gmon.out differ
diff --git a/zpu/sw/simulator/zpusim.jar b/zpu/sw/simulator/zpusim.jar
new file mode 100644
index 0000000..e6e763a
Binary files /dev/null and b/zpu/sw/simulator/zpusim.jar differ
-- 
cgit v1.1


From e5627082149dbce408555bd3a128fd5d128880d2 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Thu, 21 Feb 2008 19:17:03 +0000
Subject: 	* zpu/zpu/sw/index.html. Changed it a bit to make installation
 easier.

---
 zpu/sw/env.sh     | 2 ++
 zpu/sw/index.html | 8 ++++----
 zpu/sw/setup.sh   | 6 ++++++
 3 files changed, 12 insertions(+), 4 deletions(-)
 create mode 100644 zpu/sw/env.sh
 create mode 100644 zpu/sw/setup.sh

(limited to 'zpu/sw')

diff --git a/zpu/sw/env.sh b/zpu/sw/env.sh
new file mode 100644
index 0000000..8ed43f0
--- /dev/null
+++ b/zpu/sw/env.sh
@@ -0,0 +1,2 @@
+export ZPUSW=`pwd`
+export PATH=$PATH:/tmp/zpu/install/bin
diff --git a/zpu/sw/index.html b/zpu/sw/index.html
index 6c860a9..fd0a1b4 100644
--- a/zpu/sw/index.html
+++ b/zpu/sw/index.html
@@ -9,10 +9,10 @@ some very basic peripherals defined: counter, timer interrupt and a debug output
 <li>Install Java
 <li>Start Cygwin bash
 <li>cd zpu/sw
-<li>unzip tools/zputoolchain.zip
-<li>zpu/sw/install/bin now has the .exe files for the GCC toolchain & GDB
-<li>You may want to add install/bin from zputoolchain.zip to PATH.<br>
-export PATH=$PATH:&lt;unzipdir&gt;/install/bin
+<li>sh setup.sh
+<li>/tmp/zpu/install/bin now has the .exe files for the GCC toolchain & GDB
+<li>Optionally you may set up PATH variables to point to /tmp/zpu/install/bin<br>
+source env.sh
 </ol>
 <h1>Hello world example</h1>
 The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification.
diff --git a/zpu/sw/setup.sh b/zpu/sw/setup.sh
new file mode 100644
index 0000000..57747f8
--- /dev/null
+++ b/zpu/sw/setup.sh
@@ -0,0 +1,6 @@
+. env.sh
+rm -rf /tmp/zpu
+mkdir -p /tmp/zpu/install/bin
+cd /tmp/zpu
+unzip $ZPUSW/tools/zputoolchain.zip
+
-- 
cgit v1.1


From 648a70893907a9cb446f1546d4fd39cf6457f0e8 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Fri, 22 Feb 2008 12:38:46 +0000
Subject: * Hooked up support for the simulator to the Zylin Embedded CDT

---
 zpu/sw/simulator/.classpath                        |   1 +
 zpu/sw/simulator/.project                          |  11 +
 zpu/sw/simulator/ChangeLog                         |   2 +
 zpu/sw/simulator/META-INF/MANIFEST.MF              |  11 +
 zpu/sw/simulator/build.properties                  |   3 +
 zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java  |   2 +-
 .../simulator/com/zylin/zpu/simulator/SimApp.java  |  93 +++++-
 .../com/zylin/zpu/simulator/Simulator.java         |   2 +
 .../simulator/exceptions/EndSessionException.java  |  24 ++
 .../com/zylin/zpu/simulator/gdb/GDBServer.java     | 313 +++------------------
 .../com/zylin/zpu/simulator/gdb/Packet.java        |  23 +-
 11 files changed, 188 insertions(+), 297 deletions(-)
 create mode 100644 zpu/sw/simulator/META-INF/MANIFEST.MF
 create mode 100644 zpu/sw/simulator/build.properties

(limited to 'zpu/sw')

diff --git a/zpu/sw/simulator/.classpath b/zpu/sw/simulator/.classpath
index 617be7e..5e4fa9f 100644
--- a/zpu/sw/simulator/.classpath
+++ b/zpu/sw/simulator/.classpath
@@ -2,5 +2,6 @@
 <classpath>
 	<classpathentry excluding="bin/" kind="src" output="bin" path=""/>
 	<classpathentry kind="con" path="org.eclipse.jdt.launching.JRE_CONTAINER"/>
+	<classpathentry kind="con" path="org.eclipse.pde.core.requiredPlugins"/>
 	<classpathentry kind="output" path=""/>
 </classpath>
diff --git a/zpu/sw/simulator/.project b/zpu/sw/simulator/.project
index 9cd2fd7..29c7a4f 100644
--- a/zpu/sw/simulator/.project
+++ b/zpu/sw/simulator/.project
@@ -10,8 +10,19 @@
 			<arguments>
 			</arguments>
 		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.pde.ManifestBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.pde.SchemaBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
 	</buildSpec>
 	<natures>
 		<nature>org.eclipse.jdt.core.javanature</nature>
+		<nature>org.eclipse.pde.PluginNature</nature>
 	</natures>
 </projectDescription>
diff --git a/zpu/sw/simulator/ChangeLog b/zpu/sw/simulator/ChangeLog
index c645841..18b0981 100644
--- a/zpu/sw/simulator/ChangeLog
+++ b/zpu/sw/simulator/ChangeLog
@@ -1,2 +1,4 @@
+2008-02-22 Øyvind Harboe
+	* Hooked up support for the simulator to the Zylin Embedded CDT
 2007-08-04 Øyvind Harboe
 	* First version after open sourcing ZPU
diff --git a/zpu/sw/simulator/META-INF/MANIFEST.MF b/zpu/sw/simulator/META-INF/MANIFEST.MF
new file mode 100644
index 0000000..b0ad5b9
--- /dev/null
+++ b/zpu/sw/simulator/META-INF/MANIFEST.MF
@@ -0,0 +1,11 @@
+Manifest-Version: 1.0
+Bundle-ManifestVersion: 2
+Bundle-Name: ZPU simulator
+Bundle-SymbolicName: com.zylin.zpu.simulator
+Bundle-Version: 1.0.0
+Export-Package: com.zylin.zpu.simulator,
+ com.zylin.zpu.simulator.applet,
+ com.zylin.zpu.simulator.exceptions,
+ com.zylin.zpu.simulator.gdb,
+ com.zylin.zpu.simulator.tools,
+ com.zylin.zpu.stats
diff --git a/zpu/sw/simulator/build.properties b/zpu/sw/simulator/build.properties
new file mode 100644
index 0000000..19c7019
--- /dev/null
+++ b/zpu/sw/simulator/build.properties
@@ -0,0 +1,3 @@
+source.. = .
+bin.includes = META-INF/,\
+               .
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
index 862deae..0e3e7a1 100644
--- a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
@@ -98,7 +98,7 @@ public class Phi extends Simulator
         }
     }
 
-    Phi() throws CPUException
+    public Phi() throws CPUException
     {
     }
 
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
index 8008275..3f6e1a9 100644
--- a/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/SimApp.java
@@ -2,6 +2,8 @@ package com.zylin.zpu.simulator;
 
 import java.io.IOException;
 import java.net.InetSocketAddress;
+import java.net.ServerSocket;
+import java.net.Socket;
 import java.nio.channels.ServerSocketChannel;
 
 import com.zylin.zpu.simulator.exceptions.CPUException;
@@ -10,7 +12,6 @@ import com.zylin.zpu.simulator.gdb.GDBServer;
 public class SimApp
 {
 	private static Simulator simulator;
-	public ServerSocketChannel channel;
     private String[] args;
     private int portNumber;
 	private SimFactory simFactory;
@@ -40,39 +41,65 @@ public class SimApp
 	void run(String[] args)
 	{
         this.args=args;
+		createSimulator();
         parseArgs();
+        moreParse();
+        runSimAndGDB();
+	}
+	Object launched=new Object();
+	private boolean doneLaunching;
+	private boolean manyGDBSessions;
+	public ServerSocket serverSocket;
+	public void runSimAndGDB()
+	{
         try
 		{
-			channel = ServerSocketChannel.open();
+			serverSocket = new ServerSocket(portNumber);
 			try
 			{
+				serverSocket.setReuseAddress(true);
                 System.out.println("Listening on port " + portNumber);
-				channel.socket().bind(new InetSocketAddress(portNumber));
-				for (;;)
-				{
+                setLaunchedFlag();
+                do 
+                {
 					try
 					{
-						simulator=simFactory.create();
-				        simulator.suspend();
-                        moreParse();
-						run();
+						runGDBServer();
 					} catch (CPUException e)
 					{
 						e.printStackTrace();
-					} 
-				}
+					}
+                } while (manyGDBSessions);
 			} finally
 			{
-				channel.close();
+				serverSocket.close();
 			}
 		} catch (IOException e1)
 		{
 			e1.printStackTrace();
+		} finally
+		{
+            setLaunchedFlag();
 		}
 	
 	}
 
-    private void run() throws CPUException
+	private void setLaunchedFlag()
+	{
+		synchronized(launched)
+		{
+			doneLaunching=true;
+			launched.notify();
+		}
+	}
+
+	public void createSimulator()
+	{
+		simulator=simFactory.create();
+        simulator.suspend();
+	}
+
+    private void runGDBServer() throws CPUException
     {
         final GDBServer gdbServer=new GDBServer(simulator, this);
         simulator.setSyscall(gdbServer);
@@ -98,7 +125,6 @@ public class SimApp
         } 
         finally
         {
-            
             try
             {
                 thread.join();
@@ -109,4 +135,43 @@ public class SimApp
         }
             
     }
+
+	public Simulator getSimulator()
+	{
+		return simulator;
+	}
+
+	public void setPort(int i)
+	{
+		portNumber=i;
+	}
+
+	/** synchronous launch of GDB server */
+	public void launchGDBServer()
+	{
+		Thread t=new Thread(new Runnable()
+		{
+
+			public void run()
+			{
+				runSimAndGDB();
+			}
+		});
+		t.start();
+		synchronized (launched)
+		{
+			while (!doneLaunching)
+			{
+				try
+				{
+					launched.wait(2000);
+				} catch (InterruptedException e)
+				{
+					e.printStackTrace();
+				}
+			}
+		}
+		
+		
+	}
 }
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
index c1b86d4..791e253 100644
--- a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
@@ -268,6 +268,8 @@ public class Simulator implements ZPU, Machine, Sim
      **/
 	private void dumpGmon()
 	{
+		if (memory==null)
+			return;
 		try
 		{
 		ByteArrayOutputStream b=new ByteArrayOutputStream();
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
index 7dd27e0..13fc875 100644
--- a/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/exceptions/EndSessionException.java
@@ -15,6 +15,30 @@ package com.zylin.zpu.simulator.exceptions;
 public class EndSessionException extends Exception
 {
 
+	public EndSessionException()
+	{
+		super();
+		// TODO Auto-generated constructor stub
+	}
+
+	public EndSessionException(String arg0, Throwable arg1)
+	{
+		super(arg0, arg1);
+		// TODO Auto-generated constructor stub
+	}
+
+	public EndSessionException(String arg0)
+	{
+		super(arg0);
+		// TODO Auto-generated constructor stub
+	}
+
+	public EndSessionException(Throwable arg0)
+	{
+		super(arg0);
+		// TODO Auto-generated constructor stub
+	}
+
 	/**
 	 * 
 	 */
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
index 2580ded..182e426 100644
--- a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/GDBServer.java
@@ -5,6 +5,7 @@
 package com.zylin.zpu.simulator.gdb;
 
 import java.io.IOException;
+import java.net.Socket;
 import java.nio.ByteBuffer;
 import java.nio.channels.SelectionKey;
 import java.nio.channels.Selector;
@@ -23,30 +24,25 @@ import com.zylin.zpu.simulator.exceptions.UnsupportedSyscallException;
 
 public class GDBServer implements Host 
 {
+	/* logging filter */
 	static final boolean UNKNOWN=false;
 	static final boolean ALL=false;
 	static final boolean CPUEXCEPTION = false;
 	static protected boolean MINIMAL=true;
-	static boolean PACKET=false;
-	static boolean REPLY=false;
+	static boolean PACKET=true;
+	static boolean REPLY=true;
 	static protected boolean IGNOREDEXCEPTIONS=false;
+	
+	
+	
 	protected Throwable packetException;
 	protected Object packetReady=new Object();
 	private Packet packet;
 	boolean done;
-	private Thread asyncMessage;
-	private Object listenBreak=new Object();
-	private boolean listenForBreak;
-	private boolean sleeping;
-	private ByteBuffer readBuffer;
-	private ByteBuffer writeBuffer;
-	private SocketChannel sc;
-	private Selector selectorRead;
-	private Selector selectorWrite;
+	private Socket sc;
     public boolean alive;
     static private int sessionNr;
 	private SimApp app;
-	private boolean stopAsyncMessage;
     Sim simulator;
     
     public GDBServer(Sim simulator, SimApp app)
@@ -66,39 +62,10 @@ public class GDBServer implements Host
 	/** infinite loop that waits for debug sessions to be initiated via TCP/IP */
 	public void gdbServer() throws MemoryAccessException, IOException, GDBServerException, EndSessionException 
 	{
+		sc=app.serverSocket.accept();
 		try
 		{
-			asyncMessage = new Thread(new Runnable()
-			{
-				public void run()
-				{
-					asyncMessage();
-				}
-			});
-			asyncMessage.start();
-			try
-			{
-				readBuffer = ByteBuffer.allocate(1);
-				writeBuffer = ByteBuffer.allocate(128);
-				debugSession();
-			}
-			finally
-			{
-				/* tell it to stop waiting for break chars and wake up the thread */
-				stopAsyncMessage = true;
-				synchronized(listenBreak)
-				{
-					listenBreak.notify();
-				}
-				
-				try
-				{
-					asyncMessage.join();
-				} catch (InterruptedException e3)
-				{
-					e3.printStackTrace();
-				}
-			}
+			debugSession();
 		} catch (IOException e)
 		{
 			// the session failed...
@@ -119,111 +86,12 @@ public class GDBServer implements Host
 		{
 			// some terrible unforseen failure.
 			e.printStackTrace();
-		}
-	}
-
-	/**
-	 * We have to wait for break, but as soon as the main thread wants to wait
-	 * for packets again, we have to stop waiting for a break.
-	 * 
-	 * Tricky....
-	 */
-	private void asyncMessage()
-	{
-		for (;;)
+		} finally
 		{
-			synchronized(listenBreak)
-			{
-				if (stopAsyncMessage)
-				{
-					/* shutting down */
-					return;
-				}
-				try
-				{
-					sleeping=true;
-					listenBreak.notify();
-					
-					listenBreak.wait();
-					sleeping=false;
-					listenBreak.notify();
-				} catch (InterruptedException e)
-				{
-					e.printStackTrace();
-				}
-				if (stopAsyncMessage)
-				{
-					/* shutting down */
-					return;
-				}
-			}
-			
-			while (listenForBreak)
-			{
-				try
-				{
-					if (waitSelect(selectorRead, true))
-					{
-						int t = read();
-						if (t == 0x03)
-						{
-							// We received a ctrl-c while processing a package,
-							// this
-							// would be a suspend
-							simulator.suspend();
-						} else
-						{
-							// ignore garbage. Shouldn't happen.
-						}
-					} else
-					{
-						// we've been awoken since we're ready to send 
-						// the reply to the package...
-//						int x=0;
-					}
-				} catch (IOException e)
-				{
-					// Perfectly normal. This would happen if the connection
-					// is terminated.
-				}
-			}
+			sc.close();
 		}
 	}
 
-	/** wait for read/write ready */
-	private boolean waitSelect(Selector selector, boolean read) throws IOException
-	{
-		boolean gotit=false;
-		
-		selector.select(1000);
-		if (!sc.isOpen())
-		{
-			throw new IOException("Channel closed");
-		}
-		if (!sc.isConnected())
-		{
-			throw new IOException("Channel not connected");
-		}
-
-		// Get list of selection keys with pending events
-		Iterator it = selector.selectedKeys().iterator();
-		// Process each key at a time
-		while (it.hasNext())
-		{
-			// Get the selection key
-			SelectionKey selKey = (SelectionKey) it.next();
-			// Remove it from the list to indicate that it is being
-			// processed
-			it.remove();
-			if (selKey.isValid() && 
-					((read && selKey.isReadable()) || (!read && selKey.isWritable())))
-			{
-				gotit=true;
-			}
-			
-		}
-		return gotit;
-	}
 
 	
 	protected void sleepABit()
@@ -243,44 +111,18 @@ public class GDBServer implements Host
 	{
 		print(MINIMAL, "GDB server waiting for connection " + sessionNr++ + "...");
 
-		writeBuffer.clear();
-		readBuffer.clear();
-
-
-        selectorRead = Selector.open();
         try
         {
-            selectorWrite = Selector.open();
-            try
-            {
-				sc = app.channel.accept();
-		        try
-		        {
-		        	sc.socket().setKeepAlive(true);
-		            sc.configureBlocking(false);
-		            sc.register(selectorRead, SelectionKey.OP_READ);
-		            sc.register(selectorWrite, SelectionKey.OP_WRITE);
-		
-		            sessionStarted();
-		
-		            expect('+'); // connection ack.
-		
-		            sessionLoop();
-		        } finally
-		        {
-		            sc.close();
-		            
-					print(MINIMAL, "Session ended");
-		        }
-            } finally
-            {
-                selectorWrite.close();
-            }
+            sessionStarted();
+
+            expect('+'); // connection ack.
+
+            sessionLoop();
         } finally
         {
-            selectorRead.close();
+			print(MINIMAL, "Session ended");
         }
-	
+            
 	}
 
 	private void sessionStarted()
@@ -301,19 +143,8 @@ public class GDBServer implements Host
 				packet=new Packet(this);
 				packet.receive();
 		
-				enterListenForCtrlC();
-                
-				try
-				{
-					// During execution we can receive an abort/suspend command...
-					packet.parseAndExecute();
-				} 
-				finally
-				{
-					leaveListenForCtrlC();
-				}
-                
-				packet.sendReply();
+				// During execution we can receive an abort/suspend command...
+				packet.parseAndExecute();
 				
 				if (!alive)
 				    throw new EndSessionException();
@@ -337,41 +168,6 @@ public class GDBServer implements Host
 		}
 	}
 
-    private void enterListenForCtrlC()
-    {
-        setBreakListen(true);
-    }
-
-    private void leaveListenForCtrlC()
-    {
-        /* we don't want to wait for the select to time out as that would make
-         * the protocol excruciatingly slow */
-        setBreakListen(false);
-        selectorRead.wakeup();
-        synchronized(listenBreak)
-        {
-        	try
-        	{
-        		while (!sleeping)
-        		{
-        			listenBreak.notify();
-        			listenBreak.wait();
-        		}
-        	} catch (InterruptedException e)
-        	{
-        		e.printStackTrace();
-        	}
-        }
-    }
-
-	private void setBreakListen(boolean state)
-	{
-		synchronized(listenBreak)
-		{
-			listenForBreak=state;
-			listenBreak.notify();
-		}
-	}
 
 	
 
@@ -387,19 +183,9 @@ public class GDBServer implements Host
 	int read() throws IOException
 	{
 		flush();
-		readBuffer.clear();
-		for (;;)
-		{
-			int n;
-			n = sc.read(readBuffer);
-			if (n == 1)
-			{
-				break;
-			}
-			while (!waitSelect(selectorRead, true));
-		}
-		readBuffer.flip();
-		int t = readBuffer.get(0);
+		int t=sc.getInputStream().read();
+		if (t==-1)
+			throw new IOException();
 		return t;
 	}
 
@@ -429,42 +215,12 @@ public class GDBServer implements Host
 
 	public void write(byte[] bytes) throws IOException
 	{
-		int i=0;
-		while (i<bytes.length)
-		{
-			int len;
-			
-			while ((len=Math.min(bytes.length-i, writeBuffer.capacity()-writeBuffer.position()))==0)
-			{
-				flush();
-			}
-			
-			writeBuffer.put(bytes, i, len);
-			
-			i+=len;
-		}
+		sc.getOutputStream().write(bytes);
 	}
 
 	void flush() throws IOException 
 	{
-		if (writeBuffer.position()>0)
-		{
-			writeBuffer.flip();
-			int len=writeBuffer.limit();
-	
-			int j=0;
-			while (j<len)
-			{
-				int t=sc.write(writeBuffer);
-				
-				if (t==0)
-				{
-					while (!waitSelect(selectorWrite, false));
-				}
-				j+=t;
-			}
-			writeBuffer.clear();
-		}		
+		sc.getOutputStream().flush();
 	}
 
     
@@ -544,14 +300,7 @@ public class GDBServer implements Host
     {
         if (!enterSyscall)
             return true;
-        leaveListenForCtrlC();
-        try
-        {
-            performSyscall();
-        } finally
-        {
-            enterListenForCtrlC();
-        }
+        performSyscall();
         return false;
     }
     
@@ -560,11 +309,17 @@ public class GDBServer implements Host
         return simulator.getArg(i+2);
     }
 
-
     public void writeUART(int val)
     {
         System.out.print((char)val);
         System.out.flush();
+        
+
+        Packet p=new Packet(this);
+        p.reply("O" + formatHex(val, "00"));
+        p.sendReply();
+        
+        
     }
     public int readUART() throws CPUException
     {
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
index 7925bd5..ad68947 100644
--- a/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/gdb/Packet.java
@@ -159,6 +159,8 @@ class Packet
 			e.printStackTrace();
 			reply("E01");
 		} 
+        
+		sendReply();
 	}
 
 	private void checkEmpty() throws GDBServerException
@@ -192,6 +194,7 @@ class Packet
 	}
 	/**
 	 * @throws GDBServerException
+	 * @throws IOException 
 	 * @throws MemoryAccessException
 	 * 
 	 */
@@ -342,7 +345,7 @@ class Packet
 	{
 		reply.append(string);
 	}
-	void sendReply() throws IOException, NoAckException
+	void sendReply()
 	{
 		// a bit easier to debug if we can see the entire string.
 		StringBuffer buffer = new StringBuffer();
@@ -365,12 +368,25 @@ class Packet
 		}
 		buffer.append(t);
 		this.server.print(GDBServer.REPLY, "Reply " + number + " : " + buffer.toString());
-		this.server.write(buffer.toString().getBytes());
+		try
+		{
+			this.server.write(buffer.toString().getBytes());
+		} catch (IOException e)
+		{
+			throw new RuntimeException(e);
+		}
 		
 		if (server.alive)
 		{
 			/* check for ack. */
-			int ack = (char)this.server.read();
+			int ack;
+			try
+			{
+				ack = (char)this.server.read();
+			} catch (IOException e)
+			{
+				throw new RuntimeException(e);
+			}
 			if (ack == '+')
 			{
 				return;
@@ -379,6 +395,7 @@ class Packet
 			
 			throw new NoAckException();
 		}
+		reply=new StringBuffer();
 	}
 	
 	private void querySignal()
-- 
cgit v1.1


From 78e84633f945692c966a933df42f06f0df988e44 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Fri, 22 Feb 2008 17:38:08 +0000
Subject: 	* reduced memory for Phi to 2mByte to avoid Java heap out of
 memory. 	  Why does Java have trouble allocating a meagre 32mByte long
 array? :-)

---
 zpu/sw/simulator/ChangeLog                              | 2 ++
 zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java       | 2 +-
 zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java | 2 +-
 3 files changed, 4 insertions(+), 2 deletions(-)

(limited to 'zpu/sw')

diff --git a/zpu/sw/simulator/ChangeLog b/zpu/sw/simulator/ChangeLog
index 18b0981..2f54967 100644
--- a/zpu/sw/simulator/ChangeLog
+++ b/zpu/sw/simulator/ChangeLog
@@ -1,4 +1,6 @@
 2008-02-22 Øyvind Harboe
+	* reduced memory for Phi to 2mByte to avoid Java heap out of memory.
+	  Why does Java have trouble allocating a meagre 32mByte long array? :-)
 	* Hooked up support for the simulator to the Zylin Embedded CDT
 2007-08-04 Øyvind Harboe
 	* First version after open sourcing ZPU
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
index 0e3e7a1..663e68f 100644
--- a/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Phi.java
@@ -114,7 +114,7 @@ public class Phi extends Simulator
 
     protected int getRAMSIZE()
     {
-        return 32*1024*1024;
+        return 2*1024*1024;
     }
 
 
diff --git a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
index 791e253..cf6cf41 100644
--- a/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
+++ b/zpu/sw/simulator/com/zylin/zpu/simulator/Simulator.java
@@ -1942,7 +1942,7 @@ public class Simulator implements ZPU, Machine, Sim
 
     protected int getRAMSIZE()
     {
-        return (16*1024*1024);
+        return (2*1024*1024);
     }
 
     protected int getStartStack()
-- 
cgit v1.1


From 28011391a8f5ed1cfd5b289ab3a016e4da69f772 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Mon, 5 May 2008 18:31:21 +0000
Subject: 	* added eCos HAL for ZPU 	  zpu/zpu/sw/ecos/repository

---
 .../current/cdl/phi_opencores_ethmac_drivers.cdl   | 127 +++++++
 .../current/include/devs_eth_zpu_opencores_phi.inl |  92 ++++++
 .../zpu/opencores/phi/current/src/if_opencores.c   | 112 +++++++
 .../repository/hal/zylin/arch/current/ChangeLog    |  39 +++
 .../hal/zylin/arch/current/cdl/hal_zylin.cdl       | 108 ++++++
 .../hal/zylin/arch/current/include/arch.inc        |  79 +++++
 .../hal/zylin/arch/current/include/basetype.h      |  83 +++++
 .../hal/zylin/arch/current/include/hal_arch.h      | 255 ++++++++++++++
 .../hal/zylin/arch/current/include/hal_intr.h      | 261 +++++++++++++++
 .../hal/zylin/arch/current/include/hal_io.h        | 305 +++++++++++++++++
 .../hal/zylin/arch/current/src/context.S           | 324 ++++++++++++++++++
 .../hal/zylin/arch/current/src/hal_misc.c          | 177 ++++++++++
 .../hal/zylin/arch/current/src/hal_mk_defs.c       | 102 ++++++
 .../hal/zylin/arch/current/src/vectors.c           | 116 +++++++
 .../repository/hal/zylin/arch/current/src/zylin.ld | 226 +++++++++++++
 .../hal/zylin/zpu/abel/current/ChangeLog           |  39 +++
 .../zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl    | 298 +++++++++++++++++
 .../zpu/abel/current/include/hal_platform_ints.h   |  79 +++++
 .../include/pkgconf/mlt_zylin_zpu_abel_ram.h       |  17 +
 .../include/pkgconf/mlt_zylin_zpu_abel_ram.ldi     |  27 ++
 .../hal/zylin/zpu/abel/current/include/plf_io.h    |  64 ++++
 .../zylin/zpu/abel/current/misc/redboot_RAM.ecm    |  53 +++
 .../hal/zylin/zpu/abel/current/src/abel_misc.c     |  61 ++++
 .../repository/hal/zylin/zpu/phi/current/ChangeLog |  39 +++
 .../zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl      | 292 ++++++++++++++++
 .../zpu/phi/current/include/hal_platform_ints.h    |  81 +++++
 .../include/pkgconf/mlt_zylin_zpu_phi_ram.h        |  17 +
 .../include/pkgconf/mlt_zylin_zpu_phi_ram.ldi      |  27 ++
 .../hal/zylin/zpu/phi/current/include/plf_io.h     |  58 ++++
 .../hal/zylin/zpu/phi/current/src/phi_misc.c       |  72 ++++
 .../repository/hal/zylin/zpu/var/current/ChangeLog |  38 +++
 .../zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl    |  83 +++++
 .../hal/zylin/zpu/var/current/include/hal_cache.h  | 192 +++++++++++
 .../hal/zylin/zpu/var/current/include/hal_diag.h   |  90 +++++
 .../hal/zylin/zpu/var/current/include/plf_stub.h   |  85 +++++
 .../hal/zylin/zpu/var/current/include/var_arch.h   |  73 ++++
 .../hal/zylin/zpu/var/current/include/var_io.h     |  73 ++++
 .../hal/zylin/zpu/var/current/src/hal_diag.c       |  88 +++++
 .../hal/zylin/zpu/var/current/src/zpu_misc.c       | 252 ++++++++++++++
 .../hal/zylin/zpu/zeta/current/ChangeLog           |  39 +++
 .../zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl    | 298 +++++++++++++++++
 .../zpu/zeta/current/include/hal_platform_ints.h   |  79 +++++
 .../include/pkgconf/mlt_zylin_zpu_zeta_ram.h       |  17 +
 .../include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi     |  27 ++
 .../hal/zylin/zpu/zeta/current/include/plf_io.h    |  58 ++++
 .../zylin/zpu/zeta/current/misc/redboot_RAM.ecm    |  53 +++
 .../hal/zylin/zpu/zeta/current/src/zeta_misc.c     |  64 ++++
 .../repository/net/zylin/current/cdl/phi_net.cdl   |  56 ++++
 .../net/zylin/current/src/phi_network_support.c    | 368 +++++++++++++++++++++
 zpu/sw/ecos/repository/pkgconf/rules.mak           | 210 ++++++++++++
 50 files changed, 5873 insertions(+)
 create mode 100644 zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl
 create mode 100644 zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl
 create mode 100644 zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_mk_defs.c
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm
 create mode 100644 zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c
 create mode 100644 zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl
 create mode 100644 zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c
 create mode 100644 zpu/sw/ecos/repository/pkgconf/rules.mak

(limited to 'zpu/sw')

diff --git a/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl
new file mode 100644
index 0000000..580890d
--- /dev/null
+++ b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/cdl/phi_opencores_ethmac_drivers.cdl
@@ -0,0 +1,127 @@
+# ====================================================================
+#
+#      phi_opencores_ethmac_drivers.cdl
+#
+#      Ethernet drivers - support for Opencores ethermac controller
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Gaisler Research, (Konrad Eisele<eiselekd@web.de>)
+# Contributors:	  Zylin AS, (Edgar Grimberg<edgar.grimberg@zylin.com>)
+# Date:           2005-01-20
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI {
+
+    display       "PHI opencores ethernet driver"
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_IO_ETH_DRIVERS
+    active_if	  CYGPKG_HAL_ZYLIN_ZPU_PHI
+    
+    requires      CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC
+    description   "Ethernet driver for ethermac in on a Zylin Phi Board."
+
+    include_dir   cyg/io
+    compile       -library=libextras.a if_opencores.c
+
+    define_proc {
+        puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_INL <cyg/io/devs_eth_zpu_opencores_phi.inl>"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_OPENCORES_ETHERMAC_CFG <pkgconf/devs_eth_zpu_opencores_phi.h>"
+        puts $::cdl_system_header "/*****  ethernet driver proc output end  *****/"
+    }
+    
+    # Arguably this should do in the generic package
+    # but then there is a logic loop so you can never enable it.
+
+    cdl_interface CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED {
+        display   "opencores ethermac driver required"
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0 {
+        display       "Ethernet port 0 driver"
+        flavor        bool
+        default_value 1
+
+        implements    CYGHWR_NET_DRIVERS
+        implements    CYGHWR_NET_DRIVER_ETH0
+        implements    CYGINT_DEVS_ETH_OPENCORES_ETHERMAC_REQUIRED
+    
+        cdl_option CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_NAME {
+            display       "Device name for the ethernet driver"
+            flavor        data
+            default_value {"\"eth0\""}
+            description   "
+                          This option sets the name of the ethernet device for the
+                          ethernet port."
+       }
+    
+        cdl_option CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_ESA {
+            display       "The ethernet station address (MAC)"
+            flavor        data
+            default_value {"{0x00, 0x00, 0x5E, 0x21, 0x00, 0x01}"}
+            description   "A static ethernet station address. 
+                          Caution: Booting two systems with the same MAC on the same
+                          network, will cause severe conflicts."
+       }
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_OPTIONS {
+        display "Opencores ethermac driver build options"
+        flavor  none
+	no_define
+
+        cdl_option CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "-D_KERNEL -D__ECOS" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the opencores ethermac driver package.
+                These flags are used in addition
+                to the set of global flags."
+        }
+    }
+
+}
+
+# EOF phi_opencores_ethmac_drivers.cdl
diff --git a/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl
new file mode 100644
index 0000000..7cfa114
--- /dev/null
+++ b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/include/devs_eth_zpu_opencores_phi.inl
@@ -0,0 +1,92 @@
+//==========================================================================
+//
+//      
+//
+//      Opencores ethermac I/O definitions.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Gaisler Research, (Konrad Eisele<eiselekd@web.de>)
+// Contributors:   
+// Date:           2000-11-22
+//####DESCRIPTIONEND####
+//==========================================================================
+
+#include <pkgconf/system.h>
+#include <cyg/hal/hal_intr.h>          
+
+#define CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_ETH0_ESA CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_ESA
+#define CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_INITFN openeth_phi_init
+
+#ifdef CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0
+
+//structs and tables for eth0
+static oeth_info openeth_priv;
+ETH_DRV_SC(oeth_sc,
+           &openeth_priv,          // Driver specific data
+		   CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_NAME, // Name for device
+           openeth_start,
+           openeth_stop,
+           openeth_ioctl,
+           openeth_can_send,
+           openeth_send,
+           openeth_recv,
+           openeth_deliver,
+           openeth_poll,
+           openeth_int_vector
+);
+
+NETDEVTAB_ENTRY(oeth_netdev, 
+                "openeth_" CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0_NAME,
+                openeth_init,
+                &oeth_sc);
+#endif
+
+#if CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT > 1
+#error Only 1 ethermac at a time supported yet (eth0) 
+#endif
+
+oeth_info *openeth_priv_array[CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT] = {
+#ifdef CYGPKG_DEVS_ETH_ZPU_OPENCORES_PHI_ETH0
+          &openeth_priv
+#endif          
+};
+
+       
+//EOF devs_eth_zpu_opencorec_phi.inl
+
+
diff --git a/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c
new file mode 100644
index 0000000..c18caca
--- /dev/null
+++ b/zpu/sw/ecos/repository/dev/eth/zpu/opencores/phi/current/src/if_opencores.c
@@ -0,0 +1,112 @@
+//==========================================================================
+//
+//     
+//
+//      Ethernet device driver for Opencore's ethermac on Zylin Phi
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//####BSDCOPYRIGHTBEGIN####
+//
+// -------------------------------------------
+//
+// Portions of this software may have been derived from OpenBSD or other sources,
+// and are covered by the appropriate copyright disclaimers included herein.
+//
+// -------------------------------------------
+//
+//####BSDCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      Gaisler Research, (Konrad Eisele<eiselekd@web.de>)
+// Contributors: 
+// Date:         2005-01-20
+// Purpose:      
+// Description:  hardware driver for Opencores ethernet
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/system.h>
+#ifdef CYGPKG_IO_ETH_DRIVERS
+#include <pkgconf/io_eth_drivers.h>
+#endif
+#include <pkgconf/devs_eth_opencores_ethermac.h>
+
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/infra/cyg_ass.h>
+#include <cyg/infra/diag.h>
+#include <cyg/hal/drv_api.h>
+#include <cyg/io/eth/netdev.h>
+#include <cyg/io/eth/eth_drv.h>
+
+#ifdef CYGPKG_NET
+#include <pkgconf/net.h>
+#include <cyg/kernel/kapi.h>
+#include <net/if.h>  /* Needed for struct ifnet */
+#endif
+
+#include <cyg/hal/hal_arch.h>
+#include <cyg/hal/hal_intr.h>
+//#include <cyg/hal/hal_leon3.h>
+
+externC void openeth_device_init(struct eth_drv_sc *sc, cyg_uint32 idx, cyg_uint32 base, cyg_uint32 irq);
+ 
+bool openeth_phi_init(struct cyg_netdevtab_entry *ndp)
+{
+  struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance);
+
+#if !defined(CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH)
+#error "CYGPKG_DEVS_ETH_OPENCORES_ETHERMAC_FLUSH must be 1 for Zylin Phi"
+#endif
+
+#if 0  
+  int  i,j;
+  amba_ahb_device adev[CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT];
+  j = amba_get_free_ahbslv_devices (VENDOR_GAISLER, GAISLER_ETHAHB, adev, CYGNUM_DEVS_ETH_OPENCORES_ETHERMAC_DEV_COUNT);
+  for (i = 0;i < j;i++) {
+    openeth_device_init(sc,i,adev[i].start[0],adev[i].irq);
+  }
+#endif
+	openeth_device_init(sc, 0, 0x080C0000, CYGNUM_HAL_INTERRUPT_ETHERMAC);
+	return 1;
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog
new file mode 100644
index 0000000..6403c63
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/ChangeLog
@@ -0,0 +1,39 @@
+2004-11-05  Øyvind Harboe <oyvind.harboe@zylin.com>
+
+	* First cut of ZYLIN support
+	
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl b/zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl
new file mode 100644
index 0000000..cecc879
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/cdl/hal_zylin.cdl
@@ -0,0 +1,108 @@
+# ====================================================================
+#
+#      hal_zylin.cdl
+#
+#      ZYLIN architectural HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      bartv
+# Original data:  gthomas
+# Contributors:
+# Date:           1999-06-13
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ZYLIN {
+    display       "ZYLIN architecture"
+    parent        CYGPKG_HAL
+    hardware
+    include_dir   cyg/hal
+    requires      !CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
+    define_header hal_zylin.h
+    description   "
+        The ZYLIN architecture HAL package provides generic
+        support for this processor architecture. It is also
+        necessary to select a specific target platform HAL
+        package."
+
+    compile       hal_misc.c context.S  vectors.c 
+
+    # The "-o file" is a workaround for CR100958 - without it the
+    # output file would end up in the source directory under CygWin.
+    # n.b. grep does not behave itself under win32
+    make -priority 1 {
+        zylin.inc : <PACKAGE>/src/hal_mk_defs.c
+        $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,zylin.tmp -o hal_mk_defs.tmp -S $<
+        fgrep .equ hal_mk_defs.tmp | sed s/#// > $@
+        @echo $@ ": \\" > $(notdir $@).deps
+        @tail -n +2 zylin.tmp >> $(notdir $@).deps
+        @echo >> $(notdir $@).deps
+        @rm zylin.tmp hal_mk_defs.tmp
+    }
+
+    make {
+        <PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.c
+        $(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<
+        @echo $@ ": \\" > $(notdir $@).deps
+        @tail -n +2 vectors.tmp >> $(notdir $@).deps
+        @echo >> $(notdir $@).deps
+        @rm vectors.tmp
+    }
+
+
+    make {
+        <PREFIX>/lib/target.ld: <PACKAGE>/src/zylin.ld
+        $(CC) -E -P -Wp,-MD,target.tmp -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
+        @echo $@ ": \\" > $(notdir $@).deps
+        @tail -n +2 target.tmp >> $(notdir $@).deps
+        @echo >> $(notdir $@).deps
+        @rm target.tmp
+    }
+
+
+    cdl_option CYGBLD_LINKER_SCRIPT {
+        display "Linker script"
+        flavor data
+	no_define
+        calculated  { "src/zylin.ld" }
+    }
+
+}
+
+# EOF hal_zylin.cdl
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc
new file mode 100644
index 0000000..a30819e
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/arch.inc
@@ -0,0 +1,79 @@
+##=============================================================================
+##
+##	arch.inc
+##
+##	ZYLIN architecture assembler header file
+##
+##=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+##=============================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s): 	jskov
+## Contributors:jskov
+## Date:	2000-11-15
+## Purpose:	ZYLIN definitions.
+## Description:	This file contains various definitions and macros that are
+##              useful for writing assembly code for the ZYLIN
+##              It also includes the variant/platform assembly header file.
+## Usage:
+##		#include <cyg/hal/arch.inc>
+##		...
+##		
+##
+######DESCRIPTIONEND####
+##
+##=============================================================================
+
+#include <cyg/hal/basetype.h>
+
+##-----------------------------------------------------------------------------
+## ZYLIN entry definitions. This allows _ prefixing to change by modifying
+## the CYG_LABEL_DEFN macro.
+
+#define FUNC_START(name)        \
+        .type CYG_LABEL_DEFN(name),@function;   \
+        .globl CYG_LABEL_DEFN(name);            \
+CYG_LABEL_DEFN(name):
+
+#define FUNC_END(name)  \
+        .globl CYG_LABEL_DEFN(name);            \
+CYG_LABEL_DEFN(name):
+        
+#define SYM_DEF(name)   \
+        .globl CYG_LABEL_DEFN(name);            \
+CYG_LABEL_DEFN(name):
+	
+#------------------------------------------------------------------------------
+# end of arch.inc
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h
new file mode 100644
index 0000000..6f2c2c7
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/basetype.h
@@ -0,0 +1,83 @@
+#ifndef CYGONCE_HAL_BASETYPE_H
+#define CYGONCE_HAL_BASETYPE_H
+
+//=============================================================================
+//
+//      basetype.h
+//
+//      Standard types for this architecture.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, gthomas
+// Contributors:  nickg, gthomas
+// Date:        1998-09-11
+// Purpose:     Define architecture base types.
+// Usage:       Included by "cyg_type.h", do not use directly
+
+//              
+//####DESCRIPTIONEND####
+//
+
+//-----------------------------------------------------------------------------
+// Characterize the architecture
+
+#define CYG_BYTEORDER           CYG_MSBFIRST    // Big endian
+#define CYG_DOUBLE_BYTEORDER    CYG_MSBFIRST    // Big? endian
+
+//-----------------------------------------------------------------------------
+// ZYLIN does not usually use labels with underscores.
+
+#define CYG_LABEL_NAME(_name_) _name_
+#define CYG_LABEL_DEFN(_name_) _name_
+
+//-----------------------------------------------------------------------------
+// Override the alignment definitions from cyg_type.h. ZYLIN only allows 4 
+// byte alignment whereas the default is 8 byte.
+
+#define CYGARC_ALIGNMENT 4
+#define CYGARC_P2ALIGNMENT 2
+
+//-----------------------------------------------------------------------------
+// Define the standard variable sizes
+
+// The ZYLIN architecture uses the default definitions of the base types,
+// so we do not need to define any here.
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BASETYPE_H
+// End of basetype.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h
new file mode 100644
index 0000000..cd61277
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_arch.h
@@ -0,0 +1,255 @@
+#ifndef CYGONCE_HAL_ARCH_H
+#define CYGONCE_HAL_ARCH_H
+
+//==========================================================================
+//
+//      hal_arch.h
+//
+//      Architecture specific abstractions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, gthomas
+// Contributors: nickg, gthomas
+// Date:         1999-02-20
+// Purpose:      Define architecture abstractions
+// Usage:        #include <cyg/hal/hal_arch.h>
+
+//              
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>         // To decide on stack usage
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/plf_io.h>
+#ifdef CYGBLD_HAL_ZYLIN_PLF_ARCH_H
+#include <cyg/hal/plf_arch.h>
+#endif
+
+#ifdef CYGBLD_HAL_ZYLIN_VAR_ARCH_H
+#include <cyg/hal/var_arch.h>
+#endif
+
+
+// It seems that r0-r3,r12 are considered scratch by function calls
+
+typedef struct 
+{
+    cyg_uint32 reg[8];
+    cyg_uint32  interrupt;
+    cyg_uint32  pc;	// must be last...
+} HAL_SavedRegisters;
+
+//-------------------------------------------------------------------------
+// Exception handling function.
+// This function is defined by the kernel according to this prototype. It is
+// invoked from the HAL to deal with any CPU exceptions that the HAL does
+// not want to deal with itself. It usually invokes the kernel's exception
+// delivery mechanism.
+
+externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
+
+//-------------------------------------------------------------------------
+// Bit manipulation macros
+
+externC int hal_lsbindex(int);
+externC int hal_msbindex(int);
+
+#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbindex(mask)
+#define HAL_MSBIT_INDEX(index, mask) index = hal_msbindex(mask)
+
+//-------------------------------------------------------------------------
+// Context Initialization
+// Initialize the context of a thread.
+// Arguments:
+// _sparg_ name of variable containing current sp, will be changed to new sp
+// _thread_ thread object address, passed as argument to entry point
+// _entry_ entry point address.
+// _id_ bit pattern used in initializing registers, for debugging.
+
+#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
+    CYG_MACRO_START                                                         \
+    cyg_uint32 *_sp_=(cyg_uint32 *)(((CYG_WORD)_sparg_) &~3); 				\
+    *--_sp_=(CYG_ADDRWORD)_thread_;											\
+    *--_sp_=(CYG_ADDRWORD)0xffffffff; /* dummy return address */				\
+    *--_sp_=(cyg_uint32)(_entry_);     /* PC = [initial] entry point */ \
+    *--_sp_= 0; /* interrupt mask */  \
+    *--_sp_= (_id_)|7;      \
+    *--_sp_= (_id_)|6;      \
+    *--_sp_= (_id_)|5;      \
+    *--_sp_= (_id_)|4;      \
+    *--_sp_= (_id_)|3;      \
+    *--_sp_= (_id_)|2;      \
+    *--_sp_= (_id_)|1;      \
+    *--_sp_=(_id_)|0;      \
+    _sparg_ = (CYG_ADDRWORD)_sp_;                                          \
+    CYG_MACRO_END
+
+//--------------------------------------------------------------------------
+// Context switch macros.
+// The arguments are pointers to locations where the stack pointer
+// of the current thread is to be stored, and from where the sp of the
+// next thread is to be fetched.
+
+externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
+externC void hal_thread_load_context( CYG_ADDRESS to )
+    __attribute__ ((noreturn));
+
+#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_)                    \
+        hal_thread_switch_context((CYG_ADDRESS)_tspptr_,                \
+                                  (CYG_ADDRESS)_fspptr_);
+
+#define HAL_THREAD_LOAD_CONTEXT(_tspptr_)                               \
+        hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
+
+//--------------------------------------------------------------------------
+// Execution reorder barrier.
+// When optimizing the compiler can reorder code. In multithreaded systems
+// where the order of actions is vital, this can sometimes cause problems.
+// This macro may be inserted into places where reordering should not happen.
+
+#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
+
+//--------------------------------------------------------------------------
+// Breakpoint support
+// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
+// if executed.
+// HAL_BREAKINST is the value of the breakpoint instruction and 
+// HAL_BREAKINST_SIZE is its size in bytes.
+
+#define _stringify1(__arg) #__arg
+#define _stringify(__arg) _stringify1(__arg)
+
+#define HAL_BREAKINST_ZYLIN          0
+#define HAL_BREAKINST_ZYLIN_SIZE     1
+
+
+#define HAL_BREAKPOINT(_label_)                   \
+asm volatile (" .globl  " #_label_ ";"            \
+              #_label_":"                         \
+              " .byte " _stringify(HAL_BREAKINST_ZYLIN) \
+    );
+
+//#define HAL_BREAKINST           {0xFE, 0xDE, 0xFF, 0xE7}
+#define HAL_BREAKINST            HAL_BREAKINST_ZYLIN
+#define HAL_BREAKINST_SIZE       HAL_BREAKINST_ZYLIN_SIZE
+#define HAL_BREAKINST_TYPE       cyg_uint8
+
+extern cyg_uint32 __zylin_breakinst;
+#define HAL_BREAKINST_ADDR(x) (void*)&__zylin_breakinst)
+
+
+// Translate a stack pointer as saved by the thread context macros above into
+// a pointer to a HAL_SavedRegisters structure.
+#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ )  \
+        (_regs_) = (HAL_SavedRegisters *)(_sp_)
+
+
+
+//--------------------------------------------------------------------------
+// HAL setjmp
+
+#define CYGARC_JMP_BUF_SIZE 16  // Actually 11, but some room left over
+
+typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
+
+externC int hal_setjmp(hal_jmp_buf env);
+externC void hal_longjmp(hal_jmp_buf env, int val);
+
+
+//--------------------------------------------------------------------------
+// Idle thread code.
+// This macro is called in the idle thread loop, and gives the HAL the
+// chance to insert code. Typical idle thread behaviour might be to halt the
+// processor. Here we only supply a default fallback if the variant/platform
+// doesn't define anything.
+
+#ifndef HAL_IDLE_THREAD_ACTION
+#define HAL_IDLE_THREAD_ACTION(_count_) CYG_EMPTY_STATEMENT
+#endif
+
+//---------------------------------------------------------------------------
+
+// Minimal and sensible stack sizes: the intention is that applications
+// will use these to provide a stack size in the first instance prior to
+// proper analysis.  Idle thread stack should be this big.
+
+//    THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
+//           THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
+// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
+
+// This is not a config option because it should not be adjusted except
+// under "enough rope" sort of disclaimers.
+
+// A minimal, optimized stack frame, rounded up - no autos
+#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 80)
+
+// Stack needed for a context switch: this is implicit in the estimate for
+// interrupts so not explicitly used below:
+#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 80)
+
+// Interrupt + call to ISR, interrupt_end() and the DSR
+#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
+    ((4 * 80) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+
+// Space for the maximum number of nested interrupts, plus room to call functions
+#define CYGNUM_HAL_MAX_INTERRUPT_NESTING 16
+
+#if 0
+#define CYGNUM_HAL_STACK_SIZE_MINIMUM 
+        (CYGNUM_HAL_MAX_INTERRUPT_NESTING * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \
+         2 * CYGNUM_HAL_STACK_FRAME_SIZE)
+
+#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
+        (CYGNUM_HAL_STACK_SIZE_MINIMUM + \
+         16 * CYGNUM_HAL_STACK_FRAME_SIZE)
+#else
+#define CYGNUM_HAL_STACK_SIZE_MINIMUM 16384 // KLUDGE!!! until interrupt stacks can be added
+
+#define CYGNUM_HAL_STACK_SIZE_TYPICAL 32768 // KLUDGE!!! until interrupt stacks can be added
+
+#endif
+
+//--------------------------------------------------------------------------
+// Macros for switching context between two eCos instances (jump from
+// code in ROM to code in RAM or vice versa).
+#define CYGARC_HAL_SAVE_GP()
+#define CYGARC_HAL_RESTORE_GP()
+
+#endif // CYGONCE_HAL_ARCH_H
+// End of hal_arch.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h
new file mode 100644
index 0000000..6ec6070
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_intr.h
@@ -0,0 +1,261 @@
+#ifndef CYGONCE_HAL_INTR_H
+#define CYGONCE_HAL_INTR_H
+
+//==========================================================================
+//
+//      hal_intr.h
+//
+//      HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, gthomas
+// Contributors: nickg, gthomas,
+//               jlzylinour
+// Date:         1999-02-20
+// Purpose:      Define Interrupt support
+// Description:  The macros defined here provide the HAL APIs for handling
+//               interrupts and the clock.
+//              
+// Usage:        #include <cyg/hal/hal_intr.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+// This is to allow a variant to decide that there is no platform-specific
+// interrupts file; and that in turn can be overridden by a platform that
+// refines the variant's ideas.
+#ifdef    CYGBLD_HAL_PLF_INTS_H
+# include CYGBLD_HAL_PLF_INTS_H // should include variant data as required
+#else 
+# ifdef    CYGBLD_HAL_VAR_INTS_H
+#  include CYGBLD_HAL_VAR_INTS_H
+# else
+#  include <cyg/hal/hal_platform_ints.h> // default less-complex platforms
+# endif
+#endif
+
+// Spurious interrupt (no interrupt source could be found)
+#define CYGNUM_HAL_INTERRUPT_NONE -1
+
+//--------------------------------------------------------------------------
+// ZYLIN exception vectors.
+
+// These vectors correspond to VSRs. These values are the ones to use for
+// HAL_VSR_GET/SET
+
+#define CYGNUM_HAL_VECTOR_RESET                0
+#define CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION    1
+#define CYGNUM_HAL_VECTOR_MISC				   2
+#define CYGNUM_HAL_VECTOR_IRQ                  3
+#define CYGNUM_HAL_VECTOR_MEMORY               4
+
+#define CYGNUM_HAL_VSR_MIN                     0
+#define CYGNUM_HAL_VSR_MAX                     4
+#define CYGNUM_HAL_VSR_COUNT                   5
+
+// Exception vectors. These are the values used when passed out to an
+// external exception handler using cyg_hal_deliver_exception()
+
+#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
+          CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION
+#define CYGNUM_HAL_EXCEPTION_INTERRUPT \
+          CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT
+#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS    CYGNUM_HAL_VECTOR_MEMORY
+#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS    CYGNUM_HAL_VECTOR_MEMORY
+
+#define CYGNUM_HAL_EXCEPTION_MIN     CYGNUM_HAL_VSR_MIN 
+#define CYGNUM_HAL_EXCEPTION_MAX     CYGNUM_HAL_VSR_MAX
+#define CYGNUM_HAL_EXCEPTION_COUNT   (CYGNUM_HAL_EXCEPTION_MAX - \
+                                      CYGNUM_HAL_EXCEPTION_MIN + 1)
+
+//--------------------------------------------------------------------------
+// Static data used by HAL
+
+// ISR tables
+
+externC CYG_ADDRESS   hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
+externC CYG_ADDRWORD   hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
+externC CYG_ADDRESS    hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
+
+// VSR table
+externC CYG_ADDRESS    hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
+
+//--------------------------------------------------------------------------
+// Default ISR
+// The #define is used to test whether this routine exists, and to allow
+// code outside the HAL to call it.
+ 
+externC cyg_uint32 hal_default_isr(cyg_uint32  vector, CYG_ADDRWORD data);
+
+#define HAL_DEFAULT_ISR hal_default_isr
+
+//--------------------------------------------------------------------------
+// Interrupt state storage
+
+typedef cyg_uint32 CYG_INTERRUPT_STATE;
+
+//--------------------------------------------------------------------------
+// Interrupt control macros
+
+externC cyg_uint32 zpu_disable_interrupts();
+externC void zpu_enable_interrupts();
+externC void zpu_restore_interrupts(cyg_uint32);
+externC cyg_uint32 zpu_query_interrupts();
+
+#define HAL_DISABLE_INTERRUPTS(_old_) {_old_=zpu_disable_interrupts();}
+#define HAL_ENABLE_INTERRUPTS() zpu_enable_interrupts()
+#define HAL_RESTORE_INTERRUPTS(_old_) { zpu_restore_interrupts(_old_); }
+#define HAL_QUERY_INTERRUPTS(_old_) { _old_=zpu_query_interrupts(); }     
+
+
+//--------------------------------------------------------------------------
+// Vector translation.
+
+#ifndef HAL_TRANSLATE_VECTOR
+#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
+    (_index_) = (_vector_)
+#endif
+
+//--------------------------------------------------------------------------
+// Interrupt and VSR attachment macros
+
+#define HAL_INTERRUPT_IN_USE( _vector_, _state_)                          \
+    CYG_MACRO_START                                                       \
+    cyg_uint32 _index_;                                                   \
+    HAL_TRANSLATE_VECTOR ((_vector_), _index_);                           \
+                                                                          \
+    if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
+        (_state_) = 0;                                                    \
+    else                                                                  \
+        (_state_) = 1;                                                    \
+    CYG_MACRO_END
+
+#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ )          \
+    CYG_MACRO_START                                                        \
+    if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \
+    {                                                                      \
+        hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_;             \
+        hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_;              \
+        hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_;           \
+    }                                                                      \
+    CYG_MACRO_END
+
+#define HAL_INTERRUPT_DETACH( _vector_, _isr_ )                            \
+    CYG_MACRO_START                                                        \
+    if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ )           \
+    {                                                                      \
+        hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr;   \
+        hal_interrupt_data[_vector_] = 0;                                  \
+        hal_interrupt_objects[_vector_] = 0;                               \
+    }                                                                      \
+    CYG_MACRO_END
+
+#define HAL_VSR_GET( _vector_, _pvsr_ )                         \
+    *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
+    
+
+#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ )               \
+    CYG_MACRO_START                                             \
+    if( _poldvsr_ != NULL )                                     \
+        *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_];    \
+    hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;               \
+    CYG_MACRO_END
+
+//--------------------------------------------------------------------------
+// Interrupt controller access
+
+externC void hal_interrupt_mask(int);
+externC void hal_interrupt_unmask(int);
+externC void hal_interrupt_acknowledge(int);
+externC void hal_interrupt_configure(int, int, int);
+externC void hal_interrupt_set_level(int, int);
+
+#define HAL_INTERRUPT_MASK( _vector_ )                     \
+    hal_interrupt_mask( _vector_ ) 
+#define HAL_INTERRUPT_UNMASK( _vector_ )                   \
+    hal_interrupt_unmask( _vector_ )
+#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )              \
+    hal_interrupt_acknowledge( _vector_ )
+#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
+    hal_interrupt_configure( _vector_, _level_, _up_ )
+#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )       \
+    hal_interrupt_set_level( _vector_, _level_ )
+
+//--------------------------------------------------------------------------
+// Clock control
+
+externC void hal_clock_initialize(cyg_uint32);
+externC void hal_clock_read(cyg_uint32 *);
+externC void hal_clock_reset(cyg_uint32, cyg_uint32);
+
+#define HAL_CLOCK_INITIALIZE( _period_ )   hal_clock_initialize( _period_ )
+#define HAL_CLOCK_RESET( _vec_, _period_ ) hal_clock_reset( _vec_, _period_ )
+#define HAL_CLOCK_READ( _pvalue_ )         hal_clock_read( _pvalue_ )
+#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
+# ifndef HAL_CLOCK_LATENCY
+#  define HAL_CLOCK_LATENCY( _pvalue_ )    HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
+# endif
+#endif
+
+
+#ifdef  CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+externC void hal_interrupt_stack_call_pending_DSRs(void);
+#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
+    hal_interrupt_stack_call_pending_DSRs() 
+
+// these are offered solely for stack usage testing
+// if they are not defined, then there is no interrupt stack.
+#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
+#define HAL_INTERRUPT_STACK_TOP  cyg_interrupt_stack
+// use them to declare these extern however you want:
+//       extern char HAL_INTERRUPT_STACK_BASE[];
+//       extern char HAL_INTERRUPT_STACK_TOP[];
+// is recommended
+#endif
+
+
+//--------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_INTR_H
+// End of hal_intr.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h
new file mode 100644
index 0000000..64ad695
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/include/hal_io.h
@@ -0,0 +1,305 @@
+#ifndef CYGONCE_HAL_IO_H
+#define CYGONCE_HAL_IO_H
+
+//=============================================================================
+//
+//      hal_io.h
+//
+//      HAL device IO register support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, gthomas
+// Contributors: Fabrice Gautier
+// Date:         1998-09-11
+// Purpose:      Define IO register support
+// Description:  The macros defined here provide the HAL APIs for handling
+//               device IO control registers.
+//              
+// Usage:
+//               #include <cyg/hal/hal_io.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/system.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/basetype.h>
+
+//-----------------------------------------------------------------------------
+// Include plf_io.h for platforms. Either via var_io.h or directly.
+#ifdef CYGBLD_HAL_ZYLIN_VAR_IO_H
+#include <cyg/hal/var_io.h>
+#else
+#include <cyg/hal/plf_io.h>
+#endif
+
+
+//-----------------------------------------------------------------------------
+// IO Register address.
+// This type is for recording the address of an IO register.
+
+typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
+
+//-----------------------------------------------------------------------------
+// HAL IO macros.
+#ifndef HAL_IO_MACROS_DEFINED
+
+//-----------------------------------------------------------------------------
+// BYTE Register access.
+// Individual and vectorized access to 8 bit registers.
+
+// Little-endian version or big-endian version that doesn't need address munging
+#if (CYG_BYTEORDER == CYG_LSBFIRST) || defined(HAL_IO_MACROS_NO_ADDRESS_MUNGING)
+
+#define HAL_READ_UINT8( _register_, _value_ ) \
+        ((_value_) = *((volatile CYG_BYTE *)(_register_)))
+
+#define HAL_WRITE_UINT8( _register_, _value_ ) \
+        (*((volatile CYG_BYTE *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_];        \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_];        \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ )             \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_i_];        \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ )            \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        ((volatile CYG_BYTE *)(_register_)) = (_buf_)[_i_];             \
+    CYG_MACRO_END
+
+#else // Big-endian version
+
+#define HAL_READ_UINT8( _register_, _value_ ) \
+        ((_value_) = *((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)))
+
+#define HAL_WRITE_UINT8( _register_, _value_ ) \
+        (*((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
+
+#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3);            \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        (_buf_)[_i_] = _r_[_j_];                                        \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3);            \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        _r_[_j_] = (_buf_)[_i_];                                        \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT8_STRING( _register_, _buf_, _count_ )             \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3);            \
+    for( _i_ = 0; _i_ < (_count_); _i_++;                               \
+        (_buf_)[_i_] = _r_[_i_];                                        \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT8_STRING( _register_, _buf_, _count_ )            \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3);            \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        _r_[_i_] = (_buf_)[_i_];                                        \
+    CYG_MACRO_END
+
+#endif // Big-endian
+
+//-----------------------------------------------------------------------------
+// 16 bit access.
+// Individual and vectorized access to 16 bit registers.
+    
+// Little-endian version or big-endian version that doesn't need address munging
+#if (CYG_BYTEORDER == CYG_LSBFIRST) || defined(HAL_IO_MACROS_NO_ADDRESS_MUNGING)
+
+#define HAL_READ_UINT16( _register_, _value_ ) \
+        ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
+
+#define HAL_WRITE_UINT16( _register_, _value_ ) \
+        (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_];      \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_];      \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_)             \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_i_];      \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_)            \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        ((volatile CYG_WORD16 *)(_register_))[_i_] = (_buf_)[_i_];      \
+    CYG_MACRO_END
+
+
+#else // Big-endian version
+
+#define HAL_READ_UINT16( _register_, _value_ ) \
+        ((_value_) = *((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)))
+
+#define HAL_WRITE_UINT16( _register_, _value_ ) \
+        (*((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
+
+#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3);          \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        (_buf_)[_i_] = _r_[_j_];                                        \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3);          \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        _r_[_j_] = (_buf_)[_i_];                                        \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT16_STRING( _register_, _buf_, _count_)             \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3);          \
+    for( _i_ = 0 = 0; _i_ < (_count_); _i_++)                           \
+        (_buf_)[_i_] = _r_[_i_];                                        \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT16_STRING( _register_, _buf_, _count_)            \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3);          \
+    for( _i_ = 0 = 0; _i_ < (_count_); _i_++)                           \
+        _r_[_i_] = (_buf_)[_i_];                                        \
+    CYG_MACRO_END
+
+
+#endif // Big-endian
+
+//-----------------------------------------------------------------------------
+// 32 bit access.
+// Individual and vectorized access to 32 bit registers.
+
+// Note: same macros for little- and big-endian systems.
+    
+#define HAL_READ_UINT32( _register_, _value_ ) \
+        ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
+
+#define HAL_WRITE_UINT32( _register_, _value_ ) \
+        (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
+
+#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )    \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_];      \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )   \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_,_j_;                                                \
+    for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_))     \
+        ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_];      \
+    CYG_MACRO_END
+
+#define HAL_READ_UINT32_STRING( _register_, _buf_, _count_)             \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_i_];      \
+    CYG_MACRO_END
+
+#define HAL_WRITE_UINT32_STRING( _register_, _buf_, _count_)            \
+    CYG_MACRO_START                                                     \
+    cyg_count32 _i_;                                                    \
+    for( _i_ = 0; _i_ < (_count_); _i_++)                               \
+        ((volatile CYG_WORD32 *)(_register_))[_i_] = (_buf_)[_i_];      \
+    CYG_MACRO_END
+
+
+#define HAL_IO_MACROS_DEFINED
+
+#endif // !HAL_IO_MACROS_DEFINED
+
+// Enforce a flow "barrier" to prevent optimizing compiler from reordering 
+// operations.
+#define HAL_IO_BARRIER()
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_IO_H
+// End of hal_io.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S
new file mode 100644
index 0000000..6b0b833
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/context.S
@@ -0,0 +1,324 @@
+// #===========================================================================
+// #
+// #    context.S
+// #
+// #    ZYLIN context switch code
+// #
+// #===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+// #===========================================================================
+// ######DESCRIPTIONBEGIN####
+// #
+// # Author(s):    nickg, gthomas
+// # Contributors: nickg, gthomas
+// # Date:         1998-09-15
+// # Purpose:      ZYLIN context switch code
+// # Description:  This file contains implementations of the thread context 
+// #               switch routines. It also contains the longjmp() and setjmp()
+// #               routines.
+// #
+// #####DESCRIPTIONEND####
+// #
+// #===========================================================================
+
+#include <pkgconf/hal.h>
+#ifdef CYGPKG_KERNEL  // no CDL yet
+#include <pkgconf/kernel.h>
+#else
+# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
+# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+#endif
+
+
+
+
+#include "zylin.inc"
+
+        .text
+
+
+;; By using a macro, we get multiple breakpoint sites
+	.macro LOAD_STATE 
+	popsp	
+	; stack pointer now points to beginning of HAL_SavedRegisters
+	; we now pop the state of the CPU
+
+	; this will restore r0-r3
+	im 0
+	store		
+	im 4	
+	store		
+	im 8
+	store		
+	im 12
+	store		
+	im 16
+	store		
+	im 20
+	store		
+	im 24
+	store		
+	im 28
+	store		
+	
+	;; restore interrupts 
+	im INTERRUPT_MASK
+	load
+	store
+
+
+	.endm
+
+
+// ----------------------------------------------------------------------------
+//  hal_thread_switch_context
+//  Switch thread contexts
+
+	    
+	.globl hal_thread_switch_context
+hal_thread_switch_context:
+
+	;; save interrupt state
+	im INTERRUPT_MASK
+	load
+	load
+
+	; store current state on stack
+	im 28
+	load
+	im 24
+	load
+	im 20
+	load
+	im 16
+	load
+	im 12
+	load
+	im 8 
+	load
+	im 4
+	load
+	im 0
+	load
+	
+
+	;; store pointer to SP in "from" pointer
+	pushsp
+	pushsp
+	im 8+8*4+4+4
+	add
+	load
+	store		
+
+	;; put pointer to '*to' on stack
+	pushsp
+	im 4+8*4+4
+	add
+	load
+	load
+
+	LOAD_STATE
+
+	poppc			; voila! jump to saved pc
+	
+	
+		
+        
+// ----------------------------------------------------------------------------
+//  hal_thread_load_context
+//  Load thread context
+
+	.globl hal_thread_load_context
+hal_thread_load_context:
+	pushsp
+	im 4
+	add
+	load
+	load			; pointer to HAL_SavedRegisters on stack
+
+load_state_internal:	
+	LOAD_STATE
+	
+	poppc			; voila! jump to saved pc
+
+// ----------------------------------------------------------------------------
+//  HAL longjmp, setjmp implementations
+
+	.globl hal_setjmp
+hal_setjmp:	
+	.byte 0
+
+        
+	.globl hal_longjmp
+ hal_longjmp:	
+	.byte 0
+
+// ----------------------------------------------------------------------------
+//  end of context.S
+
+#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+
+	; push 1 onto stack if we're already switched, 0 otherwise
+	.macro  check_thread_stack
+	pushsp						; 0xda68
+	im __interrupt_stack		; 0x241a
+	lessthan					; => 1
+	im __interrupt_stack_base
+	pushsp 
+	lessthan
+	or
+	
+	.endm
+
+	; push 1 onto stack if we're already switched, 0 otherwise
+	.macro  switch_stack
+	pushsp
+	im __interrupt_stack-4
+	store	; saved stack pointer on interrupt stack.
+	
+	im __interrupt_stack-4
+	popsp
+	; we're now on the interrupt stack 
+	
+	.endm
+	
+	.macro  switch_stack_back
+	; return to thread stack
+	popsp
+	.endm
+
+_zpu_invoke_zpu_interrupt_stack:
+	im hal_IRQ_handler
+	call
+	im 0
+	load ; return value - source
+	
+	im _zpu_interrupt_stack
+	call
+	im 0 
+	load ; return value - result
+	
+	; we've got source and ISR result args on the stack
+	im _zpu_interrupt_thread
+	call
+	storesp 0 ; destroy args 
+	storesp 0
+
+	poppc
+
+
+// switch to interrupt stack, invoke interrupt handler, switch back to original stack, enable interrupts
+	.globl _zpu_interrupt
+_zpu_interrupt:
+	; disable interrupts, we don't nest	
+	im 1
+	nop
+	im INTERRUPT_MASK
+	load
+	store	
+
+	; if we're interrupting the DSRs then
+	; we're already on the interrupt stack
+	check_thread_stack
+	
+	impcrel _already_switched
+	eqbranch
+	
+_zpu_interrupt_switch_stack:
+	switch_stack	
+	
+	im _zpu_invoke_zpu_interrupt_stack
+	call
+	
+	switch_stack_back
+	
+	im .already_switched2
+	poppc
+	
+_already_switched:
+	im _zpu_invoke_zpu_interrupt_stack
+	call
+	
+.already_switched2:
+	; turn on interrupts and run on thread stack.	
+	im 0
+	nop
+	im INTERRUPT_MASK
+	load
+	store	; unmask interrupts
+
+	; we're now running on thread stack
+	
+	im _zpu_interrupt_thread
+	call
+	
+	poppc
+
+	.globl hal_interrupt_stack_call_pending_DSRs
+hal_interrupt_stack_call_pending_DSRs:
+	; the scheduler is not running, so only interrupts
+	; could have switched stacks at this point and
+	; since we're running, interrupts are not
+	switch_stack	
+	
+	im cyg_interrupt_call_pending_DSRs
+	call
+	
+	switch_stack_back
+
+	; back on thread stack
+	poppc
+
+
+
+	
+// Runtime stack used during all interrupt processing
+#ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096
+#endif
+		.bss
+        .balign 4,0
+        .global cyg_interrupt_stack_base
+cyg_interrupt_stack_base:
+__interrupt_stack_base:
+        .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
+        .byte 0
+        .endr
+        .balign 4,0
+        .global cyg_interrupt_stack
+cyg_interrupt_stack:
+__interrupt_stack:
+#endif
+
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c
new file mode 100644
index 0000000..eea2465
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_misc.c
@@ -0,0 +1,177 @@
+/*==========================================================================
+//
+//      hal_misc.c
+//
+//      HAL miscellaneous functions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, gthomas
+// Contributors: nickg, gthomas
+// Date:         1999-02-20
+// Purpose:      HAL miscellaneous functions
+// Description:  This file contains miscellaneous functions provided by the
+//               HAL.
+//
+//####DESCRIPTIONEND####
+//
+//=========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_zylin.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+#ifdef CYGPKG_CYGMON
+#include <pkgconf/cygmon.h>
+#endif
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+
+#include <cyg/hal/var_io.h>
+#include <cyg/hal/hal_io.h>
+
+externC void diag_printf(const char *fmt, ...);
+
+/*------------------------------------------------------------------------*/
+/* First level C exception handler.                                       */
+
+
+/*------------------------------------------------------------------------*/
+/* C++ support - run initial constructors                                 */
+
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+cyg_bool cyg_hal_stop_constructors;
+#endif
+
+typedef void (*pfunc) (void);
+extern pfunc __CTOR_LIST__[];
+extern pfunc __CTOR_END__[];
+
+void
+cyg_hal_invoke_constructors (void)
+{
+#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
+    static pfunc *p = &__CTOR_END__[-1];
+    
+    cyg_hal_stop_constructors = 0;
+    for (; p >= __CTOR_LIST__; p--) {
+        (*p) ();
+        if (cyg_hal_stop_constructors) {
+            p--;
+            break;
+        }
+    }
+#else
+    pfunc *p;
+
+    for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
+        (*p) ();
+#endif
+}
+
+
+/*-------------------------------------------------------------------------*/
+/* Misc functions                                                          */
+
+int
+hal_lsbindex(int mask)
+{
+    int i;
+    for (i = 0;  i < 32;  i++) {
+      if (mask & (1<<i)) return (i);
+    }
+    return (-1);
+}
+
+int
+hal_msbindex(int mask)
+{
+    int i;
+    for (i = 31;  i >= 0;  i--) {
+      if (mask & (1<<i)) return (i);
+    }
+    return (-1);
+}
+
+/*------------------------------------------------------------------------*/
+/* Architecture default ISR                                               */
+
+externC cyg_uint32
+hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
+{
+    CYG_TRACE1(true, "Interrupt: %d", vector);
+
+    CYG_FAIL("Spurious Interrupt!!!");
+    return 0;
+}
+
+extern volatile int *INTERRUPT_MASK;
+
+cyg_uint32 zpu_disable_interrupts()
+{
+	/* NOTE! We disable interrupts before flipping the cached state */
+	cyg_uint32 t=*INTERRUPT_MASK;
+	*INTERRUPT_MASK=1;
+	return t;
+}
+
+void zpu_enable_interrupts()
+{
+	*INTERRUPT_MASK=0;
+}
+
+void zpu_restore_interrupts(cyg_uint32 t)
+{
+	if (t==0)
+		zpu_enable_interrupts();
+	else
+		zpu_disable_interrupts();
+}
+
+externC cyg_uint32 zpu_query_interrupts()
+{
+	return *INTERRUPT_MASK;
+}
+
+/*------------------------------------------------------------------------*/
+// EOF hal_misc.c
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_mk_defs.c b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_mk_defs.c
new file mode 100644
index 0000000..734ce65
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/hal_mk_defs.c
@@ -0,0 +1,102 @@
+/*==========================================================================
+//
+//      hal_mk_defs.c
+//
+//      HAL (architecture) "make defs" program
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         1999-02-20
+// Purpose:      ZYLIN architecture dependent definition generator
+// Description:  This file contains code that can be compiled by the target
+//               compiler and used to generate machine specific definitions
+//               suitable for use in assembly code.
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+# include <cyg/kernel/instrmnt.h>
+#endif
+#include <cyg/hal/hal_if.h>
+
+/*
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * This technique was first used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ */
+
+#define DEFINE(sym, val) \
+        asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val))
+
+int
+main(void)
+{
+    DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT);
+    DEFINE(CYGNUM_HAL_VSR_COUNT, CYGNUM_HAL_VSR_COUNT);
+    DEFINE(CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION,
+           CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION);
+    DEFINE(CYGNUM_HAL_EXCEPTION_CODE_ACCESS,
+           CYGNUM_HAL_EXCEPTION_CODE_ACCESS);
+    DEFINE(CYGNUM_HAL_EXCEPTION_DATA_ACCESS,
+           CYGNUM_HAL_EXCEPTION_DATA_ACCESS);
+    DEFINE(CYGNUM_HAL_VECTOR_IRQ, CYGNUM_HAL_VECTOR_IRQ);
+#ifdef CYGPKG_KERNEL
+    DEFINE(RAISE_INTR, CYG_INSTRUMENT_CLASS_INTR|CYG_INSTRUMENT_EVENT_INTR_RAISE);
+#endif
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
+    DEFINE(CYGNUM_CALL_IF_TABLE_SIZE, CYGNUM_CALL_IF_TABLE_SIZE);
+#endif
+    DEFINE(CYGNUM_HAL_INTERRUPT_NONE, CYGNUM_HAL_INTERRUPT_NONE);
+    return 0;
+}
+
+
+/*------------------------------------------------------------------------*/
+// EOF hal_mk_defs.c
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c
new file mode 100644
index 0000000..b254a85
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/vectors.c
@@ -0,0 +1,116 @@
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_zylin.h>
+#ifdef CYGPKG_KERNEL
+#include <pkgconf/kernel.h>
+#endif
+#ifdef CYGPKG_CYGMON
+#include <pkgconf/cygmon.h>
+#endif
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // HAL header
+#include <cyg/hal/hal_intr.h>           // HAL header
+#include <string.h>
+#include <cyg/hal/hal_arch.h>           // Register state info
+
+extern char __bss_start[];
+extern char __bss_end[];
+
+externC void cyg_hal_invoke_constructors (void);
+externC void cyg_start (void);
+externC void hal_hardware_init (void);
+externC void _initIO();
+
+void _premain(void)
+{
+    // clear BSS
+	memset(__bss_start, 0, __bss_end-__bss_start);
+	
+	_initIO();
+
+	hal_hardware_init();	
+	
+    cyg_hal_invoke_constructors();
+
+	cyg_start();
+	
+	__asm("breakpoint"); // stop debugger/sim here for now
+//	for (;;); // hang forever
+}
+
+CYG_ADDRWORD hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
+CYG_ADDRWORD hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
+CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
+CYG_ADDRWORD hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
+
+externC cyg_ucount32 cyg_scheduler_sched_lock;
+externC cyg_uint32 hal_IRQ_handler();
+
+externC void interrupt_end(
+    cyg_uint32          isr_ret,
+    CYG_ADDRWORD       intr,
+    HAL_SavedRegisters  *ctx
+    );
+
+
+#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
+
+
+void _zpu_interrupt(void)
+{
+	cyg_uint32 source;
+#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT                 
+	cyg_scheduler_sched_lock++;
+#endif
+	/* we don't support reentrant interrupts, so we disable interrupts here. */
+	cyg_uint32 t;
+	HAL_DISABLE_INTERRUPTS(t);
+
+	source=hal_IRQ_handler();
+ 	if (source!=CYGNUM_HAL_INTERRUPT_NONE)
+ 	{
+
+ 		cyg_uint32 result;
+
+ 		result=((cyg_uint32 (*)(cyg_uint32, CYG_ADDRWORD))hal_interrupt_handlers[source])(source, hal_interrupt_data[source]);
+ 	 	/* restore interrupts again. */
+ 		HAL_ENABLE_INTERRUPTS();
+ 		/* Interrupts must be enabled here as the scheduler is invoked here. */
+ 		interrupt_end(result, hal_interrupt_objects[source], NULL);
+ 	} else
+ 	{
+ 	 	/* restore interrupts again. */
+ 		HAL_ENABLE_INTERRUPTS();
+ 	}
+}
+#else
+/* low-level interrupt handling routine */
+cyg_uint32 _zpu_interrupt_stack(cyg_uint32 source)
+{
+#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT                 
+	cyg_scheduler_sched_lock++;
+#endif
+	/* we don't support reentrant interrupts, so we disable interrupts here. */
+	cyg_uint32 t;
+	HAL_DISABLE_INTERRUPTS(t);
+	
+	cyg_uint32 result=0;
+ 	if (source!=CYGNUM_HAL_INTERRUPT_NONE)
+ 	{
+ 		cyg_uint32 result;
+ 		result=((cyg_uint32 (*)(cyg_uint32, CYG_ADDRWORD))hal_interrupt_handlers[source])(source, hal_interrupt_data[source]);
+ 	}
+ 	return result;
+}
+void _zpu_interrupt_thread(cyg_uint32 source, cyg_uint32 result)
+{
+ 	if (source!=CYGNUM_HAL_INTERRUPT_NONE)
+ 	{
+ 		/* Interrupts must be enabled here as the scheduler is invoked here. */
+ 		interrupt_end(result, hal_interrupt_objects[source], NULL);
+ 	}
+}
+#endif
diff --git a/zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld
new file mode 100644
index 0000000..eef2cd7
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/arch/current/src/zylin.ld
@@ -0,0 +1,226 @@
+//=============================================================================
+//
+// MLT linker script for ZYLIN
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <pkgconf/system.h>
+
+STARTUP(crt0.o)
+ENTRY(_start)
+INPUT(crt_io.o)
+INPUT(extras.o)
+INPUT(vectors.o)
+GROUP(libtarget.a libgcc.a libsupc++.a)
+
+// Keep RODATA in separate sections.
+#define MERGE_IN_RODATA
+
+#define ALIGN_LMA 4
+#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
+#define LMA_EQ_VMA
+#define FORCE_OUTPUT . = .
+
+#define SECTIONS_BEGIN                        
+
+#define SECTION_fixed_vectors(_region_, _vma_, _lma_) \
+    .fixed_vectors _vma_ : _lma_ \
+    { FORCE_OUTPUT; KEEP (*(.fixed_vectors)) } \
+    > _region_
+
+#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
+    .rom_vectors _vma_ : _lma_ \
+    { __rom_vectors_vma = ABSOLUTE(.); \
+      FORCE_OUTPUT; KEEP (*(.vectors)) } \
+    > _region_ \
+    __rom_vectors_lma = LOADADDR(.rom_vectors);
+
+#define SECTION_text(_region_, _vma_, _lma_) \
+    .text _vma_ : _lma_ \
+    { _stext = ABSOLUTE(.); \
+    PROVIDE (__stext = ABSOLUTE(.)); \
+    *(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \
+    *(.glue_7) *(.glue_7t)  \
+    } > _region_ \
+    _etext = .; PROVIDE (__etext = .);
+
+#define SECTION_fini(_region_, _vma_, _lma_) \
+    .fini _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.fini) } \
+    > _region_
+
+#define SECTION_rodata(_region_, _vma_, _lma_) \
+    .rodata _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.rodata*) *(.gnu.linkonce.r.*) } \
+    > _region_
+
+#define SECTION_rodata1(_region_, _vma_, _lma_) \
+    .rodata1 _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.rodata1) } \
+    > _region_
+
+#define SECTION_fixup(_region_, _vma_, _lma_) \
+    .fixup _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.fixup) } \
+    > _region_
+
+#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
+    .gcc_except_table _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.gcc_except_table) } \
+    > _region_
+
+#define SECTION_eh_frame(_region_, _vma_, _lma_)      \
+  .eh_frame _vma_ : _lma_                             \
+    {                                                 \
+       FORCE_OUTPUT;  __EH_FRAME_BEGIN__ = .;         \
+       KEEP(*(.eh_frame))                             \
+       __FRAME_END__ = .;                             \
+       . = . + 8;                                     \
+    } > _region_ = 0
+
+#define SECTION_RELOCS(_region_, _vma_, _lma_)                              \
+  .rel.text      :                                                          \
+    {                                                                       \
+      *(.rel.text)                                                          \
+      *(.rel.text.*)                                                        \
+      *(.rel.gnu.linkonce.t*)                                               \
+    } > _region_                                                            \
+  .rela.text     :                                                          \
+    {                                                                       \
+      *(.rela.text)                                                         \
+      *(.rela.text.*)                                                       \
+      *(.rela.gnu.linkonce.t*)                                              \
+    } > _region_                                                            \
+  .rel.data      :                                                          \
+    {                                                                       \
+      *(.rel.data)                                                          \
+      *(.rel.data.*)                                                        \
+      *(.rel.gnu.linkonce.d*)                                               \
+    } > _region_                                                            \
+  .rela.data     :                                                          \
+    {                                                                       \
+      *(.rela.data)                                                         \
+      *(.rela.data.*)                                                       \
+      *(.rela.gnu.linkonce.d*)                                              \
+    } > _region_                                                            \
+  .rel.rodata    :                                                          \
+    {                                                                       \
+      *(.rel.rodata)                                                        \
+      *(.rel.rodata.*)                                                      \
+      *(.rel.gnu.linkonce.r*)                                               \
+    } > _region_                                                            \
+  .rela.rodata   :                                                          \
+    {                                                                       \
+      *(.rela.rodata)                                                       \
+      *(.rela.rodata.*)                                                     \
+      *(.rela.gnu.linkonce.r*)                                              \
+    } > _region_                                                            \
+  .rel.got       :   { *(.rel.got)    } > _region_                          \
+  .rela.got      :   { *(.rela.got)   } > _region_                          \
+  .rel.ctors     :   { *(.rel.ctors)  } > _region_                          \
+  .rela.ctors    :   { *(.rela.ctors) } > _region_                          \
+  .rel.dtors     :   { *(.rel.dtors)  } > _region_                          \
+  .rela.dtors    :   { *(.rela.dtors) } > _region_                          \
+  .rel.init      :   { *(.rel.init)   } > _region_                          \
+  .rela.init     :   { *(.rela.init)  } > _region_                          \
+  .rel.fini      :   { *(.rel.fini)   } > _region_                          \
+  .rela.fini     :   { *(.rela.fini)  } > _region_                          \
+  .rel.bss       :   { *(.rel.bss)    } > _region_                          \
+  .rela.bss      :   { *(.rela.bss)   } > _region_                          \
+  .rel.plt       :   { *(.rel.plt)    } > _region_                          \
+  .rela.plt      :   { *(.rela.plt)   } > _region_                          \
+  .rel.dyn       :   { *(.rel.dyn)    } > _region_
+
+#define SECTION_got(_region_, _vma_, _lma_)                                 \
+  .got _vma_ : _lma_                                                        \
+    {                                                                       \
+      FORCE_OUTPUT; *(.got.plt) *(.got)                                     \
+      _GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.);      \
+      _GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.);      \
+    } > _region_
+
+#define SECTION_mmu_tables(_region_, _vma_, _lma_) \
+    .mmu_tables _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.mmu_tables) } \
+    > _region_
+
+#define SECTION_sram(_region_, _vma_, _lma_) \
+    .sram _vma_ : _lma_ \
+    { FORCE_OUTPUT; *(.sram*) } \
+    > _region_
+
+#define SECTION_data(_region_,  _vma_, _lma_) \
+    .data _vma_ : _lma_ \
+    { __ram_data_start = ABSOLUTE (.); \
+    *(.data*) *(.data1) *(.gnu.linkonce.d.*) MERGE_IN_RODATA \
+    . = ALIGN (4); \
+    KEEP(*( SORT (.ecos.table.*))) ;            \
+    . = ALIGN (4); \
+    __CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \
+    __DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \
+    *(.dynamic) *(.sdata*) *(.gnu.linkonce.s.*) \
+    . = ALIGN (4); *(.2ram.*) } \
+    > _region_ \
+    __rom_data_start = LOADADDR (.data); \
+    __ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); \
+    PROVIDE (__rom_data_end = LOADADDR (.data) + SIZEOF(.data));
+
+#define SECTION_bss(_region_,  _vma_, _lma_) \
+    .bss _vma_ : _lma_ \
+    { __bss_start = ABSOLUTE (.); \
+    *(.scommon) *(.dynsbss) *(.sbss*) *(.gnu.linkonce.sb.*) \
+    *(.dynbss) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON) \
+    __bss_end = ABSOLUTE (.); } \
+    > _region_
+
+// Some versions of gcc define "zpu" which causes problems with .note.arm.ident
+#undef zpu
+#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \
+  /* Debug information */                       \
+  .debug_aranges  0 : { *(.debug_aranges) }     \
+  .debug_pubnames 0 : { *(.debug_pubnames) }    \
+  .debug_info     0 : { *(.debug_info) }        \
+  .debug_abbrev   0 : { *(.debug_abbrev) }      \
+  .debug_line     0 : { *(.debug_line) }        \
+  .debug_frame    0 : { *(.debug_frame) }       \
+  .debug_str      0 : { *(.debug_str) }         \
+  .debug_loc      0 : { *(.debug_loc) }         \
+  .debug_macinfo  0 : { *(.debug_macinfo) }     \
+  .note.gnu.zpu.ident 0 : { KEEP (*(.note.gnu.zpu.ident)) }
+
+
+#include <pkgconf/hal_zylin.h>
+#include CYGHWR_MEMORY_LAYOUT_LDI
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog
new file mode 100644
index 0000000..a29dbf8
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/ChangeLog
@@ -0,0 +1,39 @@
+2004-09-16  Øyvind Harboe <oyvind.harboe@zylin.com>
+
+	* first cut HAL support for ZPU
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl
new file mode 100644
index 0000000..f5c2f81
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/cdl/hal_zylin_zpu_abel.cdl
@@ -0,0 +1,298 @@
+# ====================================================================
+#
+#      hal_zpu.cdl
+#
+#      ZPU HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      
+# Contributors:   
+# Date:           2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ZYLIN_ZPU_ABEL {
+    display       "Zylin ZPU HAL"
+    parent        CYGPKG_HAL_ZYLIN_ZPU
+    define_header hal_zylin_zpu_abel.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The Zylin ZPU HAL package provides the support needed to run
+        eCos on an Zylin ZPU board using the Abel board."
+
+    compile       abel_misc.c
+
+    requires      { CYGHWR_HAL_ZYLIN_ZPU == "ZPU1" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_zylin.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_zylin_zpu.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_zylin_zpu_abel.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"ZPU1\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Zylin Abel\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    # Real-time clock/counter specifics
+    cdl_option CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED {
+        display       "CPU clock speed"
+        flavor        data
+        default_value 90000000
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value (CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR)
+        }
+    }
+
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"RAM"}
+        legal_values  {"RAM"}
+	    no_define
+	    define -file system.h CYG_HAL_STARTUP
+        description   "
+            When targetting the ZPU board it is possible to build
+            the system for either RAM bootstrap or ROM bootstrap(s). Select
+            'ram' when building programs to load into RAM using onboard
+            debug software such as Angel or eCos GDB stubs.  Select 'rom'
+            when building a stand-alone application which will be put
+            into ROM.  Using ROMRAM will allow the program to exist in
+            ROM, but be copied to RAM during startup."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+ 
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    0
+         description      "
+            This option
+            chooses which port will be used for diagnostic output."
+     }
+     
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option selects the baud rate used for the diagnostic port."
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+         display       "GDB serial port baud rate"
+         flavor        data
+         legal_values  9600 19200 38400 57600 115200
+         default_value 38400
+         description   "
+            This option controls the baud rate used for the GDB connection."
+     }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" }
+         default_value { 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary image"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to a binary image suitable for ROM programming."
+    
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img) 
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+
+        }
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "zpu-elf" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { "-Wall -Wpointer-arith -Winline -Wundef -g -Os -ffunction-sections -fdata-sections  -fno-exceptions -finit-priority -abel" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-Wl,--gc-sections -Wl,-static -g -nostdlib -abel -Wl,--relax -Os" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+ 
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated { (CYG_HAL_STARTUP == "RAM") ?    "zpu_ram" :
+                     (CYG_HAL_STARTUP == "ROMRAM") ? "zpu_romram" :
+                                                     "zpu_rom" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_abel_ram.ldi>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_abel_romram.ldi>" :
+                                                      "<pkgconf/mlt_zylin_zpu_abel_rom.ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_abel_ram.h>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_abel_romram.h>" :
+                                                      "<pkgconf/mlt_zylin_zpu_abel_rom.h>" }
+        }
+    }
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h
new file mode 100644
index 0000000..9ff0029
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/hal_platform_ints.h
@@ -0,0 +1,79 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+//==========================================================================
+//
+//      hal_platform_ints.h
+//
+//      HAL Interrupt and clock assignments for ZPU
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2001-07-12
+// Purpose:      Define Interrupt support
+// Description:  The interrupt specifics for the ZPU board/platform are
+//               defined here.
+//              
+// Usage:        #include <cyg/hal/hal_platform_ints.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_TIMER		0
+
+#define CYGNUM_HAL_ISR_MIN              0
+
+#define CYGNUM_HAL_ISR_MAX              0
+
+#define CYGNUM_HAL_ISR_COUNT                   (CYGNUM_HAL_ISR_MAX + 1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC               CYGNUM_HAL_INTERRUPT_TIMER
+
+
+//----------------------------------------------------------------------------
+// Reset.
+__externC void hal_zpu_reset_cpu(void);
+#define HAL_PLATFORM_RESET() hal_zpu_reset_cpu()
+
+
+
+#endif // CYGONCE_HAL_PLATFORM_INTS_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h
new file mode 100644
index 0000000..4d31221
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.h
@@ -0,0 +1,17 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x00008000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi
new file mode 100644
index 0000000..9a50a17
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/pkgconf/mlt_zylin_zpu_abel_ram.ldi
@@ -0,0 +1,27 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0x00000000, LENGTH = 0x8000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_fixed_vectors (ram, 0x0, LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h
new file mode 100644
index 0000000..7e6a234
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/include/plf_io.h
@@ -0,0 +1,64 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      ZPU board specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   tkoeller
+// Contributors: tdrury
+// Date:        2002-06-22
+// Purpose:     Zylin ZPU board specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+/* cause an "interrupt" from the idle thread */
+
+void _zpu_interrupt(void);
+/* KLUDGE!!!! some linker problem with _zpu_interrupt() that I'll solve later */
+#define HAL_IDLE_THREAD_ACTION(_count_) ((void (*)())0x20)();
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm
new file mode 100644
index 0000000..04eae62
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/misc/redboot_RAM.ecm
@@ -0,0 +1,53 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    zpu_board ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_ZPU current ;
+    package -hardware CYGPKG_HAL_ZPU_CPU current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+};
+
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGOPT_REDBOOT_FIS {
+    user_value 0
+};
+
+cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
+    user_value 0
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+    user_value 0
+};
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c
new file mode 100644
index 0000000..ed5a0e9
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/abel/current/src/abel_misc.c
@@ -0,0 +1,61 @@
+//==========================================================================
+//
+//      zpu_misc.c
+//
+//      HAL misc board support code for Zylin ZPU board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas, jskov, tkoeller, tdrury, nickg
+// Date:         2002-05-30
+// Purpose:      HAL board support
+// Description:  Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/hal/hal_io.h>             // low level i/o
+#include <cyg/hal/var_io.h>             // common registers
+#include <cyg/hal/plf_io.h>             // platform registers
+
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog
new file mode 100644
index 0000000..a29dbf8
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/ChangeLog
@@ -0,0 +1,39 @@
+2004-09-16  Øyvind Harboe <oyvind.harboe@zylin.com>
+
+	* first cut HAL support for ZPU
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl
new file mode 100644
index 0000000..d7b7234
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/cdl/hal_zylin_zpu_phi.cdl
@@ -0,0 +1,292 @@
+# ====================================================================
+#
+#      hal_zpu.cdl
+#
+#      ZPU HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      
+# Contributors:   
+# Date:           2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ZYLIN_ZPU_PHI {
+    display       "Zylin ZPU HAL"
+    parent        CYGPKG_HAL_ZYLIN_ZPU
+    define_header hal_zylin_zpu_phi.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The Zylin ZPU HAL package provides the support needed to run
+        eCos on an Zylin ZPU board."
+
+    compile       phi_misc.c
+
+    requires      { CYGHWR_HAL_ZYLIN_ZPU == "ZPU1" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_zylin.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_zylin_zpu.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_zylin_zpu_phi.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"ZPU1\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Zylin Phi\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    # Real-time clock/counter specifics
+    cdl_option CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED {
+        display       "CPU clock speed"
+        flavor        data
+        default_value 64000000
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+	        description   "How many times a second to invoke the timer interrupt, normally 100"
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value (CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR)
+        }
+    }
+
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"RAM"}
+        legal_values  {"RAM"}
+	    no_define
+	    define -file system.h CYG_HAL_STARTUP
+        description   "For now the eCosBoard only supports DRAM startup"
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+ 
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    0
+         description      "
+            This option
+            chooses which port will be used for diagnostic output."
+     }
+     
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option selects the baud rate used for the diagnostic port."
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+         display       "GDB serial port baud rate"
+         flavor        data
+         legal_values  9600 19200 38400 57600 115200
+         default_value 38400
+         description   "
+            This option controls the baud rate used for the GDB connection."
+     }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" }
+         default_value { 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary image"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to a binary image suitable for ROM programming."
+    
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img) 
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+
+        }
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "zpu-elf" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { "-Wall -Wpointer-arith -Winline -Wundef -g -Os -ffunction-sections -fdata-sections  -fno-exceptions -phi" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-Wl,--gc-sections -Wl,-static -g -nostdlib -phi -Wl,--relax -Os" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+ 
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated { (CYG_HAL_STARTUP == "RAM") ?    "zpu_ram" :
+                     (CYG_HAL_STARTUP == "ROMRAM") ? "zpu_romram" :
+                                                     "zpu_rom" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_phi_ram.ldi>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_phi_romram.ldi>" :
+                                                      "<pkgconf/mlt_zylin_zpu_phi_rom.ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_phi_ram.h>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_phi_romram.h>" :
+                                                      "<pkgconf/mlt_zylin_zpu_phi_rom.h>" }
+        }
+    }
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h
new file mode 100644
index 0000000..1ec0475
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/hal_platform_ints.h
@@ -0,0 +1,81 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+//==========================================================================
+//
+//      hal_platform_ints.h
+//
+//      HAL Interrupt and clock assignments for ZPU
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2001-07-12
+// Purpose:      Define Interrupt support
+// Description:  The interrupt specifics for the ZPU board/platform are
+//               defined here.
+//              
+// Usage:        #include <cyg/hal/hal_platform_ints.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_TIMER		0
+#define CYGNUM_HAL_INTERRUPT_UART		1
+#define CYGNUM_HAL_INTERRUPT_ETHERMAC	2
+
+#define CYGNUM_HAL_ISR_MIN              0
+
+#define CYGNUM_HAL_ISR_MAX              2
+
+#define CYGNUM_HAL_ISR_COUNT                   (CYGNUM_HAL_ISR_MAX + 1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC               CYGNUM_HAL_INTERRUPT_TIMER
+
+
+//----------------------------------------------------------------------------
+// Reset.
+__externC void hal_zpu_reset_cpu(void);
+#define HAL_PLATFORM_RESET() hal_zpu_reset_cpu()
+
+
+
+#endif // CYGONCE_HAL_PLATFORM_INTS_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h
new file mode 100644
index 0000000..165467f
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.h
@@ -0,0 +1,17 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x01ff0000) // 0x10000 as startup stack...
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi
new file mode 100644
index 0000000..ef5947c
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/pkgconf/mlt_zylin_zpu_phi_ram.ldi
@@ -0,0 +1,27 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0x00000000, LENGTH = 0x01ff0000 // 0x10000 as startup stack...
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_fixed_vectors (ram, 0x0, LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h
new file mode 100644
index 0000000..1c6f53b
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/include/plf_io.h
@@ -0,0 +1,58 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      ZPU board specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   tkoeller
+// Contributors: tdrury
+// Date:        2002-06-22
+// Purpose:     Zylin ZPU board specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c
new file mode 100644
index 0000000..f7393f7
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/phi/current/src/phi_misc.c
@@ -0,0 +1,72 @@
+//==========================================================================
+//
+//      zpu_misc.c
+//
+//      HAL misc board support code for Zylin ZPU board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas, jskov, tkoeller, tdrury, nickg
+// Date:         2002-05-30
+// Purpose:      HAL board support
+// Description:  Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/hal/hal_io.h>             // low level i/o
+#include <cyg/hal/var_io.h>             // common registers
+#include <cyg/hal/plf_io.h>             // platform registers
+
+
+volatile int *INTERRUPT_MASK=(volatile int *)0x080a0020;
+
+volatile int *TIMER_PERIOD=(volatile int *)0x080a0034;
+volatile int *TIMER_INTERRUPT=(volatile int *)0x080a0030;
+volatile int *TIMER_ENABLE=(volatile int *)0x080a002c;
+volatile int *TIMER_COUNTER=(volatile int *)0x080a0038;
+volatile int *UART_INTERRUPT=(volatile int *)0x080a0028;
+volatile int *UART_ENABLE=(volatile int *)0x080a0024;
+
+
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog
new file mode 100644
index 0000000..519b620
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/ChangeLog
@@ -0,0 +1,38 @@
+2004-12-05  Øyvind Harboe <oyvind.harboe@zylin.com>
+
+	* first cut ZPU HAL
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl
new file mode 100644
index 0000000..8d96088
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/cdl/hal_zylin_zpu.cdl
@@ -0,0 +1,83 @@
+# ====================================================================
+#
+#      hal_zpu.cdl
+#
+#      Zylin ZPU HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+## Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Contributors:   gthomas, tkoeller, tdrury, nickg
+# Date:           2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ZYLIN_ZPU {
+    display       "Zylin ZPU variant HAL"
+    parent        CYGPKG_HAL_ZYLIN
+    define_header hal_zylin_zpu.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The ZPU HAL package provides the support needed to run
+        eCos on Zylin ZPU based targets."
+
+    compile       hal_diag.c zpu_misc.c
+
+
+    # Let the architectural HAL see this variant's files
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_ZPU_VAR_IO_H"
+        puts $::cdl_system_header "#define CYGBLD_HAL_ZPU_VAR_ARCH_H"
+    }
+
+    cdl_option CYGHWR_HAL_ZYLIN_ZPU {
+        display        "ZPU variant used"
+        flavor         data
+        default_value  {"ZPU1"}
+        legal_values   {"ZPU1"}
+        description    "The ZPU microcontroller family has several variants,
+                        the main differences being the amount of on-chip SRAM,
+                        peripherals and their layout. This option allows the
+                        platform HALs to select the specific microcontroller
+                        being used."
+    }
+
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h
new file mode 100644
index 0000000..d3fef4f
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_cache.h
@@ -0,0 +1,192 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg, gthomas
+// Contributors:        nickg, gthomas
+// Date:        1998-09-28
+// Purpose:     Cache control API
+// Description: The macros defined here provide the HAL APIs for handling
+//              cache control operations.
+// Usage:
+//              #include <cyg/hal/hal_cache.h>
+//              ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+// Data cache
+//#define HAL_DCACHE_SIZE                 0    // Size of data cache in bytes
+//#define HAL_DCACHE_LINE_SIZE            0    // Size of a data cache line
+//#define HAL_DCACHE_WAYS                 0    // Associativity of the cache
+
+// Instruction cache
+//#define HAL_ICACHE_SIZE                 0    // Size of cache in bytes
+//#define HAL_ICACHE_LINE_SIZE            0    // Size of a cache line
+//#define HAL_ICACHE_WAYS                 0    // Associativity of the cache
+
+//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+// Set the data cache refill burst size
+//#define HAL_DCACHE_BURST_SIZE(_size_)
+
+// Set the data cache write mode
+//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+
+//#define HAL_DCACHE_WRITETHRU_MODE       0
+//#define HAL_DCACHE_WRITEBACK_MODE       1
+
+// Load the contents of the given address range into the data cache
+// and then lock the cache so that it stays there.
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_DCACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Allocate cache lines for the given address range without reading its
+// contents from memory.
+//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory for the given address range.
+//#define HAL_DCACHE_STORE( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h
new file mode 100644
index 0000000..3a9dba4
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/hal_diag.h
@@ -0,0 +1,90 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov, gthomas, tkoeller
+// Date:        2001-07-12
+// Purpose:     HAL Support for Kernel Diagnostic Routines
+// Description: Diagnostic routines for use during kernel development.
+// Usage:       #include <cyg/hal/hal_diag.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/hal_if.h>
+
+externC void zpu_if_diag_init(void);
+externC void zpu_if_diag_write_char(char c);
+externC void zpu_if_diag_read_char(char *c);
+
+#define HAL_DIAG_INIT() zpu_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) zpu_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) zpu_if_diag_read_char(&_c_)
+
+//-----------------------------------------------------------------------------
+// LED
+externC void hal_diag_led(int mask);
+
+externC void hal_zpu_set_leds(int mask);
+
+//-----------------------------------------------------------------------------
+// delay
+
+externC void hal_delay_us(cyg_int32 usecs);
+#define HAL_DELAY_US(n) hal_delay_us(n);
+
+//-----------------------------------------------------------------------------
+// reset
+
+extern void hal_zpu_reset_cpu(void);
+
+//-----------------------------------------------------------------------------
+// end of hal_diag.h
+#endif // CYGONCE_HAL_DIAG_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h
new file mode 100644
index 0000000..eb87958
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/plf_stub.h
@@ -0,0 +1,85 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov, gthomas
+// Date:        2001-07-12
+// Purpose:     Platform HAL stub support for ZPU boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h
new file mode 100644
index 0000000..293d7fc
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_arch.h
@@ -0,0 +1,73 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      ZPU variant architecture overrides
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2003 Jonathan Larmour <jifl@eCosCentric.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting the copyright
+// holders.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors: Daniel Neri
+// Date:         2003-06-24
+// Purpose:      ZPU variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+//--------------------------------------------------------------------------
+// Idle thread code.
+// This macro is called in the idle thread loop, and gives the HAL the
+// chance to insert code. Typical idle thread behaviour might be to halt the
+// processor. These implementations halt the system core clock.
+
+#ifndef HAL_IDLE_THREAD_ACTION
+#define HAL_IDLE_THREAD_ACTION(_count_)                       \
+CYG_MACRO_START                                               \
+CYG_MACRO_END
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_arch.h
+#endif // CYGONCE_HAL_VAR_ARCH_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h
new file mode 100644
index 0000000..f1ef035
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/include/var_io.h
@@ -0,0 +1,73 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov, gthomas, tkoeller, tdrury, nickg
+// Date:        2001-07-12
+// Purpose:     ZPU variant specific registers
+// Description: 
+// Usage:       #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/hal/plf_io.h>
+
+
+extern volatile int *INTERRUPT_MASK;
+extern volatile int *TIMER_PERIOD;
+extern volatile int *TIMER_INTERRUPT;
+extern volatile int *TIMER_ENABLE;
+extern volatile int *TIMER_COUNTER;
+extern volatile int *UART_INTERRUPT;
+extern volatile int *UART_ENABLE;
+void ethermac_enable(int enable);
+int ethermac_interrupt();
+void ethermac_ack();
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_HAL_VAR_IO_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c
new file mode 100644
index 0000000..0b0f901
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/hal_diag.c
@@ -0,0 +1,88 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov
+// Contributors:jskov, gthomas
+// Date:        2001-07-12
+// Purpose:     HAL diagnostic output
+// Description: Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+
+#include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // interface API
+#include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
+#include <cyg/hal/hal_diag.h>
+
+#include <cyg/hal/var_io.h>             // USART registers
+
+void zpu_if_diag_init(void)
+{
+}
+
+extern void outbyte(int c);
+extern int inbyte();
+
+void 
+zpu_if_diag_write_char(char c)
+{
+	outbyte(c);
+}
+
+void 
+zpu_if_diag_read_char(char *c)
+{
+	*c=inbyte();
+}
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c
new file mode 100644
index 0000000..019e024
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/var/current/src/zpu_misc.c
@@ -0,0 +1,252 @@
+/*==========================================================================
+//
+//      zpu_misc.c
+//
+//      HAL misc board support code for Zylin ZPU
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas, jskov, nickg, tkoeller
+// Date:         2001-07-12
+// Purpose:      HAL board support
+// Description:  Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_arch.h>           // Register state info
+#include <cyg/hal/hal_diag.h>
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+#include <cyg/hal/drv_api.h>            // HAL ISR support
+#endif
+#include <cyg/hal/hal_intr.h>           // necessary?
+
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_if.h>             // calling interface
+#include <cyg/hal/hal_misc.h>           // helper functions
+#include <cyg/hal/var_io.h>             // platform registers
+
+
+
+
+
+// -------------------------------------------------------------------------
+// Clock support
+
+static cyg_uint32 _period;
+
+
+void hal_clock_initialize(cyg_uint32 period)
+{
+	_period=period;
+	*TIMER_PERIOD=period;
+	*TIMER_INTERRUPT=0x2; // reset counter
+}
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+	/* the next interrupt will happen without further action */
+}
+
+
+long long  _readCycles();
+
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+	*pvalue=_period-1-*TIMER_COUNTER;
+}
+
+// -------------------------------------------------------------------------
+//
+void hal_delay_us(cyg_int32 usecs)
+{
+	long long until=_readCycles();
+	until+=((long long)usecs*(long long)(CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED))/(long long)1000000;
+	
+	/* waiting for the moment to pass.... */		
+	for (;;)
+	{
+		if (_readCycles()>until)
+		{
+			break;
+		}
+	}
+}
+
+// -------------------------------------------------------------------------
+// Hardware init
+
+void hal_hardware_init(void)
+{
+	int i;
+	for (i=0; i<CYGNUM_HAL_ISR_COUNT; i++)
+	{
+		hal_interrupt_handlers[i]=(CYG_ADDRESS)hal_default_isr;
+	}
+}
+
+// -------------------------------------------------------------------------
+// This routine is called to respond to a hardware interrupt (IRQ).  It
+// should interrogate the hardware and return the IRQ vector number.
+
+int hal_IRQ_handler(void)
+{
+	// for now we only have this type of interrupt
+	if ((*TIMER_INTERRUPT&0x1)!=0)
+	{
+		return CYGNUM_HAL_INTERRUPT_TIMER;
+	} else if ((*UART_INTERRUPT&0x1)!=0)
+	{
+		return CYGNUM_HAL_INTERRUPT_UART;
+	}
+#ifdef CYGPKG_IO_ETH_DRIVERS
+	else if (ethermac_interrupt())
+	{
+		return CYGNUM_HAL_INTERRUPT_ETHERMAC;
+	} 
+#endif
+	else
+	{
+		return CYGNUM_HAL_INTERRUPT_NONE;
+	}
+}
+
+// -------------------------------------------------------------------------
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+
+	if (vector==CYGNUM_HAL_INTERRUPT_TIMER)
+	{
+		*TIMER_ENABLE=0;
+	} else if (vector==CYGNUM_HAL_INTERRUPT_UART)
+	{
+		*UART_ENABLE=0;
+	} 
+#ifdef CYGPKG_IO_ETH_DRIVERS
+	else if (vector==CYGNUM_HAL_INTERRUPT_ETHERMAC)
+	{
+		ethermac_enable(0);
+	}
+#endif
+}
+
+void hal_interrupt_unmask(int vector)
+{
+    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+	if (vector==CYGNUM_HAL_INTERRUPT_TIMER)
+	{
+		*TIMER_ENABLE=1;
+	} else if (vector==CYGNUM_HAL_INTERRUPT_UART)
+	{
+		*UART_ENABLE=1;
+	} 
+#ifdef CYGPKG_IO_ETH_DRIVERS
+	else if (vector==CYGNUM_HAL_INTERRUPT_ETHERMAC)
+	{
+		ethermac_enable(1);
+	}
+#endif
+	
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+	if (vector==CYGNUM_HAL_INTERRUPT_TIMER)
+	{
+		*TIMER_INTERRUPT=0x1;
+	} else if (vector==CYGNUM_HAL_INTERRUPT_UART)
+	{
+		*UART_INTERRUPT=0x1;
+	} 
+#ifdef CYGPKG_IO_ETH_DRIVERS
+	else if (vector==CYGNUM_HAL_INTERRUPT_ETHERMAC)
+	{
+		ethermac_ack();
+	}
+#endif	
+	
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
+               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
+    CYG_ASSERT(level >= 0 && level <= 7, "Invalid level");
+
+}
+
+void hal_show_IRQ(int vector, int data, int handler)
+{
+}
+
+
+/* Use the watchdog to generate a reset */
+void hal_zpu_reset_cpu(void)
+{
+}
+
+/* nothing to do by default */
+cyg_uint32
+hal_default_isr(cyg_uint32 vector, CYG_ADDRWORD data)
+{
+	return 0;
+}
+
+//--------------------------------------------------------------------------
+// EOF zpu_misc.c
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog
new file mode 100644
index 0000000..a29dbf8
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/ChangeLog
@@ -0,0 +1,39 @@
+2004-09-16  Øyvind Harboe <oyvind.harboe@zylin.com>
+
+	* first cut HAL support for ZPU
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl
new file mode 100644
index 0000000..65a8d59
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/cdl/hal_zylin_zpu_zeta.cdl
@@ -0,0 +1,298 @@
+# ====================================================================
+#
+#      hal_zpu.cdl
+#
+#      ZPU HAL package configuration data
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      
+# Contributors:   
+# Date:           2001-07-12
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ZYLIN_ZPU_ZETA {
+    display       "Zylin ZPU HAL"
+    parent        CYGPKG_HAL_ZYLIN_ZPU
+    define_header hal_zylin_zpu_zeta.h
+    include_dir   cyg/hal
+    hardware
+    description   "
+        The Zylin ZPU HAL package provides the support needed to run
+        eCos on an Zylin ZPU board."
+
+    compile       zeta_misc.c
+
+    requires      { CYGHWR_HAL_ZYLIN_ZPU == "ZPU1" }
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_zylin.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_zylin_zpu.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_zylin_zpu_zeta.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"ZPU1\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Zylin Zeta\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    # Real-time clock/counter specifics
+    cdl_option CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED {
+        display       "CPU clock speed"
+        flavor        data
+        default_value 90000000
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value (CYGNUM_HAL_ZYLIN_ZPU_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR)
+        }
+    }
+
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"RAM"}
+        legal_values  {"RAM"}
+	    no_define
+	    define -file system.h CYG_HAL_STARTUP
+        description   "
+            When targetting the ZPU board it is possible to build
+            the system for either RAM bootstrap or ROM bootstrap(s). Select
+            'ram' when building programs to load into RAM using onboard
+            debug software such as Angel or eCos GDB stubs.  Select 'rom'
+            when building a stand-alone application which will be put
+            into ROM.  Using ROMRAM will allow the program to exist in
+            ROM, but be copied to RAM during startup."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   1
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+ 
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Diagnostic serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    0
+         description      "
+            This option
+            chooses which port will be used for diagnostic output."
+     }
+     
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option selects the baud rate used for the diagnostic port."
+    }
+ 
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+         display       "GDB serial port baud rate"
+         flavor        data
+         legal_values  9600 19200 38400 57600 115200
+         default_value 38400
+         description   "
+            This option controls the baud rate used for the GDB connection."
+     }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" }
+         default_value { 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary image"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to a binary image suitable for ROM programming."
+    
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img) 
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+
+        }
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        parent  CYGPKG_NONE
+        description   "
+	    Global build options including control over
+	    compiler flags, linker flags and choice of toolchain."
+
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "zpu-elf" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { "-Wall -Wpointer-arith -Winline -Wundef -g -Os -ffunction-sections -fdata-sections  -fno-exceptions -finit-priority -zeta" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-Wl,--gc-sections -Wl,-static -g -nostdlib -zeta -Wl,--relax -Os" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+    }
+ 
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated { (CYG_HAL_STARTUP == "RAM") ?    "zpu_ram" :
+                     (CYG_HAL_STARTUP == "ROMRAM") ? "zpu_romram" :
+                                                     "zpu_rom" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_zeta_ram.ldi>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_zeta_romram.ldi>" :
+                                                      "<pkgconf/mlt_zylin_zpu_zeta_rom.ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_zylin_zpu_zeta_ram.h>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_zylin_zpu_zeta_romram.h>" :
+                                                      "<pkgconf/mlt_zylin_zpu_zeta_rom.h>" }
+        }
+    }
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h
new file mode 100644
index 0000000..9ff0029
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/hal_platform_ints.h
@@ -0,0 +1,79 @@
+#ifndef CYGONCE_HAL_PLATFORM_INTS_H
+#define CYGONCE_HAL_PLATFORM_INTS_H
+//==========================================================================
+//
+//      hal_platform_ints.h
+//
+//      HAL Interrupt and clock assignments for ZPU
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas
+// Date:         2001-07-12
+// Purpose:      Define Interrupt support
+// Description:  The interrupt specifics for the ZPU board/platform are
+//               defined here.
+//              
+// Usage:        #include <cyg/hal/hal_platform_ints.h>
+//               ...
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_TIMER		0
+
+#define CYGNUM_HAL_ISR_MIN              0
+
+#define CYGNUM_HAL_ISR_MAX              0
+
+#define CYGNUM_HAL_ISR_COUNT                   (CYGNUM_HAL_ISR_MAX + 1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC               CYGNUM_HAL_INTERRUPT_TIMER
+
+
+//----------------------------------------------------------------------------
+// Reset.
+__externC void hal_zpu_reset_cpu(void);
+#define HAL_PLATFORM_RESET() hal_zpu_reset_cpu()
+
+
+
+#endif // CYGONCE_HAL_PLATFORM_INTS_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h
new file mode 100644
index 0000000..ddbaae8
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.h
@@ -0,0 +1,17 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x10000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE ((CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE) - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi
new file mode 100644
index 0000000..d9a14be
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/pkgconf/mlt_zylin_zpu_zeta_ram.ldi
@@ -0,0 +1,27 @@
+// eCos memory layout - Mon Jul 23 11:49:04 2001
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0x00000000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_fixed_vectors (ram, 0x0, LMA_EQ_VMA)
+    SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rom_vectors (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h
new file mode 100644
index 0000000..1c6f53b
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/include/plf_io.h
@@ -0,0 +1,58 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      ZPU board specific registers
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   tkoeller
+// Contributors: tdrury
+// Date:        2002-06-22
+// Purpose:     Zylin ZPU board specific registers
+// Description:
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm
new file mode 100644
index 0000000..04eae62
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/misc/redboot_RAM.ecm
@@ -0,0 +1,53 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    zpu_board ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_ZPU current ;
+    package -hardware CYGPKG_HAL_ZPU_CPU current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+};
+
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+    inferred_value 0 0
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGOPT_REDBOOT_FIS {
+    user_value 0
+};
+
+cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
+    user_value 0
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+    user_value 0
+};
+
diff --git a/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c
new file mode 100644
index 0000000..b8b2e39
--- /dev/null
+++ b/zpu/sw/ecos/repository/hal/zylin/zpu/zeta/current/src/zeta_misc.c
@@ -0,0 +1,64 @@
+//==========================================================================
+//
+//      zpu_misc.c
+//
+//      HAL misc board support code for Zylin ZPU board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas, jskov, tkoeller, tdrury, nickg
+// Date:         2002-05-30
+// Purpose:      HAL board support
+// Description:  Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/hal/hal_io.h>             // low level i/o
+#include <cyg/hal/var_io.h>             // common registers
+#include <cyg/hal/plf_io.h>             // platform registers
+
+
+void hal_zpu_set_leds(int leds)
+{
+}
diff --git a/zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl b/zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl
new file mode 100644
index 0000000..d98bc96
--- /dev/null
+++ b/zpu/sw/ecos/repository/net/zylin/current/cdl/phi_net.cdl
@@ -0,0 +1,56 @@
+# ====================================================================
+#
+#      net.cdl
+#
+#      Networking configuration data
+#
+# ====================================================================
+#####ECOSPDCOPYRIGHTBEGIN####
+#
+# Copyright (C) 2000, 2001, 2002 Red Hat, Inc.
+# All Rights Reserved.
+#
+# Permission is granted to use, copy, modify and redistribute this
+# file.
+#
+#####ECOSPDCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Original data:  gthomas
+# Contributors:
+# Date:           1999-11-29
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_PHI_NET {
+    display       "Basic networking framework"
+    doc           nothing.html
+    include_dir   .
+    requires      CYGPKG_IO
+    requires      CYGPKG_ISOINFRA
+    requires      CYGINT_ISO_C_TIME_TYPES
+    requires      CYGINT_ISO_STRERROR
+    requires      CYGINT_ISO_ERRNO
+    requires      CYGINT_ISO_ERRNO_CODES
+    requires      CYGINT_ISO_MALLOC
+    requires      CYGINT_ISO_STRING_BSD_FUNCS
+    requires      CYGPKG_NET 
+    description   "Basic networking support, including TCP/IP."
+
+    cdl_component CYGPKG_PHI_NET_INET {
+        display       "INET support"
+        active_if     CYGPKG_NET_STACK_INET
+        flavor        bool
+        no_define
+        default_value 1
+        description   "
+            This option enables support for PHI INET (IP) network processing."
+        compile \
+            phi_network_support.c
+
+    }
+}
diff --git a/zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c b/zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c
new file mode 100644
index 0000000..c297651
--- /dev/null
+++ b/zpu/sw/ecos/repository/net/zylin/current/src/phi_network_support.c
@@ -0,0 +1,368 @@
+//==========================================================================
+//
+//      ph_network_support.c
+//
+//      Misc network support functions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2003 Andrew Lunn <andrew.lunn@ascom.ch>   
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    gthomas
+// Contributors: gthomas, sorin@netappi.com ("Sorin Babeanu"), hmt, jlarmour,
+//               andrew.lunn@ascom.ch
+// Date:         2000-01-10
+// Purpose:      
+// Description:  
+//              
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+// BOOTP support
+
+#include <pkgconf/net.h>
+#undef _KERNEL
+#include <sys/param.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+#include <sys/errno.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include <net/if.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+#include <netinet/ip_icmp.h>
+#include <net/route.h>
+
+#include <cyg/infra/diag.h>
+#include <cyg/kernel/kapi.h>
+
+#include <stdio.h>    // for 'sprintf()'
+#include <string.h>	  // for strncpy and strtok_r
+#include <bootp.h>
+#include <network.h>
+#include <arpa/inet.h>
+
+#ifdef CYGPKG_IO_PCMCIA
+#include <cyg/io/eth/netdev.h>
+#endif
+
+#ifdef CYGPKG_NET_DHCP
+#include <dhcp.h>
+#endif
+
+#ifdef CYGPKG_NS_DNS
+#include <pkgconf/ns_dns.h>
+#endif
+
+#ifdef CYGHWR_NET_DRIVER_ETH0
+//struct bootp eth0_bootp_data;
+//cyg_bool_t   eth0_up = false;
+//const char  *eth0_name = "eth0";
+#endif
+#ifdef CYGHWR_NET_DRIVER_ETH1
+struct bootp eth1_bootp_data;
+//cyg_bool_t   eth1_up = false;
+//const char  *eth1_name = "eth1";
+#endif
+
+#define _string(s) #s
+#define string(s) _string(s)
+
+#ifndef CYGPKG_LIBC_STDIO
+#define perror(s) diag_printf(#s ": %s\n", strerror(errno))
+#endif
+
+
+static int hasIP(char *ip, char *mask, char *broadcast, char *gateway, char *server)
+{
+	int retVal = false;
+	int len = -1;
+	char buf[81];
+	char *ptr1 = NULL;
+	char *token = NULL;
+	
+	if(ip == NULL)
+		return 0;
+	
+	//try to open ip file
+	int fd = open("/jffs2/ip", O_RDONLY);
+	if(fd < 0)
+	{
+		ip[0] = '\0';
+		return 0;
+	}
+	//return ip address
+	if( (len = read(fd, buf, 80)) > 0)
+	{
+		buf[len] = '\0';
+		//get IP
+		token = strtok_r(buf, "_", &ptr1);
+		if(token != NULL)
+			strncpy(ip, token, 15);
+		else
+		{
+			close(fd);
+			return 0;
+		}
+		//get MASK
+		token = strtok_r(NULL, "_", &ptr1);
+		if(token != NULL)
+			strncpy(mask, token, 15);
+		else
+		{
+			close(fd);
+			return 0;
+		}
+		//get broadcast
+		token = strtok_r(NULL, "_", &ptr1);
+		if(token != NULL)
+			strncpy(broadcast, token, 15);
+		else
+		{
+			close(fd);
+			return 0;
+		}
+		//get gateway
+		token = strtok_r(NULL, "_", &ptr1);
+		if(token != NULL)
+			strncpy(gateway, token, 15);
+		else
+		{
+			close(fd);
+			return 0;
+		}
+		//get server
+		token = strtok_r(NULL, "_", &ptr1);
+		if(token != NULL)
+			strncpy(server, token, 15);
+		else
+		{
+			close(fd);
+			return 0;
+		}
+		
+		retVal = 1;
+	}
+	else
+	{
+		retVal = 0;
+		ip[0] = '\0';
+	}
+	return retVal;
+}
+
+//
+// Initialize network interface[s] using BOOTP/DHCP
+//
+void
+phi_init_all_network_interfaces(void)
+{
+    static volatile int in_init_all_network_interfaces = 0;
+
+#ifdef CYGOPT_NET_IPV6_ROUTING_THREAD
+    int rs_wait = 40;
+#endif
+
+    cyg_scheduler_lock();
+    while ( in_init_all_network_interfaces ) {
+        // Another thread is doing this...
+        cyg_scheduler_unlock();
+        cyg_thread_delay( 10 );
+        cyg_scheduler_lock();
+    }
+    in_init_all_network_interfaces = 1;
+    cyg_scheduler_unlock();
+
+#ifdef CYGHWR_NET_DRIVER_ETH0
+    if ( ! eth0_up ) { // Make this call idempotent
+		char ip[16], mask[16], broadcast[16], gateway[16], server[16];
+		if(!hasIP(ip, mask, broadcast, gateway, server))
+		{
+	        // Perform a complete initialization, using BOOTP/DHCP
+	        eth0_up = true;
+	        eth0_dhcpstate = 0; // Says that initialization is external to dhcp
+	        if (do_dhcp(eth0_name, &eth0_bootp_data, &eth0_dhcpstate, &eth0_lease))
+//	        { 
+//		        if (do_bootp(eth0_name, &eth0_bootp_data)) 
+        		{
+		            show_bootp(eth0_name, &eth0_bootp_data);
+        		} else {
+		            diag_printf("BOOTP/DHCP failed on eth0\n");
+        		    eth0_up = false;
+        		}
+//	        }
+		}
+		else
+		{
+
+	        eth0_up = true;
+	        build_bootp_record(&eth0_bootp_data,
+                           eth0_name,
+                           ip,
+                           mask,
+                           broadcast,
+                           gateway,
+                           server);
+	        show_bootp(eth0_name, &eth0_bootp_data);
+		}
+    }
+#endif // CYGHWR_NET_DRIVER_ETH0
+#ifdef CYGHWR_NET_DRIVER_ETH1
+    if ( ! eth1_up ) { // Make this call idempotent
+#ifdef CYGHWR_NET_DRIVER_ETH1_BOOTP
+        // Perform a complete initialization, using BOOTP/DHCP
+        eth1_up = true;
+#ifdef CYGHWR_NET_DRIVER_ETH1_DHCP
+        eth1_dhcpstate = 0; // Says that initialization is external to dhcp
+        if (do_dhcp(eth1_name, &eth1_bootp_data, &eth1_dhcpstate, &eth1_lease)) 
+#else
+#ifdef CYGPKG_NET_DHCP
+        eth1_dhcpstate = DHCPSTATE_BOOTP_FALLBACK;
+        // so the dhcp machine does no harm if called
+#endif
+        if (do_bootp(eth1_name, &eth1_bootp_data))
+#endif
+        {
+#ifdef CYGHWR_NET_DRIVER_ETH1_BOOTP_SHOW
+            show_bootp(eth1_name, &eth1_bootp_data);
+#endif
+        } else {
+            diag_printf("BOOTP/DHCP failed on eth1\n");
+            eth1_up = false;
+        }
+#elif defined(CYGHWR_NET_DRIVER_ETH1_ADDRS_IP)
+        eth1_up = true;
+        build_bootp_record(&eth1_bootp_data,
+                           eth1_name,
+                           string(CYGHWR_NET_DRIVER_ETH1_ADDRS_IP),
+                           string(CYGHWR_NET_DRIVER_ETH1_ADDRS_NETMASK),
+                           string(CYGHWR_NET_DRIVER_ETH1_ADDRS_BROADCAST),
+                           string(CYGHWR_NET_DRIVER_ETH1_ADDRS_GATEWAY),
+                           string(CYGHWR_NET_DRIVER_ETH1_ADDRS_SERVER));
+        show_bootp(eth1_name, &eth1_bootp_data);
+#endif
+    }
+#endif // CYGHWR_NET_DRIVER_ETH1
+#ifdef CYGHWR_NET_DRIVER_ETH0
+#ifndef CYGHWR_NET_DRIVER_ETH0_MANUAL
+    if (eth0_up) {
+        if (!init_net(eth0_name, &eth0_bootp_data)) {
+            diag_printf("Network initialization failed for eth0\n");
+            eth0_up = false;
+        }
+#ifdef CYGHWR_NET_DRIVER_ETH0_IPV6_PREFIX
+        if (!init_net_IPv6(eth0_name, &eth0_bootp_data, 
+                           string(CYGHWR_NET_DRIVER_ETH0_IPV6_PREFIX))) {
+            diag_printf("Static IPv6 network initialization failed for eth0\n");
+            eth0_up = false;  // ???
+        }
+#endif
+    }
+#endif
+#endif
+#ifdef CYGHWR_NET_DRIVER_ETH1
+#ifndef CYGHWR_NET_DRIVER_ETH1_MANUAL
+    if (eth1_up) {
+        if (!init_net(eth1_name, &eth1_bootp_data)) {
+            diag_printf("Network initialization failed for eth1\n");
+            eth1_up = false;
+        }
+#ifdef CYGHWR_NET_DRIVER_ETH1_IPV6_PREFIX
+        if (!init_net_IPv6(eth1_name, &eth1_bootp_data, 
+                           string(CYGHWR_NET_DRIVER_ETH1_IPV6_PREFIX))) {
+            diag_printf("Static IPv6 network initialization failed for eth1\n");
+            eth1_up = false; // ???
+        }
+#endif
+    }
+#endif
+#endif
+
+#ifdef CYGPKG_NET_NLOOP
+#if 0 < CYGPKG_NET_NLOOP
+    {
+        static int loop_init = 0;
+        int i;
+        if ( 0 == loop_init++ )
+            for ( i = 0; i < CYGPKG_NET_NLOOP; i++ )
+                init_loopback_interface( i );
+    }
+#endif
+#endif
+
+#ifdef CYGOPT_NET_DHCP_DHCP_THREAD
+    dhcp_start_dhcp_mgt_thread();
+#endif
+
+#ifdef CYGOPT_NET_IPV6_ROUTING_THREAD
+    ipv6_start_routing_thread();
+
+    // Wait for router solicit process to happen.
+    while (rs_wait-- && !cyg_net_get_ipv6_advrouter(NULL)) {
+      cyg_thread_delay(10);
+    }
+    if (rs_wait == 0 ) {
+      diag_printf("No router solicit received\n");
+    } else {
+      // Give Duplicate Address Detection time to work
+      cyg_thread_delay(200);
+    }
+#endif
+
+#ifdef CYGDAT_NS_DNS_DEFAULT_SERVER
+      cyg_dns_res_start(string(CYGDAT_NS_DNS_DEFAULT_SERVER));
+#endif
+
+#ifdef CYGDAT_NS_DNS_DOMAINNAME_NAME
+#define _NAME string(CYGDAT_NS_DNS_DOMAINNAME_NAME)
+    {
+      const char buf[] = _NAME;
+      int len = strlen(_NAME);
+      
+      setdomainname(buf,len);
+    }
+#endif
+    // Open the monitor to other threads.
+    in_init_all_network_interfaces = 0;
+
+}
+
+// EOF phi_network_support.c
diff --git a/zpu/sw/ecos/repository/pkgconf/rules.mak b/zpu/sw/ecos/repository/pkgconf/rules.mak
new file mode 100644
index 0000000..e043efa
--- /dev/null
+++ b/zpu/sw/ecos/repository/pkgconf/rules.mak
@@ -0,0 +1,210 @@
+#=============================================================================
+#
+#    rules.mak
+#
+#    Generic rules for inclusion by all package makefiles.
+#
+#=============================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+#=============================================================================
+#####DESCRIPTIONBEGIN####
+#
+# Author(s):     jld
+# Contributors:  bartv
+# Date:          1999-11-04
+# Purpose:       Generic rules for inclusion by all package makefiles
+# Description:   
+#
+#####DESCRIPTIONEND####
+#=============================================================================
+
+# FIXME: This definition belongs in the top-level makefile.
+export HOST_CC := gcc
+
+.PHONY: default build clean tests headers mlt_headers
+
+# include any dependency rules generated previously
+ifneq ($(wildcard *.deps),)
+include $(wildcard *.deps)
+endif
+
+# GCC since 2.95 does -finit-priority by default so remove it from old HALs
+CFLAGS := $(subst -finit-priority,,$(CFLAGS))
+
+# -fvtable-gc is known to be broken in all recent GCC.
+CFLAGS := $(subst -fvtable-gc,,$(CFLAGS))
+
+# To support more recent GCC whilst preserving existing behaviour, we need
+# to increase the inlining limit globally from the default 600. Note this
+# will break GCC 2.95 based tools and earlier. You must use "make OLDGCC=1"
+# to avoid this.
+ifneq ($(OLDGCC),1)
+CFLAGS := -finline-limit=7000 $(CFLAGS)
+endif
+
+# Separate C++ flags out from C flags.
+ACTUAL_CFLAGS = $(CFLAGS)
+ACTUAL_CFLAGS := $(subst -fno-rtti,,$(ACTUAL_CFLAGS))
+ACTUAL_CFLAGS := $(subst -frtti,,$(ACTUAL_CFLAGS))
+ACTUAL_CFLAGS := $(subst -Woverloaded-virtual,,$(ACTUAL_CFLAGS))
+ACTUAL_CFLAGS := $(subst -fvtable-gc,,$(ACTUAL_CFLAGS))
+
+ACTUAL_CXXFLAGS = $(subst -Wstrict-prototypes,,$(CFLAGS))
+
+# pattern matching rules to generate a library object from source code
+# object filenames are prefixed to avoid name clashes
+# a single dependency rule is generated (file extension = ".o.d")
+%.o.d : %.c
+ifeq ($(HOST),CYGWIN)
+	@mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+	@mkdir -p $(dir $@)
+endif
+	$(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $<
+	@sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@
+	@rm $(@:.o.d=.tmp)
+
+%.o.d : %.cxx
+ifeq ($(HOST),CYGWIN)
+	@mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+	@mkdir -p $(dir $@)
+endif
+	$(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $<
+	@sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@
+	@rm $(@:.o.d=.tmp)
+
+%.o.d : %.cpp
+ifeq ($(HOST),CYGWIN)
+	@mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+	@mkdir -p $(dir $@)
+endif
+	$(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $<
+	@sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@
+	@rm $(@:.o.d=.tmp)
+
+%.o.d : %.S
+ifeq ($(HOST),CYGWIN)
+	@mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+	@mkdir -p $(dir $@)
+endif	
+	$(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.o.d=.tmp) -o $(dir $@)$(OBJECT_PREFIX)_$(notdir $(@:.o.d=.o)) $<
+	@sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.o.d=.tmp) > $@
+	@rm $(@:.o.d=.tmp)
+
+# pattern matching rules to generate a test object from source code
+# object filenames are not prefixed
+# a single dependency rule is generated (file extension = ".d")
+%.d : %.c
+ifeq ($(HOST),CYGWIN)
+	@mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+	@mkdir -p $(dir $@)
+endif
+	$(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $<
+	@sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@
+	@rm $(@:.d=.tmp)
+
+%.d : %.cxx
+ifeq ($(HOST),CYGWIN)
+	@mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+	@mkdir -p $(dir $@)
+endif
+	$(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $<
+	@sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@
+	@rm $(@:.d=.tmp)
+
+%.d : %.cpp
+ifeq ($(HOST),CYGWIN)
+	@mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+	@mkdir -p $(dir $@)
+endif
+	$(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CXXFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $<
+	@sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@
+	@rm $(@:.d=.tmp)
+
+%.d : %.S
+ifeq ($(HOST),CYGWIN)
+	@mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+	@mkdir -p $(dir $@)
+endif	
+	$(CC) -c $(INCLUDE_PATH) -I$(dir $<) $(ACTUAL_CFLAGS) -Wp,-MD,$(@:.d=.tmp) -o $(@:.d=.o) $<
+	@sed -e '/^ *\\/d' -e "s#.*: #$@: #" $(@:.d=.tmp) > $@
+	@rm $(@:.d=.tmp)
+
+# rule to generate a test executable from object code
+$(PREFIX)/tests/$(PACKAGE)/%$(EXEEXT): %.d $(wildcard $(PREFIX)/lib/target.ld) $(wildcard $(PREFIX)/lib/*.[ao])
+ifeq ($(HOST),CYGWIN)
+	@mkdir -p `cygpath -w "$(dir $@)" | sed "s@\\\\\\\\@/@g"`
+else
+	@mkdir -p $(dir $@)
+endif	
+ifneq ($(IGNORE_LINK_ERRORS),)
+	-$(CC) -L$(PREFIX)/lib -Ttarget.ld -o $@ $(<:.d=.o) $(LDFLAGS)
+else
+	$(CC) -L$(PREFIX)/lib -Ttarget.ld -o $@ $(<:.d=.o) $(LDFLAGS) 
+endif
+
+# rule to generate all tests and create a dependency file "tests.deps" by
+# concatenating the individual dependency rule files (file extension = ".d")
+# generated during compilation
+tests: tests.stamp
+
+TESTS := $(TESTS:.cpp=)
+TESTS := $(TESTS:.cxx=)
+TESTS := $(TESTS:.c=)
+TESTS := $(TESTS:.S=)
+tests.stamp: $(foreach target,$(TESTS),$(target).d $(PREFIX)/tests/$(PACKAGE)/$(target)$(EXEEXT))
+ifneq ($(strip $(TESTS)),)
+	@cat $(TESTS:%=%.d) > $(@:.stamp=.deps)
+endif
+	@touch $@
+
+# rule to clean the build tree
+clean:
+	@find . -type f -print | grep -v makefile | xargs rm -f
+
+# rule to copy MLT files
+mlt_headers: $(foreach x,$(MLT),$(PREFIX)/include/pkgconf/$(notdir $x))
+
+$(foreach x,$(MLT),$(PREFIX)/include/pkgconf/$(notdir $x)): $(MLT)
+	@cp $(dir $<)/$(notdir $@) $(PREFIX)/include/pkgconf
+	@chmod u+w $(PREFIX)/include/pkgconf/$(notdir $@)
+
+# end of file
-- 
cgit v1.1


From e9b757cdba91ceb77523f5d9bb092b8c723fabbb Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Thu, 8 May 2008 07:32:52 +0000
Subject: Mike Frysinger found this file which is not needed.

---
 zpu/sw/simulator/gmon.out | Bin 120053 -> 0 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 zpu/sw/simulator/gmon.out

(limited to 'zpu/sw')

diff --git a/zpu/sw/simulator/gmon.out b/zpu/sw/simulator/gmon.out
deleted file mode 100644
index c49b3d7..0000000
Binary files a/zpu/sw/simulator/gmon.out and /dev/null differ
-- 
cgit v1.1


From 431a1bf775d468bcd788c3dd716b97cc0fca1f34 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Mon, 18 Aug 2008 12:00:34 +0000
Subject: 	* duplicated crt0.s and some other stuff from libgloss into 
 sw/startup. This makes it easier to tinker w/startup code.

---
 zpu/sw/startup/crt0.S   | 957 ++++++++++++++++++++++++++++++++++++++++++++++++
 zpu/sw/startup/crt_io.c |  91 +++++
 zpu/sw/startup/time.c   |  32 ++
 3 files changed, 1080 insertions(+)
 create mode 100644 zpu/sw/startup/crt0.S
 create mode 100644 zpu/sw/startup/crt_io.c
 create mode 100644 zpu/sw/startup/time.c

(limited to 'zpu/sw')

diff --git a/zpu/sw/startup/crt0.S b/zpu/sw/startup/crt0.S
new file mode 100644
index 0000000..00870c4
--- /dev/null
+++ b/zpu/sw/startup/crt0.S
@@ -0,0 +1,957 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"crt0.S"
+	
+	
+	
+	
+;	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+; DANGER!!!! 
+; we need to align these code sections to 32 bytes, which
+; means we must not use any assembler instructions that are relaxed
+; at linker time
+; DANGER!!!! 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jsr address
+	
+			im 0		; save R0
+			load
+			im 4		; save R1
+			load
+			im 8		; save R2
+			load
+	
+			fixedim \address
+			call
+			
+			im 8
+			store		; restore R2
+			im 4
+			store		; restore R1
+			im 0
+			store		; restore R0
+	.endm
+
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+		
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+	
+	.macro cimpl funcname
+	; save R0
+	im 0
+	load
+	
+	; save R1
+	im 4
+	load
+	
+	; save R2
+	im 8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im 0
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im 8
+	store
+	
+	; restore R1
+	im 4
+	store
+	
+	; restore r0
+	im 0
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+
+
+/* vectors */
+        .balign 32,0
+# offset 0x0000 0000
+		.globl _start
+_start:
+		; intSp must be 0 when we jump to _premain
+		
+		im ZPU_ID
+		loadsp 0
+		im _cpu_config
+		store
+		config
+		jmp _premain
+
+
+
+        .balign 32,0
+# offset 0x0000 0020
+		.globl _zpu_interrupt_vector
+_zpu_interrupt_vector:
+		jsr _zpu_interrupt
+		poppc
+
+
+/* instruction emulation code */
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	cimpl __divsi3
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	cimpl __modsi3
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+	
+	.data
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
diff --git a/zpu/sw/startup/crt_io.c b/zpu/sw/startup/crt_io.c
new file mode 100644
index 0000000..966ae33
--- /dev/null
+++ b/zpu/sw/startup/crt_io.c
@@ -0,0 +1,91 @@
+#include <syscall.h>
+#include <stdio.h>
+#include <errno.h>
+#include <sys/stat.h>
+
+extern int _hardware;
+/* _cpu_config==0 => Abel
+ * _cpu_config==1 => Zeta
+ * _cpu_config==2 => Phi
+ */
+extern int _cpu_config;
+static volatile int *UART;
+static volatile int *TIMER;
+volatile int *MHZ;
+
+
+
+/*
+ * Wait indefinitely for input byte
+ */
+
+
+int __attribute__ ((weak)) inbyte()  
+{
+	int val;
+	for (;;)
+	{
+		val=UART[1];
+		if ((val&0x100)!=0)
+		{
+			return val&0xff;
+		}
+	}
+}
+
+
+
+/* 
+ * Output one character to the serial port 
+ * 
+ * 
+ */
+void __attribute__ ((weak)) outbyte(int c)  
+{
+	/* Wait for space in FIFO */
+	while ((UART[0]&0x100)==0);
+	UART[0]=c;
+}
+
+static const int mhz=64;
+
+void __attribute__ ((weak)) _initIO(void)  
+{
+	if (_hardware)
+	{
+		if (_cpu_config==2)
+		{
+			/* Phi board addresses */
+			UART=(volatile int *)0x080a000c;
+			TIMER=(volatile int *)0x080a0014; 
+			MHZ=(volatile int *)&mhz; 
+		} else 
+		{
+			/* Abel board */
+			UART=(volatile int *)0xc000;
+			TIMER=(volatile int *)0x9000;
+			MHZ=(volatile int *)0x8800;
+		}
+	} else
+	{
+		UART=(volatile int *)0x80000024;
+		TIMER=(volatile int *)0x80000100;
+		MHZ=(volatile int *)0x80000200;
+	}
+}
+
+
+
+long long __attribute__ ((weak)) _readCycles()  
+{
+	long long clock;
+	unsigned int i;
+	
+	TIMER[0]=0x2; /* sample timer */
+	clock=0;
+	for (i=0; i<2; i++)
+	{
+		clock|=((long long )(TIMER[i]))<<(i*32);
+	}
+	return clock;
+}
diff --git a/zpu/sw/startup/time.c b/zpu/sw/startup/time.c
new file mode 100644
index 0000000..767b62f
--- /dev/null
+++ b/zpu/sw/startup/time.c
@@ -0,0 +1,32 @@
+#include <_ansi.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+extern long long _readCycles();
+
+
+extern volatile int *MHZ;
+
+long long _readMicroseconds()
+{
+	int Hz;
+	long long clock;
+	Hz=(*MHZ&0xff);
+	clock=_readCycles();
+	return clock/(long long)Hz;
+}
+
+
+
+
+time_t
+time (time_t *tloc)
+{
+	time_t t;
+	t=(time_t)(_readMicroseconds()/(long long )1000000);
+	if (tloc!=NULL)
+	{
+		*tloc=t;
+	}
+	return t;
+}
-- 
cgit v1.1


From 7792f314b6b259b9d5088337dad4c9e8519ce095 Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Mon, 18 Aug 2008 12:28:59 +0000
Subject: very early work.

---
 zpu/sw/startup/nextgen_crt0.S | 894 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 894 insertions(+)
 create mode 100644 zpu/sw/startup/nextgen_crt0.S

(limited to 'zpu/sw')

diff --git a/zpu/sw/startup/nextgen_crt0.S b/zpu/sw/startup/nextgen_crt0.S
new file mode 100644
index 0000000..3cf9112
--- /dev/null
+++ b/zpu/sw/startup/nextgen_crt0.S
@@ -0,0 +1,894 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"crt0.S"
+	
+	.section ".fixed_vectors","ax"
+
+
+
+	
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+	
+	.macro cimpl funcname
+	; save R0
+	im 0
+	load
+	
+	; save R1
+	im 4
+	load
+	
+	; save R2
+	im 8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im 0
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im 8
+	store
+	
+	; restore R1
+	im 4
+	store
+	
+	; restore r0
+	im 0
+	store
+	
+	storesp 4
+	poppc
+	.endm
+
+
+
+
+/* vectors */
+        .balign 32,0
+# offset 0x0000 0000
+		.globl _start
+_start:
+		im _premain
+		poppc
+
+        .balign 16,0
+# offset 0x0000 0010
+		.globl _zpu_unknown_instruction_vector
+_zpu_unknown_instruction:
+		/* We have unsupported instruction * 4 on stack */
+		im _emulate_table
+		add
+		load
+		poppc
+
+	.rodata
+	.balign 4,0
+_emulate_table:
+	.long	_storeh
+	.long ...
+
+/* instruction emulation code */
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	cimpl __divsi3
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	cimpl __modsi3
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+	
+	.data
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
+; Pointers to emulated instructions
-- 
cgit v1.1


From 952bcd56f3b4e412594920ef02d9d740b3ce119a Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Thu, 21 Aug 2008 21:12:57 +0000
Subject: merging in some docs to zpu_arch.html

---
 zpu/sw/helloworld/gccgdb.PNG | Bin 34473 -> 0 bytes
 zpu/sw/helloworld/zpusim.PNG | Bin 17817 -> 0 bytes
 zpu/sw/index.html            |  44 -------------------------------------------
 3 files changed, 44 deletions(-)
 delete mode 100644 zpu/sw/helloworld/gccgdb.PNG
 delete mode 100644 zpu/sw/helloworld/zpusim.PNG
 delete mode 100644 zpu/sw/index.html

(limited to 'zpu/sw')

diff --git a/zpu/sw/helloworld/gccgdb.PNG b/zpu/sw/helloworld/gccgdb.PNG
deleted file mode 100644
index afdfc31..0000000
Binary files a/zpu/sw/helloworld/gccgdb.PNG and /dev/null differ
diff --git a/zpu/sw/helloworld/zpusim.PNG b/zpu/sw/helloworld/zpusim.PNG
deleted file mode 100644
index d8fc277..0000000
Binary files a/zpu/sw/helloworld/zpusim.PNG and /dev/null differ
diff --git a/zpu/sw/index.html b/zpu/sw/index.html
deleted file mode 100644
index fd0a1b4..0000000
--- a/zpu/sw/index.html
+++ /dev/null
@@ -1,44 +0,0 @@
-<html>
-<body>
-<h1>Getting started - a ZPU hello world program</h1>
-The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has 
-some very basic peripherals defined: counter, timer interrupt and a debug output port. 
-<h2>Installing</h2>
-<ol>
-<li>Install Cygwin. http://www.cygwin.com 
-<li>Install Java
-<li>Start Cygwin bash
-<li>cd zpu/sw
-<li>sh setup.sh
-<li>/tmp/zpu/install/bin now has the .exe files for the GCC toolchain & GDB
-<li>Optionally you may set up PATH variables to point to /tmp/zpu/install/bin<br>
-source env.sh
-</ol>
-<h1>Hello world example</h1>
-The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification.
-<p> 
-<code>
-cd zpu/sw/helloworld<br>
-../install/bin/zpu-elf-gcc -phi hello.c -o hello.elf <br>
-</code>
-<h2>Running the hello world example in GDB</h2>
-<ol>
-<li>cd zpu/sw/helloworld
-<li>Launch the simulator from a seperate bash shell:<p>
-java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444
-<p>
-<img src="helloworld/zpusim.PNG" border=0> 
-<li>Launch GDB:<p>
-../install/bin/zpu-elf-gdb hello.elf
-<li>Connect to target, load and run application:<p>
-<code>
-(gdb) target remote localhost:4444<br>
-(gdb) load<br>
-(gdb) continue<br>
-</code>
-<p>
-<img src="helloworld/gccgdb.PNG">
-
-
-</body>
-</html>
-- 
cgit v1.1


From 879f385d7ae2bcef98f1970aba872235e940776b Mon Sep 17 00:00:00 2001
From: Antonio Anton <antonio.anton@anro-ingenieros.com>
Date: Mon, 14 Sep 2009 08:34:41 +0200
Subject: FreeRTOS port

---
 zpu/sw/freertos/port/port.c             | 271 ++++++++++++++++++++++++++++++++
 zpu/sw/freertos/port/portasm.s          | 142 +++++++++++++++++
 zpu/sw/freertos/port/portmacro.h        | 125 +++++++++++++++
 zpu/sw/freertos/readme.txt              |  40 +++++
 zpu/sw/freertos/sample/FreeRTOSConfig.h |  96 +++++++++++
 zpu/sw/freertos/sample/Makefile         |  50 ++++++
 zpu/sw/freertos/sample/test1.c          |  67 ++++++++
 7 files changed, 791 insertions(+)
 create mode 100644 zpu/sw/freertos/port/port.c
 create mode 100644 zpu/sw/freertos/port/portasm.s
 create mode 100644 zpu/sw/freertos/port/portmacro.h
 create mode 100644 zpu/sw/freertos/readme.txt
 create mode 100644 zpu/sw/freertos/sample/FreeRTOSConfig.h
 create mode 100644 zpu/sw/freertos/sample/Makefile
 create mode 100644 zpu/sw/freertos/sample/test1.c

(limited to 'zpu/sw')

diff --git a/zpu/sw/freertos/port/port.c b/zpu/sw/freertos/port/port.c
new file mode 100644
index 0000000..ff243ee
--- /dev/null
+++ b/zpu/sw/freertos/port/port.c
@@ -0,0 +1,271 @@
+/*
+	FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify it
+	under the terms of the GNU General Public License (version 2) as published
+	by the Free Software Foundation and modified by the FreeRTOS exception.
+	**NOTE** The exception to the GPL is included to allow you to distribute a
+	combined work that includes FreeRTOS.org without being obliged to provide
+	the source code for any proprietary components.  Alternative commercial
+	license and support terms are also available upon request.  See the 
+	licensing section of http://www.FreeRTOS.org for full details.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,	but WITHOUT
+	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+	FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+	more details.
+
+	You should have received a copy of the GNU General Public License along
+	with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
+	Temple Place, Suite 330, Boston, MA  02111-1307  USA.
+
+
+	***************************************************************************
+	*                                                                         *
+	* Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
+	*                                                                         *
+	* This is a concise, step by step, 'hands on' guide that describes both   *
+	* general multitasking concepts and FreeRTOS specifics. It presents and   *
+	* explains numerous examples that are written using the FreeRTOS API.     *
+	* Full source code for all the examples is provided in an accompanying    *
+	* .zip file.                                                              *
+	*                                                                         *
+	***************************************************************************
+
+	1 tab == 4 spaces!
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting,
+	licensing and training services.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <string.h>
+
+/* hardware/software platform specific defines */
+#define DISABLE_C_PROTOTYPES
+#include <devices.h>
+
+/* Tasks are started with interrupts enabled. */
+#define portINITIAL_INTERRUPT_ENABLE	( ( portSTACK_TYPE ) INTERRUPT_GLOBAL_ENABLE )
+
+/* Tasks are started with a critical section nesting of 0 - however prior
+to the scheduler being commenced we don't want the critical nesting level
+to reach zero, so it is initialised to a high value. */
+#define portINITIAL_NESTING_VALUE	( 0xff )
+
+/* The stack used by the ISR is filled with a known value to assist in
+debugging. */
+#define portISR_STACK_FILL_VALUE	0x55555555
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task 
+maintains it's own count, so this variable is saved as part of the task
+context. */
+volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* To limit the amount of stack required by each task, this port uses a
+separate stack for interrupts. */
+unsigned portLONG *pulISRStack;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been made.
+ * 
+ * See the header file portable.h.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
+{
+	/* Function call parameters. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;
+
+	/* Place initial PC (task entry point) */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) pxCode;	/* PC */
+
+	/* Place initial value for INTERRUPT global ENABLE */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_INTERRUPT_ENABLE;	/* interrupt state (global enable) */
+	
+	/* Stack an initial value for the critical section nesting.  This
+	is initialised to zero as tasks are started with interrupts enabled. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x00;
+
+	/* Place an initial value for all temporary registers mapped to mem[0..16] by gcc */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;	/* mem[0] */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x22222222;	/* mem[4] */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x33333333;	/* mem[8] */
+	pxTopOfStack--;
+	*pxTopOfStack = ( portSTACK_TYPE ) 0x44444444;	/* mem[12] */
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+extern void ( __FreeRTOS_interrupt_handler )( void );
+extern void ( vStartFirstTask )( void );
+
+	/* Setup the FreeRTOS interrupt handler */
+	*(volatile unsigned *) INTERRUPT_VECTOR = (unsigned) __FreeRTOS_interrupt_handler;
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Allocate the stack to be used by the interrupt handler. */
+	pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
+
+	/* Restore the context of the first task that is going to run. */
+	if( pulISRStack != NULL )
+	{
+		/* Fill the ISR stack with a known value to facilitate debugging. */
+		memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
+		pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
+
+		/* Kick off the first task. */
+		vStartFirstTask();
+	}
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.  
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+	/* Perform the context switch in a critical section to assure it is
+	not interrupted by the tick ISR.  It is not a problem to do this as
+	each task maintains it's own interrupt status. */
+	portENTER_CRITICAL();
+		/* Jump directly to the yield function to ensure there is no
+		compiler generated prologue code. */
+		asm volatile (	"im VPortYieldASM		\n\t" \
+						"call					\n\t" );
+	portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.   
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Initialize and start timer1 counter */
+	*(volatile unsigned *) TIMER1_PORT = ulCounterValue;
+	*(volatile unsigned *) TIMERS_CONTROL = TIMER1_ENABLE;
+	
+	/* Enable timer1 interrupt while maintaining other bit states
+	   but disable global enable */
+	*(volatile unsigned *) INTERRUPT_ENABLE &= ~INTERRUPT_GLOBAL_ENABLE;
+	*(volatile unsigned *) INTERRUPT_ENABLE |= INTERRUPT_TIMER1;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt handler placed in the interrupt vector when the scheduler is
+ * started.  The task context has already been saved when this is called.
+ * This handler determines the interrupt source and calls the relevant 
+ * peripheral handler.
+ */
+void vTaskISRHandler( void )
+{
+void vTickISR(void);
+
+	unsigned int_status = *(volatile unsigned *) INTERRUPT_STATUS;
+	if(int_status & INTERRUPT_TIMER1)	vTickISR();
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * Handler for the timer interrupt.
+ */
+void vTickISR( void )
+{
+	/* Increment the RTOS tick - this might cause a task to unblock. */
+	vTaskIncrementTick();
+
+	/* Clear the timer interrupt */
+	/* ... in this platform, timer interrupt is cleared automatically */
+
+	/* If we are using the preemptive scheduler then we also need to determine
+	if this tick should cause a context switch. */
+	#if configUSE_PREEMPTION == 1
+		vTaskSwitchContext();
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void zpu_disable_interrupts(void)
+{	
+	*(volatile unsigned *) INTERRUPT_ENABLE &= ~INTERRUPT_GLOBAL_ENABLE;
+}
+
+void zpu_enable_interrupts(void)
+{
+	*(volatile unsigned *) INTERRUPT_ENABLE |= INTERRUPT_GLOBAL_ENABLE;
+}
+
+/*-----------------------------------------------------------*/
+
+void zpu_enter_critical(void)
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+}
+									
+void zpu_exit_critical(void)
+{	
+	if( --uxCriticalNesting == 0 )
+	{
+  	  portENABLE_INTERRUPTS();
+  	}
+}
diff --git a/zpu/sw/freertos/port/portasm.s b/zpu/sw/freertos/port/portasm.s
new file mode 100644
index 0000000..29c41ab
--- /dev/null
+++ b/zpu/sw/freertos/port/portasm.s
@@ -0,0 +1,142 @@
+	.extern pxCurrentTCB
+	.extern vTaskISRHandler
+	.extern vTaskSwitchContext
+	.extern uxCriticalNesting
+	.extern pulISRStack
+
+	.global __FreeRTOS_interrupt_handler
+	.global VPortYieldASM
+	.global vStartFirstTask
+
+/* interrupt controller port */
+	.equ INTERRUPT_ENABLE,0x8020
+
+.macro portSAVE_CONTEXT
+	/* PC is at the top of stack */
+	
+	/* store interrupt global enable bit */
+	im INTERRUPT_ENABLE
+	load
+	im 1
+	and
+	
+	/* Store nesting critical level */
+	im uxCriticalNesting
+	load
+	
+	/* Store temporary registers */
+	im 0
+	load			/* store mem[0] */
+	im 4
+	load			/* store mem[4] */
+	im 8
+	load			/* store mem[8] */
+	im 12
+	load			/* store mem[12] */
+	
+	/* Store top of stack at pxCurrentTCB */
+	pushsp
+	im pxCurrentTCB
+	load
+	store
+.endm
+
+.macro portRESTORE_CONTEXT
+	im pxCurrentTCB		/* Load the top of stack value from the TCB. */
+	load
+	load
+	popsp
+	
+	/* Restore the temporary registers. */
+	im 12
+	store				/* restore mem[12] */
+	im 8
+	store				/* restore mem[8] */
+	im 4
+	store				/* restore mem[4] */
+	im 0
+	store				/* restore mem[0] */
+
+	/* Load the critical nesting value. */
+	im uxCriticalNesting
+	store
+
+	/* Set interrupt global enable status */
+	im INTERRUPT_ENABLE
+	load
+	im ~1
+	and
+	or
+	im INTERRUPT_ENABLE
+	store
+
+	/* restore PC and enable interrupts at ZPU level */
+	.byte 0x03			/* popint */
+.endm
+
+.macro portRESTORE_CONTEXT_NOINTERRUPT
+	im pxCurrentTCB		/* Load the top of stack value from the TCB. */
+	load
+	load
+	popsp
+	
+	/* Restore the temporary registers. */
+	im 12
+	store				/* restore mem[12] */
+	im 8
+	store				/* restore mem[8] */
+	im 4
+	store				/* restore mem[4] */
+	im 0
+	store				/* restore mem[0] */
+
+	/* Load the critical nesting value. */
+	im uxCriticalNesting
+	store
+
+	/* Set interrupt global enable status */
+	im INTERRUPT_ENABLE
+	load
+	im ~1
+	and
+	or
+	im INTERRUPT_ENABLE
+	store
+
+	/* restore PC */
+	poppc
+.endm
+
+	.text
+	.align  2
+
+__FreeRTOS_interrupt_handler:
+	portSAVE_CONTEXT
+
+	/* Now switch to use the ISR stack. */
+	im pulISRStack
+	load
+	popsp
+
+	/* Call function */
+	im vTaskISRHandler
+	call
+
+	portRESTORE_CONTEXT
+
+VPortYieldASM:
+	portSAVE_CONTEXT
+
+	/* Now switch to use the ISR stack. */
+	im pulISRStack
+	load
+	popsp
+
+	/* Call function to switch context */
+	im vTaskSwitchContext
+	call
+
+	portRESTORE_CONTEXT_NOINTERRUPT
+
+vStartFirstTask:
+	portRESTORE_CONTEXT_NOINTERRUPT
diff --git a/zpu/sw/freertos/port/portmacro.h b/zpu/sw/freertos/port/portmacro.h
new file mode 100644
index 0000000..2b4d35a
--- /dev/null
+++ b/zpu/sw/freertos/port/portmacro.h
@@ -0,0 +1,125 @@
+/*
+	FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify it
+	under the terms of the GNU General Public License (version 2) as published
+	by the Free Software Foundation and modified by the FreeRTOS exception.
+	**NOTE** The exception to the GPL is included to allow you to distribute a
+	combined work that includes FreeRTOS.org without being obliged to provide
+	the source code for any proprietary components.  Alternative commercial
+	license and support terms are also available upon request.  See the 
+	licensing section of http://www.FreeRTOS.org for full details.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,	but WITHOUT
+	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+	FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+	more details.
+
+	You should have received a copy of the GNU General Public License along
+	with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
+	Temple Place, Suite 330, Boston, MA  02111-1307  USA.
+
+
+	***************************************************************************
+	*                                                                         *
+	* Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
+	*                                                                         *
+	* This is a concise, step by step, 'hands on' guide that describes both   *
+	* general multitasking concepts and FreeRTOS specifics. It presents and   *
+	* explains numerous examples that are written using the FreeRTOS API.     *
+	* Full source code for all the examples is provided in an accompanying    *
+	* .zip file.                                                              *
+	*                                                                         *
+	***************************************************************************
+
+	1 tab == 4 spaces!
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting,
+	licensing and training services.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.  
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned portLONG
+#define portBASE_TYPE	portLONG
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned portSHORT portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffff
+#else
+	typedef unsigned portLONG portTickType;
+	#define portMAX_DELAY ( portTickType ) 0xffffffff
+#endif
+/*-----------------------------------------------------------*/	
+
+/* Interrupt control macros. */
+void zpu_disable_interrupts(void);
+void zpu_enable_interrupts(void);
+#define portDISABLE_INTERRUPTS()	zpu_disable_interrupts()
+#define portENABLE_INTERRUPTS()		zpu_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void zpu_enter_critical(void);
+void zpu_exit_critical(void);
+#define portENTER_CRITICAL()		zpu_enter_critical()
+#define portEXIT_CRITICAL()			zpu_exit_critical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() 				vPortYield()
+
+void vTaskSwitchContext();
+#define portYIELD_FROM_ISR() 		vTaskSwitchContext()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_RATE_MS			( ( portTickType ) 1000 / configTICK_RATE_HZ )		
+#define portNOP()					asm volatile ( "nop\n" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/zpu/sw/freertos/readme.txt b/zpu/sw/freertos/readme.txt
new file mode 100644
index 0000000..a1f1c89
--- /dev/null
+++ b/zpu/sw/freertos/readme.txt
@@ -0,0 +1,40 @@
+The FreeRTOS port was contributed by
+Antonio Anton <antonio.anton@anro-ingenieros.com>.
+
+Some of the files state that someone else is copyright
+holder, but I believe that to be copy and paste laziness
+and that, in fact, Antonio did this port.
+
+The port needs work, but is committed to ZPU git repository
+to get things started.
+
+Post questions to the zylin-zpu mailing list.
+
+Øyvind Harboe
+14/9-2009
+
+From Antonio:
+
+Ported version: 5.3.0
+Port goes to folder ${FREERTOS_ROOT}/Source/portable/GCC/ZPU
+
+portmacro.h : macro definitions for this port
+portasm.s   : contains code for context switch, interrupt handler and
+other initializations
+port.c      : other initialization functions that not need to be
+assembly code.
+
+(please note that #include <device.h> in port.c is specific for my ZPU
+port; it contains the definitions my peripherals)
+
+Each FreeRTOS application is compiled with the FreeRTOS port itself
+(source code).
+
+2nd file contains a sample application which includes the Makefile in
+order to compile & link against FreeRTOS port. It will link against some
+specific library (-lio) and specific linker file (sram-zpu.ld) which are
+not included. You must adapt these to your peripheral and memory
+configuration.
+
+At the moment there is no documentation but the source code is quite
+commented.
diff --git a/zpu/sw/freertos/sample/FreeRTOSConfig.h b/zpu/sw/freertos/sample/FreeRTOSConfig.h
new file mode 100644
index 0000000..d9470fd
--- /dev/null
+++ b/zpu/sw/freertos/sample/FreeRTOSConfig.h
@@ -0,0 +1,96 @@
+/*
+	FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
+
+	This file is part of the FreeRTOS.org distribution.
+
+	FreeRTOS.org is free software; you can redistribute it and/or modify it
+	under the terms of the GNU General Public License (version 2) as published
+	by the Free Software Foundation and modified by the FreeRTOS exception.
+	**NOTE** The exception to the GPL is included to allow you to distribute a
+	combined work that includes FreeRTOS.org without being obliged to provide
+	the source code for any proprietary components.  Alternative commercial
+	license and support terms are also available upon request.  See the 
+	licensing section of http://www.FreeRTOS.org for full details.
+
+	FreeRTOS.org is distributed in the hope that it will be useful,	but WITHOUT
+	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+	FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+	more details.
+
+	You should have received a copy of the GNU General Public License along
+	with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
+	Temple Place, Suite 330, Boston, MA  02111-1307  USA.
+
+
+	***************************************************************************
+	*                                                                         *
+	* Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
+	*                                                                         *
+	* This is a concise, step by step, 'hands on' guide that describes both   *
+	* general multitasking concepts and FreeRTOS specifics. It presents and   *
+	* explains numerous examples that are written using the FreeRTOS API.     *
+	* Full source code for all the examples is provided in an accompanying    *
+	* .zip file.                                                              *
+	*                                                                         *
+	***************************************************************************
+
+	1 tab == 4 spaces!
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	http://www.FreeRTOS.org - Documentation, latest information, license and
+	contact details.
+
+	http://www.SafeRTOS.com - A version that is certified for use in safety
+	critical systems.
+
+	http://www.OpenRTOS.com - Commercial support, development, porting,
+	licensing and training services.
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned portLONG ) 25000000 )
+#define configTICK_RATE_HZ			( ( portTickType ) 100 )
+#define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 4 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned portLONG ) 256 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 8 * 1024 ) )
+#define configMAX_TASK_NAME_LEN		( 5 )
+#define configUSE_TRACE_FACILITY	0
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				0
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/zpu/sw/freertos/sample/Makefile b/zpu/sw/freertos/sample/Makefile
new file mode 100644
index 0000000..d3a6f6f
--- /dev/null
+++ b/zpu/sw/freertos/sample/Makefile
@@ -0,0 +1,50 @@
+PRJ      =  test1
+PATH_SW  =  /home/antonan/desarrollo/zpu/sw
+INCLUDES =  $(PATH_SW)/freertos/Source/portable/GCC/ZPU/portmacro.h \
+		 	FreeRTOSConfig.h
+SRCS_C   =  $(PATH_SW)/freertos/Source/portable/GCC/ZPU/port.c \
+			$(PATH_SW)/freertos/Source/portable/MemMang/heap_1.c \
+		    $(PATH_SW)/freertos/Source/croutine.c \
+			$(PATH_SW)/freertos/Source/list.c \
+			$(PATH_SW)/freertos/Source/queue.c \
+			$(PATH_SW)/freertos/Source/tasks.c \
+			test1.c
+SRCS_ASM =  $(PATH_SW)/freertos/Source/portable/GCC/ZPU/portasm.s
+PATH_INC = -I$(PATH_SW)/include \
+		   -I$(PATH_SW)/freertos/Source/include \
+		   -I$(PATH_SW)/freertos/Source/portable/GCC/ZPU \
+		   -I$(PATH_SW)/freertos/Demo/ZPU \
+		   -I.
+OPTIONS  = -g -Os -DGCC_ZPU 
+LINK 	 = -T $(PATH_SW)/ldscripts/zpu-sram.ld
+CRT      =  $(PATH_SW)/startup/crt-sram.o
+LLIB     = -L $(PATH_SW)/lib
+LIBS     = -lio -lgcc --start-group -lc -lbcc --end-group -lgcc -lio
+LFLAGS   = --relax --gc-sections
+
+OBJS_ASM = $(SRCS_ASM:.s=.o)
+OBJS_C   = $(SRCS_C:.c=.o)
+
+$(PRJ).srec: $(PRJ).out
+	zpu-elf-objcopy -O srec $(PRJ).out $(PRJ).srec
+	zpu-elf-objcopy -O binary $(PRJ).out $(PRJ).bin
+	bin2rom $(PRJ).bin $(PRJ).rom
+
+$(OBJS_ASM): $(SRCS_ASM)
+	zpu-elf-gcc $(OPTIONS) $(PATH_INC) -B. -c -Wa,-ahlms=$(@:.o=.lst) -o $@ $(@:.o=.s)
+
+$(OBJS_C): $(SRCS_C) $(INCLUDES)
+	zpu-elf-gcc $(OPTIONS) $(PATH_INC) -B. -c -Wa,-ahlms=$(@:.o=.lst) -o $@ $(@:.o=.c)
+
+$(PRJ).out: $(CRT) $(OBJS_C) $(OBJS_ASM)
+	zpu-elf-ld $(LLIB) $(LFLAGS) $(LINK) -Map=$(PRJ).map -o $(PRJ).out $(CRT) $(OBJS_C) $(OBJS_ASM) $(LIBS)
+
+
+clean:
+	-rm *.o
+	-rm *.out
+	-rm *.bin
+	-rm *.map
+	-rm *.lst
+	-rm *.srec
+	-rm *.rom
diff --git a/zpu/sw/freertos/sample/test1.c b/zpu/sw/freertos/sample/test1.c
new file mode 100644
index 0000000..41b4296
--- /dev/null
+++ b/zpu/sw/freertos/sample/test1.c
@@ -0,0 +1,67 @@
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "devices.h"
+
+#define mainTINY_STACK	256
+void vTest(void *pvParameters);
+void vTest2(void *pvParameters);
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Create all the demo tasks - then start the scheduler.
+ */
+int main (void) 
+{
+	/* When re-starting a debug session (rather than cold booting) we want
+	to ensure the installed interrupt handlers do not execute until after the
+	scheduler has been started. */
+	portDISABLE_INTERRUPTS();
+
+	#if configUSE_PREEMPTION == 1
+		xTaskCreate( vTest, "TST1", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL );
+		xTaskCreate( vTest2, "TST2", mainTINY_STACK, ( void * ) 10, tskIDLE_PRIORITY, NULL );
+	#endif
+
+	/* Finally start the scheduler. */
+	vTaskStartScheduler();
+
+	/* Should not get here as the processor is now under control of the 
+	scheduler! */
+
+   	return 0;
+}
+
+void vTest(void *pvParameters)
+{
+const portTickType xDelay = 100 / portTICK_RATE_MS;
+	unsigned bit = 16;
+	unsigned dir = 0;   
+	
+	for(;;)
+	{
+		CLEAR_BIT(SP3SK_GPIO, bit);
+		if(dir == 0) { if(++bit == 23) { dir=1; } }
+		else { if(--bit == 16) { dir=0;} }
+		SET_BIT(SP3SK_GPIO, bit);
+		vTaskDelay( xDelay );
+	}
+}
+
+void vTest2(void *pvParameters)
+{
+const portTickType xDelay = 250 / portTICK_RATE_MS;
+	unsigned pos;
+	char marcas[] = "|/-\\";
+	
+	for(;;)
+	{
+		uart1_printline("\r");
+		uart1_printline("Running...");
+		uart1_printchar(marcas[pos]);
+		if(++pos == 4) pos = 0;
+		vTaskDelay( xDelay );
+	}
+}
-- 
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