From f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 2 Jan 2008 21:52:27 +0000 Subject: Initial import from www.ecosforge.net --- zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd | 31 + zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd | 213 ++ .../dummyfpgalib/ddrsdram/simscripts/ddr_tb.do | 17 + .../dummyfpgalib/ddrsdram/simscripts/ddr_top.do | 111 + zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd | 90 + zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd | 301 ++ zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd | 660 ++++ .../zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd | 1320 +++++++ zpu/hdl/zpu4/src/.cvsignore | 5 + zpu/hdl/zpu4/src/bram.vhd | 3807 ++++++++++++++++++++ zpu/hdl/zpu4/src/bram_dmips.vhd | 3717 +++++++++++++++++++ zpu/hdl/zpu4/src/build.xml | 114 + zpu/hdl/zpu4/src/clocks.vhd | 246 ++ zpu/hdl/zpu4/src/dmipssmalltrace.do | 26 + zpu/hdl/zpu4/src/dmipstrace.do | 25 + zpu/hdl/zpu4/src/dmipstraceintstack.do | 25 + zpu/hdl/zpu4/src/dram_dmips.vhd | 3702 +++++++++++++++++++ zpu/hdl/zpu4/src/dram_hello.vhd | 3214 +++++++++++++++++ zpu/hdl/zpu4/src/fastdmips.do | 19 + zpu/hdl/zpu4/src/fastdmipsintstack.do | 19 + zpu/hdl/zpu4/src/fastdmipssmall.do | 21 + zpu/hdl/zpu4/src/fastsimzpu.do | 19 + zpu/hdl/zpu4/src/ic300.bitgen | 27 + zpu/hdl/zpu4/src/ic300.lso | 1 + zpu/hdl/zpu4/src/ic300.ucf | 146 + zpu/hdl/zpu4/src/ic300.vhd | 144 + zpu/hdl/zpu4/src/ic300_config.vhd | 26 + zpu/hdl/zpu4/src/ic300pkg.vhd | 88 + zpu/hdl/zpu4/src/io.vhd | 92 + zpu/hdl/zpu4/src/log.txt | 380 ++ zpu/hdl/zpu4/src/niltrace.vhd | 26 + zpu/hdl/zpu4/src/sim_fpga_top.vhd | 190 + zpu/hdl/zpu4/src/simzpu.do | 23 + zpu/hdl/zpu4/src/simzpu_intstack.do | 23 + zpu/hdl/zpu4/src/status.txt | 109 + zpu/hdl/zpu4/src/testlut.vhd | 114 + zpu/hdl/zpu4/src/timer.vhd | 61 + zpu/hdl/zpu4/src/trace.vhd | 84 + zpu/hdl/zpu4/src/txt_util.vhd | 587 +++ zpu/hdl/zpu4/src/xmake.filelist | 12 + zpu/hdl/zpu4/src/xmake.filelist.bramsmall | 5 + zpu/hdl/zpu4/src/xmake.xst | 53 + zpu/hdl/zpu4/src/zpu_config.vhd | 16 + zpu/hdl/zpu4/src/zpu_config_fastsim.vhd | 15 + zpu/hdl/zpu4/src/zpu_config_trace.vhd | 15 + zpu/hdl/zpu4/src/zpu_core.vhd | 900 +++++ zpu/hdl/zpu4/src/zpu_core_small.vhd | 433 +++ zpu/hdl/zpu4/src/zpuio.vhd | 256 ++ zpu/hdl/zpu4/src/zpuio_bram.vhd | 229 ++ zpu/hdl/zpu4/src/zpupkg.vhd | 168 + zpu/hdl/zpu4/test/dmips/build.sh | 3 + zpu/hdl/zpu4/test/dmips/dmips.bin | Bin 0 -> 14612 bytes zpu/hdl/zpu4/test/dmips/dmips.elf | Bin 0 -> 89778 bytes zpu/hdl/zpu4/test/dmips/dmips.ram | 3507 ++++++++++++++++++ zpu/hdl/zpu4/test/hello/build.sh | 3 + zpu/hdl/zpu4/test/hello/hello.bin | Bin 0 -> 12664 bytes zpu/hdl/zpu4/test/hello/hello.c | 51 + zpu/hdl/zpu4/test/hello/hello.elf | Bin 0 -> 150455 bytes zpu/hdl/zpu4/test/hello/hello.ram | 3165 ++++++++++++++++ 59 files changed, 28654 insertions(+) create mode 100644 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd create mode 100644 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd create mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd create mode 100644 zpu/hdl/zpu4/src/.cvsignore create mode 100644 zpu/hdl/zpu4/src/bram.vhd create mode 100644 zpu/hdl/zpu4/src/bram_dmips.vhd create mode 100644 zpu/hdl/zpu4/src/build.xml create mode 100644 zpu/hdl/zpu4/src/clocks.vhd create mode 100644 zpu/hdl/zpu4/src/dmipssmalltrace.do create mode 100644 zpu/hdl/zpu4/src/dmipstrace.do create mode 100644 zpu/hdl/zpu4/src/dmipstraceintstack.do create mode 100644 zpu/hdl/zpu4/src/dram_dmips.vhd create mode 100644 zpu/hdl/zpu4/src/dram_hello.vhd create mode 100644 zpu/hdl/zpu4/src/fastdmips.do create mode 100644 zpu/hdl/zpu4/src/fastdmipsintstack.do create mode 100644 zpu/hdl/zpu4/src/fastdmipssmall.do create mode 100644 zpu/hdl/zpu4/src/fastsimzpu.do create mode 100644 zpu/hdl/zpu4/src/ic300.bitgen create mode 100644 zpu/hdl/zpu4/src/ic300.lso create mode 100644 zpu/hdl/zpu4/src/ic300.ucf create mode 100644 zpu/hdl/zpu4/src/ic300.vhd create mode 100644 zpu/hdl/zpu4/src/ic300_config.vhd create mode 100644 zpu/hdl/zpu4/src/ic300pkg.vhd create mode 100644 zpu/hdl/zpu4/src/io.vhd create mode 100644 zpu/hdl/zpu4/src/log.txt create mode 100644 zpu/hdl/zpu4/src/niltrace.vhd create mode 100644 zpu/hdl/zpu4/src/sim_fpga_top.vhd create mode 100644 zpu/hdl/zpu4/src/simzpu.do create mode 100644 zpu/hdl/zpu4/src/simzpu_intstack.do create mode 100644 zpu/hdl/zpu4/src/status.txt create mode 100644 zpu/hdl/zpu4/src/testlut.vhd create mode 100644 zpu/hdl/zpu4/src/timer.vhd create mode 100644 zpu/hdl/zpu4/src/trace.vhd create mode 100644 zpu/hdl/zpu4/src/txt_util.vhd create mode 100644 zpu/hdl/zpu4/src/xmake.filelist create mode 100644 zpu/hdl/zpu4/src/xmake.filelist.bramsmall create mode 100644 zpu/hdl/zpu4/src/xmake.xst create mode 100644 zpu/hdl/zpu4/src/zpu_config.vhd create mode 100644 zpu/hdl/zpu4/src/zpu_config_fastsim.vhd create mode 100644 zpu/hdl/zpu4/src/zpu_config_trace.vhd create mode 100644 zpu/hdl/zpu4/src/zpu_core.vhd create mode 100644 zpu/hdl/zpu4/src/zpu_core_small.vhd create mode 100644 zpu/hdl/zpu4/src/zpuio.vhd create mode 100644 zpu/hdl/zpu4/src/zpuio_bram.vhd create mode 100644 zpu/hdl/zpu4/src/zpupkg.vhd create mode 100644 zpu/hdl/zpu4/test/dmips/build.sh create mode 100644 zpu/hdl/zpu4/test/dmips/dmips.bin create mode 100644 zpu/hdl/zpu4/test/dmips/dmips.elf create mode 100644 zpu/hdl/zpu4/test/dmips/dmips.ram create mode 100644 zpu/hdl/zpu4/test/hello/build.sh create mode 100644 zpu/hdl/zpu4/test/hello/hello.bin create mode 100644 zpu/hdl/zpu4/test/hello/hello.c create mode 100644 zpu/hdl/zpu4/test/hello/hello.elf create mode 100644 zpu/hdl/zpu4/test/hello/hello.ram (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd new file mode 100644 index 0000000..95fbc18 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package arm7 is + + component arm7wb + generic( + simulate_io_time : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + cpu_din : out std_logic_vector(15 downto 0); + cpu_a : out std_logic_vector(20 downto 0); + cpu_we : out std_logic_vector(1 downto 0); + cpu_re : out std_logic; + cpu_dout : in std_logic_vector(15 downto 0)); + end component; + +end arm7; + + \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd new file mode 100644 index 0000000..55b8125 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd @@ -0,0 +1,213 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity arm7wb is + generic( + simulate_io_time : boolean := false); + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + cpu_din : out std_logic_vector(15 downto 0); + cpu_a : out std_logic_vector(20 downto 0); + cpu_we : out std_logic_vector(1 downto 0); + cpu_re : out std_logic; + cpu_dout : in std_logic_vector(15 downto 0)); +end arm7wb; + +architecture behave of arm7wb is + +attribute keep : string; + +signal cpu_oe_n : std_logic; +signal cpu_fiq : std_logic; +signal cpu_wait_n : std_logic; +signal cpu_clk_toggle : std_logic; +signal cpu_clk_smp1 : std_logic; +signal cpu_clk_smp2 : std_logic; +signal cpu_clk_phase : std_logic; +signal cpu_oe_n_del : std_logic; +signal cpu_a_smp : std_logic_vector(20 downto 0); +signal cpu_d_smp : std_logic_vector(15 downto 0); + +signal int_oe_n : std_logic_vector(15 downto 0); +attribute keep of int_oe_n:signal is "true"; + +signal cpu_irq : std_logic_vector(1 downto 0); +signal cpu_wr_n : std_logic_vector(1 downto 0); +signal cpu_cs_n : std_logic_vector(3 downto 1); + +signal dout : std_logic_vector(15 downto 0); +signal cpu_d_p_out : std_logic_vector(15 downto 0); +signal read_cnt : std_logic_vector(1 downto 0); + +signal cpu_wr_n_p_del : std_logic_vector(1 downto 0); +signal cpu_a_p_del : std_logic_vector(20 downto 0); +signal cpu_d_p_del : std_logic_vector(15 downto 0); +signal cpu_cs_n_p_del : std_logic_vector(3 downto 1); +signal cpu_oe_n_p_del : std_logic; + +constant Sim_Delay : time := 0.5 ns; +constant Clock_2_Out : time := 5.5 ns; +constant Input_Setup : time := 2.5 ns; + +begin + + cpu_wait_n <= '1'; + cpu_fiq <= '1'; + cpu_irq <= "11"; + + iotimingon: + if simulate_io_time generate + begin + cpu_wr_n_p_del <= "XX" after 0 ns, cpu_wr_n_p after Input_Setup; + cpu_a_p_del <= "XXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup; + cpu_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup; + cpu_cs_n_p_del <= "XXX" after 0 ns, cpu_cs_n_p after Input_Setup; + cpu_oe_n_p_del <= 'X' after 0 ns, cpu_oe_n_p after Input_Setup; + end generate; + + iotimingoff: + if not simulate_io_time generate + begin + cpu_wr_n_p_del <= cpu_wr_n_p; + cpu_a_p_del <= cpu_a_p; + cpu_d_p_del <= cpu_d_p; + cpu_cs_n_p_del <= cpu_cs_n_p; + cpu_oe_n_p_del <= cpu_oe_n_p; + end generate; + + process(cpu_clk, areset) -- Toggle FF with 1x clock to find phase + begin + if areset = '1' then + cpu_clk_toggle <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + cpu_clk_toggle <= not(cpu_clk_toggle); + end if; + end process; + + process(cpu_clk_2x, areset) -- Find phase relationsship between 1x and 2x clock + begin + if areset = '1' then + cpu_clk_smp1 <= '0'; + cpu_clk_smp2 <= '1'; + cpu_clk_phase <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + cpu_clk_smp1 <= cpu_clk_toggle; + cpu_clk_smp2 <= cpu_clk_smp1; + if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then + cpu_clk_phase <= '0' after Sim_Delay; + else + cpu_clk_phase <= not(cpu_clk_phase) after Sim_Delay; + end if; + end if; + end process; + + process(cpu_clk_2x, areset) -- Sample input signals + begin + if areset = '1' then + cpu_oe_n <= '1'; + cpu_a_smp <= "000000000000000000000"; + cpu_d_smp <= "0000000000000000"; + cpu_wr_n <= "11"; + cpu_cs_n <= "111"; + elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then + cpu_oe_n <= cpu_oe_n_p_del after Sim_Delay; + cpu_a_smp <= cpu_a_p_del after Sim_Delay; + cpu_d_smp <= cpu_d_p_del after Sim_Delay; + cpu_wr_n <= cpu_wr_n_p_del after Sim_Delay; + cpu_cs_n <= cpu_cs_n_p_del after Sim_Delay; + end if; + end process; + + cpu_d_out: + for i in 0 to 15 generate + begin + process(cpu_clk_2x, areset) + begin + if areset = '1' then + cpu_d_p(i) <= 'Z'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + if int_oe_n(i) = '0' then + cpu_d_p(i) <= cpu_d_p_out(i) after Clock_2_Out; + else + cpu_d_p(i) <= 'Z' after Clock_2_Out; + end if; + end if; + end process; + end generate; + + process(cpu_clk, areset) -- Clocked output pins + begin + if areset = '1' then + cpu_d_p_out <= "1111111111111111"; + cpu_wait_n_p <= '1'; + cpu_irq_p <= "11"; + cpu_fiq_p <= '1'; + elsif (cpu_clk = '1' and cpu_clk'event) then + cpu_d_p_out <= cpu_dout; + cpu_wait_n_p <= '1'; + cpu_irq_p <= "11"; + cpu_fiq_p <= '1'; + end if; + end process; + + process(cpu_clk, areset) -- Generate control signals + begin + if areset = '1' then + int_oe_n <= "1111111111111111"; + read_cnt <= "00"; + cpu_we <= "00"; + cpu_re <= '0'; + cpu_a <= "000000000000000000000"; + cpu_din <= "0000000000000000"; + elsif (cpu_clk = '1' and cpu_clk'event) then + + cpu_a <= cpu_a_smp; + cpu_din <= cpu_d_smp; + + cpu_oe_n_del <= cpu_oe_n; + + if cpu_cs_n(1) = '1' then + read_cnt <= "00"; + else + read_cnt <= read_cnt + '1'; + end if; + + if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(0) = '0' then + cpu_we(0) <= '1'; + else + cpu_we(0) <= '0'; + end if; + + if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(1) = '0' then + cpu_we(1) <= '1'; + else + cpu_we(1) <= '0'; + end if; + + if read_cnt = "00" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then + cpu_re <= '1'; + else + cpu_re <= '0'; + end if; + + if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then + int_oe_n <= "0000000000000000"; + else + int_oe_n <= "1111111111111111"; + end if; + + end if; + end process; + +end behave; diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do new file mode 100644 index 0000000..d2c22cf --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do @@ -0,0 +1,17 @@ +vlib zylin +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd +vcom -93 -explicit -work zylin ../ddrsdram/src/mt46v16m16.vhd +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_tb.vhd +vlib work +vsim -t 1ps zylin.ddr_tb +view wave +view signals +radix hex +add wave * +add wave sim:/ddr_tb/ddr_ctrl/* +force -freeze sim:/ddr_tb/areset 1 0 +run 10 ns +force -freeze sim:/ddr_tb/areset 0 0 +when sim:/ddr_tb/break_out stop +run 10 ms \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do new file mode 100644 index 0000000..31dd294 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do @@ -0,0 +1,111 @@ +vlib zylin +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd +vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd +vlib work +vsim -t 1ps zylin.ddr_top +view wave +view signals +radix hex +# Add wave signals + +add wave -divider "System" +add wave sim:/ddr_top/areset +add wave sim:/ddr_top/cpu_clk +add wave sim:/ddr_top/cpu_clk_2x +add wave sim:/ddr_top/cpu_clk_4x +add wave sim:/ddr_top/ddr_in_clk +add wave sim:/ddr_top/ddr_in_clk_2x + +add wave -divider "Ctrl interface" +add wave sim:/ddr_top/cpu_clk +add wave sim:/ddr_top/ddr_data_read +add wave sim:/ddr_top/ddr_data_write +add wave sim:/ddr_top/ddr_req +add wave sim:/ddr_top/ddr_rd_wr_n +add wave sim:/ddr_top/ddr_req_len +add wave sim:/ddr_top/ddr_wr_mask +add wave sim:/ddr_top/ddr_read_en +add wave sim:/ddr_top/ddr_write_en +add wave sim:/ddr_top/ddr_command +add wave sim:/ddr_top/ddr_command_we + +add wave -divider "DDR interface" +add wave sim:/ddr_top/sdr_clk_p +add wave sim:/ddr_top/sdr_clk_n_p +add wave sim:/ddr_top/cke_q_p +add wave sim:/ddr_top/cs_qn_p +add wave sim:/ddr_top/ras_qn_p +add wave sim:/ddr_top/cas_qn_p +add wave sim:/ddr_top/we_qn_p +add wave sim:/ddr_top/dm_q_p +add wave sim:/ddr_top/dqs_q_p +add wave sim:/ddr_top/ba_q_p +add wave sim:/ddr_top/sdr_a_p +add wave sim:/ddr_top/sdr_d_p + +add wave -divider "Internal signals" +add wave sim:/ddr_top/clk2_phase +add wave sim:/ddr_top/clk4_phase +add wave sim:/ddr_top/ddr_state +add wave sim:/ddr_top/sdr_oe_n +add wave sim:/ddr_top/sdr_smp +add wave sim:/ddr_top/sdr_d + + +# Add input signals +force -freeze sim:/ddr_top/cpu_clk_4x 1 0, 0 {1.875 ns} -r 3.75 +run 100 ps +force -freeze sim:/ddr_top/cpu_clk_2x 1 0, 0 {3.75 ns} -r 7.5 +run 100 ps +force -freeze sim:/ddr_top/cpu_clk 1 0, 0 {7.5 ns} -r 15 +force -freeze sim:/ddr_top/ddr_in_clk 1 2ns, 0 {5.75 ns} -r 7.5 +force -freeze sim:/ddr_top/ddr_in_clk_2x 0 0.125ns, 1 {2 ns} -r 3.75 + +force -freeze sim:/ddr_top/areset 1 0 +force -freeze sim:/ddr_top/ddr_command 0000 0 +force -freeze sim:/ddr_top/ddr_command_we 0 0 +force -freeze sim:/ddr_top/ddr_data_write 1234abcd 0 +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 + +# Start simulation +run 45 +force -freeze sim:/ddr_top/areset 0 0 +run 92 +# DDR Command +force -freeze sim:/ddr_top/ddr_command 000A 0 +force -freeze sim:/ddr_top/ddr_command_we 1 0 +run 15 +force -freeze sim:/ddr_top/ddr_command 0000 0 +force -freeze sim:/ddr_top/ddr_command_we 0 0 +run 90 +# DDR Read +force -freeze sim:/ddr_top/ddr_req 1 0 +force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 1 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 +run 15 +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 +run 150 +# DDR Write +force -freeze sim:/ddr_top/ddr_req 1 0 +force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 +run 15 +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 000 0 +force -freeze sim:/ddr_top/ddr_wr_mask 0 0 +run 180 + diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd new file mode 100644 index 0000000..95f4b8a --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd @@ -0,0 +1,90 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package ddr is + + component ddr_top + generic( + simulate_io_time : boolean := false); + port ( -- Asyncronous reset and clocks + areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + -- Command interface + ddr_command : in std_logic_vector(15 downto 0); + ddr_command_we : in std_logic; + refresh_en : in std_logic; + + + -- Data interface signals + ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM + ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM + ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address + ddr_req : in std_logic; -- Request DDR SDRAM access + ddr_req_ack : out std_logic; -- Request acknowledge + ddr_busy : out std_logic; -- Request acknowledge + ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE + ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) + ddr_read_en : out std_logic; -- Enable signal for read data + ddr_write_en : out std_logic; -- Enable (read) signal for data write + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus + end component; + + component MT46V16M16 + GENERIC ( -- Timing for -75Z CL2 + tCK : TIME := 7.500 ns; + tCH : TIME := 3.375 ns; -- 0.45*tCK + tCL : TIME := 3.375 ns; -- 0.45*tCK + tDH : TIME := 0.500 ns; + tDS : TIME := 0.500 ns; + tIH : TIME := 0.900 ns; + tIS : TIME := 0.900 ns; + tMRD : TIME := 15.000 ns; + tRAS : TIME := 40.000 ns; + tRAP : TIME := 20.000 ns; + tRC : TIME := 65.000 ns; + tRFC : TIME := 75.000 ns; + tRCD : TIME := 20.000 ns; + tRP : TIME := 20.000 ns; + tRRD : TIME := 15.000 ns; + tWR : TIME := 15.000 ns; + addr_bits : INTEGER := 13; + data_bits : INTEGER := 16; + cols_bits : INTEGER := 9 + ); + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + Clk : IN STD_LOGIC; + Clk_n : IN STD_LOGIC; + Cke : IN STD_LOGIC; + Cs_n : IN STD_LOGIC; + Ras_n : IN STD_LOGIC; + Cas_n : IN STD_LOGIC; + We_n : IN STD_LOGIC; + Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + end component; + +end ddr; + \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd new file mode 100644 index 0000000..5666532 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd @@ -0,0 +1,301 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library zylin; +use zylin.ddr.all; + +entity ddr_tb is + port ( areset : in std_logic; + break_out : out std_logic); +end ddr_tb; + +architecture behave of ddr_tb is + +signal cpu_clk : std_logic; +signal cpu_clk_2x : std_logic; +signal cpu_clk_4x : std_logic; +signal ddr_in_clk : std_logic; +signal ddr_in_clk_2x : std_logic; + +signal ddr_command : std_logic_vector(15 downto 0); +signal ddr_command_we : std_logic; + +signal ddr_data_read : std_logic_vector(31 downto 0); -- Data read from DDR SDRAM +signal ddr_data_write : std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM +signal ddr_req_adr : std_logic_vector(23 downto 1); -- Request address +signal ddr_req : std_logic; -- Request DDR SDRAM access +signal ddr_req_ack : std_logic; -- Request acknowledge +signal ddr_busy : std_logic; -- Request acknowledge +signal ddr_rd_wr_n : std_logic; -- Access type 1=READ, 0=WRITE +signal ddr_req_len : std_logic; -- Number of 16-bits words to transfer +signal ddr_read_en : std_logic; -- Enable signal for read data +signal ddr_write_en : std_logic; -- Enable (read) signal for data write +signal refresh_en : std_logic; + +signal sdr_clk_p : std_logic; -- ddr_sdram_clock +signal sdr_clk_n_p : std_logic; -- /ddr_sdram_clock +signal cke_q_p : std_logic; -- clock enable +signal cs_qn_p : std_logic; -- /chip select +signal ras_qn_p : std_logic; -- /ras +signal cas_qn_p : std_logic; -- /cas +signal we_qn_p : std_logic; -- /write enable +signal dm_q_p : std_logic_vector(1 downto 0); -- data mask bits, set to "00" +signal dqs_q_p : std_logic_vector(1 downto 0); -- data strobe, only for write +signal ba_q_p : std_logic_vector(1 downto 0); -- bank select +signal sdr_a_p : std_logic_vector(12 downto 0); -- address bus +signal sdr_d_p : std_logic_vector(15 downto 0); -- bidir data bus + +constant min_time : time := 1.875 ns; + +begin + + clock1: + process + begin + loop + cpu_clk_4x <= '1'; + wait for min_time; + cpu_clk_4x <= '0'; + wait for min_time; + end loop; + end process; + + clock2: + process + begin + loop + cpu_clk_2x <= '1' after 100 ps; + wait until rising_edge(cpu_clk_4x); + cpu_clk_2x <= '0' after 100 ps; + wait until rising_edge(cpu_clk_4x); + end loop; + end process; + + clock3: + process + begin + loop + cpu_clk <= '1' after 100 ps; + wait until rising_edge(cpu_clk_2x); + cpu_clk <= '0' after 100 ps; + wait until rising_edge(cpu_clk_2x); + end loop; + end process; + + ddr_in_clk_2x <= cpu_clk_4x after 1 ns; + + clock4: + process + begin + loop + ddr_in_clk <= '0' after 100 ps; + wait until rising_edge(ddr_in_clk_2x); + ddr_in_clk <= '1' after 100 ps; + wait until rising_edge(ddr_in_clk_2x); + end loop; + end process; + + inputdata: + process + begin + -- Wait until global reset released + loop + ddr_command <= x"0000"; + ddr_command_we <= '0'; + ddr_data_write <= x"000000000"; + ddr_req <= '0'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + break_out <= '0'; + refresh_en <= '0'; + + wait until falling_edge(areset); + + -- DDR initialization sequence + -- Wait more than 200 us + wait for 201000 ns; + + -- Send precharge command + wait until rising_edge(cpu_clk); + ddr_command <= x"8000"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 1 us + wait for 1000 ns; + + -- Load extended mode register + -- Enable DLL + -- Normal drive strength + wait until rising_edge(cpu_clk); + ddr_command <= x"2000"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 1 us + wait for 1000 ns; + + -- Load mode register + -- Burst length: 2 + -- Burst type: Sequential + -- Cas latency: 2 + -- Reset DLL + wait until rising_edge(cpu_clk); + ddr_command <= x"0121"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 1 us + wait for 1000 ns; + + -- Send precharge command + wait until rising_edge(cpu_clk); + ddr_command <= x"8000"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Enable refresh + refresh_en <= '1'; + + -- Wait 30 us (minimum 2 autorefresh cycles) + wait for 30000 ns; + + -- Load mode register + -- Burst length: 2 + -- Burst type: Sequential + -- Cas latency: 2 + -- Deactivate Reset DLL + wait until rising_edge(cpu_clk); + ddr_command <= x"0021"; + ddr_command_we <= '1'; + wait until rising_edge(cpu_clk); + ddr_command <= x"0000"; + ddr_command_we <= '0'; + + -- Wait for 2 us (DLL stable) + wait for 2000 ns; + + -- Write data to DDR + wait until rising_edge(cpu_clk_2x); + ddr_data_write <= x"312345678"; + ddr_req <= '1'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + wait until rising_edge(ddr_write_en); + wait until rising_edge(cpu_clk_2x); + ddr_req <= '0'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + ddr_data_write <= x"000000000"; + wait for 100 ns; + + -- Read data from DDR + wait until rising_edge(cpu_clk_2x); + ddr_req <= '1'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '1'; + ddr_req_len <= '0'; + wait until rising_edge(ddr_req_ack); + wait until rising_edge(cpu_clk_2x); + ddr_req <= '0'; + ddr_req_adr <= "00000000000000000000000"; + ddr_rd_wr_n <= '0'; + ddr_req_len <= '0'; + ddr_data_write <= x"000000000"; + + + + wait for 100 ns; + break_out <= '1'; + wait for 100 ns; + + end loop; + + end process; + + ddr_ctrl: + ddr_top port map( + areset => areset, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_clk_4x => cpu_clk_4x, + ddr_in_clk => ddr_in_clk, + ddr_in_clk_2x => ddr_in_clk_2x, + + -- Command interface + ddr_command => ddr_command, + ddr_command_we => ddr_command_we, + refresh_en => refresh_en, + + -- Data interface signals + ddr_data_read => ddr_data_read, + ddr_data_write => ddr_data_write, + ddr_req_adr => ddr_req_adr, + ddr_req => ddr_req, + ddr_req_ack => ddr_req_ack, + ddr_busy => ddr_busy, + ddr_rd_wr_n => ddr_rd_wr_n, + ddr_req_len => ddr_req_len, + ddr_read_en => ddr_read_en, + ddr_write_en => ddr_write_en, + -- DDR SDRAM Signals + sdr_clk_p => sdr_clk_p, + sdr_clk_n_p => sdr_clk_n_p, + cke_q_p => cke_q_p, + cs_qn_p => cs_qn_p, + ras_qn_p => ras_qn_p, + cas_qn_p => cas_qn_p, + we_qn_p => we_qn_p, + dm_q_p => dm_q_p, + dqs_q_p => dqs_q_p, + ba_q_p => ba_q_p, + sdr_a_p => sdr_a_p, + sdr_d_p => sdr_d_p); + + myram: + MT46V16M16 generic map( + tCK => 7.500 ns, + tCH => 3.375 ns, -- 0.45*tCK + tCL => 3.375 ns, -- 0.45*tCK + tDH => 0.500 ns, + tDS => 0.500 ns, + tIH => 0.900 ns, + tIS => 0.900 ns, + tMRD => 15.000 ns, + tRAS => 40.000 ns, + tRAP => 20.000 ns, + tRC => 65.000 ns, + tRFC => 75.000 ns, + tRCD => 20.000 ns, + tRP => 20.000 ns, + tRRD => 15.000 ns, + tWR => 15.000 ns, + addr_bits => 13, + data_bits => 16, + cols_bits => 9) + port map( + Dq => sdr_d_p, + Dqs => dqs_q_p, + Addr => sdr_a_p, + Ba => ba_q_p, + Clk => sdr_clk_p, + Clk_n => sdr_clk_n_p, + Cke => cke_q_p, + Cs_n => cs_qn_p, + Ras_n => ras_qn_p, + Cas_n => cas_qn_p, + We_n => we_qn_p, + Dm => dm_q_p); + +end behave; diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd new file mode 100644 index 0000000..d5e98e1 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd @@ -0,0 +1,660 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity ddr_top is + generic( + simulate_io_time : boolean := false); + port ( -- Asyncronous reset and clocks + areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + -- Command interface + ddr_command : in std_logic_vector(15 downto 0); + ddr_command_we : in std_logic; + refresh_en : in std_logic; + + -- Data interface signals + ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM + ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM + ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address + ddr_req : in std_logic; -- Request DDR SDRAM access + ddr_req_ack : out std_logic; -- Request acknowledge + ddr_busy : out std_logic; -- Request acknowledge + ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE + ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) + ddr_read_en : out std_logic; -- Enable signal for read data + ddr_write_en : out std_logic; -- Enable (read) signal for data write + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus +end ddr_top; + +architecture behave of ddr_top is + +attribute keep : string; + +signal cpu_clk_tog : std_logic; +signal ddr_cmd : std_logic_vector(15 downto 0); +signal ddr_cmd_we_smp : std_logic; +signal new_command : std_logic; + +signal cpu_clk_2x_smp1 : std_logic; +signal cpu_clk_2x_smp2 : std_logic; +signal cpu_clk_4x_smp1 : std_logic; +signal cpu_clk_4x_smp2 : std_logic; + +signal clk2_phase : std_logic; +signal clk4_phase : std_logic_vector(3 downto 0); +signal clk4_phase_short : std_logic_vector(1 downto 0); + +signal ddr_clk_tog : std_logic; +signal ddr_clk_smp1 : std_logic; +signal ddr_clk_smp2 : std_logic; +signal ddr_clk_phase : std_logic; + +signal smp_req_adr : std_logic_vector(23 downto 1); +signal smp_req_type : std_logic; +signal smp_req_len : std_logic; +signal ddr_write_en_int : std_logic; +signal ddr_read_en_int : std_logic; + +signal dqs_q : std_logic_vector(1 downto 0); +signal dqs_oe_n : std_logic_vector(1 downto 0); +attribute keep of dqs_oe_n:signal is "true"; +signal cas_qn : std_logic; +signal ras_qn : std_logic; +signal we_qn : std_logic; +signal ba_q : std_logic_vector(1 downto 0); +signal sdr_clk : std_logic; +signal sdr_clk_n : std_logic; +signal sdr_a : std_logic_vector(12 downto 0); +signal sdr_d : std_logic_vector(15 downto 0); +signal sdr_smp : std_logic_vector(35 downto 0); +signal sdr_oe_n : std_logic_vector(15 downto 0); +attribute keep of sdr_oe_n:signal is "true"; +signal sdr_oe_ctrl : std_logic; +signal sdr_wr_msw : std_logic_vector(17 downto 0); +attribute keep of sdr_wr_msw:signal is "true"; +signal dm_q : std_logic_vector(1 downto 0); + +signal cas_n_smp : std_logic; +signal ras_n_smp : std_logic; +signal we_n_smp : std_logic; +signal read_start_sig : std_logic; +signal sdr_d_in : std_logic_vector(15 downto 0); +signal read_time_cnt : std_logic_vector(1 downto 0); +signal read_input_en : std_logic; +signal ddr_data_read_int : std_logic_vector(31 downto 0); + +signal refresh_pend : std_logic; +signal refresh_end : std_logic; +signal refresh_cnt : std_logic_vector(9 downto 0); +signal refresh_wait_cnt : std_logic_vector(2 downto 0); +signal refresh_wait_end : std_logic; + +signal cas_qn_p_del : std_logic; +signal ras_qn_p_del : std_logic; +signal we_qn_p_del : std_logic; +signal sdr_d_p_del : std_logic_vector(15 downto 0); + +type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, + rd_nop2, pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, + wr_nop3, cmd, cpu_pre, refresh, refresh_wait); +signal ddr_state : state_type; + +constant Clk_to_Output : time := 2.2 ns; +constant Sim_Delay : time := 0.5 ns; +constant Input_Setup : time := 2.5 ns; + +constant Refresh_Interval : std_logic_vector(9 downto 0) := "1111100110"; + +begin + + iotimingon: + if simulate_io_time generate + begin + cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup; + ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup; + we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup; + sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup; + end generate; + + iotimingoff: + if not simulate_io_time generate + begin + cas_qn_p_del <= cas_qn_p; + ras_qn_p_del <= ras_qn_p; + we_qn_p_del <= we_qn_p; + sdr_d_p_del <= sdr_d_p; + end generate; + + ddr_write_en <= ddr_write_en_int; + ddr_read_en <= ddr_read_en_int; + ddr_data_read <= ddr_data_read_int; + + process(cpu_clk, areset) -- Toggle a flip-flop with cpu_clk, in order + begin -- to find phase relation with 2x and 4x clocks + if areset = '1' then + cpu_clk_tog <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + cpu_clk_tog <= not(cpu_clk_tog) after Sim_Delay; + end if; + end process; + + process(cpu_clk_2x, areset) -- Find phase relation between cpu_clk and cpu_clk_2x + begin + if areset = '1' then + cpu_clk_2x_smp1 <= '0'; + cpu_clk_2x_smp2 <= '0'; + clk2_phase <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + cpu_clk_2x_smp1 <= cpu_clk_tog after Sim_Delay; + cpu_clk_2x_smp2 <= cpu_clk_2x_smp1 after Sim_Delay; + if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then + clk2_phase <= '0' after Sim_Delay; + else + clk2_phase <= not(clk2_phase) after Sim_Delay; + end if; + end if; + end process; + + process(cpu_clk_4x, areset) -- Find phase relation between cpu_clk and cpu_clk_4x + begin + if areset = '1' then + cpu_clk_4x_smp1 <= '0'; + cpu_clk_4x_smp2 <= '0'; + clk4_phase <= "0000"; + clk4_phase_short <= "00"; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + cpu_clk_4x_smp1 <= cpu_clk_tog after Sim_Delay; + cpu_clk_4x_smp2 <= cpu_clk_4x_smp1 after Sim_Delay; + if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then + clk4_phase <= "0100" after Sim_Delay; + clk4_phase_short <= "01" after Sim_Delay; + else + clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3)) after Sim_Delay; + clk4_phase_short <= clk4_phase_short(0) & clk4_phase_short(1); + end if; + end if; + end process; + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + sdr_clk <= '0'; + sdr_clk_n <= '0'; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + if clk4_phase_short(0) = '1' then + sdr_clk <= '1' after Sim_Delay; + else + sdr_clk <= '0' after Sim_Delay; + end if; + if clk4_phase_short(1) = '1' then + sdr_clk_n <= '1' after Sim_Delay; + else + sdr_clk_n <= '0' after Sim_Delay; + end if; + end if; + end process; + + cke_q_p <= '1' after Clk_to_Output; + cs_qn_p <= '0' after Clk_to_Output; + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + ras_qn_p <= '1'; + cas_qn_p <= '1'; + we_qn_p <= '1'; + dqs_q_p <= "ZZ"; + sdr_a_p <= "0000000000000"; + ba_q_p <= "00"; + sdr_clk_p <= '0'; + sdr_clk_n_p <= '1'; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + ras_qn_p <= transport ras_qn after Clk_to_Output; + cas_qn_p <= transport cas_qn after Clk_to_Output; + we_qn_p <= transport we_qn after Clk_to_Output; + if dqs_oe_n(0) = '0' then + dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output; + else + dqs_q_p(0) <= transport 'Z' after Clk_to_Output; + end if; + if dqs_oe_n(1) = '0' then + dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output; + else + dqs_q_p(1) <= transport 'Z' after Clk_to_Output; + end if; + sdr_a_p <= transport sdr_a after Clk_to_Output; + ba_q_p <= transport ba_q after Clk_to_Output; + sdr_clk_p <= transport sdr_clk after Clk_to_Output; + sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output; + end if; + end process; + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + ddr_state <= idle; + ras_qn <= '1'; + cas_qn <= '1'; + we_qn <= '1'; + smp_req_adr <= (others => '0'); + smp_req_type <= '0'; + smp_req_len <= '0'; + sdr_a <= "XXXXXXXXXXXXX"; + ba_q <= "00"; + ddr_req_ack <= '0'; + ddr_busy <= '1'; + ddr_write_en_int <= '0'; + ddr_read_en_int <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + + -- Default values + ras_qn <= '1' after Sim_Delay; + cas_qn <= '1' after Sim_Delay; + we_qn <= '1' after Sim_Delay; + sdr_a <= "XXXXXXXXXXXXX" after Sim_Delay; + ba_q <= "00" after Sim_Delay; + ddr_req_ack <= '0' after Sim_Delay; + ddr_busy <= '1' after Sim_Delay; + ddr_write_en_int <= '0' after Sim_Delay; + ddr_read_en_int <= '0' after Sim_Delay; + + case ddr_state is + when idle => + smp_req_adr <= ddr_req_adr after Sim_Delay; + smp_req_type <= ddr_rd_wr_n after Sim_Delay; + smp_req_len <= ddr_req_len after Sim_Delay; + ddr_busy <= '0' after Sim_Delay; + if refresh_pend = '1' then + ddr_state <= refresh after Sim_Delay; + elsif new_command = '1' then + if ddr_cmd(15) = '1' then + ddr_state <= cpu_pre after Sim_Delay; + else + ddr_state <= cmd after Sim_Delay; + end if; + elsif ddr_req = '1' then + ddr_state <= act after Sim_Delay; + else + ddr_state <= idle after Sim_Delay; + end if; + when act => + sdr_a <= smp_req_adr(23 downto 11) after Sim_Delay; + ras_qn <= '0' after Sim_Delay; + ddr_state <= act_nop1 after Sim_Delay; + ddr_req_ack <= '1' after Sim_Delay; + ddr_write_en_int <= not(smp_req_type) after Sim_Delay; + when act_nop1 => + ddr_state <= act_nop2 after Sim_Delay; + when act_nop2 => + ddr_state <= rd_wr after Sim_Delay; + when rd_wr => + sdr_a(10) <= '0' after Sim_Delay; -- Disable auto precharge + sdr_a(9 downto 0) <= smp_req_adr(10 downto 1) after Sim_Delay; + cas_qn <= '0' after Sim_Delay; + we_qn <= smp_req_type after Sim_Delay; + if smp_req_type = '1' then + ddr_state <= rd_nop1 after Sim_Delay; + else + ddr_state <= wr_nop1 after Sim_Delay; + end if; + when wr_nop1 => + ddr_state <= wr_nop2 after Sim_Delay; + when wr_nop2 => + ddr_state <= wr_nop3 after Sim_Delay; + when wr_nop3 => + ddr_state <= pre after Sim_Delay; + when rd_nop1 => + ddr_state <= rd_nop2 after Sim_Delay; + when rd_nop2 => + ddr_state <= pre after Sim_Delay; + when pre => + ras_qn <= '0' after Sim_Delay; + we_qn <= '0' after Sim_Delay; + sdr_a(10) <= '1' after Sim_Delay; -- Precharge all banks + ddr_state <= pre_nop1 after Sim_Delay; + ddr_read_en_int <= smp_req_type after Sim_Delay; + when pre_nop1 => + ddr_state <= pre_nop2 after Sim_Delay; + when cmd => + cas_qn <= '0' after Sim_Delay; + ras_qn <= '0' after Sim_Delay; + we_qn <= '0' after Sim_Delay; + ba_q <= ddr_cmd(14 downto 13) after Sim_Delay; + sdr_a <= ddr_cmd(12 downto 0) after Sim_Delay; + ddr_state <= idle after Sim_Delay; + when cpu_pre => + ddr_state <= pre after Sim_Delay; + when refresh => + cas_qn <= '0' after Sim_Delay; + ras_qn <= '0' after Sim_Delay; + ddr_state <= refresh_wait after Sim_Delay; + when refresh_wait => + if refresh_wait_end = '1' then + ddr_state <= pre after Sim_Delay; + end if; + when pre_nop2 => + ddr_state <= idle after Sim_Delay; + when others => + ddr_state <= idle after Sim_Delay; + end case; + end if; + end process; + + process(cpu_clk, areset) -- + begin + if areset = '1' then + ddr_cmd <= "0000000000000000"; + elsif (cpu_clk'event and cpu_clk = '1') then + if ddr_command_we = '1' then + ddr_cmd <= ddr_command after Sim_Delay; + else + ddr_cmd <= ddr_cmd after Sim_Delay; + end if; + end if; + end process; + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + ddr_cmd_we_smp <= '0'; + new_command <= '0'; + sdr_smp <= "000000000000000000000000000000000000"; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + ddr_cmd_we_smp <= ddr_command_we after Sim_Delay; + if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then + new_command <= '1' after Sim_Delay; + elsif ddr_state = cmd or ddr_state = cpu_pre then + new_command <= '0' after Sim_Delay; + else + new_command <= new_command after Sim_Delay; + end if; + + if ddr_write_en_int = '1' then + sdr_smp <= ddr_data_write after Sim_Delay; + else + sdr_smp <= sdr_smp after Sim_Delay; + end if; + + end if; + end process; + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + dqs_q <= "00"; + dqs_oe_n <= "11"; + sdr_oe_ctrl <= '1'; + sdr_wr_msw <= "000000000000000000"; + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + + if ddr_state = wr_nop1 and clk4_phase_short(0) = '1' then + sdr_oe_ctrl <= '0' after Sim_Delay; + elsif ddr_state = wr_nop3 and clk4_phase_short(0) = '1' then + sdr_oe_ctrl <= '1' after Sim_Delay; + else + sdr_oe_ctrl <= sdr_oe_ctrl after Sim_Delay; + end if; + + if ddr_state = idle or ddr_state = wr_nop3 then + dqs_oe_n <= "11" after Sim_Delay; + elsif ddr_state = wr_nop1 then + dqs_oe_n <= "00" after Sim_Delay; + else + dqs_oe_n <= dqs_oe_n after Sim_Delay; + end if; + + if (ddr_state = wr_nop2 and clk4_phase_short(0) = '1') then + dqs_q <= "11" after Sim_Delay; + else + dqs_q <= "00" after Sim_Delay; + end if; + + if ddr_state = wr_nop1 and clk4_phase_short(1) = '1' then + sdr_wr_msw <= "111111111111111111" after Sim_Delay; + else + sdr_wr_msw <= "000000000000000000" after Sim_Delay; + end if; + + end if; + end process; + + -- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + sdr_d_p <= "ZZZZZZZZZZZZZZZZ"; + dm_q_p <= "11"; + sdr_oe_n <= "1111111111111111"; + sdr_d <= "0000000000000000"; + dm_q <= "11"; + elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then + + for i in 0 to 15 loop + if sdr_oe_n(i) = '0' then + sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output; + else + sdr_d_p(i) <= transport 'Z' after Clk_to_Output; + end if; + end loop; + + dm_q_p <= transport dm_q after Clk_to_Output; + + if sdr_oe_ctrl = '0' then + sdr_oe_n <= "0000000000000000" after Sim_Delay; + else + sdr_oe_n <= "1111111111111111" after Sim_Delay; + end if; + + for i in 0 to 15 loop + if sdr_wr_msw(i) = '0' then + sdr_d(i) <= sdr_smp(i) after Sim_Delay; + else + sdr_d(i) <= sdr_smp(i+16) after Sim_Delay; + end if; + end loop; + + for i in 0 to 1 loop + if sdr_wr_msw(i+16) = '0' then + dm_q(i) <= sdr_smp(i+32) after Sim_Delay; + else + dm_q(i) <= sdr_smp(i+34) after Sim_Delay; + end if; + end loop; + + end if; + end process; + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + refresh_cnt <= "0000000000"; + refresh_pend <= '0'; + refresh_end <= '0'; + refresh_wait_cnt <= "000"; + refresh_wait_end <= '0'; + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + + if refresh_cnt = Refresh_Interval then + refresh_end <= '1'; + else + refresh_end <= '0'; + end if; + + if refresh_end = '1' then + refresh_cnt <= "0000000000"; + else + refresh_cnt <= refresh_cnt + '1'; + end if; + + if refresh_end = '1' and refresh_en = '1' then + refresh_pend <= '1' after Sim_Delay; + elsif ddr_state = refresh then + refresh_pend <= '0' after Sim_Delay; + else + refresh_pend <= refresh_pend after Sim_Delay; + end if; + + if ddr_state = refresh_wait then + refresh_wait_cnt <= refresh_wait_cnt + '1'; + else + refresh_wait_cnt <= "000"; + end if; + + if refresh_wait_cnt = "111" then + refresh_wait_end <= '1' after Sim_Delay; + else + refresh_wait_end <= '0' after Sim_Delay; + end if; + + end if; + end process; + + -- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING + + process(ddr_in_clk, areset) + begin + if areset = '1' then + ddr_clk_tog <= '0'; + elsif (ddr_in_clk'event and ddr_in_clk = '1') then + ddr_clk_tog <= not(ddr_clk_tog) after Sim_Delay; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + ddr_clk_smp1 <= '0'; + ddr_clk_smp2 <= '0'; + ddr_clk_phase <= '0'; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + ddr_clk_smp1 <= ddr_clk_tog after Sim_Delay; + ddr_clk_smp2 <= ddr_clk_smp1 after Sim_Delay; + if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then + ddr_clk_phase <= '0'; + else + ddr_clk_phase <= not(ddr_clk_phase); + end if; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + cas_n_smp <= '0'; + ras_n_smp <= '0'; + we_n_smp <= '0'; + read_start_sig <= '0'; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + cas_n_smp <= cas_qn_p_del after Sim_Delay; + ras_n_smp <= ras_qn_p_del after Sim_Delay; + we_n_smp <= we_qn_p_del after Sim_Delay; + if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then + read_start_sig <= '1' after Sim_Delay; + else + read_start_sig <= '0' after Sim_Delay; + end if; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + sdr_d_in <= "0000000000000000"; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + sdr_d_in <= sdr_d_p_del after Sim_Delay; + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + read_time_cnt <= "00"; + read_input_en <= '0'; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + + if read_start_sig = '1' then + read_time_cnt <= "01" after Sim_Delay; + elsif read_time_cnt = "00" then + read_time_cnt <= read_time_cnt after Sim_Delay; + else + read_time_cnt <= read_time_cnt + '1' after Sim_Delay; + end if; + + if read_time_cnt = "11" then + read_input_en <= '1' after Sim_Delay; + else + read_input_en <= '0' after Sim_Delay; + end if; + + end if; + end process; + + process(ddr_in_clk_2x, areset) + begin + if areset = '1' then + ddr_data_read_int <= "00000000000000000000000000000000"; + elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then + ddr_data_read_int(31 downto 16) <= "0000000000000000" after Sim_Delay; + if read_input_en = '1' then + ddr_data_read_int(15 downto 0) <= sdr_d_in after Sim_Delay; + else + ddr_data_read_int(15 downto 0) <= ddr_data_read_int(15 downto 0) after Sim_Delay; + end if; + end if; + end process; + + + + + + + + + -- ############### + + process(cpu_clk, areset) -- + begin + if areset = '1' then + elsif (cpu_clk'event and cpu_clk = '1') then + end if; + end process; + + + process(cpu_clk_2x, areset) -- + begin + if areset = '1' then + elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then + end if; + end process; + + + process(cpu_clk_4x, areset) -- + begin + if areset = '1' then + elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then + end if; + end process; + + +end behave; + + diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd new file mode 100644 index 0000000..6b89345 --- /dev/null +++ b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd @@ -0,0 +1,1320 @@ +----------------------------------------------------------------------------------------- +-- +-- File Name: MT46V16M16.VHD +-- Version: 2.1 +-- Date: January 14th, 2002 +-- Model: Behavioral +-- Simulator: NCDesktop - http://www.cadence.com +-- ModelSim PE - http://www.model.com +-- +-- Dependencies: None +-- +-- Author: Son P. Huynh +-- Email: sphuynh@micron.com +-- Phone: (208) 368-3825 +-- Company: Micron Technology, Inc. +-- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) +-- +-- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) +-- +-- Limitation: Doesn't model internal refresh counter +-- +-- Note: +-- +-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +-- +-- Copyright (c) 1998 Micron Semiconductor Products, Inc. +-- All rights researved +-- +-- Rev Author Date Changes +-- --- ---------------------------- ---------- ------------------------------------- +-- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter +-- Micron Technology, Inc. +-- +-- 2.0 Son P. Huynh 11/08/2001 - Second release +-- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE +-- +----------------------------------------------------------------------------------------- + +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.STD_LOGIC_UNSIGNED.ALL; + USE IEEE.STD_LOGIC_ARITH.ALL; + +ENTITY MT46V16M16 IS + GENERIC ( -- Timing for -75Z CL2 + tCK : TIME := 7.500 ns; + tCH : TIME := 3.375 ns; -- 0.45*tCK + tCL : TIME := 3.375 ns; -- 0.45*tCK + tDH : TIME := 0.500 ns; + tDS : TIME := 0.500 ns; + tIH : TIME := 0.900 ns; + tIS : TIME := 0.900 ns; + tMRD : TIME := 15.000 ns; + tRAS : TIME := 40.000 ns; + tRAP : TIME := 20.000 ns; + tRC : TIME := 65.000 ns; + tRFC : TIME := 75.000 ns; + tRCD : TIME := 20.000 ns; + tRP : TIME := 20.000 ns; + tRRD : TIME := 15.000 ns; + tWR : TIME := 15.000 ns; + addr_bits : INTEGER := 13; + data_bits : INTEGER := 16; + cols_bits : INTEGER := 9 + ); + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + Clk : IN STD_LOGIC; + Clk_n : IN STD_LOGIC; + Cke : IN STD_LOGIC; + Cs_n : IN STD_LOGIC; + Ras_n : IN STD_LOGIC; + Cas_n : IN STD_LOGIC; + We_n : IN STD_LOGIC; + Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END MT46V16M16; + +ARCHITECTURE behave OF MT46V16M16 IS + -- Array for Read pipeline + TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + + -- Array for Write pipeline + TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + + -- Array for Auto Precharge + TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; + + -- Array for Manual Precharge + TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); + TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + + -- Array for Burst Terminate + TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; + + -- Array for Memory Access + TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + TYPE Array_ram_pntr IS ACCESS Array_ram_type; + TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; + + -- Data pair + SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); + SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); + + -- Mode Register + SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + + -- Command Decode Variables + SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; + SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; + + -- Burst Length Decode Variables + SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; + + -- Cas Latency Decode Variables + SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; + + -- Internal Control Signals + SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; + + -- System Clock + SIGNAL Sys_clk : STD_LOGIC := '0'; + + -- Dqs buffer + SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + +BEGIN + -- Strip the strength + Cs_in <= To_X01 (Cs_n); + Ras_in <= To_X01 (Ras_n); + Cas_in <= To_X01 (Cas_n); + We_in <= To_X01 (We_n); + + -- Commands Decode + Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; + Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; + Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); + Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); + Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); + Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); + Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; + Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); + + -- Burst Length Decode + Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); + Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); + Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + + -- CAS Latency Decode + Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); + Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); + Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); + + -- Dqs buffer + Dqs <= Dqs_out; + + -- + -- System Clock + -- + int_clk : PROCESS (Clk, Clk_n) + VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; + begin + IF Clk = '1' AND Clk_n = '0' THEN + ClkZ := '1'; + CkeZ := Cke; + ELSIF Clk = '0' AND Clk_n = '1' THEN + ClkZ := '0'; + END IF; + Sys_clk <= CkeZ AND ClkZ; + END PROCESS; + + -- + -- Main Process + -- + state_register : PROCESS + -- Precharge Variables + VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; + + -- Activate Variables + VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; + + -- Data IO variables + VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; + + -- Internal address mux variables + VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); + VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); + + -- DLL Reset variables + VARIABLE DLL_enable : STD_LOGIC := '0'; + VARIABLE DLL_reset : STD_LOGIC := '0'; + VARIABLE DLL_done : STD_LOGIC := '0'; + VARIABLE DLL_count : INTEGER := 0; + + -- Timing Check + VARIABLE MRD_chk : TIME := 0 ns; + VARIABLE RFC_chk : TIME := 0 ns; + VARIABLE RRD_chk : TIME := 0 ns; + VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; + VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; + VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; + VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; + VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; + VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; + + -- Read pipeline variables + VARIABLE Read_cmnd : Array_Read_cmnd; + VARIABLE Read_bank : Array_Read_bank; + VARIABLE Read_cols : Array_Read_cols; + + -- Write pipeline variables + VARIABLE Write_cmnd : Array_Write_cmnd; + VARIABLE Write_bank : Array_Write_bank; + VARIABLE Write_cols : Array_Write_cols; + + -- Auto Precharge variables + VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); + VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); + VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); + + -- Manual Precharge variables + VARIABLE A10_precharge : Array_A10_precharge; + VARIABLE Bank_precharge : Array_Bank_precharge; + VARIABLE Cmnd_precharge : Array_Cmnd_precharge; + + -- Burst Terminate variable + VARIABLE Cmnd_bst : Array_Cmnd_bst; + + -- Memory Banks + VARIABLE Bank0 : Array_ram_stor; + VARIABLE Bank1 : Array_ram_stor; + VARIABLE Bank2 : Array_ram_stor; + VARIABLE Bank3 : Array_ram_stor; + + -- Burst Counter + VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); + + -- Internal Dqs initialize + VARIABLE Dqs_int : STD_LOGIC := '0'; + + -- Data buffer for DM Mask + VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + + -- + -- Initialize empty rows + -- + PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS + VARIABLE i, j : INTEGER := 0; + BEGIN + IF Bank = "00" THEN + IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty + Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank0 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "01" THEN + IF Bank1 (Row_index) = NULL THEN + Bank1 (Row_index) := NEW Array_ram_type; + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank1 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "10" THEN + IF Bank2 (Row_index) = NULL THEN + Bank2 (Row_index) := NEW Array_ram_type; + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank2 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "11" THEN + IF Bank3 (Row_index) = NULL THEN + Bank3 (Row_index) := NEW Array_ram_type; + FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank3 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + END IF; + END; + + -- + -- Burst Counter + -- + PROCEDURE Burst_decode IS + VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); + BEGIN + -- Advance burst counter + Burst_counter := Burst_counter + 1; + + -- Burst Type + IF Mode_reg (3) = '0' THEN + Cols_temp := Cols_addr + 1; + ELSIF Mode_reg (3) = '1' THEN + Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); + Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); + Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); + END IF; + + -- Burst Length + IF Burst_length_2 = '1' THEN + Cols_addr (0) := Cols_temp (0); + ELSIF Burst_length_4 = '1' THEN + Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); + ELSIF Burst_length_8 = '1' THEN + Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); + ELSE + Cols_addr := Cols_temp; + END IF; + + -- Data counter + IF Burst_length_2 = '1' THEN + IF Burst_counter >= 2 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_4 = '1' THEN + IF Burst_counter >= 4 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_8 = '1' THEN + IF Burst_counter >= 8 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + END IF; + END; + + BEGIN + WAIT ON Sys_clk; + + -- + -- Manual Precharge Pipeline + -- + IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN + -- A10 Precharge Pipeline + A10_precharge(0) := A10_precharge(1); + A10_precharge(1) := A10_precharge(2); + A10_precharge(2) := A10_precharge(3); + A10_precharge(3) := A10_precharge(4); + A10_precharge(4) := A10_precharge(5); + A10_precharge(5) := A10_precharge(6); + A10_precharge(6) := A10_precharge(7); + A10_precharge(7) := A10_precharge(8); + A10_precharge(8) := '0'; + + -- Bank Precharge Pipeline + Bank_precharge(0) := Bank_precharge(1); + Bank_precharge(1) := Bank_precharge(2); + Bank_precharge(2) := Bank_precharge(3); + Bank_precharge(3) := Bank_precharge(4); + Bank_precharge(4) := Bank_precharge(5); + Bank_precharge(5) := Bank_precharge(6); + Bank_precharge(6) := Bank_precharge(7); + Bank_precharge(7) := Bank_precharge(8); + Bank_precharge(8) := "00"; + + -- Command Precharge Pipeline + Cmnd_precharge(0) := Cmnd_precharge(1); + Cmnd_precharge(1) := Cmnd_precharge(2); + Cmnd_precharge(2) := Cmnd_precharge(3); + Cmnd_precharge(3) := Cmnd_precharge(4); + Cmnd_precharge(4) := Cmnd_precharge(5); + Cmnd_precharge(5) := Cmnd_precharge(6); + Cmnd_precharge(6) := Cmnd_precharge(7); + Cmnd_precharge(7) := Cmnd_precharge(8); + Cmnd_precharge(8) := '0'; + + -- Terminate Read if same bank or all banks + IF ((Cmnd_precharge (0) = '1') AND + (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND + (Data_out_enable = '1')) THEN + Data_out_enable := '0'; + END IF; + END IF; + + -- + -- Burst Terminate Pipeline + -- + IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN + -- Burst Terminate pipeline + Cmnd_bst (0) := Cmnd_bst (1); + Cmnd_bst (1) := Cmnd_bst (2); + Cmnd_bst (2) := Cmnd_bst (3); + Cmnd_bst (3) := Cmnd_bst (4); + Cmnd_bst (4) := Cmnd_bst (5); + Cmnd_bst (5) := Cmnd_bst (6); + Cmnd_bst (6) := Cmnd_bst (7); + Cmnd_bst (7) := Cmnd_bst (8); + Cmnd_bst (8) := '0'; + + -- Terminate current Read + IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN + Data_out_enable := '0'; + END IF; + END IF; + + -- + -- Dq and Dqs Drivers + -- + IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN + -- Read Command Pipeline + Read_cmnd (0) := Read_cmnd (1); + Read_cmnd (1) := Read_cmnd (2); + Read_cmnd (2) := Read_cmnd (3); + Read_cmnd (3) := Read_cmnd (4); + Read_cmnd (4) := Read_cmnd (5); + Read_cmnd (5) := Read_cmnd (6); + Read_cmnd (6) := Read_cmnd (7); + Read_cmnd (7) := Read_cmnd (8); + Read_cmnd (8) := '0'; + + -- Read Bank Pipeline + Read_bank (0) := Read_bank (1); + Read_bank (1) := Read_bank (2); + Read_bank (2) := Read_bank (3); + Read_bank (3) := Read_bank (4); + Read_bank (4) := Read_bank (5); + Read_bank (5) := Read_bank (6); + Read_bank (6) := Read_bank (7); + Read_bank (7) := Read_bank (8); + Read_bank (8) := "00"; + + -- Read Column Pipeline + Read_cols (0) := Read_cols (1); + Read_cols (1) := Read_cols (2); + Read_cols (2) := Read_cols (3); + Read_cols (3) := Read_cols (4); + Read_cols (4) := Read_cols (5); + Read_cols (5) := Read_cols (6); + Read_cols (6) := Read_cols (7); + Read_cols (7) := Read_cols (8); + Read_cols (8) := (OTHERS => '0'); + + -- Initialize Read command + IF Read_cmnd (0) = '1' THEN + Data_out_enable := '1'; + Bank_addr := Read_bank (0); + Cols_addr := Read_cols (0); + Cols_brst := Cols_addr (2 DOWNTO 0); + Burst_counter := (OTHERS => '0'); + + -- Row address mux + CASE Bank_addr IS + WHEN "00" => Rows_addr := B0_row_addr; + WHEN "01" => Rows_addr := B1_row_addr; + WHEN "10" => Rows_addr := B2_row_addr; + WHEN OTHERS => Rows_addr := B3_row_addr; + END CASE; + END IF; + + -- Toggle Dqs during Read command + IF Data_out_enable = '1' THEN + Dqs_int := '0'; + IF Dqs_out = "00" THEN + Dqs_out <= "11"; + ELSIF Dqs_out = "11" THEN + Dqs_out <= "00"; + ELSE + Dqs_out <= "00"; + END IF; + ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN + Dqs_out <= "ZZ"; + END IF; + + -- Initialize Dqs for Read command + IF Read_cmnd (2) = '1' THEN + IF Data_out_enable = '0' THEN + Dqs_int := '1'; + Dqs_out <= "00"; + END IF; + END IF; + + -- Read Latch + IF Data_out_enable = '1' THEN + -- Initialize Memory + Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); + + -- Output Data + CASE Bank_addr IS + WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + END CASE; + + -- Increase Burst Counter + Burst_decode; + ELSE + Dq <= (OTHERS => 'Z'); + END IF; + END IF; + + -- + -- Write FIFO and DM Mask Logic + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + -- Write command pipeline + Write_cmnd (0) := Write_cmnd (1); + Write_cmnd (1) := Write_cmnd (2); + Write_cmnd (2) := '0'; + + -- Write command pipeline + Write_bank (0) := Write_bank (1); + Write_bank (1) := Write_bank (2); + Write_bank (2) := "00"; + + -- Write column pipeline + Write_cols (0) := Write_cols (1); + Write_cols (1) := Write_cols (2); + Write_cols (2) := (OTHERS => '0'); + + -- Initialize Write command + IF Write_cmnd (0) = '1' THEN + Data_in_enable := '1'; + Bank_addr := Write_bank (0); + Cols_addr := Write_cols (0); + Cols_brst := Cols_addr (2 DOWNTO 0); + Burst_counter := (OTHERS => '0'); + + -- Row address mux + CASE Bank_addr IS + WHEN "00" => Rows_addr := B0_row_addr; + WHEN "01" => Rows_addr := B1_row_addr; + WHEN "10" => Rows_addr := B2_row_addr; + WHEN OTHERS => Rows_addr := B3_row_addr; + END CASE; + END IF; + + -- Write data + IF Data_in_enable = '1' THEN + -- Initialize memory + Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); + + -- Write first data + IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN + -- Data Buffer + CASE Bank_addr IS + WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + END CASE; + + -- Perform DM Mask + IF Dm_pair (0) = '0' THEN + Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); + END IF; + IF Dm_pair (1) = '0' THEN + Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); + END IF; + + -- Write Data + CASE Bank_addr IS + WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + END CASE; + END IF; + + -- Increase Burst Counter + Burst_decode; + + -- Write second data + IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN + -- Data Buffer + CASE Bank_addr IS + WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); + END CASE; + + -- Perform DM Mask + IF Dm_pair (2) = '0' THEN + Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); + END IF; + IF Dm_pair (3) = '0' THEN + Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); + END IF; + + -- Write Data + CASE Bank_addr IS + WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; + END CASE; + END IF; + + -- Increase Burst Counter + Burst_decode; + + -- tWR start and tWTR check + IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN + CASE Bank_addr IS + WHEN "00" => WR_chk0 := NOW; + WHEN "01" => WR_chk1 := NOW; + WHEN "10" => WR_chk2 := NOW; + WHEN OTHERS => WR_chk3 := NOW; + END CASE; + + -- tWTR check + ASSERT (Read_enable = '0') + REPORT "tWTR violation during Read" + SEVERITY WARNING; + END IF; + END IF; + END IF; + + -- + -- Auto Precharge Calculation + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + -- Precharge counter + IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN + Count_precharge (0) := Count_precharge (0) + 1; + END IF; + IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN + Count_precharge (1) := Count_precharge (1) + 1; + END IF; + IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN + Count_precharge (2) := Count_precharge (2) + 1; + END IF; + IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN + Count_precharge (3) := Count_precharge (3) + 1; + END IF; + + -- Read with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet tRAS requirement + -- 2. BL/2 cycles after command + IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + Read_precharge(0) := '0'; + END IF; + END IF; + IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + Read_precharge(1) := '0'; + END IF; + END IF; + IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + Read_precharge(2) := '0'; + END IF; + END IF; + IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + Read_precharge(3) := '0'; + END IF; + END IF; + + -- Write with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. Meet tRAS requirement + -- 2. Two clock after last burst + -- Since tWR is time base, the model will compensate tRP + IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW - ((2 * tCK) - tWR); + Write_precharge(0) := '0'; + END IF; + END IF; + IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW - ((2 * tCK) - tWR); + Write_precharge(1) := '0'; + END IF; + END IF; + IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW - ((2 * tCK) - tWR); + Write_precharge(2) := '0'; + END IF; + END IF; + IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN + IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR + (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW - ((2 * tCK) - tWR); + Write_precharge(3) := '0'; + END IF; + END IF; + END IF; + + -- + -- DLL Counter + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + IF (DLL_Reset = '1' AND DLL_done = '0') THEN + DLL_count := DLL_count + 1; + IF (DLL_count >= 200) THEN + DLL_done := '1'; + END IF; + END IF; + END IF; + + -- + -- Control Logic + -- + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + -- Auto Refresh + IF Aref_enable = '1' THEN + -- Auto Refresh to Auto Refresh + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND + (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Auto Refresh" + SEVERITY WARNING; + + -- Precharge to Auto Refresh + ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') + REPORT "All banks must be Precharge before Auto Refresh" + SEVERITY WARNING; + + -- Record current tRFC time + RFC_chk := NOW; + END IF; + + -- Extended Load Mode Register + IF Ext_mode_enable = '1' THEN + IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN + IF (Addr (0) = '0') THEN + DLL_enable := '1'; + ELSE + DLL_enable := '0'; + END IF; + END IF; + + -- Precharge to EMR + ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') + REPORT "All bank must be Precharged before Extended Mode Register" + SEVERITY WARNING; + + -- Precharge to EMR + ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND + (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Extended Load Register" + SEVERITY WARNING; + + -- LMR/EMR to EMR + ASSERT (NOW - MRD_chk >= tMRD) + REPORT "tMRD violation during Extended Mode Register" + SEVERITY WARNING; + + -- Record current tMRD time + MRD_chk := NOW; + END IF; + + -- Load Mode Register + IF Mode_reg_enable = '1' THEN + -- Register mode + Mode_reg <= Addr; + + -- DLL Reset + IF (DLL_enable = '1' AND Addr (8) = '1') THEN + DLL_reset := '1'; + DLL_done := '0'; + DLL_count := 0; + ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN + ASSERT (FALSE) + REPORT "DLL is ENABLE: DLL RESET is require" + SEVERITY WARNING; + ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN + ASSERT (FALSE) + REPORT "DLL is DISABLE: DLL RESET will be ignored" + SEVERITY WARNING; + END IF; + + -- Precharge to LMR + ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') + REPORT "All bank must be Precharged before Load Mode Register" + SEVERITY WARNING; + + -- Precharge to EMR + ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND + (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) + REPORT "tRP violation during Load Mode Register" + SEVERITY WARNING; + + -- LMR/ELMR to LMR + ASSERT (NOW - MRD_chk >= tMRD) + REPORT "tMRD violation during Load Mode Register" + SEVERITY WARNING; + + -- Check for invalid Burst Length + ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 + (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 + (Addr (2 DOWNTO 0) = "011")) -- BL = 8 + REPORT "Invalid Burst Length during Load Mode Register" + SEVERITY WARNING; + + -- Check for invalid CAS Latency + ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 + (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 + REPORT "Invalid CAS Latency during Load Mode Register" + SEVERITY WARNING; + + -- Record current tMRD time + MRD_chk := NOW; + END IF; + + -- Active Block (latch Bank and Row Address) + IF Active_enable = '1' THEN + -- Activate an OPEN bank can corrupt data + ASSERT ((Ba = "00" AND Act_b0 = '0') OR + (Ba = "01" AND Act_b1 = '0') OR + (Ba = "10" AND Act_b2 = '0') OR + (Ba = "11" AND Act_b3 = '0')) + REPORT "Bank is already activated - data can be corrupted" + SEVERITY WARNING; + + -- Activate Bank 0 + IF Ba = "00" AND Pc_b0 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk0 >= tRC) + REPORT "tRC violation during Activate Bank 0" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk0 >= tRP) + REPORT "tRP violation during Activate Bank 0" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b0 := '1'; + Pc_b0 := '0'; + B0_row_addr := Addr; + RC_chk0 := NOW; + RCD_chk0 := NOW; + RAS_chk0 := NOW; + RAP_chk0 := NOW; + END IF; + + -- Activate Bank 1 + IF Ba = "01" AND Pc_b1 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk1 >= tRC) + REPORT "tRC violation during Activate Bank 1" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk1 >= tRP) + REPORT "tRP violation during Activate Bank 1" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b1 := '1'; + Pc_b1 := '0'; + B1_row_addr := Addr; + RC_chk1 := NOW; + RCD_chk1 := NOW; + RAS_chk1 := NOW; + RAP_chk1 := NOW; + END IF; + + -- Activate Bank 2 + IF Ba = "10" AND Pc_b2 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk2 >= tRC) + REPORT "tRC violation during Activate Bank 2" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk2 >= tRP) + REPORT "tRP violation during Activate Bank 2" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b2 := '1'; + Pc_b2 := '0'; + B2_row_addr := Addr; + RC_chk2 := NOW; + RCD_chk2 := NOW; + RAS_chk2 := NOW; + RAP_chk2 := NOW; + END IF; + + -- Activate Bank 3 + IF Ba = "11" AND Pc_b3 = '1' THEN + -- Activate to Activate (same bank) + ASSERT (NOW - RC_chk3 >= tRC) + REPORT "tRC violation during Activate Bank 3" + SEVERITY WARNING; + + -- Precharge to Active + ASSERT (NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Activate Bank 3" + SEVERITY WARNING; + + -- Record Variables for checking violation + Act_b3 := '1'; + Pc_b3 := '0'; + B3_row_addr := Addr; + RC_chk3 := NOW; + RCD_chk3 := NOW; + RAS_chk3 := NOW; + RAP_chk3 := NOW; + END IF; + + -- Activate Bank A to Activate Bank B + IF (Prev_bank /= Ba) THEN + ASSERT (NOW - RRD_chk >= tRRD) + REPORT "tRRD violation during Activate" + SEVERITY WARNING; + END IF; + + -- AutoRefresh to Activate + ASSERT (NOW - RFC_chk >= tRFC) + REPORT "tRFC violation during Activate" + SEVERITY WARNING; + + -- Record Variables for Checking Violation + RRD_chk := NOW; + Prev_bank := Ba; + END IF; + + -- Precharge Block - Consider NOP if bank already precharged or in process of precharging + IF Prech_enable = '1' THEN + -- EMR or LMR to Precharge + ASSERT (NOW - MRD_chk >= tMRD) + REPORT "tMRD violation during Precharge" + SEVERITY WARNING; + + -- Precharge Bank 0 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN + Act_b0 := '0'; + Pc_b0 := '1'; + RP_chk0 := NOW; + + -- Activate to Precharge bank 0 + ASSERT (NOW - RAS_chk0 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk0 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 1 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN + Act_b1 := '0'; + Pc_b1 := '1'; + RP_chk1 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk1 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk1 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 2 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN + Act_b2 := '0'; + Pc_b2 := '1'; + RP_chk2 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk2 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk2 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Precharge Bank 3 + IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN + Act_b3 := '0'; + Pc_b3 := '1'; + RP_chk3 := NOW; + + -- Activate to Precharge + ASSERT (NOW - RAS_chk3 >= tRAS) + REPORT "tRAS violation during Precharge" + SEVERITY WARNING; + + -- tWR violation check for Write + ASSERT (NOW - WR_chk3 >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + + -- Pipeline for READ + IF CAS_latency_15 = '1' THEN + A10_precharge (3) := Addr(10); + Bank_precharge (3) := Ba; + Cmnd_precharge (3) := '1'; + ELSIF CAS_latency_2 = '1' THEN + A10_precharge (4) := Addr(10); + Bank_precharge (4) := Ba; + Cmnd_precharge (4) := '1'; + ELSIF CAS_latency_25 = '1' THEN + A10_precharge (5) := Addr(10); + Bank_precharge (5) := Ba; + Cmnd_precharge (5) := '1'; + ELSIF CAS_latency_3 = '1' THEN + A10_precharge (6) := Addr(10); + Bank_precharge (6) := Ba; + Cmnd_precharge (6) := '1'; + ELSIF CAS_latency_4 = '1' THEN + A10_precharge (8) := Addr(10); + Bank_precharge (8) := Ba; + Cmnd_precharge (8) := '1'; + END IF; + END IF; + + -- Burst Terminate + IF Burst_term = '1' THEN + -- Pipeline for Read + IF CAS_latency_15 = '1' THEN + Cmnd_bst (3) := '1'; + ELSIF CAS_latency_2 = '1' THEN + Cmnd_bst (4) := '1'; + ELSIF CAS_latency_25 = '1' THEN + Cmnd_bst (5) := '1'; + ELSIF CAS_latency_3 = '1' THEN + Cmnd_bst (6) := '1'; + ELSIF CAS_latency_4 = '1' THEN + Cmnd_bst (8) := '1'; + END IF; + + -- Terminate Write + ASSERT (Data_in_enable = '0') + REPORT "It's illegal to Burst Terminate a Write" + SEVERITY WARNING; + + -- Terminate Read with Auto Precharge + ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND + Read_precharge (2) = '0' AND Read_precharge (3) = '0') + REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" + SEVERITY WARNING; + END IF; + + -- Read Command + IF Read_enable = '1' THEN + -- CAS Latency Pipeline + IF Cas_latency_15 = '1' THEN + Read_cmnd (3) := '1'; + Read_bank (3) := Ba; + Read_cols (3) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_2 = '1' THEN + Read_cmnd (4) := '1'; + Read_bank (4) := Ba; + Read_cols (4) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_25 = '1' THEN + Read_cmnd (5) := '1'; + Read_bank (5) := Ba; + Read_cols (5) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_3 = '1' THEN + Read_cmnd (6) := '1'; + Read_bank (6) := Ba; + Read_cols (6) := Addr (8 DOWNTO 0); + ELSIF Cas_latency_4 = '1' THEN + Read_cmnd (8) := '1'; + Read_bank (8) := Ba; + Read_cols (8) := Addr (8 DOWNTO 0); + END IF; + + -- Write to Read: Terminate Write Immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Interrupting a Read with Auto Precharge (same bank only) + ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') + REPORT "It's illegal to interrupt a Read with Auto Precharge" + SEVERITY WARNING; + + -- Activate to Read + ASSERT ((Ba = "00" AND Act_b0 = '1') OR + (Ba = "01" AND Act_b1 = '1') OR + (Ba = "10" AND Act_b2 = '1') OR + (Ba = "11" AND Act_b3 = '1')) + REPORT "Bank is not Activated for Read" + SEVERITY WARNING; + + -- Activate to Read without Auto Precharge + IF Addr (10) = '0' THEN + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Read" + SEVERITY WARNING; + END IF; + + -- Activate to Read with Auto Precharge + IF Addr (10) = '1' THEN + ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR + (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR + (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR + (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) + REPORT "tRAP violation during Read" + SEVERITY WARNING; + END IF; + + -- Auto precharge + IF Addr (10) = '1' THEN + Read_precharge (Conv_INTEGER(Ba)) := '1'; + Count_precharge (Conv_INTEGER(Ba)) := 0; + END IF; + + -- DLL Check + IF (DLL_reset = '1') THEN + ASSERT (DLL_done = '1') + REPORT "DLL RESET not complete" + SEVERITY WARNING; + END IF; + END IF; + + -- Write Command + IF Write_enable = '1' THEN + -- Pipeline for Write + Write_cmnd (2) := '1'; + Write_bank (2) := Ba; + Write_cols (2) := Addr (8 DOWNTO 0); + + -- Interrupting a Write with Auto Precharge (same bank only) + ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') + REPORT "It's illegal to interrupt a Write with Auto Precharge" + SEVERITY WARNING; + + -- Activate to Write + ASSERT ((Ba = "00" AND Act_b0 = '1') OR + (Ba = "01" AND Act_b1 = '1') OR + (Ba = "10" AND Act_b2 = '1') OR + (Ba = "11" AND Act_b3 = '1')) + REPORT "Bank is not Activated for Write" + SEVERITY WARNING; + + -- Activate to Write + ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR + (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR + (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR + (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) + REPORT "tRCD violation during Write" + SEVERITY WARNING; + + -- Auto precharge + IF Addr (10) = '1' THEN + Write_precharge (Conv_INTEGER(Ba)) := '1'; + Count_precharge (Conv_INTEGER(Ba)) := 0; + END IF; + END IF; + END IF; + END PROCESS; + + -- + -- Dqs Receiver + -- + dqs_rcvrs : PROCESS + VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); + VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); + BEGIN + WAIT ON Dqs; + -- Latch data at posedge Dqs + IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN + Dq_temp := Dq; + Dm_temp := Dm; + END IF; + -- Latch data at negedge Dqs + IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN + Dq_pair <= (Dq & Dq_temp); + Dm_pair <= (Dm & Dm_temp); + END IF; + END PROCESS; + + -- + -- Setup timing checks + -- + Setup_check : PROCESS + BEGIN + WAIT ON Sys_clk; + IF Sys_clk'EVENT AND Sys_clk = '1' THEN + ASSERT(Cke'LAST_EVENT >= tIS) + REPORT "CKE Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tIS) + REPORT "CS# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tIS) + REPORT "CAS# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tIS) + REPORT "RAS# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tIS) + REPORT "WE# Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tIS) + REPORT "ADDR Setup time violation -- tIS" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tIS) + REPORT "BA Setup time violation -- tIS" + SEVERITY WARNING; + END IF; + END PROCESS; + + -- + -- Hold timing checks + -- + Hold_check : PROCESS + BEGIN + WAIT ON Sys_clk'DELAYED (tIH); + IF Sys_clk'DELAYED (tIH) = '1' THEN + ASSERT(Cke'LAST_EVENT >= tIH) + REPORT "CKE Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tIH) + REPORT "CS# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tIH) + REPORT "CAS# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tIH) + REPORT "RAS# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tIH) + REPORT "WE# Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tIH) + REPORT "ADDR Hold time violation -- tIH" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tIH) + REPORT "BA Hold time violation -- tIH" + SEVERITY WARNING; + END IF; + END PROCESS; + +END behave; diff --git a/zpu/hdl/zpu4/src/.cvsignore b/zpu/hdl/zpu4/src/.cvsignore new file mode 100644 index 0000000..41c40a0 --- /dev/null +++ b/zpu/hdl/zpu4/src/.cvsignore @@ -0,0 +1,5 @@ +work +vsim.wlf +xilinx_device_details.xml +tcl_stacktrace.txt +vish_stacktrace.vstf diff --git a/zpu/hdl/zpu4/src/bram.vhd b/zpu/hdl/zpu4/src/bram.vhd new file mode 100644 index 0000000..435f3f4 --- /dev/null +++ b/zpu/hdl/zpu4/src/bram.vhd @@ -0,0 +1,3807 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +entity dram is +port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"800b0b0b", +1 => x"0b0b8070", +2 => x"0b0b80e5", +3 => x"d00c3a0b", +4 => x"0b0bbed7", +5 => x"04000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0bbfa72d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"0b0b0400", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"530b0b51", +38 => x"04000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"0b0b5104", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"530b0b51", +55 => x"04000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"0b0b5104", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c6040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a530b0b", +82 => x"51040000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"0607530b", +101 => x"0b510400", +102 => x"00000000", +103 => x"00000000", +104 => x"7171530b", +105 => x"0b510406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"0b0b5104", +117 => x"00000000", +118 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x"43000000", +3180 => x"64756d6d", +3181 => x"792e6578", +3182 => x"65000000", +3183 => x"00010202", +3184 => x"03030303", +3185 => x"04040404", +3186 => x"04040404", +3187 => x"05050505", +3188 => x"05050505", +3189 => x"05050505", +3190 => x"05050505", +3191 => x"06060606", +3192 => x"06060606", +3193 => x"06060606", +3194 => x"06060606", +3195 => x"06060606", +3196 => x"06060606", +3197 => x"06060606", +3198 => x"06060606", +3199 => x"07070707", +3200 => x"07070707", +3201 => x"07070707", +3202 => x"07070707", +3203 => x"07070707", +3204 => x"07070707", +3205 => x"07070707", +3206 => x"07070707", +3207 => x"07070707", +3208 => x"07070707", +3209 => x"07070707", +3210 => x"07070707", +3211 => x"07070707", +3212 => x"07070707", +3213 => x"07070707", +3214 => x"07070707", +3215 => x"08080808", +3216 => x"08080808", +3217 => x"08080808", +3218 => x"08080808", +3219 => x"08080808", +3220 => x"08080808", +3221 => x"08080808", +3222 => x"08080808", +3223 => x"08080808", +3224 => x"08080808", +3225 => x"08080808", +3226 => x"08080808", +3227 => x"08080808", +3228 => x"08080808", +3229 => x"08080808", +3230 => x"08080808", +3231 => x"08080808", +3232 => x"08080808", +3233 => x"08080808", +3234 => x"08080808", +3235 => x"08080808", +3236 => x"08080808", +3237 => x"08080808", +3238 => x"08080808", +3239 => x"08080808", +3240 => x"08080808", +3241 => x"08080808", +3242 => x"08080808", +3243 => x"08080808", +3244 => x"08080808", +3245 => x"08080808", +3246 => x"08080808", +3247 => x"00ffffff", +3248 => x"ff00ffff", +3249 => x"ffff00ff", +3250 => x"ffffff00", +3251 => x"00000000", +3252 => x"00000000", +3253 => x"00000000", +3254 => x"00003ab8", +3255 => x"000186a0", -- iterations +3256 => x"00000000", +3257 => x"00000000", +3258 => x"00000000", +3259 => x"00000000", +3260 => x"00000000", +3261 => x"00000000", +3262 => x"00000000", +3263 => x"00000000", +3264 => x"00000000", +3265 => x"00000000", +3266 => x"00000000", +3267 => x"00000000", +3268 => x"00000000", +3269 => x"ffffffff", +3270 => x"00000000", +3271 => x"00020000", +3272 => x"00000000", +3273 => x"00000000", +3274 => x"00003320", +3275 => x"00003320", +3276 => x"00003328", +3277 => x"00003328", +3278 => x"00003330", +3279 => x"00003330", +3280 => x"00003338", +3281 => x"00003338", +3282 => x"00003340", +3283 => x"00003340", +3284 => x"00003348", +3285 => x"00003348", +3286 => x"00003350", +3287 => x"00003350", +3288 => x"00003358", +3289 => x"00003358", +3290 => x"00003360", +3291 => x"00003360", +3292 => x"00003368", +3293 => x"00003368", +3294 => x"00003370", +3295 => x"00003370", +3296 => x"00003378", +3297 => x"00003378", +3298 => x"00003380", +3299 => x"00003380", +3300 => x"00003388", +3301 => x"00003388", +3302 => x"00003390", +3303 => x"00003390", +3304 => x"00003398", +3305 => x"00003398", +3306 => x"000033a0", +3307 => x"000033a0", +3308 => x"000033a8", +3309 => x"000033a8", +3310 => x"000033b0", +3311 => x"000033b0", +3312 => x"000033b8", +3313 => x"000033b8", +3314 => x"000033c0", +3315 => x"000033c0", +3316 => x"000033c8", +3317 => x"000033c8", +3318 => x"000033d0", +3319 => x"000033d0", +3320 => x"000033d8", +3321 => x"000033d8", +3322 => x"000033e0", +3323 => x"000033e0", +3324 => x"000033e8", +3325 => x"000033e8", +3326 => x"000033f0", +3327 => x"000033f0", +3328 => x"000033f8", +3329 => x"000033f8", +3330 => x"00003400", +3331 => x"00003400", +3332 => x"00003408", +3333 => x"00003408", +3334 => x"00003410", +3335 => x"00003410", +3336 => x"00003418", +3337 => x"00003418", +3338 => x"00003420", +3339 => x"00003420", +3340 => x"00003428", +3341 => x"00003428", +3342 => x"00003430", +3343 => x"00003430", +3344 => x"00003438", +3345 => x"00003438", +3346 => x"00003440", +3347 => x"00003440", +3348 => x"00003448", +3349 => x"00003448", +3350 => x"00003450", +3351 => x"00003450", +3352 => x"00003458", +3353 => x"00003458", +3354 => x"00003460", +3355 => x"00003460", +3356 => x"00003468", +3357 => x"00003468", +3358 => x"00003470", +3359 => x"00003470", +3360 => x"00003478", +3361 => x"00003478", +3362 => x"00003480", +3363 => x"00003480", +3364 => x"00003488", +3365 => x"00003488", +3366 => x"00003490", +3367 => x"00003490", +3368 => x"00003498", +3369 => x"00003498", +3370 => x"000034a0", +3371 => x"000034a0", +3372 => x"000034a8", +3373 => x"000034a8", +3374 => x"000034b0", +3375 => x"000034b0", +3376 => x"000034b8", +3377 => x"000034b8", +3378 => x"000034c0", +3379 => x"000034c0", +3380 => x"000034c8", +3381 => x"000034c8", +3382 => x"000034d0", +3383 => x"000034d0", +3384 => x"000034d8", +3385 => x"000034d8", +3386 => x"000034e0", +3387 => x"000034e0", +3388 => x"000034e8", +3389 => x"000034e8", +3390 => x"000034f0", +3391 => x"000034f0", +3392 => x"000034f8", +3393 => x"000034f8", +3394 => x"00003500", +3395 => x"00003500", +3396 => x"00003508", +3397 => x"00003508", +3398 => x"00003510", +3399 => x"00003510", +3400 => x"00003518", +3401 => x"00003518", +3402 => x"00003520", +3403 => x"00003520", +3404 => x"00003528", +3405 => x"00003528", +3406 => x"00003530", +3407 => x"00003530", +3408 => x"00003538", +3409 => x"00003538", +3410 => x"00003540", +3411 => x"00003540", +3412 => x"00003548", +3413 => x"00003548", +3414 => x"00003550", +3415 => x"00003550", +3416 => x"00003558", +3417 => x"00003558", +3418 => x"00003560", +3419 => x"00003560", +3420 => x"00003568", +3421 => x"00003568", +3422 => x"00003570", +3423 => x"00003570", +3424 => x"00003578", +3425 => x"00003578", +3426 => x"00003580", +3427 => x"00003580", +3428 => x"00003588", +3429 => x"00003588", +3430 => x"00003590", +3431 => x"00003590", +3432 => x"00003598", +3433 => x"00003598", +3434 => x"000035a0", +3435 => x"000035a0", +3436 => x"000035a8", +3437 => x"000035a8", +3438 => x"000035b0", +3439 => x"000035b0", +3440 => x"000035b8", +3441 => x"000035b8", +3442 => x"000035c0", +3443 => x"000035c0", +3444 => x"000035c8", +3445 => x"000035c8", +3446 => x"000035d0", +3447 => x"000035d0", +3448 => x"000035d8", +3449 => x"000035d8", +3450 => x"000035e0", +3451 => x"000035e0", +3452 => x"000035e8", +3453 => x"000035e8", +3454 => x"000035f0", +3455 => x"000035f0", +3456 => x"000035f8", +3457 => x"000035f8", +3458 => x"00003600", +3459 => x"00003600", +3460 => x"00003608", +3461 => x"00003608", +3462 => x"00003610", +3463 => x"00003610", +3464 => x"00003618", +3465 => x"00003618", +3466 => x"00003620", +3467 => x"00003620", +3468 => x"00003628", +3469 => x"00003628", +3470 => x"00003630", +3471 => x"00003630", +3472 => x"00003638", +3473 => x"00003638", +3474 => x"00003640", +3475 => x"00003640", +3476 => x"00003648", +3477 => x"00003648", +3478 => x"00003650", +3479 => x"00003650", +3480 => x"00003658", +3481 => x"00003658", +3482 => x"00003660", +3483 => x"00003660", +3484 => x"00003668", +3485 => x"00003668", +3486 => x"00003670", +3487 => x"00003670", +3488 => x"00003678", +3489 => x"00003678", +3490 => x"00003680", +3491 => x"00003680", +3492 => x"00003688", +3493 => x"00003688", +3494 => x"00003690", +3495 => x"00003690", +3496 => x"00003698", +3497 => x"00003698", +3498 => x"000036a0", +3499 => x"000036a0", +3500 => x"000036a8", +3501 => x"000036a8", +3502 => x"000036b0", +3503 => x"000036b0", +3504 => x"000036b8", +3505 => x"000036b8", +3506 => x"000036c0", +3507 => x"000036c0", +3508 => x"000036c8", +3509 => x"000036c8", +3510 => x"000036d0", +3511 => x"000036d0", +3512 => x"000036d8", +3513 => x"000036d8", +3514 => x"000036e0", +3515 => x"000036e0", +3516 => x"000036e8", +3517 => x"000036e8", +3518 => x"000036f0", +3519 => x"000036f0", +3520 => x"000036f8", +3521 => x"000036f8", +3522 => x"00003700", +3523 => x"00003700", +3524 => x"00003708", +3525 => x"00003708", +3526 => x"00003710", +3527 => x"00003710", +3528 => x"00003718", +3529 => x"00003718", +3530 => x"0000372c", +3531 => x"00000000", +3532 => x"00003994", +3533 => x"000039f0", +3534 => x"00003a4c", +3535 => x"00000000", +3536 => x"00000000", +3537 => x"00000000", +3538 => x"00000000", +3539 => x"00000000", +3540 => x"00000000", +3541 => x"00000000", +3542 => x"00000000", +3543 => x"00000000", +3544 => x"000031ac", +3545 => x"00000000", +3546 => x"00000000", +3547 => x"00000000", +3548 => x"00000000", +3549 => x"00000000", +3550 => x"00000000", +3551 => x"00000000", +3552 => x"00000000", +3553 => x"00000000", +3554 => x"00000000", +3555 => x"00000000", +3556 => x"00000000", +3557 => x"00000000", +3558 => x"00000000", +3559 => x"00000000", +3560 => x"00000000", +3561 => x"00000000", +3562 => x"00000000", +3563 => x"00000000", +3564 => x"00000000", +3565 => x"00000000", +3566 => x"00000000", +3567 => x"00000000", +3568 => x"00000000", +3569 => x"00000000", +3570 => x"00000000", +3571 => x"00000000", +3572 => x"00000000", +3573 => x"00000001", +3574 => x"330eabcd", +3575 => x"1234e66d", +3576 => x"deec0005", +3577 => x"000b0000", +3578 => x"00000000", +3579 => x"00000000", +3580 => x"00000000", +3581 => x"00000000", +3582 => x"00000000", +3583 => x"00000000", +3584 => x"00000000", +3585 => x"00000000", +3586 => x"00000000", +3587 => x"00000000", +3588 => x"00000000", +3589 => x"00000000", +3590 => x"00000000", +3591 => x"00000000", +3592 => x"00000000", +3593 => x"00000000", +3594 => x"00000000", +3595 => x"00000000", +3596 => x"00000000", +3597 => x"00000000", +3598 => x"00000000", +3599 => x"00000000", +3600 => x"00000000", +3601 => x"00000000", +3602 => x"00000000", +3603 => x"00000000", +3604 => x"00000000", +3605 => x"00000000", +3606 => x"00000000", +3607 => x"00000000", +3608 => x"00000000", +3609 => x"00000000", +3610 => x"00000000", +3611 => x"00000000", +3612 => x"00000000", +3613 => x"00000000", +3614 => x"00000000", +3615 => x"00000000", +3616 => x"00000000", +3617 => x"00000000", +3618 => x"00000000", +3619 => x"00000000", +3620 => x"00000000", +3621 => x"00000000", +3622 => x"00000000", +3623 => x"00000000", +3624 => x"00000000", +3625 => x"00000000", +3626 => x"00000000", +3627 => x"00000000", +3628 => x"00000000", +3629 => x"00000000", +3630 => x"00000000", +3631 => x"00000000", +3632 => x"00000000", +3633 => x"00000000", +3634 => x"00000000", +3635 => x"00000000", +3636 => x"00000000", +3637 => x"00000000", +3638 => x"00000000", +3639 => x"00000000", +3640 => x"00000000", +3641 => x"00000000", +3642 => x"00000000", +3643 => x"00000000", +3644 => x"00000000", +3645 => x"00000000", +3646 => x"00000000", +3647 => x"00000000", +3648 => x"00000000", +3649 => x"00000000", +3650 => x"00000000", +3651 => x"00000000", +3652 => x"00000000", +3653 => x"00000000", +3654 => x"00000000", +3655 => x"00000000", +3656 => x"00000000", +3657 => x"00000000", +3658 => x"00000000", +3659 => x"00000000", +3660 => x"00000000", +3661 => x"00000000", +3662 => x"00000000", +3663 => x"00000000", +3664 => x"00000000", +3665 => x"00000000", +3666 => x"00000000", +3667 => x"00000000", +3668 => x"00000000", +3669 => x"00000000", +3670 => x"00000000", +3671 => x"00000000", +3672 => x"00000000", +3673 => x"00000000", +3674 => x"00000000", +3675 => x"00000000", +3676 => x"00000000", +3677 => x"00000000", +3678 => x"00000000", +3679 => x"00000000", +3680 => x"00000000", +3681 => x"00000000", +3682 => x"00000000", +3683 => x"00000000", +3684 => x"00000000", +3685 => x"00000000", +3686 => x"00000000", +3687 => x"00000000", +3688 => x"00000000", +3689 => x"00000000", +3690 => x"00000000", +3691 => x"00000000", +3692 => x"00000000", +3693 => x"00000000", +3694 => x"00000000", +3695 => x"00000000", +3696 => x"00000000", +3697 => x"00000000", +3698 => x"00000000", +3699 => x"00000000", +3700 => x"00000000", +3701 => x"00000000", +3702 => x"00000000", +3703 => x"00000000", +3704 => x"00000000", +3705 => x"00000000", +3706 => x"00000000", +3707 => x"00000000", +3708 => x"00000000", +3709 => x"00000000", +3710 => x"00000000", +3711 => x"00000000", +3712 => x"00000000", +3713 => x"00000000", +3714 => x"00000000", +3715 => x"00000000", +3716 => x"00000000", +3717 => x"00000000", +3718 => x"00000000", +3719 => x"00000000", +3720 => x"00000000", +3721 => x"00000000", +3722 => x"00000000", +3723 => x"00000000", +3724 => x"00000000", +3725 => x"00000000", +3726 => x"00000000", +3727 => x"00000000", +3728 => x"00000000", +3729 => x"00000000", +3730 => x"00000000", +3731 => x"00000000", +3732 => x"00000000", +3733 => x"00000000", +3734 => x"00000000", +3735 => x"00000000", +3736 => x"00000000", +3737 => x"00000000", +3738 => x"00000000", +3739 => x"00000000", +3740 => x"00000000", +3741 => x"00000000", +3742 => x"00000000", +3743 => x"00000000", +3744 => x"00000000", +3745 => x"00000000", +3746 => x"00000000", +3747 => x"00000000", +3748 => x"00000000", +3749 => x"00000000", +3750 => x"00000000", +3751 => x"00000000", +3752 => x"00000000", +3753 => x"00000000", +3754 => x"000031b0", +3755 => x"ffffffff", +3756 => x"00000000", +3757 => x"ffffffff", +3758 => x"00000000", + others => x"00000000" +); + +begin + +mem_busy <= '0'; + +process (clk) +begin + if (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(conv_integer(mem_addr)) := mem_write; + end if; + mem_read <= ram(conv_integer(mem_addr)); + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/zpu4/src/bram_dmips.vhd b/zpu/hdl/zpu4/src/bram_dmips.vhd new file mode 100644 index 0000000..1c85e0d --- /dev/null +++ b/zpu/hdl/zpu4/src/bram_dmips.vhd @@ -0,0 +1,3717 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end dualport_ram; + +architecture dualport_ram_arch of dualport_ram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80e2a40c", +3 => x"3a0b0b80", +4 => x"c6fc0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c7c32d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", 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x"0000329c", +3243 => x"000032a4", +3244 => x"000032a4", +3245 => x"000032ac", +3246 => x"000032ac", +3247 => x"000032b4", +3248 => x"000032b4", +3249 => x"000032bc", +3250 => x"000032bc", +3251 => x"000032c4", +3252 => x"000032c4", +3253 => x"000032cc", +3254 => x"000032cc", +3255 => x"000032d4", +3256 => x"000032d4", +3257 => x"000032dc", +3258 => x"000032dc", +3259 => x"000032e4", +3260 => x"000032e4", +3261 => x"000032ec", +3262 => x"000032ec", +3263 => x"000032f4", +3264 => x"000032f4", +3265 => x"000032fc", +3266 => x"000032fc", +3267 => x"00003304", +3268 => x"00003304", +3269 => x"0000330c", +3270 => x"0000330c", +3271 => x"00003314", +3272 => x"00003314", +3273 => x"0000331c", +3274 => x"0000331c", +3275 => x"00003324", +3276 => x"00003324", +3277 => x"0000332c", +3278 => x"0000332c", +3279 => x"00003334", +3280 => x"00003334", +3281 => x"0000333c", +3282 => x"0000333c", +3283 => x"00003344", +3284 => x"00003344", +3285 => x"0000334c", +3286 => x"0000334c", +3287 => x"00003354", +3288 => x"00003354", +3289 => x"0000335c", +3290 => x"0000335c", +3291 => x"00003364", +3292 => x"00003364", +3293 => x"0000336c", +3294 => x"0000336c", +3295 => x"00003374", +3296 => x"00003374", +3297 => x"0000337c", +3298 => x"0000337c", +3299 => x"00003384", +3300 => x"00003384", +3301 => x"0000338c", +3302 => x"0000338c", +3303 => x"00003394", +3304 => x"00003394", +3305 => x"0000339c", +3306 => x"0000339c", +3307 => x"000033a4", +3308 => x"000033a4", +3309 => x"000033ac", +3310 => x"000033ac", +3311 => x"000033b4", +3312 => x"000033b4", +3313 => x"000033bc", +3314 => x"000033bc", +3315 => x"000033c4", +3316 => x"000033c4", +3317 => x"000033cc", +3318 => x"000033cc", +3319 => x"000033d4", +3320 => x"000033d4", +3321 => x"000033dc", +3322 => x"000033dc", +3323 => x"000033e4", +3324 => x"000033e4", +3325 => x"000033ec", +3326 => x"000033ec", +3327 => x"000033f4", +3328 => x"000033f4", +3329 => x"000033fc", +3330 => x"000033fc", +3331 => x"00003404", +3332 => x"00003404", +3333 => x"0000340c", +3334 => x"0000340c", +3335 => x"00003414", +3336 => x"00003414", +3337 => x"0000341c", +3338 => x"0000341c", +3339 => x"00003424", +3340 => x"00003424", +3341 => x"0000342c", +3342 => x"0000342c", +3343 => x"00003434", +3344 => x"00003434", +3345 => x"0000343c", +3346 => x"0000343c", +3347 => x"00003444", +3348 => x"00003444", +3349 => x"0000344c", +3350 => x"0000344c", +3351 => x"00003454", +3352 => x"00003454", +3353 => x"0000345c", +3354 => x"0000345c", +3355 => x"00003464", +3356 => x"00003464", +3357 => x"0000346c", +3358 => x"0000346c", +3359 => x"00003474", +3360 => x"00003474", +3361 => x"0000347c", +3362 => x"0000347c", +3363 => x"00003484", +3364 => x"00003484", +3365 => x"0000348c", +3366 => x"0000348c", +3367 => x"00003494", +3368 => x"00003494", +3369 => x"0000349c", +3370 => x"0000349c", +3371 => x"000034a4", +3372 => x"000034a4", +3373 => x"000034ac", +3374 => x"000034ac", +3375 => x"000034b4", +3376 => x"000034b4", +3377 => x"000034bc", +3378 => x"000034bc", +3379 => x"000034c4", +3380 => x"000034c4", +3381 => x"000034cc", +3382 => x"000034cc", +3383 => x"000034d4", +3384 => x"000034d4", +3385 => x"000034dc", +3386 => x"000034dc", +3387 => x"000034e4", +3388 => x"000034e4", +3389 => x"000034ec", +3390 => x"000034ec", +3391 => x"000034f4", +3392 => x"000034f4", +3393 => x"000034fc", +3394 => x"000034fc", +3395 => x"00003504", +3396 => x"00003504", +3397 => x"0000350c", +3398 => x"0000350c", +3399 => x"00003514", +3400 => x"00003514", +3401 => x"0000351c", +3402 => x"0000351c", +3403 => x"00003524", +3404 => x"00003524", +3405 => x"0000352c", +3406 => x"0000352c", +3407 => x"00003534", +3408 => x"00003534", +3409 => x"0000353c", +3410 => x"0000353c", +3411 => x"00003544", +3412 => x"00003544", +3413 => x"0000354c", +3414 => x"0000354c", +3415 => x"00003554", +3416 => x"00003554", +3417 => x"0000355c", +3418 => x"0000355c", +3419 => x"00003564", +3420 => x"00003564", +3421 => x"0000356c", +3422 => x"0000356c", +3423 => x"00003580", +3424 => x"00000000", +3425 => x"000037e8", +3426 => x"00003844", +3427 => x"000038a0", +3428 => x"00000000", +3429 => x"00000000", +3430 => x"00000000", +3431 => x"00000000", +3432 => x"00000000", +3433 => x"00000000", +3434 => x"00000000", +3435 => x"00000000", +3436 => x"00000000", +3437 => x"00003100", +3438 => x"00000000", +3439 => x"00000000", +3440 => x"00000000", +3441 => x"00000000", +3442 => x"00000000", +3443 => x"00000000", +3444 => x"00000000", +3445 => x"00000000", +3446 => x"00000000", +3447 => x"00000000", +3448 => x"00000000", +3449 => x"00000000", +3450 => x"00000000", +3451 => x"00000000", +3452 => x"00000000", +3453 => x"00000000", +3454 => x"00000000", +3455 => x"00000000", +3456 => x"00000000", +3457 => x"00000000", +3458 => x"00000000", +3459 => x"00000000", +3460 => x"00000000", +3461 => x"00000000", +3462 => x"00000000", +3463 => x"00000000", +3464 => x"00000000", +3465 => x"00000000", +3466 => x"00000001", +3467 => x"330eabcd", +3468 => x"1234e66d", +3469 => x"deec0005", +3470 => x"000b0000", +3471 => x"00000000", +3472 => x"00000000", +3473 => x"00000000", +3474 => x"00000000", +3475 => x"00000000", +3476 => x"00000000", +3477 => x"00000000", +3478 => x"00000000", +3479 => x"00000000", +3480 => x"00000000", +3481 => x"00000000", +3482 => x"00000000", +3483 => x"00000000", +3484 => x"00000000", +3485 => x"00000000", +3486 => x"00000000", +3487 => x"00000000", +3488 => x"00000000", +3489 => x"00000000", +3490 => x"00000000", +3491 => x"00000000", +3492 => x"00000000", +3493 => x"00000000", +3494 => x"00000000", +3495 => x"00000000", +3496 => x"00000000", +3497 => x"00000000", +3498 => x"00000000", +3499 => x"00000000", +3500 => x"00000000", +3501 => x"00000000", +3502 => x"00000000", +3503 => x"00000000", +3504 => x"00000000", +3505 => x"00000000", +3506 => x"00000000", +3507 => x"00000000", +3508 => x"00000000", +3509 => x"00000000", +3510 => x"00000000", +3511 => x"00000000", +3512 => x"00000000", +3513 => x"00000000", +3514 => x"00000000", +3515 => x"00000000", +3516 => x"00000000", +3517 => x"00000000", +3518 => x"00000000", +3519 => x"00000000", +3520 => x"00000000", +3521 => x"00000000", +3522 => x"00000000", +3523 => x"00000000", +3524 => x"00000000", +3525 => x"00000000", +3526 => x"00000000", +3527 => x"00000000", +3528 => x"00000000", +3529 => x"00000000", +3530 => x"00000000", +3531 => x"00000000", +3532 => x"00000000", +3533 => x"00000000", +3534 => x"00000000", +3535 => x"00000000", +3536 => x"00000000", +3537 => x"00000000", +3538 => x"00000000", +3539 => x"00000000", +3540 => x"00000000", +3541 => x"00000000", +3542 => x"00000000", +3543 => x"00000000", +3544 => x"00000000", +3545 => x"00000000", +3546 => x"00000000", +3547 => x"00000000", +3548 => x"00000000", +3549 => x"00000000", +3550 => x"00000000", +3551 => x"00000000", +3552 => x"00000000", +3553 => x"00000000", +3554 => x"00000000", +3555 => x"00000000", +3556 => x"00000000", +3557 => x"00000000", +3558 => x"00000000", +3559 => x"00000000", +3560 => x"00000000", +3561 => x"00000000", +3562 => x"00000000", +3563 => x"00000000", +3564 => x"00000000", +3565 => x"00000000", +3566 => x"00000000", +3567 => x"00000000", +3568 => x"00000000", +3569 => x"00000000", +3570 => x"00000000", +3571 => x"00000000", +3572 => x"00000000", +3573 => x"00000000", +3574 => x"00000000", +3575 => x"00000000", +3576 => x"00000000", +3577 => x"00000000", +3578 => x"00000000", +3579 => x"00000000", +3580 => x"00000000", +3581 => x"00000000", +3582 => x"00000000", +3583 => x"00000000", +3584 => x"00000000", +3585 => x"00000000", +3586 => x"00000000", +3587 => x"00000000", +3588 => x"00000000", +3589 => x"00000000", +3590 => x"00000000", +3591 => x"00000000", +3592 => x"00000000", +3593 => x"00000000", +3594 => x"00000000", +3595 => x"00000000", +3596 => x"00000000", +3597 => x"00000000", +3598 => x"00000000", +3599 => x"00000000", +3600 => x"00000000", +3601 => x"00000000", +3602 => x"00000000", +3603 => x"00000000", +3604 => x"00000000", +3605 => x"00000000", +3606 => x"00000000", +3607 => x"00000000", +3608 => x"00000000", +3609 => x"00000000", +3610 => x"00000000", +3611 => x"00000000", +3612 => x"00000000", +3613 => x"00000000", +3614 => x"00000000", +3615 => x"00000000", +3616 => x"00000000", +3617 => x"00000000", +3618 => x"00000000", +3619 => x"00000000", +3620 => x"00000000", +3621 => x"00000000", +3622 => x"00000000", +3623 => x"00000000", +3624 => x"00000000", +3625 => x"00000000", +3626 => x"00000000", +3627 => x"00000000", +3628 => x"00000000", +3629 => x"00000000", +3630 => x"00000000", +3631 => x"00000000", +3632 => x"00000000", +3633 => x"00000000", +3634 => x"00000000", +3635 => x"00000000", +3636 => x"00000000", +3637 => x"00000000", +3638 => x"00000000", +3639 => x"00000000", +3640 => x"00000000", +3641 => x"00000000", +3642 => x"00000000", +3643 => x"00000000", +3644 => x"00000000", +3645 => x"00000000", +3646 => x"00000000", +3647 => x"00003104", +3648 => x"ffffffff", +3649 => x"00000000", +3650 => x"ffffffff", +3651 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then + report "write collision" severity failure; + end if; + + if (memAWriteEnable = '1') then + ram(conv_integer(memAAddr)) := memAWrite; + memARead <= memAWrite; + else + memARead <= ram(conv_integer(memAAddr)); + end if; + end if; +end process; + +process (clk) +begin + if (clk'event and clk = '1') then + if (memBWriteEnable = '1') then + ram(conv_integer(memBAddr)) := memBWrite; + memBRead <= memBWrite; + else + memBRead <= ram(conv_integer(memBAddr)); + end if; + end if; +end process; + + + + +end dualport_ram_arch; diff --git a/zpu/hdl/zpu4/src/build.xml b/zpu/hdl/zpu4/src/build.xml new file mode 100644 index 0000000..e1b268a --- /dev/null +++ b/zpu/hdl/zpu4/src/build.xml @@ -0,0 +1,114 @@ + + + + + + + eCosBoard firmware build file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/clocks.vhd b/zpu/hdl/zpu4/src/clocks.vhd new file mode 100644 index 0000000..a352b3c --- /dev/null +++ b/zpu/hdl/zpu4/src/clocks.vhd @@ -0,0 +1,246 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity clocks is + port ( areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0)); +end clocks; + +architecture behave of clocks is + +signal low : std_logic; + +signal cpu_clk_in : std_logic; +signal sdr_clk_fb_in : std_logic; + +signal dcm_cpu1 : std_logic; +signal dcm_cpu2 : std_logic; +signal dcm_cpu2_dum : std_logic; +signal dcm_cpu4 : std_logic; +signal dcm_ddr2 : std_logic; +signal dcm_ddr2_2x : std_logic; + +signal cpu_clk_int : std_logic; +signal cpu_clk_2x_int : std_logic; +signal cpu_clk_2x_dum_int : std_logic; +signal cpu_clk_4x_int : std_logic; +signal ddr_in_clk_int : std_logic; +signal ddr_in_clk_2x_int : std_logic; + +signal dcm1_locked_del : std_logic; +signal dcm2_locked_del : std_logic; +signal dcm2_reset : std_logic; +signal dcm3_reset : std_logic; + +signal locked_int : std_logic_vector(2 downto 0); +signal del_addr : std_logic_vector(3 downto 0); + +begin + + low <= '0'; + del_addr <= "1111"; + + cpu_clk <= cpu_clk_int; + cpu_clk_2x <= cpu_clk_2x_int; + cpu_clk_4x <= cpu_clk_4x_int; + ddr_in_clk <= ddr_in_clk_int; + ddr_in_clk_2x <= ddr_in_clk_2x_int; + locked <= locked_int; + + + CPU_IBUFG: + IBUFG port map ( + O => cpu_clk_in, + I => cpu_clk_p); + + SDR_FB_IBUFG: + IBUFG port map ( + O => sdr_clk_fb_in, + I => sdr_clk_fb_p); + + dcm2_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm1_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(0)); + + dcm2_reset <= not(dcm1_locked_del); + + dcm3_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm2_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(1)); + + dcm3_reset <= not(dcm2_locked_del); + + cpu1_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 15.625, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu2, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(0), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_int, -- DCM clock feedback + CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => areset); -- DCM asynchronous reset input + + cpu2_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu4, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(1), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback + CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm2_reset); -- DCM asynchronous reset input + + ddr_read_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE +-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255 +-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(2), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => ddr_in_clk_int, -- DCM clock feedback + CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm3_reset); -- DCM asynchronous reset input + + cpu1: + BUFG port map ( + I => dcm_cpu1, + O => cpu_clk_int); + + cpu2: + BUFG port map ( + I => dcm_cpu2, + O => cpu_clk_2x_int); + + cpu2_dum: + BUFG port map ( + I => dcm_cpu2_dum, + O => cpu_clk_2x_dum_int); + + cpu4: + BUFG port map ( + I => dcm_cpu4, + O => cpu_clk_4x_int); + + ddr_clk: + BUFG port map ( + I => dcm_ddr2, + O => ddr_in_clk_int); + + ddr_clk_2x: + BUFG port map ( + I => dcm_ddr2_2x, + O => ddr_in_clk_2x_int); + +end behave; \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace.do b/zpu/hdl/zpu4/src/dmipssmalltrace.do new file mode 100644 index 0000000..eb4c6fe --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipssmalltrace.do @@ -0,0 +1,26 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_small.vhd +vcom -93 -explicit bram_dmips.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +add wave -recursive fpga_top/zpu/* +#--add wave -recursive fpga_top/ioMap/* +#add wave -recursive fpga_top/* +view structure + + +# run ZPU +run 5 ms diff --git a/zpu/hdl/zpu4/src/dmipstrace.do b/zpu/hdl/zpu4/src/dmipstrace.do new file mode 100644 index 0000000..8d5f430 --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipstrace.do @@ -0,0 +1,25 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +add wave -recursive fpga_top/zpu/* +#--add wave -recursive fpga_top/ioMap/* +#add wave -recursive fpga_top/* +view structure + + +# run ZPU +run 5 ms diff --git a/zpu/hdl/zpu4/src/dmipstraceintstack.do b/zpu/hdl/zpu4/src/dmipstraceintstack.do new file mode 100644 index 0000000..b2addb4 --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipstraceintstack.do @@ -0,0 +1,25 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_intstack.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +add wave -recursive fpga_top/zpu/* +#--add wave -recursive fpga_top/ioMap/* +#add wave -recursive fpga_top/* +view structure + + +# run ZPU +run 5 ms diff --git a/zpu/hdl/zpu4/src/dram_dmips.vhd b/zpu/hdl/zpu4/src/dram_dmips.vhd new file mode 100644 index 0000000..e63a27a --- /dev/null +++ b/zpu/hdl/zpu4/src/dram_dmips.vhd @@ -0,0 +1,3702 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dram is +port (clk : in std_logic; +areset : std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80e2a40c", +3 => x"3a0b0b80", +4 => x"c6fc0400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c7c32d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80e2", +162 => x"90738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0baf", +171 => x"ac2d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0baf", +179 => x"f02d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80e2a00c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", +237 => x"00000000", +238 => x"00000000", +239 => x"00000000", +240 => x"00000000", +241 => x"00000000", +242 => x"00000000", +243 => x"00000000", +244 => x"00000000", +245 => x"00000000", +246 => x"00000000", +247 => x"00000000", +248 => x"717105ff", +249 => x"05715351", +250 => x"020d0400", +251 => x"00000000", +252 => x"00000000", +253 => x"00000000", +254 => x"00000000", +255 => x"00000000", +256 => x"83d93f80", +257 => x"cbcf3f04", +258 => x"10101010", +259 => x"10101010", +260 => x"10101010", +261 => x"10101010", +262 => x"10101010", +263 => x"10101010", +264 => x"10101010", +265 => x"10101053", +266 => x"51047381", +267 => x"ff067383", +268 => x"06098105", +269 => x"83051010", +270 => x"102b0772", +271 => x"fc060c51", +272 => x"51043c04", +273 => x"72728072", +274 => x"8106ff05", +275 => x"09720605", +276 => x"71105272", +277 => x"0a100a53", +278 => x"72ed3851", +279 => x"51535104", +280 => x"ff3d0d0b", +281 => x"0b80f294", +282 => x"08528412", +283 => x"08708106", +284 => x"515170f6", +285 => x"38710881", +286 => x"ff06800c", +287 => x"833d0d04", +288 => x"ff3d0d0b", +289 => x"0b80f294", +290 => x"08528412", +291 => x"08700a10", +292 => x"0a708106", +293 => x"51515170", +294 => x"f1387372", +295 => x"0c833d0d", +296 => x"0480e2a0", +297 => x"08802ea8", +298 => x"38838080", +299 => x"0b0b0b80", +300 => x"f2940c82", +301 => x"a0800b0b", +302 => x"0b80f298", +303 => x"0c829080", +304 => x"0b80f2a8", +305 => x"0c0b0b80", +306 => x"f29c0b80", +307 => x"f2ac0c04", +308 => x"f8808080", +309 => x"a40b0b0b", +310 => x"80f2940c", +311 => x"f8808082", +312 => x"800b0b0b", +313 => x"80f2980c", +314 => x"f8808084", +315 => x"800b80f2", +316 => x"a80cf880", +317 => x"8080940b", +318 => x"80f2ac0c", +319 => x"f8808080", +320 => x"9c0b80f2", +321 => x"a40cf880", +322 => x"8080a00b", +323 => x"80f2b00c", +324 => x"04f23d0d", +325 => x"600b0b80", +326 => x"f2980856", +327 => x"5d82750c", +328 => x"8059805a", +329 => x"800b8f3d", +330 => x"71101017", +331 => x"70085957", +332 => x"5d5b8076", +333 => x"81ff067c", +334 => x"832b5658", +335 => x"5276537b", +336 => x"519af33f", +337 => x"7d7f7a72", +338 => x"077c7207", +339 => x"71716081", +340 => x"05415f5d", +341 => x"5b595755", +342 => x"7a8724bb", +343 => x"380b0b80", +344 => x"f298087b", +345 => x"10101170", +346 => x"08585155", +347 => x"807681ff", +348 => x"067c832b", +349 => x"56585276", +350 => x"537b519a", +351 => x"b93f7d7f", +352 => x"7a72077c", +353 => x"72077171", +354 => x"60810541", +355 => x"5f5d5b59", +356 => x"5755877b", +357 => x"25c73876", +358 => x"7d0c7784", +359 => x"1e0c7c80", +360 => x"0c903d0d", +361 => x"04ff3d0d", +362 => x"80f2a033", +363 => x"5170a738", +364 => x"80e2ac08", +365 => x"70085252", +366 => x"70802e94", +367 => x"38841280", +368 => x"e2ac0c70", +369 => x"2d80e2ac", +370 => x"08700852", +371 => x"5270ee38", +372 => x"810b80f2", +373 => x"a034833d", +374 => x"0d040480", +375 => x"3d0d0b0b", +376 => x"80f29008", +377 => x"802e8e38", +378 => x"0b0b0b0b", +379 => x"800b802e", +380 => x"09810685", +381 => x"38823d0d", +382 => x"040b0b80", +383 => x"f290510b", +384 => x"0b0bf3fc", +385 => x"3f823d0d", +386 => x"0404ff3d", +387 => x"0d028f05", +388 => x"3352718a", +389 => x"2e8a3871", +390 => x"51fce53f", +391 => x"833d0d04", +392 => x"8d51fcdc", +393 => x"3f7151fc", +394 => x"d73f833d", +395 => x"0d04ce3d", +396 => x"0db53d70", +397 => x"70840552", +398 => x"088c8a5c", +399 => x"56a53d5e", +400 => x"5c807570", +401 => x"81055733", +402 => x"765b5558", +403 => x"73782e80", +404 => x"c1388e3d", +405 => x"5b73a52e", +406 => x"09810680", +407 => x"c5387870", +408 => x"81055a33", +409 => x"547380e4", +410 => x"2e81b638", +411 => x"7380e424", +412 => x"80c63873", +413 => x"80e32ea1", +414 => x"388052a5", +415 => x"51792d80", +416 => x"52735179", +417 => x"2d821858", +418 => x"78708105", +419 => x"5a335473", +420 => x"c4387780", +421 => x"0cb43d0d", +422 => x"047b841d", +423 => x"83123356", +424 => x"5d578052", +425 => x"7351792d", +426 => x"81187970", +427 => x"81055b33", +428 => x"555873ff", +429 => x"a038db39", +430 => x"7380f32e", +431 => x"098106ff", +432 => x"b8387b84", +433 => x"1d710859", +434 => x"5d568077", +435 => x"33555673", +436 => x"762e8d38", +437 => x"81167018", +438 => x"70335755", +439 => x"5674f538", +440 => x"ff165580", +441 => x"7625ffa0", +442 => x"38767081", +443 => x"05583354", +444 => x"80527351", +445 => x"792d8118", +446 => x"75ff1757", +447 => x"57588076", +448 => x"25ff8538", +449 => x"76708105", +450 => x"58335480", +451 => x"52735179", +452 => x"2d811875", +453 => x"ff175757", +454 => x"58758024", +455 => x"cc38fee8", +456 => x"397b841d", +457 => x"71087071", +458 => x"9f2c5953", +459 => x"595d5680", +460 => x"75248195", +461 => x"38757d7c", +462 => x"58565480", +463 => x"5773772e", +464 => x"098106b6", +465 => x"38b07b34", +466 => x"02b50556", +467 => x"7a762e97", +468 => x"38ff1656", +469 => x"75337570", +470 => x"81055734", +471 => x"8117577a", +472 => x"762e0981", +473 => x"06eb3880", +474 => x"7534767d", +475 => x"ff125758", +476 => x"56758024", +477 => x"fef338fe", +478 => x"8f398a52", +479 => x"7351a0f0", +480 => x"3f80080b", +481 => x"0b80d484", +482 => x"05337670", +483 => x"81055834", +484 => x"8a527351", +485 => x"a0963f80", +486 => x"08548008", +487 => x"802effac", +488 => x"388a5273", +489 => x"51a0c93f", +490 => x"80080b0b", +491 => x"80d48405", +492 => x"33767081", +493 => x"0558348a", +494 => x"5273519f", +495 => x"ef3f8008", +496 => x"548008ff", +497 => x"b538ff84", +498 => x"39745276", +499 => x"53b43dff", +500 => x"b8055195", +501 => x"b63fa33d", +502 => x"0856fed9", +503 => x"39803d0d", +504 => x"80c10b81", +505 => x"c0f43480", +506 => x"0b81c2d0", +507 => x"0c70800c", +508 => x"823d0d04", +509 => x"ff3d0d80", +510 => x"0b81c0f4", +511 => x"33525270", +512 => x"80c12e99", +513 => x"387181c2", +514 => x"d0080781", +515 => x"c2d00c80", +516 => x"c20b81c0", +517 => x"f8347080", +518 => x"0c833d0d", +519 => x"04810b81", +520 => x"c2d00807", +521 => x"81c2d00c", +522 => x"80c20b81", +523 => x"c0f83470", +524 => x"800c833d", +525 => x"0d04fd3d", +526 => x"0d757008", +527 => x"8a055353", +528 => x"81c0f433", +529 => x"517080c1", +530 => x"2e8b3873", +531 => x"f3387080", +532 => x"0c853d0d", +533 => x"04ff1270", +534 => x"81c0f008", +535 => x"31740c80", +536 => x"0c853d0d", +537 => x"04fc3d0d", +538 => x"81c0fc08", +539 => x"5574802e", +540 => x"8c387675", +541 => x"08710c81", +542 => x"c0fc0856", +543 => x"548c1553", +544 => x"81c0f008", +545 => x"528a5190", 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x"08080808", +3136 => x"43000000", +3137 => x"64756d6d", +3138 => x"792e6578", +3139 => x"65000000", +3140 => x"00ffffff", +3141 => x"ff00ffff", +3142 => x"ffff00ff", +3143 => x"ffffff00", +3144 => x"00000000", +3145 => x"00000000", +3146 => x"00000000", +3147 => x"0000390c", +3148 => x"000004d2", -- iterations 0x4d2=1234 +3149 => x"00000000", +3150 => x"00000000", +3151 => x"00000000", +3152 => x"00000000", +3153 => x"00000000", +3154 => x"00000000", +3155 => x"00000000", +3156 => x"00000000", +3157 => x"00000000", +3158 => x"00000000", +3159 => x"00000000", +3160 => x"00000000", +3161 => x"00000000", +3162 => x"ffffffff", +3163 => x"00000000", +3164 => x"00020000", +3165 => x"00000000", +3166 => x"00000000", +3167 => x"00003174", +3168 => x"00003174", +3169 => x"0000317c", +3170 => x"0000317c", +3171 => x"00003184", +3172 => x"00003184", +3173 => x"0000318c", +3174 => x"0000318c", +3175 => x"00003194", +3176 => x"00003194", +3177 => x"0000319c", +3178 => x"0000319c", +3179 => x"000031a4", +3180 => x"000031a4", +3181 => x"000031ac", +3182 => x"000031ac", +3183 => x"000031b4", +3184 => x"000031b4", +3185 => x"000031bc", +3186 => x"000031bc", +3187 => x"000031c4", +3188 => x"000031c4", +3189 => x"000031cc", +3190 => x"000031cc", +3191 => x"000031d4", +3192 => x"000031d4", +3193 => x"000031dc", +3194 => x"000031dc", +3195 => x"000031e4", +3196 => x"000031e4", +3197 => x"000031ec", +3198 => x"000031ec", +3199 => x"000031f4", +3200 => x"000031f4", +3201 => x"000031fc", +3202 => x"000031fc", +3203 => x"00003204", +3204 => x"00003204", +3205 => x"0000320c", +3206 => x"0000320c", +3207 => x"00003214", +3208 => x"00003214", +3209 => x"0000321c", +3210 => x"0000321c", +3211 => x"00003224", +3212 => x"00003224", +3213 => x"0000322c", +3214 => x"0000322c", +3215 => x"00003234", +3216 => x"00003234", +3217 => x"0000323c", +3218 => x"0000323c", +3219 => x"00003244", +3220 => x"00003244", +3221 => x"0000324c", +3222 => x"0000324c", +3223 => x"00003254", +3224 => x"00003254", +3225 => x"0000325c", +3226 => x"0000325c", +3227 => x"00003264", +3228 => x"00003264", +3229 => x"0000326c", +3230 => x"0000326c", +3231 => x"00003274", +3232 => x"00003274", +3233 => x"0000327c", +3234 => x"0000327c", +3235 => x"00003284", +3236 => x"00003284", +3237 => x"0000328c", +3238 => x"0000328c", +3239 => x"00003294", +3240 => x"00003294", +3241 => x"0000329c", +3242 => x"0000329c", +3243 => x"000032a4", +3244 => x"000032a4", +3245 => x"000032ac", +3246 => x"000032ac", +3247 => x"000032b4", +3248 => x"000032b4", +3249 => x"000032bc", +3250 => x"000032bc", +3251 => x"000032c4", +3252 => x"000032c4", +3253 => x"000032cc", +3254 => x"000032cc", +3255 => x"000032d4", +3256 => x"000032d4", +3257 => x"000032dc", +3258 => x"000032dc", +3259 => x"000032e4", +3260 => x"000032e4", +3261 => x"000032ec", +3262 => x"000032ec", +3263 => x"000032f4", +3264 => x"000032f4", +3265 => x"000032fc", +3266 => x"000032fc", +3267 => x"00003304", +3268 => x"00003304", +3269 => x"0000330c", +3270 => x"0000330c", +3271 => x"00003314", +3272 => x"00003314", +3273 => x"0000331c", +3274 => x"0000331c", +3275 => x"00003324", +3276 => x"00003324", +3277 => x"0000332c", +3278 => x"0000332c", +3279 => x"00003334", +3280 => x"00003334", +3281 => x"0000333c", +3282 => x"0000333c", +3283 => x"00003344", +3284 => x"00003344", +3285 => x"0000334c", +3286 => x"0000334c", +3287 => x"00003354", +3288 => x"00003354", +3289 => x"0000335c", +3290 => x"0000335c", +3291 => x"00003364", +3292 => x"00003364", +3293 => x"0000336c", +3294 => x"0000336c", +3295 => x"00003374", +3296 => x"00003374", +3297 => x"0000337c", +3298 => x"0000337c", +3299 => x"00003384", +3300 => x"00003384", +3301 => x"0000338c", +3302 => x"0000338c", +3303 => x"00003394", +3304 => x"00003394", +3305 => x"0000339c", +3306 => x"0000339c", +3307 => x"000033a4", +3308 => x"000033a4", +3309 => x"000033ac", +3310 => x"000033ac", +3311 => x"000033b4", +3312 => x"000033b4", +3313 => x"000033bc", +3314 => x"000033bc", +3315 => x"000033c4", +3316 => x"000033c4", +3317 => x"000033cc", +3318 => x"000033cc", +3319 => x"000033d4", +3320 => x"000033d4", +3321 => x"000033dc", +3322 => x"000033dc", +3323 => x"000033e4", +3324 => x"000033e4", +3325 => x"000033ec", +3326 => x"000033ec", +3327 => x"000033f4", +3328 => x"000033f4", +3329 => x"000033fc", +3330 => x"000033fc", +3331 => x"00003404", +3332 => x"00003404", +3333 => x"0000340c", +3334 => x"0000340c", +3335 => x"00003414", +3336 => x"00003414", +3337 => x"0000341c", +3338 => x"0000341c", +3339 => x"00003424", +3340 => x"00003424", +3341 => x"0000342c", +3342 => x"0000342c", +3343 => x"00003434", +3344 => x"00003434", +3345 => x"0000343c", +3346 => x"0000343c", +3347 => x"00003444", +3348 => x"00003444", +3349 => x"0000344c", +3350 => x"0000344c", +3351 => x"00003454", +3352 => x"00003454", +3353 => x"0000345c", +3354 => x"0000345c", +3355 => x"00003464", +3356 => x"00003464", +3357 => x"0000346c", +3358 => x"0000346c", +3359 => x"00003474", +3360 => x"00003474", +3361 => x"0000347c", +3362 => x"0000347c", +3363 => x"00003484", +3364 => x"00003484", +3365 => x"0000348c", +3366 => x"0000348c", +3367 => x"00003494", +3368 => x"00003494", +3369 => x"0000349c", +3370 => x"0000349c", +3371 => x"000034a4", +3372 => x"000034a4", +3373 => x"000034ac", +3374 => x"000034ac", +3375 => x"000034b4", +3376 => x"000034b4", +3377 => x"000034bc", +3378 => x"000034bc", +3379 => x"000034c4", +3380 => x"000034c4", +3381 => x"000034cc", +3382 => x"000034cc", +3383 => x"000034d4", +3384 => x"000034d4", +3385 => x"000034dc", +3386 => x"000034dc", +3387 => x"000034e4", +3388 => x"000034e4", +3389 => x"000034ec", +3390 => x"000034ec", +3391 => x"000034f4", +3392 => x"000034f4", +3393 => x"000034fc", +3394 => x"000034fc", +3395 => x"00003504", +3396 => x"00003504", +3397 => x"0000350c", +3398 => x"0000350c", +3399 => x"00003514", +3400 => x"00003514", +3401 => x"0000351c", +3402 => x"0000351c", +3403 => x"00003524", +3404 => x"00003524", +3405 => x"0000352c", +3406 => x"0000352c", +3407 => x"00003534", +3408 => x"00003534", +3409 => x"0000353c", +3410 => x"0000353c", +3411 => x"00003544", +3412 => x"00003544", +3413 => x"0000354c", +3414 => x"0000354c", +3415 => x"00003554", +3416 => x"00003554", +3417 => x"0000355c", +3418 => x"0000355c", +3419 => x"00003564", +3420 => x"00003564", +3421 => x"0000356c", +3422 => x"0000356c", +3423 => x"00003580", +3424 => x"00000000", +3425 => x"000037e8", +3426 => x"00003844", +3427 => x"000038a0", +3428 => x"00000000", +3429 => x"00000000", +3430 => x"00000000", +3431 => x"00000000", +3432 => x"00000000", +3433 => x"00000000", +3434 => x"00000000", +3435 => x"00000000", +3436 => x"00000000", +3437 => x"00003100", +3438 => x"00000000", +3439 => x"00000000", +3440 => x"00000000", +3441 => x"00000000", +3442 => x"00000000", +3443 => x"00000000", +3444 => x"00000000", +3445 => x"00000000", +3446 => x"00000000", +3447 => x"00000000", +3448 => x"00000000", +3449 => x"00000000", +3450 => x"00000000", +3451 => x"00000000", +3452 => x"00000000", +3453 => x"00000000", +3454 => x"00000000", +3455 => x"00000000", +3456 => x"00000000", +3457 => x"00000000", +3458 => x"00000000", +3459 => x"00000000", +3460 => x"00000000", +3461 => x"00000000", +3462 => x"00000000", +3463 => x"00000000", +3464 => x"00000000", +3465 => x"00000000", +3466 => x"00000001", +3467 => x"330eabcd", +3468 => x"1234e66d", +3469 => x"deec0005", +3470 => x"000b0000", +3471 => x"00000000", +3472 => x"00000000", +3473 => x"00000000", +3474 => x"00000000", +3475 => x"00000000", +3476 => x"00000000", +3477 => x"00000000", +3478 => x"00000000", +3479 => x"00000000", +3480 => x"00000000", +3481 => x"00000000", +3482 => x"00000000", +3483 => x"00000000", +3484 => x"00000000", +3485 => x"00000000", +3486 => x"00000000", +3487 => x"00000000", +3488 => x"00000000", +3489 => x"00000000", +3490 => x"00000000", +3491 => x"00000000", +3492 => x"00000000", +3493 => x"00000000", +3494 => x"00000000", +3495 => x"00000000", +3496 => x"00000000", +3497 => x"00000000", +3498 => x"00000000", +3499 => x"00000000", +3500 => x"00000000", +3501 => x"00000000", +3502 => x"00000000", +3503 => x"00000000", +3504 => x"00000000", +3505 => x"00000000", +3506 => x"00000000", +3507 => x"00000000", +3508 => x"00000000", +3509 => x"00000000", +3510 => x"00000000", +3511 => x"00000000", +3512 => x"00000000", +3513 => x"00000000", +3514 => x"00000000", +3515 => x"00000000", +3516 => x"00000000", +3517 => x"00000000", +3518 => x"00000000", +3519 => x"00000000", +3520 => x"00000000", +3521 => x"00000000", +3522 => x"00000000", +3523 => x"00000000", +3524 => x"00000000", +3525 => x"00000000", +3526 => x"00000000", +3527 => x"00000000", +3528 => x"00000000", +3529 => x"00000000", +3530 => x"00000000", +3531 => x"00000000", +3532 => x"00000000", +3533 => x"00000000", +3534 => x"00000000", +3535 => x"00000000", +3536 => x"00000000", +3537 => x"00000000", +3538 => x"00000000", +3539 => x"00000000", +3540 => x"00000000", +3541 => x"00000000", +3542 => x"00000000", +3543 => x"00000000", +3544 => x"00000000", +3545 => x"00000000", +3546 => x"00000000", +3547 => x"00000000", +3548 => x"00000000", +3549 => x"00000000", +3550 => x"00000000", +3551 => x"00000000", +3552 => x"00000000", +3553 => x"00000000", +3554 => x"00000000", +3555 => x"00000000", +3556 => x"00000000", +3557 => x"00000000", +3558 => x"00000000", +3559 => x"00000000", +3560 => x"00000000", +3561 => x"00000000", +3562 => x"00000000", +3563 => x"00000000", +3564 => x"00000000", +3565 => x"00000000", +3566 => x"00000000", +3567 => x"00000000", +3568 => x"00000000", +3569 => x"00000000", +3570 => x"00000000", +3571 => x"00000000", +3572 => x"00000000", +3573 => x"00000000", +3574 => x"00000000", +3575 => x"00000000", +3576 => x"00000000", +3577 => x"00000000", +3578 => x"00000000", +3579 => x"00000000", +3580 => x"00000000", +3581 => x"00000000", +3582 => x"00000000", +3583 => x"00000000", +3584 => x"00000000", +3585 => x"00000000", +3586 => x"00000000", +3587 => x"00000000", +3588 => x"00000000", +3589 => x"00000000", +3590 => x"00000000", +3591 => x"00000000", +3592 => x"00000000", +3593 => x"00000000", +3594 => x"00000000", +3595 => x"00000000", +3596 => x"00000000", +3597 => x"00000000", +3598 => x"00000000", +3599 => x"00000000", +3600 => x"00000000", +3601 => x"00000000", +3602 => x"00000000", +3603 => x"00000000", +3604 => x"00000000", +3605 => x"00000000", +3606 => x"00000000", +3607 => x"00000000", +3608 => x"00000000", +3609 => x"00000000", +3610 => x"00000000", +3611 => x"00000000", +3612 => x"00000000", +3613 => x"00000000", +3614 => x"00000000", +3615 => x"00000000", +3616 => x"00000000", +3617 => x"00000000", +3618 => x"00000000", +3619 => x"00000000", +3620 => x"00000000", +3621 => x"00000000", +3622 => x"00000000", +3623 => x"00000000", +3624 => x"00000000", +3625 => x"00000000", +3626 => x"00000000", +3627 => x"00000000", +3628 => x"00000000", +3629 => x"00000000", +3630 => x"00000000", +3631 => x"00000000", +3632 => x"00000000", +3633 => x"00000000", +3634 => x"00000000", +3635 => x"00000000", +3636 => x"00000000", +3637 => x"00000000", +3638 => x"00000000", +3639 => x"00000000", +3640 => x"00000000", +3641 => x"00000000", +3642 => x"00000000", +3643 => x"00000000", +3644 => x"00000000", +3645 => x"00000000", +3646 => x"00000000", +3647 => x"00003104", +3648 => x"ffffffff", +3649 => x"00000000", +3650 => x"ffffffff", +3651 => x"00000000", + others => x"00000000" +); + +begin + +mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request + +process (clk, areset) +begin + if areset = '1' then + elsif (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + end if; + mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/zpu4/src/dram_hello.vhd b/zpu/hdl/zpu4/src/dram_hello.vhd new file mode 100644 index 0000000..dc46dbb --- /dev/null +++ b/zpu/hdl/zpu4/src/dram_hello.vhd @@ -0,0 +1,3214 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity dram is +port (clk : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); +end dram; + +architecture dram_arch of dram is + + +type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); + +shared variable ram : ram_type := +( +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80d3900c", +3 => x"3a0b0b80", +4 => x"c8b20400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c8fb2d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", 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x"00000000", +2855 => x"00000000", +2856 => x"00000000", +2857 => x"00000000", +2858 => x"00000000", +2859 => x"00000000", +2860 => x"00000000", +2861 => x"00000000", +2862 => x"00000000", +2863 => x"00000000", +2864 => x"00000000", +2865 => x"00000000", +2866 => x"00000000", +2867 => x"00000000", +2868 => x"00000000", +2869 => x"00000000", +2870 => x"00000000", +2871 => x"00000000", +2872 => x"00000000", +2873 => x"00000000", +2874 => x"00000000", +2875 => x"00000000", +2876 => x"00000000", +2877 => x"00000000", +2878 => x"00000000", +2879 => x"00000000", +2880 => x"00000000", +2881 => x"00000000", +2882 => x"00000000", +2883 => x"00000000", +2884 => x"00000000", +2885 => x"00000000", +2886 => x"00000000", +2887 => x"00000000", +2888 => x"00000000", +2889 => x"00000000", +2890 => x"00000000", +2891 => x"00000000", +2892 => x"00000000", +2893 => x"00000000", +2894 => x"00000000", +2895 => x"00000000", +2896 => x"00000000", +2897 => x"00000000", +2898 => x"00000000", +2899 => x"ffffffff", +2900 => x"00000000", +2901 => x"00020000", +2902 => x"00000000", +2903 => x"00000000", +2904 => x"00002d58", +2905 => x"00002d58", +2906 => x"00002d60", +2907 => x"00002d60", +2908 => x"00002d68", +2909 => x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"00002fa8", +3053 => x"00002fa8", +3054 => x"00002fb0", +3055 => x"00002fb0", +3056 => x"00002fb8", +3057 => x"00002fb8", +3058 => x"00002fc0", +3059 => x"00002fc0", +3060 => x"00002fc8", +3061 => x"00002fc8", +3062 => x"00002fd0", +3063 => x"00002fd0", +3064 => x"00002fd8", +3065 => x"00002fd8", +3066 => x"00002fe0", +3067 => x"00002fe0", +3068 => x"00002fe8", +3069 => x"00002fe8", +3070 => x"00002ff0", +3071 => x"00002ff0", +3072 => x"00002ff8", +3073 => x"00002ff8", +3074 => x"00003000", +3075 => x"00003000", +3076 => x"00003008", +3077 => x"00003008", +3078 => x"00003010", +3079 => x"00003010", +3080 => x"00003018", +3081 => x"00003018", +3082 => x"00003020", +3083 => x"00003020", +3084 => x"00003028", +3085 => x"00003028", +3086 => x"00003030", +3087 => x"00003030", +3088 => x"00003038", +3089 => x"00003038", +3090 => x"00003040", +3091 => x"00003040", +3092 => x"00003048", +3093 => x"00003048", +3094 => x"00003050", +3095 => x"00003050", +3096 => x"00003058", +3097 => x"00003058", +3098 => x"00003060", +3099 => x"00003060", +3100 => x"00003068", +3101 => x"00003068", +3102 => x"00003070", +3103 => x"00003070", +3104 => x"00003078", +3105 => x"00003078", +3106 => x"00003080", +3107 => x"00003080", +3108 => x"00003088", +3109 => x"00003088", +3110 => x"00003090", +3111 => x"00003090", +3112 => x"00003098", +3113 => x"00003098", +3114 => x"000030a0", +3115 => x"000030a0", +3116 => x"000030a8", +3117 => x"000030a8", +3118 => x"000030b0", +3119 => x"000030b0", +3120 => x"000030b8", +3121 => x"000030b8", +3122 => x"000030c0", +3123 => x"000030c0", +3124 => x"000030c8", +3125 => x"000030c8", +3126 => x"000030d0", +3127 => x"000030d0", +3128 => x"000030d8", +3129 => x"000030d8", +3130 => x"000030e0", +3131 => x"000030e0", +3132 => x"000030e8", +3133 => x"000030e8", +3134 => x"000030f0", +3135 => x"000030f0", +3136 => x"000030f8", +3137 => x"000030f8", +3138 => x"00003100", +3139 => x"00003100", +3140 => x"00003108", +3141 => x"00003108", +3142 => x"00003110", +3143 => x"00003110", +3144 => x"00003118", +3145 => x"00003118", +3146 => x"00003120", +3147 => x"00003120", +3148 => x"00003128", +3149 => x"00003128", +3150 => x"00003130", +3151 => x"00003130", +3152 => x"00003138", +3153 => x"00003138", +3154 => x"00003140", +3155 => x"00003140", +3156 => x"00003148", +3157 => x"00003148", +3158 => x"00003150", +3159 => x"00003150", +3160 => x"00002970", +3161 => x"ffffffff", +3162 => x"00000000", +3163 => x"ffffffff", +3164 => x"00000000", + others => x"00000000" +); + +begin + +process (clk) +begin + if (clk'event and clk = '1') then + mem_busy<=mem_writeEnable or mem_readEnable; + if (mem_writeEnable = '1') then + ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + end if; + if (mem_readEnable = '1') then + mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + end if; + end if; +end process; + + + + +end dram_arch; diff --git a/zpu/hdl/zpu4/src/fastdmips.do b/zpu/hdl/zpu4/src/fastdmips.do new file mode 100644 index 0000000..504bf60 --- /dev/null +++ b/zpu/hdl/zpu4/src/fastdmips.do @@ -0,0 +1,19 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_fastsim.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastdmipsintstack.do b/zpu/hdl/zpu4/src/fastdmipsintstack.do new file mode 100644 index 0000000..ee9571e --- /dev/null +++ b/zpu/hdl/zpu4/src/fastdmipsintstack.do @@ -0,0 +1,19 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_fastsim.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_intstack.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastdmipssmall.do b/zpu/hdl/zpu4/src/fastdmipssmall.do new file mode 100644 index 0000000..3eaa083 --- /dev/null +++ b/zpu/hdl/zpu4/src/fastdmipssmall.do @@ -0,0 +1,21 @@ +set BreakOnAssertion 1 +vlib work + + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_small.vhd +vcom -93 -explicit bram_dmips.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastsimzpu.do b/zpu/hdl/zpu4/src/fastsimzpu.do new file mode 100644 index 0000000..504bf60 --- /dev/null +++ b/zpu/hdl/zpu4/src/fastsimzpu.do @@ -0,0 +1,19 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_fastsim.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/ic300.bitgen b/zpu/hdl/zpu4/src/ic300.bitgen new file mode 100644 index 0000000..1095099 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300.bitgen @@ -0,0 +1,27 @@ +-g DebugBitstream:No +-g Binary:yes +-g CRC:Enable +-g ConfigRate:50 +-g CclkPin:Pullnone +-g M0Pin:Pullnone +-g M1Pin:Pullnone +-g M2Pin:Pullnone +-g ProgPin:PullUp +-g DonePin:Pullnone +-g TckPin:Pullnone +-g TdiPin:Pullnone +-g TdoPin:Pullnone +-g TmsPin:Pullnone +-g UnusedPin:Pullnone +-g UserID:0xFFFFFFFF +-g DCMShutDown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:Level1 +-g DonePipe:No +-g DriveDone:Yes + diff --git a/zpu/hdl/zpu4/src/ic300.lso b/zpu/hdl/zpu4/src/ic300.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300.lso @@ -0,0 +1 @@ +work diff --git a/zpu/hdl/zpu4/src/ic300.ucf b/zpu/hdl/zpu4/src/ic300.ucf new file mode 100644 index 0000000..4a141b9 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300.ucf @@ -0,0 +1,146 @@ +# clock inputs +net "cpu_clk_p" loc = "R9" | iostandard=LVTTL; + +# input pins +net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL; +net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL; +net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL; +net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL; +net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL; +net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL; +net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL; +net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL; +net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL; +net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL; +net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL; +net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL; +net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL; +net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL; +net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL; +net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL; +net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL; +net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL; +net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL; +net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL; +net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL; +net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL; +net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL; +net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL; +net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL; +net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL; +net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL; + +#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I; + +# output pins +net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL; +net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL; +net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL; +net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL; + +#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST; +#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST; +#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST; +#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP; +#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; +#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; +#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; +#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST; +#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST; +#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST; +#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST; +#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST; +#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST; +#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST; + +# bidirectional pins +net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL; +net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL; +net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL; +net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL; +net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL; +net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL; +net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL; +net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL; +net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL; +net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL; +net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL; +net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL; +net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL; +net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL; +net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL; +net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL; + +#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST; +#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST; + +# TIMING +# Create timing names +NET "cpu_clk_p" TNM_NET = "cpu_clk_p"; +NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p"; +#NET "cpu_clk" TNM_NET = "cpu_clk"; +#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x"; +#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x"; +#NET "ddr_in_clk" TNM_NET = "ddr_in_clk"; +#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x"; + +## Create timing + +# Periode timing +TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 10 ns HIGH 50 %; +#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %; + +# Clock domain crossing timing +#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns; +#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns; +#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns; +#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns; +#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns; +#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns; +#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns; +#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns; +#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns; +#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns; + +#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns; +#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns; +#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns; +#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns; + + + diff --git a/zpu/hdl/zpu4/src/ic300.vhd b/zpu/hdl/zpu4/src/ic300.vhd new file mode 100644 index 0000000..a1b4f41 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300.vhd @@ -0,0 +1,144 @@ +-------------------------------------------------------------------------------- +-- Company: Zylin AS +-- Engineer: Tore Ramsland +-- +-- Create Date: 21:47:41 07/03/05 +-- Design Name: ic300 +-- Module Name: ic300 - behave +-- Project Name: eCosBoard +-- Target Device: XC3S400400-FG256 +-- Tool versions: 7.1i +-- Description: Top level +-- +-- Dependencies: +-- +-- Revision: +-- 2005-07-11 Updated to test FPGA +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +library zylin; +use zylin.arm7.all; + +library zylin; +use zylin.zpu_config.all; +use zylin.zpupkg.all; + +library work; +use work.phi_config.all; +use work.ic300pkg.all; + +entity ic300 is + generic( + simulate_io_time : boolean := false); + port ( -- Clock inputs + cpu_clk_p : in std_logic; + + -- CPU interface signals + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus + sdr_clk_fb_p : in std_logic -- DDR clock feedback + ); +end ic300; + +architecture behave of ic300 is + +signal cpu_we : std_logic_vector(1 downto 0); -- Write signal for lower(0) and upper(1) 8 data bits +signal cpu_re : std_logic; -- Read enable signal for all 16 bits +signal areset : std_logic; -- Asyncronous active high reset (for initialization) +signal areset_dummy : std_logic; + +-- Clock module signals +signal clk_status : std_logic_vector(2 downto 0); -- DLL lock status (from 3 DLL's) +signal cpu_clk : std_logic; -- 64 MHz CPU clk +signal cpu_clk_2x : std_logic; -- 128 MHz CPU clk (in phase with 64 MHz) +signal cpu_clk_4x : std_logic; -- 256 MHz CPU clk (in phase with 64 MHz) +signal ddr_in_clk : std_logic; -- 128 MHz clock from DDR SDRAM +signal ddr_in_clk_2x : std_logic; -- 256 MHz clock from DDR SDRAM + -- NOTE! Phase relation to 64 MHz clock unknown + +-- Internal CPU interface signals +signal cpu_din : std_logic_vector(15 downto 0); -- 16-bit data from CPU +signal cpu_dout : std_logic_vector(15 downto 0); -- 16-bit data to CPU +signal cpu_a : std_logic_vector(20 downto 0); -- 21-bit address from CPU + +begin + +-- areset <= '0'; + areset_dummy <= '0'; + + global_init_reset: + rocbuf port map(I=>areset_dummy,O=>areset); + + allclocks: + clocks port map( + areset => areset, + cpu_clk_p => cpu_clk_p, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_clk_4x => cpu_clk_4x, + sdr_clk_fb_p => sdr_clk_fb_p, + ddr_in_clk => ddr_in_clk, + ddr_in_clk_2x => ddr_in_clk_2x, + locked => clk_status); + + arm7cpu: + arm7wb generic map (simulate_io_time => simulate_io_time) + port map( + areset => areset, + cpu_clk => cpu_clk, + cpu_clk_2x => cpu_clk_2x, + cpu_a_p => cpu_a_p, + cpu_wr_n_p => cpu_wr_n_p, + cpu_cs_n_p => cpu_cs_n_p, + cpu_oe_n_p => cpu_oe_n_p, + cpu_d_p => cpu_d_p, + cpu_irq_p => cpu_irq_p, + cpu_fiq_p => cpu_fiq_p, + cpu_wait_n_p => cpu_wait_n_p, + cpu_din => cpu_din, + cpu_a => cpu_a, + cpu_we => cpu_we, + cpu_re => cpu_re, + cpu_dout => cpu_dout); + + + cpu_fpga_regs: + zpuio port map( + areset => areset, + cpu_clk => cpu_clk, + clk_status => clk_status, + cpu_din => cpu_din, + cpu_a => cpu_a, + cpu_we => cpu_we, + cpu_re => cpu_re, + cpu_dout => cpu_dout); + + +end behave; diff --git a/zpu/hdl/zpu4/src/ic300_config.vhd b/zpu/hdl/zpu4/src/ic300_config.vhd new file mode 100644 index 0000000..b14ec79 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300_config.vhd @@ -0,0 +1,26 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package phi_config is + + constant Fpga_Global_Base : std_logic_vector(19 downto 17) := "000"; -- 0x0800.... + constant Clock_Stat_Reg_Addr : std_logic_vector(5 downto 2) := "0000"; -- 0x....0000 + constant Ctrl_Reg_Addr : std_logic_vector(5 downto 2) := "0001"; -- 0x....0004 + constant output_enable : std_logic_vector(5 downto 2) := "0010"; -- 0x....0008 + constant output_disable : std_logic_vector(5 downto 2) := "0011"; -- 0x....000C + constant data_status : std_logic_vector(5 downto 2) := "0100"; -- 0x....0010 + constant set_output_data : std_logic_vector(5 downto 2) := "0101"; -- 0x....0014 + constant clear_output_data : std_logic_vector(5 downto 2) := "0110"; -- 0x....0018 + constant data_in_read : std_logic_vector(5 downto 2) := "0111"; -- 0x....001C + constant output_status : std_logic_vector(5 downto 2) := "1000"; -- 0x....0020 + constant cpu_access_address : std_logic_vector(5 downto 2) := "1001"; -- 0x....0024 + + constant Fpga_Ethernet_Reg_Base : std_logic_vector(19 downto 17) := "110"; -- 0x080C0000 + + constant Fpga_DDR_Ctrl_Base : std_logic_vector(19 downto 17) := "111"; -- 0x080E.... + constant DDR_Ctrl_Reg_Addr : std_logic_vector(3 downto 2) := "00"; -- 0x....0000 + constant DDR_Mode_Reg_Addr : std_logic_vector(3 downto 2) := "01"; -- 0x....0004 + constant DDR_Page_Select_Addr : std_logic_vector(3 downto 2) := "10"; -- 0x....0008 + + +end phi_config; diff --git a/zpu/hdl/zpu4/src/ic300pkg.vhd b/zpu/hdl/zpu4/src/ic300pkg.vhd new file mode 100644 index 0000000..13da306 --- /dev/null +++ b/zpu/hdl/zpu4/src/ic300pkg.vhd @@ -0,0 +1,88 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package ic300pkg is + + component ic300 is + port ( -- Clock inputs + cpu_clk_p : in std_logic; + + -- CPU interface signals + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : inout std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + -- DDR SDRAM Signals + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus + sdr_clk_fb_p : in std_logic -- DDR clock feedback + ); + end component; + + component clocks is + port ( areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0)); + end component; + + component cpu_regs is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + component ddr_bridge is + port ( areset : in std_logic; + cpu_clk : in std_logic; + cpu_clk_2x : in std_logic; + cpu_clk_4x : in std_logic; + ddr_in_clk : in std_logic; + ddr_in_clk_2x : in std_logic; + + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_dout : inout std_logic_vector(15 downto 0); + + sdr_clk_p : out std_logic; -- ddr_sdram_clock + sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock + cke_q_p : out std_logic; -- clock enable + cs_qn_p : out std_logic; -- /chip select + ras_qn_p : inout std_logic; -- /ras + cas_qn_p : inout std_logic; -- /cas + we_qn_p : inout std_logic; -- /write enable + dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" + dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write + ba_q_p : out std_logic_vector(1 downto 0); -- bank select + sdr_a_p : out std_logic_vector(12 downto 0); -- address bus + sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus + end component; + +end ic300pkg; diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd new file mode 100644 index 0000000..b5465d1 --- /dev/null +++ b/zpu/hdl/zpu4/src/io.vhd @@ -0,0 +1,92 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + +entity zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(7 downto 0); + read : out std_logic_vector(7 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end zpu_io; + + +architecture behave of zpu_io is + + + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + +signal serving : std_logic; + +file l_file : TEXT open write_mode is log_file; + +begin + + + timerinst: timer port map ( + clk => clk, + areset => areset, + we => timer_we, + din => write, + adr => addr(4 downto 2), + dout => timer_read); + + busy <= writeEnable or readEnable; + timer_we <= writeEnable and addr(12); + + process(areset, clk) + begin + if (areset = '1') then +-- timer_we <= '0'; + elsif (clk'event and clk = '1') then +-- timer_we <= '0'; + if writeEnable = '1' then + -- external interface + if addr=x"1000" then + -- Write to UART + -- report "" & character'image(conv_integer(memBint)) severity note; + print(l_file, character'val(conv_integer(write))); + elsif addr(12)='1' then +-- report "xxx" severity failure; +-- timer_we <= '1'; + else + report "Illegal IO write" severity failure; + end if; + + end if; + read <= (others => 'U'); + if (readEnable = '1') then + if addr=x"1001" then + read <= (0=>'1', others => '0'); -- recieve empty + elsif addr(12)='1' then + read <= timer_read; + elsif addr(11)='1' then + read <= ZPU_Frequency; + else + report "Illegal IO read" severity failure; + end if; + end if; + end if; + end process; + + +end behave; + diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt new file mode 100644 index 0000000..af58c93 --- /dev/null +++ b/zpu/hdl/zpu4/src/log.txt @@ -0,0 +1,380 @@ +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +1 + + + + + + +H +e +l +l +o + +w +o +r +l +d + +2 + + + + + + diff --git a/zpu/hdl/zpu4/src/niltrace.vhd b/zpu/hdl/zpu4/src/niltrace.vhd new file mode 100644 index 0000000..40fc1ca --- /dev/null +++ b/zpu/hdl/zpu4/src/niltrace.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; +use work.zpu_config.all; + + +entity trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBit downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBit downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic); +end trace; + + +architecture behave of trace is + +begin + +end behave; + diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd new file mode 100644 index 0000000..2905505 --- /dev/null +++ b/zpu/hdl/zpu4/src/sim_fpga_top.vhd @@ -0,0 +1,190 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(7 downto 0); + read : out std_logic_vector(7 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(7 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + dram_imp: dram port map ( + clk => clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write(7 downto 0), + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read(7 downto 0) <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/zpu4/src/simzpu.do b/zpu/hdl/zpu4/src/simzpu.do new file mode 100644 index 0000000..e6e3068 --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu.do @@ -0,0 +1,23 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 1000 ms diff --git a/zpu/hdl/zpu4/src/simzpu_intstack.do b/zpu/hdl/zpu4/src/simzpu_intstack.do new file mode 100644 index 0000000..cec4873 --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu_intstack.do @@ -0,0 +1,23 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_intstack.vhd +vcom -93 -explicit dram_hello.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 15 ms diff --git a/zpu/hdl/zpu4/src/status.txt b/zpu/hdl/zpu4/src/status.txt new file mode 100644 index 0000000..df01caf --- /dev/null +++ b/zpu/hdl/zpu4/src/status.txt @@ -0,0 +1,109 @@ +- Before NEQBRANCH opt 4.684 DMIPS 8.0 cycles average, after +- opcode pairs + +0x6060 0.1519223038446077 75961 9.048362120309708 LOADSP + LOADSP +0x4040 0.13967027934055867 69835 11.08668042546436 STORESP + STORESP +0x8038 0.10230620461240922 51153 10.251102204408818 IM + NEQBRANCH +0x4060 0.09856219712439425 49281 9.822802471596571 STORESP + LOADSP +0x6080 0.09734219468438937 48671 6.483415478886373 LOADSP + IM +0x3860 0.08642217284434568 43211 12.616350364963504 NEQBRANCH + LOADSP +0x8080 0.060966121932243864 30483 4.275915275634731 IM + IM +0x8005 0.05317010634021268 26585 6.572311495673671 IM + ADD +0x540 0.05215210430420861 26076 9.339541547277937 ADD + STORESP +0x3d0d 0.050808101616203236 25404 12.398243045387995 +0xd04 0.0466000932001864 23300 20.0 +0x6040 0.04389608779217558 21948 9.460344827586207 +0x4080 0.043648087296174594 21824 7.630769230769231 +0xc80 0.03966807933615867 19834 11.438292964244521 +0x8010 0.0391500783001566 19575 6.1248435544430535 +0x480 0.038798077596155195 19399 10.941342357586013 + + +- zpu_core.vhd: 1500 LUTs. Xilinx ISE reports 83MHz maximum frequency after P&R + which matches what I've found w/my ic300.vhd testbench + +- zpu_core_instack.vhd + - problems w/simulation trace since storeb/loadb will run into undefined memory + during emulation. Solution: implement loadb+storeb. + - simulation needs to read cycles from ModelSim trace so as to m ake readcycles + not cause false positives. This has other interesting potentials w.r.t. + knowing which instructions take the longest. + +- Ca. 1700 LUT inc. all instructions. Removing all higher level instructions + => 1300. + +- Review memory interface + - When is mem_busy high? Will it be high on the next cycle after + I've send mem_read/writeEnable? + - Should I hold off posting a read/write until mem_busy = '0'? + - Write posting could increase performance somewhat. Should there be + a seperate write busy signal? + - Synchronous reset? The ARM7 will have to copy the program to DRAM and + then start the ZPU. + +- Current instruction set has + - 31 DMIPS single cycle performance Simulator.java + - 8 DMIPS w/single cycle RAM access in ModelSim + +112 0.06100380865858346 67215918 +56 0.04139603650830458 45611457 +129 0.0375812381475752 41408192 +5 0.03703417264799563 40805418 +113 0.03540341331682748 39008596 +128 0.0343154384313754 37809831 +83 0.03322159422742951 36604599 +114 0.03213492807203279 35407276 +132 0.03158580962697109 34802240 +12 0.03049709687915076 33602662 +8 0.029409690138646426 32404523 +115 0.026690690908727877 29408644 +46 0.025054316381406774 27605635 +82 0.023965804208719754 26406278 +84 0.023961360698074072 26401382 +116 0.023417718589457643 25802380 +81 0.02179306727026773 24012288 +117 0.021783900714401432 24002188 +4 0.01797685126990833 19807461 +6 0.016340292503890113 18004249 +85 0.016339001017850734 18002826 +255 0.016338918428089957 18002735 +86 0.016337281154151066 18000931 +11 0.011984767180825744 13205194 +51 0.0114390303780569 12603884 +38 0.010892246228211845 12001420 +118 0.010347263624247446 11400941 +131 0.009257503529350904 10200209 +7 0.008713386756504965 9600684 +22 0.008712946580307425 9600199 + + +64 0.16176824859336478 178241352 +96 0.23147927881894828 255051161 +128 0.2646966482624612 291651105 + + +- Alternate memory interface to allow more caching in memory subsystem? + +-- The memory interface allows a dual port memory to be used +-- to increase performance. +-- +-- Also it is possible to implement a zero cycle register file instead +-- of memory, though obviously that will cause problems w.r.t. max +-- frequency for the ZPU. +-- +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- mem_read is a single cycle while mem_read_busy='0'. +-- +-- mem_read/write_busy - It is illegal to send off a read/write request when mem_read/write_busy='1'. +-- Set to '0' when mem_read is valid after a read request. Note that +-- the definition allows zero wait state ram. +-- mem_read/write_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. diff --git a/zpu/hdl/zpu4/src/testlut.vhd b/zpu/hdl/zpu4/src/testlut.vhd new file mode 100644 index 0000000..668efcc --- /dev/null +++ b/zpu/hdl/zpu4/src/testlut.vhd @@ -0,0 +1,114 @@ +-- Company: Zylin AS +-- +-- Hooks up the ZPU to physical pads to ensure that it is not optimized to +-- oblivion. This is purely to have something to measure LUT usage against. +-- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity ic300 is + port ( -- Clock inputs + cpu_clk_p : in std_logic; + + -- CPU interface signals + cpu_a_p : in std_logic_vector(20 downto 0); + cpu_wr_n_p : in std_logic_vector(1 downto 0); + cpu_cs_n_p : in std_logic_vector(3 downto 1); + cpu_oe_n_p : in std_logic; + cpu_d_p : out std_logic_vector(15 downto 0); + cpu_irq_p : out std_logic_vector(1 downto 0); + cpu_fiq_p : out std_logic; + cpu_wait_n_p : out std_logic; + + sdr_clk_fb_p : in std_logic -- DDR clock feedback + ); +end ic300; + +architecture behave of ic300 is + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal io_readEnable : std_logic; + + +signal cpu_we : std_logic_vector(1 downto 0); +signal cpu_re : std_logic; +signal areset : std_logic; + +-- Clock module signals +signal clk_status : std_logic_vector(2 downto 0); +signal cpu_clk : std_logic; +signal cpu_clk_2x : std_logic; +signal cpu_clk_4x : std_logic; +signal ddr_in_clk : std_logic; + + +-- Internal CPU interface signals +signal cpu_din : std_logic_vector(15 downto 0); +signal cpu_dout : std_logic_vector(15 downto 0); +signal cpu_a : std_logic_vector(20 downto 0); + +signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5); + +signal dummy2 : std_logic_vector(wordSize-1 downto 0); +signal dummy3 : std_logic_vector(wordSize-1 downto 0); +signal dummy4 : std_logic_vector(wordSize-1 downto 0); +begin + + areset <= '0'; -- MUST BE CHANGED TO SOMETHING CORRECT + +-- cpu_d_p <= (others => '0'); + cpu_irq_p <= (others => '0'); + cpu_fiq_p <= '0'; + cpu_wait_n_p <= '0'; + + cpu_d_p(15 downto 15) <= (others => '0'); + + -- delay signals going out/in w/1 clk so the + -- ZPU does not have to drive those pins. + -- + -- these registers can be placed close to the ZPU and these + -- registers then have a full clock to drive the pins. + process(cpu_clk_p, areset) + begin + if (cpu_clk_p'event and cpu_clk_p = '1') then + cpu_d_p(0) <= io_writeEnable; + cpu_d_p(1) <= io_readEnable; + cpu_d_p(9 downto 2) <= io_write; + io_read <= cpu_a_p(7 downto 0); + -- 32 read/write registers is plenty realisitic for a minimal size + -- soft-CPU + cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit); + end if; + end process; + + + zpu: zpu_core port map ( + clk => cpu_clk_p , + areset => areset, + enable => '1', + + in_mem_busy => '0', + out_mem_writeEnable => io_writeEnable, + out_mem_readEnable => io_readEnable, + mem_write(7 downto 0) => io_write, + mem_write(wordSize-1 downto 8) => dummy3(wordSize-1 downto 8), + mem_read(7 downto 0) => io_read, + mem_read(wordSize-1 downto 8) => dummy2(wordSize-1 downto 8), + out_mem_addr(maxAddrBitIncIO) => dummy4(maxAddrBitIncIO), + out_mem_addr(minAddrBit-1 downto 0) => dummy4(minAddrBit-1 downto 0) , + out_mem_addr(maxAddrBit downto minAddrBit) => io_addr, + interrupt => '0' + ); + + +end behave; diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd new file mode 100644 index 0000000..60c8fe2 --- /dev/null +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -0,0 +1,61 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); +end timer; + + +architecture behave of timer is + +signal sample : std_logic; +signal reset : std_logic; + + +signal cnt : std_logic_vector(63 downto 0); +signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + elsif (clk'event and clk = '1') then + cnt <= cnt + 1; + if sample = '1' then +-- report "sampling" severity failure; + cnt_smp <= cnt; + end if; + end if; + end process; + + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end behave; + diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd new file mode 100644 index 0000000..bc5279f --- /dev/null +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -0,0 +1,84 @@ +library ieee; +use ieee.std_logic_1164.all; +--use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + + +entity trace is + generic ( + log_file: string := "trace.txt" + ); + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); +end trace; + + +architecture behave of trace is + + +file l_file : TEXT open write_mode is log_file; + + +begin + + +-- write data and control information to a file + +receive_data: process + +variable l: line; +variable t : std_logic_vector(wordSize-1 downto 0); +variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); +variable counter : std_logic_vector(63 downto 0); + + + +begin + + t:= (others => '0'); + t2:= (others => '0'); + +counter := (others => '0'); + -- print header for the logfile + print(l_file, "#pc,opcode,sp,top_of_stack "); + print(l_file, "#----------"); + print(l_file, " "); + + wait until clk = '1'; + wait until clk = '0'; + + while true loop + + counter := counter + 1; + if begin_inst = '1' then + t(maxAddrBitIncIO downto 2):=sp; + t2:=pc; + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter)); + end if; + + wait until clk = '0'; + + end loop; + + end process receive_data; + + + +end behave; + diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd new file mode 100644 index 0000000..d3bf01a --- /dev/null +++ b/zpu/hdl/zpu4/src/txt_util.vhd @@ -0,0 +1,587 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + +library work; + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + diff --git a/zpu/hdl/zpu4/src/xmake.filelist b/zpu/hdl/zpu4/src/xmake.filelist new file mode 100644 index 0000000..91e623f --- /dev/null +++ b/zpu/hdl/zpu4/src/xmake.filelist @@ -0,0 +1,12 @@ +vhdl work "ic300_config.vhd" +vhdl work "ic300pkg.vhd" +vhdl zylin "zpu_config.vhd" +vhdl zylin "zpupkg.vhd" +vhdl zylin "zpu_core.vhd" +vhdl work "bram.vhd" +vhdl zylin "zpuio.vhd" +vhdl zylin "..\dummyfpgalib\arm7\src\arm7pkg.vhd" +vhdl zylin "..\dummyfpgalib\arm7\src\arm7wb.vhd" +vhdl work "clocks.vhd" +vhdl work "timer.vhd" +vhdl work "ic300.vhd" \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall new file mode 100644 index 0000000..141633e --- /dev/null +++ b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall @@ -0,0 +1,5 @@ +vhdl work "zpu_config.vhd" +vhdl work "zpupkg.vhd" +vhdl work "zpu_core_small.vhd" +vhdl work "bram_dmips.vhd" +vhdl work "testlut.vhd" diff --git a/zpu/hdl/zpu4/src/xmake.xst b/zpu/hdl/zpu4/src/xmake.xst new file mode 100644 index 0000000..bfdb23f --- /dev/null +++ b/zpu/hdl/zpu4/src/xmake.xst @@ -0,0 +1,53 @@ +set -tmpdir ../tmp +set -xsthdpdir ../xst +run +-ifn xmake.filelist +-ifmt mixed +-ofn ../syn/ic300 +-ofmt NGC +-p xc3s400-4-ft256 +-top ic300 +-opt_mode Area +-opt_level 2 +-iuc NO +-lso ic300.lso +-keep_hierarchy NO +-glob_opt AllClockNets +-rtlview Yes +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-rom_style Auto +-mux_extract YES +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-resource_sharing YES +-mult_style auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-equivalent_register_removal NO +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set No +-use_sync_reset No +-iob true +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zpu4/src/zpu_config.vhd b/zpu/hdl/zpu4/src/zpu_config.vhd new file mode 100644 index 0000000..a13c0bf --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_config.vhd @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := 'X'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 15; + +end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd new file mode 100644 index 0000000..d39c9e9 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"50"; -- 80MHz + constant maxAddrBitIncIO : integer := 15; + +end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd new file mode 100644 index 0000000..d1bbbbb --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_config_trace.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + + constant Generate_Trace : boolean := true; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + constant maxAddrBitIncIO : integer := 15; + +end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/src/zpu_core.vhd new file mode 100644 index 0000000..c7093e2 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core.vhd @@ -0,0 +1,900 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_InsnFetch +); + +type StateType is +( +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult4, +State_BinaryOpResult2, +State_BinaryOpResult, +State_Idle +); + + +signal pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal stackA : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult3 : std_logic_vector(wordSize-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); +signal multA : std_logic_vector(wordSize-1 downto 0); +signal multB : std_logic_vector(wordSize-1 downto 0); +signal stackB : std_logic_vector(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; + +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +begin + + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable tSpOffset : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + -- point to top of RAM-8 + sp <= (others => '0'); + sp(maxAddrBit downto minAddrBit+1) <= (others => '1'); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + + mem_addr <= (others => DontCareValue); + mem_readEnable <='0'; + mem_writeEnable <='0'; + mem_write <= (others => DontCareValue); + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + + + spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); + trace_pc <= pc; + trace_sp <= sp; + trace_topOfStack <= stackA; + trace_topOfStackB <= stackB; + begin_inst <= '0'; + + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if in_mem_busy='0' then + mem_addr <= sp; + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if in_mem_busy='0' then + stackA <= mem_read; + mem_addr <= incSp; + mem_readEnable <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if in_mem_busy='0' then + stackB <= mem_read; + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if in_mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=tOpcode(3 downto 0); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + else + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + end if; + end if; + when State_StoreSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= sp+spOffset; + mem_write <= stackA; + stackA <= stackB; + sp <= incSp; + end if; + + + when State_LoadSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + end if; + when State_Emulate => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); + state <= State_Fetch; + end if; + when State_Callpcrel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_Call => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_AddSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= sp+spOffset; + end if; + when State_PushSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + end if; + when State_PopPC => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + end if; + when State_PopPCRel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + end if; + when State_Add => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_Sub => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + when State_Pop => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + when State_PopDown => + if in_mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + when State_Or => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_And => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_Eq => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Ulessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Lessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Load => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + end if; + + when State_Dup => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + mem_writeEnable <= '1'; + end if; + when State_DupStackB => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + mem_writeEnable <= '1'; + end if; + when State_Store => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= stackB; + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_PopSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= stackB; + mem_addr <= incSp; + mem_writeEnable <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + end if; + when State_Storeb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if in_mem_busy='0' then + mem_addr <= incSp; + mem_readEnable <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if in_mem_busy='0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= sp+spOffset+1; + end if; + when State_LoadSP3 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= mem_read; + end if; + when State_AddSP2 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + mem_read; + end if; + when State_Load2 => + if in_mem_busy='0' then + stackA <= mem_read; + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if in_mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if in_mem_busy='0' then + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= mem_read; + mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if in_mem_busy='0' then + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + if in_mem_busy='0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + when State_Popped => + if in_mem_busy='0' then + pc <= pc + 1; + stackB <= mem_read; + state <= State_Execute; + end if; + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd new file mode 100644 index 0000000..4d73f88 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -0,0 +1,433 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memAWrite : std_logic_vector(wordSize-1 downto 0); +signal memARead : std_logic_vector(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memBWrite : std_logic_vector(wordSize-1 downto 0); +signal memBRead : std_logic_vector(wordSize-1 downto 0); + + + +signal pc : std_logic_vector(maxAddrBit downto 0); +signal sp : std_logic_vector(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. +type State_Type is +( +State_Fetch, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_FetchNext, +State_AddSP, +State_ReadIODone, +State_Decode, +State_Resync +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP , +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP +); + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; +signal sampledDecodedOpcode : DecodedOpcodeType; + + +signal state : State_Type; + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit), + memAWrite => memAWrite, + memARead => memARead, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit), + memBWrite => memBWrite, + memBRead => memBRead + ); + + + + decodeControl: + process(memBRead, pc) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + tOpcode := memBRead((wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0)))*8); + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : std_logic_vector(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= spStart(maxAddrBit downto minAddrBit); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + mem_write <= memBRead; + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= pc; + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= sp; + trace_topOfStack <= memARead; + trace_topOfStackB <= memBRead; + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0):=opcode(3 downto 0); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= opcode(6 downto 0); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= opcode(6 downto 0); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(4 downto 0); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= mem_read; + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + mem_write <= memBRead; + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd new file mode 100644 index 0000000..d14629e --- /dev/null +++ b/zpu/hdl/zpu4/src/zpuio.vhd @@ -0,0 +1,256 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); +end zpuio; + +architecture behave of zpuio is + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +--signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal Enable : std_logic; + +signal din : std_logic_vector(7 downto 0); +signal dout : std_logic_vector(7 downto 0); +signal adr : std_logic_vector(15 downto 0); +signal break : std_logic; +signal we : std_logic; +signal re : std_logic; + + +-- uart forwarding... + +signal uartTXPending : std_logic; +signal uartTXCleared : std_logic; +signal uartData : std_logic_vector(7 downto 0); + +signal readingTimer : std_logic; + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + + +--signal io_mem_read : std_logic_vector(7 downto 0); +--signal io_mem_writeEnable : std_logic; +--signal io_mem_readEnable : std_logic; +signal io_readEnable : std_logic; + + +signal dram_read : std_logic; + + + +begin + + io_addr <= mem_addr(maxAddrBit downto minAddrBit); + + timerinst: timer port map ( + clk => cpu_clk, + areset => areset, + we => timer_we, + din => mem_write(7 downto 0), + adr => io_addr(4 downto 2), + dout => timer_read); + + zpu: zpu_core port map ( + clk => cpu_clk , + areset => areset, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + +ram_imp: dram port map ( + clk => cpu_clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask); + + + -- Read/write are on different addresses + -- The registers are 8 bits and mapped to bit[7:0] + -- + -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) + -- Read : Reads from UART RX FIFO (4 byte FIFO) + -- 0xC004 Read : UART status register + -- Bit 0 = RX FIFO empty + -- Bit 1 = TX FIFO full + -- 0xA000 Skrive: LED's (8 stk.) + + -- 0x9000 Write: bit 0: 1= reset counter + -- 0= counter running + -- bit 1: 1= sample counter (when set to 1) + -- 0=not used + -- Read : counter bit[7:0] + -- 0x9004 Read: counter bit [15:8] + -- 0x9008 Read: counter bit [23:16] + -- 0x900C Read: counter bit [31:24] + -- 0x9010 Read: counter bit [39:32] + -- 0x9014 Read: counter bit [47:40] + -- 0x9018 Read: counter bit [55:48] + -- 0x901C Read: counter bit [63:56] + -- + -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) + + fauxUart: + process(cpu_clk, areset) + begin + if areset = '1' then + io_busy <= '0'; + uartTXPending <= '0'; + timer_we <= '0'; + io_busy <= '0'; + uartData <= x"58"; -- 'X' + readingTimer <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + timer_we <= '0'; + io_busy <= '0'; + if uartTXCleared = '1' then + uartTXPending <= '0'; + end if; + + if io_writeEnable = '1' then + if io_addr=x"1000" then + -- Write to UART + uartData <= mem_write(7 downto 0); + uartTXPending <= '1'; + io_busy <= '1'; + elsif io_addr(12)='1' then + timer_we <= '1'; + io_busy <= '1'; + else + report "Illegal IO write" severity failure; + end if; + end if; + if (io_readEnable = '1') then + if io_addr=x"1001" then + io_read <= (0=>'1', -- recieve empty + 1 => uartTXPending, -- tx full + others => '0'); + io_busy <= '1'; + elsif io_addr(12)='1' then + readingTimer <= '1'; + io_busy <= '1'; + elsif io_addr(11)='1' then + io_read <= ZPU_Frequency; + io_busy <= '1'; + else + report "Illegal IO read" severity failure; + end if; + + else + if (readingTimer = '1') then + readingTimer <= '0'; + io_read <= timer_read; + io_busy <= '0'; + else + io_read <= (others => '1'); + end if; + end if; + end if; + end process; + + + forwardUARTOutputToARM: + process(cpu_clk, areset) + begin + if areset = '1' then + uartTXCleared <= '0'; + elsif (cpu_clk = '1' and cpu_clk'event) then + if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then + uartTXCleared <= cpu_din(0); + else + uartTXCleared <= uartTXCleared; + end if; + end if; + end process; + + cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); + cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_writeEnable <= mem_writeEnable and mem_addr(ioBit); +-- io_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(cpu_clk, areset) + begin + if areset = '1' then + dram_read <= '0'; + io_readEnable <= '0'; + + + elsif (cpu_clk'event and cpu_clk = '1') then + mem_read <= (others => '0'); + if mem_addr(ioBit)='0' and mem_readEnable='1' then + dram_read <= '1'; + end if; + if dram_read='1' and dram_mem_busy='0' then + dram_read <= '0'; + mem_read <= dram_mem_read; + end if; + + if mem_addr(ioBit)='1' and mem_readEnable='1' then + io_readEnable <= '1'; + end if; + if io_readEnable='1' and io_busy='0' then + io_readEnable <= '0'; + mem_read(7 downto 0) <= io_read; + end if; + + end if; + end process; + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpuio_bram.vhd b/zpu/hdl/zpu4/src/zpuio_bram.vhd new file mode 100644 index 0000000..5d3f409 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpuio_bram.vhd @@ -0,0 +1,229 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); +end zpuio; + +architecture behave of zpuio is + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +--signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal Enable : std_logic; + +signal din : std_logic_vector(7 downto 0); +signal dout : std_logic_vector(7 downto 0); +signal adr : std_logic_vector(15 downto 0); +signal break : std_logic; +signal we : std_logic; +signal re : std_logic; + + +-- uart forwarding... + +signal uartTXPending : std_logic; +signal uartTXCleared : std_logic; +signal uartData : std_logic_vector(7 downto 0); + +signal readingTimer : std_logic; + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + + + +--signal io_mem_read : std_logic_vector(7 downto 0); +--signal io_mem_writeEnable : std_logic; +--signal io_mem_readEnable : std_logic; +signal io_readEnable : std_logic; + + + + + +begin + + io_addr <= mem_addr(maxAddrBit downto minAddrBit); + + timerinst: timer port map ( + clk => cpu_clk, + areset => areset, + we => timer_we, + din => mem_write(7 downto 0), + adr => io_addr(4 downto 2), + dout => timer_read); + + zpu: zpu_core port map ( + clk => cpu_clk , + areset => areset, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + + + -- Read/write are on different addresses + -- The registers are 8 bits and mapped to bit[7:0] + -- + -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) + -- Read : Reads from UART RX FIFO (4 byte FIFO) + -- 0xC004 Read : UART status register + -- Bit 0 = RX FIFO empty + -- Bit 1 = TX FIFO full + -- 0xA000 Skrive: LED's (8 stk.) + + -- 0x9000 Write: bit 0: 1= reset counter + -- 0= counter running + -- bit 1: 1= sample counter (when set to 1) + -- 0=not used + -- Read : counter bit[7:0] + -- 0x9004 Read: counter bit [15:8] + -- 0x9008 Read: counter bit [23:16] + -- 0x900C Read: counter bit [31:24] + -- 0x9010 Read: counter bit [39:32] + -- 0x9014 Read: counter bit [47:40] + -- 0x9018 Read: counter bit [55:48] + -- 0x901C Read: counter bit [63:56] + -- + -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) + + fauxUart: + process(cpu_clk, areset) + begin + if areset = '1' then + io_busy <= '0'; + uartTXPending <= '0'; + timer_we <= '0'; + io_busy <= '0'; + uartData <= x"58"; -- 'X' + readingTimer <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + timer_we <= '0'; + io_busy <= '0'; + if uartTXCleared = '1' then + uartTXPending <= '0'; + end if; + + if io_writeEnable = '1' then + if io_addr=x"1000" then + -- Write to UART + uartData <= mem_write(7 downto 0); + uartTXPending <= '1'; + io_busy <= '1'; + elsif io_addr(12)='1' then + timer_we <= '1'; + io_busy <= '1'; + else + report "Illegal IO write" severity failure; + end if; + end if; + if (io_readEnable = '1') then + if io_addr=x"1001" then + io_read <= (0=>'1', -- recieve empty + 1 => uartTXPending, -- tx full + others => '0'); + io_busy <= '1'; + elsif io_addr(12)='1' then + readingTimer <= '1'; + io_busy <= '1'; + elsif io_addr(11)='1' then + io_read <= ZPU_Frequency; + io_busy <= '1'; + else + report "Illegal IO read" severity failure; + end if; + + else + if (readingTimer = '1') then + readingTimer <= '0'; + io_read <= timer_read; + io_busy <= '0'; + else + io_read <= (others => '1'); + end if; + end if; + end if; + end process; + + + forwardUARTOutputToARM: + process(cpu_clk, areset) + begin + if areset = '1' then + uartTXCleared <= '0'; + elsif (cpu_clk = '1' and cpu_clk'event) then + if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then + uartTXCleared <= cpu_din(0); + else + uartTXCleared <= uartTXCleared; + end if; + end if; + end process; + + cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); + cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); + + io_writeEnable <= mem_writeEnable and mem_addr(ioBit); +-- io_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or io_readEnable; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(cpu_clk, areset) + begin + if areset = '1' then + io_readEnable <= '0'; + + + elsif (cpu_clk'event and cpu_clk = '1') then + mem_read <= (others => '0'); + + if mem_addr(ioBit)='1' and mem_readEnable='1' then + io_readEnable <= '1'; + end if; + if io_readEnable='1' and io_busy='0' then + io_readEnable <= '0'; + mem_read(7 downto 0) <= io_read; + end if; + + end if; + end process; + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd new file mode 100644 index 0000000..30c3e46 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpupkg.vhd @@ -0,0 +1,168 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; + +library work; +use work.zpu_config.all; + +package zpupkg is + + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + component dram is + port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); + end component; + + + component trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component; + + component zpu_core is + port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); + end component; + + + + component timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); + end component; + + component zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + + + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); + + constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); + constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6); + + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); + constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6); + + constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); + constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); + + constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); + + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6); + + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); + + + + constant OpCode_Size : integer := 8; + + + +end zpupkg; diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh new file mode 100644 index 0000000..51ff3de --- /dev/null +++ b/zpu/hdl/zpu4/test/dmips/build.sh @@ -0,0 +1,3 @@ +zpu-elf-gcc -DTIME $ZPUDIR/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -abel -o dmips.elf +zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf +zpu-elf-objcopy -O binary dmips.elf dmips.bin diff --git a/zpu/hdl/zpu4/test/dmips/dmips.bin b/zpu/hdl/zpu4/test/dmips/dmips.bin new file mode 100644 index 0000000..1330fe3 Binary files /dev/null and b/zpu/hdl/zpu4/test/dmips/dmips.bin differ diff --git a/zpu/hdl/zpu4/test/dmips/dmips.elf b/zpu/hdl/zpu4/test/dmips/dmips.elf new file mode 100644 index 0000000..7254a5d Binary files /dev/null and b/zpu/hdl/zpu4/test/dmips/dmips.elf differ diff --git a/zpu/hdl/zpu4/test/dmips/dmips.ram b/zpu/hdl/zpu4/test/dmips/dmips.ram new file mode 100644 index 0000000..27b991d --- /dev/null +++ b/zpu/hdl/zpu4/test/dmips/dmips.ram @@ -0,0 +1,3507 @@ +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80dde00c", +3 => x"3a0b0b0b", +4 => x"b9990400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0bb9e02d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80dd", +162 => x"cc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0ba1", +171 => x"c92d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0ba2", +179 => x"8d2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80dddc0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", +216 => x"71810552", +217 => x"04000000", +218 => x"00000000", +219 => x"00000000", +220 => x"00000000", +221 => x"00000000", +222 => x"00000000", +223 => x"00000000", +224 => x"00000000", +225 => x"00000000", +226 => x"00000000", +227 => x"00000000", +228 => x"00000000", +229 => x"00000000", +230 => x"00000000", +231 => x"00000000", +232 => x"02840572", +233 => x"10100552", +234 => x"04000000", +235 => x"00000000", +236 => x"00000000", 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x"00000000", +3473 => x"00000000", +3474 => x"00000000", +3475 => x"00000000", +3476 => x"00000000", +3477 => x"00000000", +3478 => x"00000000", +3479 => x"00000000", +3480 => x"00000000", +3481 => x"00000000", +3482 => x"00000000", +3483 => x"00000000", +3484 => x"00000000", +3485 => x"00000000", +3486 => x"00000000", +3487 => x"00000000", +3488 => x"00000000", +3489 => x"00000000", +3490 => x"00000000", +3491 => x"00000000", +3492 => x"00000000", +3493 => x"00000000", +3494 => x"00000000", +3495 => x"00000000", +3496 => x"00000000", +3497 => x"00000000", +3498 => x"00000000", +3499 => x"00000000", +3500 => x"00000000", +3501 => x"00000000", +3502 => x"00002dc0", +3503 => x"ffffffff", +3504 => x"00000000", +3505 => x"ffffffff", +3506 => x"00000000", diff --git a/zpu/hdl/zpu4/test/hello/build.sh b/zpu/hdl/zpu4/test/hello/build.sh new file mode 100644 index 0000000..0d81138 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/build.sh @@ -0,0 +1,3 @@ +zpu-elf-gcc -O3 -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >hello.dis hello.elf +zpu-elf-objcopy -O binary hello.elf hello.bin diff --git a/zpu/hdl/zpu4/test/hello/hello.bin b/zpu/hdl/zpu4/test/hello/hello.bin new file mode 100644 index 0000000..fe17308 Binary files /dev/null and b/zpu/hdl/zpu4/test/hello/hello.bin differ diff --git a/zpu/hdl/zpu4/test/hello/hello.c b/zpu/hdl/zpu4/test/hello/hello.c new file mode 100644 index 0000000..ea3dbb8 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/hello.c @@ -0,0 +1,51 @@ +/* + +zpu-elf-gcc -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >hello.dis hello.elf +zpu-elf-objcopy -O binary hello.elf hello.bin + + * */ +#include + +int j; +int k; + +int main(int argc, char **argv) +{ + int i; + for (i=0; i< 10; i++) + { + puts("Hello world 1\n"); + puts("Hello world 2\n"); + j=-4; + if ((j>>1)!=-2) + { + abort(); + } + + k=10; + if (k*j!=-40) + { + abort(); + } + + j=10; + k=10000000; + if (k*j!=100000000) + { + abort(); + } + + j=0x80000000; + k=0xffffffff; + if (j>k) + { + abort(); + } + } + if (i!=10) + { + abort(); + } + +} diff --git a/zpu/hdl/zpu4/test/hello/hello.elf b/zpu/hdl/zpu4/test/hello/hello.elf new file mode 100644 index 0000000..999b9a3 Binary files /dev/null and b/zpu/hdl/zpu4/test/hello/hello.elf differ diff --git a/zpu/hdl/zpu4/test/hello/hello.ram b/zpu/hdl/zpu4/test/hello/hello.ram new file mode 100644 index 0000000..f310151 --- /dev/null +++ b/zpu/hdl/zpu4/test/hello/hello.ram @@ -0,0 +1,3165 @@ +0 => x"0b0b0b0b", +1 => x"80700b0b", +2 => x"80d3900c", +3 => x"3a0b0b80", +4 => x"c8b20400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"80c8fb2d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => x"070a8106", +37 => x"53510400", +38 => x"00000000", +39 => x"00000000", +40 => x"72722473", +41 => x"732e0753", +42 => x"51040000", +43 => x"00000000", +44 => x"00000000", +45 => x"00000000", +46 => x"00000000", +47 => x"00000000", +48 => x"71737109", +49 => x"71068106", +50 => x"30720a10", +51 => x"0a720a10", +52 => x"0a31050a", +53 => x"81065151", +54 => x"53510400", +55 => x"00000000", +56 => x"72722673", +57 => x"732e0753", +58 => x"51040000", +59 => x"00000000", +60 => x"00000000", +61 => x"00000000", +62 => x"00000000", +63 => x"00000000", +64 => x"00000000", +65 => x"00000000", +66 => x"00000000", +67 => x"00000000", +68 => x"00000000", +69 => x"00000000", +70 => x"00000000", +71 => x"00000000", +72 => x"0b0b0b88", +73 => x"c4040000", +74 => x"00000000", +75 => x"00000000", +76 => x"00000000", +77 => x"00000000", +78 => x"00000000", +79 => x"00000000", +80 => x"720a722b", +81 => x"0a535104", +82 => x"00000000", +83 => x"00000000", +84 => x"00000000", +85 => x"00000000", +86 => x"00000000", +87 => x"00000000", +88 => x"72729f06", +89 => x"0981050b", +90 => x"0b0b88a7", +91 => x"05040000", +92 => x"00000000", +93 => x"00000000", +94 => x"00000000", +95 => x"00000000", +96 => x"72722aff", +97 => x"739f062a", +98 => x"0974090a", +99 => x"8106ff05", +100 => x"06075351", +101 => x"04000000", +102 => x"00000000", +103 => x"00000000", +104 => x"71715351", +105 => x"020d0406", +106 => x"73830609", +107 => x"81058205", +108 => x"832b0b2b", +109 => x"0772fc06", +110 => x"0c515104", +111 => x"00000000", +112 => x"72098105", +113 => x"72050970", +114 => x"81050906", +115 => x"0a810653", +116 => x"51040000", +117 => x"00000000", +118 => x"00000000", +119 => x"00000000", +120 => x"72098105", +121 => x"72050970", +122 => x"81050906", +123 => x"0a098106", +124 => x"53510400", +125 => x"00000000", +126 => x"00000000", +127 => x"00000000", +128 => x"71098105", +129 => x"52040000", +130 => x"00000000", +131 => x"00000000", +132 => x"00000000", +133 => x"00000000", +134 => x"00000000", +135 => x"00000000", +136 => x"72720981", +137 => x"05055351", +138 => x"04000000", +139 => x"00000000", +140 => x"00000000", +141 => x"00000000", +142 => x"00000000", +143 => x"00000000", +144 => x"72097206", +145 => x"73730906", +146 => x"07535104", +147 => x"00000000", +148 => x"00000000", +149 => x"00000000", +150 => x"00000000", +151 => x"00000000", +152 => x"71fc0608", +153 => x"72830609", +154 => x"81058305", +155 => x"1010102a", +156 => x"81ff0652", +157 => x"04000000", +158 => x"00000000", +159 => x"00000000", +160 => x"71fc0608", +161 => x"0b0b80d2", +162 => x"fc738306", +163 => x"10100508", +164 => x"060b0b0b", +165 => x"88aa0400", +166 => x"00000000", +167 => x"00000000", +168 => x"80088408", +169 => x"88087575", +170 => x"0b0b0b8d", +171 => x"872d5050", +172 => x"80085688", +173 => x"0c840c80", +174 => x"0c510400", +175 => x"00000000", +176 => x"80088408", +177 => x"88087575", +178 => x"0b0b0b8d", +179 => x"cb2d5050", +180 => x"80085688", +181 => x"0c840c80", +182 => x"0c510400", +183 => x"00000000", +184 => x"72097081", +185 => x"0509060a", +186 => x"8106ff05", +187 => x"70547106", +188 => x"73097274", +189 => x"05ff0506", +190 => x"07515151", +191 => x"04000000", +192 => x"72097081", +193 => x"0509060a", +194 => x"098106ff", +195 => x"05705471", +196 => x"06730972", +197 => x"7405ff05", +198 => x"06075151", +199 => x"51040000", +200 => x"05ff0504", +201 => x"00000000", +202 => x"00000000", +203 => x"00000000", +204 => x"00000000", +205 => x"00000000", +206 => x"00000000", +207 => x"00000000", +208 => x"810b0b0b", +209 => x"80d38c0c", +210 => x"51040000", +211 => x"00000000", +212 => x"00000000", +213 => x"00000000", +214 => x"00000000", +215 => x"00000000", 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x"00000000", +2868 => x"00000000", +2869 => x"00000000", +2870 => x"00000000", +2871 => x"00000000", +2872 => x"00000000", +2873 => x"00000000", +2874 => x"00000000", +2875 => x"00000000", +2876 => x"00000000", +2877 => x"00000000", +2878 => x"00000000", +2879 => x"00000000", +2880 => x"00000000", +2881 => x"00000000", +2882 => x"00000000", +2883 => x"00000000", +2884 => x"00000000", +2885 => x"00000000", +2886 => x"00000000", +2887 => x"00000000", +2888 => x"00000000", +2889 => x"00000000", +2890 => x"00000000", +2891 => x"00000000", +2892 => x"00000000", +2893 => x"00000000", +2894 => x"00000000", +2895 => x"00000000", +2896 => x"00000000", +2897 => x"00000000", +2898 => x"00000000", +2899 => x"ffffffff", +2900 => x"00000000", +2901 => x"00020000", +2902 => x"00000000", +2903 => x"00000000", +2904 => x"00002d58", +2905 => x"00002d58", +2906 => x"00002d60", +2907 => x"00002d60", +2908 => x"00002d68", +2909 => x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => 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x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"00002fa8", +3053 => x"00002fa8", +3054 => x"00002fb0", +3055 => x"00002fb0", +3056 => x"00002fb8", +3057 => x"00002fb8", +3058 => x"00002fc0", +3059 => x"00002fc0", +3060 => x"00002fc8", +3061 => x"00002fc8", +3062 => x"00002fd0", +3063 => x"00002fd0", +3064 => x"00002fd8", +3065 => x"00002fd8", +3066 => x"00002fe0", +3067 => x"00002fe0", +3068 => x"00002fe8", +3069 => x"00002fe8", +3070 => x"00002ff0", +3071 => x"00002ff0", +3072 => x"00002ff8", +3073 => x"00002ff8", +3074 => x"00003000", +3075 => x"00003000", +3076 => x"00003008", +3077 => x"00003008", +3078 => x"00003010", +3079 => x"00003010", +3080 => x"00003018", +3081 => x"00003018", +3082 => x"00003020", +3083 => x"00003020", +3084 => x"00003028", +3085 => x"00003028", +3086 => x"00003030", +3087 => x"00003030", +3088 => x"00003038", +3089 => x"00003038", +3090 => x"00003040", +3091 => x"00003040", +3092 => x"00003048", +3093 => x"00003048", +3094 => x"00003050", +3095 => x"00003050", +3096 => x"00003058", +3097 => x"00003058", +3098 => x"00003060", +3099 => x"00003060", +3100 => x"00003068", +3101 => x"00003068", +3102 => x"00003070", +3103 => x"00003070", +3104 => x"00003078", +3105 => x"00003078", +3106 => x"00003080", +3107 => x"00003080", +3108 => x"00003088", +3109 => x"00003088", +3110 => x"00003090", +3111 => x"00003090", +3112 => x"00003098", +3113 => x"00003098", +3114 => x"000030a0", +3115 => x"000030a0", +3116 => x"000030a8", +3117 => x"000030a8", +3118 => x"000030b0", +3119 => x"000030b0", +3120 => x"000030b8", +3121 => x"000030b8", +3122 => x"000030c0", +3123 => x"000030c0", +3124 => x"000030c8", +3125 => x"000030c8", +3126 => x"000030d0", +3127 => x"000030d0", +3128 => x"000030d8", +3129 => x"000030d8", +3130 => x"000030e0", +3131 => x"000030e0", +3132 => x"000030e8", +3133 => x"000030e8", +3134 => x"000030f0", +3135 => x"000030f0", +3136 => x"000030f8", +3137 => x"000030f8", +3138 => x"00003100", +3139 => x"00003100", +3140 => x"00003108", +3141 => x"00003108", +3142 => x"00003110", +3143 => x"00003110", +3144 => x"00003118", +3145 => x"00003118", +3146 => x"00003120", +3147 => x"00003120", +3148 => x"00003128", +3149 => x"00003128", +3150 => x"00003130", +3151 => x"00003130", +3152 => x"00003138", +3153 => x"00003138", +3154 => x"00003140", +3155 => x"00003140", +3156 => x"00003148", +3157 => x"00003148", +3158 => x"00003150", +3159 => x"00003150", +3160 => x"00002970", +3161 => x"ffffffff", +3162 => x"00000000", +3163 => x"ffffffff", +3164 => x"00000000", -- cgit v1.1 From 4a419c5aa7ef974279042ebfba2aed2adab197db Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 21 Feb 2008 18:59:45 +0000 Subject: * zpu/zpu/hdl/index.html. Sharpened instructions and shows two working examples. Small & medium ZPU. * got zpu4/src/simzpu_medium.do working again. --- zpu/hdl/zpu4/src/dram_hello.vhd | 5167 ++++++++++++++-------------- zpu/hdl/zpu4/src/fasthello.do | 19 + zpu/hdl/zpu4/src/io.vhd | 23 +- zpu/hdl/zpu4/src/log.txt | 139 +- zpu/hdl/zpu4/src/sim_fpga_top.vhd | 11 +- zpu/hdl/zpu4/src/simzpu.do | 23 - zpu/hdl/zpu4/src/simzpu_intstack.do | 23 - zpu/hdl/zpu4/src/simzpu_medium.do | 28 + zpu/hdl/zpu4/src/zpu_config_trace.vhd | 6 +- zpu/hdl/zpu4/src/zpu_core.vhd | 4 +- zpu/hdl/zpu4/src/zpu_core_small.vhd | 13 + zpu/hdl/zpu4/src/zpuio.vhd | 32 +- zpu/hdl/zpu4/src/zpupkg.vhd | 11 - zpu/hdl/zpu4/test/dmips/build.sh | 1 + zpu/hdl/zpu4/test/dmips/dmips.ram | 5969 +++++++++++++++++---------------- zpu/hdl/zpu4/test/hello/build.sh | 3 +- zpu/hdl/zpu4/test/hello/hello.bin | Bin 12664 -> 12224 bytes zpu/hdl/zpu4/test/hello/hello.c | 8 +- zpu/hdl/zpu4/test/hello/hello.elf | Bin 150455 -> 150384 bytes zpu/hdl/zpu4/test/hello/hello.ram | 5150 ++++++++++++++-------------- 20 files changed, 8232 insertions(+), 8398 deletions(-) create mode 100644 zpu/hdl/zpu4/src/fasthello.do delete mode 100644 zpu/hdl/zpu4/src/simzpu.do delete mode 100644 zpu/hdl/zpu4/src/simzpu_intstack.do create mode 100644 zpu/hdl/zpu4/src/simzpu_medium.do (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/dram_hello.vhd b/zpu/hdl/zpu4/src/dram_hello.vhd index dc46dbb..3f7788a 100644 --- a/zpu/hdl/zpu4/src/dram_hello.vhd +++ b/zpu/hdl/zpu4/src/dram_hello.vhd @@ -9,6 +9,7 @@ use work.zpupkg.all; entity dram is port (clk : in std_logic; +areset : std_logic; mem_writeEnable : in std_logic; mem_readEnable : in std_logic; mem_addr : in std_logic_vector(maxAddrBit downto 0); @@ -21,21 +22,21 @@ end dram; architecture dram_arch of dram is -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( 0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80d3900c", +1 => x"82700b0b", +2 => x"80cfd80c", 3 => x"3a0b0b80", -4 => x"c8b20400", +4 => x"c6d00400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"80c8fb2d", +10 => x"80c7972d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -186,8 +187,8 @@ shared variable ram : ram_type := 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80d2", -162 => x"fc738306", +161 => x"0b0b80cf", +162 => x"c4738306", 163 => x"10100508", 164 => x"060b0b0b", 165 => x"88aa0400", @@ -195,16 +196,16 @@ shared variable ram : ram_type := 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0b8d", -171 => x"872d5050", +170 => x"0b0b0b8b", +171 => x"9f2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0b8d", -179 => x"cb2d5050", +178 => x"0b0b0b8b", +179 => x"e32d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -234,7 +235,7 @@ shared variable ram : ram_type := 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80d38c0c", +209 => x"80cfd40c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -281,8 +282,8 @@ shared variable ram : ram_type := 253 => x"00000000", 254 => x"00000000", 255 => x"00000000", -256 => x"83d93f80", -257 => x"ca953f04", +256 => x"82c53f80", +257 => x"c6d93f04", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -305,2394 +306,2394 @@ shared variable ram : ram_type := 277 => x"0a100a53", 278 => x"72ed3851", 279 => x"51535104", -280 => x"ff3d0d0b", -281 => x"0b80e2f8", -282 => x"08528412", -283 => x"08708106", -284 => x"515170f6", -285 => x"38710881", -286 => x"ff06800c", -287 => x"833d0d04", -288 => x"ff3d0d0b", -289 => x"0b80e2f8", -290 => x"08528412", -291 => x"08700a10", -292 => x"0a708106", -293 => x"51515170", -294 => x"f1387372", -295 => x"0c833d0d", -296 => x"0480d38c", -297 => x"08802ea8", -298 => x"38838080", -299 => x"0b0b0b80", -300 => x"e2f80c82", -301 => x"a0800b0b", -302 => x"0b80e2fc", -303 => x"0c829080", -304 => x"0b80e38c", -305 => x"0c0b0b80", -306 => x"e3800b80", -307 => x"e3900c04", -308 => x"f8808080", -309 => x"a40b0b0b", -310 => x"80e2f80c", -311 => x"f8808082", -312 => x"800b0b0b", -313 => x"80e2fc0c", -314 => x"f8808084", -315 => x"800b80e3", -316 => x"8c0cf880", -317 => x"8080940b", -318 => x"80e3900c", -319 => x"f8808080", -320 => x"9c0b80e3", -321 => x"880cf880", -322 => x"8080a00b", -323 => x"80e3940c", -324 => x"04f23d0d", -325 => x"600b0b80", -326 => x"e2fc0856", -327 => x"5d82750c", -328 => x"8059805a", -329 => x"800b8f3d", -330 => x"71101017", -331 => x"70085957", -332 => x"5d5b8076", -333 => x"81ff067c", -334 => x"832b5658", -335 => x"5276537b", -336 => x"5181fa3f", -337 => x"7d7f7a72", -338 => x"077c7207", -339 => x"71716081", -340 => x"05415f5d", -341 => x"5b595755", -342 => x"7a8724bb", -343 => x"380b0b80", -344 => x"e2fc087b", -345 => x"10101170", -346 => x"08585155", -347 => x"807681ff", -348 => x"067c832b", -349 => x"56585276", -350 => x"537b5181", -351 => x"c03f7d7f", -352 => x"7a72077c", -353 => x"72077171", -354 => x"60810541", -355 => x"5f5d5b59", -356 => x"5755877b", -357 => x"25c73876", -358 => x"7d0c7784", -359 => x"1e0c7c80", -360 => x"0c903d0d", -361 => x"04ff3d0d", -362 => x"80e38433", -363 => x"5170a738", -364 => x"80d39808", -365 => x"70085252", -366 => x"70802e94", -367 => x"38841280", -368 => x"d3980c70", -369 => x"2d80d398", -370 => x"08700852", -371 => x"5270ee38", -372 => x"810b80e3", -373 => x"8434833d", -374 => x"0d040480", -375 => x"3d0d0b0b", -376 => x"80e2f408", -377 => x"802e8e38", -378 => x"0b0b0b0b", -379 => x"800b802e", -380 => x"09810685", -381 => x"38823d0d", -382 => x"040b0b80", -383 => x"e2f4510b", -384 => x"0b0bf3fc", -385 => x"3f823d0d", -386 => x"0404fe3d", -387 => x"0d89530b", -388 => x"0b80d2c8", -389 => x"51838d3f", -390 => x"0b0b80d2", -391 => x"d8518384", -392 => x"3f810a0b", -393 => x"80e3980c", -394 => x"ff0b80e3", -395 => x"9c0cff13", -396 => x"53728025", -397 => x"da387280", -398 => x"0c843d0d", -399 => x"04f93d0d", -400 => x"797b7d7f", -401 => x"56545254", -402 => x"72802ea0", -403 => x"38705771", -404 => x"58a07331", -405 => x"52807225", -406 => x"a1387770", -407 => x"742b5770", -408 => x"732a7875", -409 => x"2b075651", -410 => x"74765351", -411 => x"70740c71", -412 => x"84150c73", -413 => x"800c893d", -414 => x"0d048056", -415 => x"7772302b", -416 => x"55747653", -417 => x"51e639fb", -418 => x"3d0d7779", -419 => x"55558056", -420 => x"757524ab", -421 => x"38807424", -422 => x"9d388053", -423 => x"73527451", -424 => x"80e13f80", -425 => x"08547580", -426 => x"2e853880", -427 => x"08305473", -428 => x"800c873d", -429 => x"0d047330", -430 => x"76813257", -431 => x"54dc3974", -432 => x"30558156", -433 => x"738025d2", -434 => x"38ec39fa", -435 => x"3d0d787a", -436 => x"57558057", -437 => x"767524a4", -438 => x"38759f2c", -439 => x"54815375", -440 => x"74327431", -441 => x"5274519b", -442 => x"3f800854", -443 => x"76802e85", -444 => x"38800830", -445 => x"5473800c", -446 => x"883d0d04", -447 => x"74305581", -448 => x"57d739fc", -449 => x"3d0d7678", -450 => x"53548153", -451 => x"80747326", -452 => x"52557280", -453 => x"2e983870", -454 => x"802eab38", -455 => x"807224a6", -456 => x"38711073", -457 => x"10757226", -458 => x"53545272", -459 => x"ea387351", -460 => x"78833874", -461 => x"5170800c", -462 => x"863d0d04", -463 => x"720a100a", -464 => x"720a100a", -465 => x"53537280", -466 => x"2ee43871", -467 => x"7426ed38", -468 => x"73723175", -469 => x"7407740a", -470 => x"100a740a", -471 => x"100a5555", -472 => x"5654e339", -473 => x"f73d0d7c", -474 => x"70525380", -475 => x"f93f7254", -476 => x"80085580", -477 => x"d2e85681", -478 => x"57800881", -479 => x"055a8b3d", -480 => x"e4115953", -481 => x"8259f413", -482 => x"527b8811", -483 => x"08525381", -484 => x"b03f8008", -485 => x"30708008", -486 => x"079f2c8a", -487 => x"07800c53", -488 => x"8b3d0d04", -489 => x"f63d0d7c", -490 => x"80d39c08", -491 => x"71535553", -492 => x"b53f7255", -493 => x"80085680", -494 => x"d2e85781", -495 => x"58800881", -496 => x"055b8c3d", -497 => x"e4115a53", -498 => x"825af413", -499 => x"52881408", -500 => x"5180ee3f", -501 => x"80083070", -502 => x"8008079f", -503 => x"2c8a0780", -504 => x"0c548c3d", -505 => x"0d04fd3d", -506 => x"0d757071", -507 => x"83065355", -508 => x"5270b438", -509 => x"71700870", -510 => x"09f7fbfd", -511 => x"ff1206f8", -512 => x"84828180", -513 => x"06545253", -514 => x"719b3884", -515 => x"13700870", -516 => x"09f7fbfd", -517 => x"ff1206f8", -518 => x"84828180", -519 => x"06545253", -520 => x"71802ee7", -521 => x"38725271", -522 => x"33537280", -523 => x"2e8a3881", -524 => x"12703354", -525 => x"5272f838", -526 => x"71743180", -527 => x"0c853d0d", -528 => x"04f23d0d", -529 => x"60628811", -530 => x"08705856", -531 => x"5f5a7380", -532 => x"2e818c38", -533 => x"8c1a2270", -534 => x"832a8132", -535 => x"81065658", -536 => x"74863890", -537 => x"1a089138", -538 => x"795190b7", -539 => x"3fff5580", -540 => x"0880ec38", -541 => x"8c1a2258", -542 => x"7d085580", -543 => x"7883ffff", -544 => x"06700a10", -545 => x"0a810641", -546 => x"5c577e77", -547 => x"2e80d738", -548 => x"76903874", -549 => x"08841608", -550 => x"88175758", -551 => x"5676802e", -552 => x"f2387654", -553 => x"88807727", -554 => x"84388880", -555 => x"54735375", -556 => x"529c1a08", -557 => x"51a41a08", -558 => x"58772d80", -559 => x"0b800825", -560 => x"82e03880", -561 => x"08167780", -562 => x"08317f88", -563 => x"05088008", -564 => x"31706188", -565 => x"050c5b58", -566 => x"5678ffb4", -567 => x"38805574", -568 => x"800c903d", -569 => x"0d047a81", -570 => x"32810677", -571 => x"40567580", -572 => x"2e81bd38", -573 => x"76903874", -574 => x"08841608", -575 => x"88175758", -576 => x"5976802e", -577 => x"f238881a", -578 => x"087883ff", -579 => x"ff067089", -580 => x"2a810656", -581 => x"59567380", -582 => x"2e82f838", -583 => x"7577278b", -584 => x"3877872a", -585 => x"81065c7b", -586 => x"82b53876", -587 => x"76278338", -588 => x"76567553", -589 => x"78527908", -590 => x"5185833f", -591 => x"881a0876", -592 => x"31881b0c", -593 => x"7908167a", -594 => x"0c765675", -595 => x"19777731", -596 => x"7f880508", -597 => x"78317061", -598 => x"88050c41", -599 => x"58597e80", -600 => x"2efefa38", -601 => x"8c1a2258", -602 => x"ff8a3978", -603 => x"79547c53", -604 => x"7b525684", -605 => x"c93f881a", -606 => x"08793188", -607 => x"1b0c7908", -608 => x"197a0c7c", -609 => x"76315d7c", -610 => x"8e387951", -611 => x"8ff23f80", -612 => x"08818f38", -613 => x"80085f75", -614 => x"1c777731", -615 => x"7f880508", -616 => x"78317061", -617 => x"88050c5d", -618 => x"585c7a80", -619 => x"2efeae38", -620 => x"76818338", -621 => x"74088416", -622 => x"08881757", -623 => x"585c7680", -624 => x"2ef23876", -625 => x"538a527b", -626 => x"5182d33f", -627 => x"80087c31", -628 => x"81055d80", -629 => x"08843881", -630 => x"175d815f", -631 => x"7c59767d", -632 => x"27833876", -633 => x"59941a08", -634 => x"881b0811", -635 => x"5758807a", -636 => x"085c5490", -637 => x"1a087b27", -638 => x"83388154", -639 => x"75792584", -640 => x"3873ba38", -641 => x"777924fe", -642 => x"e2387753", -643 => x"7b529c1a", -644 => x"0851a41a", -645 => x"0859782d", -646 => x"80085680", -647 => x"088024fe", -648 => x"e2388c1a", -649 => x"2280c007", -650 => x"5e7d8c1b", -651 => x"23ff5574", -652 => x"800c903d", -653 => x"0d047eff", -654 => x"a338ff87", -655 => x"3975537b", -656 => x"527a5182", -657 => x"f93f7908", -658 => x"167a0c79", -659 => x"518eb13f", -660 => x"8008cf38", -661 => x"7c76315d", -662 => x"7cfebc38", -663 => x"feac3990", -664 => x"1a087a08", -665 => x"71317811", -666 => x"70565a57", -667 => x"5280d39c", -668 => x"08518494", -669 => x"3f800880", -670 => x"2effa738", -671 => x"8008901b", -672 => x"0c800816", -673 => x"7a0c7794", -674 => x"1b0c7688", -675 => x"1b0c7656", -676 => x"fd993979", -677 => x"0858901a", -678 => x"08782783", -679 => x"38815475", -680 => x"77278438", -681 => x"73b33894", -682 => x"1a085473", -683 => x"772680d3", -684 => x"38735378", -685 => x"529c1a08", -686 => x"51a41a08", -687 => x"58772d80", -688 => x"08568008", -689 => x"8024fd83", -690 => x"388c1a22", -691 => x"80c0075e", -692 => x"7d8c1b23", -693 => x"ff55fed7", -694 => x"39755378", -695 => x"52775181", -696 => x"dd3f7908", -697 => x"167a0c79", -698 => x"518d953f", -699 => x"8008802e", -700 => x"fcd9388c", -701 => x"1a2280c0", -702 => x"075e7d8c", -703 => x"1b23ff55", -704 => x"fead3976", -705 => x"77547953", -706 => x"78525681", -707 => x"b13f881a", -708 => x"08773188", -709 => x"1b0c7908", -710 => x"177a0cfc", -711 => x"ae39fa3d", -712 => x"0d7a7902", -713 => x"8805a705", -714 => x"33555354", -715 => x"83742780", -716 => x"df387183", -717 => x"06517080", -718 => x"d7387171", -719 => x"57558351", -720 => x"75828029", -721 => x"13ff1252", -722 => x"56708025", -723 => x"f3388374", -724 => x"27bc3874", -725 => x"08763270", -726 => x"09f7fbfd", -727 => x"ff1206f8", -728 => x"84828180", -729 => x"06515170", -730 => x"802e9838", -731 => x"74518052", -732 => x"70335772", -733 => x"772eb938", -734 => x"81118113", -735 => x"53518372", -736 => x"27ee38fc", -737 => x"14841656", -738 => x"54738326", -739 => x"c6387452", -740 => x"ff145170", -741 => x"ff2e9738", -742 => x"71335472", -743 => x"742e9838", -744 => x"8112ff12", -745 => x"525270ff", -746 => x"2e098106", -747 => x"eb388051", -748 => x"70800c88", -749 => x"3d0d0471", -750 => x"800c883d", -751 => x"0d04fa3d", -752 => x"0d787a7c", -753 => x"72727259", -754 => x"57555856", -755 => x"57747727", -756 => x"b2387515", -757 => x"51767127", -758 => x"aa387076", -759 => x"18ff1853", -760 => x"535370ff", -761 => x"2e9638ff", -762 => x"12ff1454", -763 => x"52723372", -764 => x"34ff1151", -765 => x"70ff2e09", -766 => x"8106ec38", -767 => x"76800c88", -768 => x"3d0d048f", -769 => x"762780e6", -770 => x"38747707", -771 => x"83065170", -772 => x"80dc3876", -773 => x"75525370", -774 => x"70840552", -775 => x"08737084", -776 => x"05550c72", -777 => x"71708405", -778 => x"53087170", -779 => x"8405530c", -780 => x"71708405", -781 => x"53087170", -782 => x"8405530c", -783 => x"71708405", -784 => x"53087170", -785 => x"8405530c", -786 => x"f0155553", -787 => x"738f26c7", -788 => x"38837427", -789 => x"95387070", -790 => x"84055208", -791 => x"73708405", -792 => x"550cfc14", -793 => x"54738326", -794 => x"ed387271", -795 => x"5452ff14", -796 => x"5170ff2e", -797 => x"ff863872", -798 => x"70810554", -799 => x"33727081", -800 => x"055434ff", -801 => x"1151ea39", -802 => x"ef3d0d63", -803 => x"6567405d", -804 => x"427b802e", -805 => x"85823861", -806 => x"51a9eb3f", -807 => x"f81c7084", -808 => x"120870fc", -809 => x"0670628b", -810 => x"0570f806", -811 => x"4159455c", -812 => x"5f415796", -813 => x"742782c5", -814 => x"38807b24", -815 => x"7e7c2607", -816 => x"58805477", -817 => x"742e0981", -818 => x"0682ab38", -819 => x"787b2581", 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x"51c3fd3f", +2269 => x"80085186", +2270 => x"c23f7280", +2271 => x"dfd40cc2", +2272 => x"a53fc0fc", +2273 => x"3f80dfa8", +2274 => x"528151c3", +2275 => x"e33f8008", +2276 => x"5186a83f", +2277 => x"00ff3900", +2278 => x"ff39f53d", +2279 => x"0d7e6080", +2280 => x"dfd40870", +2281 => x"5b585b5b", +2282 => x"7580c238", +2283 => x"777a25a1", +2284 => x"38771b70", +2285 => x"337081ff", +2286 => x"06585859", +2287 => x"758a2e98", +2288 => x"387681ff", +2289 => x"0651c1bd", +2290 => x"3f811858", +2291 => x"797824e1", +2292 => x"3879800c", +2293 => x"8d3d0d04", +2294 => x"8d51c1a9", +2295 => x"3f783370", +2296 => x"81ff0652", +2297 => x"57c19e3f", +2298 => x"811858e0", +2299 => x"3979557a", +2300 => x"547d5385", +2301 => x"528d3dfc", +2302 => x"0551c0c6", +2303 => x"3f800856", +2304 => x"85b23f7b", +2305 => x"80080c75", +2306 => x"800c8d3d", +2307 => x"0d04f63d", +2308 => x"0d7d7f80", +2309 => x"dfd40870", +2310 => x"5b585a5a", +2311 => x"7580c138", +2312 => x"777925b3", +2313 => x"38c0b93f", +2314 => x"800881ff", +2315 => x"06708d32", +2316 => x"7030709f", +2317 => x"2a515157", +2318 => x"57768a2e", +2319 => x"80c43875", +2320 => x"802ebf38", +2321 => x"771a5676", +2322 => x"76347651", +2323 => x"c0b73f81", +2324 => x"18587878", +2325 => x"24cf3877", +2326 => x"5675800c", +2327 => x"8c3d0d04", +2328 => x"78557954", +2329 => x"7c538452", +2330 => x"8c3dfc05", +2331 => x"51ffbfd2", +2332 => x"3f800856", +2333 => x"84be3f7a", +2334 => x"80080c75", +2335 => x"800c8c3d", +2336 => x"0d04771a", +2337 => x"598a7934", +2338 => x"8118588d", +2339 => x"51ffbff5", +2340 => x"3f8a51ff", +2341 => x"bfef3f77", +2342 => x"56ffbe39", +2343 => x"fb3d0d80", +2344 => x"dfd40870", +2345 => x"56547388", +2346 => x"3874800c", +2347 => x"873d0d04", +2348 => x"77538352", +2349 => x"873dfc05", +2350 => x"51ffbf86", +2351 => x"3f800854", +2352 => x"83f23f75", +2353 => x"80080c73", +2354 => x"800c873d", +2355 => x"0d04fa3d", +2356 => x"0d80dfd4", +2357 => x"08802ea3", +2358 => x"387a5579", +2359 => x"54785386", +2360 => x"52883dfc", +2361 => x"0551ffbe", +2362 => x"d93f8008", +2363 => x"5683c53f", +2364 => x"7680080c", +2365 => x"75800c88", +2366 => x"3d0d0483", +2367 => x"b73f9d0b", +2368 => x"80080cff", +2369 => x"0b800c88", +2370 => x"3d0d04f7", +2371 => x"3d0d7b7d", +2372 => x"5b59bc53", +2373 => x"80527951", +2374 => x"f5f83f80", +2375 => x"70565798", +2376 => x"56741970", +2377 => x"3370782b", +2378 => x"79078118", +2379 => x"f81a5a58", +2380 => x"59555884", +2381 => x"7524ea38", +2382 => x"767a2384", +2383 => x"19588070", +2384 => x"56579856", +2385 => x"74187033", +2386 => x"70782b79", +2387 => x"078118f8", +2388 => x"1a5a5859", +2389 => x"51548475", +2390 => x"24ea3876", +2391 => x"821b2388", +2392 => x"19588070", +2393 => x"56579856", +2394 => x"74187033", +2395 => x"70782b79", +2396 => x"078118f8", +2397 => x"1a5a5859", +2398 => x"51548475", +2399 => x"24ea3876", +2400 => x"841b0c8c", +2401 => x"19588070", +2402 => x"56579856", +2403 => x"74187033", +2404 => x"70782b79", +2405 => x"078118f8", +2406 => x"1a5a5859", +2407 => x"51548475", +2408 => x"24ea3876", +2409 => x"881b2390", +2410 => x"19588070", +2411 => x"56579856", +2412 => x"74187033", +2413 => x"70782b79", +2414 => x"078118f8", +2415 => x"1a5a5859", +2416 => x"51548475", +2417 => x"24ea3876", +2418 => x"8a1b2394", +2419 => x"19588070", +2420 => x"56579856", +2421 => x"74187033", +2422 => x"70782b79", +2423 => x"078118f8", +2424 => x"1a5a5859", +2425 => x"51548475", +2426 => x"24ea3876", +2427 => x"8c1b2398", +2428 => x"19588070", +2429 => x"56579856", +2430 => x"74187033", +2431 => x"70782b79", +2432 => x"078118f8", +2433 => x"1a5a5859", +2434 => x"51548475", +2435 => x"24ea3876", +2436 => x"8e1b239c", +2437 => x"19588070", +2438 => x"5657b856", +2439 => x"74187033", +2440 => x"70782b79", +2441 => x"078118f8", +2442 => x"1a5a5859", +2443 => x"5a548875", +2444 => x"24ea3876", +2445 => x"901b0c8b", +2446 => x"3d0d04e9", +2447 => x"3d0d6a80", +2448 => x"dfd40857", +2449 => x"57759338", +2450 => x"80c0800b", +2451 => x"84180c75", +2452 => x"ac180c75", +2453 => x"800c993d", +2454 => x"0d04893d", +2455 => x"70556a54", +2456 => x"558a5299", +2457 => x"3dffbc05", +2458 => x"51ffbbd6", +2459 => x"3f800877", +2460 => x"53755256", +2461 => x"fd953fbc", +2462 => x"3f778008", +2463 => x"0c75800c", +2464 => x"993d0d04", +2465 => x"fc3d0d81", +2466 => x"5480dfd4", +2467 => x"08883873", +2468 => x"800c863d", +2469 => x"0d047653", +2470 => x"97b95286", +2471 => x"3dfc0551", +2472 => x"ffbb9f3f", +2473 => x"8008548c", +2474 => x"3f748008", +2475 => x"0c73800c", +2476 => x"863d0d04", +2477 => x"80cfe408", +2478 => x"800c04f7", +2479 => x"3d0d7b80", +2480 => x"cfe40882", +2481 => x"c811085a", +2482 => x"545a7780", +2483 => x"2e80da38", +2484 => x"81881884", +2485 => x"1908ff05", +2486 => x"81712b59", +2487 => x"55598074", +2488 => x"2480ea38", +2489 => x"807424b5", +2490 => x"3873822b", +2491 => x"78118805", +2492 => x"56568180", +2493 => x"19087706", +2494 => x"5372802e", +2495 => x"b6387816", +2496 => x"70085353", +2497 => x"79517408", +2498 => x"53722dff", +2499 => x"14fc17fc", +2500 => x"1779812c", +2501 => x"5a575754", +2502 => x"738025d6", +2503 => x"38770858", +2504 => x"77ffad38", +2505 => x"80cfe408", +2506 => x"53bc1308", +2507 => x"a5387951", +2508 => x"f8e23f74", +2509 => x"0853722d", +2510 => x"ff14fc17", +2511 => x"fc177981", +2512 => x"2c5a5757", +2513 => x"54738025", +2514 => x"ffa838d1", +2515 => x"398057ff", +2516 => x"93397251", +2517 => x"bc130854", +2518 => x"732d7951", +2519 => x"f8b63f70", +2520 => x"7080dfb0", +2521 => x"0bfc0570", +2522 => x"08525270", +2523 => x"ff2e9138", +2524 => x"702dfc12", +2525 => x"70085252", +2526 => x"70ff2e09", +2527 => x"8106f138", +2528 => x"50500404", +2529 => x"ffbb8c3f", +2530 => x"04000000", +2531 => x"00000040", +2532 => x"48656c6c", +2533 => x"6f20776f", +2534 => x"726c6420", +2535 => x"310a0000", +2536 => x"48656c6c", +2537 => x"6f20776f", +2538 => x"726c6420", +2539 => x"320a0000", +2540 => x"0a000000", +2541 => x"43000000", +2542 => x"64756d6d", +2543 => x"792e6578", +2544 => x"65000000", +2545 => x"00ffffff", +2546 => x"ff00ffff", +2547 => x"ffff00ff", +2548 => x"ffffff00", +2549 => x"00000000", +2550 => x"00000000", +2551 => x"00000000", +2552 => x"00002fb8", +2553 => x"000027e8", +2554 => x"00000000", +2555 => x"00002a50", +2556 => x"00002aac", +2557 => x"00002b08", +2558 => x"00000000", +2559 => x"00000000", +2560 => x"00000000", +2561 => x"00000000", +2562 => x"00000000", +2563 => x"00000000", +2564 => x"00000000", +2565 => x"00000000", +2566 => x"00000000", +2567 => x"000027b4", +2568 => x"00000000", +2569 => x"00000000", +2570 => x"00000000", +2571 => x"00000000", +2572 => x"00000000", +2573 => x"00000000", +2574 => x"00000000", +2575 => x"00000000", +2576 => x"00000000", +2577 => x"00000000", +2578 => x"00000000", +2579 => x"00000000", +2580 => x"00000000", +2581 => x"00000000", +2582 => x"00000000", +2583 => x"00000000", +2584 => x"00000000", +2585 => x"00000000", +2586 => x"00000000", +2587 => x"00000000", +2588 => x"00000000", +2589 => x"00000000", +2590 => x"00000000", +2591 => x"00000000", +2592 => x"00000000", +2593 => x"00000000", +2594 => x"00000000", +2595 => x"00000000", +2596 => x"00000001", +2597 => x"330eabcd", +2598 => x"1234e66d", +2599 => x"deec0005", +2600 => x"000b0000", +2601 => x"00000000", +2602 => x"00000000", +2603 => x"00000000", +2604 => x"00000000", +2605 => x"00000000", +2606 => x"00000000", +2607 => x"00000000", +2608 => x"00000000", +2609 => x"00000000", +2610 => x"00000000", +2611 => x"00000000", +2612 => x"00000000", +2613 => x"00000000", +2614 => x"00000000", +2615 => x"00000000", +2616 => x"00000000", +2617 => x"00000000", +2618 => x"00000000", +2619 => x"00000000", +2620 => x"00000000", +2621 => x"00000000", +2622 => x"00000000", +2623 => x"00000000", +2624 => x"00000000", +2625 => x"00000000", +2626 => x"00000000", +2627 => x"00000000", +2628 => x"00000000", +2629 => x"00000000", +2630 => x"00000000", +2631 => x"00000000", +2632 => x"00000000", +2633 => x"00000000", +2634 => x"00000000", +2635 => x"00000000", +2636 => x"00000000", +2637 => x"00000000", +2638 => x"00000000", +2639 => x"00000000", +2640 => x"00000000", +2641 => x"00000000", +2642 => x"00000000", +2643 => x"00000000", +2644 => x"00000000", +2645 => x"00000000", +2646 => x"00000000", +2647 => x"00000000", +2648 => x"00000000", +2649 => x"00000000", +2650 => x"00000000", +2651 => x"00000000", +2652 => x"00000000", +2653 => x"00000000", +2654 => x"00000000", +2655 => x"00000000", +2656 => x"00000000", +2657 => x"00000000", +2658 => x"00000000", 2659 => x"00000000", 2660 => x"00000000", 2661 => x"00000000", -2662 => x"00003170", -2663 => x"000029a0", +2662 => x"00000000", +2663 => x"00000000", 2664 => x"00000000", -2665 => x"00002c08", -2666 => x"00002c64", -2667 => x"00002cc0", +2665 => x"00000000", +2666 => x"00000000", +2667 => x"00000000", 2668 => x"00000000", 2669 => x"00000000", 2670 => x"00000000", @@ -2702,7 +2703,7 @@ shared variable ram : ram_type := 2674 => x"00000000", 2675 => x"00000000", 2676 => x"00000000", -2677 => x"0000296c", +2677 => x"00000000", 2678 => x"00000000", 2679 => x"00000000", 2680 => x"00000000", @@ -2731,11 +2732,11 @@ shared variable ram : ram_type := 2703 => x"00000000", 2704 => x"00000000", 2705 => x"00000000", -2706 => x"00000001", -2707 => x"330eabcd", -2708 => x"1234e66d", -2709 => x"deec0005", -2710 => x"000b0000", +2706 => x"00000000", +2707 => x"00000000", +2708 => x"00000000", +2709 => x"00000000", +2710 => x"00000000", 2711 => x"00000000", 2712 => x"00000000", 2713 => x"00000000", @@ -2814,121 +2815,121 @@ shared variable ram : ram_type := 2786 => x"00000000", 2787 => x"00000000", 2788 => x"00000000", -2789 => x"00000000", +2789 => x"ffffffff", 2790 => x"00000000", -2791 => x"00000000", +2791 => x"00020000", 2792 => x"00000000", 2793 => x"00000000", -2794 => x"00000000", -2795 => x"00000000", -2796 => x"00000000", -2797 => x"00000000", -2798 => x"00000000", -2799 => x"00000000", -2800 => x"00000000", -2801 => x"00000000", -2802 => x"00000000", -2803 => x"00000000", -2804 => x"00000000", -2805 => x"00000000", -2806 => x"00000000", -2807 => x"00000000", -2808 => x"00000000", -2809 => x"00000000", -2810 => x"00000000", -2811 => x"00000000", -2812 => x"00000000", -2813 => x"00000000", -2814 => x"00000000", -2815 => x"00000000", -2816 => x"00000000", -2817 => x"00000000", -2818 => x"00000000", -2819 => x"00000000", -2820 => x"00000000", -2821 => x"00000000", -2822 => x"00000000", -2823 => x"00000000", -2824 => x"00000000", -2825 => x"00000000", -2826 => x"00000000", -2827 => x"00000000", -2828 => x"00000000", -2829 => x"00000000", -2830 => x"00000000", -2831 => x"00000000", -2832 => x"00000000", -2833 => x"00000000", -2834 => x"00000000", -2835 => x"00000000", -2836 => x"00000000", -2837 => x"00000000", -2838 => x"00000000", -2839 => x"00000000", -2840 => x"00000000", -2841 => x"00000000", -2842 => x"00000000", -2843 => x"00000000", -2844 => x"00000000", -2845 => x"00000000", -2846 => x"00000000", -2847 => x"00000000", -2848 => x"00000000", -2849 => x"00000000", -2850 => x"00000000", -2851 => x"00000000", -2852 => x"00000000", -2853 => x"00000000", -2854 => x"00000000", -2855 => x"00000000", -2856 => x"00000000", -2857 => x"00000000", -2858 => x"00000000", -2859 => x"00000000", -2860 => x"00000000", -2861 => x"00000000", -2862 => x"00000000", -2863 => x"00000000", -2864 => x"00000000", -2865 => x"00000000", -2866 => x"00000000", -2867 => x"00000000", -2868 => x"00000000", -2869 => x"00000000", -2870 => x"00000000", -2871 => x"00000000", -2872 => x"00000000", -2873 => x"00000000", -2874 => x"00000000", -2875 => x"00000000", -2876 => x"00000000", -2877 => x"00000000", -2878 => x"00000000", -2879 => x"00000000", -2880 => x"00000000", -2881 => x"00000000", -2882 => x"00000000", -2883 => x"00000000", -2884 => x"00000000", -2885 => x"00000000", -2886 => x"00000000", -2887 => x"00000000", -2888 => x"00000000", -2889 => x"00000000", -2890 => x"00000000", -2891 => x"00000000", -2892 => x"00000000", -2893 => x"00000000", -2894 => x"00000000", -2895 => x"00000000", -2896 => x"00000000", -2897 => x"00000000", -2898 => x"00000000", -2899 => x"ffffffff", -2900 => x"00000000", -2901 => x"00020000", -2902 => x"00000000", -2903 => x"00000000", +2794 => x"00002ba0", +2795 => x"00002ba0", +2796 => x"00002ba8", +2797 => x"00002ba8", +2798 => x"00002bb0", +2799 => x"00002bb0", +2800 => x"00002bb8", +2801 => x"00002bb8", +2802 => x"00002bc0", +2803 => x"00002bc0", +2804 => x"00002bc8", +2805 => x"00002bc8", +2806 => x"00002bd0", +2807 => x"00002bd0", +2808 => x"00002bd8", +2809 => x"00002bd8", +2810 => x"00002be0", +2811 => x"00002be0", +2812 => x"00002be8", +2813 => x"00002be8", +2814 => x"00002bf0", +2815 => x"00002bf0", +2816 => x"00002bf8", +2817 => x"00002bf8", +2818 => x"00002c00", +2819 => x"00002c00", +2820 => x"00002c08", +2821 => x"00002c08", +2822 => x"00002c10", +2823 => x"00002c10", +2824 => x"00002c18", +2825 => x"00002c18", +2826 => x"00002c20", +2827 => x"00002c20", +2828 => x"00002c28", +2829 => x"00002c28", +2830 => x"00002c30", +2831 => x"00002c30", +2832 => x"00002c38", +2833 => x"00002c38", +2834 => x"00002c40", +2835 => x"00002c40", +2836 => x"00002c48", +2837 => x"00002c48", +2838 => x"00002c50", +2839 => x"00002c50", +2840 => x"00002c58", +2841 => x"00002c58", +2842 => x"00002c60", +2843 => x"00002c60", +2844 => x"00002c68", +2845 => x"00002c68", +2846 => x"00002c70", +2847 => x"00002c70", +2848 => x"00002c78", +2849 => x"00002c78", +2850 => x"00002c80", +2851 => x"00002c80", +2852 => x"00002c88", +2853 => x"00002c88", +2854 => x"00002c90", +2855 => x"00002c90", +2856 => x"00002c98", +2857 => x"00002c98", +2858 => x"00002ca0", +2859 => x"00002ca0", +2860 => x"00002ca8", +2861 => x"00002ca8", +2862 => x"00002cb0", +2863 => x"00002cb0", +2864 => x"00002cb8", +2865 => x"00002cb8", +2866 => x"00002cc0", +2867 => x"00002cc0", +2868 => x"00002cc8", +2869 => x"00002cc8", +2870 => x"00002cd0", +2871 => x"00002cd0", +2872 => x"00002cd8", +2873 => x"00002cd8", +2874 => x"00002ce0", +2875 => x"00002ce0", +2876 => x"00002ce8", +2877 => x"00002ce8", +2878 => x"00002cf0", +2879 => x"00002cf0", +2880 => x"00002cf8", +2881 => x"00002cf8", +2882 => x"00002d00", +2883 => x"00002d00", +2884 => x"00002d08", +2885 => x"00002d08", +2886 => x"00002d10", +2887 => x"00002d10", +2888 => x"00002d18", +2889 => x"00002d18", +2890 => x"00002d20", +2891 => x"00002d20", +2892 => x"00002d28", +2893 => x"00002d28", +2894 => x"00002d30", +2895 => x"00002d30", +2896 => x"00002d38", +2897 => x"00002d38", +2898 => x"00002d40", +2899 => x"00002d40", +2900 => x"00002d48", +2901 => x"00002d48", +2902 => x"00002d50", +2903 => x"00002d50", 2904 => x"00002d58", 2905 => x"00002d58", 2906 => x"00002d60", @@ -3075,133 +3076,25 @@ shared variable ram : ram_type := 3047 => x"00002f90", 3048 => x"00002f98", 3049 => x"00002f98", -3050 => x"00002fa0", -3051 => x"00002fa0", -3052 => x"00002fa8", -3053 => x"00002fa8", -3054 => x"00002fb0", -3055 => x"00002fb0", -3056 => x"00002fb8", -3057 => x"00002fb8", -3058 => x"00002fc0", -3059 => x"00002fc0", -3060 => x"00002fc8", -3061 => x"00002fc8", -3062 => x"00002fd0", -3063 => x"00002fd0", -3064 => x"00002fd8", -3065 => x"00002fd8", -3066 => x"00002fe0", -3067 => x"00002fe0", -3068 => x"00002fe8", -3069 => x"00002fe8", -3070 => x"00002ff0", -3071 => x"00002ff0", -3072 => x"00002ff8", -3073 => x"00002ff8", -3074 => x"00003000", -3075 => x"00003000", -3076 => x"00003008", -3077 => x"00003008", -3078 => x"00003010", -3079 => x"00003010", -3080 => x"00003018", -3081 => x"00003018", -3082 => x"00003020", -3083 => x"00003020", -3084 => x"00003028", -3085 => x"00003028", -3086 => x"00003030", -3087 => x"00003030", -3088 => x"00003038", -3089 => x"00003038", -3090 => x"00003040", -3091 => x"00003040", -3092 => x"00003048", -3093 => x"00003048", -3094 => x"00003050", -3095 => x"00003050", -3096 => x"00003058", -3097 => x"00003058", -3098 => x"00003060", -3099 => x"00003060", -3100 => x"00003068", -3101 => x"00003068", -3102 => x"00003070", -3103 => x"00003070", -3104 => x"00003078", -3105 => x"00003078", -3106 => x"00003080", -3107 => x"00003080", -3108 => x"00003088", -3109 => x"00003088", -3110 => x"00003090", -3111 => x"00003090", -3112 => x"00003098", -3113 => x"00003098", -3114 => x"000030a0", -3115 => x"000030a0", -3116 => x"000030a8", -3117 => x"000030a8", -3118 => x"000030b0", -3119 => x"000030b0", -3120 => x"000030b8", -3121 => x"000030b8", -3122 => x"000030c0", -3123 => x"000030c0", -3124 => x"000030c8", -3125 => x"000030c8", -3126 => x"000030d0", -3127 => x"000030d0", -3128 => x"000030d8", -3129 => x"000030d8", -3130 => x"000030e0", -3131 => x"000030e0", -3132 => x"000030e8", -3133 => x"000030e8", -3134 => x"000030f0", -3135 => x"000030f0", -3136 => x"000030f8", -3137 => x"000030f8", -3138 => x"00003100", -3139 => x"00003100", -3140 => x"00003108", -3141 => x"00003108", -3142 => x"00003110", -3143 => x"00003110", -3144 => x"00003118", -3145 => x"00003118", -3146 => x"00003120", -3147 => x"00003120", -3148 => x"00003128", -3149 => x"00003128", -3150 => x"00003130", -3151 => x"00003130", -3152 => x"00003138", -3153 => x"00003138", -3154 => x"00003140", -3155 => x"00003140", -3156 => x"00003148", -3157 => x"00003148", -3158 => x"00003150", -3159 => x"00003150", -3160 => x"00002970", -3161 => x"ffffffff", -3162 => x"00000000", -3163 => x"ffffffff", -3164 => x"00000000", +3050 => x"000027b8", +3051 => x"ffffffff", +3052 => x"00000000", +3053 => x"ffffffff", +3054 => x"00000000", others => x"00000000" ); begin -process (clk) +mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request + +process (clk, areset) begin - if (clk'event and clk = '1') then - mem_busy<=mem_writeEnable or mem_readEnable; - if (mem_writeEnable = '1') then - ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; - end if; + if areset = '1' then + elsif (clk'event and clk = '1') then + if (mem_writeEnable = '1') then + ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + end if; if (mem_readEnable = '1') then mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); end if; diff --git a/zpu/hdl/zpu4/src/fasthello.do b/zpu/hdl/zpu4/src/fasthello.do new file mode 100644 index 0000000..d49aeab --- /dev/null +++ b/zpu/hdl/zpu4/src/fasthello.do @@ -0,0 +1,19 @@ +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_fastsim.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_hello.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + + +vsim fpga_top +view wave + +# run ZPU +run 60000 ms diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index b5465d1..7dbe36f 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -19,8 +19,8 @@ entity zpu_io is busy : out std_logic; writeEnable : in std_logic; readEnable : in std_logic; - write : in std_logic_vector(7 downto 0); - read : out std_logic_vector(7 downto 0); + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); addr : in std_logic_vector(maxAddrBit downto minAddrBit) ); end zpu_io; @@ -45,7 +45,7 @@ begin clk => clk, areset => areset, we => timer_we, - din => write, + din => write(7 downto 0), adr => addr(4 downto 2), dout => timer_read); @@ -60,7 +60,7 @@ begin -- timer_we <= '0'; if writeEnable = '1' then -- external interface - if addr=x"1000" then + if addr=x"2028003" then -- Write to UART -- report "" & character'image(conv_integer(memBint)) severity note; print(l_file, character'val(conv_integer(write))); @@ -68,20 +68,25 @@ begin -- report "xxx" severity failure; -- timer_we <= '1'; else - report "Illegal IO write" severity failure; + print(l_file, character'val(conv_integer(write))); + report "Illegal IO write" severity warning; end if; end if; - read <= (others => 'U'); + read <= (others => '0'); if (readEnable = '1') then if addr=x"1001" then read <= (0=>'1', others => '0'); -- recieve empty elsif addr(12)='1' then - read <= timer_read; + read(7 downto 0) <= timer_read; elsif addr(11)='1' then - read <= ZPU_Frequency; + read(7 downto 0) <= ZPU_Frequency; + elsif addr=x"2028003" then + read <= (others => '0'); else - report "Illegal IO read" severity failure; + read <= (others => '0'); + read(8) <= '1'; + report "Illegal IO read" severity warning; end if; end if; end if; diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt index af58c93..10f0eaa 100644 --- a/zpu/hdl/zpu4/src/log.txt +++ b/zpu/hdl/zpu4/src/log.txt @@ -11,10 +11,10 @@ l d 1 + - - + H @@ -30,10 +30,10 @@ l d 2 + - - + H @@ -49,10 +49,10 @@ l d 1 + - - + H @@ -68,10 +68,10 @@ l d 2 + - - + H @@ -87,10 +87,10 @@ l d 1 + - - + H @@ -106,10 +106,10 @@ l d 2 + - - + H @@ -125,10 +125,10 @@ l d 1 + - - + H @@ -144,10 +144,10 @@ l d 2 + - - + H @@ -163,10 +163,10 @@ l d 1 + - - + H @@ -182,10 +182,10 @@ l d 2 + - - + H @@ -201,10 +201,10 @@ l d 1 + - - + H @@ -220,10 +220,10 @@ l d 2 + - - + H @@ -239,10 +239,10 @@ l d 1 + - - + H @@ -258,10 +258,10 @@ l d 2 + - - + H @@ -277,10 +277,10 @@ l d 1 + - - + H @@ -296,85 +296,10 @@ l d 2 + - - + H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd index 2905505..4defc82 100644 --- a/zpu/hdl/zpu4/src/sim_fpga_top.vhd +++ b/zpu/hdl/zpu4/src/sim_fpga_top.vhd @@ -52,8 +52,8 @@ component zpu_io is busy : out std_logic; writeEnable : in std_logic; readEnable : in std_logic; - write : in std_logic_vector(7 downto 0); - read : out std_logic_vector(7 downto 0); + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); addr : in std_logic_vector(maxAddrBit downto minAddrBit) ); end component; @@ -82,7 +82,7 @@ signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); signal io_busy : std_logic; -signal io_mem_read : std_logic_vector(7 downto 0); +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); signal io_mem_writeEnable : std_logic; signal io_mem_readEnable : std_logic; @@ -131,7 +131,7 @@ begin busy => io_busy, writeEnable => io_mem_writeEnable, readEnable => io_mem_readEnable, - write => mem_write(7 downto 0), + write => mem_write(wordSize-1 downto 0), read => io_mem_read, addr => mem_addr(maxAddrBit downto minAddrBit) ); @@ -154,8 +154,7 @@ begin end if; if io_ready='1' then - mem_read <= (others => '0'); - mem_read(7 downto 0) <= io_mem_read; + mem_read <= io_mem_read; end if; end process; diff --git a/zpu/hdl/zpu4/src/simzpu.do b/zpu/hdl/zpu4/src/simzpu.do deleted file mode 100644 index e6e3068..0000000 --- a/zpu/hdl/zpu4/src/simzpu.do +++ /dev/null @@ -1,23 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - -# run ZPU -vsim fpga_top -view wave -add wave -recursive fpga_top/zpu/* -#add wave -recursive fpga_top/* -view structure -#view signals - -# Enough to run tiny programs -run 1000 ms diff --git a/zpu/hdl/zpu4/src/simzpu_intstack.do b/zpu/hdl/zpu4/src/simzpu_intstack.do deleted file mode 100644 index cec4873..0000000 --- a/zpu/hdl/zpu4/src/simzpu_intstack.do +++ /dev/null @@ -1,23 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_intstack.vhd -vcom -93 -explicit dram_hello.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - -# run ZPU -vsim fpga_top -view wave -add wave -recursive fpga_top/zpu/* -#add wave -recursive fpga_top/* -view structure -#view signals - -# Enough to run tiny programs -run 15 ms diff --git a/zpu/hdl/zpu4/src/simzpu_medium.do b/zpu/hdl/zpu4/src/simzpu_medium.do new file mode 100644 index 0000000..a6c1fe2 --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu_medium.do @@ -0,0 +1,28 @@ +# Xilinx WebPack modelsim script +# +# cd C:/workspace/zpu/zpu/hdl/zpu4/src +# do simzpu_medium.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core.vhd +vcom -93 -explicit dram_hello.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 1000 ms diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd index d1bbbbb..a2d7d9d 100644 --- a/zpu/hdl/zpu4/src/zpu_config_trace.vhd +++ b/zpu/hdl/zpu4/src/zpu_config_trace.vhd @@ -5,11 +5,13 @@ use ieee.std_logic_unsigned.all; package zpu_config is constant Generate_Trace : boolean := true; - constant wordPower : integer := 5; + constant wordPower : integer := 5; -- during simulation, set this to '0' to get matching trace.txt constant DontCareValue : std_logic := '0'; -- Clock frequency in MHz. constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; - constant maxAddrBitIncIO : integer := 15; + constant maxAddrBitIncIO : integer := 27; + constant maxAddrBitDRAM : integer := 16; + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/src/zpu_core.vhd index c7093e2..a603fe9 100644 --- a/zpu/hdl/zpu4/src/zpu_core.vhd +++ b/zpu/hdl/zpu4/src/zpu_core.vhd @@ -210,9 +210,7 @@ begin if areset = '1' then state <= State_Idle; break <= '0'; - -- point to top of RAM-8 - sp <= (others => '0'); - sp(maxAddrBit downto minAddrBit+1) <= (others => '1'); + sp <= spStart(maxAddrBitIncIO downto minAddrBit); pc <= (others => '0'); idim_flag <= '0'; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd index 4d73f88..8ebd40d 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -27,6 +27,19 @@ end zpu_core; architecture behave of zpu_core is +component dualport_ram is +port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); +end component; + + signal readIO : std_logic; diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd index d14629e..09a1ddd 100644 --- a/zpu/hdl/zpu4/src/zpuio.vhd +++ b/zpu/hdl/zpu4/src/zpuio.vhd @@ -115,30 +115,6 @@ ram_imp: dram port map ( mem_writeMask => mem_writeMask); - -- Read/write are on different addresses - -- The registers are 8 bits and mapped to bit[7:0] - -- - -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) - -- Read : Reads from UART RX FIFO (4 byte FIFO) - -- 0xC004 Read : UART status register - -- Bit 0 = RX FIFO empty - -- Bit 1 = TX FIFO full - -- 0xA000 Skrive: LED's (8 stk.) - - -- 0x9000 Write: bit 0: 1= reset counter - -- 0= counter running - -- bit 1: 1= sample counter (when set to 1) - -- 0=not used - -- Read : counter bit[7:0] - -- 0x9004 Read: counter bit [15:8] - -- 0x9008 Read: counter bit [23:16] - -- 0x900C Read: counter bit [31:24] - -- 0x9010 Read: counter bit [39:32] - -- 0x9014 Read: counter bit [47:40] - -- 0x9018 Read: counter bit [55:48] - -- 0x901C Read: counter bit [63:56] - -- - -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) fauxUart: process(cpu_clk, areset) @@ -158,7 +134,7 @@ ram_imp: dram port map ( end if; if io_writeEnable = '1' then - if io_addr=x"1000" then + if io_addr=x"2028003" then -- Write to UART uartData <= mem_write(7 downto 0); uartTXPending <= '1'; @@ -167,11 +143,11 @@ ram_imp: dram port map ( timer_we <= '1'; io_busy <= '1'; else - report "Illegal IO write" severity failure; +-- report "Illegal IO write" severity failure; end if; end if; if (io_readEnable = '1') then - if io_addr=x"1001" then + if io_addr=x"2028003" then io_read <= (0=>'1', -- recieve empty 1 => uartTXPending, -- tx full others => '0'); @@ -183,7 +159,7 @@ ram_imp: dram port map ( io_read <= ZPU_Frequency; io_busy <= '1'; else - report "Illegal IO read" severity failure; +-- report "Illegal IO read" severity failure; end if; else diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd index 30c3e46..fd00b9e 100644 --- a/zpu/hdl/zpu4/src/zpupkg.vhd +++ b/zpu/hdl/zpu4/src/zpupkg.vhd @@ -23,17 +23,6 @@ package zpupkg is constant stack_bits : integer := 5; constant stack_size : integer := 2**stack_bits; - component dualport_ram is - port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); - end component; component dram is port (clk : in std_logic; diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh index 51ff3de..161c748 100644 --- a/zpu/hdl/zpu4/test/dmips/build.sh +++ b/zpu/hdl/zpu4/test/dmips/build.sh @@ -1,3 +1,4 @@ zpu-elf-gcc -DTIME $ZPUDIR/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -abel -o dmips.elf zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf zpu-elf-objcopy -O binary dmips.elf dmips.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam dmips.bin >dmips.ram diff --git a/zpu/hdl/zpu4/test/dmips/dmips.ram b/zpu/hdl/zpu4/test/dmips/dmips.ram index 27b991d..89047d5 100644 --- a/zpu/hdl/zpu4/test/dmips/dmips.ram +++ b/zpu/hdl/zpu4/test/dmips/dmips.ram @@ -1,14 +1,14 @@ 0 => x"0b0b0b0b", 1 => x"80700b0b", -2 => x"80dde00c", -3 => x"3a0b0b0b", -4 => x"b9990400", +2 => x"80e2a40c", +3 => x"3a0b0b80", +4 => x"c6fc0400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"0bb9e02d", +10 => x"80c7c32d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -159,8 +159,8 @@ 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80dd", -162 => x"cc738306", +161 => x"0b0b80e2", +162 => x"90738306", 163 => x"10100508", 164 => x"060b0b0b", 165 => x"88aa0400", @@ -168,16 +168,16 @@ 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0ba1", -171 => x"c92d5050", +170 => x"0b0b0baf", +171 => x"ac2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0ba2", -179 => x"8d2d5050", +178 => x"0b0b0baf", +179 => x"f02d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -207,7 +207,7 @@ 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80dddc0c", +209 => x"80e2a00c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -255,7 +255,7 @@ 254 => x"00000000", 255 => x"00000000", 256 => x"83d93f80", -257 => x"c78e3f04", +257 => x"cbcf3f04", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -279,7 +279,7 @@ 278 => x"72ed3851", 279 => x"51535104", 280 => x"ff3d0d0b", -281 => x"0b80edd0", +281 => x"0b80f294", 282 => x"08528412", 283 => x"08708106", 284 => x"515170f6", @@ -287,44 +287,44 @@ 286 => x"ff06800c", 287 => x"833d0d04", 288 => x"ff3d0d0b", -289 => x"0b80edd0", +289 => x"0b80f294", 290 => x"08528412", 291 => x"08700a10", 292 => x"0a708106", 293 => x"51515170", 294 => x"f1387372", 295 => x"0c833d0d", -296 => x"0480dddc", +296 => x"0480e2a0", 297 => x"08802ea8", 298 => x"38838080", 299 => x"0b0b0b80", -300 => x"edd00c82", +300 => x"f2940c82", 301 => x"a0800b0b", -302 => x"0b80edd4", +302 => x"0b80f298", 303 => x"0c829080", -304 => x"0b80ede4", +304 => x"0b80f2a8", 305 => x"0c0b0b80", -306 => x"edd80b80", -307 => x"ede80c04", +306 => x"f29c0b80", +307 => x"f2ac0c04", 308 => x"f8808080", 309 => x"a40b0b0b", -310 => x"80edd00c", +310 => x"80f2940c", 311 => x"f8808082", 312 => x"800b0b0b", -313 => x"80edd40c", +313 => x"80f2980c", 314 => x"f8808084", -315 => x"800b80ed", -316 => x"e40cf880", +315 => x"800b80f2", +316 => x"a80cf880", 317 => x"8080940b", -318 => x"80ede80c", +318 => x"80f2ac0c", 319 => x"f8808080", -320 => x"9c0b80ed", -321 => x"e00cf880", +320 => x"9c0b80f2", +321 => x"a40cf880", 322 => x"8080a00b", -323 => x"80edec0c", +323 => x"80f2b00c", 324 => x"04f23d0d", 325 => x"600b0b80", -326 => x"edd40856", +326 => x"f2980856", 327 => x"5d82750c", 328 => x"8059805a", 329 => x"800b8f3d", @@ -334,7 +334,7 @@ 333 => x"81ff067c", 334 => x"832b5658", 335 => x"5276537b", -336 => x"5196bc3f", +336 => x"519af33f", 337 => x"7d7f7a72", 338 => x"077c7207", 339 => x"71716081", @@ -342,14 +342,14 @@ 341 => x"5b595755", 342 => x"7a8724bb", 343 => x"380b0b80", -344 => x"edd4087b", +344 => x"f298087b", 345 => x"10101170", 346 => x"08585155", 347 => x"807681ff", 348 => x"067c832b", 349 => x"56585276", -350 => x"537b5196", -351 => x"823f7d7f", +350 => x"537b519a", +351 => x"b93f7d7f", 352 => x"7a72077c", 353 => x"72077171", 354 => x"60810541", @@ -360,28 +360,28 @@ 359 => x"1e0c7c80", 360 => x"0c903d0d", 361 => x"04ff3d0d", -362 => x"80eddc33", +362 => x"80f2a033", 363 => x"5170a738", -364 => x"80dde808", +364 => x"80e2ac08", 365 => x"70085252", 366 => x"70802e94", 367 => x"38841280", -368 => x"dde80c70", -369 => x"2d80dde8", +368 => x"e2ac0c70", +369 => x"2d80e2ac", 370 => x"08700852", 371 => x"5270ee38", -372 => x"810b80ed", -373 => x"dc34833d", +372 => x"810b80f2", +373 => x"a034833d", 374 => x"0d040480", 375 => x"3d0d0b0b", -376 => x"80edcc08", +376 => x"80f29008", 377 => x"802e8e38", 378 => x"0b0b0b0b", 379 => x"800b802e", 380 => x"09810685", 381 => x"38823d0d", 382 => x"040b0b80", -383 => x"edcc510b", +383 => x"f290510b", 384 => x"0b0bf3fc", 385 => x"3f823d0d", 386 => x"0404ff3d", @@ -477,116 +477,116 @@ 476 => x"56758024", 477 => x"fef338fe", 478 => x"8f398a52", -479 => x"7351938d", +479 => x"7351a0f0", 480 => x"3f80080b", -481 => x"0b80cfc0", +481 => x"0b80d484", 482 => x"05337670", 483 => x"81055834", 484 => x"8a527351", -485 => x"92b33f80", +485 => x"a0963f80", 486 => x"08548008", 487 => x"802effac", 488 => x"388a5273", -489 => x"5192e63f", +489 => x"51a0c93f", 490 => x"80080b0b", -491 => x"80cfc005", +491 => x"80d48405", 492 => x"33767081", 493 => x"0558348a", -494 => x"52735192", -495 => x"8c3f8008", +494 => x"5273519f", +495 => x"ef3f8008", 496 => x"548008ff", 497 => x"b538ff84", 498 => x"39745276", 499 => x"53b43dff", -500 => x"b8055190", -501 => x"ff3fa33d", +500 => x"b8055195", +501 => x"b63fa33d", 502 => x"0856fed9", 503 => x"39803d0d", 504 => x"80c10b81", -505 => x"bc9c3480", -506 => x"0b81bdf4", +505 => x"c0f43480", +506 => x"0b81c2d0", 507 => x"0c70800c", 508 => x"823d0d04", 509 => x"ff3d0d80", -510 => x"0b81bc9c", +510 => x"0b81c0f4", 511 => x"33525270", 512 => x"80c12e99", -513 => x"387181bd", -514 => x"f4080781", -515 => x"bdf40c80", -516 => x"c20b81bc", -517 => x"a0347080", +513 => x"387181c2", +514 => x"d0080781", +515 => x"c2d00c80", +516 => x"c20b81c0", +517 => x"f8347080", 518 => x"0c833d0d", 519 => x"04810b81", -520 => x"bdf40807", -521 => x"81bdf40c", +520 => x"c2d00807", +521 => x"81c2d00c", 522 => x"80c20b81", -523 => x"bca03470", +523 => x"c0f83470", 524 => x"800c833d", 525 => x"0d04fd3d", 526 => x"0d757008", 527 => x"8a055353", -528 => x"81bc9c33", +528 => x"81c0f433", 529 => x"517080c1", 530 => x"2e8b3873", 531 => x"f3387080", 532 => x"0c853d0d", 533 => x"04ff1270", -534 => x"81bc9808", +534 => x"81c0f008", 535 => x"31740c80", 536 => x"0c853d0d", 537 => x"04fc3d0d", -538 => x"81bca408", +538 => x"81c0fc08", 539 => x"5574802e", 540 => x"8c387675", 541 => x"08710c81", -542 => x"bca40856", +542 => x"c0fc0856", 543 => x"548c1553", -544 => x"81bc9808", -545 => x"528a518d", -546 => x"b83f7380", +544 => x"81c0f008", +545 => x"528a5190", +546 => x"f03f7380", 547 => x"0c863d0d", 548 => x"04fb3d0d", 549 => x"77700856", 550 => x"56b05381", -551 => x"bca40852", -552 => x"74519ed1", +551 => x"c0fc0852", +552 => x"7451acb4", 553 => x"3f850b8c", 554 => x"170c850b", 555 => x"8c160c75", 556 => x"08750c81", -557 => x"bca40854", +557 => x"c0fc0854", 558 => x"73802e8a", 559 => x"38730875", -560 => x"0c81bca4", +560 => x"0c81c0fc", 561 => x"08548c14", -562 => x"5381bc98", +562 => x"5381c0f0", 563 => x"08528a51", -564 => x"8cef3f84", +564 => x"90a73f84", 565 => x"1508ad38", 566 => x"860b8c16", 567 => x"0c881552", 568 => x"88160851", -569 => x"8bfb3f81", -570 => x"bca40870", +569 => x"8fb33f81", +570 => x"c0fc0870", 571 => x"08760c54", 572 => x"8c157054", 573 => x"548a5273", -574 => x"08518cc5", +574 => x"08518ffd", 575 => x"3f73800c", 576 => x"873d0d04", 577 => x"750854b0", 578 => x"53735275", -579 => x"519de63f", +579 => x"51abc93f", 580 => x"73800c87", -581 => x"3d0d04e1", +581 => x"3d0d04d9", 582 => x"3d0db051", -583 => x"91883f80", -584 => x"0881bc94", -585 => x"0cb05190", -586 => x"fd3f8008", -587 => x"81bca40c", -588 => x"81bc9408", +583 => x"9eeb3f80", +584 => x"0881c0ec", +585 => x"0cb0519e", +586 => x"e03f8008", +587 => x"81c0fc0c", +588 => x"81c0ec08", 589 => x"80080c80", 590 => x"0b800884", 591 => x"050c820b", @@ -594,2838 +594,2838 @@ 593 => x"0ca80b80", 594 => x"088c050c", 595 => x"9f530b0b", -596 => x"80cfcc52", +596 => x"80d49052", 597 => x"80089005", -598 => x"519d9a3f", -599 => x"993d5c9f", +598 => x"51aafd3f", +599 => x"a13d5e9f", 600 => x"530b0b80", -601 => x"cfec527b", -602 => x"519d8a3f", -603 => x"8a0b80fa", -604 => x"dc0c0b0b", -605 => x"80da9051", +601 => x"d4b0527d", +602 => x"51aaed3f", +603 => x"8a0b80ff", +604 => x"b00c0b0b", +605 => x"80ded451", 606 => x"f9b43f0b", -607 => x"0b80d08c", +607 => x"0b80d4d0", 608 => x"51f9ab3f", -609 => x"0b0b80da", -610 => x"9051f9a2", -611 => x"3f80ddf0", -612 => x"08802e89", -613 => x"aa380b0b", -614 => x"80d0bc51", +609 => x"0b0b80de", +610 => x"d451f9a2", +611 => x"3f80e2b4", +612 => x"08802e8a", +613 => x"cf380b0b", +614 => x"80d58051", 615 => x"f9903f0b", -616 => x"0b80da90", +616 => x"0b80ded4", 617 => x"51f9873f", -618 => x"80ddec08", +618 => x"80e2b008", 619 => x"520b0b80", -620 => x"d0e851f8", -621 => x"f93f8051", -622 => x"aecb3f80", -623 => x"0880edfc", -624 => x"0c810b92", -625 => x"3d5c5880", -626 => x"0b80ddec", -627 => x"082582d5", -628 => x"388e3d5d", -629 => x"80c10b81", -630 => x"bc9c3481", -631 => x"0b81bdf4", -632 => x"0c80c20b", -633 => x"81bca034", -634 => x"825e835a", -635 => x"9f530b0b", -636 => x"80d19852", -637 => x"7a519bfd", -638 => x"3f815f80", -639 => x"7b537c52", -640 => x"558be23f", -641 => x"8008752e", -642 => x"09810683", -643 => x"38815574", -644 => x"81bdf40c", -645 => x"7d705755", -646 => x"748325a1", -647 => x"38741010", -648 => x"15fd0540", -649 => x"a13dffbc", -650 => x"05538352", -651 => x"75518a91", -652 => x"3f811e70", -653 => x"5f705755", -654 => x"837524e1", -655 => x"387f5474", -656 => x"5380ee80", -657 => x"5281bcac", -658 => x"518a863f", -659 => x"81bca408", -660 => x"70085757", -661 => x"b0537652", -662 => x"75519b99", -663 => x"3f850b8c", -664 => x"180c850b", -665 => x"8c170c76", -666 => x"08760c81", -667 => x"bca40855", -668 => x"74802e8a", -669 => x"38740876", -670 => x"0c81bca4", -671 => x"08558c15", -672 => x"5381bc98", -673 => x"08528a51", -674 => x"89b73f84", -675 => x"160887b8", -676 => x"38860b8c", -677 => x"170c8816", -678 => x"52881708", -679 => x"5188c23f", -680 => x"81bca408", -681 => x"7008770c", -682 => x"578c1670", -683 => x"54558a52", -684 => x"74085189", -685 => x"8c3f80c1", -686 => x"0b81bca0", -687 => x"33565675", -688 => x"7526a238", -689 => x"80c35275", -690 => x"5189f03f", -691 => x"80087f2e", -692 => x"87b13881", -693 => x"167081ff", -694 => x"0681bca0", -695 => x"33525755", -696 => x"747627e0", -697 => x"38797e29", -698 => x"60705471", -699 => x"5358558b", -700 => x"d83f8008", -701 => x"5e747731", -702 => x"70872980", -703 => x"08318008", -704 => x"8a0581bc", -705 => x"9c3381bc", -706 => x"98085a5a", -707 => x"525b5576", -708 => x"80c12e87", -709 => x"9d3878f7", -710 => x"38811858", -711 => x"80ddec08", -712 => x"7825fdb0", -713 => x"388051ab", -714 => x"dc3f8008", -715 => x"81bc900c", -716 => x"0b0b80d1", -717 => x"b851f5f6", -718 => x"3f0b0b80", -719 => x"da9051f5", -720 => x"ed3f0b0b", -721 => x"80d1c851", -722 => x"f5e43f0b", -723 => x"0b80da90", -724 => x"51f5db3f", -725 => x"81bc9808", -726 => x"520b0b80", -727 => x"d28051f5", -728 => x"cd3f8552", -729 => x"0b0b80d2", -730 => x"9c51f5c2", -731 => x"3f81bdf4", -732 => x"08520b0b", -733 => x"80d2b851", -734 => x"f5b43f81", -735 => x"520b0b80", -736 => x"d29c51f5", -737 => x"a93f81bc", -738 => x"9c33520b", -739 => x"0b80d2d4", -740 => x"51f59b3f", -741 => x"80c1520b", -742 => x"0b80d2f0", -743 => x"51f58f3f", -744 => x"81bca033", -745 => x"520b0b80", -746 => x"d38c51f5", -747 => x"813f80c2", -748 => x"520b0b80", -749 => x"d2f051f4", -750 => x"f53f81bc", -751 => x"cc08520b", -752 => x"0b80d3a8", -753 => x"51f4e73f", -754 => x"87520b0b", -755 => x"80d29c51", -756 => x"f4dc3f80", -757 => x"fadc0852", -758 => x"0b0b80d3", -759 => x"c451f4ce", -760 => x"3f0b0b80", -761 => x"d3e051f4", -762 => x"c53f0b0b", -763 => x"80d48c51", -764 => x"f4bc3f81", -765 => x"bca40870", -766 => x"0853560b", -767 => x"0b80d498", -768 => x"51f4ab3f", -769 => x"0b0b80d4", -770 => x"b451f4a2", -771 => x"3f81bca4", -772 => x"08841108", -773 => x"535d0b0b", -774 => x"80d4e851", -775 => x"f4903f80", -776 => x"520b0b80", -777 => x"d29c51f4", -778 => x"853f81bc", -779 => x"a4088811", -780 => x"0853580b", -781 => x"0b80d584", -782 => x"51f3f33f", -783 => x"82520b0b", -784 => x"80d29c51", -785 => x"f3e83f81", -786 => x"bca4088c", -787 => x"11085359", -788 => x"0b0b80d5", -789 => x"a051f3d6", -790 => x"3f91520b", -791 => x"0b80d29c", -792 => x"51f3cb3f", -793 => x"81bca408", -794 => x"9005520b", -795 => x"0b80d5bc", -796 => x"51f3bb3f", -797 => x"0b0b80d5", -798 => x"d851f3b2", -799 => x"3f0b0b80", -800 => x"d69051f3", -801 => x"a93f81bc", -802 => x"94087008", -803 => x"53570b0b", -804 => x"80d49851", -805 => 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x"00003184", +3172 => x"00003184", +3173 => x"0000318c", +3174 => x"0000318c", +3175 => x"00003194", +3176 => x"00003194", +3177 => x"0000319c", +3178 => x"0000319c", +3179 => x"000031a4", +3180 => x"000031a4", +3181 => x"000031ac", +3182 => x"000031ac", +3183 => x"000031b4", +3184 => x"000031b4", +3185 => x"000031bc", +3186 => x"000031bc", +3187 => x"000031c4", +3188 => x"000031c4", +3189 => x"000031cc", +3190 => x"000031cc", +3191 => x"000031d4", +3192 => x"000031d4", +3193 => x"000031dc", +3194 => x"000031dc", +3195 => x"000031e4", +3196 => x"000031e4", +3197 => x"000031ec", +3198 => x"000031ec", +3199 => x"000031f4", +3200 => x"000031f4", +3201 => x"000031fc", +3202 => x"000031fc", +3203 => x"00003204", +3204 => x"00003204", +3205 => x"0000320c", +3206 => x"0000320c", +3207 => x"00003214", +3208 => x"00003214", +3209 => x"0000321c", +3210 => x"0000321c", +3211 => x"00003224", +3212 => x"00003224", +3213 => x"0000322c", +3214 => x"0000322c", +3215 => x"00003234", +3216 => x"00003234", +3217 => x"0000323c", +3218 => x"0000323c", +3219 => x"00003244", +3220 => x"00003244", +3221 => x"0000324c", +3222 => x"0000324c", +3223 => x"00003254", +3224 => x"00003254", +3225 => x"0000325c", +3226 => x"0000325c", +3227 => x"00003264", +3228 => x"00003264", +3229 => x"0000326c", +3230 => x"0000326c", +3231 => x"00003274", +3232 => x"00003274", +3233 => x"0000327c", +3234 => x"0000327c", +3235 => x"00003284", +3236 => x"00003284", +3237 => x"0000328c", +3238 => x"0000328c", +3239 => x"00003294", +3240 => x"00003294", +3241 => x"0000329c", +3242 => x"0000329c", +3243 => x"000032a4", +3244 => x"000032a4", +3245 => x"000032ac", +3246 => x"000032ac", +3247 => x"000032b4", +3248 => x"000032b4", +3249 => x"000032bc", +3250 => x"000032bc", +3251 => x"000032c4", +3252 => x"000032c4", +3253 => x"000032cc", +3254 => x"000032cc", +3255 => x"000032d4", +3256 => x"000032d4", +3257 => x"000032dc", +3258 => x"000032dc", +3259 => x"000032e4", +3260 => x"000032e4", +3261 => x"000032ec", +3262 => x"000032ec", +3263 => x"000032f4", +3264 => x"000032f4", +3265 => x"000032fc", +3266 => x"000032fc", +3267 => x"00003304", +3268 => x"00003304", +3269 => x"0000330c", +3270 => x"0000330c", +3271 => x"00003314", +3272 => x"00003314", +3273 => x"0000331c", +3274 => x"0000331c", +3275 => x"00003324", +3276 => x"00003324", +3277 => x"0000332c", +3278 => x"0000332c", +3279 => x"00003334", +3280 => x"00003334", +3281 => x"0000333c", +3282 => x"0000333c", +3283 => x"00003344", +3284 => x"00003344", +3285 => x"0000334c", +3286 => x"0000334c", +3287 => x"00003354", +3288 => x"00003354", +3289 => x"0000335c", +3290 => x"0000335c", +3291 => x"00003364", +3292 => x"00003364", +3293 => x"0000336c", +3294 => x"0000336c", +3295 => x"00003374", +3296 => x"00003374", +3297 => x"0000337c", +3298 => x"0000337c", +3299 => x"00003384", +3300 => x"00003384", +3301 => x"0000338c", +3302 => x"0000338c", +3303 => x"00003394", +3304 => x"00003394", +3305 => x"0000339c", +3306 => x"0000339c", +3307 => x"000033a4", +3308 => x"000033a4", +3309 => x"000033ac", +3310 => x"000033ac", +3311 => x"000033b4", +3312 => x"000033b4", +3313 => x"000033bc", +3314 => x"000033bc", +3315 => x"000033c4", +3316 => x"000033c4", +3317 => x"000033cc", +3318 => x"000033cc", +3319 => x"000033d4", +3320 => x"000033d4", +3321 => x"000033dc", +3322 => x"000033dc", +3323 => x"000033e4", +3324 => x"000033e4", +3325 => x"000033ec", +3326 => x"000033ec", +3327 => x"000033f4", +3328 => x"000033f4", +3329 => x"000033fc", +3330 => x"000033fc", +3331 => x"00003404", +3332 => x"00003404", +3333 => x"0000340c", +3334 => x"0000340c", +3335 => x"00003414", +3336 => x"00003414", +3337 => x"0000341c", +3338 => x"0000341c", +3339 => x"00003424", +3340 => x"00003424", +3341 => x"0000342c", +3342 => x"0000342c", +3343 => x"00003434", +3344 => x"00003434", +3345 => x"0000343c", +3346 => x"0000343c", +3347 => x"00003444", +3348 => x"00003444", +3349 => x"0000344c", +3350 => x"0000344c", +3351 => x"00003454", +3352 => x"00003454", +3353 => x"0000345c", +3354 => x"0000345c", +3355 => x"00003464", +3356 => x"00003464", +3357 => x"0000346c", +3358 => x"0000346c", +3359 => x"00003474", +3360 => x"00003474", +3361 => x"0000347c", +3362 => x"0000347c", +3363 => x"00003484", +3364 => x"00003484", +3365 => x"0000348c", +3366 => x"0000348c", +3367 => x"00003494", +3368 => x"00003494", +3369 => x"0000349c", +3370 => x"0000349c", +3371 => x"000034a4", +3372 => x"000034a4", +3373 => x"000034ac", +3374 => x"000034ac", +3375 => x"000034b4", +3376 => x"000034b4", +3377 => x"000034bc", +3378 => x"000034bc", +3379 => x"000034c4", +3380 => x"000034c4", +3381 => x"000034cc", +3382 => x"000034cc", +3383 => x"000034d4", +3384 => x"000034d4", +3385 => x"000034dc", +3386 => x"000034dc", +3387 => x"000034e4", +3388 => x"000034e4", +3389 => x"000034ec", +3390 => x"000034ec", +3391 => x"000034f4", +3392 => x"000034f4", +3393 => x"000034fc", +3394 => x"000034fc", +3395 => x"00003504", +3396 => x"00003504", +3397 => x"0000350c", +3398 => x"0000350c", +3399 => x"00003514", +3400 => x"00003514", +3401 => x"0000351c", +3402 => x"0000351c", +3403 => x"00003524", +3404 => x"00003524", +3405 => x"0000352c", +3406 => x"0000352c", +3407 => x"00003534", +3408 => x"00003534", +3409 => x"0000353c", +3410 => x"0000353c", +3411 => x"00003544", +3412 => x"00003544", +3413 => x"0000354c", +3414 => x"0000354c", +3415 => x"00003554", +3416 => x"00003554", +3417 => x"0000355c", +3418 => x"0000355c", +3419 => x"00003564", +3420 => x"00003564", +3421 => x"0000356c", +3422 => x"0000356c", +3423 => x"00003580", 3424 => x"00000000", -3425 => x"00000000", -3426 => x"00000000", -3427 => x"00000000", +3425 => x"000037e8", +3426 => x"00003844", +3427 => x"000038a0", 3428 => x"00000000", 3429 => x"00000000", 3430 => x"00000000", @@ -3435,7 +3435,7 @@ 3434 => x"00000000", 3435 => x"00000000", 3436 => x"00000000", -3437 => x"00000000", +3437 => x"00003100", 3438 => x"00000000", 3439 => x"00000000", 3440 => x"00000000", @@ -3464,11 +3464,11 @@ 3463 => x"00000000", 3464 => x"00000000", 3465 => x"00000000", -3466 => x"00000000", -3467 => x"00000000", -3468 => x"00000000", -3469 => x"00000000", -3470 => x"00000000", +3466 => x"00000001", +3467 => x"330eabcd", +3468 => x"1234e66d", +3469 => x"deec0005", +3470 => x"000b0000", 3471 => x"00000000", 3472 => x"00000000", 3473 => x"00000000", @@ -3500,8 +3500,153 @@ 3499 => x"00000000", 3500 => x"00000000", 3501 => x"00000000", -3502 => x"00002dc0", -3503 => x"ffffffff", +3502 => x"00000000", +3503 => x"00000000", 3504 => x"00000000", -3505 => x"ffffffff", +3505 => x"00000000", 3506 => x"00000000", +3507 => x"00000000", +3508 => x"00000000", +3509 => x"00000000", +3510 => x"00000000", +3511 => x"00000000", +3512 => x"00000000", +3513 => x"00000000", +3514 => x"00000000", +3515 => x"00000000", +3516 => x"00000000", +3517 => x"00000000", +3518 => x"00000000", +3519 => x"00000000", +3520 => x"00000000", +3521 => x"00000000", +3522 => x"00000000", +3523 => x"00000000", +3524 => x"00000000", +3525 => x"00000000", +3526 => x"00000000", +3527 => x"00000000", +3528 => x"00000000", +3529 => x"00000000", +3530 => x"00000000", +3531 => x"00000000", +3532 => x"00000000", +3533 => x"00000000", +3534 => x"00000000", +3535 => x"00000000", +3536 => x"00000000", +3537 => x"00000000", +3538 => x"00000000", +3539 => x"00000000", +3540 => x"00000000", +3541 => x"00000000", +3542 => x"00000000", +3543 => x"00000000", +3544 => x"00000000", +3545 => x"00000000", +3546 => x"00000000", +3547 => x"00000000", +3548 => x"00000000", +3549 => x"00000000", +3550 => x"00000000", +3551 => x"00000000", +3552 => x"00000000", +3553 => x"00000000", +3554 => x"00000000", +3555 => x"00000000", +3556 => x"00000000", +3557 => x"00000000", +3558 => x"00000000", +3559 => x"00000000", +3560 => x"00000000", +3561 => x"00000000", +3562 => x"00000000", +3563 => x"00000000", +3564 => x"00000000", +3565 => x"00000000", +3566 => x"00000000", +3567 => x"00000000", +3568 => x"00000000", +3569 => x"00000000", +3570 => x"00000000", +3571 => x"00000000", +3572 => x"00000000", +3573 => x"00000000", +3574 => x"00000000", +3575 => x"00000000", +3576 => x"00000000", +3577 => x"00000000", +3578 => x"00000000", +3579 => x"00000000", +3580 => x"00000000", +3581 => x"00000000", +3582 => x"00000000", +3583 => x"00000000", +3584 => x"00000000", +3585 => x"00000000", +3586 => x"00000000", +3587 => x"00000000", +3588 => x"00000000", +3589 => x"00000000", +3590 => x"00000000", +3591 => x"00000000", +3592 => x"00000000", +3593 => x"00000000", +3594 => x"00000000", +3595 => x"00000000", +3596 => x"00000000", +3597 => x"00000000", +3598 => x"00000000", +3599 => x"00000000", +3600 => x"00000000", +3601 => x"00000000", +3602 => x"00000000", +3603 => x"00000000", +3604 => x"00000000", +3605 => x"00000000", +3606 => x"00000000", +3607 => x"00000000", +3608 => x"00000000", +3609 => x"00000000", +3610 => x"00000000", +3611 => x"00000000", +3612 => x"00000000", +3613 => x"00000000", +3614 => x"00000000", +3615 => x"00000000", +3616 => x"00000000", +3617 => x"00000000", +3618 => x"00000000", +3619 => x"00000000", +3620 => x"00000000", +3621 => x"00000000", +3622 => x"00000000", +3623 => x"00000000", +3624 => x"00000000", +3625 => x"00000000", +3626 => x"00000000", +3627 => x"00000000", +3628 => x"00000000", +3629 => x"00000000", +3630 => x"00000000", +3631 => x"00000000", +3632 => x"00000000", +3633 => x"00000000", +3634 => x"00000000", +3635 => x"00000000", +3636 => x"00000000", +3637 => x"00000000", +3638 => x"00000000", +3639 => x"00000000", +3640 => x"00000000", +3641 => x"00000000", +3642 => x"00000000", +3643 => x"00000000", +3644 => x"00000000", +3645 => x"00000000", +3646 => x"00000000", +3647 => x"00003104", +3648 => x"ffffffff", +3649 => x"00000000", +3650 => x"ffffffff", +3651 => x"00000000", diff --git a/zpu/hdl/zpu4/test/hello/build.sh b/zpu/hdl/zpu4/test/hello/build.sh index 0d81138..dd87410 100644 --- a/zpu/hdl/zpu4/test/hello/build.sh +++ b/zpu/hdl/zpu4/test/hello/build.sh @@ -1,3 +1,4 @@ -zpu-elf-gcc -O3 -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-gcc -O3 -phi `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g zpu-elf-objdump --disassemble-all >hello.dis hello.elf zpu-elf-objcopy -O binary hello.elf hello.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.ram diff --git a/zpu/hdl/zpu4/test/hello/hello.bin b/zpu/hdl/zpu4/test/hello/hello.bin index fe17308..7c37759 100644 Binary files a/zpu/hdl/zpu4/test/hello/hello.bin and b/zpu/hdl/zpu4/test/hello/hello.bin differ diff --git a/zpu/hdl/zpu4/test/hello/hello.c b/zpu/hdl/zpu4/test/hello/hello.c index ea3dbb8..609c163 100644 --- a/zpu/hdl/zpu4/test/hello/hello.c +++ b/zpu/hdl/zpu4/test/hello/hello.c @@ -1,10 +1,6 @@ /* - -zpu-elf-gcc -abel `pwd`/hello.c -o hello.elf -Wl,--relax -Wl,--gc-sections -g -zpu-elf-objdump --disassemble-all >hello.dis hello.elf -zpu-elf-objcopy -O binary hello.elf hello.bin - - * */ + * Small hello world example, does not use printf() + */ #include int j; diff --git a/zpu/hdl/zpu4/test/hello/hello.elf b/zpu/hdl/zpu4/test/hello/hello.elf index 999b9a3..73d28e7 100644 Binary files a/zpu/hdl/zpu4/test/hello/hello.elf and b/zpu/hdl/zpu4/test/hello/hello.elf differ diff --git a/zpu/hdl/zpu4/test/hello/hello.ram b/zpu/hdl/zpu4/test/hello/hello.ram index f310151..175d3a8 100644 --- a/zpu/hdl/zpu4/test/hello/hello.ram +++ b/zpu/hdl/zpu4/test/hello/hello.ram @@ -1,14 +1,14 @@ 0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80d3900c", +1 => x"82700b0b", +2 => x"80cfd80c", 3 => x"3a0b0b80", -4 => x"c8b20400", +4 => x"c6d00400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"80c8fb2d", +10 => x"80c7972d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -159,8 +159,8 @@ 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80d2", -162 => x"fc738306", +161 => x"0b0b80cf", +162 => x"c4738306", 163 => x"10100508", 164 => x"060b0b0b", 165 => x"88aa0400", @@ -168,16 +168,16 @@ 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0b8d", -171 => x"872d5050", +170 => x"0b0b0b8b", +171 => x"9f2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0b8d", -179 => x"cb2d5050", +178 => x"0b0b0b8b", +179 => x"e32d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -207,7 +207,7 @@ 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80d38c0c", +209 => x"80cfd40c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -254,8 +254,8 @@ 253 => x"00000000", 254 => x"00000000", 255 => x"00000000", -256 => x"83d93f80", -257 => x"ca953f04", +256 => x"82c53f80", +257 => x"c6d93f04", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -278,2394 +278,2394 @@ 277 => x"0a100a53", 278 => x"72ed3851", 279 => x"51535104", -280 => x"ff3d0d0b", -281 => x"0b80e2f8", -282 => x"08528412", -283 => x"08708106", -284 => x"515170f6", -285 => x"38710881", -286 => x"ff06800c", -287 => x"833d0d04", -288 => x"ff3d0d0b", -289 => x"0b80e2f8", -290 => x"08528412", -291 => x"08700a10", -292 => x"0a708106", -293 => x"51515170", -294 => x"f1387372", -295 => x"0c833d0d", -296 => x"0480d38c", -297 => x"08802ea8", -298 => x"38838080", -299 => x"0b0b0b80", -300 => x"e2f80c82", -301 => x"a0800b0b", -302 => x"0b80e2fc", -303 => x"0c829080", -304 => x"0b80e38c", -305 => x"0c0b0b80", -306 => x"e3800b80", -307 => x"e3900c04", -308 => x"f8808080", -309 => x"a40b0b0b", -310 => x"80e2f80c", -311 => x"f8808082", -312 => x"800b0b0b", -313 => x"80e2fc0c", -314 => x"f8808084", -315 => x"800b80e3", -316 => x"8c0cf880", -317 => x"8080940b", -318 => x"80e3900c", -319 => x"f8808080", -320 => x"9c0b80e3", -321 => x"880cf880", -322 => x"8080a00b", -323 => x"80e3940c", -324 => x"04f23d0d", -325 => x"600b0b80", -326 => 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x"863d0d04", +2477 => x"80cfe408", +2478 => x"800c04f7", +2479 => x"3d0d7b80", +2480 => x"cfe40882", +2481 => x"c811085a", +2482 => x"545a7780", +2483 => x"2e80da38", +2484 => x"81881884", +2485 => x"1908ff05", +2486 => x"81712b59", +2487 => x"55598074", +2488 => x"2480ea38", +2489 => x"807424b5", +2490 => x"3873822b", +2491 => x"78118805", +2492 => x"56568180", +2493 => x"19087706", +2494 => x"5372802e", +2495 => x"b6387816", +2496 => x"70085353", +2497 => x"79517408", +2498 => x"53722dff", +2499 => x"14fc17fc", +2500 => x"1779812c", +2501 => x"5a575754", +2502 => x"738025d6", +2503 => x"38770858", +2504 => x"77ffad38", +2505 => x"80cfe408", +2506 => x"53bc1308", +2507 => x"a5387951", +2508 => x"f8e23f74", +2509 => x"0853722d", +2510 => x"ff14fc17", +2511 => x"fc177981", +2512 => x"2c5a5757", +2513 => x"54738025", +2514 => x"ffa838d1", +2515 => x"398057ff", +2516 => x"93397251", +2517 => x"bc130854", +2518 => x"732d7951", +2519 => x"f8b63f70", +2520 => x"7080dfb0", +2521 => x"0bfc0570", +2522 => x"08525270", +2523 => x"ff2e9138", +2524 => x"702dfc12", +2525 => x"70085252", +2526 => x"70ff2e09", +2527 => x"8106f138", +2528 => x"50500404", +2529 => x"ffbb8c3f", +2530 => x"04000000", +2531 => x"00000040", +2532 => x"48656c6c", +2533 => x"6f20776f", +2534 => x"726c6420", +2535 => x"310a0000", +2536 => x"48656c6c", +2537 => x"6f20776f", +2538 => x"726c6420", +2539 => x"320a0000", +2540 => x"0a000000", +2541 => x"43000000", +2542 => x"64756d6d", +2543 => x"792e6578", +2544 => x"65000000", +2545 => x"00ffffff", +2546 => x"ff00ffff", +2547 => x"ffff00ff", +2548 => x"ffffff00", +2549 => x"00000000", +2550 => x"00000000", +2551 => x"00000000", +2552 => x"00002fb8", +2553 => x"000027e8", +2554 => x"00000000", +2555 => x"00002a50", +2556 => x"00002aac", +2557 => x"00002b08", +2558 => x"00000000", +2559 => x"00000000", +2560 => x"00000000", +2561 => x"00000000", +2562 => x"00000000", +2563 => x"00000000", +2564 => x"00000000", +2565 => x"00000000", +2566 => x"00000000", +2567 => x"000027b4", +2568 => x"00000000", +2569 => x"00000000", +2570 => x"00000000", +2571 => x"00000000", +2572 => x"00000000", +2573 => x"00000000", +2574 => x"00000000", +2575 => x"00000000", +2576 => x"00000000", +2577 => x"00000000", +2578 => x"00000000", +2579 => x"00000000", +2580 => x"00000000", +2581 => x"00000000", +2582 => x"00000000", +2583 => x"00000000", +2584 => x"00000000", +2585 => x"00000000", +2586 => x"00000000", +2587 => x"00000000", +2588 => x"00000000", +2589 => x"00000000", +2590 => x"00000000", +2591 => x"00000000", +2592 => x"00000000", +2593 => x"00000000", +2594 => x"00000000", +2595 => x"00000000", +2596 => x"00000001", +2597 => x"330eabcd", +2598 => x"1234e66d", +2599 => x"deec0005", +2600 => x"000b0000", +2601 => x"00000000", +2602 => x"00000000", +2603 => x"00000000", +2604 => x"00000000", +2605 => x"00000000", +2606 => x"00000000", +2607 => x"00000000", +2608 => x"00000000", +2609 => x"00000000", +2610 => x"00000000", +2611 => x"00000000", +2612 => x"00000000", +2613 => x"00000000", +2614 => x"00000000", +2615 => x"00000000", +2616 => x"00000000", +2617 => x"00000000", +2618 => x"00000000", +2619 => x"00000000", +2620 => x"00000000", +2621 => x"00000000", +2622 => x"00000000", +2623 => x"00000000", +2624 => x"00000000", +2625 => x"00000000", +2626 => x"00000000", +2627 => x"00000000", +2628 => x"00000000", +2629 => x"00000000", +2630 => x"00000000", +2631 => x"00000000", +2632 => x"00000000", +2633 => x"00000000", +2634 => x"00000000", +2635 => x"00000000", +2636 => x"00000000", +2637 => x"00000000", +2638 => x"00000000", +2639 => x"00000000", +2640 => x"00000000", +2641 => x"00000000", +2642 => x"00000000", +2643 => x"00000000", +2644 => x"00000000", +2645 => x"00000000", +2646 => x"00000000", +2647 => x"00000000", +2648 => x"00000000", +2649 => x"00000000", +2650 => x"00000000", +2651 => x"00000000", +2652 => x"00000000", +2653 => x"00000000", +2654 => x"00000000", +2655 => x"00000000", +2656 => x"00000000", +2657 => x"00000000", +2658 => x"00000000", 2659 => x"00000000", 2660 => x"00000000", 2661 => x"00000000", -2662 => x"00003170", -2663 => x"000029a0", +2662 => x"00000000", +2663 => x"00000000", 2664 => x"00000000", -2665 => x"00002c08", -2666 => x"00002c64", -2667 => x"00002cc0", +2665 => x"00000000", +2666 => x"00000000", +2667 => x"00000000", 2668 => x"00000000", 2669 => x"00000000", 2670 => x"00000000", @@ -2675,7 +2675,7 @@ 2674 => x"00000000", 2675 => x"00000000", 2676 => x"00000000", -2677 => x"0000296c", +2677 => x"00000000", 2678 => x"00000000", 2679 => x"00000000", 2680 => x"00000000", @@ -2704,11 +2704,11 @@ 2703 => x"00000000", 2704 => x"00000000", 2705 => x"00000000", -2706 => x"00000001", -2707 => x"330eabcd", -2708 => x"1234e66d", -2709 => x"deec0005", -2710 => x"000b0000", +2706 => x"00000000", +2707 => x"00000000", +2708 => x"00000000", +2709 => x"00000000", +2710 => x"00000000", 2711 => x"00000000", 2712 => x"00000000", 2713 => x"00000000", @@ -2787,121 +2787,121 @@ 2786 => x"00000000", 2787 => x"00000000", 2788 => x"00000000", -2789 => x"00000000", +2789 => x"ffffffff", 2790 => x"00000000", -2791 => x"00000000", +2791 => x"00020000", 2792 => x"00000000", 2793 => x"00000000", -2794 => x"00000000", -2795 => x"00000000", -2796 => x"00000000", -2797 => x"00000000", -2798 => x"00000000", -2799 => x"00000000", -2800 => x"00000000", -2801 => x"00000000", -2802 => x"00000000", -2803 => x"00000000", -2804 => x"00000000", -2805 => x"00000000", -2806 => x"00000000", -2807 => x"00000000", -2808 => x"00000000", -2809 => x"00000000", -2810 => x"00000000", -2811 => x"00000000", -2812 => x"00000000", -2813 => x"00000000", -2814 => x"00000000", -2815 => x"00000000", -2816 => x"00000000", -2817 => x"00000000", -2818 => x"00000000", -2819 => x"00000000", -2820 => x"00000000", -2821 => x"00000000", -2822 => x"00000000", -2823 => x"00000000", -2824 => x"00000000", -2825 => x"00000000", -2826 => x"00000000", -2827 => x"00000000", -2828 => x"00000000", -2829 => x"00000000", -2830 => x"00000000", -2831 => x"00000000", -2832 => x"00000000", -2833 => x"00000000", -2834 => x"00000000", -2835 => x"00000000", -2836 => x"00000000", -2837 => x"00000000", -2838 => x"00000000", -2839 => x"00000000", -2840 => x"00000000", -2841 => x"00000000", -2842 => x"00000000", -2843 => x"00000000", -2844 => x"00000000", -2845 => x"00000000", -2846 => x"00000000", -2847 => x"00000000", -2848 => x"00000000", -2849 => x"00000000", -2850 => x"00000000", -2851 => x"00000000", -2852 => x"00000000", -2853 => x"00000000", -2854 => x"00000000", -2855 => x"00000000", -2856 => x"00000000", -2857 => x"00000000", -2858 => x"00000000", -2859 => x"00000000", -2860 => x"00000000", -2861 => x"00000000", -2862 => x"00000000", -2863 => x"00000000", -2864 => x"00000000", -2865 => x"00000000", -2866 => x"00000000", -2867 => x"00000000", -2868 => x"00000000", -2869 => x"00000000", -2870 => x"00000000", -2871 => x"00000000", -2872 => x"00000000", -2873 => x"00000000", -2874 => x"00000000", -2875 => x"00000000", -2876 => x"00000000", -2877 => x"00000000", -2878 => x"00000000", -2879 => x"00000000", -2880 => x"00000000", -2881 => x"00000000", -2882 => x"00000000", -2883 => x"00000000", -2884 => x"00000000", -2885 => x"00000000", -2886 => x"00000000", -2887 => x"00000000", -2888 => x"00000000", -2889 => x"00000000", -2890 => x"00000000", -2891 => x"00000000", -2892 => x"00000000", -2893 => x"00000000", -2894 => x"00000000", -2895 => x"00000000", -2896 => x"00000000", -2897 => x"00000000", -2898 => x"00000000", -2899 => x"ffffffff", -2900 => x"00000000", -2901 => x"00020000", -2902 => x"00000000", -2903 => x"00000000", +2794 => x"00002ba0", +2795 => x"00002ba0", +2796 => x"00002ba8", +2797 => x"00002ba8", +2798 => x"00002bb0", +2799 => x"00002bb0", +2800 => x"00002bb8", +2801 => x"00002bb8", +2802 => x"00002bc0", +2803 => x"00002bc0", +2804 => x"00002bc8", +2805 => x"00002bc8", +2806 => x"00002bd0", +2807 => x"00002bd0", +2808 => x"00002bd8", +2809 => x"00002bd8", +2810 => x"00002be0", +2811 => x"00002be0", +2812 => x"00002be8", +2813 => x"00002be8", +2814 => x"00002bf0", +2815 => x"00002bf0", +2816 => x"00002bf8", +2817 => x"00002bf8", +2818 => x"00002c00", +2819 => x"00002c00", +2820 => x"00002c08", +2821 => x"00002c08", +2822 => x"00002c10", +2823 => x"00002c10", +2824 => x"00002c18", +2825 => x"00002c18", +2826 => x"00002c20", +2827 => x"00002c20", +2828 => x"00002c28", +2829 => x"00002c28", +2830 => x"00002c30", +2831 => x"00002c30", +2832 => x"00002c38", +2833 => x"00002c38", +2834 => x"00002c40", +2835 => x"00002c40", +2836 => x"00002c48", +2837 => x"00002c48", +2838 => x"00002c50", +2839 => x"00002c50", +2840 => x"00002c58", +2841 => x"00002c58", +2842 => x"00002c60", +2843 => x"00002c60", +2844 => x"00002c68", +2845 => x"00002c68", +2846 => x"00002c70", +2847 => x"00002c70", +2848 => x"00002c78", +2849 => x"00002c78", +2850 => x"00002c80", +2851 => x"00002c80", +2852 => x"00002c88", +2853 => x"00002c88", +2854 => x"00002c90", +2855 => x"00002c90", +2856 => x"00002c98", +2857 => x"00002c98", +2858 => x"00002ca0", +2859 => x"00002ca0", +2860 => x"00002ca8", +2861 => x"00002ca8", +2862 => x"00002cb0", +2863 => x"00002cb0", +2864 => x"00002cb8", +2865 => x"00002cb8", +2866 => x"00002cc0", +2867 => x"00002cc0", +2868 => x"00002cc8", +2869 => x"00002cc8", +2870 => x"00002cd0", +2871 => x"00002cd0", +2872 => x"00002cd8", +2873 => x"00002cd8", +2874 => x"00002ce0", +2875 => x"00002ce0", +2876 => x"00002ce8", +2877 => x"00002ce8", +2878 => x"00002cf0", +2879 => x"00002cf0", +2880 => x"00002cf8", +2881 => x"00002cf8", +2882 => x"00002d00", +2883 => x"00002d00", +2884 => x"00002d08", +2885 => x"00002d08", +2886 => x"00002d10", +2887 => x"00002d10", +2888 => x"00002d18", +2889 => x"00002d18", +2890 => x"00002d20", +2891 => x"00002d20", +2892 => x"00002d28", +2893 => x"00002d28", +2894 => x"00002d30", +2895 => x"00002d30", +2896 => x"00002d38", +2897 => x"00002d38", +2898 => x"00002d40", +2899 => x"00002d40", +2900 => x"00002d48", +2901 => x"00002d48", +2902 => x"00002d50", +2903 => x"00002d50", 2904 => x"00002d58", 2905 => x"00002d58", 2906 => x"00002d60", @@ -3048,118 +3048,8 @@ 3047 => x"00002f90", 3048 => x"00002f98", 3049 => x"00002f98", -3050 => x"00002fa0", -3051 => x"00002fa0", -3052 => x"00002fa8", -3053 => x"00002fa8", -3054 => x"00002fb0", -3055 => x"00002fb0", -3056 => x"00002fb8", -3057 => x"00002fb8", -3058 => x"00002fc0", -3059 => x"00002fc0", -3060 => x"00002fc8", -3061 => x"00002fc8", -3062 => x"00002fd0", -3063 => x"00002fd0", -3064 => x"00002fd8", -3065 => x"00002fd8", -3066 => x"00002fe0", -3067 => x"00002fe0", -3068 => x"00002fe8", -3069 => x"00002fe8", -3070 => x"00002ff0", -3071 => x"00002ff0", -3072 => x"00002ff8", -3073 => x"00002ff8", -3074 => x"00003000", -3075 => x"00003000", -3076 => x"00003008", -3077 => x"00003008", -3078 => x"00003010", -3079 => x"00003010", -3080 => x"00003018", -3081 => x"00003018", -3082 => x"00003020", -3083 => x"00003020", -3084 => x"00003028", -3085 => x"00003028", -3086 => x"00003030", -3087 => x"00003030", -3088 => x"00003038", -3089 => x"00003038", -3090 => x"00003040", -3091 => x"00003040", -3092 => x"00003048", -3093 => x"00003048", -3094 => x"00003050", -3095 => x"00003050", -3096 => x"00003058", -3097 => x"00003058", -3098 => x"00003060", -3099 => x"00003060", -3100 => x"00003068", -3101 => x"00003068", -3102 => x"00003070", -3103 => x"00003070", -3104 => x"00003078", -3105 => x"00003078", -3106 => x"00003080", -3107 => x"00003080", -3108 => x"00003088", -3109 => x"00003088", -3110 => x"00003090", -3111 => x"00003090", -3112 => x"00003098", -3113 => x"00003098", -3114 => x"000030a0", -3115 => x"000030a0", -3116 => x"000030a8", -3117 => x"000030a8", -3118 => x"000030b0", -3119 => x"000030b0", -3120 => x"000030b8", -3121 => x"000030b8", -3122 => x"000030c0", -3123 => x"000030c0", -3124 => x"000030c8", -3125 => x"000030c8", -3126 => x"000030d0", -3127 => x"000030d0", -3128 => x"000030d8", -3129 => x"000030d8", -3130 => x"000030e0", -3131 => x"000030e0", -3132 => x"000030e8", -3133 => x"000030e8", -3134 => x"000030f0", -3135 => x"000030f0", -3136 => x"000030f8", -3137 => x"000030f8", -3138 => x"00003100", -3139 => x"00003100", -3140 => x"00003108", -3141 => x"00003108", -3142 => x"00003110", -3143 => x"00003110", -3144 => x"00003118", -3145 => x"00003118", -3146 => x"00003120", -3147 => x"00003120", -3148 => x"00003128", -3149 => x"00003128", -3150 => x"00003130", -3151 => x"00003130", -3152 => x"00003138", -3153 => x"00003138", -3154 => x"00003140", -3155 => x"00003140", -3156 => x"00003148", -3157 => x"00003148", -3158 => x"00003150", -3159 => x"00003150", -3160 => x"00002970", -3161 => x"ffffffff", -3162 => x"00000000", -3163 => x"ffffffff", -3164 => x"00000000", +3050 => x"000027b8", +3051 => x"ffffffff", +3052 => x"00000000", +3053 => x"ffffffff", +3054 => x"00000000", -- cgit v1.1 From e5627082149dbce408555bd3a128fd5d128880d2 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 21 Feb 2008 19:17:03 +0000 Subject: * zpu/zpu/sw/index.html. Changed it a bit to make installation easier. --- zpu/hdl/zpu4/src/dmipstrace.do | 5 + zpu/hdl/zpu4/src/dmipstraceintstack.do | 25 - zpu/hdl/zpu4/src/dram_dmips.vhd | 6374 +++++++++++++++---------------- zpu/hdl/zpu4/src/fastdmips.do | 19 - zpu/hdl/zpu4/src/fastdmipsintstack.do | 19 - zpu/hdl/zpu4/src/fastdmipssmall.do | 21 - zpu/hdl/zpu4/src/fasthello.do | 19 - zpu/hdl/zpu4/src/fastsimzpu.do | 19 - zpu/hdl/zpu4/src/log.txt | 347 +- zpu/hdl/zpu4/src/zpu_config_fastsim.vhd | 15 - zpu/hdl/zpu4/test/dmips/build.sh | 2 +- zpu/hdl/zpu4/test/dmips/dmips.bin | Bin 14612 -> 13028 bytes zpu/hdl/zpu4/test/dmips/dmips.elf | Bin 89778 -> 82460 bytes zpu/hdl/zpu4/test/dmips/dmips.ram | 6370 +++++++++++++++--------------- 14 files changed, 6082 insertions(+), 7153 deletions(-) delete mode 100644 zpu/hdl/zpu4/src/dmipstraceintstack.do delete mode 100644 zpu/hdl/zpu4/src/fastdmips.do delete mode 100644 zpu/hdl/zpu4/src/fastdmipsintstack.do delete mode 100644 zpu/hdl/zpu4/src/fastdmipssmall.do delete mode 100644 zpu/hdl/zpu4/src/fasthello.do delete mode 100644 zpu/hdl/zpu4/src/fastsimzpu.do delete mode 100644 zpu/hdl/zpu4/src/zpu_config_fastsim.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/dmipstrace.do b/zpu/hdl/zpu4/src/dmipstrace.do index 8d5f430..64cf8fd 100644 --- a/zpu/hdl/zpu4/src/dmipstrace.do +++ b/zpu/hdl/zpu4/src/dmipstrace.do @@ -1,3 +1,8 @@ +# Xilinx WebPack modelsim script +# +# cd C:/workspace/zpu/zpu/hdl/zpu4/src +# do dmipstrace.do + set BreakOnAssertion 1 vlib work diff --git a/zpu/hdl/zpu4/src/dmipstraceintstack.do b/zpu/hdl/zpu4/src/dmipstraceintstack.do deleted file mode 100644 index b2addb4..0000000 --- a/zpu/hdl/zpu4/src/dmipstraceintstack.do +++ /dev/null @@ -1,25 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_intstack.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -add wave -recursive fpga_top/zpu/* -#--add wave -recursive fpga_top/ioMap/* -#add wave -recursive fpga_top/* -view structure - - -# run ZPU -run 5 ms diff --git a/zpu/hdl/zpu4/src/dram_dmips.vhd b/zpu/hdl/zpu4/src/dram_dmips.vhd index e63a27a..a289fd7 100644 --- a/zpu/hdl/zpu4/src/dram_dmips.vhd +++ b/zpu/hdl/zpu4/src/dram_dmips.vhd @@ -22,21 +22,21 @@ end dram; architecture dram_arch of dram is -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( 0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80e2a40c", +1 => x"82700b0b", +2 => x"80d5f40c", 3 => x"3a0b0b80", -4 => x"c6fc0400", +4 => x"c4fb0400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"80c7c32d", +10 => x"80c5c22d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -99,7 +99,7 @@ shared variable ram : ram_type := 70 => x"00000000", 71 => x"00000000", 72 => x"0b0b0b88", -73 => x"c4040000", +73 => x"c3040000", 74 => x"00000000", 75 => x"00000000", 76 => x"00000000", @@ -116,7 +116,7 @@ shared variable ram : ram_type := 87 => x"00000000", 88 => x"72729f06", 89 => x"0981050b", -90 => x"0b0b88a7", +90 => x"0b0b88a6", 91 => x"05040000", 92 => x"00000000", 93 => x"00000000", @@ -187,25 +187,25 @@ shared variable ram : ram_type := 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80e2", -162 => x"90738306", +161 => x"0b0b80d5", +162 => x"e0738306", 163 => x"10100508", 164 => x"060b0b0b", -165 => x"88aa0400", +165 => x"88a90400", 166 => x"00000000", 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0baf", -171 => x"ac2d5050", +170 => x"0b0b0bad", +171 => x"aa2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0baf", -179 => x"f02d5050", +178 => x"0b0b0bad", +179 => x"ee2d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -235,7 +235,7 @@ shared variable ram : ram_type := 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80e2a00c", +209 => x"80d5f00c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -282,8 +282,8 @@ shared variable ram : ram_type := 253 => x"00000000", 254 => x"00000000", 255 => x"00000000", -256 => x"83d93f80", -257 => x"cbcf3f04", +256 => x"82fd3fbf", +257 => x"a03f0410", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -291,2890 +291,2890 @@ shared variable ram : ram_type := 262 => x"10101010", 263 => x"10101010", 264 => x"10101010", -265 => x"10101053", -266 => x"51047381", -267 => x"ff067383", -268 => x"06098105", -269 => x"83051010", -270 => x"102b0772", -271 => x"fc060c51", -272 => x"51043c04", -273 => x"72728072", -274 => x"8106ff05", -275 => x"09720605", -276 => x"71105272", -277 => x"0a100a53", -278 => x"72ed3851", -279 => x"51535104", -280 => x"ff3d0d0b", -281 => x"0b80f294", -282 => x"08528412", -283 => x"08708106", -284 => x"515170f6", -285 => x"38710881", -286 => x"ff06800c", +265 => x"10105351", +266 => x"047381ff", +267 => x"06738306", +268 => x"09810583", +269 => x"05101010", +270 => x"2b0772fc", +271 => x"060c5151", +272 => x"043c0472", +273 => x"72807281", +274 => x"06ff0509", +275 => x"72060571", +276 => x"1052720a", +277 => x"100a5372", +278 => x"ed385151", +279 => x"535104ff", +280 => x"3d0d0b0b", +281 => x"80e5e408", +282 => x"52710870", +283 => x"882a8132", +284 => x"70810651", +285 => x"515170f1", +286 => x"3873720c", 287 => x"833d0d04", -288 => x"ff3d0d0b", -289 => x"0b80f294", -290 => x"08528412", -291 => x"08700a10", -292 => x"0a708106", -293 => x"51515170", -294 => x"f1387372", -295 => x"0c833d0d", -296 => x"0480e2a0", -297 => x"08802ea8", -298 => x"38838080", -299 => x"0b0b0b80", -300 => x"f2940c82", -301 => x"a0800b0b", -302 => x"0b80f298", -303 => x"0c829080", -304 => x"0b80f2a8", -305 => x"0c0b0b80", -306 => x"f29c0b80", -307 => x"f2ac0c04", -308 => x"f8808080", -309 => x"a40b0b0b", -310 => x"80f2940c", -311 => x"f8808082", -312 => x"800b0b0b", -313 => x"80f2980c", -314 => x"f8808084", -315 => x"800b80f2", -316 => x"a80cf880", -317 => x"8080940b", -318 => x"80f2ac0c", -319 => x"f8808080", -320 => x"9c0b80f2", -321 => x"a40cf880", -322 => x"8080a00b", -323 => x"80f2b00c", -324 => x"04f23d0d", -325 => x"600b0b80", -326 => x"f2980856", -327 => x"5d82750c", -328 => x"8059805a", -329 => x"800b8f3d", -330 => x"71101017", -331 => x"70085957", -332 => x"5d5b8076", -333 => x"81ff067c", -334 => x"832b5658", -335 => x"5276537b", -336 => x"519af33f", -337 => x"7d7f7a72", -338 => x"077c7207", -339 => x"71716081", -340 => x"05415f5d", -341 => x"5b595755", -342 => x"7a8724bb", -343 => x"380b0b80", -344 => x"f298087b", -345 => x"10101170", -346 => x"08585155", -347 => x"807681ff", -348 => x"067c832b", -349 => x"56585276", -350 => x"537b519a", -351 => x"b93f7d7f", -352 => x"7a72077c", -353 => x"72077171", -354 => x"60810541", -355 => x"5f5d5b59", -356 => x"5755877b", -357 => x"25c73876", -358 => x"7d0c7784", -359 => x"1e0c7c80", -360 => x"0c903d0d", -361 => x"04ff3d0d", -362 => x"80f2a033", -363 => x"5170a738", -364 => x"80e2ac08", -365 => x"70085252", -366 => x"70802e94", -367 => x"38841280", -368 => x"e2ac0c70", -369 => x"2d80e2ac", -370 => x"08700852", -371 => x"5270ee38", -372 => x"810b80f2", -373 => x"a034833d", -374 => x"0d040480", -375 => x"3d0d0b0b", -376 => x"80f29008", -377 => x"802e8e38", -378 => x"0b0b0b0b", -379 => x"800b802e", -380 => x"09810685", -381 => x"38823d0d", -382 => x"040b0b80", -383 => x"f290510b", -384 => x"0b0bf3fc", -385 => x"3f823d0d", -386 => x"0404ff3d", -387 => x"0d028f05", -388 => x"3352718a", -389 => x"2e8a3871", -390 => x"51fce53f", -391 => x"833d0d04", -392 => x"8d51fcdc", -393 => x"3f7151fc", -394 => x"d73f833d", -395 => x"0d04ce3d", -396 => x"0db53d70", -397 => x"70840552", -398 => x"088c8a5c", -399 => x"56a53d5e", -400 => x"5c807570", -401 => x"81055733", -402 => x"765b5558", -403 => x"73782e80", -404 => x"c1388e3d", -405 => x"5b73a52e", -406 => x"09810680", -407 => x"c5387870", -408 => x"81055a33", -409 => x"547380e4", -410 => x"2e81b638", -411 => x"7380e424", -412 => x"80c63873", -413 => x"80e32ea1", -414 => x"388052a5", -415 => x"51792d80", -416 => x"52735179", -417 => x"2d821858", -418 => x"78708105", -419 => x"5a335473", -420 => x"c4387780", -421 => x"0cb43d0d", -422 => x"047b841d", -423 => x"83123356", -424 => x"5d578052", -425 => x"7351792d", -426 => x"81187970", -427 => x"81055b33", -428 => x"555873ff", -429 => x"a038db39", -430 => x"7380f32e", -431 => x"098106ff", -432 => x"b8387b84", -433 => x"1d710859", -434 => x"5d568077", -435 => x"33555673", -436 => x"762e8d38", -437 => x"81167018", -438 => x"70335755", -439 => x"5674f538", -440 => x"ff165580", -441 => x"7625ffa0", -442 => x"38767081", -443 => x"05583354", -444 => x"80527351", -445 => x"792d8118", -446 => x"75ff1757", -447 => x"57588076", -448 => x"25ff8538", -449 => x"76708105", -450 => x"58335480", -451 => x"52735179", -452 => x"2d811875", -453 => x"ff175757", -454 => x"58758024", -455 => x"cc38fee8", -456 => x"397b841d", -457 => x"71087071", -458 => x"9f2c5953", -459 => x"595d5680", -460 => x"75248195", -461 => x"38757d7c", -462 => x"58565480", -463 => x"5773772e", -464 => x"098106b6", -465 => x"38b07b34", -466 => x"02b50556", -467 => x"7a762e97", -468 => x"38ff1656", -469 => x"75337570", -470 => x"81055734", -471 => x"8117577a", -472 => x"762e0981", -473 => x"06eb3880", -474 => x"7534767d", -475 => x"ff125758", -476 => x"56758024", -477 => x"fef338fe", -478 => x"8f398a52", -479 => x"7351a0f0", -480 => x"3f80080b", -481 => x"0b80d484", -482 => x"05337670", -483 => x"81055834", -484 => x"8a527351", -485 => x"a0963f80", -486 => x"08548008", -487 => x"802effac", -488 => x"388a5273", -489 => x"51a0c93f", -490 => x"80080b0b", -491 => x"80d48405", -492 => x"33767081", -493 => x"0558348a", -494 => x"5273519f", -495 => x"ef3f8008", -496 => x"548008ff", -497 => x"b538ff84", -498 => x"39745276", -499 => x"53b43dff", -500 => x"b8055195", -501 => x"b63fa33d", -502 => x"0856fed9", -503 => x"39803d0d", -504 => x"80c10b81", -505 => x"c0f43480", -506 => x"0b81c2d0", -507 => x"0c70800c", -508 => x"823d0d04", -509 => x"ff3d0d80", -510 => x"0b81c0f4", -511 => x"33525270", -512 => x"80c12e99", -513 => x"387181c2", -514 => x"d0080781", -515 => x"c2d00c80", -516 => x"c20b81c0", -517 => x"f8347080", -518 => x"0c833d0d", -519 => x"04810b81", -520 => x"c2d00807", -521 => x"81c2d00c", -522 => x"80c20b81", -523 => x"c0f83470", -524 => x"800c833d", -525 => x"0d04fd3d", -526 => x"0d757008", -527 => x"8a055353", -528 => x"81c0f433", -529 => x"517080c1", -530 => x"2e8b3873", -531 => x"f3387080", -532 => x"0c853d0d", -533 => x"04ff1270", -534 => x"81c0f008", -535 => x"31740c80", -536 => x"0c853d0d", -537 => x"04fc3d0d", -538 => x"81c0fc08", -539 => x"5574802e", -540 => x"8c387675", -541 => x"08710c81", -542 => x"c0fc0856", -543 => x"548c1553", -544 => x"81c0f008", -545 => x"528a5190", -546 => x"f03f7380", -547 => x"0c863d0d", -548 => x"04fb3d0d", -549 => x"77700856", -550 => x"56b05381", -551 => x"c0fc0852", -552 => x"7451acb4", -553 => x"3f850b8c", -554 => x"170c850b", -555 => x"8c160c75", -556 => x"08750c81", -557 => x"c0fc0854", -558 => x"73802e8a", -559 => x"38730875", -560 => x"0c81c0fc", -561 => x"08548c14", -562 => x"5381c0f0", -563 => x"08528a51", -564 => x"90a73f84", -565 => x"1508ad38", -566 => x"860b8c16", -567 => x"0c881552", -568 => x"88160851", -569 => x"8fb33f81", -570 => x"c0fc0870", -571 => x"08760c54", -572 => x"8c157054", -573 => x"548a5273", -574 => x"08518ffd", -575 => x"3f73800c", -576 => x"873d0d04", -577 => x"750854b0", -578 => x"53735275", -579 => x"51abc93f", -580 => x"73800c87", -581 => x"3d0d04d9", -582 => x"3d0db051", -583 => x"9eeb3f80", -584 => x"0881c0ec", -585 => x"0cb0519e", -586 => x"e03f8008", -587 => x"81c0fc0c", -588 => x"81c0ec08", -589 => x"80080c80", -590 => x"0b800884", -591 => x"050c820b", -592 => x"80088805", -593 => x"0ca80b80", -594 => x"088c050c", -595 => x"9f530b0b", -596 => x"80d49052", -597 => x"80089005", -598 => x"51aafd3f", -599 => x"a13d5e9f", -600 => x"530b0b80", -601 => x"d4b0527d", -602 => x"51aaed3f", -603 => x"8a0b80ff", -604 => x"b00c0b0b", -605 => x"80ded451", -606 => x"f9b43f0b", -607 => x"0b80d4d0", -608 => x"51f9ab3f", -609 => x"0b0b80de", -610 => x"d451f9a2", -611 => x"3f80e2b4", -612 => x"08802e8a", -613 => x"cf380b0b", -614 => x"80d58051", -615 => x"f9903f0b", -616 => x"0b80ded4", -617 => x"51f9873f", -618 => x"80e2b008", -619 => x"520b0b80", -620 => x"d5ac51f8", -621 => x"f93f80f2", -622 => x"cc51bbf8", -623 => x"3f810b9a", -624 => x"3d5e5b80", -625 => x"0b80e2b0", -626 => x"082582d6", -627 => x"38903d5f", -628 => x"80c10b81", -629 => x"c0f43481", -630 => x"0b81c2d0", -631 => x"0c80c20b", -632 => x"81c0f834", -633 => x"8240835a", -634 => x"9f530b0b", -635 => x"80d5dc52", -636 => x"7c51a9e4", -637 => x"3f814180", -638 => x"7d537e52", -639 => x"568f9e3f", -640 => x"8008762e", -641 => x"09810683", -642 => x"38815675", -643 => x"81c2d00c", -644 => x"7f705856", -645 => x"758325a2", -646 => x"38751010", -647 => x"16fd0542", -648 => x"a93dffa4", -649 => x"05538352", -650 => x"76518dcd", -651 => x"3f7f8105", -652 => x"70417058", -653 => x"56837624", -654 => x"e0386154", -655 => x"755380f2", -656 => x"d45281c1", -657 => x"88518dc1", -658 => x"3f81c0fc", -659 => x"08700858", -660 => x"58b05377", -661 => x"527651a8", -662 => x"ff3f850b", -663 => x"8c190c85", -664 => x"0b8c180c", -665 => x"7708770c", -666 => x"81c0fc08", -667 => x"5675802e", -668 => x"8a387508", -669 => x"770c81c0", -670 => x"fc08568c", -671 => x"165381c0", -672 => x"f008528a", -673 => x"518cf23f", -674 => x"84170888", -675 => x"e038860b", -676 => x"8c180c88", -677 => x"17528818", -678 => x"08518bfd", -679 => x"3f81c0fc", -680 => x"08700878", -681 => x"0c568c17", -682 => x"7054598a", -683 => x"52780851", -684 => x"8cc73f80", -685 => x"c10b81c0", -686 => x"f8335757", -687 => x"767626a2", -688 => x"3880c352", -689 => x"76518dab", -690 => x"3f800861", -691 => x"2e8aec38", -692 => x"81177081", -693 => x"ff0681c0", -694 => x"f8335858", -695 => x"58757727", -696 => x"e0387960", -697 => x"29627054", -698 => x"71535b59", -699 => x"99be3f80", -700 => x"0840787a", -701 => x"31708729", -702 => x"80083180", -703 => x"088a0581", -704 => x"c0f43381", -705 => x"c0f0085e", -706 => x"5b525a56", -707 => x"7780c12e", -708 => x"8ad8387b", -709 => x"f738811b", -710 => x"5b80e2b0", -711 => x"087b25fd", -712 => x"af3881c0", -713 => x"e451b98c", -714 => x"3f0b0b80", -715 => x"d5fc51f5", -716 => x"fd3f0b0b", -717 => x"80ded451", -718 => x"f5f43f0b", -719 => x"0b80d68c", -720 => x"51f5eb3f", -721 => x"0b0b80de", -722 => x"d451f5e2", -723 => x"3f81c0f0", -724 => x"08520b0b", -725 => x"80d6c451", -726 => x"f5d43f85", -727 => x"520b0b80", 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x"00002e44", +2965 => x"00002e4c", +2966 => x"00002e4c", +2967 => x"00002e54", +2968 => x"00002e54", +2969 => x"00002e5c", +2970 => x"00002e5c", +2971 => x"00002e64", +2972 => x"00002e64", +2973 => x"00002e6c", +2974 => x"00002e6c", +2975 => x"00002e74", +2976 => x"00002e74", +2977 => x"00002e7c", +2978 => x"00002e7c", +2979 => x"00002e84", +2980 => x"00002e84", +2981 => x"00002e8c", +2982 => x"00002e8c", +2983 => x"00002e94", +2984 => x"00002e94", +2985 => x"00002e9c", +2986 => x"00002e9c", +2987 => x"00002ea4", +2988 => x"00002ea4", +2989 => x"00002eac", +2990 => x"00002eac", +2991 => x"00002eb4", +2992 => x"00002eb4", +2993 => x"00002ebc", +2994 => x"00002ebc", +2995 => x"00002ec4", +2996 => x"00002ec4", +2997 => x"00002ecc", +2998 => x"00002ecc", +2999 => x"00002ed4", +3000 => x"00002ed4", +3001 => x"00002edc", +3002 => x"00002edc", +3003 => x"00002ee4", +3004 => x"00002ee4", +3005 => x"00002eec", +3006 => x"00002eec", +3007 => x"00002ef4", +3008 => x"00002ef4", +3009 => x"00002efc", +3010 => x"00002efc", +3011 => x"00002f04", +3012 => x"00002f04", +3013 => x"00002f0c", +3014 => x"00002f0c", +3015 => x"00002f14", +3016 => x"00002f14", +3017 => x"00002f1c", +3018 => x"00002f1c", +3019 => x"00002f24", +3020 => x"00002f24", +3021 => x"00002f2c", +3022 => x"00002f2c", +3023 => x"00002f34", +3024 => x"00002f34", +3025 => x"00002f3c", +3026 => x"00002f3c", +3027 => x"00002f50", +3028 => x"00000000", +3029 => x"000031b8", +3030 => x"00003214", +3031 => x"00003270", +3032 => x"00000000", +3033 => x"00000000", +3034 => x"00000000", +3035 => x"00000000", +3036 => x"00000000", +3037 => x"00000000", +3038 => x"00000000", +3039 => x"00000000", +3040 => x"00000000", +3041 => x"00002ad0", +3042 => x"00000000", +3043 => x"00000000", +3044 => x"00000000", +3045 => x"00000000", +3046 => x"00000000", +3047 => x"00000000", +3048 => x"00000000", +3049 => x"00000000", +3050 => x"00000000", +3051 => x"00000000", +3052 => x"00000000", +3053 => x"00000000", +3054 => x"00000000", +3055 => x"00000000", +3056 => x"00000000", +3057 => x"00000000", +3058 => x"00000000", +3059 => x"00000000", +3060 => x"00000000", +3061 => x"00000000", +3062 => x"00000000", +3063 => x"00000000", +3064 => x"00000000", +3065 => x"00000000", +3066 => x"00000000", +3067 => x"00000000", +3068 => x"00000000", +3069 => x"00000000", +3070 => x"00000001", +3071 => x"330eabcd", +3072 => x"1234e66d", +3073 => x"deec0005", +3074 => x"000b0000", +3075 => x"00000000", +3076 => x"00000000", +3077 => x"00000000", +3078 => x"00000000", +3079 => x"00000000", +3080 => x"00000000", +3081 => x"00000000", +3082 => x"00000000", +3083 => x"00000000", +3084 => x"00000000", +3085 => x"00000000", +3086 => x"00000000", +3087 => x"00000000", +3088 => x"00000000", +3089 => x"00000000", +3090 => x"00000000", +3091 => x"00000000", +3092 => x"00000000", +3093 => x"00000000", +3094 => x"00000000", +3095 => x"00000000", +3096 => x"00000000", +3097 => x"00000000", +3098 => x"00000000", +3099 => x"00000000", +3100 => x"00000000", +3101 => x"00000000", +3102 => x"00000000", +3103 => x"00000000", +3104 => x"00000000", +3105 => x"00000000", +3106 => x"00000000", +3107 => x"00000000", +3108 => x"00000000", +3109 => x"00000000", +3110 => x"00000000", +3111 => x"00000000", +3112 => x"00000000", +3113 => x"00000000", +3114 => x"00000000", +3115 => x"00000000", +3116 => x"00000000", +3117 => x"00000000", +3118 => x"00000000", +3119 => x"00000000", +3120 => x"00000000", +3121 => x"00000000", +3122 => x"00000000", +3123 => x"00000000", +3124 => x"00000000", +3125 => x"00000000", +3126 => x"00000000", +3127 => x"00000000", +3128 => x"00000000", +3129 => x"00000000", +3130 => x"00000000", +3131 => x"00000000", +3132 => x"00000000", +3133 => x"00000000", +3134 => x"00000000", +3135 => x"00000000", +3136 => x"00000000", +3137 => x"00000000", +3138 => x"00000000", +3139 => x"00000000", +3140 => x"00000000", +3141 => x"00000000", +3142 => x"00000000", +3143 => x"00000000", 3144 => x"00000000", 3145 => x"00000000", 3146 => x"00000000", -3147 => x"0000390c", -3148 => x"000004d2", -- iterations 0x4d2=1234 +3147 => x"00000000", +3148 => x"00000000", 3149 => x"00000000", 3150 => x"00000000", 3151 => x"00000000", @@ -3188,496 +3188,100 @@ shared variable ram : ram_type := 3159 => x"00000000", 3160 => x"00000000", 3161 => x"00000000", -3162 => x"ffffffff", +3162 => x"00000000", 3163 => x"00000000", -3164 => x"00020000", +3164 => x"00000000", 3165 => x"00000000", 3166 => x"00000000", -3167 => x"00003174", -3168 => x"00003174", -3169 => x"0000317c", -3170 => x"0000317c", -3171 => x"00003184", -3172 => x"00003184", -3173 => x"0000318c", -3174 => x"0000318c", -3175 => x"00003194", -3176 => x"00003194", -3177 => x"0000319c", -3178 => x"0000319c", -3179 => x"000031a4", -3180 => x"000031a4", -3181 => x"000031ac", -3182 => x"000031ac", -3183 => x"000031b4", -3184 => x"000031b4", -3185 => x"000031bc", -3186 => x"000031bc", -3187 => x"000031c4", -3188 => x"000031c4", -3189 => x"000031cc", -3190 => x"000031cc", -3191 => x"000031d4", -3192 => x"000031d4", -3193 => x"000031dc", -3194 => x"000031dc", -3195 => x"000031e4", -3196 => x"000031e4", -3197 => x"000031ec", -3198 => x"000031ec", -3199 => x"000031f4", -3200 => x"000031f4", -3201 => x"000031fc", -3202 => x"000031fc", -3203 => x"00003204", -3204 => x"00003204", -3205 => x"0000320c", -3206 => x"0000320c", -3207 => x"00003214", -3208 => x"00003214", -3209 => x"0000321c", -3210 => x"0000321c", -3211 => x"00003224", -3212 => x"00003224", -3213 => x"0000322c", -3214 => x"0000322c", -3215 => x"00003234", -3216 => x"00003234", -3217 => x"0000323c", -3218 => x"0000323c", -3219 => x"00003244", -3220 => x"00003244", -3221 => x"0000324c", -3222 => x"0000324c", -3223 => x"00003254", -3224 => x"00003254", -3225 => x"0000325c", -3226 => x"0000325c", -3227 => x"00003264", -3228 => x"00003264", -3229 => x"0000326c", -3230 => x"0000326c", -3231 => x"00003274", -3232 => x"00003274", -3233 => x"0000327c", -3234 => x"0000327c", -3235 => x"00003284", -3236 => x"00003284", -3237 => x"0000328c", -3238 => x"0000328c", -3239 => x"00003294", -3240 => x"00003294", -3241 => x"0000329c", -3242 => x"0000329c", -3243 => x"000032a4", -3244 => x"000032a4", -3245 => x"000032ac", -3246 => x"000032ac", -3247 => x"000032b4", -3248 => x"000032b4", -3249 => x"000032bc", -3250 => x"000032bc", -3251 => x"000032c4", -3252 => x"000032c4", -3253 => x"000032cc", -3254 => x"000032cc", -3255 => x"000032d4", -3256 => x"000032d4", -3257 => x"000032dc", -3258 => x"000032dc", -3259 => x"000032e4", -3260 => x"000032e4", -3261 => x"000032ec", -3262 => x"000032ec", -3263 => x"000032f4", -3264 => x"000032f4", -3265 => x"000032fc", -3266 => x"000032fc", -3267 => x"00003304", -3268 => x"00003304", -3269 => x"0000330c", -3270 => x"0000330c", -3271 => x"00003314", -3272 => x"00003314", -3273 => x"0000331c", -3274 => x"0000331c", -3275 => x"00003324", -3276 => x"00003324", -3277 => x"0000332c", -3278 => x"0000332c", -3279 => x"00003334", -3280 => x"00003334", -3281 => x"0000333c", -3282 => x"0000333c", -3283 => x"00003344", -3284 => x"00003344", -3285 => x"0000334c", -3286 => x"0000334c", -3287 => x"00003354", -3288 => x"00003354", -3289 => x"0000335c", -3290 => x"0000335c", -3291 => x"00003364", -3292 => x"00003364", -3293 => x"0000336c", -3294 => x"0000336c", -3295 => x"00003374", -3296 => x"00003374", -3297 => x"0000337c", -3298 => x"0000337c", -3299 => x"00003384", -3300 => x"00003384", -3301 => x"0000338c", -3302 => x"0000338c", -3303 => x"00003394", -3304 => x"00003394", -3305 => x"0000339c", -3306 => x"0000339c", -3307 => x"000033a4", -3308 => x"000033a4", -3309 => x"000033ac", -3310 => x"000033ac", -3311 => x"000033b4", -3312 => x"000033b4", -3313 => x"000033bc", -3314 => x"000033bc", -3315 => x"000033c4", -3316 => x"000033c4", -3317 => x"000033cc", -3318 => x"000033cc", -3319 => x"000033d4", -3320 => x"000033d4", -3321 => x"000033dc", -3322 => x"000033dc", -3323 => x"000033e4", -3324 => x"000033e4", -3325 => x"000033ec", -3326 => x"000033ec", -3327 => x"000033f4", -3328 => x"000033f4", -3329 => x"000033fc", -3330 => x"000033fc", -3331 => x"00003404", -3332 => x"00003404", -3333 => x"0000340c", -3334 => x"0000340c", -3335 => x"00003414", -3336 => x"00003414", -3337 => x"0000341c", -3338 => x"0000341c", -3339 => x"00003424", -3340 => x"00003424", -3341 => x"0000342c", -3342 => x"0000342c", -3343 => x"00003434", -3344 => x"00003434", -3345 => x"0000343c", -3346 => x"0000343c", -3347 => x"00003444", -3348 => x"00003444", -3349 => x"0000344c", -3350 => x"0000344c", -3351 => x"00003454", -3352 => x"00003454", -3353 => x"0000345c", -3354 => x"0000345c", -3355 => x"00003464", -3356 => x"00003464", -3357 => x"0000346c", -3358 => x"0000346c", -3359 => x"00003474", -3360 => x"00003474", -3361 => x"0000347c", -3362 => x"0000347c", -3363 => x"00003484", -3364 => x"00003484", -3365 => x"0000348c", -3366 => x"0000348c", -3367 => x"00003494", -3368 => x"00003494", -3369 => x"0000349c", -3370 => x"0000349c", -3371 => x"000034a4", -3372 => x"000034a4", -3373 => x"000034ac", -3374 => x"000034ac", -3375 => x"000034b4", -3376 => x"000034b4", -3377 => x"000034bc", -3378 => x"000034bc", -3379 => x"000034c4", -3380 => x"000034c4", -3381 => x"000034cc", -3382 => x"000034cc", -3383 => x"000034d4", -3384 => x"000034d4", -3385 => x"000034dc", -3386 => x"000034dc", -3387 => x"000034e4", -3388 => x"000034e4", -3389 => x"000034ec", -3390 => x"000034ec", -3391 => x"000034f4", -3392 => x"000034f4", -3393 => x"000034fc", -3394 => x"000034fc", -3395 => x"00003504", -3396 => x"00003504", -3397 => x"0000350c", -3398 => x"0000350c", -3399 => x"00003514", -3400 => x"00003514", -3401 => x"0000351c", -3402 => x"0000351c", -3403 => x"00003524", -3404 => x"00003524", -3405 => x"0000352c", -3406 => x"0000352c", -3407 => x"00003534", -3408 => x"00003534", -3409 => x"0000353c", -3410 => x"0000353c", -3411 => x"00003544", -3412 => x"00003544", -3413 => x"0000354c", -3414 => x"0000354c", -3415 => x"00003554", -3416 => x"00003554", -3417 => x"0000355c", -3418 => x"0000355c", -3419 => x"00003564", -3420 => x"00003564", -3421 => x"0000356c", -3422 => x"0000356c", -3423 => x"00003580", -3424 => x"00000000", -3425 => x"000037e8", -3426 => x"00003844", -3427 => x"000038a0", -3428 => x"00000000", -3429 => x"00000000", -3430 => x"00000000", -3431 => x"00000000", -3432 => x"00000000", -3433 => x"00000000", -3434 => x"00000000", -3435 => x"00000000", -3436 => x"00000000", -3437 => x"00003100", -3438 => x"00000000", -3439 => x"00000000", -3440 => x"00000000", -3441 => x"00000000", -3442 => x"00000000", -3443 => x"00000000", -3444 => x"00000000", -3445 => x"00000000", -3446 => x"00000000", -3447 => x"00000000", -3448 => x"00000000", -3449 => x"00000000", -3450 => x"00000000", -3451 => x"00000000", -3452 => x"00000000", -3453 => x"00000000", -3454 => x"00000000", -3455 => x"00000000", -3456 => x"00000000", -3457 => x"00000000", -3458 => x"00000000", -3459 => x"00000000", -3460 => x"00000000", -3461 => x"00000000", -3462 => x"00000000", -3463 => x"00000000", -3464 => x"00000000", -3465 => x"00000000", -3466 => x"00000001", -3467 => x"330eabcd", -3468 => x"1234e66d", -3469 => x"deec0005", -3470 => x"000b0000", -3471 => x"00000000", -3472 => x"00000000", -3473 => x"00000000", -3474 => x"00000000", -3475 => x"00000000", -3476 => x"00000000", -3477 => x"00000000", -3478 => x"00000000", -3479 => x"00000000", -3480 => x"00000000", -3481 => x"00000000", -3482 => x"00000000", -3483 => x"00000000", -3484 => x"00000000", -3485 => x"00000000", -3486 => x"00000000", -3487 => x"00000000", -3488 => x"00000000", -3489 => x"00000000", -3490 => x"00000000", -3491 => x"00000000", -3492 => x"00000000", -3493 => x"00000000", -3494 => x"00000000", -3495 => x"00000000", -3496 => x"00000000", -3497 => x"00000000", -3498 => x"00000000", -3499 => x"00000000", -3500 => x"00000000", -3501 => x"00000000", -3502 => x"00000000", -3503 => x"00000000", -3504 => x"00000000", -3505 => x"00000000", -3506 => x"00000000", -3507 => x"00000000", -3508 => x"00000000", -3509 => x"00000000", -3510 => x"00000000", -3511 => x"00000000", -3512 => x"00000000", -3513 => x"00000000", -3514 => x"00000000", -3515 => x"00000000", -3516 => x"00000000", -3517 => x"00000000", -3518 => x"00000000", -3519 => x"00000000", -3520 => x"00000000", -3521 => x"00000000", -3522 => x"00000000", -3523 => x"00000000", -3524 => x"00000000", -3525 => x"00000000", -3526 => x"00000000", -3527 => x"00000000", -3528 => x"00000000", -3529 => x"00000000", -3530 => x"00000000", -3531 => x"00000000", -3532 => x"00000000", -3533 => x"00000000", -3534 => x"00000000", -3535 => x"00000000", -3536 => x"00000000", -3537 => x"00000000", -3538 => x"00000000", -3539 => x"00000000", -3540 => x"00000000", -3541 => x"00000000", -3542 => x"00000000", -3543 => x"00000000", -3544 => x"00000000", -3545 => x"00000000", -3546 => x"00000000", -3547 => x"00000000", -3548 => x"00000000", -3549 => x"00000000", -3550 => x"00000000", -3551 => x"00000000", -3552 => x"00000000", -3553 => x"00000000", -3554 => x"00000000", -3555 => x"00000000", -3556 => x"00000000", -3557 => x"00000000", -3558 => x"00000000", -3559 => x"00000000", -3560 => x"00000000", -3561 => x"00000000", -3562 => x"00000000", -3563 => x"00000000", -3564 => x"00000000", -3565 => x"00000000", -3566 => x"00000000", -3567 => x"00000000", -3568 => x"00000000", -3569 => x"00000000", -3570 => x"00000000", -3571 => x"00000000", -3572 => x"00000000", -3573 => x"00000000", -3574 => x"00000000", -3575 => x"00000000", -3576 => x"00000000", -3577 => x"00000000", -3578 => x"00000000", -3579 => x"00000000", -3580 => x"00000000", -3581 => x"00000000", -3582 => x"00000000", -3583 => x"00000000", -3584 => x"00000000", -3585 => x"00000000", -3586 => x"00000000", -3587 => x"00000000", -3588 => x"00000000", -3589 => x"00000000", -3590 => x"00000000", -3591 => x"00000000", -3592 => x"00000000", -3593 => x"00000000", -3594 => x"00000000", -3595 => x"00000000", -3596 => x"00000000", -3597 => x"00000000", -3598 => x"00000000", -3599 => x"00000000", -3600 => x"00000000", -3601 => x"00000000", -3602 => x"00000000", -3603 => x"00000000", -3604 => x"00000000", -3605 => x"00000000", -3606 => x"00000000", -3607 => x"00000000", -3608 => x"00000000", -3609 => x"00000000", -3610 => x"00000000", -3611 => x"00000000", -3612 => x"00000000", -3613 => x"00000000", -3614 => x"00000000", -3615 => x"00000000", -3616 => x"00000000", -3617 => x"00000000", -3618 => x"00000000", -3619 => x"00000000", -3620 => x"00000000", -3621 => x"00000000", -3622 => x"00000000", -3623 => x"00000000", -3624 => x"00000000", -3625 => x"00000000", -3626 => x"00000000", -3627 => x"00000000", -3628 => x"00000000", -3629 => x"00000000", -3630 => x"00000000", -3631 => x"00000000", -3632 => x"00000000", -3633 => x"00000000", -3634 => x"00000000", -3635 => x"00000000", -3636 => x"00000000", -3637 => x"00000000", -3638 => x"00000000", -3639 => x"00000000", -3640 => x"00000000", -3641 => x"00000000", -3642 => x"00000000", -3643 => x"00000000", -3644 => x"00000000", -3645 => x"00000000", -3646 => x"00000000", -3647 => x"00003104", -3648 => x"ffffffff", -3649 => x"00000000", -3650 => x"ffffffff", -3651 => x"00000000", +3167 => x"00000000", +3168 => x"00000000", +3169 => x"00000000", +3170 => x"00000000", +3171 => x"00000000", +3172 => x"00000000", +3173 => x"00000000", +3174 => x"00000000", +3175 => x"00000000", +3176 => x"00000000", +3177 => x"00000000", +3178 => x"00000000", +3179 => x"00000000", +3180 => x"00000000", +3181 => x"00000000", +3182 => x"00000000", +3183 => x"00000000", +3184 => x"00000000", +3185 => x"00000000", +3186 => x"00000000", +3187 => x"00000000", +3188 => x"00000000", +3189 => x"00000000", +3190 => x"00000000", +3191 => x"00000000", +3192 => x"00000000", +3193 => x"00000000", +3194 => x"00000000", +3195 => x"00000000", +3196 => x"00000000", +3197 => x"00000000", +3198 => x"00000000", +3199 => x"00000000", +3200 => x"00000000", +3201 => x"00000000", +3202 => x"00000000", +3203 => x"00000000", +3204 => x"00000000", +3205 => x"00000000", +3206 => x"00000000", +3207 => x"00000000", +3208 => x"00000000", +3209 => x"00000000", +3210 => x"00000000", +3211 => x"00000000", +3212 => x"00000000", +3213 => x"00000000", +3214 => x"00000000", +3215 => x"00000000", +3216 => x"00000000", +3217 => x"00000000", +3218 => x"00000000", +3219 => x"00000000", +3220 => x"00000000", +3221 => x"00000000", +3222 => x"00000000", +3223 => x"00000000", +3224 => x"00000000", +3225 => x"00000000", +3226 => x"00000000", +3227 => x"00000000", +3228 => x"00000000", +3229 => x"00000000", +3230 => x"00000000", +3231 => x"00000000", +3232 => x"00000000", +3233 => x"00000000", +3234 => x"00000000", +3235 => x"00000000", +3236 => x"00000000", +3237 => x"00000000", +3238 => x"00000000", +3239 => x"00000000", +3240 => x"00000000", +3241 => x"00000000", +3242 => x"00000000", +3243 => x"00000000", +3244 => x"00000000", +3245 => x"00000000", +3246 => x"00000000", +3247 => x"00000000", +3248 => x"00000000", +3249 => x"00000000", +3250 => x"00000000", +3251 => x"00002ad4", +3252 => x"ffffffff", +3253 => x"00000000", +3254 => x"ffffffff", +3255 => x"00000000", others => x"00000000" ); @@ -3692,7 +3296,9 @@ begin if (mem_writeEnable = '1') then ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; end if; + if (mem_readEnable = '1') then mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/fastdmips.do b/zpu/hdl/zpu4/src/fastdmips.do deleted file mode 100644 index 504bf60..0000000 --- a/zpu/hdl/zpu4/src/fastdmips.do +++ /dev/null @@ -1,19 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_fastsim.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastdmipsintstack.do b/zpu/hdl/zpu4/src/fastdmipsintstack.do deleted file mode 100644 index ee9571e..0000000 --- a/zpu/hdl/zpu4/src/fastdmipsintstack.do +++ /dev/null @@ -1,19 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_fastsim.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_intstack.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastdmipssmall.do b/zpu/hdl/zpu4/src/fastdmipssmall.do deleted file mode 100644 index 3eaa083..0000000 --- a/zpu/hdl/zpu4/src/fastdmipssmall.do +++ /dev/null @@ -1,21 +0,0 @@ -set BreakOnAssertion 1 -vlib work - - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_small.vhd -vcom -93 -explicit bram_dmips.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/fasthello.do b/zpu/hdl/zpu4/src/fasthello.do deleted file mode 100644 index d49aeab..0000000 --- a/zpu/hdl/zpu4/src/fasthello.do +++ /dev/null @@ -1,19 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_fastsim.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_hello.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/fastsimzpu.do b/zpu/hdl/zpu4/src/fastsimzpu.do deleted file mode 100644 index 504bf60..0000000 --- a/zpu/hdl/zpu4/src/fastsimzpu.do +++ /dev/null @@ -1,19 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_fastsim.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -# run ZPU -run 60000 ms diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt index 10f0eaa..47b8a65 100644 --- a/zpu/hdl/zpu4/src/log.txt +++ b/zpu/hdl/zpu4/src/log.txt @@ -1,305 +1,156 @@ -H -e -l -l -o - -w -o -r -l -d - -1 - - - -H -e -l -l -o - -w -o +D +h r -l -d - -2 - - - - - - -H -e -l -l +y +s +t o - -w -o -r -l -d - -1 - - - - - - -H +n e -l -l -o -w -o -r -l -d - -2 - - - - - - -H +B e -l -l -o - -w -o +n +c +h +m +a r -l -d +k +, -1 - - - - - - -H +V e -l -l -o - -w -o r -l -d - -2 - - - - - - -H -e -l -l +s +i o +n -w -o -r -l -d - +2 +. 1 - - - - - - -H -e -l -l -o -w -o -r -l -d - -2 - - - - - - -H +( +L +a +n +g +u +a +g e -l -l -o - -w -o -r -l -d +: -1 +C +) -H -e -l -l -o - -w -o +P r -l -d - -2 - - - - - - -H -e -l -l o +g +r +a +m -w +c o -r +m +p +i l -d - -1 - - - - - - -H e -l -l -o +d w +i +t +h o -r -l -d +u +t -2 - - - - - - -H +' +r +e +g +i +s +t e -l -l -o - -w -o r -l -d +' -1 +a +t +t +r +i +b +u +t +e -H +E +x e -l -l +c +u +t +i o +n -w -o +s +t +a r -l -d +t +s +, -2 - - - - - - -H -e -l -l -o +5 +0 +0 +0 +0 -w -o r -l -d +u +n +s -1 - - - - - - -H -e -l -l +t +h +r o +u +g +h -w -o +D +h r -l -d - -2 - - - +y +s +t +o +n +e -H + diff --git a/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd b/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd deleted file mode 100644 index d39c9e9..0000000 --- a/zpu/hdl/zpu4/src/zpu_config_fastsim.vhd +++ /dev/null @@ -1,15 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -package zpu_config is - - constant Generate_Trace : boolean := false; - constant wordPower : integer := 5; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := '0'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"50"; -- 80MHz - constant maxAddrBitIncIO : integer := 15; - -end zpu_config; diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh index 161c748..44ead41 100644 --- a/zpu/hdl/zpu4/test/dmips/build.sh +++ b/zpu/hdl/zpu4/test/dmips/build.sh @@ -1,4 +1,4 @@ -zpu-elf-gcc -DTIME $ZPUDIR/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -abel -o dmips.elf +zpu-elf-gcc -DTIME ../../../../../../roadshow/dhrystone/dhry_*.c -O3 -Wl,--gc-sections -Wl,--relax -phi -o dmips.elf zpu-elf-objdump --disassemble-all >dmips.dis dmips.elf zpu-elf-objcopy -O binary dmips.elf dmips.bin java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam dmips.bin >dmips.ram diff --git a/zpu/hdl/zpu4/test/dmips/dmips.bin b/zpu/hdl/zpu4/test/dmips/dmips.bin index 1330fe3..ee1a6fe 100644 Binary files a/zpu/hdl/zpu4/test/dmips/dmips.bin and b/zpu/hdl/zpu4/test/dmips/dmips.bin differ diff --git a/zpu/hdl/zpu4/test/dmips/dmips.elf b/zpu/hdl/zpu4/test/dmips/dmips.elf index 7254a5d..3a04a5b 100644 Binary files a/zpu/hdl/zpu4/test/dmips/dmips.elf and b/zpu/hdl/zpu4/test/dmips/dmips.elf differ diff --git a/zpu/hdl/zpu4/test/dmips/dmips.ram b/zpu/hdl/zpu4/test/dmips/dmips.ram index 89047d5..0919ce1 100644 --- a/zpu/hdl/zpu4/test/dmips/dmips.ram +++ b/zpu/hdl/zpu4/test/dmips/dmips.ram @@ -1,14 +1,14 @@ 0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80e2a40c", +1 => x"82700b0b", +2 => x"80d5f40c", 3 => x"3a0b0b80", -4 => x"c6fc0400", +4 => x"c4fb0400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", 8 => x"80088408", 9 => x"88080b0b", -10 => x"80c7c32d", +10 => x"80c5c22d", 11 => x"880c840c", 12 => x"800c0400", 13 => x"00000000", @@ -71,7 +71,7 @@ 70 => x"00000000", 71 => x"00000000", 72 => x"0b0b0b88", -73 => x"c4040000", +73 => x"c3040000", 74 => x"00000000", 75 => x"00000000", 76 => x"00000000", @@ -88,7 +88,7 @@ 87 => x"00000000", 88 => x"72729f06", 89 => x"0981050b", -90 => x"0b0b88a7", +90 => x"0b0b88a6", 91 => x"05040000", 92 => x"00000000", 93 => x"00000000", @@ -159,25 +159,25 @@ 158 => x"00000000", 159 => x"00000000", 160 => x"71fc0608", -161 => x"0b0b80e2", -162 => x"90738306", +161 => x"0b0b80d5", +162 => x"e0738306", 163 => x"10100508", 164 => x"060b0b0b", -165 => x"88aa0400", +165 => x"88a90400", 166 => x"00000000", 167 => x"00000000", 168 => x"80088408", 169 => x"88087575", -170 => x"0b0b0baf", -171 => x"ac2d5050", +170 => x"0b0b0bad", +171 => x"aa2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", 175 => x"00000000", 176 => x"80088408", 177 => x"88087575", -178 => x"0b0b0baf", -179 => x"f02d5050", +178 => x"0b0b0bad", +179 => x"ee2d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -207,7 +207,7 @@ 206 => x"00000000", 207 => x"00000000", 208 => x"810b0b0b", -209 => x"80e2a00c", +209 => x"80d5f00c", 210 => x"51040000", 211 => x"00000000", 212 => x"00000000", @@ -254,8 +254,8 @@ 253 => x"00000000", 254 => x"00000000", 255 => x"00000000", -256 => x"83d93f80", -257 => x"cbcf3f04", +256 => x"82fd3fbf", +257 => x"a03f0410", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -263,2890 +263,2890 @@ 262 => x"10101010", 263 => x"10101010", 264 => x"10101010", -265 => x"10101053", -266 => x"51047381", -267 => x"ff067383", -268 => x"06098105", -269 => x"83051010", -270 => x"102b0772", -271 => x"fc060c51", -272 => x"51043c04", -273 => x"72728072", -274 => x"8106ff05", -275 => x"09720605", -276 => x"71105272", -277 => x"0a100a53", -278 => x"72ed3851", -279 => x"51535104", -280 => x"ff3d0d0b", -281 => x"0b80f294", -282 => x"08528412", -283 => x"08708106", -284 => x"515170f6", -285 => x"38710881", -286 => x"ff06800c", +265 => x"10105351", +266 => x"047381ff", +267 => x"06738306", +268 => x"09810583", +269 => x"05101010", +270 => x"2b0772fc", +271 => x"060c5151", +272 => x"043c0472", +273 => x"72807281", +274 => x"06ff0509", +275 => x"72060571", +276 => x"1052720a", +277 => x"100a5372", +278 => x"ed385151", +279 => x"535104ff", +280 => x"3d0d0b0b", +281 => x"80e5e408", +282 => x"52710870", +283 => x"882a8132", +284 => x"70810651", +285 => x"515170f1", +286 => x"3873720c", 287 => x"833d0d04", -288 => x"ff3d0d0b", -289 => x"0b80f294", -290 => x"08528412", -291 => x"08700a10", -292 => x"0a708106", -293 => x"51515170", -294 => x"f1387372", -295 => x"0c833d0d", -296 => x"0480e2a0", -297 => x"08802ea8", -298 => x"38838080", -299 => x"0b0b0b80", -300 => x"f2940c82", -301 => x"a0800b0b", -302 => x"0b80f298", -303 => x"0c829080", -304 => x"0b80f2a8", -305 => x"0c0b0b80", -306 => x"f29c0b80", -307 => x"f2ac0c04", -308 => x"f8808080", -309 => x"a40b0b0b", -310 => x"80f2940c", -311 => x"f8808082", -312 => x"800b0b0b", -313 => x"80f2980c", -314 => x"f8808084", -315 => x"800b80f2", -316 => x"a80cf880", -317 => x"8080940b", -318 => x"80f2ac0c", -319 => x"f8808080", -320 => x"9c0b80f2", -321 => x"a40cf880", -322 => x"8080a00b", -323 => x"80f2b00c", -324 => x"04f23d0d", -325 => x"600b0b80", -326 => x"f2980856", -327 => x"5d82750c", -328 => x"8059805a", -329 => x"800b8f3d", -330 => x"71101017", -331 => x"70085957", -332 => x"5d5b8076", -333 => x"81ff067c", -334 => x"832b5658", -335 => x"5276537b", -336 => x"519af33f", -337 => x"7d7f7a72", -338 => x"077c7207", -339 => x"71716081", -340 => x"05415f5d", -341 => x"5b595755", -342 => x"7a8724bb", -343 => x"380b0b80", -344 => x"f298087b", -345 => x"10101170", -346 => x"08585155", -347 => x"807681ff", -348 => x"067c832b", -349 => x"56585276", -350 => x"537b519a", -351 => x"b93f7d7f", -352 => x"7a72077c", -353 => x"72077171", -354 => x"60810541", -355 => x"5f5d5b59", -356 => x"5755877b", -357 => x"25c73876", -358 => x"7d0c7784", -359 => x"1e0c7c80", -360 => x"0c903d0d", -361 => x"04ff3d0d", -362 => x"80f2a033", -363 => x"5170a738", -364 => x"80e2ac08", -365 => x"70085252", -366 => x"70802e94", -367 => x"38841280", -368 => x"e2ac0c70", -369 => x"2d80e2ac", -370 => x"08700852", -371 => x"5270ee38", -372 => x"810b80f2", -373 => x"a034833d", -374 => x"0d040480", -375 => x"3d0d0b0b", -376 => x"80f29008", -377 => x"802e8e38", -378 => x"0b0b0b0b", -379 => x"800b802e", -380 => x"09810685", -381 => x"38823d0d", -382 => x"040b0b80", -383 => x"f290510b", -384 => x"0b0bf3fc", -385 => x"3f823d0d", -386 => x"0404ff3d", -387 => x"0d028f05", -388 => x"3352718a", -389 => x"2e8a3871", -390 => x"51fce53f", -391 => x"833d0d04", -392 => x"8d51fcdc", -393 => x"3f7151fc", -394 => x"d73f833d", -395 => x"0d04ce3d", -396 => x"0db53d70", -397 => x"70840552", -398 => x"088c8a5c", -399 => x"56a53d5e", -400 => x"5c807570", -401 => x"81055733", -402 => x"765b5558", -403 => x"73782e80", -404 => x"c1388e3d", -405 => x"5b73a52e", -406 => x"09810680", -407 => x"c5387870", -408 => x"81055a33", -409 => x"547380e4", -410 => x"2e81b638", -411 => x"7380e424", -412 => x"80c63873", -413 => x"80e32ea1", -414 => x"388052a5", -415 => x"51792d80", -416 => x"52735179", -417 => x"2d821858", -418 => x"78708105", -419 => x"5a335473", -420 => x"c4387780", -421 => x"0cb43d0d", -422 => x"047b841d", -423 => x"83123356", -424 => x"5d578052", -425 => x"7351792d", -426 => x"81187970", -427 => x"81055b33", -428 => x"555873ff", -429 => x"a038db39", -430 => x"7380f32e", -431 => x"098106ff", -432 => x"b8387b84", -433 => x"1d710859", -434 => x"5d568077", -435 => x"33555673", -436 => x"762e8d38", -437 => x"81167018", -438 => x"70335755", -439 => x"5674f538", -440 => x"ff165580", -441 => x"7625ffa0", -442 => x"38767081", -443 => x"05583354", -444 => x"80527351", -445 => x"792d8118", -446 => x"75ff1757", -447 => x"57588076", -448 => x"25ff8538", -449 => x"76708105", -450 => x"58335480", -451 => x"52735179", -452 => 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x"000034cc", -3382 => x"000034cc", -3383 => x"000034d4", -3384 => x"000034d4", -3385 => x"000034dc", -3386 => x"000034dc", -3387 => x"000034e4", -3388 => x"000034e4", -3389 => x"000034ec", -3390 => x"000034ec", -3391 => x"000034f4", -3392 => x"000034f4", -3393 => x"000034fc", -3394 => x"000034fc", -3395 => x"00003504", -3396 => x"00003504", -3397 => x"0000350c", -3398 => x"0000350c", -3399 => x"00003514", -3400 => x"00003514", -3401 => x"0000351c", -3402 => x"0000351c", -3403 => x"00003524", -3404 => x"00003524", -3405 => x"0000352c", -3406 => x"0000352c", -3407 => x"00003534", -3408 => x"00003534", -3409 => x"0000353c", -3410 => x"0000353c", -3411 => x"00003544", -3412 => x"00003544", -3413 => x"0000354c", -3414 => x"0000354c", -3415 => x"00003554", -3416 => x"00003554", -3417 => x"0000355c", -3418 => x"0000355c", -3419 => x"00003564", -3420 => x"00003564", -3421 => x"0000356c", -3422 => x"0000356c", -3423 => x"00003580", -3424 => x"00000000", -3425 => x"000037e8", -3426 => x"00003844", -3427 => x"000038a0", -3428 => x"00000000", -3429 => x"00000000", -3430 => x"00000000", -3431 => x"00000000", -3432 => x"00000000", -3433 => x"00000000", -3434 => x"00000000", -3435 => x"00000000", -3436 => x"00000000", -3437 => x"00003100", -3438 => x"00000000", -3439 => x"00000000", -3440 => x"00000000", -3441 => x"00000000", -3442 => x"00000000", -3443 => x"00000000", -3444 => x"00000000", -3445 => x"00000000", -3446 => x"00000000", -3447 => x"00000000", -3448 => x"00000000", -3449 => x"00000000", -3450 => x"00000000", -3451 => x"00000000", -3452 => x"00000000", -3453 => x"00000000", -3454 => x"00000000", -3455 => x"00000000", -3456 => x"00000000", -3457 => x"00000000", -3458 => x"00000000", -3459 => x"00000000", -3460 => x"00000000", -3461 => x"00000000", -3462 => x"00000000", -3463 => x"00000000", -3464 => x"00000000", -3465 => x"00000000", -3466 => x"00000001", -3467 => x"330eabcd", -3468 => x"1234e66d", -3469 => x"deec0005", -3470 => x"000b0000", -3471 => x"00000000", -3472 => x"00000000", -3473 => x"00000000", -3474 => x"00000000", -3475 => x"00000000", -3476 => x"00000000", -3477 => x"00000000", -3478 => x"00000000", -3479 => x"00000000", -3480 => x"00000000", -3481 => x"00000000", -3482 => x"00000000", -3483 => x"00000000", -3484 => x"00000000", -3485 => x"00000000", -3486 => x"00000000", -3487 => x"00000000", -3488 => x"00000000", -3489 => x"00000000", -3490 => x"00000000", -3491 => x"00000000", -3492 => x"00000000", -3493 => x"00000000", -3494 => x"00000000", -3495 => x"00000000", -3496 => x"00000000", -3497 => x"00000000", -3498 => x"00000000", -3499 => x"00000000", -3500 => x"00000000", -3501 => x"00000000", -3502 => x"00000000", -3503 => x"00000000", -3504 => x"00000000", -3505 => x"00000000", -3506 => x"00000000", -3507 => x"00000000", -3508 => x"00000000", -3509 => x"00000000", -3510 => x"00000000", -3511 => x"00000000", -3512 => x"00000000", -3513 => x"00000000", -3514 => x"00000000", -3515 => x"00000000", -3516 => x"00000000", -3517 => x"00000000", -3518 => x"00000000", -3519 => x"00000000", -3520 => x"00000000", -3521 => x"00000000", -3522 => x"00000000", -3523 => x"00000000", -3524 => x"00000000", -3525 => x"00000000", -3526 => x"00000000", -3527 => x"00000000", -3528 => x"00000000", -3529 => x"00000000", -3530 => x"00000000", -3531 => x"00000000", -3532 => x"00000000", -3533 => x"00000000", -3534 => x"00000000", -3535 => x"00000000", -3536 => x"00000000", -3537 => x"00000000", -3538 => x"00000000", -3539 => x"00000000", -3540 => x"00000000", -3541 => x"00000000", -3542 => x"00000000", -3543 => x"00000000", -3544 => x"00000000", -3545 => x"00000000", -3546 => x"00000000", -3547 => x"00000000", -3548 => x"00000000", -3549 => x"00000000", -3550 => x"00000000", -3551 => x"00000000", -3552 => x"00000000", -3553 => x"00000000", -3554 => x"00000000", -3555 => x"00000000", -3556 => x"00000000", -3557 => x"00000000", -3558 => x"00000000", -3559 => x"00000000", -3560 => x"00000000", -3561 => x"00000000", -3562 => x"00000000", -3563 => x"00000000", -3564 => x"00000000", -3565 => x"00000000", -3566 => x"00000000", -3567 => x"00000000", -3568 => x"00000000", -3569 => x"00000000", -3570 => x"00000000", -3571 => x"00000000", -3572 => x"00000000", -3573 => x"00000000", -3574 => x"00000000", -3575 => x"00000000", -3576 => x"00000000", -3577 => x"00000000", -3578 => x"00000000", -3579 => x"00000000", -3580 => x"00000000", -3581 => x"00000000", -3582 => x"00000000", -3583 => x"00000000", -3584 => x"00000000", -3585 => x"00000000", -3586 => x"00000000", -3587 => x"00000000", -3588 => x"00000000", -3589 => x"00000000", -3590 => x"00000000", -3591 => x"00000000", -3592 => x"00000000", -3593 => x"00000000", -3594 => x"00000000", -3595 => x"00000000", -3596 => x"00000000", -3597 => x"00000000", -3598 => x"00000000", -3599 => x"00000000", -3600 => x"00000000", -3601 => x"00000000", -3602 => x"00000000", -3603 => x"00000000", -3604 => x"00000000", -3605 => x"00000000", -3606 => x"00000000", -3607 => x"00000000", -3608 => x"00000000", -3609 => x"00000000", -3610 => x"00000000", -3611 => x"00000000", -3612 => x"00000000", -3613 => x"00000000", -3614 => x"00000000", -3615 => x"00000000", -3616 => x"00000000", -3617 => x"00000000", -3618 => x"00000000", -3619 => x"00000000", -3620 => x"00000000", -3621 => x"00000000", -3622 => x"00000000", -3623 => x"00000000", -3624 => x"00000000", -3625 => x"00000000", -3626 => x"00000000", -3627 => x"00000000", -3628 => x"00000000", -3629 => x"00000000", -3630 => x"00000000", -3631 => x"00000000", -3632 => x"00000000", -3633 => x"00000000", -3634 => x"00000000", -3635 => x"00000000", -3636 => x"00000000", -3637 => x"00000000", -3638 => x"00000000", -3639 => x"00000000", -3640 => x"00000000", -3641 => x"00000000", -3642 => x"00000000", -3643 => x"00000000", -3644 => x"00000000", -3645 => x"00000000", -3646 => x"00000000", -3647 => x"00003104", -3648 => x"ffffffff", -3649 => x"00000000", -3650 => x"ffffffff", -3651 => x"00000000", +3167 => x"00000000", +3168 => x"00000000", +3169 => x"00000000", +3170 => x"00000000", +3171 => x"00000000", +3172 => x"00000000", +3173 => x"00000000", +3174 => x"00000000", +3175 => x"00000000", +3176 => x"00000000", +3177 => x"00000000", +3178 => x"00000000", +3179 => x"00000000", +3180 => x"00000000", +3181 => x"00000000", +3182 => x"00000000", +3183 => x"00000000", +3184 => x"00000000", +3185 => x"00000000", +3186 => x"00000000", +3187 => x"00000000", +3188 => x"00000000", +3189 => x"00000000", +3190 => x"00000000", +3191 => x"00000000", +3192 => x"00000000", +3193 => x"00000000", +3194 => x"00000000", +3195 => x"00000000", +3196 => x"00000000", +3197 => x"00000000", +3198 => x"00000000", +3199 => x"00000000", +3200 => x"00000000", +3201 => x"00000000", +3202 => x"00000000", +3203 => x"00000000", +3204 => x"00000000", +3205 => x"00000000", +3206 => x"00000000", +3207 => x"00000000", +3208 => x"00000000", +3209 => x"00000000", +3210 => x"00000000", +3211 => x"00000000", +3212 => x"00000000", +3213 => x"00000000", +3214 => x"00000000", +3215 => x"00000000", +3216 => x"00000000", +3217 => x"00000000", +3218 => x"00000000", +3219 => x"00000000", +3220 => x"00000000", +3221 => x"00000000", +3222 => x"00000000", +3223 => x"00000000", +3224 => x"00000000", +3225 => x"00000000", +3226 => x"00000000", +3227 => x"00000000", +3228 => x"00000000", +3229 => x"00000000", +3230 => x"00000000", +3231 => x"00000000", +3232 => x"00000000", +3233 => x"00000000", +3234 => x"00000000", +3235 => x"00000000", +3236 => x"00000000", +3237 => x"00000000", +3238 => x"00000000", +3239 => x"00000000", +3240 => x"00000000", +3241 => x"00000000", +3242 => x"00000000", +3243 => x"00000000", +3244 => x"00000000", +3245 => x"00000000", +3246 => x"00000000", +3247 => x"00000000", +3248 => x"00000000", +3249 => x"00000000", +3250 => x"00000000", +3251 => x"00002ad4", +3252 => x"ffffffff", +3253 => x"00000000", +3254 => x"ffffffff", +3255 => x"00000000", -- cgit v1.1 From fbe743288c676e94b52849f083a9f3d5015a13ed Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 22 Feb 2008 07:57:20 +0000 Subject: wip porting zpu_core_bram.vhd from ZPU3. --- zpu/hdl/zpu4/src/bram_dmips.vhd | 6 +- zpu/hdl/zpu4/src/simzpu_bram.do | 28 ++ zpu/hdl/zpu4/src/zpu_config_trace.vhd | 1 + zpu/hdl/zpu4/src/zpu_core_bram.vhd | 780 ++++++++++++++++++++++++++++++++++ zpu/hdl/zpu4/src/zpu_core_small.vhd | 13 - zpu/hdl/zpu4/src/zpupkg.vhd | 13 + 6 files changed, 825 insertions(+), 16 deletions(-) create mode 100644 zpu/hdl/zpu4/src/simzpu_bram.do create mode 100644 zpu/hdl/zpu4/src/zpu_core_bram.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/bram_dmips.vhd b/zpu/hdl/zpu4/src/bram_dmips.vhd index 1c85e0d..83bfc28 100644 --- a/zpu/hdl/zpu4/src/bram_dmips.vhd +++ b/zpu/hdl/zpu4/src/bram_dmips.vhd @@ -10,11 +10,11 @@ use work.zpupkg.all; entity dualport_ram is port (clk : in std_logic; memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); memAWrite : in std_logic_vector(wordSize-1 downto 0); memARead : out std_logic_vector(wordSize-1 downto 0); memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit); + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); memBWrite : in std_logic_vector(wordSize-1 downto 0); memBRead : out std_logic_vector(wordSize-1 downto 0)); end dualport_ram; @@ -22,7 +22,7 @@ end dualport_ram; architecture dualport_ram_arch of dualport_ram is -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( diff --git a/zpu/hdl/zpu4/src/simzpu_bram.do b/zpu/hdl/zpu4/src/simzpu_bram.do new file mode 100644 index 0000000..1c8673d --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu_bram.do @@ -0,0 +1,28 @@ +# Xilinx WebPack modelsim script +# +# cd C:/workspace/zpu/zpu/hdl/zpu4/src +# do simzpu_bram.do + +set BreakOnAssertion 1 +vlib work + +vcom -93 -explicit zpu_config_trace.vhd +vcom -93 -explicit zpupkg.vhd +vcom -93 -explicit txt_util.vhd +vcom -93 -explicit sim_fpga_top.vhd +vcom -93 -explicit zpu_core_bram.vhd +vcom -93 -explicit bram_dmips.vhd +vcom -93 -explicit timer.vhd +vcom -93 -explicit io.vhd +vcom -93 -explicit trace.vhd + +# run ZPU +vsim fpga_top +view wave +add wave -recursive fpga_top/zpu/* +#add wave -recursive fpga_top/* +view structure +#view signals + +# Enough to run tiny programs +run 1us diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd index a2d7d9d..4d0f15f 100644 --- a/zpu/hdl/zpu4/src/zpu_config_trace.vhd +++ b/zpu/hdl/zpu4/src/zpu_config_trace.vhd @@ -12,6 +12,7 @@ package zpu_config is constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; constant maxAddrBitIncIO : integer := 27; constant maxAddrBitDRAM : integer := 16; + constant maxAddrBitBRAM : integer := 16; constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_core_bram.vhd b/zpu/hdl/zpu4/src/zpu_core_bram.vhd new file mode 100644 index 0000000..0bedba3 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core_bram.vhd @@ -0,0 +1,780 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- io_busy : in std_logic; +-- io_read : in std_logic_vector(7 downto 0); +-- io_write : out std_logic_vector(7 downto 0); +-- io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); +-- io_writeEnable : out std_logic; +-- io_readEnable : out std_logic; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memAWrite : std_logic_vector(wordSize-1 downto 0); +signal memARead : std_logic_vector(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); +signal memBWrite : std_logic_vector(wordSize-1 downto 0); +signal memBRead : std_logic_vector(wordSize-1 downto 0); + + + +signal pc : std_logic_vector(maxAddrBit downto 0); +signal sp : std_logic_vector(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +type State_Type is +( +State_ResyncDecode, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_ResyncStack, +State_AddSP, +State_ReadIODone, +State_Decode, +State_LoadByte1, +State_LoadByte2, +State_StoreByte1, +State_StoreByte2, +State_Mult1, +State_Mult2, +State_Mult3 +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP, +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushPC, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP, +Decoded_Ashiftleft, +Decoded_Ashiftright, +Decoded_Lshiftright, +Decoded_Eqbranch, +Decoded_Neqbranch, +Decoded_Eq, +Decoded_Neq, +Decoded_Loadb, +Decoded_Lessthan, +Decoded_Lessthanorequal, +Decoded_Ulessthan, +Decoded_Ulessthanorequal, +Decoded_Storeb, +Decoded_Lshift2, +Decoded_DoubleIm, +Decoded_AddIm, +Decoded_Mult16x16, +Decoded_Swap, +Decoded_Callpcrel, +Decoded_Pushspadd +); + + +signal mult1 : std_logic_vector(wordSize/2-1 downto 0); +signal mult2 : std_logic_vector(wordSize/2-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); + +signal storeByte : std_logic_vector(7 downto 0); +signal byteSelect : std_logic_vector(minAddrBit-1 downto 0); + +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode2 : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; + +signal state : State_Type; + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit), + memAWrite => memAWrite, + memARead => memARead, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit), + memBWrite => memBWrite, + memBRead => memBRead + ); + + + + process(clk, areset) + begin + if (clk'event and clk = '1') then + multResult <= mult1 * mult2; + end if; + end process; + + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable tOpcode2 : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable spOffset2 : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBit downto 0); + variable pushspaddTemp : std_logic_vector(maxAddrBit downto minAddrBit); + variable tempVal : std_logic_vector(wordSize-1 downto 0); + variable compareA : signed(wordSize-1 downto 0); + variable compareB : signed(wordSize-1 downto 0); + begin + if areset = '1' then + mult1 <= (others => '0'); + mult2 <= (others => '0'); + state <= State_ResyncDecode; + break <= '0'; + sp <= spStart(maxAddrBit downto minAddrBit); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + decodedOpcode <= Decoded_Break; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + opcode <= (others => '0'); + out_mem_addr <= (others => '0'); + mem_write <= (others => '0'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + begin_inst <= '0'; + + case state is + when State_Decode => + nextPC:=pc+1; + case pc(1 downto 0) is + when "00" => tOpcode := memARead(31 downto 24); + when "01" => tOpcode := memARead(23 downto 16); + when "10" => tOpcode := memARead(15 downto 8); + when others => tOpcode := memARead(7 downto 0); + end case; + case nextPC(1 downto 0) is + when "00" => tOpcode2 := memBRead(31 downto 24); + when "01" => tOpcode2 := memBRead(23 downto 16); + when "10" => tOpcode2 := memBRead(15 downto 8); + when others => tOpcode2 := memBRead(7 downto 0); + end case; + idim_flag <= tOpcode(7); + opcode <= tOpcode; + opcode2 <= tOpcode2; + if (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 4)=0 and tOpcode2(3 downto 0)=Opcode_Add and idim_flag='0') then + idim_flag <= '0'; + decodedOpcode <= Decoded_AddIm; + nextPC := pc + 2; + elsif (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 7)=OpCode_Im and idim_flag='0') then + decodedOpcode <= Decoded_DoubleIm; + nextPC := pc + 2; + elsif (tOpcode(7 downto 4)=OpCode_AddSP and tOpcode(3 downto 0)=0 and + tOpcode2(7 downto 4)=OpCode_AddSP and tOpcode2(3 downto 0)=0) then + decodedOpcode <= Decoded_Lshift2; + nextPC := pc + 2; + elsif (tOpcode(7 downto 7)=OpCode_Im) then + if (idim_flag='1') then + decodedOpcode<=Decoded_ImShift; + else + decodedOpcode<=Decoded_Im; + end if; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + decodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + decodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + if tOpcode(5 downto 0)=OpCode_Eqbranch then + decodedOpcode <= Decoded_Eqbranch; + elsif tOpcode(5 downto 0)=OpCode_Neqbranch then + decodedOpcode <= Decoded_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + decodedOpcode <= Decoded_Eq; + elsif tOpcode(5 downto 0)=OpCode_Neq then + decodedOpcode <= Decoded_Neq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + decodedOpcode <= Decoded_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + decodedOpcode <= Decoded_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + decodedOpcode <= Decoded_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + decodedOpcode <= Decoded_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + decodedOpcode <= Decoded_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + decodedOpcode <= Decoded_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Mult16x16 then + decodedOpcode <= Decoded_Mult16x16; + elsif tOpcode(5 downto 0)=OpCode_Swap then + decodedOpcode <= Decoded_Swap; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + decodedOpcode <= Decoded_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + decodedOpcode <= Decoded_Pushspadd; +-- elsif tOpcode(5 downto 0)=OpCode_Lshiftright then +-- decodedOpcode <= Decoded_Lshiftright; +-- elsif tOpcode(5 downto 0)=OpCode_Ashiftleft then +-- decodedOpcode <= Decoded_Ashiftleft; +-- elsif tOpcode(5 downto 0)=OpCode_Ashiftright then +-- decodedOpcode <= Decoded_Ashiftright; + else + decodedOpcode<=Decoded_Emulate; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + decodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_PushSP => + decodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + decodedOpcode<=Decoded_PopPC; + when OpCode_Add => + decodedOpcode<=Decoded_Add; + when OpCode_Or => + decodedOpcode<=Decoded_Or; + when OpCode_And => + decodedOpcode<=Decoded_And; + when OpCode_Load => + decodedOpcode<=Decoded_Load; + when OpCode_Not => + decodedOpcode<=Decoded_Not; + when OpCode_Flip => + decodedOpcode<=Decoded_Flip; + when OpCode_Store => + decodedOpcode<=Decoded_Store; + when OpCode_PopSP => + decodedOpcode<=Decoded_PopSP; + when OpCode_Break => + decodedOpcode<=Decoded_Break; + when others => + decodedOpcode<=Decoded_Nop; + end case; + end if; + -- Fetch the two next opcodes... :-) + memAAddr <= nextPC(maxAddrBit downto minAddrBit); + nextPC:=nextPC+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_Execute; + when State_Execute => + state <= State_Decode; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= pc; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= sp; + trace_opcode <= opcode; + trace_topOfStack <= memARead; + trace_topOfStackB <= memBRead; + + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0):=opcode(3 downto 0); + spOffset2(4):=not opcode2(4); + spOffset2(3 downto 0):=opcode2(3 downto 0); + + case decodedOpcode is + + when Decoded_DoubleIm => + memAWriteEnable <= '1'; + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 14 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(13 downto 7) <= opcode(6 downto 0); + memAWrite(6 downto 0) <= opcode2(6 downto 0); + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + pc <= pc + 2; + when Decoded_Im => + memAWriteEnable <= '1'; + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= opcode(6 downto 0); + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_ImShift => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= opcode(6 downto 0); + memBAddr <= sp + 1; + when Decoded_StoreSP => + memAWriteEnable <= '1'; + memAAddr <= sp+spOffset; + memAWrite <= memARead; + -- avoid address crashes. + memBAddr <= sp - 1; + sp <= sp + 1; + state <= State_ResyncDecode; + when Decoded_LoadSP => + sp <= sp - 1; + if (spOffset = 0) then + -- This is a duplicate instruction. + memAAddr <= sp-1; + memAWriteEnable <= '1'; + memAWrite <= memARead; + else + memAAddr <= sp+spOffset; + end if; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_Callpcrel => + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + memBAddr <= sp+1; + pc <= pc + memARead(maxAddrBit downto 0); + state <= State_ResyncDecode; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(4 downto 0); + state <= State_ResyncDecode; + when Decoded_AddSP => + if spOffset=0 then + -- avoid address line crashes... + -- FIX!!! is this an issue? + -- oh-well. While we are at it, we've got a faster + -- shift operation without updating the toolchain. + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= memARead + memARead; + memBAddr <= sp+1; + else + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= memARead; + memBAddr <= sp+spOffset; + state <= State_AddSP; + end if; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + memBAddr <= sp; + memBWrite <= memARead; + memBWriteEnable <= '1'; + when Decoded_Pushspadd => + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= (others => DontCareValue); + pushspaddTemp := memARead(maxAddrBit-minAddrBit downto 0); + memAWrite(maxAddrBit downto minAddrBit) <= sp+pushspaddTemp; + memBAddr <= sp+1; + when Decoded_PopPC => + memAAddr <= sp; + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_ResyncDecode; + when Decoded_AddIm => + memAWriteEnable <= '1'; + memAAddr <= sp; + tempVal(wordSize-1 downto 7) := (others => tOpcode(6)); + tempVal(6 downto 0) := tOpcode(6 downto 0); + memAWrite <= memARead + tempVal; + memBAddr <= sp + 1; + pc <= pc + 2; + when Decoded_Add => + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + sp <= sp + 1; + when Decoded_Or => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + when Decoded_And => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memBAddr <= sp + 1; + end if; + when Decoded_Swap => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(wordSize/2-1 downto 0) <= memARead(wordSize-1 downto wordSize/2); + memAWrite(wordSize-1 downto wordSize/2) <= memARead(wordSize/2-1 downto 0); + memBAddr <= sp + 1; + when Decoded_Not => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= not memARead; + memBAddr <= sp + 1; + when Decoded_Flip => + memAAddr <= sp; + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + memBAddr <= sp + 1; + when Decoded_Lshift2 => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite(1 downto 0) <= (others => '0'); + memAWrite(wordSize-1 downto 2) <= memARead(wordSize-1-2 downto 0); + memBAddr <= sp + 1; + pc <= pc + 2; + when Decoded_Store => + sp <= sp + 2; + if (memARead(ioBit)='1') then + out_mem_writeEnable <= '1'; + out_mem_addr <= memARead(maxAddrBitIncIO downto 0); + mem_write <= memBRead; + state <= State_WriteIO; + else + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_ResyncDecode; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_ResyncDecode; + when Decoded_Ashiftleft => + memAWrite(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))) <= + memBRead(wordSize-conv_integer(memARead(wordPower-1 downto 0))-1 downto 0); + if memARead(wordPower-1 downto 0)/=0 then + memAWrite(conv_integer(memARead(wordPower-1 downto 0))-1 downto 0) <= (others => '0'); + end if; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + sp <= sp + 1; + when Decoded_Ashiftright | Decoded_Lshiftright => + memAWrite(wordSize-1-conv_integer(memARead(wordPower-1 downto 0)) downto 0) <= + memBRead(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))); + if memARead(wordPower-1 downto 0)/=0 then + if decodedOpcode=Decoded_Ashiftright and memBRead(wordSize-1)='1' then + memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '1'); + else + memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '0'); + end if; + end if; + memAWriteEnable <= '1'; + memAAddr <= sp + 1; + memBAddr <= sp + 2; + sp <= sp + 1; + when Decoded_Eqbranch => + sp <= sp + 2; + if (memBRead=0) then + pc <= memARead(maxAddrBit downto 0) + pc; + end if; + state <= State_ResyncDecode; + when Decoded_Neqbranch => + sp <= sp + 2; + if (memBRead/=0) then + pc <= memARead(maxAddrBit downto 0) + pc; + end if; + state <= State_ResyncDecode; + when Decoded_Eq => + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead=memBRead) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Neq => + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead/=memBRead) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Ulessthan => + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead + sp <= sp + 1; + memAWrite <= (others => '0'); + if (memARead<=memBRead) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Lessthan => + sp <= sp + 1; + memAWrite <= (others => '0'); + compareA := signed(memARead); + compareB := signed(memBRead); + if (compareA + sp <= sp + 1; + memAWrite <= (others => '0'); + compareA := signed(memARead); + compareB := signed(memBRead); + if (compareA<=compareB) then + memAWrite(0) <= '1'; + end if; + memAAddr <= sp + 1; + memAWriteEnable <= '1'; + memBAddr <= sp + 2; + when Decoded_Loadb => + byteSelect <= memARead(minAddrBit-1 downto 0); + memAAddr <= memARead(maxAddrBit downto minAddrBit); + state <= State_LoadByte1; + when Decoded_Storeb => + sp <= sp + 2; + byteSelect <= memARead(minAddrBit-1 downto 0); + storeByte <= memBRead(7 downto 0); + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memBAddr <= sp; + state <= State_StoreByte1; + when Decoded_Mult16x16 => + mult1 <= memARead(wordSize/2-1 downto 0); + mult2 <= memBRead(wordSize/2-1 downto 0); + sp <= sp + 1; + state <= State_Mult1; + when others => + -- nop. Here we persist whatever was loaded into + -- memARead + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead; + memBAddr <= sp + 1; + + end case; + when State_ReadIO => + state <= State_ReadIODone; + when State_ReadIODone => + if (in_mem_busy = '0') then + state <= State_ResyncDecode; + memAWriteEnable <= '1'; + memAWrite <= (others => '0'); + memAWrite <= mem_read; + memAAddr <= sp; + end if; + when State_WriteIO => + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_ResyncDecode; + end if; + when State_ResyncDecode => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_ResyncStack; + when State_ResyncStack => + memAAddr <= sp; + memBAddr <= sp+1; + state <= State_Decode; + when State_AddSP => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_Add; + when State_Add => + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_LoadByte1 => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_LoadByte2; + when State_LoadByte2 => + memAWriteEnable <= '1'; + memAAddr <= sp; + memAWrite <= (others => '0'); + case byteSelect is + when "00" => memAWrite(7 downto 0) <= memARead(31 downto 24); + when "01" => memAWrite(7 downto 0) <= memARead(23 downto 16); + when "10" => memAWrite(7 downto 0) <= memARead(15 downto 8); + when others => memAWrite(7 downto 0) <= memARead(7 downto 0); + end case; + memBAddr <= sp + 1; + state <= State_Decode; + when State_StoreByte1 => + state <= State_StoreByte2; + when State_StoreByte2 => + memAWriteEnable <= '1'; + memAAddr <= memBRead(maxAddrBit downto minAddrBit); + memAWrite <= memARead; + case byteSelect is + when "00" => memAWrite(31 downto 24) <= storeByte; + when "01" => memAWrite(23 downto 16) <= storeByte; + when "10" => memAWrite(15 downto 8) <= storeByte; + when others => memAWrite(7 downto 0) <= storeByte; + end case; + state <= State_ResyncDecode; + when State_Mult1 => + memAAddr <= pc(maxAddrBit downto minAddrBit); + nextPC:=pc+1; + memBAddr <= nextPC(maxAddrBit downto minAddrBit); + state <= State_Mult2; + when State_Mult2 => + memAWriteEnable <= '1'; + memAWrite <= multResult; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + + when others => + null; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd index 8ebd40d..4d73f88 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -27,19 +27,6 @@ end zpu_core; architecture behave of zpu_core is -component dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end component; - - signal readIO : std_logic; diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd index fd00b9e..32e162b 100644 --- a/zpu/hdl/zpu4/src/zpupkg.vhd +++ b/zpu/hdl/zpu4/src/zpupkg.vhd @@ -24,6 +24,19 @@ package zpupkg is constant stack_size : integer := 2**stack_bits; + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + component dram is port (clk : in std_logic; areset : in std_logic; -- cgit v1.1 From 4f29574821f2931771b30ee8e2be33030e7695a8 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 15 Apr 2008 05:58:32 +0000 Subject: * zpu/simzpu_bram.do - retired. * zpu/zpu_core_bram.vhd - retired * zpu/hdl/zpu3 - retired --- zpu/hdl/zpu4/src/simzpu_bram.do | 28 -- zpu/hdl/zpu4/src/zpu_core_bram.vhd | 780 ------------------------------------- 2 files changed, 808 deletions(-) delete mode 100644 zpu/hdl/zpu4/src/simzpu_bram.do delete mode 100644 zpu/hdl/zpu4/src/zpu_core_bram.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/simzpu_bram.do b/zpu/hdl/zpu4/src/simzpu_bram.do deleted file mode 100644 index 1c8673d..0000000 --- a/zpu/hdl/zpu4/src/simzpu_bram.do +++ /dev/null @@ -1,28 +0,0 @@ -# Xilinx WebPack modelsim script -# -# cd C:/workspace/zpu/zpu/hdl/zpu4/src -# do simzpu_bram.do - -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_bram.vhd -vcom -93 -explicit bram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - -# run ZPU -vsim fpga_top -view wave -add wave -recursive fpga_top/zpu/* -#add wave -recursive fpga_top/* -view structure -#view signals - -# Enough to run tiny programs -run 1us diff --git a/zpu/hdl/zpu4/src/zpu_core_bram.vhd b/zpu/hdl/zpu4/src/zpu_core_bram.vhd deleted file mode 100644 index 0bedba3..0000000 --- a/zpu/hdl/zpu4/src/zpu_core_bram.vhd +++ /dev/null @@ -1,780 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - --- io_busy : in std_logic; --- io_read : in std_logic_vector(7 downto 0); --- io_write : out std_logic_vector(7 downto 0); --- io_addr : out std_logic_vector(maxAddrBit downto minAddrBit); --- io_writeEnable : out std_logic; --- io_readEnable : out std_logic; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - - -signal pc : std_logic_vector(maxAddrBit downto 0); -signal sp : std_logic_vector(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -type State_Type is -( -State_ResyncDecode, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_ResyncStack, -State_AddSP, -State_ReadIODone, -State_Decode, -State_LoadByte1, -State_LoadByte2, -State_StoreByte1, -State_StoreByte2, -State_Mult1, -State_Mult2, -State_Mult3 -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP, -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushPC, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP, -Decoded_Ashiftleft, -Decoded_Ashiftright, -Decoded_Lshiftright, -Decoded_Eqbranch, -Decoded_Neqbranch, -Decoded_Eq, -Decoded_Neq, -Decoded_Loadb, -Decoded_Lessthan, -Decoded_Lessthanorequal, -Decoded_Ulessthan, -Decoded_Ulessthanorequal, -Decoded_Storeb, -Decoded_Lshift2, -Decoded_DoubleIm, -Decoded_AddIm, -Decoded_Mult16x16, -Decoded_Swap, -Decoded_Callpcrel, -Decoded_Pushspadd -); - - -signal mult1 : std_logic_vector(wordSize/2-1 downto 0); -signal mult2 : std_logic_vector(wordSize/2-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); - -signal storeByte : std_logic_vector(7 downto 0); -signal byteSelect : std_logic_vector(minAddrBit-1 downto 0); - -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode2 : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; - -signal state : State_Type; - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit), - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit), - memBWrite => memBWrite, - memBRead => memBRead - ); - - - - process(clk, areset) - begin - if (clk'event and clk = '1') then - multResult <= mult1 * mult2; - end if; - end process; - - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable tOpcode2 : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable spOffset2 : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBit downto 0); - variable pushspaddTemp : std_logic_vector(maxAddrBit downto minAddrBit); - variable tempVal : std_logic_vector(wordSize-1 downto 0); - variable compareA : signed(wordSize-1 downto 0); - variable compareB : signed(wordSize-1 downto 0); - begin - if areset = '1' then - mult1 <= (others => '0'); - mult2 <= (others => '0'); - state <= State_ResyncDecode; - break <= '0'; - sp <= spStart(maxAddrBit downto minAddrBit); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - decodedOpcode <= Decoded_Break; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - opcode <= (others => '0'); - out_mem_addr <= (others => '0'); - mem_write <= (others => '0'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - begin_inst <= '0'; - - case state is - when State_Decode => - nextPC:=pc+1; - case pc(1 downto 0) is - when "00" => tOpcode := memARead(31 downto 24); - when "01" => tOpcode := memARead(23 downto 16); - when "10" => tOpcode := memARead(15 downto 8); - when others => tOpcode := memARead(7 downto 0); - end case; - case nextPC(1 downto 0) is - when "00" => tOpcode2 := memBRead(31 downto 24); - when "01" => tOpcode2 := memBRead(23 downto 16); - when "10" => tOpcode2 := memBRead(15 downto 8); - when others => tOpcode2 := memBRead(7 downto 0); - end case; - idim_flag <= tOpcode(7); - opcode <= tOpcode; - opcode2 <= tOpcode2; - if (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 4)=0 and tOpcode2(3 downto 0)=Opcode_Add and idim_flag='0') then - idim_flag <= '0'; - decodedOpcode <= Decoded_AddIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im and tOpcode2(7 downto 7)=OpCode_Im and idim_flag='0') then - decodedOpcode <= Decoded_DoubleIm; - nextPC := pc + 2; - elsif (tOpcode(7 downto 4)=OpCode_AddSP and tOpcode(3 downto 0)=0 and - tOpcode2(7 downto 4)=OpCode_AddSP and tOpcode2(3 downto 0)=0) then - decodedOpcode <= Decoded_Lshift2; - nextPC := pc + 2; - elsif (tOpcode(7 downto 7)=OpCode_Im) then - if (idim_flag='1') then - decodedOpcode<=Decoded_ImShift; - else - decodedOpcode<=Decoded_Im; - end if; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - decodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - decodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - if tOpcode(5 downto 0)=OpCode_Eqbranch then - decodedOpcode <= Decoded_Eqbranch; - elsif tOpcode(5 downto 0)=OpCode_Neqbranch then - decodedOpcode <= Decoded_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - decodedOpcode <= Decoded_Eq; - elsif tOpcode(5 downto 0)=OpCode_Neq then - decodedOpcode <= Decoded_Neq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - decodedOpcode <= Decoded_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - decodedOpcode <= Decoded_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - decodedOpcode <= Decoded_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - decodedOpcode <= Decoded_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - decodedOpcode <= Decoded_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - decodedOpcode <= Decoded_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Mult16x16 then - decodedOpcode <= Decoded_Mult16x16; - elsif tOpcode(5 downto 0)=OpCode_Swap then - decodedOpcode <= Decoded_Swap; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - decodedOpcode <= Decoded_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - decodedOpcode <= Decoded_Pushspadd; --- elsif tOpcode(5 downto 0)=OpCode_Lshiftright then --- decodedOpcode <= Decoded_Lshiftright; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftleft then --- decodedOpcode <= Decoded_Ashiftleft; --- elsif tOpcode(5 downto 0)=OpCode_Ashiftright then --- decodedOpcode <= Decoded_Ashiftright; - else - decodedOpcode<=Decoded_Emulate; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - decodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_PushSP => - decodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - decodedOpcode<=Decoded_PopPC; - when OpCode_Add => - decodedOpcode<=Decoded_Add; - when OpCode_Or => - decodedOpcode<=Decoded_Or; - when OpCode_And => - decodedOpcode<=Decoded_And; - when OpCode_Load => - decodedOpcode<=Decoded_Load; - when OpCode_Not => - decodedOpcode<=Decoded_Not; - when OpCode_Flip => - decodedOpcode<=Decoded_Flip; - when OpCode_Store => - decodedOpcode<=Decoded_Store; - when OpCode_PopSP => - decodedOpcode<=Decoded_PopSP; - when OpCode_Break => - decodedOpcode<=Decoded_Break; - when others => - decodedOpcode<=Decoded_Nop; - end case; - end if; - -- Fetch the two next opcodes... :-) - memAAddr <= nextPC(maxAddrBit downto minAddrBit); - nextPC:=nextPC+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Execute; - when State_Execute => - state <= State_Decode; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= pc; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= sp; - trace_opcode <= opcode; - trace_topOfStack <= memARead; - trace_topOfStackB <= memBRead; - - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0):=opcode(3 downto 0); - spOffset2(4):=not opcode2(4); - spOffset2(3 downto 0):=opcode2(3 downto 0); - - case decodedOpcode is - - when Decoded_DoubleIm => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 14 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(13 downto 7) <= opcode(6 downto 0); - memAWrite(6 downto 0) <= opcode2(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - pc <= pc + 2; - when Decoded_Im => - memAWriteEnable <= '1'; - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_ImShift => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= opcode(6 downto 0); - memBAddr <= sp + 1; - when Decoded_StoreSP => - memAWriteEnable <= '1'; - memAAddr <= sp+spOffset; - memAWrite <= memARead; - -- avoid address crashes. - memBAddr <= sp - 1; - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_LoadSP => - sp <= sp - 1; - if (spOffset = 0) then - -- This is a duplicate instruction. - memAAddr <= sp-1; - memAWriteEnable <= '1'; - memAWrite <= memARead; - else - memAAddr <= sp+spOffset; - end if; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Callpcrel => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - memBAddr <= sp+1; - pc <= pc + memARead(maxAddrBit downto 0); - state <= State_ResyncDecode; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(4 downto 0); - state <= State_ResyncDecode; - when Decoded_AddSP => - if spOffset=0 then - -- avoid address line crashes... - -- FIX!!! is this an issue? - -- oh-well. While we are at it, we've got a faster - -- shift operation without updating the toolchain. - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead + memARead; - memBAddr <= sp+1; - else - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= memARead; - memBAddr <= sp+spOffset; - state <= State_AddSP; - end if; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - memBAddr <= sp; - memBWrite <= memARead; - memBWriteEnable <= '1'; - when Decoded_Pushspadd => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => DontCareValue); - pushspaddTemp := memARead(maxAddrBit-minAddrBit downto 0); - memAWrite(maxAddrBit downto minAddrBit) <= sp+pushspaddTemp; - memBAddr <= sp+1; - when Decoded_PopPC => - memAAddr <= sp; - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_ResyncDecode; - when Decoded_AddIm => - memAWriteEnable <= '1'; - memAAddr <= sp; - tempVal(wordSize-1 downto 7) := (others => tOpcode(6)); - tempVal(6 downto 0) := tOpcode(6 downto 0); - memAWrite <= memARead + tempVal; - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Or => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_And => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp + 1; - end if; - when Decoded_Swap => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(wordSize/2-1 downto 0) <= memARead(wordSize-1 downto wordSize/2); - memAWrite(wordSize-1 downto wordSize/2) <= memARead(wordSize/2-1 downto 0); - memBAddr <= sp + 1; - when Decoded_Not => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= not memARead; - memBAddr <= sp + 1; - when Decoded_Flip => - memAAddr <= sp; - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - memBAddr <= sp + 1; - when Decoded_Lshift2 => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite(1 downto 0) <= (others => '0'); - memAWrite(wordSize-1 downto 2) <= memARead(wordSize-1-2 downto 0); - memBAddr <= sp + 1; - pc <= pc + 2; - when Decoded_Store => - sp <= sp + 2; - if (memARead(ioBit)='1') then - out_mem_writeEnable <= '1'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - mem_write <= memBRead; - state <= State_WriteIO; - else - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_ResyncDecode; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_ResyncDecode; - when Decoded_Ashiftleft => - memAWrite(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))) <= - memBRead(wordSize-conv_integer(memARead(wordPower-1 downto 0))-1 downto 0); - if memARead(wordPower-1 downto 0)/=0 then - memAWrite(conv_integer(memARead(wordPower-1 downto 0))-1 downto 0) <= (others => '0'); - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Ashiftright | Decoded_Lshiftright => - memAWrite(wordSize-1-conv_integer(memARead(wordPower-1 downto 0)) downto 0) <= - memBRead(wordSize-1 downto conv_integer(memARead(wordPower-1 downto 0))); - if memARead(wordPower-1 downto 0)/=0 then - if decodedOpcode=Decoded_Ashiftright and memBRead(wordSize-1)='1' then - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '1'); - else - memAWrite(wordSize-1 downto wordSize-conv_integer(memARead(wordPower-1 downto 0))-1) <= (others => '0'); - end if; - end if; - memAWriteEnable <= '1'; - memAAddr <= sp + 1; - memBAddr <= sp + 2; - sp <= sp + 1; - when Decoded_Eqbranch => - sp <= sp + 2; - if (memBRead=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Neqbranch => - sp <= sp + 2; - if (memBRead/=0) then - pc <= memARead(maxAddrBit downto 0) + pc; - end if; - state <= State_ResyncDecode; - when Decoded_Eq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Neq => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead/=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Ulessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead - sp <= sp + 1; - memAWrite <= (others => '0'); - if (memARead<=memBRead) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Lessthan => - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA - sp <= sp + 1; - memAWrite <= (others => '0'); - compareA := signed(memARead); - compareB := signed(memBRead); - if (compareA<=compareB) then - memAWrite(0) <= '1'; - end if; - memAAddr <= sp + 1; - memAWriteEnable <= '1'; - memBAddr <= sp + 2; - when Decoded_Loadb => - byteSelect <= memARead(minAddrBit-1 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - state <= State_LoadByte1; - when Decoded_Storeb => - sp <= sp + 2; - byteSelect <= memARead(minAddrBit-1 downto 0); - storeByte <= memBRead(7 downto 0); - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memBAddr <= sp; - state <= State_StoreByte1; - when Decoded_Mult16x16 => - mult1 <= memARead(wordSize/2-1 downto 0); - mult2 <= memBRead(wordSize/2-1 downto 0); - sp <= sp + 1; - state <= State_Mult1; - when others => - -- nop. Here we persist whatever was loaded into - -- memARead - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead; - memBAddr <= sp + 1; - - end case; - when State_ReadIO => - state <= State_ReadIODone; - when State_ReadIODone => - if (in_mem_busy = '0') then - state <= State_ResyncDecode; - memAWriteEnable <= '1'; - memAWrite <= (others => '0'); - memAWrite <= mem_read; - memAAddr <= sp; - end if; - when State_WriteIO => - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_ResyncDecode; - end if; - when State_ResyncDecode => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_ResyncStack; - when State_ResyncStack => - memAAddr <= sp; - memBAddr <= sp+1; - state <= State_Decode; - when State_AddSP => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Add; - when State_Add => - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_LoadByte1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_LoadByte2; - when State_LoadByte2 => - memAWriteEnable <= '1'; - memAAddr <= sp; - memAWrite <= (others => '0'); - case byteSelect is - when "00" => memAWrite(7 downto 0) <= memARead(31 downto 24); - when "01" => memAWrite(7 downto 0) <= memARead(23 downto 16); - when "10" => memAWrite(7 downto 0) <= memARead(15 downto 8); - when others => memAWrite(7 downto 0) <= memARead(7 downto 0); - end case; - memBAddr <= sp + 1; - state <= State_Decode; - when State_StoreByte1 => - state <= State_StoreByte2; - when State_StoreByte2 => - memAWriteEnable <= '1'; - memAAddr <= memBRead(maxAddrBit downto minAddrBit); - memAWrite <= memARead; - case byteSelect is - when "00" => memAWrite(31 downto 24) <= storeByte; - when "01" => memAWrite(23 downto 16) <= storeByte; - when "10" => memAWrite(15 downto 8) <= storeByte; - when others => memAWrite(7 downto 0) <= storeByte; - end case; - state <= State_ResyncDecode; - when State_Mult1 => - memAAddr <= pc(maxAddrBit downto minAddrBit); - nextPC:=pc+1; - memBAddr <= nextPC(maxAddrBit downto minAddrBit); - state <= State_Mult2; - when State_Mult2 => - memAWriteEnable <= '1'; - memAWrite <= multResult; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - - when others => - null; - end case; - end if; - end process; - - - -end behave; -- cgit v1.1 From af198f5c76764dd55a5eed7a29ab24b032792e89 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 15 Apr 2008 06:00:18 +0000 Subject: retired --- zpu/hdl/zpu4/src/status.txt | 109 -------------------------------------------- 1 file changed, 109 deletions(-) delete mode 100644 zpu/hdl/zpu4/src/status.txt (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/status.txt b/zpu/hdl/zpu4/src/status.txt deleted file mode 100644 index df01caf..0000000 --- a/zpu/hdl/zpu4/src/status.txt +++ /dev/null @@ -1,109 +0,0 @@ -- Before NEQBRANCH opt 4.684 DMIPS 8.0 cycles average, after -- opcode pairs - -0x6060 0.1519223038446077 75961 9.048362120309708 LOADSP + LOADSP -0x4040 0.13967027934055867 69835 11.08668042546436 STORESP + STORESP -0x8038 0.10230620461240922 51153 10.251102204408818 IM + NEQBRANCH -0x4060 0.09856219712439425 49281 9.822802471596571 STORESP + LOADSP -0x6080 0.09734219468438937 48671 6.483415478886373 LOADSP + IM -0x3860 0.08642217284434568 43211 12.616350364963504 NEQBRANCH + LOADSP -0x8080 0.060966121932243864 30483 4.275915275634731 IM + IM -0x8005 0.05317010634021268 26585 6.572311495673671 IM + ADD -0x540 0.05215210430420861 26076 9.339541547277937 ADD + STORESP -0x3d0d 0.050808101616203236 25404 12.398243045387995 -0xd04 0.0466000932001864 23300 20.0 -0x6040 0.04389608779217558 21948 9.460344827586207 -0x4080 0.043648087296174594 21824 7.630769230769231 -0xc80 0.03966807933615867 19834 11.438292964244521 -0x8010 0.0391500783001566 19575 6.1248435544430535 -0x480 0.038798077596155195 19399 10.941342357586013 - - -- zpu_core.vhd: 1500 LUTs. Xilinx ISE reports 83MHz maximum frequency after P&R - which matches what I've found w/my ic300.vhd testbench - -- zpu_core_instack.vhd - - problems w/simulation trace since storeb/loadb will run into undefined memory - during emulation. Solution: implement loadb+storeb. - - simulation needs to read cycles from ModelSim trace so as to m ake readcycles - not cause false positives. This has other interesting potentials w.r.t. - knowing which instructions take the longest. - -- Ca. 1700 LUT inc. all instructions. Removing all higher level instructions - => 1300. - -- Review memory interface - - When is mem_busy high? Will it be high on the next cycle after - I've send mem_read/writeEnable? - - Should I hold off posting a read/write until mem_busy = '0'? - - Write posting could increase performance somewhat. Should there be - a seperate write busy signal? - - Synchronous reset? The ARM7 will have to copy the program to DRAM and - then start the ZPU. - -- Current instruction set has - - 31 DMIPS single cycle performance Simulator.java - - 8 DMIPS w/single cycle RAM access in ModelSim - -112 0.06100380865858346 67215918 -56 0.04139603650830458 45611457 -129 0.0375812381475752 41408192 -5 0.03703417264799563 40805418 -113 0.03540341331682748 39008596 -128 0.0343154384313754 37809831 -83 0.03322159422742951 36604599 -114 0.03213492807203279 35407276 -132 0.03158580962697109 34802240 -12 0.03049709687915076 33602662 -8 0.029409690138646426 32404523 -115 0.026690690908727877 29408644 -46 0.025054316381406774 27605635 -82 0.023965804208719754 26406278 -84 0.023961360698074072 26401382 -116 0.023417718589457643 25802380 -81 0.02179306727026773 24012288 -117 0.021783900714401432 24002188 -4 0.01797685126990833 19807461 -6 0.016340292503890113 18004249 -85 0.016339001017850734 18002826 -255 0.016338918428089957 18002735 -86 0.016337281154151066 18000931 -11 0.011984767180825744 13205194 -51 0.0114390303780569 12603884 -38 0.010892246228211845 12001420 -118 0.010347263624247446 11400941 -131 0.009257503529350904 10200209 -7 0.008713386756504965 9600684 -22 0.008712946580307425 9600199 - - -64 0.16176824859336478 178241352 -96 0.23147927881894828 255051161 -128 0.2646966482624612 291651105 - - -- Alternate memory interface to allow more caching in memory subsystem? - --- The memory interface allows a dual port memory to be used --- to increase performance. --- --- Also it is possible to implement a zero cycle register file instead --- of memory, though obviously that will cause problems w.r.t. max --- frequency for the ZPU. --- --- mem_writeEnable - set to '1' for a single cycle to send off a write request. --- mem_write is valid only while mem_writeEnable='1'. --- mem_readEnable - set to '1' for a single cycle to send off a read request. --- mem_read is a single cycle while mem_read_busy='0'. --- --- mem_read/write_busy - It is illegal to send off a read/write request when mem_read/write_busy='1'. --- Set to '0' when mem_read is valid after a read request. Note that --- the definition allows zero wait state ram. --- mem_read/write_addr - address for read/write request --- mem_read - read data. Valid only on the cycle after mem_busy='0' after --- mem_readEnable='1' for a single cycle. --- mem_write - data to write --- mem_writeMask - set to '1' for those bits that are to be written to memory upon --- write request --- break - set to '1' when CPU hits break instruction --- interrupt - set to '1' until interrupts are cleared by CPU. -- cgit v1.1 From 748de9774226a19c32ee1ed6a4e6474e9e0acb27 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 17 Apr 2008 06:42:27 +0000 Subject: * retired Xilinx synthesizing example. It messes up the zpu4 directory. --- zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd | 31 - zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd | 213 ---- .../dummyfpgalib/ddrsdram/simscripts/ddr_tb.do | 17 - .../dummyfpgalib/ddrsdram/simscripts/ddr_top.do | 111 -- zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd | 90 -- zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd | 301 ----- zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd | 660 ---------- .../zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd | 1320 -------------------- zpu/hdl/zpu4/src/build.xml | 114 -- zpu/hdl/zpu4/src/ic300.bitgen | 27 - zpu/hdl/zpu4/src/ic300.lso | 1 - zpu/hdl/zpu4/src/ic300.ucf | 146 --- zpu/hdl/zpu4/src/ic300.vhd | 144 --- zpu/hdl/zpu4/src/ic300_config.vhd | 26 - zpu/hdl/zpu4/src/ic300pkg.vhd | 88 -- zpu/hdl/zpu4/src/xmake.filelist | 12 - zpu/hdl/zpu4/src/xmake.filelist.bramsmall | 5 - zpu/hdl/zpu4/src/xmake.xst | 53 - zpu/hdl/zpu4/src/zpuio_bram.vhd | 229 ---- 19 files changed, 3588 deletions(-) delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd delete mode 100644 zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd delete mode 100644 zpu/hdl/zpu4/src/build.xml delete mode 100644 zpu/hdl/zpu4/src/ic300.bitgen delete mode 100644 zpu/hdl/zpu4/src/ic300.lso delete mode 100644 zpu/hdl/zpu4/src/ic300.ucf delete mode 100644 zpu/hdl/zpu4/src/ic300.vhd delete mode 100644 zpu/hdl/zpu4/src/ic300_config.vhd delete mode 100644 zpu/hdl/zpu4/src/ic300pkg.vhd delete mode 100644 zpu/hdl/zpu4/src/xmake.filelist delete mode 100644 zpu/hdl/zpu4/src/xmake.filelist.bramsmall delete mode 100644 zpu/hdl/zpu4/src/xmake.xst delete mode 100644 zpu/hdl/zpu4/src/zpuio_bram.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd deleted file mode 100644 index 95fbc18..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7pkg.vhd +++ /dev/null @@ -1,31 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -package arm7 is - - component arm7wb - generic( - simulate_io_time : boolean := false); - port ( areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - cpu_din : out std_logic_vector(15 downto 0); - cpu_a : out std_logic_vector(20 downto 0); - cpu_we : out std_logic_vector(1 downto 0); - cpu_re : out std_logic; - cpu_dout : in std_logic_vector(15 downto 0)); - end component; - -end arm7; - - \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd b/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd deleted file mode 100644 index 55b8125..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/arm7/src/arm7wb.vhd +++ /dev/null @@ -1,213 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity arm7wb is - generic( - simulate_io_time : boolean := false); - port ( areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - cpu_din : out std_logic_vector(15 downto 0); - cpu_a : out std_logic_vector(20 downto 0); - cpu_we : out std_logic_vector(1 downto 0); - cpu_re : out std_logic; - cpu_dout : in std_logic_vector(15 downto 0)); -end arm7wb; - -architecture behave of arm7wb is - -attribute keep : string; - -signal cpu_oe_n : std_logic; -signal cpu_fiq : std_logic; -signal cpu_wait_n : std_logic; -signal cpu_clk_toggle : std_logic; -signal cpu_clk_smp1 : std_logic; -signal cpu_clk_smp2 : std_logic; -signal cpu_clk_phase : std_logic; -signal cpu_oe_n_del : std_logic; -signal cpu_a_smp : std_logic_vector(20 downto 0); -signal cpu_d_smp : std_logic_vector(15 downto 0); - -signal int_oe_n : std_logic_vector(15 downto 0); -attribute keep of int_oe_n:signal is "true"; - -signal cpu_irq : std_logic_vector(1 downto 0); -signal cpu_wr_n : std_logic_vector(1 downto 0); -signal cpu_cs_n : std_logic_vector(3 downto 1); - -signal dout : std_logic_vector(15 downto 0); -signal cpu_d_p_out : std_logic_vector(15 downto 0); -signal read_cnt : std_logic_vector(1 downto 0); - -signal cpu_wr_n_p_del : std_logic_vector(1 downto 0); -signal cpu_a_p_del : std_logic_vector(20 downto 0); -signal cpu_d_p_del : std_logic_vector(15 downto 0); -signal cpu_cs_n_p_del : std_logic_vector(3 downto 1); -signal cpu_oe_n_p_del : std_logic; - -constant Sim_Delay : time := 0.5 ns; -constant Clock_2_Out : time := 5.5 ns; -constant Input_Setup : time := 2.5 ns; - -begin - - cpu_wait_n <= '1'; - cpu_fiq <= '1'; - cpu_irq <= "11"; - - iotimingon: - if simulate_io_time generate - begin - cpu_wr_n_p_del <= "XX" after 0 ns, cpu_wr_n_p after Input_Setup; - cpu_a_p_del <= "XXXXXXXXXXXXXXXXXXXXX" after 0 ns, cpu_a_p after Input_Setup; - cpu_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, cpu_d_p after Input_Setup; - cpu_cs_n_p_del <= "XXX" after 0 ns, cpu_cs_n_p after Input_Setup; - cpu_oe_n_p_del <= 'X' after 0 ns, cpu_oe_n_p after Input_Setup; - end generate; - - iotimingoff: - if not simulate_io_time generate - begin - cpu_wr_n_p_del <= cpu_wr_n_p; - cpu_a_p_del <= cpu_a_p; - cpu_d_p_del <= cpu_d_p; - cpu_cs_n_p_del <= cpu_cs_n_p; - cpu_oe_n_p_del <= cpu_oe_n_p; - end generate; - - process(cpu_clk, areset) -- Toggle FF with 1x clock to find phase - begin - if areset = '1' then - cpu_clk_toggle <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - cpu_clk_toggle <= not(cpu_clk_toggle); - end if; - end process; - - process(cpu_clk_2x, areset) -- Find phase relationsship between 1x and 2x clock - begin - if areset = '1' then - cpu_clk_smp1 <= '0'; - cpu_clk_smp2 <= '1'; - cpu_clk_phase <= '0'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - cpu_clk_smp1 <= cpu_clk_toggle; - cpu_clk_smp2 <= cpu_clk_smp1; - if cpu_clk_smp1 = '1' and cpu_clk_smp2 = '0' then - cpu_clk_phase <= '0' after Sim_Delay; - else - cpu_clk_phase <= not(cpu_clk_phase) after Sim_Delay; - end if; - end if; - end process; - - process(cpu_clk_2x, areset) -- Sample input signals - begin - if areset = '1' then - cpu_oe_n <= '1'; - cpu_a_smp <= "000000000000000000000"; - cpu_d_smp <= "0000000000000000"; - cpu_wr_n <= "11"; - cpu_cs_n <= "111"; - elsif (cpu_clk_2x = '1' and cpu_clk_2x'event) then - cpu_oe_n <= cpu_oe_n_p_del after Sim_Delay; - cpu_a_smp <= cpu_a_p_del after Sim_Delay; - cpu_d_smp <= cpu_d_p_del after Sim_Delay; - cpu_wr_n <= cpu_wr_n_p_del after Sim_Delay; - cpu_cs_n <= cpu_cs_n_p_del after Sim_Delay; - end if; - end process; - - cpu_d_out: - for i in 0 to 15 generate - begin - process(cpu_clk_2x, areset) - begin - if areset = '1' then - cpu_d_p(i) <= 'Z'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - if int_oe_n(i) = '0' then - cpu_d_p(i) <= cpu_d_p_out(i) after Clock_2_Out; - else - cpu_d_p(i) <= 'Z' after Clock_2_Out; - end if; - end if; - end process; - end generate; - - process(cpu_clk, areset) -- Clocked output pins - begin - if areset = '1' then - cpu_d_p_out <= "1111111111111111"; - cpu_wait_n_p <= '1'; - cpu_irq_p <= "11"; - cpu_fiq_p <= '1'; - elsif (cpu_clk = '1' and cpu_clk'event) then - cpu_d_p_out <= cpu_dout; - cpu_wait_n_p <= '1'; - cpu_irq_p <= "11"; - cpu_fiq_p <= '1'; - end if; - end process; - - process(cpu_clk, areset) -- Generate control signals - begin - if areset = '1' then - int_oe_n <= "1111111111111111"; - read_cnt <= "00"; - cpu_we <= "00"; - cpu_re <= '0'; - cpu_a <= "000000000000000000000"; - cpu_din <= "0000000000000000"; - elsif (cpu_clk = '1' and cpu_clk'event) then - - cpu_a <= cpu_a_smp; - cpu_din <= cpu_d_smp; - - cpu_oe_n_del <= cpu_oe_n; - - if cpu_cs_n(1) = '1' then - read_cnt <= "00"; - else - read_cnt <= read_cnt + '1'; - end if; - - if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(0) = '0' then - cpu_we(0) <= '1'; - else - cpu_we(0) <= '0'; - end if; - - if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_wr_n(1) = '0' then - cpu_we(1) <= '1'; - else - cpu_we(1) <= '0'; - end if; - - if read_cnt = "00" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then - cpu_re <= '1'; - else - cpu_re <= '0'; - end if; - - if read_cnt = "01" and cpu_cs_n(1) = '0' and cpu_oe_n = '0' then - int_oe_n <= "0000000000000000"; - else - int_oe_n <= "1111111111111111"; - end if; - - end if; - end process; - -end behave; diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do deleted file mode 100644 index d2c22cf..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_tb.do +++ /dev/null @@ -1,17 +0,0 @@ -vlib zylin -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd -vcom -93 -explicit -work zylin ../ddrsdram/src/mt46v16m16.vhd -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_tb.vhd -vlib work -vsim -t 1ps zylin.ddr_tb -view wave -view signals -radix hex -add wave * -add wave sim:/ddr_tb/ddr_ctrl/* -force -freeze sim:/ddr_tb/areset 1 0 -run 10 ns -force -freeze sim:/ddr_tb/areset 0 0 -when sim:/ddr_tb/break_out stop -run 10 ms \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do deleted file mode 100644 index 31dd294..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/simscripts/ddr_top.do +++ /dev/null @@ -1,111 +0,0 @@ -vlib zylin -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_pkg.vhd -vcom -93 -explicit -work zylin ../ddrsdram/src/ddr_top.vhd -vlib work -vsim -t 1ps zylin.ddr_top -view wave -view signals -radix hex -# Add wave signals - -add wave -divider "System" -add wave sim:/ddr_top/areset -add wave sim:/ddr_top/cpu_clk -add wave sim:/ddr_top/cpu_clk_2x -add wave sim:/ddr_top/cpu_clk_4x -add wave sim:/ddr_top/ddr_in_clk -add wave sim:/ddr_top/ddr_in_clk_2x - -add wave -divider "Ctrl interface" -add wave sim:/ddr_top/cpu_clk -add wave sim:/ddr_top/ddr_data_read -add wave sim:/ddr_top/ddr_data_write -add wave sim:/ddr_top/ddr_req -add wave sim:/ddr_top/ddr_rd_wr_n -add wave sim:/ddr_top/ddr_req_len -add wave sim:/ddr_top/ddr_wr_mask -add wave sim:/ddr_top/ddr_read_en -add wave sim:/ddr_top/ddr_write_en -add wave sim:/ddr_top/ddr_command -add wave sim:/ddr_top/ddr_command_we - -add wave -divider "DDR interface" -add wave sim:/ddr_top/sdr_clk_p -add wave sim:/ddr_top/sdr_clk_n_p -add wave sim:/ddr_top/cke_q_p -add wave sim:/ddr_top/cs_qn_p -add wave sim:/ddr_top/ras_qn_p -add wave sim:/ddr_top/cas_qn_p -add wave sim:/ddr_top/we_qn_p -add wave sim:/ddr_top/dm_q_p -add wave sim:/ddr_top/dqs_q_p -add wave sim:/ddr_top/ba_q_p -add wave sim:/ddr_top/sdr_a_p -add wave sim:/ddr_top/sdr_d_p - -add wave -divider "Internal signals" -add wave sim:/ddr_top/clk2_phase -add wave sim:/ddr_top/clk4_phase -add wave sim:/ddr_top/ddr_state -add wave sim:/ddr_top/sdr_oe_n -add wave sim:/ddr_top/sdr_smp -add wave sim:/ddr_top/sdr_d - - -# Add input signals -force -freeze sim:/ddr_top/cpu_clk_4x 1 0, 0 {1.875 ns} -r 3.75 -run 100 ps -force -freeze sim:/ddr_top/cpu_clk_2x 1 0, 0 {3.75 ns} -r 7.5 -run 100 ps -force -freeze sim:/ddr_top/cpu_clk 1 0, 0 {7.5 ns} -r 15 -force -freeze sim:/ddr_top/ddr_in_clk 1 2ns, 0 {5.75 ns} -r 7.5 -force -freeze sim:/ddr_top/ddr_in_clk_2x 0 0.125ns, 1 {2 ns} -r 3.75 - -force -freeze sim:/ddr_top/areset 1 0 -force -freeze sim:/ddr_top/ddr_command 0000 0 -force -freeze sim:/ddr_top/ddr_command_we 0 0 -force -freeze sim:/ddr_top/ddr_data_write 1234abcd 0 -force -freeze sim:/ddr_top/ddr_req 0 0 -force -freeze sim:/ddr_top/ddr_req_adr 000000 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 - -# Start simulation -run 45 -force -freeze sim:/ddr_top/areset 0 0 -run 92 -# DDR Command -force -freeze sim:/ddr_top/ddr_command 000A 0 -force -freeze sim:/ddr_top/ddr_command_we 1 0 -run 15 -force -freeze sim:/ddr_top/ddr_command 0000 0 -force -freeze sim:/ddr_top/ddr_command_we 0 0 -run 90 -# DDR Read -force -freeze sim:/ddr_top/ddr_req 1 0 -force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 1 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 -run 15 -force -freeze sim:/ddr_top/ddr_req 0 0 -force -freeze sim:/ddr_top/ddr_req_adr 000000 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 -run 150 -# DDR Write -force -freeze sim:/ddr_top/ddr_req 1 0 -force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 -run 15 -force -freeze sim:/ddr_top/ddr_req 0 0 -force -freeze sim:/ddr_top/ddr_req_adr 000000 0 -force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 -force -freeze sim:/ddr_top/ddr_req_len 000 0 -force -freeze sim:/ddr_top/ddr_wr_mask 0 0 -run 180 - diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd deleted file mode 100644 index 95f4b8a..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_pkg.vhd +++ /dev/null @@ -1,90 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -package ddr is - - component ddr_top - generic( - simulate_io_time : boolean := false); - port ( -- Asyncronous reset and clocks - areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_clk_4x : in std_logic; - ddr_in_clk : in std_logic; - ddr_in_clk_2x : in std_logic; - - -- Command interface - ddr_command : in std_logic_vector(15 downto 0); - ddr_command_we : in std_logic; - refresh_en : in std_logic; - - - -- Data interface signals - ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM - ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM - ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address - ddr_req : in std_logic; -- Request DDR SDRAM access - ddr_req_ack : out std_logic; -- Request acknowledge - ddr_busy : out std_logic; -- Request acknowledge - ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE - ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) - ddr_read_en : out std_logic; -- Enable signal for read data - ddr_write_en : out std_logic; -- Enable (read) signal for data write - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus - end component; - - component MT46V16M16 - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - end component; - -end ddr; - \ No newline at end of file diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd deleted file mode 100644 index 5666532..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_tb.vhd +++ /dev/null @@ -1,301 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library zylin; -use zylin.ddr.all; - -entity ddr_tb is - port ( areset : in std_logic; - break_out : out std_logic); -end ddr_tb; - -architecture behave of ddr_tb is - -signal cpu_clk : std_logic; -signal cpu_clk_2x : std_logic; -signal cpu_clk_4x : std_logic; -signal ddr_in_clk : std_logic; -signal ddr_in_clk_2x : std_logic; - -signal ddr_command : std_logic_vector(15 downto 0); -signal ddr_command_we : std_logic; - -signal ddr_data_read : std_logic_vector(31 downto 0); -- Data read from DDR SDRAM -signal ddr_data_write : std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM -signal ddr_req_adr : std_logic_vector(23 downto 1); -- Request address -signal ddr_req : std_logic; -- Request DDR SDRAM access -signal ddr_req_ack : std_logic; -- Request acknowledge -signal ddr_busy : std_logic; -- Request acknowledge -signal ddr_rd_wr_n : std_logic; -- Access type 1=READ, 0=WRITE -signal ddr_req_len : std_logic; -- Number of 16-bits words to transfer -signal ddr_read_en : std_logic; -- Enable signal for read data -signal ddr_write_en : std_logic; -- Enable (read) signal for data write -signal refresh_en : std_logic; - -signal sdr_clk_p : std_logic; -- ddr_sdram_clock -signal sdr_clk_n_p : std_logic; -- /ddr_sdram_clock -signal cke_q_p : std_logic; -- clock enable -signal cs_qn_p : std_logic; -- /chip select -signal ras_qn_p : std_logic; -- /ras -signal cas_qn_p : std_logic; -- /cas -signal we_qn_p : std_logic; -- /write enable -signal dm_q_p : std_logic_vector(1 downto 0); -- data mask bits, set to "00" -signal dqs_q_p : std_logic_vector(1 downto 0); -- data strobe, only for write -signal ba_q_p : std_logic_vector(1 downto 0); -- bank select -signal sdr_a_p : std_logic_vector(12 downto 0); -- address bus -signal sdr_d_p : std_logic_vector(15 downto 0); -- bidir data bus - -constant min_time : time := 1.875 ns; - -begin - - clock1: - process - begin - loop - cpu_clk_4x <= '1'; - wait for min_time; - cpu_clk_4x <= '0'; - wait for min_time; - end loop; - end process; - - clock2: - process - begin - loop - cpu_clk_2x <= '1' after 100 ps; - wait until rising_edge(cpu_clk_4x); - cpu_clk_2x <= '0' after 100 ps; - wait until rising_edge(cpu_clk_4x); - end loop; - end process; - - clock3: - process - begin - loop - cpu_clk <= '1' after 100 ps; - wait until rising_edge(cpu_clk_2x); - cpu_clk <= '0' after 100 ps; - wait until rising_edge(cpu_clk_2x); - end loop; - end process; - - ddr_in_clk_2x <= cpu_clk_4x after 1 ns; - - clock4: - process - begin - loop - ddr_in_clk <= '0' after 100 ps; - wait until rising_edge(ddr_in_clk_2x); - ddr_in_clk <= '1' after 100 ps; - wait until rising_edge(ddr_in_clk_2x); - end loop; - end process; - - inputdata: - process - begin - -- Wait until global reset released - loop - ddr_command <= x"0000"; - ddr_command_we <= '0'; - ddr_data_write <= x"000000000"; - ddr_req <= '0'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '0'; - ddr_req_len <= '0'; - break_out <= '0'; - refresh_en <= '0'; - - wait until falling_edge(areset); - - -- DDR initialization sequence - -- Wait more than 200 us - wait for 201000 ns; - - -- Send precharge command - wait until rising_edge(cpu_clk); - ddr_command <= x"8000"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Wait for 1 us - wait for 1000 ns; - - -- Load extended mode register - -- Enable DLL - -- Normal drive strength - wait until rising_edge(cpu_clk); - ddr_command <= x"2000"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Wait for 1 us - wait for 1000 ns; - - -- Load mode register - -- Burst length: 2 - -- Burst type: Sequential - -- Cas latency: 2 - -- Reset DLL - wait until rising_edge(cpu_clk); - ddr_command <= x"0121"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Wait for 1 us - wait for 1000 ns; - - -- Send precharge command - wait until rising_edge(cpu_clk); - ddr_command <= x"8000"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Enable refresh - refresh_en <= '1'; - - -- Wait 30 us (minimum 2 autorefresh cycles) - wait for 30000 ns; - - -- Load mode register - -- Burst length: 2 - -- Burst type: Sequential - -- Cas latency: 2 - -- Deactivate Reset DLL - wait until rising_edge(cpu_clk); - ddr_command <= x"0021"; - ddr_command_we <= '1'; - wait until rising_edge(cpu_clk); - ddr_command <= x"0000"; - ddr_command_we <= '0'; - - -- Wait for 2 us (DLL stable) - wait for 2000 ns; - - -- Write data to DDR - wait until rising_edge(cpu_clk_2x); - ddr_data_write <= x"312345678"; - ddr_req <= '1'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '0'; - ddr_req_len <= '0'; - wait until rising_edge(ddr_write_en); - wait until rising_edge(cpu_clk_2x); - ddr_req <= '0'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '0'; - ddr_req_len <= '0'; - ddr_data_write <= x"000000000"; - wait for 100 ns; - - -- Read data from DDR - wait until rising_edge(cpu_clk_2x); - ddr_req <= '1'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '1'; - ddr_req_len <= '0'; - wait until rising_edge(ddr_req_ack); - wait until rising_edge(cpu_clk_2x); - ddr_req <= '0'; - ddr_req_adr <= "00000000000000000000000"; - ddr_rd_wr_n <= '0'; - ddr_req_len <= '0'; - ddr_data_write <= x"000000000"; - - - - wait for 100 ns; - break_out <= '1'; - wait for 100 ns; - - end loop; - - end process; - - ddr_ctrl: - ddr_top port map( - areset => areset, - cpu_clk => cpu_clk, - cpu_clk_2x => cpu_clk_2x, - cpu_clk_4x => cpu_clk_4x, - ddr_in_clk => ddr_in_clk, - ddr_in_clk_2x => ddr_in_clk_2x, - - -- Command interface - ddr_command => ddr_command, - ddr_command_we => ddr_command_we, - refresh_en => refresh_en, - - -- Data interface signals - ddr_data_read => ddr_data_read, - ddr_data_write => ddr_data_write, - ddr_req_adr => ddr_req_adr, - ddr_req => ddr_req, - ddr_req_ack => ddr_req_ack, - ddr_busy => ddr_busy, - ddr_rd_wr_n => ddr_rd_wr_n, - ddr_req_len => ddr_req_len, - ddr_read_en => ddr_read_en, - ddr_write_en => ddr_write_en, - -- DDR SDRAM Signals - sdr_clk_p => sdr_clk_p, - sdr_clk_n_p => sdr_clk_n_p, - cke_q_p => cke_q_p, - cs_qn_p => cs_qn_p, - ras_qn_p => ras_qn_p, - cas_qn_p => cas_qn_p, - we_qn_p => we_qn_p, - dm_q_p => dm_q_p, - dqs_q_p => dqs_q_p, - ba_q_p => ba_q_p, - sdr_a_p => sdr_a_p, - sdr_d_p => sdr_d_p); - - myram: - MT46V16M16 generic map( - tCK => 7.500 ns, - tCH => 3.375 ns, -- 0.45*tCK - tCL => 3.375 ns, -- 0.45*tCK - tDH => 0.500 ns, - tDS => 0.500 ns, - tIH => 0.900 ns, - tIS => 0.900 ns, - tMRD => 15.000 ns, - tRAS => 40.000 ns, - tRAP => 20.000 ns, - tRC => 65.000 ns, - tRFC => 75.000 ns, - tRCD => 20.000 ns, - tRP => 20.000 ns, - tRRD => 15.000 ns, - tWR => 15.000 ns, - addr_bits => 13, - data_bits => 16, - cols_bits => 9) - port map( - Dq => sdr_d_p, - Dqs => dqs_q_p, - Addr => sdr_a_p, - Ba => ba_q_p, - Clk => sdr_clk_p, - Clk_n => sdr_clk_n_p, - Cke => cke_q_p, - Cs_n => cs_qn_p, - Ras_n => ras_qn_p, - Cas_n => cas_qn_p, - We_n => we_qn_p, - Dm => dm_q_p); - -end behave; diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd deleted file mode 100644 index d5e98e1..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/ddr_top.vhd +++ /dev/null @@ -1,660 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity ddr_top is - generic( - simulate_io_time : boolean := false); - port ( -- Asyncronous reset and clocks - areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_clk_4x : in std_logic; - ddr_in_clk : in std_logic; - ddr_in_clk_2x : in std_logic; - - -- Command interface - ddr_command : in std_logic_vector(15 downto 0); - ddr_command_we : in std_logic; - refresh_en : in std_logic; - - -- Data interface signals - ddr_data_read : out std_logic_vector(31 downto 0); -- Data read from DDR SDRAM - ddr_data_write : in std_logic_vector(35 downto 0); -- Data to be written to DDR SDRAM - ddr_req_adr : in std_logic_vector(23 downto 1); -- Request address - ddr_req : in std_logic; -- Request DDR SDRAM access - ddr_req_ack : out std_logic; -- Request acknowledge - ddr_busy : out std_logic; -- Request acknowledge - ddr_rd_wr_n : in std_logic; -- Access type 1=READ, 0=WRITE - ddr_req_len : in std_logic; -- Number of 16-bits words to transfer (0=2, 1=8) - ddr_read_en : out std_logic; -- Enable signal for read data - ddr_write_en : out std_logic; -- Enable (read) signal for data write - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus -end ddr_top; - -architecture behave of ddr_top is - -attribute keep : string; - -signal cpu_clk_tog : std_logic; -signal ddr_cmd : std_logic_vector(15 downto 0); -signal ddr_cmd_we_smp : std_logic; -signal new_command : std_logic; - -signal cpu_clk_2x_smp1 : std_logic; -signal cpu_clk_2x_smp2 : std_logic; -signal cpu_clk_4x_smp1 : std_logic; -signal cpu_clk_4x_smp2 : std_logic; - -signal clk2_phase : std_logic; -signal clk4_phase : std_logic_vector(3 downto 0); -signal clk4_phase_short : std_logic_vector(1 downto 0); - -signal ddr_clk_tog : std_logic; -signal ddr_clk_smp1 : std_logic; -signal ddr_clk_smp2 : std_logic; -signal ddr_clk_phase : std_logic; - -signal smp_req_adr : std_logic_vector(23 downto 1); -signal smp_req_type : std_logic; -signal smp_req_len : std_logic; -signal ddr_write_en_int : std_logic; -signal ddr_read_en_int : std_logic; - -signal dqs_q : std_logic_vector(1 downto 0); -signal dqs_oe_n : std_logic_vector(1 downto 0); -attribute keep of dqs_oe_n:signal is "true"; -signal cas_qn : std_logic; -signal ras_qn : std_logic; -signal we_qn : std_logic; -signal ba_q : std_logic_vector(1 downto 0); -signal sdr_clk : std_logic; -signal sdr_clk_n : std_logic; -signal sdr_a : std_logic_vector(12 downto 0); -signal sdr_d : std_logic_vector(15 downto 0); -signal sdr_smp : std_logic_vector(35 downto 0); -signal sdr_oe_n : std_logic_vector(15 downto 0); -attribute keep of sdr_oe_n:signal is "true"; -signal sdr_oe_ctrl : std_logic; -signal sdr_wr_msw : std_logic_vector(17 downto 0); -attribute keep of sdr_wr_msw:signal is "true"; -signal dm_q : std_logic_vector(1 downto 0); - -signal cas_n_smp : std_logic; -signal ras_n_smp : std_logic; -signal we_n_smp : std_logic; -signal read_start_sig : std_logic; -signal sdr_d_in : std_logic_vector(15 downto 0); -signal read_time_cnt : std_logic_vector(1 downto 0); -signal read_input_en : std_logic; -signal ddr_data_read_int : std_logic_vector(31 downto 0); - -signal refresh_pend : std_logic; -signal refresh_end : std_logic; -signal refresh_cnt : std_logic_vector(9 downto 0); -signal refresh_wait_cnt : std_logic_vector(2 downto 0); -signal refresh_wait_end : std_logic; - -signal cas_qn_p_del : std_logic; -signal ras_qn_p_del : std_logic; -signal we_qn_p_del : std_logic; -signal sdr_d_p_del : std_logic_vector(15 downto 0); - -type state_type is (idle, act, act_nop1, act_nop2, rd_wr, rd_nop1, - rd_nop2, pre, pre_nop1, pre_nop2, wr_nop1, wr_nop2, - wr_nop3, cmd, cpu_pre, refresh, refresh_wait); -signal ddr_state : state_type; - -constant Clk_to_Output : time := 2.2 ns; -constant Sim_Delay : time := 0.5 ns; -constant Input_Setup : time := 2.5 ns; - -constant Refresh_Interval : std_logic_vector(9 downto 0) := "1111100110"; - -begin - - iotimingon: - if simulate_io_time generate - begin - cas_qn_p_del <= 'X' after 0 ns, cas_qn_p after Input_Setup; - ras_qn_p_del <= 'X' after 0 ns, ras_qn_p after Input_Setup; - we_qn_p_del <= 'X' after 0 ns, we_qn_p after Input_Setup; - sdr_d_p_del <= "XXXXXXXXXXXXXXXX" after 0 ns, sdr_d_p after Input_Setup; - end generate; - - iotimingoff: - if not simulate_io_time generate - begin - cas_qn_p_del <= cas_qn_p; - ras_qn_p_del <= ras_qn_p; - we_qn_p_del <= we_qn_p; - sdr_d_p_del <= sdr_d_p; - end generate; - - ddr_write_en <= ddr_write_en_int; - ddr_read_en <= ddr_read_en_int; - ddr_data_read <= ddr_data_read_int; - - process(cpu_clk, areset) -- Toggle a flip-flop with cpu_clk, in order - begin -- to find phase relation with 2x and 4x clocks - if areset = '1' then - cpu_clk_tog <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - cpu_clk_tog <= not(cpu_clk_tog) after Sim_Delay; - end if; - end process; - - process(cpu_clk_2x, areset) -- Find phase relation between cpu_clk and cpu_clk_2x - begin - if areset = '1' then - cpu_clk_2x_smp1 <= '0'; - cpu_clk_2x_smp2 <= '0'; - clk2_phase <= '0'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - cpu_clk_2x_smp1 <= cpu_clk_tog after Sim_Delay; - cpu_clk_2x_smp2 <= cpu_clk_2x_smp1 after Sim_Delay; - if (cpu_clk_2x_smp1 = '1' and cpu_clk_2x_smp2 = '0') then - clk2_phase <= '0' after Sim_Delay; - else - clk2_phase <= not(clk2_phase) after Sim_Delay; - end if; - end if; - end process; - - process(cpu_clk_4x, areset) -- Find phase relation between cpu_clk and cpu_clk_4x - begin - if areset = '1' then - cpu_clk_4x_smp1 <= '0'; - cpu_clk_4x_smp2 <= '0'; - clk4_phase <= "0000"; - clk4_phase_short <= "00"; - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - cpu_clk_4x_smp1 <= cpu_clk_tog after Sim_Delay; - cpu_clk_4x_smp2 <= cpu_clk_4x_smp1 after Sim_Delay; - if (cpu_clk_4x_smp1 = '1' and cpu_clk_4x_smp2 = '0') then - clk4_phase <= "0100" after Sim_Delay; - clk4_phase_short <= "01" after Sim_Delay; - else - clk4_phase <= (clk4_phase(2 downto 0) & clk4_phase(3)) after Sim_Delay; - clk4_phase_short <= clk4_phase_short(0) & clk4_phase_short(1); - end if; - end if; - end process; - - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - sdr_clk <= '0'; - sdr_clk_n <= '0'; - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - if clk4_phase_short(0) = '1' then - sdr_clk <= '1' after Sim_Delay; - else - sdr_clk <= '0' after Sim_Delay; - end if; - if clk4_phase_short(1) = '1' then - sdr_clk_n <= '1' after Sim_Delay; - else - sdr_clk_n <= '0' after Sim_Delay; - end if; - end if; - end process; - - cke_q_p <= '1' after Clk_to_Output; - cs_qn_p <= '0' after Clk_to_Output; - - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - ras_qn_p <= '1'; - cas_qn_p <= '1'; - we_qn_p <= '1'; - dqs_q_p <= "ZZ"; - sdr_a_p <= "0000000000000"; - ba_q_p <= "00"; - sdr_clk_p <= '0'; - sdr_clk_n_p <= '1'; - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - ras_qn_p <= transport ras_qn after Clk_to_Output; - cas_qn_p <= transport cas_qn after Clk_to_Output; - we_qn_p <= transport we_qn after Clk_to_Output; - if dqs_oe_n(0) = '0' then - dqs_q_p(0) <= transport dqs_q(0) after Clk_to_Output; - else - dqs_q_p(0) <= transport 'Z' after Clk_to_Output; - end if; - if dqs_oe_n(1) = '0' then - dqs_q_p(1) <= transport dqs_q(1) after Clk_to_Output; - else - dqs_q_p(1) <= transport 'Z' after Clk_to_Output; - end if; - sdr_a_p <= transport sdr_a after Clk_to_Output; - ba_q_p <= transport ba_q after Clk_to_Output; - sdr_clk_p <= transport sdr_clk after Clk_to_Output; - sdr_clk_n_p <= transport sdr_clk_n after Clk_to_Output; - end if; - end process; - - process(cpu_clk_2x, areset) -- - begin - if areset = '1' then - ddr_state <= idle; - ras_qn <= '1'; - cas_qn <= '1'; - we_qn <= '1'; - smp_req_adr <= (others => '0'); - smp_req_type <= '0'; - smp_req_len <= '0'; - sdr_a <= "XXXXXXXXXXXXX"; - ba_q <= "00"; - ddr_req_ack <= '0'; - ddr_busy <= '1'; - ddr_write_en_int <= '0'; - ddr_read_en_int <= '0'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - - -- Default values - ras_qn <= '1' after Sim_Delay; - cas_qn <= '1' after Sim_Delay; - we_qn <= '1' after Sim_Delay; - sdr_a <= "XXXXXXXXXXXXX" after Sim_Delay; - ba_q <= "00" after Sim_Delay; - ddr_req_ack <= '0' after Sim_Delay; - ddr_busy <= '1' after Sim_Delay; - ddr_write_en_int <= '0' after Sim_Delay; - ddr_read_en_int <= '0' after Sim_Delay; - - case ddr_state is - when idle => - smp_req_adr <= ddr_req_adr after Sim_Delay; - smp_req_type <= ddr_rd_wr_n after Sim_Delay; - smp_req_len <= ddr_req_len after Sim_Delay; - ddr_busy <= '0' after Sim_Delay; - if refresh_pend = '1' then - ddr_state <= refresh after Sim_Delay; - elsif new_command = '1' then - if ddr_cmd(15) = '1' then - ddr_state <= cpu_pre after Sim_Delay; - else - ddr_state <= cmd after Sim_Delay; - end if; - elsif ddr_req = '1' then - ddr_state <= act after Sim_Delay; - else - ddr_state <= idle after Sim_Delay; - end if; - when act => - sdr_a <= smp_req_adr(23 downto 11) after Sim_Delay; - ras_qn <= '0' after Sim_Delay; - ddr_state <= act_nop1 after Sim_Delay; - ddr_req_ack <= '1' after Sim_Delay; - ddr_write_en_int <= not(smp_req_type) after Sim_Delay; - when act_nop1 => - ddr_state <= act_nop2 after Sim_Delay; - when act_nop2 => - ddr_state <= rd_wr after Sim_Delay; - when rd_wr => - sdr_a(10) <= '0' after Sim_Delay; -- Disable auto precharge - sdr_a(9 downto 0) <= smp_req_adr(10 downto 1) after Sim_Delay; - cas_qn <= '0' after Sim_Delay; - we_qn <= smp_req_type after Sim_Delay; - if smp_req_type = '1' then - ddr_state <= rd_nop1 after Sim_Delay; - else - ddr_state <= wr_nop1 after Sim_Delay; - end if; - when wr_nop1 => - ddr_state <= wr_nop2 after Sim_Delay; - when wr_nop2 => - ddr_state <= wr_nop3 after Sim_Delay; - when wr_nop3 => - ddr_state <= pre after Sim_Delay; - when rd_nop1 => - ddr_state <= rd_nop2 after Sim_Delay; - when rd_nop2 => - ddr_state <= pre after Sim_Delay; - when pre => - ras_qn <= '0' after Sim_Delay; - we_qn <= '0' after Sim_Delay; - sdr_a(10) <= '1' after Sim_Delay; -- Precharge all banks - ddr_state <= pre_nop1 after Sim_Delay; - ddr_read_en_int <= smp_req_type after Sim_Delay; - when pre_nop1 => - ddr_state <= pre_nop2 after Sim_Delay; - when cmd => - cas_qn <= '0' after Sim_Delay; - ras_qn <= '0' after Sim_Delay; - we_qn <= '0' after Sim_Delay; - ba_q <= ddr_cmd(14 downto 13) after Sim_Delay; - sdr_a <= ddr_cmd(12 downto 0) after Sim_Delay; - ddr_state <= idle after Sim_Delay; - when cpu_pre => - ddr_state <= pre after Sim_Delay; - when refresh => - cas_qn <= '0' after Sim_Delay; - ras_qn <= '0' after Sim_Delay; - ddr_state <= refresh_wait after Sim_Delay; - when refresh_wait => - if refresh_wait_end = '1' then - ddr_state <= pre after Sim_Delay; - end if; - when pre_nop2 => - ddr_state <= idle after Sim_Delay; - when others => - ddr_state <= idle after Sim_Delay; - end case; - end if; - end process; - - process(cpu_clk, areset) -- - begin - if areset = '1' then - ddr_cmd <= "0000000000000000"; - elsif (cpu_clk'event and cpu_clk = '1') then - if ddr_command_we = '1' then - ddr_cmd <= ddr_command after Sim_Delay; - else - ddr_cmd <= ddr_cmd after Sim_Delay; - end if; - end if; - end process; - - process(cpu_clk_2x, areset) -- - begin - if areset = '1' then - ddr_cmd_we_smp <= '0'; - new_command <= '0'; - sdr_smp <= "000000000000000000000000000000000000"; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - ddr_cmd_we_smp <= ddr_command_we after Sim_Delay; - if ddr_command_we = '0' and ddr_cmd_we_smp = '1' then - new_command <= '1' after Sim_Delay; - elsif ddr_state = cmd or ddr_state = cpu_pre then - new_command <= '0' after Sim_Delay; - else - new_command <= new_command after Sim_Delay; - end if; - - if ddr_write_en_int = '1' then - sdr_smp <= ddr_data_write after Sim_Delay; - else - sdr_smp <= sdr_smp after Sim_Delay; - end if; - - end if; - end process; - - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - dqs_q <= "00"; - dqs_oe_n <= "11"; - sdr_oe_ctrl <= '1'; - sdr_wr_msw <= "000000000000000000"; - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - - if ddr_state = wr_nop1 and clk4_phase_short(0) = '1' then - sdr_oe_ctrl <= '0' after Sim_Delay; - elsif ddr_state = wr_nop3 and clk4_phase_short(0) = '1' then - sdr_oe_ctrl <= '1' after Sim_Delay; - else - sdr_oe_ctrl <= sdr_oe_ctrl after Sim_Delay; - end if; - - if ddr_state = idle or ddr_state = wr_nop3 then - dqs_oe_n <= "11" after Sim_Delay; - elsif ddr_state = wr_nop1 then - dqs_oe_n <= "00" after Sim_Delay; - else - dqs_oe_n <= dqs_oe_n after Sim_Delay; - end if; - - if (ddr_state = wr_nop2 and clk4_phase_short(0) = '1') then - dqs_q <= "11" after Sim_Delay; - else - dqs_q <= "00" after Sim_Delay; - end if; - - if ddr_state = wr_nop1 and clk4_phase_short(1) = '1' then - sdr_wr_msw <= "111111111111111111" after Sim_Delay; - else - sdr_wr_msw <= "000000000000000000" after Sim_Delay; - end if; - - end if; - end process; - - -- NOTE! DATA OUTPUT PATH. CLOCKED ON FALLING 4X CLOCK - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - sdr_d_p <= "ZZZZZZZZZZZZZZZZ"; - dm_q_p <= "11"; - sdr_oe_n <= "1111111111111111"; - sdr_d <= "0000000000000000"; - dm_q <= "11"; - elsif (cpu_clk_4x'event and cpu_clk_4x = '0') then - - for i in 0 to 15 loop - if sdr_oe_n(i) = '0' then - sdr_d_p(i) <= transport sdr_d(i) after Clk_to_Output; - else - sdr_d_p(i) <= transport 'Z' after Clk_to_Output; - end if; - end loop; - - dm_q_p <= transport dm_q after Clk_to_Output; - - if sdr_oe_ctrl = '0' then - sdr_oe_n <= "0000000000000000" after Sim_Delay; - else - sdr_oe_n <= "1111111111111111" after Sim_Delay; - end if; - - for i in 0 to 15 loop - if sdr_wr_msw(i) = '0' then - sdr_d(i) <= sdr_smp(i) after Sim_Delay; - else - sdr_d(i) <= sdr_smp(i+16) after Sim_Delay; - end if; - end loop; - - for i in 0 to 1 loop - if sdr_wr_msw(i+16) = '0' then - dm_q(i) <= sdr_smp(i+32) after Sim_Delay; - else - dm_q(i) <= sdr_smp(i+34) after Sim_Delay; - end if; - end loop; - - end if; - end process; - - process(cpu_clk_2x, areset) -- - begin - if areset = '1' then - refresh_cnt <= "0000000000"; - refresh_pend <= '0'; - refresh_end <= '0'; - refresh_wait_cnt <= "000"; - refresh_wait_end <= '0'; - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - - if refresh_cnt = Refresh_Interval then - refresh_end <= '1'; - else - refresh_end <= '0'; - end if; - - if refresh_end = '1' then - refresh_cnt <= "0000000000"; - else - refresh_cnt <= refresh_cnt + '1'; - end if; - - if refresh_end = '1' and refresh_en = '1' then - refresh_pend <= '1' after Sim_Delay; - elsif ddr_state = refresh then - refresh_pend <= '0' after Sim_Delay; - else - refresh_pend <= refresh_pend after Sim_Delay; - end if; - - if ddr_state = refresh_wait then - refresh_wait_cnt <= refresh_wait_cnt + '1'; - else - refresh_wait_cnt <= "000"; - end if; - - if refresh_wait_cnt = "111" then - refresh_wait_end <= '1' after Sim_Delay; - else - refresh_wait_end <= '0' after Sim_Delay; - end if; - - end if; - end process; - - -- 911. THIS IS A DUMMY FOR FGPA IMPEMENTATION TESTING - - process(ddr_in_clk, areset) - begin - if areset = '1' then - ddr_clk_tog <= '0'; - elsif (ddr_in_clk'event and ddr_in_clk = '1') then - ddr_clk_tog <= not(ddr_clk_tog) after Sim_Delay; - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - ddr_clk_smp1 <= '0'; - ddr_clk_smp2 <= '0'; - ddr_clk_phase <= '0'; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - ddr_clk_smp1 <= ddr_clk_tog after Sim_Delay; - ddr_clk_smp2 <= ddr_clk_smp1 after Sim_Delay; - if ddr_clk_smp1 = '1' and ddr_clk_smp2 = '0' then - ddr_clk_phase <= '0'; - else - ddr_clk_phase <= not(ddr_clk_phase); - end if; - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - cas_n_smp <= '0'; - ras_n_smp <= '0'; - we_n_smp <= '0'; - read_start_sig <= '0'; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - cas_n_smp <= cas_qn_p_del after Sim_Delay; - ras_n_smp <= ras_qn_p_del after Sim_Delay; - we_n_smp <= we_qn_p_del after Sim_Delay; - if ras_n_smp = '1' and cas_n_smp = '0' and we_n_smp = '1' and ddr_clk_phase = '1' then - read_start_sig <= '1' after Sim_Delay; - else - read_start_sig <= '0' after Sim_Delay; - end if; - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - sdr_d_in <= "0000000000000000"; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - sdr_d_in <= sdr_d_p_del after Sim_Delay; - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - read_time_cnt <= "00"; - read_input_en <= '0'; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - - if read_start_sig = '1' then - read_time_cnt <= "01" after Sim_Delay; - elsif read_time_cnt = "00" then - read_time_cnt <= read_time_cnt after Sim_Delay; - else - read_time_cnt <= read_time_cnt + '1' after Sim_Delay; - end if; - - if read_time_cnt = "11" then - read_input_en <= '1' after Sim_Delay; - else - read_input_en <= '0' after Sim_Delay; - end if; - - end if; - end process; - - process(ddr_in_clk_2x, areset) - begin - if areset = '1' then - ddr_data_read_int <= "00000000000000000000000000000000"; - elsif (ddr_in_clk_2x'event and ddr_in_clk_2x = '1') then - ddr_data_read_int(31 downto 16) <= "0000000000000000" after Sim_Delay; - if read_input_en = '1' then - ddr_data_read_int(15 downto 0) <= sdr_d_in after Sim_Delay; - else - ddr_data_read_int(15 downto 0) <= ddr_data_read_int(15 downto 0) after Sim_Delay; - end if; - end if; - end process; - - - - - - - - - -- ############### - - process(cpu_clk, areset) -- - begin - if areset = '1' then - elsif (cpu_clk'event and cpu_clk = '1') then - end if; - end process; - - - process(cpu_clk_2x, areset) -- - begin - if areset = '1' then - elsif (cpu_clk_2x'event and cpu_clk_2x = '1') then - end if; - end process; - - - process(cpu_clk_4x, areset) -- - begin - if areset = '1' then - elsif (cpu_clk_4x'event and cpu_clk_4x = '1') then - end if; - end process; - - -end behave; - - diff --git a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd b/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd deleted file mode 100644 index 6b89345..0000000 --- a/zpu/hdl/zpu4/dummyfpgalib/ddrsdram/src/mt46v16m16.vhd +++ /dev/null @@ -1,1320 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: MT46V16M16.VHD --- Version: 2.1 --- Date: January 14th, 2002 --- Model: Behavioral --- Simulator: NCDesktop - http://www.cadence.com --- ModelSim PE - http://www.model.com --- --- Dependencies: None --- --- Author: Son P. Huynh --- Email: sphuynh@micron.com --- Phone: (208) 368-3825 --- Company: Micron Technology, Inc. --- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) --- --- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) --- --- Limitation: Doesn't model internal refresh counter --- --- Note: --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 1998 Micron Semiconductor Products, Inc. --- All rights researved --- --- Rev Author Date Changes --- --- ---------------------------- ---------- ------------------------------------- --- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter --- Micron Technology, Inc. --- --- 2.0 Son P. Huynh 11/08/2001 - Second release --- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE --- ------------------------------------------------------------------------------------------ - -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_UNSIGNED.ALL; - USE IEEE.STD_LOGIC_ARITH.ALL; - -ENTITY MT46V16M16 IS - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END MT46V16M16; - -ARCHITECTURE behave OF MT46V16M16 IS - -- Array for Read pipeline - TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Write pipeline - TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Auto Precharge - TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; - - -- Array for Manual Precharge - TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Burst Terminate - TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Memory Access - TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - TYPE Array_ram_pntr IS ACCESS Array_ram_type; - TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; - - -- Data pair - SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); - SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); - - -- Mode Register - SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Command Decode Variables - SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; - SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; - - -- Burst Length Decode Variables - SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; - - -- Cas Latency Decode Variables - SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; - - -- Internal Control Signals - SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; - - -- System Clock - SIGNAL Sys_clk : STD_LOGIC := '0'; - - -- Dqs buffer - SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - -BEGIN - -- Strip the strength - Cs_in <= To_X01 (Cs_n); - Ras_in <= To_X01 (Ras_n); - Cas_in <= To_X01 (Cas_n); - We_in <= To_X01 (We_n); - - -- Commands Decode - Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; - Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; - Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); - Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); - Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); - Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); - Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; - Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); - - -- Burst Length Decode - Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); - Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); - Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - - -- CAS Latency Decode - Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); - Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); - Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); - - -- Dqs buffer - Dqs <= Dqs_out; - - -- - -- System Clock - -- - int_clk : PROCESS (Clk, Clk_n) - VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; - begin - IF Clk = '1' AND Clk_n = '0' THEN - ClkZ := '1'; - CkeZ := Cke; - ELSIF Clk = '0' AND Clk_n = '1' THEN - ClkZ := '0'; - END IF; - Sys_clk <= CkeZ AND ClkZ; - END PROCESS; - - -- - -- Main Process - -- - state_register : PROCESS - -- Precharge Variables - VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; - - -- Activate Variables - VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; - - -- Data IO variables - VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; - - -- Internal address mux variables - VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); - VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - - -- DLL Reset variables - VARIABLE DLL_enable : STD_LOGIC := '0'; - VARIABLE DLL_reset : STD_LOGIC := '0'; - VARIABLE DLL_done : STD_LOGIC := '0'; - VARIABLE DLL_count : INTEGER := 0; - - -- Timing Check - VARIABLE MRD_chk : TIME := 0 ns; - VARIABLE RFC_chk : TIME := 0 ns; - VARIABLE RRD_chk : TIME := 0 ns; - VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; - VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; - VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; - VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; - VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; - VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; - - -- Read pipeline variables - VARIABLE Read_cmnd : Array_Read_cmnd; - VARIABLE Read_bank : Array_Read_bank; - VARIABLE Read_cols : Array_Read_cols; - - -- Write pipeline variables - VARIABLE Write_cmnd : Array_Write_cmnd; - VARIABLE Write_bank : Array_Write_bank; - VARIABLE Write_cols : Array_Write_cols; - - -- Auto Precharge variables - VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); - - -- Manual Precharge variables - VARIABLE A10_precharge : Array_A10_precharge; - VARIABLE Bank_precharge : Array_Bank_precharge; - VARIABLE Cmnd_precharge : Array_Cmnd_precharge; - - -- Burst Terminate variable - VARIABLE Cmnd_bst : Array_Cmnd_bst; - - -- Memory Banks - VARIABLE Bank0 : Array_ram_stor; - VARIABLE Bank1 : Array_ram_stor; - VARIABLE Bank2 : Array_ram_stor; - VARIABLE Bank3 : Array_ram_stor; - - -- Burst Counter - VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Internal Dqs initialize - VARIABLE Dqs_int : STD_LOGIC := '0'; - - -- Data buffer for DM Mask - VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - - -- - -- Initialize empty rows - -- - PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS - VARIABLE i, j : INTEGER := 0; - BEGIN - IF Bank = "00" THEN - IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty - Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank0 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "01" THEN - IF Bank1 (Row_index) = NULL THEN - Bank1 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank1 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "10" THEN - IF Bank2 (Row_index) = NULL THEN - Bank2 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank2 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "11" THEN - IF Bank3 (Row_index) = NULL THEN - Bank3 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank3 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - END IF; - END; - - -- - -- Burst Counter - -- - PROCEDURE Burst_decode IS - VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); - BEGIN - -- Advance burst counter - Burst_counter := Burst_counter + 1; - - -- Burst Type - IF Mode_reg (3) = '0' THEN - Cols_temp := Cols_addr + 1; - ELSIF Mode_reg (3) = '1' THEN - Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); - Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); - Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); - END IF; - - -- Burst Length - IF Burst_length_2 = '1' THEN - Cols_addr (0) := Cols_temp (0); - ELSIF Burst_length_4 = '1' THEN - Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); - ELSIF Burst_length_8 = '1' THEN - Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); - ELSE - Cols_addr := Cols_temp; - END IF; - - -- Data counter - IF Burst_length_2 = '1' THEN - IF Burst_counter >= 2 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_4 = '1' THEN - IF Burst_counter >= 4 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_8 = '1' THEN - IF Burst_counter >= 8 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - END IF; - END; - - BEGIN - WAIT ON Sys_clk; - - -- - -- Manual Precharge Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- A10 Precharge Pipeline - A10_precharge(0) := A10_precharge(1); - A10_precharge(1) := A10_precharge(2); - A10_precharge(2) := A10_precharge(3); - A10_precharge(3) := A10_precharge(4); - A10_precharge(4) := A10_precharge(5); - A10_precharge(5) := A10_precharge(6); - A10_precharge(6) := A10_precharge(7); - A10_precharge(7) := A10_precharge(8); - A10_precharge(8) := '0'; - - -- Bank Precharge Pipeline - Bank_precharge(0) := Bank_precharge(1); - Bank_precharge(1) := Bank_precharge(2); - Bank_precharge(2) := Bank_precharge(3); - Bank_precharge(3) := Bank_precharge(4); - Bank_precharge(4) := Bank_precharge(5); - Bank_precharge(5) := Bank_precharge(6); - Bank_precharge(6) := Bank_precharge(7); - Bank_precharge(7) := Bank_precharge(8); - Bank_precharge(8) := "00"; - - -- Command Precharge Pipeline - Cmnd_precharge(0) := Cmnd_precharge(1); - Cmnd_precharge(1) := Cmnd_precharge(2); - Cmnd_precharge(2) := Cmnd_precharge(3); - Cmnd_precharge(3) := Cmnd_precharge(4); - Cmnd_precharge(4) := Cmnd_precharge(5); - Cmnd_precharge(5) := Cmnd_precharge(6); - Cmnd_precharge(6) := Cmnd_precharge(7); - Cmnd_precharge(7) := Cmnd_precharge(8); - Cmnd_precharge(8) := '0'; - - -- Terminate Read if same bank or all banks - IF ((Cmnd_precharge (0) = '1') AND - (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND - (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Burst Terminate Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Burst Terminate pipeline - Cmnd_bst (0) := Cmnd_bst (1); - Cmnd_bst (1) := Cmnd_bst (2); - Cmnd_bst (2) := Cmnd_bst (3); - Cmnd_bst (3) := Cmnd_bst (4); - Cmnd_bst (4) := Cmnd_bst (5); - Cmnd_bst (5) := Cmnd_bst (6); - Cmnd_bst (6) := Cmnd_bst (7); - Cmnd_bst (7) := Cmnd_bst (8); - Cmnd_bst (8) := '0'; - - -- Terminate current Read - IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Dq and Dqs Drivers - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Read Command Pipeline - Read_cmnd (0) := Read_cmnd (1); - Read_cmnd (1) := Read_cmnd (2); - Read_cmnd (2) := Read_cmnd (3); - Read_cmnd (3) := Read_cmnd (4); - Read_cmnd (4) := Read_cmnd (5); - Read_cmnd (5) := Read_cmnd (6); - Read_cmnd (6) := Read_cmnd (7); - Read_cmnd (7) := Read_cmnd (8); - Read_cmnd (8) := '0'; - - -- Read Bank Pipeline - Read_bank (0) := Read_bank (1); - Read_bank (1) := Read_bank (2); - Read_bank (2) := Read_bank (3); - Read_bank (3) := Read_bank (4); - Read_bank (4) := Read_bank (5); - Read_bank (5) := Read_bank (6); - Read_bank (6) := Read_bank (7); - Read_bank (7) := Read_bank (8); - Read_bank (8) := "00"; - - -- Read Column Pipeline - Read_cols (0) := Read_cols (1); - Read_cols (1) := Read_cols (2); - Read_cols (2) := Read_cols (3); - Read_cols (3) := Read_cols (4); - Read_cols (4) := Read_cols (5); - Read_cols (5) := Read_cols (6); - Read_cols (6) := Read_cols (7); - Read_cols (7) := Read_cols (8); - Read_cols (8) := (OTHERS => '0'); - - -- Initialize Read command - IF Read_cmnd (0) = '1' THEN - Data_out_enable := '1'; - Bank_addr := Read_bank (0); - Cols_addr := Read_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Toggle Dqs during Read command - IF Data_out_enable = '1' THEN - Dqs_int := '0'; - IF Dqs_out = "00" THEN - Dqs_out <= "11"; - ELSIF Dqs_out = "11" THEN - Dqs_out <= "00"; - ELSE - Dqs_out <= "00"; - END IF; - ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN - Dqs_out <= "ZZ"; - END IF; - - -- Initialize Dqs for Read command - IF Read_cmnd (2) = '1' THEN - IF Data_out_enable = '0' THEN - Dqs_int := '1'; - Dqs_out <= "00"; - END IF; - END IF; - - -- Read Latch - IF Data_out_enable = '1' THEN - -- Initialize Memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Output Data - CASE Bank_addr IS - WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Increase Burst Counter - Burst_decode; - ELSE - Dq <= (OTHERS => 'Z'); - END IF; - END IF; - - -- - -- Write FIFO and DM Mask Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Write command pipeline - Write_cmnd (0) := Write_cmnd (1); - Write_cmnd (1) := Write_cmnd (2); - Write_cmnd (2) := '0'; - - -- Write command pipeline - Write_bank (0) := Write_bank (1); - Write_bank (1) := Write_bank (2); - Write_bank (2) := "00"; - - -- Write column pipeline - Write_cols (0) := Write_cols (1); - Write_cols (1) := Write_cols (2); - Write_cols (2) := (OTHERS => '0'); - - -- Initialize Write command - IF Write_cmnd (0) = '1' THEN - Data_in_enable := '1'; - Bank_addr := Write_bank (0); - Cols_addr := Write_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Write data - IF Data_in_enable = '1' THEN - -- Initialize memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Write first data - IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (0) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); - END IF; - IF Dm_pair (1) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- Write second data - IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (2) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); - END IF; - IF Dm_pair (3) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- tWR start and tWTR check - IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN - CASE Bank_addr IS - WHEN "00" => WR_chk0 := NOW; - WHEN "01" => WR_chk1 := NOW; - WHEN "10" => WR_chk2 := NOW; - WHEN OTHERS => WR_chk3 := NOW; - END CASE; - - -- tWTR check - ASSERT (Read_enable = '0') - REPORT "tWTR violation during Read" - SEVERITY WARNING; - END IF; - END IF; - END IF; - - -- - -- Auto Precharge Calculation - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Precharge counter - IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN - Count_precharge (0) := Count_precharge (0) + 1; - END IF; - IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN - Count_precharge (1) := Count_precharge (1) + 1; - END IF; - IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN - Count_precharge (2) := Count_precharge (2) + 1; - END IF; - IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN - Count_precharge (3) := Count_precharge (3) + 1; - END IF; - - -- Read with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. BL/2 cycles after command - IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW; - Read_precharge(0) := '0'; - END IF; - END IF; - IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW; - Read_precharge(1) := '0'; - END IF; - END IF; - IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW; - Read_precharge(2) := '0'; - END IF; - END IF; - IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW; - Read_precharge(3) := '0'; - END IF; - END IF; - - -- Write with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. Two clock after last burst - -- Since tWR is time base, the model will compensate tRP - IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW - ((2 * tCK) - tWR); - Write_precharge(0) := '0'; - END IF; - END IF; - IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW - ((2 * tCK) - tWR); - Write_precharge(1) := '0'; - END IF; - END IF; - IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW - ((2 * tCK) - tWR); - Write_precharge(2) := '0'; - END IF; - END IF; - IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW - ((2 * tCK) - tWR); - Write_precharge(3) := '0'; - END IF; - END IF; - END IF; - - -- - -- DLL Counter - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - IF (DLL_Reset = '1' AND DLL_done = '0') THEN - DLL_count := DLL_count + 1; - IF (DLL_count >= 200) THEN - DLL_done := '1'; - END IF; - END IF; - END IF; - - -- - -- Control Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Auto Refresh - IF Aref_enable = '1' THEN - -- Auto Refresh to Auto Refresh - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All banks must be Precharge before Auto Refresh" - SEVERITY WARNING; - - -- Record current tRFC time - RFC_chk := NOW; - END IF; - - -- Extended Load Mode Register - IF Ext_mode_enable = '1' THEN - IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN - IF (Addr (0) = '0') THEN - DLL_enable := '1'; - ELSE - DLL_enable := '0'; - END IF; - END IF; - - -- Precharge to EMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Extended Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Extended Load Register" - SEVERITY WARNING; - - -- LMR/EMR to EMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Extended Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Load Mode Register - IF Mode_reg_enable = '1' THEN - -- Register mode - Mode_reg <= Addr; - - -- DLL Reset - IF (DLL_enable = '1' AND Addr (8) = '1') THEN - DLL_reset := '1'; - DLL_done := '0'; - DLL_count := 0; - ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN - ASSERT (FALSE) - REPORT "DLL is ENABLE: DLL RESET is require" - SEVERITY WARNING; - ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN - ASSERT (FALSE) - REPORT "DLL is DISABLE: DLL RESET will be ignored" - SEVERITY WARNING; - END IF; - - -- Precharge to LMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Load Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Load Mode Register" - SEVERITY WARNING; - - -- LMR/ELMR to LMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid Burst Length - ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 - (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 - (Addr (2 DOWNTO 0) = "011")) -- BL = 8 - REPORT "Invalid Burst Length during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid CAS Latency - ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 - (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 - REPORT "Invalid CAS Latency during Load Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Active Block (latch Bank and Row Address) - IF Active_enable = '1' THEN - -- Activate an OPEN bank can corrupt data - ASSERT ((Ba = "00" AND Act_b0 = '0') OR - (Ba = "01" AND Act_b1 = '0') OR - (Ba = "10" AND Act_b2 = '0') OR - (Ba = "11" AND Act_b3 = '0')) - REPORT "Bank is already activated - data can be corrupted" - SEVERITY WARNING; - - -- Activate Bank 0 - IF Ba = "00" AND Pc_b0 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk0 >= tRC) - REPORT "tRC violation during Activate Bank 0" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk0 >= tRP) - REPORT "tRP violation during Activate Bank 0" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b0 := '1'; - Pc_b0 := '0'; - B0_row_addr := Addr; - RC_chk0 := NOW; - RCD_chk0 := NOW; - RAS_chk0 := NOW; - RAP_chk0 := NOW; - END IF; - - -- Activate Bank 1 - IF Ba = "01" AND Pc_b1 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk1 >= tRC) - REPORT "tRC violation during Activate Bank 1" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk1 >= tRP) - REPORT "tRP violation during Activate Bank 1" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b1 := '1'; - Pc_b1 := '0'; - B1_row_addr := Addr; - RC_chk1 := NOW; - RCD_chk1 := NOW; - RAS_chk1 := NOW; - RAP_chk1 := NOW; - END IF; - - -- Activate Bank 2 - IF Ba = "10" AND Pc_b2 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk2 >= tRC) - REPORT "tRC violation during Activate Bank 2" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk2 >= tRP) - REPORT "tRP violation during Activate Bank 2" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b2 := '1'; - Pc_b2 := '0'; - B2_row_addr := Addr; - RC_chk2 := NOW; - RCD_chk2 := NOW; - RAS_chk2 := NOW; - RAP_chk2 := NOW; - END IF; - - -- Activate Bank 3 - IF Ba = "11" AND Pc_b3 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk3 >= tRC) - REPORT "tRC violation during Activate Bank 3" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk3 >= tRP) - REPORT "tRP violation during Activate Bank 3" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b3 := '1'; - Pc_b3 := '0'; - B3_row_addr := Addr; - RC_chk3 := NOW; - RCD_chk3 := NOW; - RAS_chk3 := NOW; - RAP_chk3 := NOW; - END IF; - - -- Activate Bank A to Activate Bank B - IF (Prev_bank /= Ba) THEN - ASSERT (NOW - RRD_chk >= tRRD) - REPORT "tRRD violation during Activate" - SEVERITY WARNING; - END IF; - - -- AutoRefresh to Activate - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Activate" - SEVERITY WARNING; - - -- Record Variables for Checking Violation - RRD_chk := NOW; - Prev_bank := Ba; - END IF; - - -- Precharge Block - Consider NOP if bank already precharged or in process of precharging - IF Prech_enable = '1' THEN - -- EMR or LMR to Precharge - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Precharge" - SEVERITY WARNING; - - -- Precharge Bank 0 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN - Act_b0 := '0'; - Pc_b0 := '1'; - RP_chk0 := NOW; - - -- Activate to Precharge bank 0 - ASSERT (NOW - RAS_chk0 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk0 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 1 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN - Act_b1 := '0'; - Pc_b1 := '1'; - RP_chk1 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk1 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk1 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 2 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN - Act_b2 := '0'; - Pc_b2 := '1'; - RP_chk2 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk2 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk2 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 3 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN - Act_b3 := '0'; - Pc_b3 := '1'; - RP_chk3 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk3 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk3 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Pipeline for READ - IF CAS_latency_15 = '1' THEN - A10_precharge (3) := Addr(10); - Bank_precharge (3) := Ba; - Cmnd_precharge (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - A10_precharge (4) := Addr(10); - Bank_precharge (4) := Ba; - Cmnd_precharge (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - A10_precharge (5) := Addr(10); - Bank_precharge (5) := Ba; - Cmnd_precharge (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - A10_precharge (6) := Addr(10); - Bank_precharge (6) := Ba; - Cmnd_precharge (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - A10_precharge (8) := Addr(10); - Bank_precharge (8) := Ba; - Cmnd_precharge (8) := '1'; - END IF; - END IF; - - -- Burst Terminate - IF Burst_term = '1' THEN - -- Pipeline for Read - IF CAS_latency_15 = '1' THEN - Cmnd_bst (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - Cmnd_bst (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - Cmnd_bst (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - Cmnd_bst (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - Cmnd_bst (8) := '1'; - END IF; - - -- Terminate Write - ASSERT (Data_in_enable = '0') - REPORT "It's illegal to Burst Terminate a Write" - SEVERITY WARNING; - - -- Terminate Read with Auto Precharge - ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND - Read_precharge (2) = '0' AND Read_precharge (3) = '0') - REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" - SEVERITY WARNING; - END IF; - - -- Read Command - IF Read_enable = '1' THEN - -- CAS Latency Pipeline - IF Cas_latency_15 = '1' THEN - Read_cmnd (3) := '1'; - Read_bank (3) := Ba; - Read_cols (3) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_2 = '1' THEN - Read_cmnd (4) := '1'; - Read_bank (4) := Ba; - Read_cols (4) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_25 = '1' THEN - Read_cmnd (5) := '1'; - Read_bank (5) := Ba; - Read_cols (5) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_3 = '1' THEN - Read_cmnd (6) := '1'; - Read_bank (6) := Ba; - Read_cols (6) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_4 = '1' THEN - Read_cmnd (8) := '1'; - Read_bank (8) := Ba; - Read_cols (8) := Addr (8 DOWNTO 0); - END IF; - - -- Write to Read: Terminate Write Immediately - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - END IF; - - -- Interrupting a Read with Auto Precharge (same bank only) - ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Read with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Read - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Read" - SEVERITY WARNING; - - -- Activate to Read without Auto Precharge - IF Addr (10) = '0' THEN - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Read" - SEVERITY WARNING; - END IF; - - -- Activate to Read with Auto Precharge - IF Addr (10) = '1' THEN - ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR - (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR - (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR - (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) - REPORT "tRAP violation during Read" - SEVERITY WARNING; - END IF; - - -- Auto precharge - IF Addr (10) = '1' THEN - Read_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - - -- DLL Check - IF (DLL_reset = '1') THEN - ASSERT (DLL_done = '1') - REPORT "DLL RESET not complete" - SEVERITY WARNING; - END IF; - END IF; - - -- Write Command - IF Write_enable = '1' THEN - -- Pipeline for Write - Write_cmnd (2) := '1'; - Write_bank (2) := Ba; - Write_cols (2) := Addr (8 DOWNTO 0); - - -- Interrupting a Write with Auto Precharge (same bank only) - ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Write with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Write" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Write" - SEVERITY WARNING; - - -- Auto precharge - IF Addr (10) = '1' THEN - Write_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - END IF; - END IF; - END PROCESS; - - -- - -- Dqs Receiver - -- - dqs_rcvrs : PROCESS - VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); - VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - BEGIN - WAIT ON Dqs; - -- Latch data at posedge Dqs - IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN - Dq_temp := Dq; - Dm_temp := Dm; - END IF; - -- Latch data at negedge Dqs - IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN - Dq_pair <= (Dq & Dq_temp); - Dm_pair <= (Dm & Dm_temp); - END IF; - END PROCESS; - - -- - -- Setup timing checks - -- - Setup_check : PROCESS - BEGIN - WAIT ON Sys_clk; - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIS) - REPORT "CKE Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIS) - REPORT "CS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIS) - REPORT "CAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIS) - REPORT "RAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIS) - REPORT "WE# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIS) - REPORT "ADDR Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIS) - REPORT "BA Setup time violation -- tIS" - SEVERITY WARNING; - END IF; - END PROCESS; - - -- - -- Hold timing checks - -- - Hold_check : PROCESS - BEGIN - WAIT ON Sys_clk'DELAYED (tIH); - IF Sys_clk'DELAYED (tIH) = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIH) - REPORT "CKE Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIH) - REPORT "CS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIH) - REPORT "CAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIH) - REPORT "RAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIH) - REPORT "WE# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIH) - REPORT "ADDR Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIH) - REPORT "BA Hold time violation -- tIH" - SEVERITY WARNING; - END IF; - END PROCESS; - -END behave; diff --git a/zpu/hdl/zpu4/src/build.xml b/zpu/hdl/zpu4/src/build.xml deleted file mode 100644 index e1b268a..0000000 --- a/zpu/hdl/zpu4/src/build.xml +++ /dev/null @@ -1,114 +0,0 @@ - - - - - - - eCosBoard firmware build file - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/ic300.bitgen b/zpu/hdl/zpu4/src/ic300.bitgen deleted file mode 100644 index 1095099..0000000 --- a/zpu/hdl/zpu4/src/ic300.bitgen +++ /dev/null @@ -1,27 +0,0 @@ --g DebugBitstream:No --g Binary:yes --g CRC:Enable --g ConfigRate:50 --g CclkPin:Pullnone --g M0Pin:Pullnone --g M1Pin:Pullnone --g M2Pin:Pullnone --g ProgPin:PullUp --g DonePin:Pullnone --g TckPin:Pullnone --g TdiPin:Pullnone --g TdoPin:Pullnone --g TmsPin:Pullnone --g UnusedPin:Pullnone --g UserID:0xFFFFFFFF --g DCMShutDown:Disable --g DCIUpdateMode:AsRequired --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:Level1 --g DonePipe:No --g DriveDone:Yes - diff --git a/zpu/hdl/zpu4/src/ic300.lso b/zpu/hdl/zpu4/src/ic300.lso deleted file mode 100644 index 22de730..0000000 --- a/zpu/hdl/zpu4/src/ic300.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/zpu/hdl/zpu4/src/ic300.ucf b/zpu/hdl/zpu4/src/ic300.ucf deleted file mode 100644 index 4a141b9..0000000 --- a/zpu/hdl/zpu4/src/ic300.ucf +++ /dev/null @@ -1,146 +0,0 @@ -# clock inputs -net "cpu_clk_p" loc = "R9" | iostandard=LVTTL; - -# input pins -net "cpu_a_p(0)" loc = "N15" | iostandard=LVTTL; -net "cpu_a_p(1)" loc = "P16" | iostandard=LVTTL; -net "cpu_a_p(2)" loc = "P13" | iostandard=LVTTL; -net "cpu_a_p(3)" loc = "N16" | iostandard=LVTTL; -net "cpu_a_p(4)" loc = "P15" | iostandard=LVTTL; -net "cpu_a_p(5)" loc = "R11" | iostandard=LVTTL; -net "cpu_a_p(6)" loc = "T14" | iostandard=LVTTL; -net "cpu_a_p(7)" loc = "R16" | iostandard=LVTTL; -net "cpu_a_p(8)" loc = "P14" | iostandard=LVTTL; -net "cpu_a_p(9)" loc = "T13" | iostandard=LVTTL; -net "cpu_a_p(10)" loc = "R13" | iostandard=LVTTL; -net "cpu_a_p(11)" loc = "P7" | iostandard=LVTTL; -net "cpu_a_p(12)" loc = "N12" | iostandard=LVTTL; -net "cpu_a_p(13)" loc = "R12" | iostandard=LVTTL; -net "cpu_a_p(14)" loc = "L13" | iostandard=LVTTL; -net "cpu_a_p(15)" loc = "K12" | iostandard=LVTTL; -net "cpu_a_p(16)" loc = "K15" | iostandard=LVTTL; -net "cpu_a_p(17)" loc = "T10" | iostandard=LVTTL; -net "cpu_a_p(18)" loc = "T9" | iostandard=LVTTL; -net "cpu_a_p(19)" loc = "N10" | iostandard=LVTTL; -net "cpu_a_p(20)" loc = "T8" | iostandard=LVTTL; -net "cpu_wr_n_p(0)" loc = "L15" | iostandard=LVTTL; -net "cpu_wr_n_p(1)" loc = "N14" | iostandard=LVTTL; -net "cpu_oe_n_p" loc = "T12" | iostandard=LVTTL; -net "cpu_cs_n_p(1)" loc = "R3" | iostandard=LVTTL; -net "cpu_cs_n_p(2)" loc = "M16" | iostandard=LVTTL; -net "cpu_cs_n_p(3)" loc = "P11" | iostandard=LVTTL; - -#net "sdr_clk_fb_p" loc = "B8" | iostandard=SSTL2_I; - -# output pins -net "cpu_fiq_p" loc = "K16" | iostandard=LVTTL; -net "cpu_irq_p(0)" loc = "M14" | iostandard=LVTTL; -net "cpu_irq_p(1)" loc = "J16" | iostandard=LVTTL; -net "cpu_wait_n_p" loc = "M15" | iostandard=LVTTL; - -#net "sdr_clk_p" loc = "D8" | iostandard=SSTL2_I | FAST; -#net "sdr_clk_n_p" loc = "F5" | iostandard=SSTL2_I | FAST; -#net "cke_q_p" loc = "F4" | iostandard=SSTL2_I | FAST; -#net "cs_qn_p" loc = "M2" | iostandard=SSTL2_I | FAST | PULLUP; -#net "ras_qn_p" loc = "J2" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; -#net "cas_qn_p" loc = "M3" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; -#net "we_qn_p" loc = "K4" | iostandard=SSTL2_I | FAST | PULLUP | NODELAY; -#net "dm_q_p(0)" loc = "L4" | iostandard=SSTL2_I | FAST; -#net "dm_q_p(1)" loc = "E4" | iostandard=SSTL2_I | FAST; -#net "dqs_q_p(0)" loc = "L3" | iostandard=SSTL2_I | FAST; -#net "dqs_q_p(1)" loc = "D3" | iostandard=SSTL2_I | FAST; -#net "ba_q_p(0)" loc = "M1" | iostandard=SSTL2_I | FAST; -#net "ba_q_p(1)" loc = "J3" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(0)" loc = "J4" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(1)" loc = "N2" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(2)" loc = "H4" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(3)" loc = "P2" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(4)" loc = "E7" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(5)" loc = "G4" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(6)" loc = "D7" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(7)" loc = "G5" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(8)" loc = "C7" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(9)" loc = "F3" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(10)" loc = "N3" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(11)" loc = "E6" | iostandard=SSTL2_I | FAST; -#net "sdr_a_p(12)" loc = "D6" | iostandard=SSTL2_I | FAST; - -# bidirectional pins -net "cpu_d_p(0)" loc = "M11" | iostandard=LVTTL; -net "cpu_d_p(1)" loc = "N11" | iostandard=LVTTL; -net "cpu_d_p(2)" loc = "P10" | iostandard=LVTTL; -net "cpu_d_p(3)" loc = "R10" | iostandard=LVTTL; -net "cpu_d_p(4)" loc = "T7" | iostandard=LVTTL; -net "cpu_d_p(5)" loc = "R7" | iostandard=LVTTL; -net "cpu_d_p(6)" loc = "N6" | iostandard=LVTTL; -net "cpu_d_p(7)" loc = "M6" | iostandard=LVTTL; -net "cpu_d_p(8)" loc = "K13" | iostandard=LVTTL; -net "cpu_d_p(9)" loc = "M10" | iostandard=LVTTL; -net "cpu_d_p(10)" loc = "L12" | iostandard=LVTTL; -net "cpu_d_p(11)" loc = "M13" | iostandard=LVTTL; -net "cpu_d_p(12)" loc = "K14" | iostandard=LVTTL; -net "cpu_d_p(13)" loc = "L14" | iostandard=LVTTL; -net "cpu_d_p(14)" loc = "J13" | iostandard=LVTTL; -net "cpu_d_p(15)" loc = "J14" | iostandard=LVTTL; - -#net "sdr_d_p(0)" loc = "G1" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(1)" loc = "H3" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(2)" loc = "G3" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(3)" loc = "K2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(4)" loc = "F2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(5)" loc = "L2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(6)" loc = "E1" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(7)" loc = "M4" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(8)" loc = "C6" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(9)" loc = "E2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(10)" loc = "C2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(11)" loc = "D1" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(12)" loc = "B7" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(13)" loc = "D2" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(14)" loc = "B6" | iostandard=SSTL2_I | NODELAY | FAST; -#net "sdr_d_p(15)" loc = "B5" | iostandard=SSTL2_I | NODELAY | FAST; - -# TIMING -# Create timing names -NET "cpu_clk_p" TNM_NET = "cpu_clk_p"; -NET "sdr_clk_fb_p" TNM_NET = "sdr_clk_fb_p"; -#NET "cpu_clk" TNM_NET = "cpu_clk"; -#NET "cpu_clk_2x" TNM_NET = "cpu_clk_2x"; -#NET "cpu_clk_4x" TNM_NET = "cpu_clk_4x"; -#NET "ddr_in_clk" TNM_NET = "ddr_in_clk"; -#NET "ddr_in_clk_2x" TNM_NET = "ddr_in_clk_2x"; - -## Create timing - -# Periode timing -TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk_p" 10 ns HIGH 50 %; -#TIMESPEC "TS_sdr_clk_fb_p" = PERIOD "sdr_clk_fb_p" 7.8 ns HIGH 50 %; - -# Clock domain crossing timing -#TIMESPEC "TS_cpu1_to_cpu2" = FROM "cpu_clk" TO "cpu_clk_2x" 7.8 ns; -#TIMESPEC "TS_cpu1_to_cpu4" = FROM "cpu_clk" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_cpu1_to_ddr2" = FROM "cpu_clk" TO "ddr_in_clk" 7.8 ns; -#TIMESPEC "TS_cpu1_to_ddr2_2x" = FROM "cpu_clk" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_cpu2_to_cpu1" = FROM "cpu_clk_2x" TO "cpu_clk" 7.8 ns; -#TIMESPEC "TS_cpu2_to_cpu4" = FROM "cpu_clk_2x" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_cpu2_to_ddr2" = FROM "cpu_clk_2x" TO "ddr_in_clk" 7.8 ns; -#TIMESPEC "TS_cpu2_to_ddr_2x" = FROM "cpu_clk_2x" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_cpu4_to_cpu1" = FROM "cpu_clk_4x" TO "cpu_clk" 3.9 ns; -#TIMESPEC "TS_cpu4_to_cpu2" = FROM "cpu_clk_4x" TO "cpu_clk_2x" 3.9 ns; -#TIMESPEC "TS_cpu4_to_ddr2" = FROM "cpu_clk_4x" TO "ddr_in_clk" 3.9 ns; -#TIMESPEC "TS_cpu4_to_ddr2_2x" = FROM "cpu_clk_4x" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_ddr2_to_cpu1" = FROM "ddr_in_clk" TO "cpu_clk" 7.8 ns; -#TIMESPEC "TS_ddr2_to_cpu2" = FROM "ddr_in_clk" TO "cpu_clk_2x" 7.8 ns; -#TIMESPEC "TS_ddr2_to_cpu4" = FROM "ddr_in_clk" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_ddr2_to_ddr2_2x" = FROM "ddr_in_clk" TO "ddr_in_clk_2x" 3.9 ns; - -#TIMESPEC "TS_ddr2_2x_to_cpu1" = FROM "ddr_in_clk_2x" TO "cpu_clk" 3.9 ns; -#TIMESPEC "TS_ddr2_2x_to_cpu2" = FROM "ddr_in_clk_2x" TO "cpu_clk_2x" 3.9 ns; -#TIMESPEC "TS_ddr2_2x_to_cpu4" = FROM "ddr_in_clk_2x" TO "cpu_clk_4x" 3.9 ns; -#TIMESPEC "TS_ddr2_2x_to_ddr2" = FROM "ddr_in_clk_2x" TO "ddr_in_clk" 3.9 ns; - - - diff --git a/zpu/hdl/zpu4/src/ic300.vhd b/zpu/hdl/zpu4/src/ic300.vhd deleted file mode 100644 index a1b4f41..0000000 --- a/zpu/hdl/zpu4/src/ic300.vhd +++ /dev/null @@ -1,144 +0,0 @@ --------------------------------------------------------------------------------- --- Company: Zylin AS --- Engineer: Tore Ramsland --- --- Create Date: 21:47:41 07/03/05 --- Design Name: ic300 --- Module Name: ic300 - behave --- Project Name: eCosBoard --- Target Device: XC3S400400-FG256 --- Tool versions: 7.1i --- Description: Top level --- --- Dependencies: --- --- Revision: --- 2005-07-11 Updated to test FPGA --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library zylin; -use zylin.arm7.all; - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -library work; -use work.phi_config.all; -use work.ic300pkg.all; - -entity ic300 is - generic( - simulate_io_time : boolean := false); - port ( -- Clock inputs - cpu_clk_p : in std_logic; - - -- CPU interface signals - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus - sdr_clk_fb_p : in std_logic -- DDR clock feedback - ); -end ic300; - -architecture behave of ic300 is - -signal cpu_we : std_logic_vector(1 downto 0); -- Write signal for lower(0) and upper(1) 8 data bits -signal cpu_re : std_logic; -- Read enable signal for all 16 bits -signal areset : std_logic; -- Asyncronous active high reset (for initialization) -signal areset_dummy : std_logic; - --- Clock module signals -signal clk_status : std_logic_vector(2 downto 0); -- DLL lock status (from 3 DLL's) -signal cpu_clk : std_logic; -- 64 MHz CPU clk -signal cpu_clk_2x : std_logic; -- 128 MHz CPU clk (in phase with 64 MHz) -signal cpu_clk_4x : std_logic; -- 256 MHz CPU clk (in phase with 64 MHz) -signal ddr_in_clk : std_logic; -- 128 MHz clock from DDR SDRAM -signal ddr_in_clk_2x : std_logic; -- 256 MHz clock from DDR SDRAM - -- NOTE! Phase relation to 64 MHz clock unknown - --- Internal CPU interface signals -signal cpu_din : std_logic_vector(15 downto 0); -- 16-bit data from CPU -signal cpu_dout : std_logic_vector(15 downto 0); -- 16-bit data to CPU -signal cpu_a : std_logic_vector(20 downto 0); -- 21-bit address from CPU - -begin - --- areset <= '0'; - areset_dummy <= '0'; - - global_init_reset: - rocbuf port map(I=>areset_dummy,O=>areset); - - allclocks: - clocks port map( - areset => areset, - cpu_clk_p => cpu_clk_p, - cpu_clk => cpu_clk, - cpu_clk_2x => cpu_clk_2x, - cpu_clk_4x => cpu_clk_4x, - sdr_clk_fb_p => sdr_clk_fb_p, - ddr_in_clk => ddr_in_clk, - ddr_in_clk_2x => ddr_in_clk_2x, - locked => clk_status); - - arm7cpu: - arm7wb generic map (simulate_io_time => simulate_io_time) - port map( - areset => areset, - cpu_clk => cpu_clk, - cpu_clk_2x => cpu_clk_2x, - cpu_a_p => cpu_a_p, - cpu_wr_n_p => cpu_wr_n_p, - cpu_cs_n_p => cpu_cs_n_p, - cpu_oe_n_p => cpu_oe_n_p, - cpu_d_p => cpu_d_p, - cpu_irq_p => cpu_irq_p, - cpu_fiq_p => cpu_fiq_p, - cpu_wait_n_p => cpu_wait_n_p, - cpu_din => cpu_din, - cpu_a => cpu_a, - cpu_we => cpu_we, - cpu_re => cpu_re, - cpu_dout => cpu_dout); - - - cpu_fpga_regs: - zpuio port map( - areset => areset, - cpu_clk => cpu_clk, - clk_status => clk_status, - cpu_din => cpu_din, - cpu_a => cpu_a, - cpu_we => cpu_we, - cpu_re => cpu_re, - cpu_dout => cpu_dout); - - -end behave; diff --git a/zpu/hdl/zpu4/src/ic300_config.vhd b/zpu/hdl/zpu4/src/ic300_config.vhd deleted file mode 100644 index b14ec79..0000000 --- a/zpu/hdl/zpu4/src/ic300_config.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -package phi_config is - - constant Fpga_Global_Base : std_logic_vector(19 downto 17) := "000"; -- 0x0800.... - constant Clock_Stat_Reg_Addr : std_logic_vector(5 downto 2) := "0000"; -- 0x....0000 - constant Ctrl_Reg_Addr : std_logic_vector(5 downto 2) := "0001"; -- 0x....0004 - constant output_enable : std_logic_vector(5 downto 2) := "0010"; -- 0x....0008 - constant output_disable : std_logic_vector(5 downto 2) := "0011"; -- 0x....000C - constant data_status : std_logic_vector(5 downto 2) := "0100"; -- 0x....0010 - constant set_output_data : std_logic_vector(5 downto 2) := "0101"; -- 0x....0014 - constant clear_output_data : std_logic_vector(5 downto 2) := "0110"; -- 0x....0018 - constant data_in_read : std_logic_vector(5 downto 2) := "0111"; -- 0x....001C - constant output_status : std_logic_vector(5 downto 2) := "1000"; -- 0x....0020 - constant cpu_access_address : std_logic_vector(5 downto 2) := "1001"; -- 0x....0024 - - constant Fpga_Ethernet_Reg_Base : std_logic_vector(19 downto 17) := "110"; -- 0x080C0000 - - constant Fpga_DDR_Ctrl_Base : std_logic_vector(19 downto 17) := "111"; -- 0x080E.... - constant DDR_Ctrl_Reg_Addr : std_logic_vector(3 downto 2) := "00"; -- 0x....0000 - constant DDR_Mode_Reg_Addr : std_logic_vector(3 downto 2) := "01"; -- 0x....0004 - constant DDR_Page_Select_Addr : std_logic_vector(3 downto 2) := "10"; -- 0x....0008 - - -end phi_config; diff --git a/zpu/hdl/zpu4/src/ic300pkg.vhd b/zpu/hdl/zpu4/src/ic300pkg.vhd deleted file mode 100644 index 13da306..0000000 --- a/zpu/hdl/zpu4/src/ic300pkg.vhd +++ /dev/null @@ -1,88 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; - -package ic300pkg is - - component ic300 is - port ( -- Clock inputs - cpu_clk_p : in std_logic; - - -- CPU interface signals - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : inout std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - -- DDR SDRAM Signals - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0); -- bidir data bus - sdr_clk_fb_p : in std_logic -- DDR clock feedback - ); - end component; - - component clocks is - port ( areset : in std_logic; - cpu_clk_p : in std_logic; - sdr_clk_fb_p : in std_logic; - cpu_clk : out std_logic; - cpu_clk_2x : out std_logic; - cpu_clk_4x : out std_logic; - ddr_in_clk : out std_logic; - ddr_in_clk_2x : out std_logic; - locked : out std_logic_vector(2 downto 0)); - end component; - - component cpu_regs is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); - end component; - - component ddr_bridge is - port ( areset : in std_logic; - cpu_clk : in std_logic; - cpu_clk_2x : in std_logic; - cpu_clk_4x : in std_logic; - ddr_in_clk : in std_logic; - ddr_in_clk_2x : in std_logic; - - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_dout : inout std_logic_vector(15 downto 0); - - sdr_clk_p : out std_logic; -- ddr_sdram_clock - sdr_clk_n_p : out std_logic; -- /ddr_sdram_clock - cke_q_p : out std_logic; -- clock enable - cs_qn_p : out std_logic; -- /chip select - ras_qn_p : inout std_logic; -- /ras - cas_qn_p : inout std_logic; -- /cas - we_qn_p : inout std_logic; -- /write enable - dm_q_p : out std_logic_vector(1 downto 0); -- data mask bits, set to "00" - dqs_q_p : out std_logic_vector(1 downto 0); -- data strobe, only for write - ba_q_p : out std_logic_vector(1 downto 0); -- bank select - sdr_a_p : out std_logic_vector(12 downto 0); -- address bus - sdr_d_p : inout std_logic_vector(15 downto 0)); -- bidir data bus - end component; - -end ic300pkg; diff --git a/zpu/hdl/zpu4/src/xmake.filelist b/zpu/hdl/zpu4/src/xmake.filelist deleted file mode 100644 index 91e623f..0000000 --- a/zpu/hdl/zpu4/src/xmake.filelist +++ /dev/null @@ -1,12 +0,0 @@ -vhdl work "ic300_config.vhd" -vhdl work "ic300pkg.vhd" -vhdl zylin "zpu_config.vhd" -vhdl zylin "zpupkg.vhd" -vhdl zylin "zpu_core.vhd" -vhdl work "bram.vhd" -vhdl zylin "zpuio.vhd" -vhdl zylin "..\dummyfpgalib\arm7\src\arm7pkg.vhd" -vhdl zylin "..\dummyfpgalib\arm7\src\arm7wb.vhd" -vhdl work "clocks.vhd" -vhdl work "timer.vhd" -vhdl work "ic300.vhd" \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall b/zpu/hdl/zpu4/src/xmake.filelist.bramsmall deleted file mode 100644 index 141633e..0000000 --- a/zpu/hdl/zpu4/src/xmake.filelist.bramsmall +++ /dev/null @@ -1,5 +0,0 @@ -vhdl work "zpu_config.vhd" -vhdl work "zpupkg.vhd" -vhdl work "zpu_core_small.vhd" -vhdl work "bram_dmips.vhd" -vhdl work "testlut.vhd" diff --git a/zpu/hdl/zpu4/src/xmake.xst b/zpu/hdl/zpu4/src/xmake.xst deleted file mode 100644 index bfdb23f..0000000 --- a/zpu/hdl/zpu4/src/xmake.xst +++ /dev/null @@ -1,53 +0,0 @@ -set -tmpdir ../tmp -set -xsthdpdir ../xst -run --ifn xmake.filelist --ifmt mixed --ofn ../syn/ic300 --ofmt NGC --p xc3s400-4-ft256 --top ic300 --opt_mode Area --opt_level 2 --iuc NO --lso ic300.lso --keep_hierarchy NO --glob_opt AllClockNets --rtlview Yes --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --rom_style Auto --mux_extract YES --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --resource_sharing YES --mult_style auto --iobuf YES --max_fanout 500 --bufg 8 --register_duplication YES --equivalent_register_removal NO --register_balancing No --slice_packing YES --optimize_primitives NO --use_clock_enable Yes --use_sync_set No --use_sync_reset No --iob true --slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zpu4/src/zpuio_bram.vhd b/zpu/hdl/zpu4/src/zpuio_bram.vhd deleted file mode 100644 index 5d3f409..0000000 --- a/zpu/hdl/zpu4/src/zpuio_bram.vhd +++ /dev/null @@ -1,229 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); -end zpuio; - -architecture behave of zpuio is - -signal timer_read : std_logic_vector(7 downto 0); ---signal timer_write : std_logic_vector(7 downto 0); -signal timer_we : std_logic; - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); ---signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal Enable : std_logic; - -signal din : std_logic_vector(7 downto 0); -signal dout : std_logic_vector(7 downto 0); -signal adr : std_logic_vector(15 downto 0); -signal break : std_logic; -signal we : std_logic; -signal re : std_logic; - - --- uart forwarding... - -signal uartTXPending : std_logic; -signal uartTXCleared : std_logic; -signal uartData : std_logic_vector(7 downto 0); - -signal readingTimer : std_logic; - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - - - ---signal io_mem_read : std_logic_vector(7 downto 0); ---signal io_mem_writeEnable : std_logic; ---signal io_mem_readEnable : std_logic; -signal io_readEnable : std_logic; - - - - - -begin - - io_addr <= mem_addr(maxAddrBit downto minAddrBit); - - timerinst: timer port map ( - clk => cpu_clk, - areset => areset, - we => timer_we, - din => mem_write(7 downto 0), - adr => io_addr(4 downto 2), - dout => timer_read); - - zpu: zpu_core port map ( - clk => cpu_clk , - areset => areset, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - - - - -- Read/write are on different addresses - -- The registers are 8 bits and mapped to bit[7:0] - -- - -- 0xC000 Write: Writes to UART TX FIFO (4 byte FIFO) - -- Read : Reads from UART RX FIFO (4 byte FIFO) - -- 0xC004 Read : UART status register - -- Bit 0 = RX FIFO empty - -- Bit 1 = TX FIFO full - -- 0xA000 Skrive: LED's (8 stk.) - - -- 0x9000 Write: bit 0: 1= reset counter - -- 0= counter running - -- bit 1: 1= sample counter (when set to 1) - -- 0=not used - -- Read : counter bit[7:0] - -- 0x9004 Read: counter bit [15:8] - -- 0x9008 Read: counter bit [23:16] - -- 0x900C Read: counter bit [31:24] - -- 0x9010 Read: counter bit [39:32] - -- 0x9014 Read: counter bit [47:40] - -- 0x9018 Read: counter bit [55:48] - -- 0x901C Read: counter bit [63:56] - -- - -- 0x8800 Read: unsigned 8-bit integer with FPGA frequency (in MHz) - - fauxUart: - process(cpu_clk, areset) - begin - if areset = '1' then - io_busy <= '0'; - uartTXPending <= '0'; - timer_we <= '0'; - io_busy <= '0'; - uartData <= x"58"; -- 'X' - readingTimer <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - timer_we <= '0'; - io_busy <= '0'; - if uartTXCleared = '1' then - uartTXPending <= '0'; - end if; - - if io_writeEnable = '1' then - if io_addr=x"1000" then - -- Write to UART - uartData <= mem_write(7 downto 0); - uartTXPending <= '1'; - io_busy <= '1'; - elsif io_addr(12)='1' then - timer_we <= '1'; - io_busy <= '1'; - else - report "Illegal IO write" severity failure; - end if; - end if; - if (io_readEnable = '1') then - if io_addr=x"1001" then - io_read <= (0=>'1', -- recieve empty - 1 => uartTXPending, -- tx full - others => '0'); - io_busy <= '1'; - elsif io_addr(12)='1' then - readingTimer <= '1'; - io_busy <= '1'; - elsif io_addr(11)='1' then - io_read <= ZPU_Frequency; - io_busy <= '1'; - else - report "Illegal IO read" severity failure; - end if; - - else - if (readingTimer = '1') then - readingTimer <= '0'; - io_read <= timer_read; - io_busy <= '0'; - else - io_read <= (others => '1'); - end if; - end if; - end if; - end process; - - - forwardUARTOutputToARM: - process(cpu_clk, areset) - begin - if areset = '1' then - uartTXCleared <= '0'; - elsif (cpu_clk = '1' and cpu_clk'event) then - if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then - uartTXCleared <= cpu_din(0); - else - uartTXCleared <= uartTXCleared; - end if; - end if; - end process; - - cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); - cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); - - io_writeEnable <= mem_writeEnable and mem_addr(ioBit); --- io_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy or io_readEnable; - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(cpu_clk, areset) - begin - if areset = '1' then - io_readEnable <= '0'; - - - elsif (cpu_clk'event and cpu_clk = '1') then - mem_read <= (others => '0'); - - if mem_addr(ioBit)='1' and mem_readEnable='1' then - io_readEnable <= '1'; - end if; - if io_readEnable='1' and io_busy='0' then - io_readEnable <= '0'; - mem_read(7 downto 0) <= io_read; - end if; - - end if; - end process; - - -end behave; -- cgit v1.1 From 167263dcae188a8812627ab52cfd96b8fdc5df8a Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 17 Apr 2008 08:31:56 +0000 Subject: * deleted duplicate files from example folder. --- zpu/hdl/zpu4/src/sim_small_fpga_top.vhd | 179 ++++++++++++++++++++++++++++++++ 1 file changed, 179 insertions(+) create mode 100644 zpu/hdl/zpu4/src/sim_small_fpga_top.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd new file mode 100644 index 0000000..b51fea0 --- /dev/null +++ b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd @@ -0,0 +1,179 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; -- cgit v1.1 From d09fa3de9df02a66c5084623076ac3e167b58274 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 22 Apr 2008 05:52:16 +0000 Subject: * zpu/hdl/example_ghdl/ghdl_import.sh, zpu/hdl/example_ghdl/ghdl_make.sh, zpu/hdl/example_ghdl/ghdl_options.sh, zpu/hdl/example_ghdl/README: GHDL example * zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh: testcase for GHDL * zpu/hdl/zpu4/src/dmipstrace_ghdl.sh: testcase for GHDL * zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh: testcase for GHDL * zpu/hdl/example/helloworld.vhd, zpu/hdl/zpu4/src/bram_dmips.vhd, zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh, zpu/hdl/zpu4/src/dram_dmips.vhd, zpu/hdl/zpu4/src/dram_hello.vhd, zpu/hdl/zpu4/src/io.vhd, zpu/hdl/zpu4/src/sim_fpga_top.vhd, zpu/hdl/zpu4/src/sim_small_fpga_top.vhd, zpu/hdl/zpu4/src/timer.vhd, zpu/hdl/zpu4/src/trace.vhd, zpu/hdl/zpu4/src/zpu_config_trace.vhd, zpu/hdl/zpu4/src/zpu_core_small.vhd, zpu/hdl/zpu4/src/zpu_core.vhd, zpu/hdl/zpu4/src/zpupkg.vhd: conversion to numeric_std --- zpu/hdl/zpu4/src/bram_dmips.vhd | 12 +- zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh | 26 + zpu/hdl/zpu4/src/dmipstrace_ghdl.sh | 25 + zpu/hdl/zpu4/src/dram_dmips.vhd | 8 +- zpu/hdl/zpu4/src/dram_hello.vhd | 8 +- zpu/hdl/zpu4/src/io.vhd | 6 +- zpu/hdl/zpu4/src/log.txt | 414 +++++-- zpu/hdl/zpu4/src/sim_fpga_top.vhd | 377 ++++--- zpu/hdl/zpu4/src/sim_small_fpga_top.vhd | 356 +++--- zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh | 25 + zpu/hdl/zpu4/src/timer.vhd | 6 +- zpu/hdl/zpu4/src/trace.vhd | 7 +- zpu/hdl/zpu4/src/zpu_config_trace.vhd | 1 - zpu/hdl/zpu4/src/zpu_core.vhd | 1795 +++++++++++++++--------------- zpu/hdl/zpu4/src/zpu_core_small.vhd | 880 ++++++++------- zpu/hdl/zpu4/src/zpupkg.vhd | 44 +- 16 files changed, 2149 insertions(+), 1841 deletions(-) create mode 100644 zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh create mode 100644 zpu/hdl/zpu4/src/dmipstrace_ghdl.sh create mode 100644 zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/bram_dmips.vhd b/zpu/hdl/zpu4/src/bram_dmips.vhd index 83bfc28..1d62d21 100644 --- a/zpu/hdl/zpu4/src/bram_dmips.vhd +++ b/zpu/hdl/zpu4/src/bram_dmips.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; library work; @@ -22,7 +22,7 @@ end dualport_ram; architecture dualport_ram_arch of dualport_ram is -type ram_type is array(0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( @@ -3691,10 +3691,10 @@ begin end if; if (memAWriteEnable = '1') then - ram(conv_integer(memAAddr)) := memAWrite; + ram(to_integer(unsigned(memAAddr))) := memAWrite; memARead <= memAWrite; else - memARead <= ram(conv_integer(memAAddr)); + memARead <= ram(to_integer(unsigned(memAAddr))); end if; end if; end process; @@ -3703,10 +3703,10 @@ process (clk) begin if (clk'event and clk = '1') then if (memBWriteEnable = '1') then - ram(conv_integer(memBAddr)) := memBWrite; + ram(to_integer(unsigned(memBAddr))) := memBWrite; memBRead <= memBWrite; else - memBRead <= ram(conv_integer(memBAddr)); + memBRead <= ram(to_integer(unsigned(memBAddr))); end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh new file mode 100644 index 0000000..5e43b64 --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" + +if test ! -e work; then + echo "Building work library..." + mkdir work + ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} zpu_core_small.vhd + ghdl -i ${IMPORT_OPTIONS} bram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} timer.vhd + ghdl -i ${IMPORT_OPTIONS} io.vhd + ghdl -i ${IMPORT_OPTIONS} trace.vhd +fi + +echo "Compiling design..." +if ghdl -m ${MAKE_OPTIONS} fpga_top; then + echo "Compilation finished, start simulation with" + echo " ./fpga_top --stop-time=1ms" +fi diff --git a/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh new file mode 100644 index 0000000..3be392f --- /dev/null +++ b/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" + +if test ! -e work; then + echo "Building work library..." + mkdir work + ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd + ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd + ghdl -i ${IMPORT_OPTIONS} timer.vhd + ghdl -i ${IMPORT_OPTIONS} io.vhd + ghdl -i ${IMPORT_OPTIONS} trace.vhd +fi + +echo "Compiling design..." +if ghdl -m ${MAKE_OPTIONS} fpga_top; then + echo "Compilation finished, start simulation with" + echo " ./fpga_top --stop-time=2500us" +fi diff --git a/zpu/hdl/zpu4/src/dram_dmips.vhd b/zpu/hdl/zpu4/src/dram_dmips.vhd index a289fd7..a9fd59e 100644 --- a/zpu/hdl/zpu4/src/dram_dmips.vhd +++ b/zpu/hdl/zpu4/src/dram_dmips.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; library work; @@ -22,7 +22,7 @@ end dram; architecture dram_arch of dram is -type ram_type is array(0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( @@ -3294,10 +3294,10 @@ begin if areset = '1' then elsif (clk'event and clk = '1') then if (mem_writeEnable = '1') then - ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; end if; if (mem_readEnable = '1') then - mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/dram_hello.vhd b/zpu/hdl/zpu4/src/dram_hello.vhd index 3f7788a..4f02cca 100644 --- a/zpu/hdl/zpu4/src/dram_hello.vhd +++ b/zpu/hdl/zpu4/src/dram_hello.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; library work; @@ -22,7 +22,7 @@ end dram; architecture dram_arch of dram is -type ram_type is array(0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); +type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); shared variable ram : ram_type := ( @@ -3093,10 +3093,10 @@ begin if areset = '1' then elsif (clk'event and clk = '1') then if (mem_writeEnable = '1') then - ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))) := mem_write; + ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; end if; if (mem_readEnable = '1') then - mem_read <= ram(conv_integer(mem_addr(maxAddrBit downto minAddrBit))); + mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index 7dbe36f..7a2601f 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; use std.textio.all; @@ -63,12 +63,12 @@ begin if addr=x"2028003" then -- Write to UART -- report "" & character'image(conv_integer(memBint)) severity note; - print(l_file, character'val(conv_integer(write))); + print(l_file, character'val(to_integer(unsigned(write)))); elsif addr(12)='1' then -- report "xxx" severity failure; -- timer_we <= '1'; else - print(l_file, character'val(conv_integer(write))); + print(l_file, character'val(to_integer(unsigned(write)))); report "Illegal IO write" severity warning; end if; diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt index 47b8a65..7a82879 100644 --- a/zpu/hdl/zpu4/src/log.txt +++ b/zpu/hdl/zpu4/src/log.txt @@ -1,156 +1,380 @@ +H +e +l +l +o + +w +o +r +l +d + +1 -D -h -r -y -s -t -o -n + + + +H e +l +l +o -B -e -n -c -h -m -a +w +o r -k -, +l +d -V +2 + + + + + + +H e -r -s -i +l +l o -n -2 -. -1 +w +o +r +l +d -( -L -a -n -g -u -a -g +1 + + + + + + +H e -: +l +l +o + +w +o +r +l +d -C -) +2 -P +H +e +l +l +o + +w +o r +l +d + +1 + + + + + + +H +e +l +l +o + +w o -g r -a -m +l +d + +2 + + + + + + +H +e +l +l +o -c +w o -m -p -i +r l +d + +1 + + + + + + +H e +l +l +o + +w +o +r +l d +2 + + + + + + +H +e +l +l +o + w -i -t -h o -u -t +r +l +d + +1 + + + + + + +H +e +l +l +o -' +w +o r +l +d + +2 + + + + + + +H e -g -i -s -t +l +l +o + +w +o +r +l +d + +1 + + + + + + +H e +l +l +o + +w +o r -' +l +d + +2 + + + + + + +H +e +l +l +o -a -t -t +w +o r -i -b -u -t +l +d + +1 + + + + + + +H e +l +l +o + +w +o +r +l +d + +2 -E -x +H e -c -u -t -i +l +l o -n -s -t -a +w +o r -t -s -, +l +d -5 -0 -0 -0 -0 +1 + + + + + + +H +e +l +l +o +w +o r -u -n -s +l +d -t -h +2 + + + + + + +H +e +l +l +o + +w +o r +l +d + +1 + + + + + + +H +e +l +l o -u -g -h -D -h +w +o r -y -s -t +l +d + +2 + + + + + + +H +e +l +l o -n + +w +o +r +l +d + +1 + + + + + + +H e +l +l +o + +w +o +r +l +d + +2 + + + - diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd index 4defc82..29151af 100644 --- a/zpu/hdl/zpu4/src/sim_fpga_top.vhd +++ b/zpu/hdl/zpu4/src/sim_fpga_top.vhd @@ -1,189 +1,188 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity fpga_top is -end fpga_top; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal enable : std_logic; - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - -signal io_busy : std_logic; - -signal io_mem_read : std_logic_vector(wordSize-1 downto 0); -signal io_mem_writeEnable : std_logic; -signal io_mem_readEnable : std_logic; - - -signal dram_ready : std_logic; -signal io_ready : std_logic; -signal io_reading : std_logic; - - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_core port map ( - clk => clk , - areset => areset, - enable => enable, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - dram_imp: dram port map ( - clk => clk , - areset => areset, - mem_busy => dram_mem_busy, - mem_read => dram_mem_read, - mem_write => mem_write, - mem_addr => mem_addr(maxAddrBit downto 0), - mem_writeEnable => dram_mem_writeEnable, - mem_readEnable => dram_mem_readEnable, - mem_writeMask => mem_writeMask); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_mem_writeEnable, - readEnable => io_mem_readEnable, - write => mem_write(wordSize-1 downto 0), - read => io_mem_read, - addr => mem_addr(maxAddrBit downto minAddrBit) - ); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); - io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy or dram_mem_busy or io_busy; - - - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(dram_mem_read, dram_ready, io_ready, io_mem_read) - begin - mem_read <= (others => 'U'); - if dram_ready='1' then - mem_read <= dram_mem_read; - end if; - - if io_ready='1' then - mem_read <= io_mem_read; - end if; - end process; - - - io_ready <= (io_reading or io_mem_readEnable) and not io_busy; - - memoryControlSync: - process(clk, areset) - begin - if areset = '1' then - enable <= '0'; - io_reading <= '0'; - dram_ready <= '0'; - elsif (clk'event and clk = '1') then - enable <= '1'; - io_reading <= io_busy or io_mem_readEnable; - dram_ready<=dram_mem_readEnable; - - end if; - end process; - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; + +entity fpga_top is +end fpga_top; + +use work.zpupkg.all; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + dram_imp: dram port map ( + clk => clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write(wordSize-1 downto 0), + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd index b51fea0..5c05881 100644 --- a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd +++ b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd @@ -1,179 +1,177 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity fpga_top is -end fpga_top; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal enable : std_logic; - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - -signal io_busy : std_logic; - -signal io_mem_read : std_logic_vector(wordSize-1 downto 0); -signal io_mem_writeEnable : std_logic; -signal io_mem_readEnable : std_logic; - - -signal dram_ready : std_logic; -signal io_ready : std_logic; -signal io_reading : std_logic; - - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_core port map ( - clk => clk , - areset => areset, - enable => enable, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_mem_writeEnable, - readEnable => io_mem_readEnable, - write => mem_write, - read => io_mem_read, - addr => mem_addr(maxAddrBit downto minAddrBit) - ); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); - io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy; - - - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(dram_mem_read, dram_ready, io_ready, io_mem_read) - begin - mem_read <= (others => 'U'); - if dram_ready='1' then - mem_read <= dram_mem_read; - end if; - - if io_ready='1' then - mem_read <= (others => '0'); - mem_read <= io_mem_read; - end if; - end process; - - - io_ready <= (io_reading or io_mem_readEnable) and not io_busy; - - memoryControlSync: - process(clk, areset) - begin - if areset = '1' then - enable <= '0'; - io_reading <= '0'; - dram_ready <= '0'; - elsif (clk'event and clk = '1') then - enable <= '1'; - io_reading <= io_busy or io_mem_readEnable; - dram_ready<=dram_mem_readEnable; - - end if; - end process; - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:15:31 04/14/05 +-- Design Name: +-- Module Name: fpga_top - behave +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity fpga_top is +end fpga_top; + +architecture behave of fpga_top is + + +signal clk : std_logic; + +signal areset : std_logic; + + +component zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end component; + + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal enable : std_logic; + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + +signal io_busy : std_logic; + +signal io_mem_read : std_logic_vector(wordSize-1 downto 0); +signal io_mem_writeEnable : std_logic; +signal io_mem_readEnable : std_logic; + + +signal dram_ready : std_logic; +signal io_ready : std_logic; +signal io_reading : std_logic; + + +signal break : std_logic; + +begin + poweronreset: roc port map (O => areset); + + + + zpu: zpu_core port map ( + clk => clk , + areset => areset, + enable => enable, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + + ioMap: zpu_io port map ( + clk => clk, + areset => areset, + busy => io_busy, + writeEnable => io_mem_writeEnable, + readEnable => io_mem_readEnable, + write => mem_write, + read => io_mem_read, + addr => mem_addr(maxAddrBit downto minAddrBit) + ); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); + io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy; + + + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(dram_mem_read, dram_ready, io_ready, io_mem_read) + begin + mem_read <= (others => 'U'); + if dram_ready='1' then + mem_read <= dram_mem_read; + end if; + + if io_ready='1' then + mem_read <= (others => '0'); + mem_read <= io_mem_read; + end if; + end process; + + + io_ready <= (io_reading or io_mem_readEnable) and not io_busy; + + memoryControlSync: + process(clk, areset) + begin + if areset = '1' then + enable <= '0'; + io_reading <= '0'; + dram_ready <= '0'; + elsif (clk'event and clk = '1') then + enable <= '1'; + io_reading <= io_busy or io_mem_readEnable; + dram_ready<=dram_mem_readEnable; + + end if; + end process; + + -- wiggle the clock @ 100MHz + clock : PROCESS + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end PROCESS clock; + + +end behave; diff --git a/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh b/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh new file mode 100644 index 0000000..7a7f3df --- /dev/null +++ b/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" +IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" +MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" + +if test ! -e work; then + echo "Building work library..." + mkdir work + ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd + ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd + ghdl -i ${IMPORT_OPTIONS} txt_util.vhd + ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd + ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd + ghdl -i ${IMPORT_OPTIONS} dram_hello.vhd + ghdl -i ${IMPORT_OPTIONS} timer.vhd + ghdl -i ${IMPORT_OPTIONS} io.vhd + ghdl -i ${IMPORT_OPTIONS} trace.vhd +fi + +echo "Compiling design..." +if ghdl -m ${MAKE_OPTIONS} fpga_top; then + echo "Compilation finished, start simulation with" + echo " ./fpga_top --stop-time=1ms" +fi diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd index 60c8fe2..be1dbb8 100644 --- a/zpu/hdl/zpu4/src/timer.vhd +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; entity timer is port( @@ -19,7 +19,7 @@ signal sample : std_logic; signal reset : std_logic; -signal cnt : std_logic_vector(63 downto 0); +signal cnt : unsigned(63 downto 0); signal cnt_smp : std_logic_vector(63 downto 0); begin @@ -36,7 +36,7 @@ begin cnt <= cnt + 1; if sample = '1' then -- report "sampling" severity failure; - cnt_smp <= cnt; + cnt_smp <= std_logic_vector(cnt); end if; end if; end process; diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd index bc5279f..e687aaf 100644 --- a/zpu/hdl/zpu4/src/trace.vhd +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -1,7 +1,6 @@ library ieee; use ieee.std_logic_1164.all; ---use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; use std.textio.all; @@ -45,7 +44,7 @@ receive_data: process variable l: line; variable t : std_logic_vector(wordSize-1 downto 0); variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); -variable counter : std_logic_vector(63 downto 0); +variable counter : unsigned(63 downto 0); @@ -69,7 +68,7 @@ counter := (others => '0'); if begin_inst = '1' then t(maxAddrBitIncIO downto 2):=sp; t2:=pc; - print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(counter)); + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter))); end if; wait until clk = '0'; diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd index 4d0f15f..d765d9a 100644 --- a/zpu/hdl/zpu4/src/zpu_config_trace.vhd +++ b/zpu/hdl/zpu4/src/zpu_config_trace.vhd @@ -1,6 +1,5 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; package zpu_config is diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/src/zpu_core.vhd index a603fe9..37fa2d1 100644 --- a/zpu/hdl/zpu4/src/zpu_core.vhd +++ b/zpu/hdl/zpu4/src/zpu_core.vhd @@ -1,898 +1,897 @@ - --- Company: ZPU4 generic memory interface CPU --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - --- mem_writeEnable - set to '1' for a single cycle to send off a write request. --- mem_write is valid only while mem_writeEnable='1'. --- mem_readEnable - set to '1' for a single cycle to send off a read request. --- --- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. --- Set to '0' when mem_read is valid after a read request. --- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable --- is '1'. --- mem_addr - address for read/write request --- mem_read - read data. Valid only on the cycle after mem_busy='0' after --- mem_readEnable='1' for a single cycle. --- mem_write - data to write --- mem_writeMask - set to '1' for those bits that are to be written to memory upon --- write request --- break - set to '1' when CPU hits break instruction --- interrupt - set to '1' until interrupts are cleared by CPU. - - - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -type InsnType is -( -State_AddTop, -State_Dup, -State_DupStackB, -State_Pop, -State_Popdown, -State_Add, -State_Or, -State_And, -State_Store, -State_AddSP, -State_Shift, -State_Nop, -State_Im, -State_LoadSP, -State_StoreSP, -State_Emulate, -State_Load, -State_PushPC, -State_PushSP, -State_PopPC, -State_PopPCRel, -State_Not, -State_Flip, -State_PopSP, -State_Neqbranch, -State_Eq, -State_Loadb, -State_Mult, -State_Lessthan, -State_Lessthanorequal, -State_Ulessthanorequal, -State_Ulessthan, -State_Pushspadd, -State_Call, -State_Callpcrel, -State_Sub, -State_Break, -State_Storeb, -State_InsnFetch -); - -type StateType is -( -State_Load2, -State_Popped, -State_LoadSP2, -State_LoadSP3, -State_AddSP2, -State_Fetch, -State_Execute, -State_Decode, -State_Decode2, -State_Resync, - -State_StoreSP2, -State_Resync2, -State_Resync3, -State_Loadb2, -State_Storeb2, -State_Mult2, -State_Mult3, -State_Mult5, -State_Mult4, -State_BinaryOpResult2, -State_BinaryOpResult, -State_Idle -); - - -signal pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal stackA : std_logic_vector(wordSize-1 downto 0); -signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); -signal binaryOpResult2 : std_logic_vector(wordSize-1 downto 0); -signal multResult2 : std_logic_vector(wordSize-1 downto 0); -signal multResult3 : std_logic_vector(wordSize-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); -signal multA : std_logic_vector(wordSize-1 downto 0); -signal multB : std_logic_vector(wordSize-1 downto 0); -signal stackB : std_logic_vector(wordSize-1 downto 0); -signal idim_flag : std_logic; -signal busy : std_logic; -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayReadEnable : std_logic; - -signal decodeWord : std_logic_vector(wordSize-1 downto 0); - - -signal state : StateType; -signal insn : InsnType; -type InsnArray is array(0 to wordBytes-1) of InsnType; -signal decodedOpcode : InsnArray; - -type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); - -signal opcode : OpcodeArray; - - - - -signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -begin - - - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - -- the memory subsystem will tell us one cycle later whether or - -- not it is busy - out_mem_writeEnable <= mem_writeEnable; - out_mem_readEnable <= mem_readEnable; - out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; - out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); - - incSp <= sp + 1; - incIncSp <= sp + 2; - decSp <= sp - 1; - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable tSpOffset : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); - variable tNextState : InsnType; - variable tDecodedOpcode : InsnArray; - variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); - begin - if areset = '1' then - state <= State_Idle; - break <= '0'; - sp <= spStart(maxAddrBitIncIO downto minAddrBit); - - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - mem_writeEnable <= '0'; - mem_readEnable <= '0'; - multA <= (others => '0'); - multB <= (others => '0'); - mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then - -- we must multiply unconditionally to get pipelined multiplication - tMultResult := multA * multB; - multResult3 <= multResult2; - multResult2 <= multResult; - multResult <= tMultResult(wordSize-1 downto 0); - - - binaryOpResult2 <= binaryOpResult; -- pipeline a bit. - - - multA <= (others => DontCareValue); - multB <= (others => DontCareValue); - - - mem_addr <= (others => DontCareValue); - mem_readEnable <='0'; - mem_writeEnable <='0'; - mem_write <= (others => DontCareValue); - - if (mem_writeEnable = '1') and (mem_readEnable = '1') then - report "read/write collision" severity failure; - end if; - - - - - spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); - spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); - nextPC := pc + 1; - - -- prepare trace snapshot - trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); - trace_pc <= pc; - trace_sp <= sp; - trace_topOfStack <= stackA; - trace_topOfStackB <= stackB; - begin_inst <= '0'; - - - case state is - when State_Idle => - if enable='1' then - state <= State_Resync; - end if; - -- Initial state of ZPU, fetch top of stack + first instruction - when State_Resync => - if in_mem_busy='0' then - mem_addr <= sp; - mem_readEnable <= '1'; - state <= State_Resync2; - end if; - when State_Resync2 => - if in_mem_busy='0' then - stackA <= mem_read; - mem_addr <= incSp; - mem_readEnable <= '1'; - state <= State_Resync3; - end if; - when State_Resync3 => - if in_mem_busy='0' then - stackB <= mem_read; - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Decode => - if in_mem_busy='0' then - decodeWord <= mem_read; - state <= State_Decode2; - end if; - when State_Decode2 => - -- decode 4 instructions in parallel - for i in 0 to wordBytes-1 loop - tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); - - tSpOffset(4):=not tOpcode(4); - tSpOffset(3 downto 0):=tOpcode(3 downto 0); - - opcode(i) <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - tNextState:=State_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - if tSpOffset = 0 then - tNextState := State_Pop; - elsif tSpOffset=1 then - tNextState := State_PopDown; - else - tNextState :=State_StoreSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - if tSpOffset = 0 then - tNextState :=State_Dup; - elsif tSpOffset = 1 then - tNextState :=State_DupStackB; - else - tNextState :=State_LoadSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - tNextState :=State_Emulate; - if tOpcode(5 downto 0)=OpCode_Neqbranch then - tNextState :=State_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - tNextState :=State_Eq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - tNextState :=State_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - --tNextState :=State_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - tNextState :=State_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - --tNextState :=State_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - tNextState :=State_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Mult then - tNextState :=State_Mult; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - tNextState :=State_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - tNextState :=State_Pushspadd; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - tNextState :=State_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Call then - --tNextState :=State_Call; - elsif tOpcode(5 downto 0)=OpCode_Sub then - tNextState :=State_Sub; - elsif tOpcode(5 downto 0)=OpCode_PopPCRel then - --tNextState :=State_PopPCRel; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - if tSpOffset = 0 then - tNextState := State_Shift; - elsif tSpOffset = 1 then - tNextState := State_AddTop; - else - tNextState :=State_AddSP; - end if; - else - case tOpcode(3 downto 0) is - when OpCode_Nop => - tNextState :=State_Nop; - when OpCode_PushSP => - tNextState :=State_PushSP; - when OpCode_PopPC => - tNextState :=State_PopPC; - when OpCode_Add => - tNextState :=State_Add; - when OpCode_Or => - tNextState :=State_Or; - when OpCode_And => - tNextState :=State_And; - when OpCode_Load => - tNextState :=State_Load; - when OpCode_Not => - tNextState :=State_Not; - when OpCode_Flip => - tNextState :=State_Flip; - when OpCode_Store => - tNextState :=State_Store; - when OpCode_PopSP => - tNextState :=State_PopSP; - when others => - tNextState := State_Break; - - end case; - end if; - tDecodedOpcode(i) := tNextState; - - end loop; - - insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); - - -- once we wrap, we need to fetch - tDecodedOpcode(0) := State_InsnFetch; - - decodedOpcode <= tDecodedOpcode; - state <= State_Execute; - - - - -- Each instruction must: - -- - -- 1. set idim_flag - -- 2. increase pc if applicable - -- 3. set next state if appliable - -- 4. do it's operation - - when State_Execute => - insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); - - case insn is - when State_InsnFetch => - state <= State_Fetch; - when State_Im => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '1'; - pc <= pc + 1; - - if idim_flag='1' then - stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - else - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackB <= stackA; - sp <= decSp; - for i in wordSize-1 downto 7 loop - stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); - end loop; - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - end if; - end if; - when State_StoreSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_StoreSP2; - - mem_writeEnable <= '1'; - mem_addr <= sp+spOffset; - mem_write <= stackA; - stackA <= stackB; - sp <= incSp; - end if; - - - when State_LoadSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_LoadSP2; - - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - end if; - when State_Emulate => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - stackB <= stackA; - - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); - state <= State_Fetch; - end if; - when State_Callpcrel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - - pc <= pc + stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_Call => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - pc <= stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_AddSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_AddSP2; - - mem_readEnable <= '1'; - mem_addr <= sp+spOffset; - end if; - when State_PushSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= sp; - stackB <= stackA; - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - end if; - when State_PopPC => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0); - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - end if; - when State_PopPCRel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - end if; - when State_Add => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA + stackB; - - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_Sub => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - binaryOpResult <= stackB - stackA; - state <= State_BinaryOpResult; - end if; - when State_Pop => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - mem_readEnable <= '1'; - sp <= incSp; - stackA <= stackB; - state <= State_Popped; - end if; - when State_PopDown => - if in_mem_busy='0' then - -- PopDown leaves top of stack unchanged - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - mem_readEnable <= '1'; - sp <= incSp; - state <= State_Popped; - end if; - when State_Or => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA or stackB; - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_And => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - stackA <= stackA and stackB; - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_Eq => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Ulessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA<=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Lessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA) - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA)<=signed(stackB)) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Load => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Load2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - end if; - - when State_Dup => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - mem_writeEnable <= '1'; - end if; - when State_DupStackB => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= stackB; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - mem_writeEnable <= '1'; - end if; - when State_Store => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= stackB; - mem_writeEnable <= '1'; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_PopSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - mem_write <= stackB; - mem_addr <= incSp; - mem_writeEnable <= '1'; - sp <= stackA(maxAddrBitIncIO downto minAddrBit); - state <= State_Resync; - end if; - when State_Nop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - when State_Not => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= not stackA; - when State_Flip => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - for i in 0 to wordSize-1 loop - stackA(i) <= stackA(wordSize-1-i); - end loop; - when State_AddTop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= stackA + stackB; - when State_Shift => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); - stackA(0) <= '0'; - when State_Pushspadd => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; - when State_Neqbranch => - -- branches are almost always taken as they form loops - begin_inst <= '1'; - idim_flag <= '0'; - sp <= incIncSp; - if (stackB/=0) then - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - else - pc <= pc + 1; - end if; - -- need to fetch stack again. - state <= State_Resync; - when State_Mult => - begin_inst <= '1'; - idim_flag <= '0'; - - multA <= stackA; - multB <= stackB; - state <= State_Mult2; - when State_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - - when State_Loadb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Loadb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - end if; - when State_Storeb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Storeb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - end if; - - when others => - sp <= (others => DontCareValue); - report "Illegal instruction" severity failure; - break <= '1'; - end case; - - - when State_StoreSP2 => - if in_mem_busy='0' then - mem_addr <= incSp; - mem_readEnable <= '1'; - state <= State_Popped; - end if; - when State_LoadSP2 => - if in_mem_busy='0' then - state <= State_LoadSP3; - mem_readEnable <= '1'; - mem_addr <= sp+spOffset+1; - end if; - when State_LoadSP3 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackB <= stackA; - stackA <= mem_read; - end if; - when State_AddSP2 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackA <= stackA + mem_read; - end if; - when State_Load2 => - if in_mem_busy='0' then - stackA <= mem_read; - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Loadb2 => - if in_mem_busy='0' then - stackA <= (others => '0'); - stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Storeb2 => - if in_mem_busy='0' then - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= mem_read; - mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; - mem_writeEnable <= '1'; - pc <= pc + 1; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_Fetch => - if in_mem_busy='0' then - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Mult2 => - state <= State_Mult3; - when State_Mult3 => - state <= State_Mult4; - when State_Mult4 => - state <= State_Mult5; - when State_Mult5 => - if in_mem_busy='0' then - stackA <= multResult3; - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_BinaryOpResult => - state <= State_BinaryOpResult2; - when State_BinaryOpResult2 => - mem_readEnable <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - stackA <= binaryOpResult2; - state <= State_Popped; - when State_Popped => - if in_mem_busy='0' then - pc <= pc + 1; - stackB <= mem_read; - state <= State_Execute; - end if; - when others => - sp <= (others => DontCareValue); - report "Illegal state" severity failure; - break <= '1'; - end case; - end if; - end process; - - - -end behave; + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_InsnFetch +); + +type StateType is +( +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult4, +State_BinaryOpResult2, +State_BinaryOpResult, +State_Idle +); + + +signal pc : unsigned(maxAddrBitIncIO downto 0); +signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal stackA : unsigned(wordSize-1 downto 0); +signal binaryOpResult : unsigned(wordSize-1 downto 0); +signal binaryOpResult2 : unsigned(wordSize-1 downto 0); +signal multResult2 : unsigned(wordSize-1 downto 0); +signal multResult3 : unsigned(wordSize-1 downto 0); +signal multResult : unsigned(wordSize-1 downto 0); +signal multA : unsigned(wordSize-1 downto 0); +signal multB : unsigned(wordSize-1 downto 0); +signal stackB : unsigned(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; + +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +begin + + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : unsigned(4 downto 0); + variable tSpOffset : unsigned(4 downto 0); + variable nextPC : unsigned(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + + mem_addr <= (others => DontCareValue); + mem_readEnable <='0'; + mem_writeEnable <='0'; + mem_write <= (others => DontCareValue); + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + + + spOffset(4):=not opcode(to_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); + trace_pc <= std_logic_vector(pc); + trace_sp <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(stackA); + trace_topOfStackB <= std_logic_vector(stackB); + begin_inst <= '0'; + + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(sp); + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if in_mem_busy='0' then + stackB <= unsigned(mem_read); + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if in_mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=unsigned(tOpcode(3 downto 0)); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + else + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + end if; + end if; + when State_StoreSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + mem_write <= std_logic_vector(stackA); + stackA <= stackB; + sp <= incSp; + end if; + + + when State_LoadSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_Emulate => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); + state <= State_Fetch; + end if; + when State_Callpcrel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_Call => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_AddSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + end if; + when State_PushSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_PopPC => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_PopPCRel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_Add => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Sub => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + when State_Pop => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + when State_PopDown => + if in_mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + when State_Or => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_And => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Eq => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Ulessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Lessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Load => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when State_Dup => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_DupStackB => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_Store => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= std_logic_vector(stackB); + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_PopSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + when State_Storeb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if in_mem_busy='0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset+1); + end if; + when State_LoadSP3 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= unsigned(mem_read); + end if; + when State_AddSP2 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + unsigned(mem_read); + end if; + when State_Load2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if in_mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= mem_read; + mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + if in_mem_busy='0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + when State_Popped => + if in_mem_busy='0' then + pc <= pc + 1; + stackB <= unsigned(mem_read); + state <= State_Execute; + end if; + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd index 4d73f88..0d734d2 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -1,433 +1,447 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memAWrite : std_logic_vector(wordSize-1 downto 0); -signal memARead : std_logic_vector(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : std_logic_vector(maxAddrBit downto minAddrBit); -signal memBWrite : std_logic_vector(wordSize-1 downto 0); -signal memBRead : std_logic_vector(wordSize-1 downto 0); - - - -signal pc : std_logic_vector(maxAddrBit downto 0); -signal sp : std_logic_vector(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. -type State_Type is -( -State_Fetch, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_FetchNext, -State_AddSP, -State_ReadIODone, -State_Decode, -State_Resync -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP , -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP -); - - - -signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; -signal sampledDecodedOpcode : DecodedOpcodeType; - - -signal state : State_Type; - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr(maxAddrBitBRAM downto minAddrBit), - memAWrite => memAWrite, - memARead => memARead, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr(maxAddrBitBRAM downto minAddrBit), - memBWrite => memBWrite, - memBRead => memBRead - ); - - - - decodeControl: - process(memBRead, pc) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - tOpcode := memBRead((wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-conv_integer(pc(minAddrBit-1 downto 0)))*8); - - sampledOpcode <= tOpcode; - - if (tOpcode(7 downto 7)=OpCode_Im) then - sampledDecodedOpcode<=Decoded_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - sampledDecodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - sampledDecodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - sampledDecodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - sampledDecodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - sampledDecodedOpcode<=Decoded_Break; - when OpCode_PushSP => - sampledDecodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - sampledDecodedOpcode<=Decoded_PopPC; - when OpCode_Add => - sampledDecodedOpcode<=Decoded_Add; - when OpCode_Or => - sampledDecodedOpcode<=Decoded_Or; - when OpCode_And => - sampledDecodedOpcode<=Decoded_And; - when OpCode_Load => - sampledDecodedOpcode<=Decoded_Load; - when OpCode_Not => - sampledDecodedOpcode<=Decoded_Not; - when OpCode_Flip => - sampledDecodedOpcode<=Decoded_Flip; - when OpCode_Store => - sampledDecodedOpcode<=Decoded_Store; - when OpCode_PopSP => - sampledDecodedOpcode<=Decoded_PopSP; - when others => - sampledDecodedOpcode<=Decoded_Nop; - end case; - end if; - end process; - - - opcodeControl: - process(clk, areset) - variable spOffset : std_logic_vector(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= spStart(maxAddrBit downto minAddrBit); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); --- out_mem_addr <= (others => DontCareValue); --- mem_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - begin_inst <= '0'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - mem_write <= memBRead; - - decodedOpcode <= sampledDecodedOpcode; - opcode <= sampledOpcode; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= pc; - trace_opcode <= opcode; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= sp; - trace_topOfStack <= memARead; - trace_topOfStackB <= memBRead; - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0):=opcode(3 downto 0); - - idim_flag <= '0'; - case decodedOpcode is - when Decoded_Im => - idim_flag <= '1'; - memAWriteEnable <= '1'; - if (idim_flag='0') then - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= opcode(6 downto 0); - else - memAAddr <= sp; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= opcode(6 downto 0); - end if; - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(4 downto 0); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (in_mem_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= mem_read; - end if; - when State_WriteIO => - sp <= sp + 1; - out_mem_writeEnable <= '1'; - out_mem_addr <= memARead(maxAddrBitIncIO downto 0); - mem_write <= memBRead; - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - - end if; - end process; - - - -end behave; +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : unsigned(maxAddrBit downto minAddrBit); +signal memAWrite : unsigned(wordSize-1 downto 0); +signal memARead : unsigned(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : unsigned(maxAddrBit downto minAddrBit); +signal memBWrite : unsigned(wordSize-1 downto 0); +signal memBRead : unsigned(wordSize-1 downto 0); + + + +signal pc : unsigned(maxAddrBit downto 0); +signal sp : unsigned(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. +type State_Type is +( +State_Fetch, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_FetchNext, +State_AddSP, +State_ReadIODone, +State_Decode, +State_Resync +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP , +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP +); + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; +signal sampledDecodedOpcode : DecodedOpcodeType; + + +signal state : State_Type; + +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; +signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); +signal memARead_stdlogic : std_logic_vector(memARead'range); +signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); +signal memBRead_stdlogic : std_logic_vector(memBRead'range); + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic + ); + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); + + + + decodeControl: + process(memBRead, pc) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd index 32e162b..f3800b0 100644 --- a/zpu/hdl/zpu4/src/zpupkg.vhd +++ b/zpu/hdl/zpu4/src/zpupkg.vhd @@ -1,6 +1,6 @@ library IEEE; use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; +use ieee.numeric_std.all; library work; use work.zpu_config.all; @@ -133,33 +133,33 @@ package zpupkg is constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; - constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6); - constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6); - constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6); - constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6); + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); - constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6); - constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6); + constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); + constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); - constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6); - constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6); - constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6); - constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6); + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); + constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); - constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6); - constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6); + constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); + constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); - constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6); - constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6); - constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6); + constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); - constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6); - constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6); - constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6); + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); - constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6); - constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6); - constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6); + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); -- cgit v1.1 From c641936739878f3c47e248b82a5f318103fd72f2 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 30 Apr 2008 18:11:46 +0000 Subject: wip to fix some synthesizing problems w/Synopsis --- zpu/hdl/zpu4/src/zpu_core_small_wip.vhd | 957 ++++++++++++++++++++++++++++++++ 1 file changed, 957 insertions(+) create mode 100644 zpu/hdl/zpu4/src/zpu_core_small_wip.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd new file mode 100644 index 0000000..60ad070 --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd @@ -0,0 +1,957 @@ +-- Company: ZPU3 + +-- Engineer: �yvind Harboe + + + +library IEEE; + +use IEEE.STD_LOGIC_1164.ALL; + +use ieee.numeric_std.all; + + + +library work; + +use work.zpu_config.all; + +use work.zpupkg.all; + + + +entity zpu_core is + + Port ( clk : in std_logic; + + areset : in std_logic; + + enable : in std_logic; + + in_mem_busy : in std_logic; + + mem_read : in std_logic_vector(wordSize-1 downto 0); + + mem_write : out std_logic_vector(wordSize-1 downto 0); + + out_mem_addr : out std_logic_vector(maxAddrBitIncIO + +downto 0); + + out_mem_writeEnable : out std_logic; + + out_mem_readEnable : out std_logic; + + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + + interrupt : in std_logic; + + break : out std_logic + + ); + + + +end zpu_core; + + + +architecture behave of zpu_core is + + + +signal readIO : std_logic; + + + + + + + +signal memAWriteEnable : std_logic; + +signal memAAddr : unsigned(maxAddrBit downto minAddrBit); + +signal memAWrite : unsigned(wordSize-1 downto 0); + +signal memARead : unsigned(wordSize-1 downto 0); + +signal memBWriteEnable : std_logic; + +signal memBAddr : unsigned(maxAddrBit downto minAddrBit); + +signal memBWrite : unsigned(wordSize-1 downto 0); + +signal memBRead : unsigned(wordSize-1 downto 0); + + + +signal pc : unsigned(maxAddrBit downto 0); + +signal sp : unsigned(maxAddrBit downto minAddrBit); + + + +signal idim_flag : std_logic; + + + +--signal storeToStack : std_logic; + +--signal fetchNextInstruction : std_logic; + +--signal extraCycle : std_logic; + + + +signal busy : std_logic; + +--signal fetching : std_logic; + + + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); + +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); + +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto + +minAddrBit); + +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); + +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + + + +-- state machine. + +type State_Type is + +( + +State_Fetch, + +State_WriteIODone, + +State_Execute, + +State_StoreToStack, + +State_Add, + +State_Or, + +State_And, + +State_Store, + +State_ReadIO, + +State_WriteIO, + +State_Load, + +State_FetchNext, + +State_AddSP, + +State_ReadIODone, + +State_Decode, + +State_Resync + +); + + + +type DecodedOpcodeType is + +( + +Decoded_Nop, + +Decoded_Im, + +Decoded_ImShift, + +Decoded_LoadSP, + +Decoded_StoreSP , + +Decoded_AddSP, + +Decoded_Emulate, + +Decoded_Break, + +Decoded_PushSP, + +Decoded_PopPC, + +Decoded_Add, + +Decoded_Or, + +Decoded_And, + +Decoded_Load, + +Decoded_Not, + +Decoded_Flip, + +Decoded_Store, + +Decoded_PopSP + +); + + + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + + + +signal decodedOpcode : DecodedOpcodeType; + +signal sampledDecodedOpcode : DecodedOpcodeType; + + + + + +signal state : State_Type; + + + +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto + +minAddrBit; + +signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); + +signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); + +signal memARead_stdlogic : std_logic_vector(memARead'range); + +signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); + +signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); + +signal memBRead_stdlogic : std_logic_vector(memBRead'range); + + + +-- debug + +subtype index is integer range 0 to 31; + +signal tOpcode_sel : index; + + + + + +begin + + traceFileGenerate: + + if Generate_Trace generate + + trace_file: trace port map ( + + clk => clk, + + begin_inst => begin_inst, + + pc => trace_pc, + + opcode => trace_opcode, + + sp => trace_sp, + + memA => trace_topOfStack, + + memB => trace_topOfStackB, + + busy => busy, + + intsp => (others => 'U') + + ); + + end generate; + + + + -- not used in this design + + mem_writeMask <= (others => '1'); + + + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + + memAWrite_stdlogic <= std_logic_vector(memAWrite); + + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + + memBWrite_stdlogic <= std_logic_vector(memBWrite); + + memory: dualport_ram port map ( + + clk => clk, + + memAWriteEnable => memAWriteEnable, + + memAAddr => memAAddr_stdlogic, + + memAWrite => memAWrite_stdlogic, + + memARead => memARead_stdlogic, + + memBWriteEnable => memBWriteEnable, + + memBAddr => memBAddr_stdlogic, + + memBWrite => memBWrite_stdlogic, + + memBRead => memBRead_stdlogic + + ); + + memARead <= unsigned(memARead_stdlogic); + + memBRead <= unsigned(memBRead_stdlogic); + + + +tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + + decodeControl: + + process(memBRead, pc,tOpcode_sel) + + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + + begin + + -- not worked with synopsys + + -- tOpcode := + +std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 + +downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 + +downto 0)))*8)); + + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 + +downto 0)); + + end case; + + sampledOpcode <= tOpcode; + + + + if (tOpcode(7 downto 7)=OpCode_Im) then + + sampledDecodedOpcode<=Decoded_Im; + + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + + sampledDecodedOpcode<=Decoded_StoreSP; + + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + + sampledDecodedOpcode<=Decoded_LoadSP; + + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + + sampledDecodedOpcode<=Decoded_Emulate; + + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + + sampledDecodedOpcode<=Decoded_AddSP; + + else + + case tOpcode(3 downto 0) is + + when OpCode_Break => + + sampledDecodedOpcode<=Decoded_Break; + + when OpCode_PushSP => + + sampledDecodedOpcode<=Decoded_PushSP; + + when OpCode_PopPC => + + sampledDecodedOpcode<=Decoded_PopPC; + + when OpCode_Add => + + sampledDecodedOpcode<=Decoded_Add; + + when OpCode_Or => + + sampledDecodedOpcode<=Decoded_Or; + + when OpCode_And => + + sampledDecodedOpcode<=Decoded_And; + + when OpCode_Load => + + sampledDecodedOpcode<=Decoded_Load; + + when OpCode_Not => + + sampledDecodedOpcode<=Decoded_Not; + + when OpCode_Flip => + + sampledDecodedOpcode<=Decoded_Flip; + + when OpCode_Store => + + sampledDecodedOpcode<=Decoded_Store; + + when OpCode_PopSP => + + sampledDecodedOpcode<=Decoded_PopSP; + + when others => + + sampledDecodedOpcode<=Decoded_Nop; + + end case; + + end if; + + end process; + + + + + + opcodeControl: + + process(clk, areset) + + variable spOffset : unsigned(4 downto 0); + + begin + + if areset = '1' then + + state <= State_Resync; + + break <= '0'; + + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + + pc <= (others => '0'); + + idim_flag <= '0'; + + begin_inst <= '0'; + + memAAddr <= (others => '0'); + + memBAddr <= (others => '0'); + + memAWriteEnable <= '0'; + + memBWriteEnable <= '0'; + + out_mem_writeEnable <= '0'; + + out_mem_readEnable <= '0'; + + memAWrite <= (others => '0'); + + memBWrite <= (others => '0'); + + -- avoid Latch in synopsys + + -- mem_writeMask <= (others => '1'); + + elsif (clk'event and clk = '1') then + + memAWriteEnable <= '0'; + + memBWriteEnable <= '0'; + + -- This saves ca. 100 LUT's, by explicitly declaring that the + + -- memAWrite can be left at whatever value if + +memAWriteEnable is + + -- not set. + + memAWrite <= (others => DontCareValue); + + memBWrite <= (others => DontCareValue); + +-- out_mem_addr <= (others => DontCareValue); + +-- mem_write <= (others => DontCareValue); + + spOffset := (others => DontCareValue); + + memAAddr <= (others => DontCareValue); + + memBAddr <= (others => DontCareValue); + + + + out_mem_writeEnable <= '0'; + + out_mem_readEnable <= '0'; + + begin_inst <= '0'; + + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO + +downto 0)); + + mem_write <= std_logic_vector(memBRead); + + + + decodedOpcode <= sampledDecodedOpcode; + + opcode <= sampledOpcode; + + + + case state is + + when State_Execute => + + state <= State_Fetch; + + -- at this point: + + -- memBRead contains opcode word + + -- memARead contains top of stack + + pc <= pc + 1; + + + + -- trace + + begin_inst <= '1'; + + trace_pc <= (others => '0'); + + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + + trace_opcode <= opcode; + + trace_sp <= (others => '0'); + + trace_sp(maxAddrBit downto minAddrBit) <= + +std_logic_vector(sp); + + trace_topOfStack <= std_logic_vector(memARead); + + trace_topOfStackB <= std_logic_vector(memBRead); + + + + -- during the next cycle we'll be reading the next + +opcode + + spOffset(4):=not opcode(4); + + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + + + idim_flag <= '0'; + + case decodedOpcode is + + when Decoded_Im => + + idim_flag <= '1'; + + memAWriteEnable <= '1'; + + if (idim_flag='0') then + + sp <= sp - 1; + + memAAddr <= sp-1; + + for i in wordSize-1 downto 7 loop + + memAWrite(i) <= opcode(6); + + end loop; + + memAWrite(6 downto 0) <= + +unsigned(opcode(6 downto 0)); + + else + + memAAddr <= sp; + + memAWrite(wordSize-1 downto 7) <= + +memARead(wordSize-8 downto 0); + + memAWrite(6 downto 0) <= + +unsigned(opcode(6 downto 0)); + + end if; + + when Decoded_StoreSP => + + memBWriteEnable <= '1'; + + memBAddr <= sp+spOffset; + + memBWrite <= memARead; + + sp <= sp + 1; + + state <= State_Resync; + + when Decoded_LoadSP => + + sp <= sp - 1; + + memAAddr <= sp+spOffset; + + when Decoded_Emulate => + + sp <= sp - 1; + + memAWriteEnable <= '1'; + + memAAddr <= sp - 1; + + memAWrite <= (others => DontCareValue); + + memAWrite(maxAddrBit downto 0) <= pc + 1; + + -- The emulate address is: + + -- 98 7654 3210 + + -- 0000 00aa aaa0 0000 + + pc <= (others => '0'); + + pc(9 downto 5) <= unsigned(opcode(4 downto + +0)); + + when Decoded_AddSP => + + memAAddr <= sp; + + memBAddr <= sp+spOffset; + + state <= State_AddSP; + + when Decoded_Break => + + report "Break instruction encountered" + +severity failure; + + break <= '1'; + + when Decoded_PushSP => + + memAWriteEnable <= '1'; + + memAAddr <= sp - 1; + + sp <= sp - 1; + + memAWrite <= (others => DontCareValue); + + memAWrite(maxAddrBit downto minAddrBit) <= sp; + + when Decoded_PopPC => + + pc <= memARead(maxAddrBit downto 0); + + sp <= sp + 1; + + state <= State_Resync; + + when Decoded_Add => + + sp <= sp + 1; + + state <= State_Add; + + when Decoded_Or => + + sp <= sp + 1; + + state <= State_Or; + + when Decoded_And => + + sp <= sp + 1; + + state <= State_And; + + when Decoded_Load => + + if (memARead(ioBit)='1') then + + out_mem_addr <= + +std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + + out_mem_readEnable <= '1'; + + state <= State_ReadIO; + + else + + memAAddr <= memARead(maxAddrBit downto + +minAddrBit); + + end if; + + when Decoded_Not => + + memAAddr <= sp(maxAddrBit downto minAddrBit); + + memAWriteEnable <= '1'; + + memAWrite <= not memARead; + + when Decoded_Flip => + + memAAddr <= sp(maxAddrBit downto minAddrBit); + + memAWriteEnable <= '1'; + + for i in 0 to wordSize-1 loop + + memAWrite(i) <= memARead(wordSize-1-i); + + end loop; + + when Decoded_Store => + + memBAddr <= sp + 1; + + sp <= sp + 1; + + if (memARead(ioBit)='1') then + + state <= State_WriteIO; + + else + + state <= State_Store; + + end if; + + when Decoded_PopSP => + + sp <= memARead(maxAddrBit downto minAddrBit); + + state <= State_Resync; + + when Decoded_Nop => + + memAAddr <= sp; + + when others => + + null; + + end case; + + when State_ReadIO => + + if (in_mem_busy = '0') then + + state <= State_Fetch; + + memAWriteEnable <= '1'; + + memAWrite <= unsigned(mem_read); + + end if; + + when State_WriteIO => + + sp <= sp + 1; + + out_mem_writeEnable <= '1'; + + out_mem_addr <= + +std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + + mem_write <= std_logic_vector(memBRead); + + state <= State_WriteIODone; + + when State_WriteIODone => + + if (in_mem_busy = '0') then + + state <= State_Resync; + + end if; + + when State_Fetch => + + -- We need to resync. During the *next* cycle + + -- we'll fetch the opcode @ pc and thus it will + + -- be available for State_Execute the cycle after + + -- next + + memBAddr <= pc(maxAddrBit downto minAddrBit); + + state <= State_FetchNext; + + when State_FetchNext => + + -- at this point memARead contains the value that + +is either + + -- from the top of stack or should be copied to + +the top of the stack + + memAWriteEnable <= '1'; + + memAWrite <= memARead; + + memAAddr <= sp; + + memBAddr <= sp + 1; + + state <= State_Decode; + + when State_Decode => + + -- during the State_Execute cycle we'll be + +fetching SP+1 + + memAAddr <= sp; + + memBAddr <= sp + 1; + + state <= State_Execute; + + when State_Store => + + sp <= sp + 1; + + memAWriteEnable <= '1'; + + memAAddr <= memARead(maxAddrBit downto minAddrBit); + + memAWrite <= memBRead; + + state <= State_Resync; + + when State_AddSP => + + state <= State_Add; + + when State_Add => + + memAAddr <= sp; + + memAWriteEnable <= '1'; + + memAWrite <= memARead + memBRead; + + state <= State_Fetch; + + when State_Or => + + memAAddr <= sp; + + memAWriteEnable <= '1'; + + memAWrite <= memARead or memBRead; + + state <= State_Fetch; + + when State_Resync => + + memAAddr <= sp; + + state <= State_Fetch; + + when State_And => + + memAAddr <= sp; + + memAWriteEnable <= '1'; + + memAWrite <= memARead and memBRead; + + state <= State_Fetch; + + when others => + + null; + + end case; + + + + end if; + + end process; + + + +end behave; -- cgit v1.1 From 7a1fb6dbe419749a2acf4ce583d7732480264ba6 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 30 Apr 2008 18:12:06 +0000 Subject: wip to fix some synthesizing problems w/Synopsis --- zpu/hdl/zpu4/src/zpu_core_small_wip.vhd | 1155 +++++++++---------------------- 1 file changed, 338 insertions(+), 817 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd index 60ad070..63e02e4 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd @@ -1,260 +1,131 @@ -- Company: ZPU3 - --- Engineer: �yvind Harboe - - +-- Engineer: Øyvind Harboe library IEEE; - use IEEE.STD_LOGIC_1164.ALL; - use ieee.numeric_std.all; - - library work; - use work.zpu_config.all; - use work.zpupkg.all; - entity zpu_core is - - Port ( clk : in std_logic; - - areset : in std_logic; - - enable : in std_logic; - - in_mem_busy : in std_logic; - - mem_read : in std_logic_vector(wordSize-1 downto 0); - - mem_write : out std_logic_vector(wordSize-1 downto 0); - - out_mem_addr : out std_logic_vector(maxAddrBitIncIO - -downto 0); - - out_mem_writeEnable : out std_logic; - - out_mem_readEnable : out std_logic; - - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - - interrupt : in std_logic; - - break : out std_logic - - ); - - - + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); end zpu_core; - - architecture behave of zpu_core is - - -signal readIO : std_logic; - - - - +signal readIO : std_logic; signal memAWriteEnable : std_logic; - signal memAAddr : unsigned(maxAddrBit downto minAddrBit); - signal memAWrite : unsigned(wordSize-1 downto 0); - signal memARead : unsigned(wordSize-1 downto 0); - signal memBWriteEnable : std_logic; - signal memBAddr : unsigned(maxAddrBit downto minAddrBit); - signal memBWrite : unsigned(wordSize-1 downto 0); - signal memBRead : unsigned(wordSize-1 downto 0); -signal pc : unsigned(maxAddrBit downto 0); - -signal sp : unsigned(maxAddrBit downto minAddrBit); - - - -signal idim_flag : std_logic; - - - ---signal storeToStack : std_logic; - ---signal fetchNextInstruction : std_logic; - ---signal extraCycle : std_logic; - - - -signal busy : std_logic; - ---signal fetching : std_logic; - - +signal pc : unsigned(maxAddrBit downto 0); +signal sp : unsigned(maxAddrBit downto minAddrBit); -signal begin_inst : std_logic; +signal idim_flag : std_logic; +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; +signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); - -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); - -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto - -minAddrBit); - -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); - -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); -- state machine. - type State_Type is - ( - State_Fetch, - State_WriteIODone, - State_Execute, - State_StoreToStack, - State_Add, - State_Or, - State_And, - State_Store, - State_ReadIO, - State_WriteIO, - State_Load, - State_FetchNext, - State_AddSP, - State_ReadIODone, - State_Decode, - State_Resync - ); - - type DecodedOpcodeType is - ( - Decoded_Nop, - Decoded_Im, - Decoded_ImShift, - Decoded_LoadSP, - -Decoded_StoreSP , - +Decoded_StoreSP , Decoded_AddSP, - Decoded_Emulate, - Decoded_Break, - Decoded_PushSP, - Decoded_PopPC, - Decoded_Add, - Decoded_Or, - Decoded_And, - Decoded_Load, - Decoded_Not, - Decoded_Flip, - Decoded_Store, - Decoded_PopSP - ); - - signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); - signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - - signal decodedOpcode : DecodedOpcodeType; - signal sampledDecodedOpcode : DecodedOpcodeType; - - - signal state : State_Type; - - -subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto - -minAddrBit; - +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); - signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); - signal memARead_stdlogic : std_logic_vector(memARead'range); - signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); - signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); - signal memBRead_stdlogic : std_logic_vector(memBRead'range); - - --- debug - -subtype index is integer range 0 to 31; +subtype index is integer range 0 to 3; signal tOpcode_sel : index; @@ -263,34 +134,20 @@ signal tOpcode_sel : index; begin - - traceFileGenerate: - + traceFileGenerate: if Generate_Trace generate - - trace_file: trace port map ( - - clk => clk, - - begin_inst => begin_inst, - - pc => trace_pc, - - opcode => trace_opcode, - - sp => trace_sp, - - memA => trace_topOfStack, - - memB => trace_topOfStackB, - - busy => busy, - - intsp => (others => 'U') - + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') ); - - end generate; + end generate; @@ -300,64 +157,36 @@ begin - memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); - - memAWrite_stdlogic <= std_logic_vector(memAWrite); - - memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); - - memBWrite_stdlogic <= std_logic_vector(memBWrite); - - memory: dualport_ram port map ( - - clk => clk, - - memAWriteEnable => memAWriteEnable, - - memAAddr => memAAddr_stdlogic, - - memAWrite => memAWrite_stdlogic, - - memARead => memARead_stdlogic, - - memBWriteEnable => memBWriteEnable, - - memBAddr => memBAddr_stdlogic, - - memBWrite => memBWrite_stdlogic, - - memBRead => memBRead_stdlogic - + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic ); - - memARead <= unsigned(memARead_stdlogic); - - memBRead <= unsigned(memBRead_stdlogic); - - - -tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); - decodeControl: - process(memBRead, pc,tOpcode_sel) + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - -- not worked with synopsys - - -- tOpcode := - -std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 - -downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 - -downto 0)))*8)); + decodeControl: + process(memBRead, pc,tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + -- simplify opcode selection a bit so it passes more synthesizers case (tOpcode_sel) is when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); @@ -368,589 +197,281 @@ downto 0)))*8)); when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - when others => tOpcode := std_logic_vector(memBRead(7 - -downto 0)); - + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); end case; - sampledOpcode <= tOpcode; - - - - if (tOpcode(7 downto 7)=OpCode_Im) then - - sampledDecodedOpcode<=Decoded_Im; - - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - - sampledDecodedOpcode<=Decoded_StoreSP; - - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - - sampledDecodedOpcode<=Decoded_LoadSP; - - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - - sampledDecodedOpcode<=Decoded_Emulate; - - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - - sampledDecodedOpcode<=Decoded_AddSP; - - else - - case tOpcode(3 downto 0) is - - when OpCode_Break => - - sampledDecodedOpcode<=Decoded_Break; - - when OpCode_PushSP => - - sampledDecodedOpcode<=Decoded_PushSP; - - when OpCode_PopPC => - - sampledDecodedOpcode<=Decoded_PopPC; - - when OpCode_Add => - - sampledDecodedOpcode<=Decoded_Add; - - when OpCode_Or => - - sampledDecodedOpcode<=Decoded_Or; - - when OpCode_And => - - sampledDecodedOpcode<=Decoded_And; - - when OpCode_Load => - - sampledDecodedOpcode<=Decoded_Load; - - when OpCode_Not => - - sampledDecodedOpcode<=Decoded_Not; - - when OpCode_Flip => - - sampledDecodedOpcode<=Decoded_Flip; - - when OpCode_Store => - - sampledDecodedOpcode<=Decoded_Store; - - when OpCode_PopSP => - - sampledDecodedOpcode<=Decoded_PopSP; - - when others => - - sampledDecodedOpcode<=Decoded_Nop; - - end case; - - end if; - - end process; - - - - - - opcodeControl: - - process(clk, areset) - - variable spOffset : unsigned(4 downto 0); - - begin - - if areset = '1' then - - state <= State_Resync; - - break <= '0'; - - sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); - - pc <= (others => '0'); - - idim_flag <= '0'; - - begin_inst <= '0'; - - memAAddr <= (others => '0'); - - memBAddr <= (others => '0'); - - memAWriteEnable <= '0'; - - memBWriteEnable <= '0'; - - out_mem_writeEnable <= '0'; - - out_mem_readEnable <= '0'; - - memAWrite <= (others => '0'); - - memBWrite <= (others => '0'); - - -- avoid Latch in synopsys - - -- mem_writeMask <= (others => '1'); - - elsif (clk'event and clk = '1') then - - memAWriteEnable <= '0'; - - memBWriteEnable <= '0'; - - -- This saves ca. 100 LUT's, by explicitly declaring that the - - -- memAWrite can be left at whatever value if - -memAWriteEnable is - - -- not set. - - memAWrite <= (others => DontCareValue); - - memBWrite <= (others => DontCareValue); - --- out_mem_addr <= (others => DontCareValue); - --- mem_write <= (others => DontCareValue); - - spOffset := (others => DontCareValue); - - memAAddr <= (others => DontCareValue); - - memBAddr <= (others => DontCareValue); - - - - out_mem_writeEnable <= '0'; - - out_mem_readEnable <= '0'; - - begin_inst <= '0'; - - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO - -downto 0)); - - mem_write <= std_logic_vector(memBRead); - - - - decodedOpcode <= sampledDecodedOpcode; - - opcode <= sampledOpcode; - - - - case state is - - when State_Execute => - - state <= State_Fetch; - - -- at this point: - - -- memBRead contains opcode word - - -- memARead contains top of stack - - pc <= pc + 1; - - - - -- trace - - begin_inst <= '1'; - - trace_pc <= (others => '0'); - - trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); - - trace_opcode <= opcode; - - trace_sp <= (others => '0'); - - trace_sp(maxAddrBit downto minAddrBit) <= - -std_logic_vector(sp); - - trace_topOfStack <= std_logic_vector(memARead); - - trace_topOfStackB <= std_logic_vector(memBRead); - - - - -- during the next cycle we'll be reading the next - -opcode - - spOffset(4):=not opcode(4); - - spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); - - - - idim_flag <= '0'; - - case decodedOpcode is - - when Decoded_Im => - - idim_flag <= '1'; - - memAWriteEnable <= '1'; - - if (idim_flag='0') then - - sp <= sp - 1; - - memAAddr <= sp-1; - - for i in wordSize-1 downto 7 loop - - memAWrite(i) <= opcode(6); - - end loop; - - memAWrite(6 downto 0) <= - -unsigned(opcode(6 downto 0)); - - else - - memAAddr <= sp; - - memAWrite(wordSize-1 downto 7) <= - -memARead(wordSize-8 downto 0); - - memAWrite(6 downto 0) <= - -unsigned(opcode(6 downto 0)); - - end if; - - when Decoded_StoreSP => - - memBWriteEnable <= '1'; - - memBAddr <= sp+spOffset; - - memBWrite <= memARead; - - sp <= sp + 1; - - state <= State_Resync; - - when Decoded_LoadSP => - - sp <= sp - 1; - - memAAddr <= sp+spOffset; - - when Decoded_Emulate => - - sp <= sp - 1; - - memAWriteEnable <= '1'; - - memAAddr <= sp - 1; - - memAWrite <= (others => DontCareValue); - - memAWrite(maxAddrBit downto 0) <= pc + 1; - - -- The emulate address is: - - -- 98 7654 3210 - - -- 0000 00aa aaa0 0000 - - pc <= (others => '0'); - - pc(9 downto 5) <= unsigned(opcode(4 downto - -0)); - - when Decoded_AddSP => - - memAAddr <= sp; - - memBAddr <= sp+spOffset; - - state <= State_AddSP; - - when Decoded_Break => - - report "Break instruction encountered" - -severity failure; - - break <= '1'; - - when Decoded_PushSP => - - memAWriteEnable <= '1'; - - memAAddr <= sp - 1; - - sp <= sp - 1; - - memAWrite <= (others => DontCareValue); - - memAWrite(maxAddrBit downto minAddrBit) <= sp; - - when Decoded_PopPC => - - pc <= memARead(maxAddrBit downto 0); - - sp <= sp + 1; - - state <= State_Resync; - - when Decoded_Add => - - sp <= sp + 1; - - state <= State_Add; - - when Decoded_Or => - - sp <= sp + 1; - - state <= State_Or; - - when Decoded_And => - - sp <= sp + 1; - - state <= State_And; - - when Decoded_Load => - - if (memARead(ioBit)='1') then - - out_mem_addr <= - -std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - - out_mem_readEnable <= '1'; - - state <= State_ReadIO; - - else - - memAAddr <= memARead(maxAddrBit downto - -minAddrBit); - - end if; - - when Decoded_Not => - - memAAddr <= sp(maxAddrBit downto minAddrBit); - - memAWriteEnable <= '1'; - - memAWrite <= not memARead; - - when Decoded_Flip => - - memAAddr <= sp(maxAddrBit downto minAddrBit); - - memAWriteEnable <= '1'; - - for i in 0 to wordSize-1 loop - - memAWrite(i) <= memARead(wordSize-1-i); - - end loop; - - when Decoded_Store => - - memBAddr <= sp + 1; - - sp <= sp + 1; - - if (memARead(ioBit)='1') then - - state <= State_WriteIO; - - else - - state <= State_Store; - - end if; - - when Decoded_PopSP => - - sp <= memARead(maxAddrBit downto minAddrBit); - - state <= State_Resync; - - when Decoded_Nop => - - memAAddr <= sp; - - when others => - - null; - - end case; - - when State_ReadIO => - - if (in_mem_busy = '0') then - - state <= State_Fetch; - - memAWriteEnable <= '1'; - - memAWrite <= unsigned(mem_read); - - end if; - - when State_WriteIO => - - sp <= sp + 1; - - out_mem_writeEnable <= '1'; - - out_mem_addr <= - -std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - - mem_write <= std_logic_vector(memBRead); - - state <= State_WriteIODone; - - when State_WriteIODone => - - if (in_mem_busy = '0') then - - state <= State_Resync; - - end if; - - when State_Fetch => - - -- We need to resync. During the *next* cycle - - -- we'll fetch the opcode @ pc and thus it will - - -- be available for State_Execute the cycle after - - -- next - - memBAddr <= pc(maxAddrBit downto minAddrBit); - - state <= State_FetchNext; - - when State_FetchNext => - - -- at this point memARead contains the value that - -is either - - -- from the top of stack or should be copied to - -the top of the stack - - memAWriteEnable <= '1'; - - memAWrite <= memARead; - - memAAddr <= sp; - - memBAddr <= sp + 1; - - state <= State_Decode; - - when State_Decode => - - -- during the State_Execute cycle we'll be - -fetching SP+1 - - memAAddr <= sp; - - memBAddr <= sp + 1; - - state <= State_Execute; - - when State_Store => - - sp <= sp + 1; - - memAWriteEnable <= '1'; - - memAAddr <= memARead(maxAddrBit downto minAddrBit); - - memAWrite <= memBRead; - - state <= State_Resync; - - when State_AddSP => - - state <= State_Add; - - when State_Add => - - memAAddr <= sp; - - memAWriteEnable <= '1'; - - memAWrite <= memARead + memBRead; - - state <= State_Fetch; - - when State_Or => - - memAAddr <= sp; - - memAWriteEnable <= '1'; - - memAWrite <= memARead or memBRead; - - state <= State_Fetch; - - when State_Resync => - - memAAddr <= sp; - - state <= State_Fetch; - - when State_And => - - memAAddr <= sp; - - memAWriteEnable <= '1'; - - memAWrite <= memARead and memBRead; - - state <= State_Fetch; - - when others => - - null; - - end case; - - - - end if; - - end process; + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; -- cgit v1.1 From 30faee20f811215e6d53ca2434119aa5cd059feb Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 1 May 2008 08:20:02 +0000 Subject: work in progress. --- zpu/hdl/zpu4/src/zpu_core_wip.vhd | 948 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 948 insertions(+) create mode 100644 zpu/hdl/zpu4/src/zpu_core_wip.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/zpu_core_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_wip.vhd new file mode 100644 index 0000000..882719d --- /dev/null +++ b/zpu/hdl/zpu4/src/zpu_core_wip.vhd @@ -0,0 +1,948 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.STD_LOGIC_arith.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + mem_req : out std_logic; + mem_we : out std_logic; + mem_ack : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic; + zpu_status : out std_logic_vector(63 downto 0)); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_Interrupt, +State_InsnFetch +); + +type StateType is +( +State_Idle, -- using first state first on the list out of paranoia +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult6, +State_Mult4, +State_BinaryOpResult +); + + +signal pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal stackA : std_logic_vector(wordSize-1 downto 0); +signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); +signal multResult2 : std_logic_vector(wordSize-1 downto 0); +signal multResult3 : std_logic_vector(wordSize-1 downto 0); +signal multResult : std_logic_vector(wordSize-1 downto 0); +signal multA : std_logic_vector(wordSize-1 downto 0); +signal multB : std_logic_vector(wordSize-1 downto 0); +signal stackB : std_logic_vector(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; +signal mem_busy : std_logic; +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +signal out_mem_req : std_logic; + +signal inInterrupt : std_logic; + +-- state machine. + +begin + + zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; + zpu_status(31) <= '1'; + zpu_status(39 downto 32) <= trace_opcode; + zpu_status(40) <= '1' when (state = State_Idle) else '0'; + zpu_status(62) <= '1'; + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + mem_req <= out_mem_req; + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : std_logic_vector(4 downto 0); + variable tSpOffset : std_logic_vector(4 downto 0); + variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= spStart(maxAddrBitIncIO downto minAddrBit); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_we <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + out_mem_req <= '0'; + mem_addr <= (others => DontCareValue); + mem_write <= (others => DontCareValue); + inInterrupt <= '0'; + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); + trace_pc <= pc; + trace_sp <= sp; + trace_topOfStack <= stackA; + trace_topOfStackB <= stackB; + begin_inst <= '0'; + + -- we terminate the requeset as soon as we get acknowledge + if mem_ack = '1' then + out_mem_req <= '0'; + mem_we <= '0'; + end if; + + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if mem_busy='0' then + mem_addr <= sp; + out_mem_req <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if mem_busy='0' then + stackA <= mem_read; + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if mem_busy='0' then + stackB <= mem_read; + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=tOpcode(3 downto 0); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + else + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); + end if; + else + insn <= insn; + end if; + when State_StoreSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= sp+spOffset; + mem_write <= stackA; + stackA <= stackB; + sp <= incSp; + else + insn <= insn; + end if; + + + when State_LoadSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_Emulate => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Callpcrel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_Call => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + else + insn <= insn; + end if; + when State_AddSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + out_mem_req <= '1'; + mem_addr <= sp+spOffset; + else + insn <= insn; + end if; + when State_PushSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + else + insn <= insn; + end if; + when State_PopPC => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopPCRel => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + state <= State_Resync; + else + insn <= insn; + end if; + when State_Add => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Sub => + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + when State_Pop => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + else + insn <= insn; + end if; + when State_PopDown => + if mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= incIncSp; + out_mem_req <= '1'; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Or => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_And => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + else + insn <= insn; + end if; + when State_Eq => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Ulessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Lessthan => + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + when State_Load => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when State_Dup => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_DupStackB => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + else + insn <= insn; + end if; + when State_Store => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= stackB; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= incIncSp; + state <= State_Resync; + else + insn <= insn; + end if; + when State_PopSP => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= stackB; + mem_addr <= incSp; + out_mem_req <= '1'; + mem_we <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + else + insn <= insn; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + when State_Storeb => + if mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + else + insn <= insn; + end if; + + when others => +-- sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if mem_busy='0' then + mem_addr <= incSp; + out_mem_req <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if mem_busy='0' then + state <= State_LoadSP3; + out_mem_req <= '1'; + mem_addr <= sp+spOffset+1; + end if; + when State_LoadSP3 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= mem_read; + end if; + when State_AddSP2 => + if mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + mem_read; + end if; + when State_Load2 => + if mem_busy='0' then + stackA <= mem_read; + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if mem_busy='0' then + mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); + mem_write <= mem_read; + mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; + out_mem_req <= '1'; + mem_we <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if mem_busy='0' then + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt + inInterrupt <= '1'; + + sp <= decSp; + out_mem_req <= '1'; + mem_we <= '1'; + mem_addr <= incSp; + mem_write <= stackB; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + + report "ZPU jumped to interrupt!" severity note; + else + mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); + out_mem_req <= '1'; + state <= State_Decode; + end if; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + stackA <= multResult3; + state <= State_Mult6; + when State_Mult6 => + if mem_busy='0' then + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + if mem_busy='0' then + -- NB!!!! we know that the memory isn't busy at this point!!!! + out_mem_req <= '1'; + mem_addr <= incIncSp; + sp <= incSp; + stackA <= binaryOpResult; + state <= State_Popped; + end if; + when State_Popped => + if mem_busy='0' then + pc <= pc + 1; + stackB <= mem_read; + state <= State_Execute; + end if; + when others => +-- sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; -- cgit v1.1 From 0d7bc56eab8ff2d28aa9c4721a56b022385e13d9 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 1 May 2008 08:23:39 +0000 Subject: * zpu/hdl/zy1000 - ZPU implementation used on the zy1000 dev kit --- zpu/hdl/zpu4/src/zpu_core_wip.vhd | 948 -------------------------------------- 1 file changed, 948 deletions(-) delete mode 100644 zpu/hdl/zpu4/src/zpu_core_wip.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/zpu_core_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_wip.vhd deleted file mode 100644 index 882719d..0000000 --- a/zpu/hdl/zpu4/src/zpu_core_wip.vhd +++ /dev/null @@ -1,948 +0,0 @@ - --- Company: ZPU4 generic memory interface CPU --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.STD_LOGIC_arith.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - - - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - mem_req : out std_logic; - mem_we : out std_logic; - mem_ack : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic; - zpu_status : out std_logic_vector(63 downto 0)); -end zpu_core; - -architecture behave of zpu_core is - -type InsnType is -( -State_AddTop, -State_Dup, -State_DupStackB, -State_Pop, -State_Popdown, -State_Add, -State_Or, -State_And, -State_Store, -State_AddSP, -State_Shift, -State_Nop, -State_Im, -State_LoadSP, -State_StoreSP, -State_Emulate, -State_Load, -State_PushPC, -State_PushSP, -State_PopPC, -State_PopPCRel, -State_Not, -State_Flip, -State_PopSP, -State_Neqbranch, -State_Eq, -State_Loadb, -State_Mult, -State_Lessthan, -State_Lessthanorequal, -State_Ulessthanorequal, -State_Ulessthan, -State_Pushspadd, -State_Call, -State_Callpcrel, -State_Sub, -State_Break, -State_Storeb, -State_Interrupt, -State_InsnFetch -); - -type StateType is -( -State_Idle, -- using first state first on the list out of paranoia -State_Load2, -State_Popped, -State_LoadSP2, -State_LoadSP3, -State_AddSP2, -State_Fetch, -State_Execute, -State_Decode, -State_Decode2, -State_Resync, - -State_StoreSP2, -State_Resync2, -State_Resync3, -State_Loadb2, -State_Storeb2, -State_Mult2, -State_Mult3, -State_Mult5, -State_Mult6, -State_Mult4, -State_BinaryOpResult -); - - -signal pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal stackA : std_logic_vector(wordSize-1 downto 0); -signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); -signal multResult2 : std_logic_vector(wordSize-1 downto 0); -signal multResult3 : std_logic_vector(wordSize-1 downto 0); -signal multResult : std_logic_vector(wordSize-1 downto 0); -signal multA : std_logic_vector(wordSize-1 downto 0); -signal multB : std_logic_vector(wordSize-1 downto 0); -signal stackB : std_logic_vector(wordSize-1 downto 0); -signal idim_flag : std_logic; -signal busy : std_logic; -signal mem_readEnable : std_logic; -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayReadEnable : std_logic; -signal mem_busy : std_logic; -signal decodeWord : std_logic_vector(wordSize-1 downto 0); - - -signal state : StateType; -signal insn : InsnType; -type InsnArray is array(0 to wordBytes-1) of InsnType; -signal decodedOpcode : InsnArray; - -type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); - -signal opcode : OpcodeArray; - - - - -signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - -signal out_mem_req : std_logic; - -signal inInterrupt : std_logic; - --- state machine. - -begin - - zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; - zpu_status(31) <= '1'; - zpu_status(39 downto 32) <= trace_opcode; - zpu_status(40) <= '1' when (state = State_Idle) else '0'; - zpu_status(62) <= '1'; - - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - -- the memory subsystem will tell us one cycle later whether or - -- not it is busy - out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; - out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); - mem_req <= out_mem_req; - - incSp <= sp + 1; - incIncSp <= sp + 2; - decSp <= sp - 1; - - mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : std_logic_vector(4 downto 0); - variable tSpOffset : std_logic_vector(4 downto 0); - variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); - variable tNextState : InsnType; - variable tDecodedOpcode : InsnArray; - variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); - begin - if areset = '1' then - state <= State_Idle; - break <= '0'; - sp <= spStart(maxAddrBitIncIO downto minAddrBit); - - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - mem_we <= '0'; - multA <= (others => '0'); - multB <= (others => '0'); - mem_writeMask <= (others => '1'); - out_mem_req <= '0'; - mem_addr <= (others => DontCareValue); - mem_write <= (others => DontCareValue); - inInterrupt <= '0'; - elsif (clk'event and clk = '1') then - -- we must multiply unconditionally to get pipelined multiplication - tMultResult := multA * multB; - multResult3 <= multResult2; - multResult2 <= multResult; - multResult <= tMultResult(wordSize-1 downto 0); - - - spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); - spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); - nextPC := pc + 1; - - -- prepare trace snapshot - trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); - trace_pc <= pc; - trace_sp <= sp; - trace_topOfStack <= stackA; - trace_topOfStackB <= stackB; - begin_inst <= '0'; - - -- we terminate the requeset as soon as we get acknowledge - if mem_ack = '1' then - out_mem_req <= '0'; - mem_we <= '0'; - end if; - - if interrupt='0' then - inInterrupt <= '0'; -- no longer in an interrupt - end if; - - case state is - when State_Idle => - if enable='1' then - state <= State_Resync; - end if; - -- Initial state of ZPU, fetch top of stack + first instruction - when State_Resync => - if mem_busy='0' then - mem_addr <= sp; - out_mem_req <= '1'; - state <= State_Resync2; - end if; - when State_Resync2 => - if mem_busy='0' then - stackA <= mem_read; - mem_addr <= incSp; - out_mem_req <= '1'; - state <= State_Resync3; - end if; - when State_Resync3 => - if mem_busy='0' then - stackB <= mem_read; - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - state <= State_Decode; - end if; - when State_Decode => - if mem_busy='0' then - decodeWord <= mem_read; - state <= State_Decode2; - end if; - when State_Decode2 => - -- decode 4 instructions in parallel - for i in 0 to wordBytes-1 loop - tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); - - tSpOffset(4):=not tOpcode(4); - tSpOffset(3 downto 0):=tOpcode(3 downto 0); - - opcode(i) <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - tNextState:=State_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - if tSpOffset = 0 then - tNextState := State_Pop; - elsif tSpOffset=1 then - tNextState := State_PopDown; - else - tNextState :=State_StoreSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - if tSpOffset = 0 then - tNextState :=State_Dup; - elsif tSpOffset = 1 then - tNextState :=State_DupStackB; - else - tNextState :=State_LoadSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - tNextState :=State_Emulate; - if tOpcode(5 downto 0)=OpCode_Neqbranch then - tNextState :=State_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - tNextState :=State_Eq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - tNextState :=State_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - --tNextState :=State_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - tNextState :=State_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - --tNextState :=State_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - tNextState :=State_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Mult then - tNextState :=State_Mult; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - tNextState :=State_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - tNextState :=State_Pushspadd; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - tNextState :=State_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Call then - --tNextState :=State_Call; - elsif tOpcode(5 downto 0)=OpCode_Sub then - tNextState :=State_Sub; - elsif tOpcode(5 downto 0)=OpCode_PopPCRel then - --tNextState :=State_PopPCRel; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - if tSpOffset = 0 then - tNextState := State_Shift; - elsif tSpOffset = 1 then - tNextState := State_AddTop; - else - tNextState :=State_AddSP; - end if; - else - case tOpcode(3 downto 0) is - when OpCode_Nop => - tNextState :=State_Nop; - when OpCode_PushSP => - tNextState :=State_PushSP; - when OpCode_PopPC => - tNextState :=State_PopPC; - when OpCode_Add => - tNextState :=State_Add; - when OpCode_Or => - tNextState :=State_Or; - when OpCode_And => - tNextState :=State_And; - when OpCode_Load => - tNextState :=State_Load; - when OpCode_Not => - tNextState :=State_Not; - when OpCode_Flip => - tNextState :=State_Flip; - when OpCode_Store => - tNextState :=State_Store; - when OpCode_PopSP => - tNextState :=State_PopSP; - when others => - tNextState := State_Break; - - end case; - end if; - tDecodedOpcode(i) := tNextState; - - end loop; - - insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); - - -- once we wrap, we need to fetch - tDecodedOpcode(0) := State_InsnFetch; - - decodedOpcode <= tDecodedOpcode; - state <= State_Execute; - - - - -- Each instruction must: - -- - -- 1. set idim_flag - -- 2. increase pc if applicable - -- 3. set next state if appliable - -- 4. do it's operation - - when State_Execute => - insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); - - case insn is - when State_InsnFetch => - state <= State_Fetch; - when State_Im => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '1'; - pc <= pc + 1; - - if idim_flag='1' then - stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - else - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackB <= stackA; - sp <= decSp; - for i in wordSize-1 downto 7 loop - stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); - end loop; - stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); - end if; - else - insn <= insn; - end if; - when State_StoreSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_StoreSP2; - - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= sp+spOffset; - mem_write <= stackA; - stackA <= stackB; - sp <= incSp; - else - insn <= insn; - end if; - - - when State_LoadSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_LoadSP2; - - sp <= decSp; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - else - insn <= insn; - end if; - when State_Emulate => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - sp <= decSp; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - stackB <= stackA; - - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); - state <= State_Fetch; - else - insn <= insn; - end if; - when State_Callpcrel => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - - pc <= pc + stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - else - insn <= insn; - end if; - when State_Call => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - pc <= stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - else - insn <= insn; - end if; - when State_AddSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_AddSP2; - - out_mem_req <= '1'; - mem_addr <= sp+spOffset; - else - insn <= insn; - end if; - when State_PushSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= sp; - stackB <= stackA; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - else - insn <= insn; - end if; - when State_PopPC => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0); - sp <= incSp; - - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - else - insn <= insn; - end if; - when State_PopPCRel => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - sp <= incSp; - - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - state <= State_Resync; - else - insn <= insn; - end if; - when State_Add => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA + stackB; - - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_Sub => - begin_inst <= '1'; - idim_flag <= '0'; - binaryOpResult <= stackB - stackA; - state <= State_BinaryOpResult; - when State_Pop => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - out_mem_req <= '1'; - sp <= incSp; - stackA <= stackB; - state <= State_Popped; - else - insn <= insn; - end if; - when State_PopDown => - if mem_busy='0' then - -- PopDown leaves top of stack unchanged - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= incIncSp; - out_mem_req <= '1'; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_Or => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA or stackB; - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_And => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - stackA <= stackA and stackB; - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - else - insn <= insn; - end if; - when State_Eq => - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - when State_Ulessthan => - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA<=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - when State_Lessthan => - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA) - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA)<=signed(stackB)) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - when State_Load => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Load2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - else - insn <= insn; - end if; - - when State_Dup => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - out_mem_req <= '1'; - mem_we <= '1'; - else - insn <= insn; - end if; - when State_DupStackB => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= stackB; - stackB <= stackA; - mem_write <= stackB; - mem_addr <= incSp; - out_mem_req <= '1'; - mem_we <= '1'; - else - insn <= insn; - end if; - when State_Store => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= stackB; - out_mem_req <= '1'; - mem_we <= '1'; - sp <= incIncSp; - state <= State_Resync; - else - insn <= insn; - end if; - when State_PopSP => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - mem_write <= stackB; - mem_addr <= incSp; - out_mem_req <= '1'; - mem_we <= '1'; - sp <= stackA(maxAddrBitIncIO downto minAddrBit); - state <= State_Resync; - else - insn <= insn; - end if; - when State_Nop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - when State_Not => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= not stackA; - when State_Flip => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - for i in 0 to wordSize-1 loop - stackA(i) <= stackA(wordSize-1-i); - end loop; - when State_AddTop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= stackA + stackB; - when State_Shift => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); - stackA(0) <= '0'; - when State_Pushspadd => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; - when State_Neqbranch => - -- branches are almost always taken as they form loops - begin_inst <= '1'; - idim_flag <= '0'; - sp <= incIncSp; - if (stackB/=0) then - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - else - pc <= pc + 1; - end if; - -- need to fetch stack again. - state <= State_Resync; - when State_Mult => - begin_inst <= '1'; - idim_flag <= '0'; - - multA <= stackA; - multB <= stackB; - state <= State_Mult2; - when State_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - - when State_Loadb => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Loadb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - else - insn <= insn; - end if; - when State_Storeb => - if mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Storeb2; - - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - else - insn <= insn; - end if; - - when others => --- sp <= (others => DontCareValue); - report "Illegal instruction" severity failure; - break <= '1'; - end case; - - - when State_StoreSP2 => - if mem_busy='0' then - mem_addr <= incSp; - out_mem_req <= '1'; - state <= State_Popped; - end if; - when State_LoadSP2 => - if mem_busy='0' then - state <= State_LoadSP3; - out_mem_req <= '1'; - mem_addr <= sp+spOffset+1; - end if; - when State_LoadSP3 => - if mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackB <= stackA; - stackA <= mem_read; - end if; - when State_AddSP2 => - if mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackA <= stackA + mem_read; - end if; - when State_Load2 => - if mem_busy='0' then - stackA <= mem_read; - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Loadb2 => - if mem_busy='0' then - stackA <= (others => '0'); - stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Storeb2 => - if mem_busy='0' then - mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); - mem_write <= mem_read; - mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; - out_mem_req <= '1'; - mem_we <= '1'; - pc <= pc + 1; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_Fetch => - if mem_busy='0' then - if interrupt='1' and inInterrupt='0' and idim_flag='0' then - -- We got an interrupt - inInterrupt <= '1'; - - sp <= decSp; - out_mem_req <= '1'; - mem_we <= '1'; - mem_addr <= incSp; - mem_write <= stackB; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc; - stackB <= stackA; - - pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address - - report "ZPU jumped to interrupt!" severity note; - else - mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); - out_mem_req <= '1'; - state <= State_Decode; - end if; - end if; - when State_Mult2 => - state <= State_Mult3; - when State_Mult3 => - state <= State_Mult4; - when State_Mult4 => - state <= State_Mult5; - when State_Mult5 => - stackA <= multResult3; - state <= State_Mult6; - when State_Mult6 => - if mem_busy='0' then - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - state <= State_Popped; - end if; - when State_BinaryOpResult => - if mem_busy='0' then - -- NB!!!! we know that the memory isn't busy at this point!!!! - out_mem_req <= '1'; - mem_addr <= incIncSp; - sp <= incSp; - stackA <= binaryOpResult; - state <= State_Popped; - end if; - when State_Popped => - if mem_busy='0' then - pc <= pc + 1; - stackB <= mem_read; - state <= State_Execute; - end if; - when others => --- sp <= (others => DontCareValue); - report "Illegal state" severity failure; - break <= '1'; - end case; - end if; - end process; - - - -end behave; -- cgit v1.1 From 47fd50b7c9654cf750e6c2024c9169a9eab2d6ad Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 1 May 2008 08:44:59 +0000 Subject: wip --- zpu/hdl/zpu4/src/zpu_core_small_wip.vhd | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd index 63e02e4..8d87804 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd @@ -81,7 +81,9 @@ State_FetchNext, State_AddSP, State_ReadIODone, State_Decode, -State_Resync +State_Resync, +State_Interrupt + ); type DecodedOpcodeType is @@ -130,6 +132,7 @@ subtype index is integer range 0 to 3; signal tOpcode_sel : index; +signal inInterrupt : std_logic; @@ -262,6 +265,7 @@ begin out_mem_readEnable <= '0'; memAWrite <= (others => '0'); memBWrite <= (others => '0'); + inInterrupt <= '0'; elsif (clk'event and clk = '1') then memAWriteEnable <= '0'; memBWriteEnable <= '0'; @@ -284,6 +288,9 @@ begin decodedOpcode <= sampledDecodedOpcode; opcode <= sampledOpcode; + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; case state is when State_Execute => @@ -309,6 +316,14 @@ begin idim_flag <= '0'; case decodedOpcode is + when Decoded_Interrupt => + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBitIncIO downto 0) <= pc; + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + report "ZPU jumped to interrupt!" severity note; when Decoded_Im => idim_flag <= '1'; memAWriteEnable <= '1'; @@ -436,6 +451,10 @@ begin memBAddr <= sp + 1; state <= State_Decode; when State_Decode => + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + decodedOpcode <= Decoded_Interrupt; + end if; -- during the State_Execute cycle we'll be fetching SP+1 memAAddr <= sp; memBAddr <= sp + 1; -- cgit v1.1 From ed14271c9743490ebc4947ba7904adaa0d16e279 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 1 May 2008 18:49:10 +0000 Subject: wip for interrupts --- zpu/hdl/zpu4/test/interrupt/build.sh | 4 ++++ zpu/hdl/zpu4/test/interrupt/int.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 zpu/hdl/zpu4/test/interrupt/build.sh create mode 100644 zpu/hdl/zpu4/test/interrupt/int.c (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/test/interrupt/build.sh b/zpu/hdl/zpu4/test/interrupt/build.sh new file mode 100644 index 0000000..3d617e9 --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/build.sh @@ -0,0 +1,4 @@ +zpu-elf-gcc -O3 -phi `pwd`/int.c -o int.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >int.dis int.elf +zpu-elf-objcopy -O binary int.elf int.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam int.bin >int.ram diff --git a/zpu/hdl/zpu4/test/interrupt/int.c b/zpu/hdl/zpu4/test/interrupt/int.c new file mode 100644 index 0000000..2be6483 --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/int.c @@ -0,0 +1,32 @@ +/* + * Shows usage of interrupts. Goes along with zpu_core_small_wip.vhd. + */ +#include + + +int counter; + +/* Example of single, fixed interval non-maskable, nested interrupt */ +void _zpu_interrupt(void) +{ + /* interrupts are enabled so we need to finish up quickly, + * lest we will get infinite recursion!*/ + counter++; +} + +int main(int argc, char **argv) +{ + int t; + t=counter; + for (;;) + { + if (t==counter) + { + puts("No interrupt\n"); + } else + { + puts("Got interrupt\n"); + } + } + +} -- cgit v1.1 From 1362bd4ace3ce962ed744a153e5f969154bb6682 Mon Sep 17 00:00:00 2001 From: oharboe Date: Sun, 4 May 2008 19:29:07 +0000 Subject: * Make code synthesize on Synopsis zpu/hdl/zpu4/src/zpu_core_small.vhd zpu/hdl/zpu4/src/io.vhd --- zpu/hdl/zpu4/src/io.vhd | 15 +-- zpu/hdl/zpu4/src/sim_small_fpga_top.vhd | 177 -------------------------------- zpu/hdl/zpu4/src/zpu_core_small.vhd | 25 ++++- zpu/hdl/zpu4/test/interrupt/int.c | 5 +- 4 files changed, 34 insertions(+), 188 deletions(-) delete mode 100644 zpu/hdl/zpu4/src/sim_small_fpga_top.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index 7a2601f..9e65929 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -59,8 +59,9 @@ begin elsif (clk'event and clk = '1') then -- timer_we <= '0'; if writeEnable = '1' then - -- external interface - if addr=x"2028003" then + -- external interface (fixed address) + -- extend compare to avoid waring messages + if ("000" & addr)=x"2028003" then -- Write to UART -- report "" & character'image(conv_integer(memBint)) severity note; print(l_file, character'val(to_integer(unsigned(write)))); @@ -69,24 +70,26 @@ begin -- timer_we <= '1'; else print(l_file, character'val(to_integer(unsigned(write)))); - report "Illegal IO write" severity warning; + -- report "Illegal IO write" severity warning; end if; end if; read <= (others => '0'); if (readEnable = '1') then - if addr=x"1001" then + -- extend compare to avoid waring messages + if ("000" & addr)=x"0001001" then read <= (0=>'1', others => '0'); -- recieve empty elsif addr(12)='1' then read(7 downto 0) <= timer_read; elsif addr(11)='1' then read(7 downto 0) <= ZPU_Frequency; - elsif addr=x"2028003" then + -- extend compare to avoid waring messages + elsif ("000" & addr)=x"2028003" then read <= (others => '0'); else read <= (others => '0'); read(8) <= '1'; - report "Illegal IO read" severity warning; + -- report "Illegal IO read" severity warning; end if; end if; end if; diff --git a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd deleted file mode 100644 index 5c05881..0000000 --- a/zpu/hdl/zpu4/src/sim_small_fpga_top.vhd +++ /dev/null @@ -1,177 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity fpga_top is -end fpga_top; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal enable : std_logic; - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - -signal io_busy : std_logic; - -signal io_mem_read : std_logic_vector(wordSize-1 downto 0); -signal io_mem_writeEnable : std_logic; -signal io_mem_readEnable : std_logic; - - -signal dram_ready : std_logic; -signal io_ready : std_logic; -signal io_reading : std_logic; - - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_core port map ( - clk => clk , - areset => areset, - enable => enable, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_mem_writeEnable, - readEnable => io_mem_readEnable, - write => mem_write, - read => io_mem_read, - addr => mem_addr(maxAddrBit downto minAddrBit) - ); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); - io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy; - - - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(dram_mem_read, dram_ready, io_ready, io_mem_read) - begin - mem_read <= (others => 'U'); - if dram_ready='1' then - mem_read <= dram_mem_read; - end if; - - if io_ready='1' then - mem_read <= (others => '0'); - mem_read <= io_mem_read; - end if; - end process; - - - io_ready <= (io_reading or io_mem_readEnable) and not io_busy; - - memoryControlSync: - process(clk, areset) - begin - if areset = '1' then - enable <= '0'; - io_reading <= '0'; - dram_ready <= '0'; - elsif (clk'event and clk = '1') then - enable <= '1'; - io_reading <= io_busy or io_mem_readEnable; - dram_ready<=dram_mem_readEnable; - - end if; - end process; - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd index 0d734d2..9cda01c 100644 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/src/zpu_core_small.vhd @@ -125,6 +125,11 @@ signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); signal memBRead_stdlogic : std_logic_vector(memBRead'range); +-- debug +subtype index is integer range 0 to 3; +signal tOpcode_sel : index; + + begin traceFileGenerate: if Generate_Trace generate @@ -141,6 +146,8 @@ begin ); end generate; + -- not used in this design + mem_writeMask <= (others => '1'); memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); memAWrite_stdlogic <= std_logic_vector(memAWrite); @@ -160,14 +167,23 @@ begin memARead <= unsigned(memARead_stdlogic); memBRead <= unsigned(memBRead_stdlogic); +tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); decodeControl: - process(memBRead, pc) + process(memBRead, pc,tOpcode_sel) variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); begin - tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); - + -- not worked with synopsys + -- tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); + -- use full case + case (tOpcode_sel) is + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; sampledOpcode <= tOpcode; if (tOpcode(7 downto 7)=OpCode_Im) then @@ -230,7 +246,8 @@ begin out_mem_readEnable <= '0'; memAWrite <= (others => '0'); memBWrite <= (others => '0'); - mem_writeMask <= (others => '1'); + -- avoid Latch in synopsys + -- mem_writeMask <= (others => '1'); elsif (clk'event and clk = '1') then memAWriteEnable <= '0'; memBWriteEnable <= '0'; diff --git a/zpu/hdl/zpu4/test/interrupt/int.c b/zpu/hdl/zpu4/test/interrupt/int.c index 2be6483..1b6ec01 100644 --- a/zpu/hdl/zpu4/test/interrupt/int.c +++ b/zpu/hdl/zpu4/test/interrupt/int.c @@ -6,7 +6,10 @@ int counter; -/* Example of single, fixed interval non-maskable, nested interrupt */ +/* Example of single, fixed interval non-maskable, nested interrupt. The interrupt signal is + * held high for enough cycles to guarantee that it will be noticed, i.e. longer than + * any io access + 4 cycles roughly. + */ void _zpu_interrupt(void) { /* interrupts are enabled so we need to finish up quickly, -- cgit v1.1 From b93ac48f3c323a11a97a39338897c521780a16b9 Mon Sep 17 00:00:00 2001 From: oharboe Date: Sun, 4 May 2008 20:44:27 +0000 Subject: * moved ZPU core files to seperate folder * deleted some obsolete files --- zpu/hdl/zpu4/core/zpu_config.vhd | 16 + zpu/hdl/zpu4/core/zpu_core.vhd | 897 +++++++++++++++++++++++++++++++ zpu/hdl/zpu4/core/zpu_core_small.vhd | 464 ++++++++++++++++ zpu/hdl/zpu4/core/zpu_core_small_wip.vhd | 497 +++++++++++++++++ zpu/hdl/zpu4/core/zpupkg.vhd | 170 ++++++ zpu/hdl/zpu4/src/dmipssmalltrace.do | 26 - zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh | 26 - zpu/hdl/zpu4/src/dmipstrace.do | 30 -- zpu/hdl/zpu4/src/dmipstrace_ghdl.sh | 25 - zpu/hdl/zpu4/src/log.txt | 380 ------------- zpu/hdl/zpu4/src/niltrace.vhd | 26 - zpu/hdl/zpu4/src/sim_fpga_top.vhd | 188 ------- zpu/hdl/zpu4/src/simzpu_medium.do | 28 - zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh | 25 - zpu/hdl/zpu4/src/testlut.vhd | 114 ---- zpu/hdl/zpu4/src/zpu_config.vhd | 16 - zpu/hdl/zpu4/src/zpu_core.vhd | 897 ------------------------------- zpu/hdl/zpu4/src/zpu_core_small.vhd | 464 ---------------- zpu/hdl/zpu4/src/zpu_core_small_wip.vhd | 497 ----------------- zpu/hdl/zpu4/src/zpupkg.vhd | 170 ------ 20 files changed, 2044 insertions(+), 2912 deletions(-) create mode 100644 zpu/hdl/zpu4/core/zpu_config.vhd create mode 100644 zpu/hdl/zpu4/core/zpu_core.vhd create mode 100644 zpu/hdl/zpu4/core/zpu_core_small.vhd create mode 100644 zpu/hdl/zpu4/core/zpu_core_small_wip.vhd create mode 100644 zpu/hdl/zpu4/core/zpupkg.vhd delete mode 100644 zpu/hdl/zpu4/src/dmipssmalltrace.do delete mode 100644 zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh delete mode 100644 zpu/hdl/zpu4/src/dmipstrace.do delete mode 100644 zpu/hdl/zpu4/src/dmipstrace_ghdl.sh delete mode 100644 zpu/hdl/zpu4/src/log.txt delete mode 100644 zpu/hdl/zpu4/src/niltrace.vhd delete mode 100644 zpu/hdl/zpu4/src/sim_fpga_top.vhd delete mode 100644 zpu/hdl/zpu4/src/simzpu_medium.do delete mode 100644 zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh delete mode 100644 zpu/hdl/zpu4/src/testlut.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_config.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_core.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_core_small.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_core_small_wip.vhd delete mode 100644 zpu/hdl/zpu4/src/zpupkg.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd new file mode 100644 index 0000000..a13c0bf --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := 'X'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 15; + +end zpu_config; diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd new file mode 100644 index 0000000..37fa2d1 --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -0,0 +1,897 @@ + +-- Company: ZPU4 generic memory interface CPU +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + + + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +type InsnType is +( +State_AddTop, +State_Dup, +State_DupStackB, +State_Pop, +State_Popdown, +State_Add, +State_Or, +State_And, +State_Store, +State_AddSP, +State_Shift, +State_Nop, +State_Im, +State_LoadSP, +State_StoreSP, +State_Emulate, +State_Load, +State_PushPC, +State_PushSP, +State_PopPC, +State_PopPCRel, +State_Not, +State_Flip, +State_PopSP, +State_Neqbranch, +State_Eq, +State_Loadb, +State_Mult, +State_Lessthan, +State_Lessthanorequal, +State_Ulessthanorequal, +State_Ulessthan, +State_Pushspadd, +State_Call, +State_Callpcrel, +State_Sub, +State_Break, +State_Storeb, +State_InsnFetch +); + +type StateType is +( +State_Load2, +State_Popped, +State_LoadSP2, +State_LoadSP3, +State_AddSP2, +State_Fetch, +State_Execute, +State_Decode, +State_Decode2, +State_Resync, + +State_StoreSP2, +State_Resync2, +State_Resync3, +State_Loadb2, +State_Storeb2, +State_Mult2, +State_Mult3, +State_Mult5, +State_Mult4, +State_BinaryOpResult2, +State_BinaryOpResult, +State_Idle +); + + +signal pc : unsigned(maxAddrBitIncIO downto 0); +signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); +signal stackA : unsigned(wordSize-1 downto 0); +signal binaryOpResult : unsigned(wordSize-1 downto 0); +signal binaryOpResult2 : unsigned(wordSize-1 downto 0); +signal multResult2 : unsigned(wordSize-1 downto 0); +signal multResult3 : unsigned(wordSize-1 downto 0); +signal multResult : unsigned(wordSize-1 downto 0); +signal multA : unsigned(wordSize-1 downto 0); +signal multB : unsigned(wordSize-1 downto 0); +signal stackB : unsigned(wordSize-1 downto 0); +signal idim_flag : std_logic; +signal busy : std_logic; +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal mem_delayReadEnable : std_logic; + +signal decodeWord : std_logic_vector(wordSize-1 downto 0); + + +signal state : StateType; +signal insn : InsnType; +type InsnArray is array(0 to wordBytes-1) of InsnType; +signal decodedOpcode : InsnArray; + +type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + +signal opcode : OpcodeArray; + + + + +signal begin_inst : std_logic; +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. + +begin + + + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + + opcodeControl: + process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : unsigned(4 downto 0); + variable tSpOffset : unsigned(4 downto 0); + variable nextPC : unsigned(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + + mem_addr <= (others => DontCareValue); + mem_readEnable <='0'; + mem_writeEnable <='0'; + mem_write <= (others => DontCareValue); + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + + + spOffset(4):=not opcode(to_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0):=unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); + trace_pc <= std_logic_vector(pc); + trace_sp <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(stackA); + trace_topOfStackB <= std_logic_vector(stackB); + begin_inst <= '0'; + + + case state is + when State_Idle => + if enable='1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + when State_Resync => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(sp); + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + when State_Resync2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Resync3; + end if; + when State_Resync3 => + if in_mem_busy='0' then + stackB <= unsigned(mem_read); + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Decode => + if in_mem_busy='0' then + decodeWord <= mem_read; + state <= State_Decode2; + end if; + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4):=not tOpcode(4); + tSpOffset(3 downto 0):=unsigned(tOpcode(3 downto 0)); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7)=OpCode_Im) then + tNextState:=State_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset=1 then + tNextState := State_PopDown; + else + tNextState :=State_StoreSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState :=State_Dup; + elsif tSpOffset = 1 then + tNextState :=State_DupStackB; + else + tNextState :=State_LoadSP; + end if; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + tNextState :=State_Emulate; + if tOpcode(5 downto 0)=OpCode_Neqbranch then + tNextState :=State_Neqbranch; + elsif tOpcode(5 downto 0)=OpCode_Eq then + tNextState :=State_Eq; + elsif tOpcode(5 downto 0)=OpCode_Lessthan then + tNextState :=State_Lessthan; + elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Ulessthan then + tNextState :=State_Ulessthan; + elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0)=OpCode_Loadb then + tNextState :=State_Loadb; + elsif tOpcode(5 downto 0)=OpCode_Mult then + tNextState :=State_Mult; + elsif tOpcode(5 downto 0)=OpCode_Storeb then + tNextState :=State_Storeb; + elsif tOpcode(5 downto 0)=OpCode_Pushspadd then + tNextState :=State_Pushspadd; + elsif tOpcode(5 downto 0)=OpCode_Callpcrel then + tNextState :=State_Callpcrel; + elsif tOpcode(5 downto 0)=OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0)=OpCode_Sub then + tNextState :=State_Sub; + elsif tOpcode(5 downto 0)=OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState :=State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState :=State_Nop; + when OpCode_PushSP => + tNextState :=State_PushSP; + when OpCode_PopPC => + tNextState :=State_PopPC; + when OpCode_Add => + tNextState :=State_Add; + when OpCode_Or => + tNextState :=State_Or; + when OpCode_And => + tNextState :=State_And; + when OpCode_Load => + tNextState :=State_Load; + when OpCode_Not => + tNextState :=State_Not; + when OpCode_Flip => + tNextState :=State_Flip; + when OpCode_Store => + tNextState :=State_Store; + when OpCode_PopSP => + tNextState :=State_PopSP; + when others => + tNextState := State_Break; + + end case; + end if; + tDecodedOpcode(i) := tNextState; + + end loop; + + insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); + + case insn is + when State_InsnFetch => + state <= State_Fetch; + when State_Im => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag='1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + else + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + end if; + end if; + when State_StoreSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + mem_write <= std_logic_vector(stackA); + stackA <= stackB; + sp <= incSp; + end if; + + + when State_LoadSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_Emulate => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); + state <= State_Fetch; + end if; + when State_Callpcrel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_Call => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + when State_AddSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + end if; + when State_PushSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + when State_PopPC => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_PopPCRel => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + when State_Add => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Sub => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + when State_Pop => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + when State_PopDown => + if in_mem_busy='0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + when State_Or => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_And => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_Eq => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Ulessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA<=stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Lessthan => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA)<=signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + when State_Load => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when State_Dup => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_DupStackB => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + when State_Store => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= std_logic_vector(stackB); + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_PopSP => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + end if; + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB/=0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + when State_Storeb => + if in_mem_busy='0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + end case; + + + when State_StoreSP2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Popped; + end if; + when State_LoadSP2 => + if in_mem_busy='0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset+1); + end if; + when State_LoadSP3 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= unsigned(mem_read); + end if; + when State_AddSP2 => + if in_mem_busy='0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + unsigned(mem_read); + end if; + when State_Load2 => + if in_mem_busy='0' then + stackA <= unsigned(mem_read); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Loadb2 => + if in_mem_busy='0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); + pc <= pc + 1; + state <= State_Execute; + end if; + when State_Storeb2 => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= mem_read; + mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + when State_Fetch => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + when State_Mult2 => + state <= State_Mult3; + when State_Mult3 => + state <= State_Mult4; + when State_Mult4 => + state <= State_Mult5; + when State_Mult5 => + if in_mem_busy='0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + when State_Popped => + if in_mem_busy='0' then + pc <= pc + 1; + stackB <= unsigned(mem_read); + state <= State_Execute; + end if; + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + end case; + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd new file mode 100644 index 0000000..9cda01c --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -0,0 +1,464 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : unsigned(maxAddrBit downto minAddrBit); +signal memAWrite : unsigned(wordSize-1 downto 0); +signal memARead : unsigned(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : unsigned(maxAddrBit downto minAddrBit); +signal memBWrite : unsigned(wordSize-1 downto 0); +signal memBRead : unsigned(wordSize-1 downto 0); + + + +signal pc : unsigned(maxAddrBit downto 0); +signal sp : unsigned(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. +type State_Type is +( +State_Fetch, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_FetchNext, +State_AddSP, +State_ReadIODone, +State_Decode, +State_Resync +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP , +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP +); + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; +signal sampledDecodedOpcode : DecodedOpcodeType; + + +signal state : State_Type; + +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; +signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); +signal memARead_stdlogic : std_logic_vector(memARead'range); +signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); +signal memBRead_stdlogic : std_logic_vector(memBRead'range); + +-- debug +subtype index is integer range 0 to 3; +signal tOpcode_sel : index; + + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + -- not used in this design + mem_writeMask <= (others => '1'); + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic + ); + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); + +tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + decodeControl: + process(memBRead, pc,tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + -- not worked with synopsys + -- tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); + -- use full case + case (tOpcode_sel) is + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + -- avoid Latch in synopsys + -- mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd new file mode 100644 index 0000000..8d87804 --- /dev/null +++ b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd @@ -0,0 +1,497 @@ +-- Company: ZPU3 +-- Engineer: Øyvind Harboe + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is + Port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); +end zpu_core; + +architecture behave of zpu_core is + +signal readIO : std_logic; + + + +signal memAWriteEnable : std_logic; +signal memAAddr : unsigned(maxAddrBit downto minAddrBit); +signal memAWrite : unsigned(wordSize-1 downto 0); +signal memARead : unsigned(wordSize-1 downto 0); +signal memBWriteEnable : std_logic; +signal memBAddr : unsigned(maxAddrBit downto minAddrBit); +signal memBWrite : unsigned(wordSize-1 downto 0); +signal memBRead : unsigned(wordSize-1 downto 0); + + + +signal pc : unsigned(maxAddrBit downto 0); +signal sp : unsigned(maxAddrBit downto minAddrBit); + +signal idim_flag : std_logic; + +--signal storeToStack : std_logic; +--signal fetchNextInstruction : std_logic; +--signal extraCycle : std_logic; +signal busy : std_logic; +--signal fetching : std_logic; + +signal begin_inst : std_logic; + + + +signal trace_opcode : std_logic_vector(7 downto 0); +signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); +signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); +signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); +signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + +-- state machine. +type State_Type is +( +State_Fetch, +State_WriteIODone, +State_Execute, +State_StoreToStack, +State_Add, +State_Or, +State_And, +State_Store, +State_ReadIO, +State_WriteIO, +State_Load, +State_FetchNext, +State_AddSP, +State_ReadIODone, +State_Decode, +State_Resync, +State_Interrupt + +); + +type DecodedOpcodeType is +( +Decoded_Nop, +Decoded_Im, +Decoded_ImShift, +Decoded_LoadSP, +Decoded_StoreSP , +Decoded_AddSP, +Decoded_Emulate, +Decoded_Break, +Decoded_PushSP, +Decoded_PopPC, +Decoded_Add, +Decoded_Or, +Decoded_And, +Decoded_Load, +Decoded_Not, +Decoded_Flip, +Decoded_Store, +Decoded_PopSP +); + + + +signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); +signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + +signal decodedOpcode : DecodedOpcodeType; +signal sampledDecodedOpcode : DecodedOpcodeType; + + +signal state : State_Type; + +subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; +signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); +signal memARead_stdlogic : std_logic_vector(memARead'range); +signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); +signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); +signal memBRead_stdlogic : std_logic_vector(memBRead'range); + +subtype index is integer range 0 to 3; + +signal tOpcode_sel : index; + + +signal inInterrupt : std_logic; + + + +begin + traceFileGenerate: + if Generate_Trace generate + trace_file: trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + + -- not used in this design + + mem_writeMask <= (others => '1'); + + + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + memory: dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic + ); + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); + + + + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + + decodeControl: + process(memBRead, pc,tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + + -- simplify opcode selection a bit so it passes more synthesizers + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7)=OpCode_Im) then + sampledDecodedOpcode<=Decoded_Im; + elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then + sampledDecodedOpcode<=Decoded_StoreSP; + elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then + sampledDecodedOpcode<=Decoded_LoadSP; + elsif (tOpcode(7 downto 5)=OpCode_Emulate) then + sampledDecodedOpcode<=Decoded_Emulate; + elsif (tOpcode(7 downto 4)=OpCode_AddSP) then + sampledDecodedOpcode<=Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode<=Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode<=Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode<=Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode<=Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode<=Decoded_Or; + when OpCode_And => + sampledDecodedOpcode<=Decoded_And; + when OpCode_Load => + sampledDecodedOpcode<=Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode<=Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode<=Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode<=Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode<=Decoded_PopSP; + when others => + sampledDecodedOpcode<=Decoded_Nop; + end case; + end if; + end process; + + + opcodeControl: + process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + inInterrupt <= '0'; + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4):=not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + case decodedOpcode is + when Decoded_Interrupt => + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBitIncIO downto 0) <= pc; + pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address + report "ZPU jumped to interrupt!" severity note; + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag='0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + when Decoded_And => + sp <= sp + 1; + state <= State_And; + when Decoded_Load => + if (memARead(ioBit)='1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit)='1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + when Decoded_Nop => + memAAddr <= sp; + when others => + null; + end case; + when State_ReadIO => + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + when State_Decode => + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + decodedOpcode <= Decoded_Interrupt; + end if; + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + when State_AddSP => + state <= State_Add; + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + when others => + null; + end case; + + end if; + end process; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd new file mode 100644 index 0000000..f3800b0 --- /dev/null +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -0,0 +1,170 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; + +package zpupkg is + + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + + component dualport_ram is + port (clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0)); + end component; + + + component dram is + port (clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); + end component; + + + component trace is + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component; + + component zpu_core is + port ( clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic); + end component; + + + + component timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); + end component; + + component zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); + end component; + + + + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); + + constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); + constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); + + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); + constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); + + constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); + constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); + + constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); + + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); + + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); + + + + constant OpCode_Size : integer := 8; + + + +end zpupkg; diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace.do b/zpu/hdl/zpu4/src/dmipssmalltrace.do deleted file mode 100644 index eb4c6fe..0000000 --- a/zpu/hdl/zpu4/src/dmipssmalltrace.do +++ /dev/null @@ -1,26 +0,0 @@ -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core_small.vhd -vcom -93 -explicit bram_dmips.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -add wave -recursive fpga_top/zpu/* -#--add wave -recursive fpga_top/ioMap/* -#add wave -recursive fpga_top/* -view structure - - -# run ZPU -run 5 ms diff --git a/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh deleted file mode 100644 index 5e43b64..0000000 --- a/zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh - -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" -MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" - -if test ! -e work; then - echo "Building work library..." - mkdir work - ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd - ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd - ghdl -i ${IMPORT_OPTIONS} txt_util.vhd - ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd - ghdl -i ${IMPORT_OPTIONS} zpu_core_small.vhd - ghdl -i ${IMPORT_OPTIONS} bram_dmips.vhd - ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd - ghdl -i ${IMPORT_OPTIONS} timer.vhd - ghdl -i ${IMPORT_OPTIONS} io.vhd - ghdl -i ${IMPORT_OPTIONS} trace.vhd -fi - -echo "Compiling design..." -if ghdl -m ${MAKE_OPTIONS} fpga_top; then - echo "Compilation finished, start simulation with" - echo " ./fpga_top --stop-time=1ms" -fi diff --git a/zpu/hdl/zpu4/src/dmipstrace.do b/zpu/hdl/zpu4/src/dmipstrace.do deleted file mode 100644 index 64cf8fd..0000000 --- a/zpu/hdl/zpu4/src/dmipstrace.do +++ /dev/null @@ -1,30 +0,0 @@ -# Xilinx WebPack modelsim script -# -# cd C:/workspace/zpu/zpu/hdl/zpu4/src -# do dmipstrace.do - -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_dmips.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - - -vsim fpga_top -view wave - -add wave -recursive fpga_top/zpu/* -#--add wave -recursive fpga_top/ioMap/* -#add wave -recursive fpga_top/* -view structure - - -# run ZPU -run 5 ms diff --git a/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh b/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh deleted file mode 100644 index 3be392f..0000000 --- a/zpu/hdl/zpu4/src/dmipstrace_ghdl.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh - -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" -MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" - -if test ! -e work; then - echo "Building work library..." - mkdir work - ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd - ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd - ghdl -i ${IMPORT_OPTIONS} txt_util.vhd - ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd - ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd - ghdl -i ${IMPORT_OPTIONS} dram_dmips.vhd - ghdl -i ${IMPORT_OPTIONS} timer.vhd - ghdl -i ${IMPORT_OPTIONS} io.vhd - ghdl -i ${IMPORT_OPTIONS} trace.vhd -fi - -echo "Compiling design..." -if ghdl -m ${MAKE_OPTIONS} fpga_top; then - echo "Compilation finished, start simulation with" - echo " ./fpga_top --stop-time=2500us" -fi diff --git a/zpu/hdl/zpu4/src/log.txt b/zpu/hdl/zpu4/src/log.txt deleted file mode 100644 index 7a82879..0000000 --- a/zpu/hdl/zpu4/src/log.txt +++ /dev/null @@ -1,380 +0,0 @@ -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -1 - - - - - - -H -e -l -l -o - -w -o -r -l -d - -2 - - - - - - diff --git a/zpu/hdl/zpu4/src/niltrace.vhd b/zpu/hdl/zpu4/src/niltrace.vhd deleted file mode 100644 index 40fc1ca..0000000 --- a/zpu/hdl/zpu4/src/niltrace.vhd +++ /dev/null @@ -1,26 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -use std.textio.all; -use work.zpu_config.all; - - -entity trace is - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBit downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBit downto 2); - memA : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic); -end trace; - - -architecture behave of trace is - -begin - -end behave; - diff --git a/zpu/hdl/zpu4/src/sim_fpga_top.vhd b/zpu/hdl/zpu4/src/sim_fpga_top.vhd deleted file mode 100644 index 29151af..0000000 --- a/zpu/hdl/zpu4/src/sim_fpga_top.vhd +++ /dev/null @@ -1,188 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:15:31 04/14/05 --- Design Name: --- Module Name: fpga_top - behave --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.zpu_config.all; - -entity fpga_top is -end fpga_top; - -use work.zpupkg.all; - -architecture behave of fpga_top is - - -signal clk : std_logic; - -signal areset : std_logic; - - -component zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end component; - - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal enable : std_logic; - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - -signal io_busy : std_logic; - -signal io_mem_read : std_logic_vector(wordSize-1 downto 0); -signal io_mem_writeEnable : std_logic; -signal io_mem_readEnable : std_logic; - - -signal dram_ready : std_logic; -signal io_ready : std_logic; -signal io_reading : std_logic; - - -signal break : std_logic; - -begin - poweronreset: roc port map (O => areset); - - - - zpu: zpu_core port map ( - clk => clk , - areset => areset, - enable => enable, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - dram_imp: dram port map ( - clk => clk , - areset => areset, - mem_busy => dram_mem_busy, - mem_read => dram_mem_read, - mem_write => mem_write, - mem_addr => mem_addr(maxAddrBit downto 0), - mem_writeEnable => dram_mem_writeEnable, - mem_readEnable => dram_mem_readEnable, - mem_writeMask => mem_writeMask); - - - ioMap: zpu_io port map ( - clk => clk, - areset => areset, - busy => io_busy, - writeEnable => io_mem_writeEnable, - readEnable => io_mem_readEnable, - write => mem_write(wordSize-1 downto 0), - read => io_mem_read, - addr => mem_addr(maxAddrBit downto minAddrBit) - ); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit); - io_mem_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy or dram_mem_busy or io_busy; - - - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(dram_mem_read, dram_ready, io_ready, io_mem_read) - begin - mem_read <= (others => 'U'); - if dram_ready='1' then - mem_read <= dram_mem_read; - end if; - - if io_ready='1' then - mem_read <= io_mem_read; - end if; - end process; - - - io_ready <= (io_reading or io_mem_readEnable) and not io_busy; - - memoryControlSync: - process(clk, areset) - begin - if areset = '1' then - enable <= '0'; - io_reading <= '0'; - dram_ready <= '0'; - elsif (clk'event and clk = '1') then - enable <= '1'; - io_reading <= io_busy or io_mem_readEnable; - dram_ready<=dram_mem_readEnable; - - end if; - end process; - - -- wiggle the clock @ 100MHz - clock : PROCESS - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end PROCESS clock; - - -end behave; diff --git a/zpu/hdl/zpu4/src/simzpu_medium.do b/zpu/hdl/zpu4/src/simzpu_medium.do deleted file mode 100644 index a6c1fe2..0000000 --- a/zpu/hdl/zpu4/src/simzpu_medium.do +++ /dev/null @@ -1,28 +0,0 @@ -# Xilinx WebPack modelsim script -# -# cd C:/workspace/zpu/zpu/hdl/zpu4/src -# do simzpu_medium.do - -set BreakOnAssertion 1 -vlib work - -vcom -93 -explicit zpu_config_trace.vhd -vcom -93 -explicit zpupkg.vhd -vcom -93 -explicit txt_util.vhd -vcom -93 -explicit sim_fpga_top.vhd -vcom -93 -explicit zpu_core.vhd -vcom -93 -explicit dram_hello.vhd -vcom -93 -explicit timer.vhd -vcom -93 -explicit io.vhd -vcom -93 -explicit trace.vhd - -# run ZPU -vsim fpga_top -view wave -add wave -recursive fpga_top/zpu/* -#add wave -recursive fpga_top/* -view structure -#view signals - -# Enough to run tiny programs -run 1000 ms diff --git a/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh b/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh deleted file mode 100644 index 7a7f3df..0000000 --- a/zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh - -UNISIM_DIR="'location of GHDL objects for unisim library'/unisim_v93" -IMPORT_OPTIONS="--std=93 --ieee=synopsys --workdir=work -P${UNISIM_DIR}" -MAKE_OPTIONS="${IMPORT_OPTIONS} -Wl,-s -fexplicit --syn-binding" - -if test ! -e work; then - echo "Building work library..." - mkdir work - ghdl -i ${IMPORT_OPTIONS} zpu_config_trace.vhd - ghdl -i ${IMPORT_OPTIONS} zpupkg.vhd - ghdl -i ${IMPORT_OPTIONS} txt_util.vhd - ghdl -i ${IMPORT_OPTIONS} sim_fpga_top.vhd - ghdl -i ${IMPORT_OPTIONS} zpu_core.vhd - ghdl -i ${IMPORT_OPTIONS} dram_hello.vhd - ghdl -i ${IMPORT_OPTIONS} timer.vhd - ghdl -i ${IMPORT_OPTIONS} io.vhd - ghdl -i ${IMPORT_OPTIONS} trace.vhd -fi - -echo "Compiling design..." -if ghdl -m ${MAKE_OPTIONS} fpga_top; then - echo "Compilation finished, start simulation with" - echo " ./fpga_top --stop-time=1ms" -fi diff --git a/zpu/hdl/zpu4/src/testlut.vhd b/zpu/hdl/zpu4/src/testlut.vhd deleted file mode 100644 index 668efcc..0000000 --- a/zpu/hdl/zpu4/src/testlut.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- Company: Zylin AS --- --- Hooks up the ZPU to physical pads to ensure that it is not optimized to --- oblivion. This is purely to have something to measure LUT usage against. --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity ic300 is - port ( -- Clock inputs - cpu_clk_p : in std_logic; - - -- CPU interface signals - cpu_a_p : in std_logic_vector(20 downto 0); - cpu_wr_n_p : in std_logic_vector(1 downto 0); - cpu_cs_n_p : in std_logic_vector(3 downto 1); - cpu_oe_n_p : in std_logic; - cpu_d_p : out std_logic_vector(15 downto 0); - cpu_irq_p : out std_logic_vector(1 downto 0); - cpu_fiq_p : out std_logic; - cpu_wait_n_p : out std_logic; - - sdr_clk_fb_p : in std_logic -- DDR clock feedback - ); -end ic300; - -architecture behave of ic300 is - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); -signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal io_readEnable : std_logic; - - -signal cpu_we : std_logic_vector(1 downto 0); -signal cpu_re : std_logic; -signal areset : std_logic; - --- Clock module signals -signal clk_status : std_logic_vector(2 downto 0); -signal cpu_clk : std_logic; -signal cpu_clk_2x : std_logic; -signal cpu_clk_4x : std_logic; -signal ddr_in_clk : std_logic; - - --- Internal CPU interface signals -signal cpu_din : std_logic_vector(15 downto 0); -signal cpu_dout : std_logic_vector(15 downto 0); -signal cpu_a : std_logic_vector(20 downto 0); - -signal dummy : std_logic_vector(maxAddrBit downto minAddrBit+5); - -signal dummy2 : std_logic_vector(wordSize-1 downto 0); -signal dummy3 : std_logic_vector(wordSize-1 downto 0); -signal dummy4 : std_logic_vector(wordSize-1 downto 0); -begin - - areset <= '0'; -- MUST BE CHANGED TO SOMETHING CORRECT - --- cpu_d_p <= (others => '0'); - cpu_irq_p <= (others => '0'); - cpu_fiq_p <= '0'; - cpu_wait_n_p <= '0'; - - cpu_d_p(15 downto 15) <= (others => '0'); - - -- delay signals going out/in w/1 clk so the - -- ZPU does not have to drive those pins. - -- - -- these registers can be placed close to the ZPU and these - -- registers then have a full clock to drive the pins. - process(cpu_clk_p, areset) - begin - if (cpu_clk_p'event and cpu_clk_p = '1') then - cpu_d_p(0) <= io_writeEnable; - cpu_d_p(1) <= io_readEnable; - cpu_d_p(9 downto 2) <= io_write; - io_read <= cpu_a_p(7 downto 0); - -- 32 read/write registers is plenty realisitic for a minimal size - -- soft-CPU - cpu_d_p(14 downto 10) <= io_addr(minAddrBit+4 downto minAddrBit); - end if; - end process; - - - zpu: zpu_core port map ( - clk => cpu_clk_p , - areset => areset, - enable => '1', - - in_mem_busy => '0', - out_mem_writeEnable => io_writeEnable, - out_mem_readEnable => io_readEnable, - mem_write(7 downto 0) => io_write, - mem_write(wordSize-1 downto 8) => dummy3(wordSize-1 downto 8), - mem_read(7 downto 0) => io_read, - mem_read(wordSize-1 downto 8) => dummy2(wordSize-1 downto 8), - out_mem_addr(maxAddrBitIncIO) => dummy4(maxAddrBitIncIO), - out_mem_addr(minAddrBit-1 downto 0) => dummy4(minAddrBit-1 downto 0) , - out_mem_addr(maxAddrBit downto minAddrBit) => io_addr, - interrupt => '0' - ); - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpu_config.vhd b/zpu/hdl/zpu4/src/zpu_config.vhd deleted file mode 100644 index a13c0bf..0000000 --- a/zpu/hdl/zpu4/src/zpu_config.vhd +++ /dev/null @@ -1,16 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -package zpu_config is - -- generate trace output or not. - constant Generate_Trace : boolean := false; - constant wordPower : integer := 5; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := 'X'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; - -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) - constant maxAddrBitIncIO : integer := 15; - -end zpu_config; diff --git a/zpu/hdl/zpu4/src/zpu_core.vhd b/zpu/hdl/zpu4/src/zpu_core.vhd deleted file mode 100644 index 37fa2d1..0000000 --- a/zpu/hdl/zpu4/src/zpu_core.vhd +++ /dev/null @@ -1,897 +0,0 @@ - --- Company: ZPU4 generic memory interface CPU --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - --- mem_writeEnable - set to '1' for a single cycle to send off a write request. --- mem_write is valid only while mem_writeEnable='1'. --- mem_readEnable - set to '1' for a single cycle to send off a read request. --- --- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. --- Set to '0' when mem_read is valid after a read request. --- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable --- is '1'. --- mem_addr - address for read/write request --- mem_read - read data. Valid only on the cycle after mem_busy='0' after --- mem_readEnable='1' for a single cycle. --- mem_write - data to write --- mem_writeMask - set to '1' for those bits that are to be written to memory upon --- write request --- break - set to '1' when CPU hits break instruction --- interrupt - set to '1' until interrupts are cleared by CPU. - - - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -type InsnType is -( -State_AddTop, -State_Dup, -State_DupStackB, -State_Pop, -State_Popdown, -State_Add, -State_Or, -State_And, -State_Store, -State_AddSP, -State_Shift, -State_Nop, -State_Im, -State_LoadSP, -State_StoreSP, -State_Emulate, -State_Load, -State_PushPC, -State_PushSP, -State_PopPC, -State_PopPCRel, -State_Not, -State_Flip, -State_PopSP, -State_Neqbranch, -State_Eq, -State_Loadb, -State_Mult, -State_Lessthan, -State_Lessthanorequal, -State_Ulessthanorequal, -State_Ulessthan, -State_Pushspadd, -State_Call, -State_Callpcrel, -State_Sub, -State_Break, -State_Storeb, -State_InsnFetch -); - -type StateType is -( -State_Load2, -State_Popped, -State_LoadSP2, -State_LoadSP3, -State_AddSP2, -State_Fetch, -State_Execute, -State_Decode, -State_Decode2, -State_Resync, - -State_StoreSP2, -State_Resync2, -State_Resync3, -State_Loadb2, -State_Storeb2, -State_Mult2, -State_Mult3, -State_Mult5, -State_Mult4, -State_BinaryOpResult2, -State_BinaryOpResult, -State_Idle -); - - -signal pc : unsigned(maxAddrBitIncIO downto 0); -signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal stackA : unsigned(wordSize-1 downto 0); -signal binaryOpResult : unsigned(wordSize-1 downto 0); -signal binaryOpResult2 : unsigned(wordSize-1 downto 0); -signal multResult2 : unsigned(wordSize-1 downto 0); -signal multResult3 : unsigned(wordSize-1 downto 0); -signal multResult : unsigned(wordSize-1 downto 0); -signal multA : unsigned(wordSize-1 downto 0); -signal multB : unsigned(wordSize-1 downto 0); -signal stackB : unsigned(wordSize-1 downto 0); -signal idim_flag : std_logic; -signal busy : std_logic; -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayReadEnable : std_logic; - -signal decodeWord : std_logic_vector(wordSize-1 downto 0); - - -signal state : StateType; -signal insn : InsnType; -type InsnArray is array(0 to wordBytes-1) of InsnType; -signal decodedOpcode : InsnArray; - -type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); - -signal opcode : OpcodeArray; - - - - -signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -begin - - - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - -- the memory subsystem will tell us one cycle later whether or - -- not it is busy - out_mem_writeEnable <= mem_writeEnable; - out_mem_readEnable <= mem_readEnable; - out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; - out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); - - incSp <= sp + 1; - incIncSp <= sp + 2; - decSp <= sp - 1; - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : unsigned(4 downto 0); - variable tSpOffset : unsigned(4 downto 0); - variable nextPC : unsigned(maxAddrBitIncIO downto 0); - variable tNextState : InsnType; - variable tDecodedOpcode : InsnArray; - variable tMultResult : unsigned(wordSize*2-1 downto 0); - begin - if areset = '1' then - state <= State_Idle; - break <= '0'; - sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); - - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - mem_writeEnable <= '0'; - mem_readEnable <= '0'; - multA <= (others => '0'); - multB <= (others => '0'); - mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then - -- we must multiply unconditionally to get pipelined multiplication - tMultResult := multA * multB; - multResult3 <= multResult2; - multResult2 <= multResult; - multResult <= tMultResult(wordSize-1 downto 0); - - - binaryOpResult2 <= binaryOpResult; -- pipeline a bit. - - - multA <= (others => DontCareValue); - multB <= (others => DontCareValue); - - - mem_addr <= (others => DontCareValue); - mem_readEnable <='0'; - mem_writeEnable <='0'; - mem_write <= (others => DontCareValue); - - if (mem_writeEnable = '1') and (mem_readEnable = '1') then - report "read/write collision" severity failure; - end if; - - - - - spOffset(4):=not opcode(to_integer(pc(byteBits-1 downto 0)))(4); - spOffset(3 downto 0):=unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); - nextPC := pc + 1; - - -- prepare trace snapshot - trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); - trace_pc <= std_logic_vector(pc); - trace_sp <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(stackA); - trace_topOfStackB <= std_logic_vector(stackB); - begin_inst <= '0'; - - - case state is - when State_Idle => - if enable='1' then - state <= State_Resync; - end if; - -- Initial state of ZPU, fetch top of stack + first instruction - when State_Resync => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(sp); - mem_readEnable <= '1'; - state <= State_Resync2; - end if; - when State_Resync2 => - if in_mem_busy='0' then - stackA <= unsigned(mem_read); - mem_addr <= std_logic_vector(incSp); - mem_readEnable <= '1'; - state <= State_Resync3; - end if; - when State_Resync3 => - if in_mem_busy='0' then - stackB <= unsigned(mem_read); - mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Decode => - if in_mem_busy='0' then - decodeWord <= mem_read; - state <= State_Decode2; - end if; - when State_Decode2 => - -- decode 4 instructions in parallel - for i in 0 to wordBytes-1 loop - tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); - - tSpOffset(4):=not tOpcode(4); - tSpOffset(3 downto 0):=unsigned(tOpcode(3 downto 0)); - - opcode(i) <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - tNextState:=State_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - if tSpOffset = 0 then - tNextState := State_Pop; - elsif tSpOffset=1 then - tNextState := State_PopDown; - else - tNextState :=State_StoreSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - if tSpOffset = 0 then - tNextState :=State_Dup; - elsif tSpOffset = 1 then - tNextState :=State_DupStackB; - else - tNextState :=State_LoadSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - tNextState :=State_Emulate; - if tOpcode(5 downto 0)=OpCode_Neqbranch then - tNextState :=State_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - tNextState :=State_Eq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - tNextState :=State_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - --tNextState :=State_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - tNextState :=State_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - --tNextState :=State_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - tNextState :=State_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Mult then - tNextState :=State_Mult; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - tNextState :=State_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - tNextState :=State_Pushspadd; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - tNextState :=State_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Call then - --tNextState :=State_Call; - elsif tOpcode(5 downto 0)=OpCode_Sub then - tNextState :=State_Sub; - elsif tOpcode(5 downto 0)=OpCode_PopPCRel then - --tNextState :=State_PopPCRel; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - if tSpOffset = 0 then - tNextState := State_Shift; - elsif tSpOffset = 1 then - tNextState := State_AddTop; - else - tNextState :=State_AddSP; - end if; - else - case tOpcode(3 downto 0) is - when OpCode_Nop => - tNextState :=State_Nop; - when OpCode_PushSP => - tNextState :=State_PushSP; - when OpCode_PopPC => - tNextState :=State_PopPC; - when OpCode_Add => - tNextState :=State_Add; - when OpCode_Or => - tNextState :=State_Or; - when OpCode_And => - tNextState :=State_And; - when OpCode_Load => - tNextState :=State_Load; - when OpCode_Not => - tNextState :=State_Not; - when OpCode_Flip => - tNextState :=State_Flip; - when OpCode_Store => - tNextState :=State_Store; - when OpCode_PopSP => - tNextState :=State_PopSP; - when others => - tNextState := State_Break; - - end case; - end if; - tDecodedOpcode(i) := tNextState; - - end loop; - - insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); - - -- once we wrap, we need to fetch - tDecodedOpcode(0) := State_InsnFetch; - - decodedOpcode <= tDecodedOpcode; - state <= State_Execute; - - - - -- Each instruction must: - -- - -- 1. set idim_flag - -- 2. increase pc if applicable - -- 3. set next state if appliable - -- 4. do it's operation - - when State_Execute => - insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); - - case insn is - when State_InsnFetch => - state <= State_Fetch; - when State_Im => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '1'; - pc <= pc + 1; - - if idim_flag='1' then - stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); - stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); - else - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - stackB <= stackA; - sp <= decSp; - for i in wordSize-1 downto 7 loop - stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); - end loop; - stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); - end if; - end if; - when State_StoreSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_StoreSP2; - - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(sp+spOffset); - mem_write <= std_logic_vector(stackA); - stackA <= stackB; - sp <= incSp; - end if; - - - when State_LoadSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_LoadSP2; - - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - end if; - when State_Emulate => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - stackB <= stackA; - - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); - state <= State_Fetch; - end if; - when State_Callpcrel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - - pc <= pc + stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_Call => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - pc <= stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_AddSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_AddSP2; - - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(sp+spOffset); - end if; - when State_PushSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= sp; - stackB <= stackA; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - end if; - when State_PopPC => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0); - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - state <= State_Resync; - end if; - when State_PopPCRel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - state <= State_Resync; - end if; - when State_Add => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA + stackB; - - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_Sub => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - binaryOpResult <= stackB - stackA; - state <= State_BinaryOpResult; - end if; - when State_Pop => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= std_logic_vector(incIncSp); - mem_readEnable <= '1'; - sp <= incSp; - stackA <= stackB; - state <= State_Popped; - end if; - when State_PopDown => - if in_mem_busy='0' then - -- PopDown leaves top of stack unchanged - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= std_logic_vector(incIncSp); - mem_readEnable <= '1'; - sp <= incSp; - state <= State_Popped; - end if; - when State_Or => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA or stackB; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_And => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - stackA <= stackA and stackB; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_Eq => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Ulessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA<=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Lessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA) - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA)<=signed(stackB)) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Load => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Load2; - - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - end if; - - when State_Dup => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackB <= stackA; - mem_write <= std_logic_vector(stackB); - mem_addr <= std_logic_vector(incSp); - mem_writeEnable <= '1'; - end if; - when State_DupStackB => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= stackB; - stackB <= stackA; - mem_write <= std_logic_vector(stackB); - mem_addr <= std_logic_vector(incSp); - mem_writeEnable <= '1'; - end if; - when State_Store => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_write <= std_logic_vector(stackB); - mem_writeEnable <= '1'; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_PopSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - mem_write <= std_logic_vector(stackB); - mem_addr <= std_logic_vector(incSp); - mem_writeEnable <= '1'; - sp <= stackA(maxAddrBitIncIO downto minAddrBit); - state <= State_Resync; - end if; - when State_Nop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - when State_Not => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= not stackA; - when State_Flip => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - for i in 0 to wordSize-1 loop - stackA(i) <= stackA(wordSize-1-i); - end loop; - when State_AddTop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= stackA + stackB; - when State_Shift => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); - stackA(0) <= '0'; - when State_Pushspadd => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; - when State_Neqbranch => - -- branches are almost always taken as they form loops - begin_inst <= '1'; - idim_flag <= '0'; - sp <= incIncSp; - if (stackB/=0) then - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - else - pc <= pc + 1; - end if; - -- need to fetch stack again. - state <= State_Resync; - when State_Mult => - begin_inst <= '1'; - idim_flag <= '0'; - - multA <= stackA; - multB <= stackB; - state <= State_Mult2; - when State_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - - when State_Loadb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Loadb2; - - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - end if; - when State_Storeb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Storeb2; - - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - end if; - - when others => - sp <= (others => DontCareValue); - report "Illegal instruction" severity failure; - break <= '1'; - end case; - - - when State_StoreSP2 => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(incSp); - mem_readEnable <= '1'; - state <= State_Popped; - end if; - when State_LoadSP2 => - if in_mem_busy='0' then - state <= State_LoadSP3; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(sp+spOffset+1); - end if; - when State_LoadSP3 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackB <= stackA; - stackA <= unsigned(mem_read); - end if; - when State_AddSP2 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackA <= stackA + unsigned(mem_read); - end if; - when State_Load2 => - if in_mem_busy='0' then - stackA <= unsigned(mem_read); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Loadb2 => - if in_mem_busy='0' then - stackA <= (others => '0'); - stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Storeb2 => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_write <= mem_read; - mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); - mem_writeEnable <= '1'; - pc <= pc + 1; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_Fetch => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Mult2 => - state <= State_Mult3; - when State_Mult3 => - state <= State_Mult4; - when State_Mult4 => - state <= State_Mult5; - when State_Mult5 => - if in_mem_busy='0' then - stackA <= multResult3; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_BinaryOpResult => - state <= State_BinaryOpResult2; - when State_BinaryOpResult2 => - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - stackA <= binaryOpResult2; - state <= State_Popped; - when State_Popped => - if in_mem_busy='0' then - pc <= pc + 1; - stackB <= unsigned(mem_read); - state <= State_Execute; - end if; - when others => - sp <= (others => DontCareValue); - report "Illegal state" severity failure; - break <= '1'; - end case; - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small.vhd b/zpu/hdl/zpu4/src/zpu_core_small.vhd deleted file mode 100644 index 9cda01c..0000000 --- a/zpu/hdl/zpu4/src/zpu_core_small.vhd +++ /dev/null @@ -1,464 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : unsigned(maxAddrBit downto minAddrBit); -signal memAWrite : unsigned(wordSize-1 downto 0); -signal memARead : unsigned(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : unsigned(maxAddrBit downto minAddrBit); -signal memBWrite : unsigned(wordSize-1 downto 0); -signal memBRead : unsigned(wordSize-1 downto 0); - - - -signal pc : unsigned(maxAddrBit downto 0); -signal sp : unsigned(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. -type State_Type is -( -State_Fetch, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_FetchNext, -State_AddSP, -State_ReadIODone, -State_Decode, -State_Resync -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP , -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP -); - - - -signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; -signal sampledDecodedOpcode : DecodedOpcodeType; - - -signal state : State_Type; - -subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; -signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); -signal memARead_stdlogic : std_logic_vector(memARead'range); -signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); -signal memBRead_stdlogic : std_logic_vector(memBRead'range); - --- debug -subtype index is integer range 0 to 3; -signal tOpcode_sel : index; - - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - -- not used in this design - mem_writeMask <= (others => '1'); - - memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); - memAWrite_stdlogic <= std_logic_vector(memAWrite); - memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); - memBWrite_stdlogic <= std_logic_vector(memBWrite); - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr_stdlogic, - memAWrite => memAWrite_stdlogic, - memARead => memARead_stdlogic, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr_stdlogic, - memBWrite => memBWrite_stdlogic, - memBRead => memBRead_stdlogic - ); - memARead <= unsigned(memARead_stdlogic); - memBRead <= unsigned(memBRead_stdlogic); - -tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - - - decodeControl: - process(memBRead, pc,tOpcode_sel) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - -- not worked with synopsys - -- tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); - -- use full case - case (tOpcode_sel) is - when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); - when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); - when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); - when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); - end case; - sampledOpcode <= tOpcode; - - if (tOpcode(7 downto 7)=OpCode_Im) then - sampledDecodedOpcode<=Decoded_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - sampledDecodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - sampledDecodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - sampledDecodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - sampledDecodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - sampledDecodedOpcode<=Decoded_Break; - when OpCode_PushSP => - sampledDecodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - sampledDecodedOpcode<=Decoded_PopPC; - when OpCode_Add => - sampledDecodedOpcode<=Decoded_Add; - when OpCode_Or => - sampledDecodedOpcode<=Decoded_Or; - when OpCode_And => - sampledDecodedOpcode<=Decoded_And; - when OpCode_Load => - sampledDecodedOpcode<=Decoded_Load; - when OpCode_Not => - sampledDecodedOpcode<=Decoded_Not; - when OpCode_Flip => - sampledDecodedOpcode<=Decoded_Flip; - when OpCode_Store => - sampledDecodedOpcode<=Decoded_Store; - when OpCode_PopSP => - sampledDecodedOpcode<=Decoded_PopSP; - when others => - sampledDecodedOpcode<=Decoded_Nop; - end case; - end if; - end process; - - - opcodeControl: - process(clk, areset) - variable spOffset : unsigned(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - -- avoid Latch in synopsys - -- mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); --- out_mem_addr <= (others => DontCareValue); --- mem_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - begin_inst <= '0'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - - decodedOpcode <= sampledDecodedOpcode; - opcode <= sampledOpcode; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); - trace_opcode <= opcode; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(memARead); - trace_topOfStackB <= std_logic_vector(memBRead); - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); - - idim_flag <= '0'; - case decodedOpcode is - when Decoded_Im => - idim_flag <= '1'; - memAWriteEnable <= '1'; - if (idim_flag='0') then - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - else - memAAddr <= sp; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - end if; - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(4 downto 0)); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (in_mem_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= unsigned(mem_read); - end if; - when State_WriteIO => - sp <= sp + 1; - out_mem_writeEnable <= '1'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd deleted file mode 100644 index 8d87804..0000000 --- a/zpu/hdl/zpu4/src/zpu_core_small_wip.vhd +++ /dev/null @@ -1,497 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : unsigned(maxAddrBit downto minAddrBit); -signal memAWrite : unsigned(wordSize-1 downto 0); -signal memARead : unsigned(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : unsigned(maxAddrBit downto minAddrBit); -signal memBWrite : unsigned(wordSize-1 downto 0); -signal memBRead : unsigned(wordSize-1 downto 0); - - - -signal pc : unsigned(maxAddrBit downto 0); -signal sp : unsigned(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. -type State_Type is -( -State_Fetch, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_FetchNext, -State_AddSP, -State_ReadIODone, -State_Decode, -State_Resync, -State_Interrupt - -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP , -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP -); - - - -signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; -signal sampledDecodedOpcode : DecodedOpcodeType; - - -signal state : State_Type; - -subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; -signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); -signal memARead_stdlogic : std_logic_vector(memARead'range); -signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); -signal memBRead_stdlogic : std_logic_vector(memBRead'range); - -subtype index is integer range 0 to 3; - -signal tOpcode_sel : index; - - -signal inInterrupt : std_logic; - - - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - - -- not used in this design - - mem_writeMask <= (others => '1'); - - - - memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); - memAWrite_stdlogic <= std_logic_vector(memAWrite); - memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); - memBWrite_stdlogic <= std_logic_vector(memBWrite); - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr_stdlogic, - memAWrite => memAWrite_stdlogic, - memARead => memARead_stdlogic, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr_stdlogic, - memBWrite => memBWrite_stdlogic, - memBRead => memBRead_stdlogic - ); - memARead <= unsigned(memARead_stdlogic); - memBRead <= unsigned(memBRead_stdlogic); - - - - tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - - - - decodeControl: - process(memBRead, pc,tOpcode_sel) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - - -- simplify opcode selection a bit so it passes more synthesizers - case (tOpcode_sel) is - - when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); - - when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); - - when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); - - when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - - when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); - end case; - - sampledOpcode <= tOpcode; - - if (tOpcode(7 downto 7)=OpCode_Im) then - sampledDecodedOpcode<=Decoded_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - sampledDecodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - sampledDecodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - sampledDecodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - sampledDecodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - sampledDecodedOpcode<=Decoded_Break; - when OpCode_PushSP => - sampledDecodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - sampledDecodedOpcode<=Decoded_PopPC; - when OpCode_Add => - sampledDecodedOpcode<=Decoded_Add; - when OpCode_Or => - sampledDecodedOpcode<=Decoded_Or; - when OpCode_And => - sampledDecodedOpcode<=Decoded_And; - when OpCode_Load => - sampledDecodedOpcode<=Decoded_Load; - when OpCode_Not => - sampledDecodedOpcode<=Decoded_Not; - when OpCode_Flip => - sampledDecodedOpcode<=Decoded_Flip; - when OpCode_Store => - sampledDecodedOpcode<=Decoded_Store; - when OpCode_PopSP => - sampledDecodedOpcode<=Decoded_PopSP; - when others => - sampledDecodedOpcode<=Decoded_Nop; - end case; - end if; - end process; - - - opcodeControl: - process(clk, areset) - variable spOffset : unsigned(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - inInterrupt <= '0'; - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); --- out_mem_addr <= (others => DontCareValue); --- mem_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - begin_inst <= '0'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - - decodedOpcode <= sampledDecodedOpcode; - opcode <= sampledOpcode; - if interrupt='0' then - inInterrupt <= '0'; -- no longer in an interrupt - end if; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); - trace_opcode <= opcode; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(memARead); - trace_topOfStackB <= std_logic_vector(memBRead); - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); - - idim_flag <= '0'; - case decodedOpcode is - when Decoded_Interrupt => - sp <= sp - 1; - memAAddr <= sp - 1; - memAWriteEnable <= '1'; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBitIncIO downto 0) <= pc; - pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address - report "ZPU jumped to interrupt!" severity note; - when Decoded_Im => - idim_flag <= '1'; - memAWriteEnable <= '1'; - if (idim_flag='0') then - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - else - memAAddr <= sp; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - end if; - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(4 downto 0)); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (in_mem_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= unsigned(mem_read); - end if; - when State_WriteIO => - sp <= sp + 1; - out_mem_writeEnable <= '1'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - if interrupt='1' and inInterrupt='0' and idim_flag='0' then - -- We got an interrupt, execute interrupt instead of next instruction - decodedOpcode <= Decoded_Interrupt; - end if; - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu4/src/zpupkg.vhd b/zpu/hdl/zpu4/src/zpupkg.vhd deleted file mode 100644 index f3800b0..0000000 --- a/zpu/hdl/zpu4/src/zpupkg.vhd +++ /dev/null @@ -1,170 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; - -package zpupkg is - - -- This bit is set for read/writes to IO - -- FIX!!! eventually this should be set to wordSize-1 so as to - -- to make the address of IO independent of amount of memory - -- reserved for CPU. Requires trivial tweaks in toolchain/runtime - -- libraries. - - constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes - constant maxAddrBit : integer := maxAddrBitIncIO-1; - constant ioBit : integer := maxAddrBit+1; - constant wordSize : integer := 2**wordPower; - constant wordBytes : integer := wordSize/8; - constant minAddrBit : integer := byteBits; - -- configurable internal stack size. Probably going to be 16 after toolchain is done - constant stack_bits : integer := 5; - constant stack_size : integer := 2**stack_bits; - - - component dualport_ram is - port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); - end component; - - - component dram is - port (clk : in std_logic; - areset : in std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); - end component; - - - component trace is - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBitIncIO downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); - memA : in std_logic_vector(wordSize-1 downto 0); - memB : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic; - intSp : in std_logic_vector(stack_bits-1 downto 0) - ); - end component; - - component zpu_core is - port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); - end component; - - - - component timer is - port( - clk : in std_logic; - areset : in std_logic; - we : in std_logic; - din : in std_logic_vector(7 downto 0); - adr : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(7 downto 0)); - end component; - - component zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); - end component; - - - - - -- opcode decode constants - constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; - constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; - constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; - constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; - constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; - constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; - - constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; - constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; - constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; - constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; - - constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; - constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; - constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; - constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; - - constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; - constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; - constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; - constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; - - constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; - constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; - constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; - constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; - - constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); - constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); - constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); - constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); - - constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); - constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); - - constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); - constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); - constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); - constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); - - constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); - constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); - - constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); - constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); - constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); - - constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); - constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); - constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); - - constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); - constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); - constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); - - - - constant OpCode_Size : integer := 8; - - - -end zpupkg; -- cgit v1.1 From ef1ebefa6075994c4f0a76035b585def8c5c1d3a Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 5 May 2008 11:40:45 +0000 Subject: wip --- zpu/hdl/zpu4/core/zpu_core_small_wip.vhd | 1 + 1 file changed, 1 insertion(+) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd index 8d87804..a169103 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd @@ -453,6 +453,7 @@ begin when State_Decode => if interrupt='1' and inInterrupt='0' and idim_flag='0' then -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; decodedOpcode <= Decoded_Interrupt; end if; -- during the State_Execute cycle we'll be fetching SP+1 -- cgit v1.1 From 68e306c13274f504281a94a52b5fb2f8ed4d9a75 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 5 May 2008 11:56:28 +0000 Subject: wip --- zpu/hdl/zpu4/test/interrupt/int.bin | Bin 0 -> 12232 bytes zpu/hdl/zpu4/test/interrupt/int.elf | Bin 0 -> 150454 bytes zpu/hdl/zpu4/test/interrupt/int.ram | 3057 +++++++++++++++++++++++++++++++++++ 3 files changed, 3057 insertions(+) create mode 100644 zpu/hdl/zpu4/test/interrupt/int.bin create mode 100644 zpu/hdl/zpu4/test/interrupt/int.elf create mode 100644 zpu/hdl/zpu4/test/interrupt/int.ram (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/test/interrupt/int.bin b/zpu/hdl/zpu4/test/interrupt/int.bin new file mode 100644 index 0000000..94cbe31 Binary files /dev/null and b/zpu/hdl/zpu4/test/interrupt/int.bin differ diff --git a/zpu/hdl/zpu4/test/interrupt/int.elf b/zpu/hdl/zpu4/test/interrupt/int.elf new file mode 100644 index 0000000..a550987 Binary files /dev/null and b/zpu/hdl/zpu4/test/interrupt/int.elf differ diff --git a/zpu/hdl/zpu4/test/interrupt/int.ram b/zpu/hdl/zpu4/test/interrupt/int.ram new file mode 100644 index 0000000..bcb424a --- /dev/null +++ b/zpu/hdl/zpu4/test/interrupt/int.ram @@ -0,0 +1,3057 @@ +0 => x"0b0b0b0b", +1 => x"82700b0b", +2 => x"80cfe00c", +3 => x"3a0b0b80", +4 => x"c6e10400", +5 => x"00000000", +6 => x"00000000", +7 => x"00000000", +8 => x"80088408", +9 => x"88080b0b", +10 => x"0b8af02d", +11 => x"880c840c", +12 => x"800c0400", +13 => x"00000000", +14 => x"00000000", +15 => x"00000000", +16 => x"71fd0608", +17 => x"72830609", +18 => x"81058205", +19 => x"832b2a83", +20 => x"ffff0652", +21 => x"04000000", +22 => x"00000000", +23 => x"00000000", +24 => x"71fd0608", +25 => x"83ffff73", +26 => x"83060981", +27 => x"05820583", +28 => x"2b2b0906", +29 => x"7383ffff", +30 => x"0b0b0b0b", +31 => x"83a70400", +32 => x"72098105", +33 => x"72057373", +34 => x"09060906", +35 => x"73097306", +36 => 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x"7251bc13", +2521 => x"0854732d", +2522 => x"7951f8b9", +2523 => x"3f707080", +2524 => x"dfb80bfc", +2525 => x"05700852", +2526 => x"5270ff2e", +2527 => x"9138702d", +2528 => x"fc127008", +2529 => x"525270ff", +2530 => x"2e098106", +2531 => x"f1385050", +2532 => x"0404ffba", +2533 => x"fe3f0400", +2534 => x"00000040", +2535 => x"476f7420", +2536 => x"696e7465", +2537 => x"72727570", +2538 => x"740a0000", +2539 => x"4e6f2069", +2540 => x"6e746572", +2541 => x"72757074", +2542 => x"0a000000", +2543 => x"43000000", +2544 => x"64756d6d", +2545 => x"792e6578", +2546 => x"65000000", +2547 => x"00ffffff", +2548 => x"ff00ffff", +2549 => x"ffff00ff", +2550 => x"ffffff00", +2551 => x"00000000", +2552 => x"00000000", +2553 => x"00000000", +2554 => x"00002fc0", +2555 => x"000027f0", +2556 => x"00000000", +2557 => x"00002a58", +2558 => x"00002ab4", +2559 => x"00002b10", +2560 => x"00000000", +2561 => x"00000000", +2562 => x"00000000", +2563 => x"00000000", +2564 => x"00000000", +2565 => x"00000000", +2566 => x"00000000", +2567 => x"00000000", +2568 => x"00000000", +2569 => x"000027bc", +2570 => x"00000000", +2571 => x"00000000", +2572 => x"00000000", +2573 => x"00000000", +2574 => x"00000000", +2575 => x"00000000", +2576 => x"00000000", +2577 => x"00000000", +2578 => x"00000000", +2579 => x"00000000", +2580 => x"00000000", +2581 => x"00000000", +2582 => x"00000000", +2583 => x"00000000", +2584 => x"00000000", +2585 => x"00000000", +2586 => x"00000000", +2587 => x"00000000", +2588 => x"00000000", +2589 => x"00000000", +2590 => x"00000000", +2591 => x"00000000", +2592 => x"00000000", +2593 => x"00000000", +2594 => x"00000000", +2595 => x"00000000", +2596 => x"00000000", +2597 => x"00000000", +2598 => x"00000001", +2599 => x"330eabcd", +2600 => x"1234e66d", +2601 => x"deec0005", +2602 => x"000b0000", +2603 => x"00000000", +2604 => x"00000000", +2605 => x"00000000", +2606 => x"00000000", +2607 => x"00000000", +2608 => x"00000000", +2609 => x"00000000", +2610 => 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x"00000000", +2656 => x"00000000", +2657 => x"00000000", +2658 => x"00000000", +2659 => x"00000000", +2660 => x"00000000", +2661 => x"00000000", +2662 => x"00000000", +2663 => x"00000000", +2664 => x"00000000", +2665 => x"00000000", +2666 => x"00000000", +2667 => x"00000000", +2668 => x"00000000", +2669 => x"00000000", +2670 => x"00000000", +2671 => x"00000000", +2672 => x"00000000", +2673 => x"00000000", +2674 => x"00000000", +2675 => x"00000000", +2676 => x"00000000", +2677 => x"00000000", +2678 => x"00000000", +2679 => x"00000000", +2680 => x"00000000", +2681 => x"00000000", +2682 => x"00000000", +2683 => x"00000000", +2684 => x"00000000", +2685 => x"00000000", +2686 => x"00000000", +2687 => x"00000000", +2688 => x"00000000", +2689 => x"00000000", +2690 => x"00000000", +2691 => x"00000000", +2692 => x"00000000", +2693 => x"00000000", +2694 => x"00000000", +2695 => x"00000000", +2696 => x"00000000", +2697 => x"00000000", +2698 => x"00000000", +2699 => x"00000000", +2700 => x"00000000", +2701 => x"00000000", +2702 => x"00000000", +2703 => x"00000000", +2704 => x"00000000", +2705 => x"00000000", +2706 => x"00000000", +2707 => x"00000000", +2708 => x"00000000", +2709 => x"00000000", +2710 => x"00000000", +2711 => x"00000000", +2712 => x"00000000", +2713 => x"00000000", +2714 => x"00000000", +2715 => x"00000000", +2716 => x"00000000", +2717 => x"00000000", +2718 => x"00000000", +2719 => x"00000000", +2720 => x"00000000", +2721 => x"00000000", +2722 => x"00000000", +2723 => x"00000000", +2724 => x"00000000", +2725 => x"00000000", +2726 => x"00000000", +2727 => x"00000000", +2728 => x"00000000", +2729 => x"00000000", +2730 => x"00000000", +2731 => x"00000000", +2732 => x"00000000", +2733 => x"00000000", +2734 => x"00000000", +2735 => x"00000000", +2736 => x"00000000", +2737 => x"00000000", +2738 => x"00000000", +2739 => x"00000000", +2740 => x"00000000", +2741 => x"00000000", +2742 => x"00000000", +2743 => x"00000000", +2744 => x"00000000", +2745 => x"00000000", +2746 => x"00000000", +2747 => x"00000000", +2748 => x"00000000", +2749 => x"00000000", +2750 => x"00000000", +2751 => x"00000000", +2752 => x"00000000", +2753 => x"00000000", +2754 => x"00000000", +2755 => x"00000000", +2756 => x"00000000", +2757 => x"00000000", +2758 => x"00000000", +2759 => x"00000000", +2760 => x"00000000", +2761 => x"00000000", +2762 => x"00000000", +2763 => x"00000000", +2764 => x"00000000", +2765 => x"00000000", +2766 => x"00000000", +2767 => x"00000000", +2768 => x"00000000", +2769 => x"00000000", +2770 => x"00000000", +2771 => x"00000000", +2772 => x"00000000", +2773 => x"00000000", +2774 => x"00000000", +2775 => x"00000000", +2776 => x"00000000", +2777 => x"00000000", +2778 => x"00000000", +2779 => x"00000000", +2780 => x"00000000", +2781 => x"00000000", +2782 => x"00000000", +2783 => x"00000000", +2784 => x"00000000", +2785 => x"00000000", +2786 => x"00000000", +2787 => x"00000000", +2788 => x"00000000", +2789 => x"00000000", +2790 => x"00000000", +2791 => x"ffffffff", +2792 => x"00000000", +2793 => x"00020000", +2794 => x"00000000", +2795 => x"00000000", +2796 => x"00002ba8", +2797 => x"00002ba8", +2798 => x"00002bb0", +2799 => x"00002bb0", +2800 => x"00002bb8", +2801 => x"00002bb8", +2802 => x"00002bc0", +2803 => x"00002bc0", +2804 => x"00002bc8", +2805 => x"00002bc8", +2806 => x"00002bd0", +2807 => x"00002bd0", +2808 => x"00002bd8", +2809 => x"00002bd8", +2810 => x"00002be0", +2811 => x"00002be0", +2812 => x"00002be8", +2813 => x"00002be8", +2814 => x"00002bf0", +2815 => x"00002bf0", +2816 => x"00002bf8", +2817 => x"00002bf8", +2818 => x"00002c00", +2819 => x"00002c00", +2820 => x"00002c08", +2821 => x"00002c08", +2822 => x"00002c10", +2823 => x"00002c10", +2824 => x"00002c18", +2825 => x"00002c18", +2826 => x"00002c20", +2827 => x"00002c20", +2828 => x"00002c28", +2829 => x"00002c28", +2830 => x"00002c30", +2831 => x"00002c30", +2832 => x"00002c38", +2833 => x"00002c38", +2834 => x"00002c40", +2835 => x"00002c40", +2836 => x"00002c48", +2837 => x"00002c48", +2838 => x"00002c50", +2839 => x"00002c50", +2840 => x"00002c58", +2841 => x"00002c58", +2842 => x"00002c60", +2843 => x"00002c60", +2844 => x"00002c68", +2845 => x"00002c68", +2846 => x"00002c70", +2847 => x"00002c70", +2848 => x"00002c78", +2849 => x"00002c78", +2850 => x"00002c80", +2851 => x"00002c80", +2852 => x"00002c88", +2853 => x"00002c88", +2854 => x"00002c90", +2855 => x"00002c90", +2856 => x"00002c98", +2857 => x"00002c98", +2858 => x"00002ca0", +2859 => x"00002ca0", +2860 => x"00002ca8", +2861 => x"00002ca8", +2862 => x"00002cb0", +2863 => x"00002cb0", +2864 => x"00002cb8", +2865 => x"00002cb8", +2866 => x"00002cc0", +2867 => x"00002cc0", +2868 => x"00002cc8", +2869 => x"00002cc8", +2870 => x"00002cd0", +2871 => x"00002cd0", +2872 => x"00002cd8", +2873 => x"00002cd8", +2874 => x"00002ce0", +2875 => x"00002ce0", +2876 => x"00002ce8", +2877 => x"00002ce8", +2878 => x"00002cf0", +2879 => x"00002cf0", +2880 => x"00002cf8", +2881 => x"00002cf8", +2882 => x"00002d00", +2883 => x"00002d00", +2884 => x"00002d08", +2885 => x"00002d08", +2886 => x"00002d10", +2887 => x"00002d10", +2888 => x"00002d18", +2889 => x"00002d18", +2890 => x"00002d20", +2891 => x"00002d20", +2892 => x"00002d28", +2893 => x"00002d28", +2894 => x"00002d30", +2895 => x"00002d30", +2896 => x"00002d38", +2897 => x"00002d38", +2898 => x"00002d40", +2899 => x"00002d40", +2900 => x"00002d48", +2901 => x"00002d48", +2902 => x"00002d50", +2903 => x"00002d50", +2904 => x"00002d58", +2905 => x"00002d58", +2906 => x"00002d60", +2907 => x"00002d60", +2908 => x"00002d68", +2909 => x"00002d68", +2910 => x"00002d70", +2911 => x"00002d70", +2912 => x"00002d78", +2913 => x"00002d78", +2914 => x"00002d80", +2915 => x"00002d80", +2916 => x"00002d88", +2917 => x"00002d88", +2918 => x"00002d90", +2919 => x"00002d90", +2920 => x"00002d98", +2921 => x"00002d98", +2922 => x"00002da0", +2923 => x"00002da0", +2924 => x"00002da8", +2925 => x"00002da8", +2926 => x"00002db0", +2927 => x"00002db0", +2928 => x"00002db8", +2929 => x"00002db8", +2930 => x"00002dc0", +2931 => x"00002dc0", +2932 => x"00002dc8", +2933 => x"00002dc8", +2934 => x"00002dd0", +2935 => x"00002dd0", +2936 => x"00002dd8", +2937 => x"00002dd8", +2938 => x"00002de0", +2939 => x"00002de0", +2940 => x"00002de8", +2941 => x"00002de8", +2942 => x"00002df0", +2943 => x"00002df0", +2944 => x"00002df8", +2945 => x"00002df8", +2946 => x"00002e00", +2947 => x"00002e00", +2948 => x"00002e08", +2949 => x"00002e08", +2950 => x"00002e10", +2951 => x"00002e10", +2952 => x"00002e18", +2953 => x"00002e18", +2954 => x"00002e20", +2955 => x"00002e20", +2956 => x"00002e28", +2957 => x"00002e28", +2958 => x"00002e30", +2959 => x"00002e30", +2960 => x"00002e38", +2961 => x"00002e38", +2962 => x"00002e40", +2963 => x"00002e40", +2964 => x"00002e48", +2965 => x"00002e48", +2966 => x"00002e50", +2967 => x"00002e50", +2968 => x"00002e58", +2969 => x"00002e58", +2970 => x"00002e60", +2971 => x"00002e60", +2972 => x"00002e68", +2973 => x"00002e68", +2974 => x"00002e70", +2975 => x"00002e70", +2976 => x"00002e78", +2977 => x"00002e78", +2978 => x"00002e80", +2979 => x"00002e80", +2980 => x"00002e88", +2981 => x"00002e88", +2982 => x"00002e90", +2983 => x"00002e90", +2984 => x"00002e98", +2985 => x"00002e98", +2986 => x"00002ea0", +2987 => x"00002ea0", +2988 => x"00002ea8", +2989 => x"00002ea8", +2990 => x"00002eb0", +2991 => x"00002eb0", +2992 => x"00002eb8", +2993 => x"00002eb8", +2994 => x"00002ec0", +2995 => x"00002ec0", +2996 => x"00002ec8", +2997 => x"00002ec8", +2998 => x"00002ed0", +2999 => x"00002ed0", +3000 => x"00002ed8", +3001 => x"00002ed8", +3002 => x"00002ee0", +3003 => x"00002ee0", +3004 => x"00002ee8", +3005 => x"00002ee8", +3006 => x"00002ef0", +3007 => x"00002ef0", +3008 => x"00002ef8", +3009 => x"00002ef8", +3010 => x"00002f00", +3011 => x"00002f00", +3012 => x"00002f08", +3013 => x"00002f08", +3014 => x"00002f10", +3015 => x"00002f10", +3016 => x"00002f18", +3017 => x"00002f18", +3018 => x"00002f20", +3019 => x"00002f20", +3020 => x"00002f28", +3021 => x"00002f28", +3022 => x"00002f30", +3023 => x"00002f30", +3024 => x"00002f38", +3025 => x"00002f38", +3026 => x"00002f40", +3027 => x"00002f40", +3028 => x"00002f48", +3029 => x"00002f48", +3030 => x"00002f50", +3031 => x"00002f50", +3032 => x"00002f58", +3033 => x"00002f58", +3034 => x"00002f60", +3035 => x"00002f60", +3036 => x"00002f68", +3037 => x"00002f68", +3038 => x"00002f70", +3039 => x"00002f70", +3040 => x"00002f78", +3041 => x"00002f78", +3042 => x"00002f80", +3043 => x"00002f80", +3044 => x"00002f88", +3045 => x"00002f88", +3046 => x"00002f90", +3047 => x"00002f90", +3048 => x"00002f98", +3049 => x"00002f98", +3050 => x"00002fa0", +3051 => x"00002fa0", +3052 => x"000027c0", +3053 => x"ffffffff", +3054 => x"00000000", +3055 => x"ffffffff", +3056 => x"00000000", -- cgit v1.1 From 6c7ee841131808466eb0c93e5c8f112771004fbf Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 6 May 2008 06:39:21 +0000 Subject: * Small ZPU now supports interrupts * added simulation example demonstrating interrupts --- zpu/hdl/zpu4/core/zpu_core_small.vhd | 83 +- zpu/hdl/zpu4/core/zpu_core_small_wip.vhd | 498 ---- zpu/hdl/zpu4/src/bram.vhd | 3807 -------------------------- zpu/hdl/zpu4/src/bram_dmips.vhd | 3717 ------------------------- zpu/hdl/zpu4/src/dram_dmips.vhd | 3308 ---------------------- zpu/hdl/zpu4/src/dram_hello.vhd | 3107 --------------------- zpu/hdl/zpu4/src/zpu_config_trace.vhd | 17 - zpu/hdl/zpu4/test/interrupt/int.bin | Bin 12232 -> 12232 bytes zpu/hdl/zpu4/test/interrupt/int.c | 7 +- zpu/hdl/zpu4/test/interrupt/int.elf | Bin 150454 -> 150458 bytes zpu/hdl/zpu4/test/interrupt/int.ram | 4380 +++++++++++++++--------------- 11 files changed, 2255 insertions(+), 16669 deletions(-) delete mode 100644 zpu/hdl/zpu4/core/zpu_core_small_wip.vhd delete mode 100644 zpu/hdl/zpu4/src/bram.vhd delete mode 100644 zpu/hdl/zpu4/src/bram_dmips.vhd delete mode 100644 zpu/hdl/zpu4/src/dram_dmips.vhd delete mode 100644 zpu/hdl/zpu4/src/dram_hello.vhd delete mode 100644 zpu/hdl/zpu4/src/zpu_config_trace.vhd (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 9cda01c..03526bd 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -81,7 +81,9 @@ State_FetchNext, State_AddSP, State_ReadIODone, State_Decode, -State_Resync +State_Resync, +State_Interrupt + ); type DecodedOpcodeType is @@ -103,7 +105,8 @@ Decoded_Load, Decoded_Not, Decoded_Flip, Decoded_Store, -Decoded_PopSP +Decoded_PopSP, +Decoded_Interrupt ); @@ -125,11 +128,15 @@ signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); signal memBRead_stdlogic : std_logic_vector(memBRead'range); --- debug -subtype index is integer range 0 to 3; -signal tOpcode_sel : index; - - +subtype index is integer range 0 to 3; + +signal tOpcode_sel : index; + + +signal inInterrupt : std_logic; + + + begin traceFileGenerate: if Generate_Trace generate @@ -146,8 +153,13 @@ begin ); end generate; - -- not used in this design - mem_writeMask <= (others => '1'); + + + -- not used in this design + + mem_writeMask <= (others => '1'); + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); memAWrite_stdlogic <= std_logic_vector(memAWrite); @@ -167,23 +179,31 @@ begin memARead <= unsigned(memARead_stdlogic); memBRead <= unsigned(memBRead_stdlogic); -tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + decodeControl: - process(memBRead, pc,tOpcode_sel) + process(memBRead, pc,tOpcode_sel) variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); begin - -- not worked with synopsys - -- tOpcode := std_logic_vector(memBRead((wordBytes-1-to_integer(pc(minAddrBit-1 downto 0))+1)*8-1 downto (wordBytes-1-to_integer(pc(minAddrBit-1 downto 0)))*8)); - -- use full case - case (tOpcode_sel) is - when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); - when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); - when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); - when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); - end case; + + -- simplify opcode selection a bit so it passes more synthesizers + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + sampledOpcode <= tOpcode; if (tOpcode(7 downto 7)=OpCode_Im) then @@ -246,13 +266,12 @@ tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); out_mem_readEnable <= '0'; memAWrite <= (others => '0'); memBWrite <= (others => '0'); - -- avoid Latch in synopsys - -- mem_writeMask <= (others => '1'); + inInterrupt <= '0'; elsif (clk'event and clk = '1') then memAWriteEnable <= '0'; memBWriteEnable <= '0'; -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is + -- memAWrite can be left at whatever value if memAWriteEnable is -- not set. memAWrite <= (others => DontCareValue); memBWrite <= (others => DontCareValue); @@ -270,6 +289,9 @@ tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); decodedOpcode <= sampledDecodedOpcode; opcode <= sampledOpcode; + if interrupt='0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; case state is when State_Execute => @@ -295,6 +317,14 @@ tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); idim_flag <= '0'; case decodedOpcode is + when Decoded_Interrupt => + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc; + pc <= to_unsigned(32, maxAddrBit+1); -- interrupt address + report "ZPU jumped to interrupt!" severity note; when Decoded_Im => idim_flag <= '1'; memAWriteEnable <= '1'; @@ -422,6 +452,11 @@ tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); memBAddr <= sp + 1; state <= State_Decode; when State_Decode => + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + decodedOpcode <= Decoded_Interrupt; + end if; -- during the State_Execute cycle we'll be fetching SP+1 memAAddr <= sp; memBAddr <= sp + 1; diff --git a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd b/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd deleted file mode 100644 index a169103..0000000 --- a/zpu/hdl/zpu4/core/zpu_core_small_wip.vhd +++ /dev/null @@ -1,498 +0,0 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - -entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); -end zpu_core; - -architecture behave of zpu_core is - -signal readIO : std_logic; - - - -signal memAWriteEnable : std_logic; -signal memAAddr : unsigned(maxAddrBit downto minAddrBit); -signal memAWrite : unsigned(wordSize-1 downto 0); -signal memARead : unsigned(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : unsigned(maxAddrBit downto minAddrBit); -signal memBWrite : unsigned(wordSize-1 downto 0); -signal memBRead : unsigned(wordSize-1 downto 0); - - - -signal pc : unsigned(maxAddrBit downto 0); -signal sp : unsigned(maxAddrBit downto minAddrBit); - -signal idim_flag : std_logic; - ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; -signal busy : std_logic; ---signal fetching : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. -type State_Type is -( -State_Fetch, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_FetchNext, -State_AddSP, -State_ReadIODone, -State_Decode, -State_Resync, -State_Interrupt - -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP , -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP -); - - - -signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; -signal sampledDecodedOpcode : DecodedOpcodeType; - - -signal state : State_Type; - -subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; -signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); -signal memARead_stdlogic : std_logic_vector(memARead'range); -signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); -signal memBRead_stdlogic : std_logic_vector(memBRead'range); - -subtype index is integer range 0 to 3; - -signal tOpcode_sel : index; - - -signal inInterrupt : std_logic; - - - -begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - - -- not used in this design - - mem_writeMask <= (others => '1'); - - - - memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); - memAWrite_stdlogic <= std_logic_vector(memAWrite); - memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); - memBWrite_stdlogic <= std_logic_vector(memBWrite); - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr_stdlogic, - memAWrite => memAWrite_stdlogic, - memARead => memARead_stdlogic, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr_stdlogic, - memBWrite => memBWrite_stdlogic, - memBRead => memBRead_stdlogic - ); - memARead <= unsigned(memARead_stdlogic); - memBRead <= unsigned(memBRead_stdlogic); - - - - tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - - - - decodeControl: - process(memBRead, pc,tOpcode_sel) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - - -- simplify opcode selection a bit so it passes more synthesizers - case (tOpcode_sel) is - - when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); - - when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); - - when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); - - when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - - when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); - end case; - - sampledOpcode <= tOpcode; - - if (tOpcode(7 downto 7)=OpCode_Im) then - sampledDecodedOpcode<=Decoded_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - sampledDecodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - sampledDecodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - sampledDecodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - sampledDecodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - sampledDecodedOpcode<=Decoded_Break; - when OpCode_PushSP => - sampledDecodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - sampledDecodedOpcode<=Decoded_PopPC; - when OpCode_Add => - sampledDecodedOpcode<=Decoded_Add; - when OpCode_Or => - sampledDecodedOpcode<=Decoded_Or; - when OpCode_And => - sampledDecodedOpcode<=Decoded_And; - when OpCode_Load => - sampledDecodedOpcode<=Decoded_Load; - when OpCode_Not => - sampledDecodedOpcode<=Decoded_Not; - when OpCode_Flip => - sampledDecodedOpcode<=Decoded_Flip; - when OpCode_Store => - sampledDecodedOpcode<=Decoded_Store; - when OpCode_PopSP => - sampledDecodedOpcode<=Decoded_PopSP; - when others => - sampledDecodedOpcode<=Decoded_Nop; - end case; - end if; - end process; - - - opcodeControl: - process(clk, areset) - variable spOffset : unsigned(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - inInterrupt <= '0'; - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); --- out_mem_addr <= (others => DontCareValue); --- mem_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - begin_inst <= '0'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - - decodedOpcode <= sampledDecodedOpcode; - opcode <= sampledOpcode; - if interrupt='0' then - inInterrupt <= '0'; -- no longer in an interrupt - end if; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); - trace_opcode <= opcode; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(memARead); - trace_topOfStackB <= std_logic_vector(memBRead); - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); - - idim_flag <= '0'; - case decodedOpcode is - when Decoded_Interrupt => - sp <= sp - 1; - memAAddr <= sp - 1; - memAWriteEnable <= '1'; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBitIncIO downto 0) <= pc; - pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address - report "ZPU jumped to interrupt!" severity note; - when Decoded_Im => - idim_flag <= '1'; - memAWriteEnable <= '1'; - if (idim_flag='0') then - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - else - memAAddr <= sp; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - end if; - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(4 downto 0)); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - if (in_mem_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= unsigned(mem_read); - end if; - when State_WriteIO => - sp <= sp + 1; - out_mem_writeEnable <= '1'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - if interrupt='1' and inInterrupt='0' and idim_flag='0' then - -- We got an interrupt, execute interrupt instead of next instruction - inInterrupt <= '1'; - decodedOpcode <= Decoded_Interrupt; - end if; - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - - end if; - end process; - - - -end behave; diff --git a/zpu/hdl/zpu4/src/bram.vhd b/zpu/hdl/zpu4/src/bram.vhd deleted file mode 100644 index 435f3f4..0000000 --- a/zpu/hdl/zpu4/src/bram.vhd +++ /dev/null @@ -1,3807 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - -library zylin; -use zylin.zpu_config.all; -use zylin.zpupkg.all; - -entity dram is -port (clk : in std_logic; - areset : in std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); -end dram; - -architecture dram_arch of dram is - -type ram_type is array(0 to ((2**(maxAddrBit+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"800b0b0b", -1 => x"0b0b8070", -2 => x"0b0b80e5", -3 => x"d00c3a0b", -4 => x"0b0bbed7", -5 => x"04000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"0bbfa72d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"0b0b0400", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"530b0b51", -38 => x"04000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"0b0b5104", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"530b0b51", -55 => x"04000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"0b0b5104", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c6040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a530b0b", -82 => x"51040000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"0607530b", -101 => x"0b510400", -102 => x"00000000", -103 => x"00000000", -104 => x"7171530b", -105 => x"0b510406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"0b0b5104", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"530b0b51", -125 => x"04000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"520b0b04", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"0505530b", -138 => x"0b510400", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07530b0b", -147 => x"51040000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"0b0b0400", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80e5", -162 => x"bc738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88ac0400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0ba3", -171 => x"fa2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0ba4", -179 => x"ca2d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70540b0b", -188 => x"71067309", -189 => x"727405ff", -190 => x"05060751", -191 => x"51510400", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"0570540b", -196 => x"0b710673", -197 => x"09727405", -198 => x"ff050607", -199 => x"51515104", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"80e5cc0c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"0b0b0400", -218 => x"00000000", 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x"04040404", -3186 => x"04040404", -3187 => x"05050505", -3188 => x"05050505", -3189 => x"05050505", -3190 => x"05050505", -3191 => x"06060606", -3192 => x"06060606", -3193 => x"06060606", -3194 => x"06060606", -3195 => x"06060606", -3196 => x"06060606", -3197 => x"06060606", -3198 => x"06060606", -3199 => x"07070707", -3200 => x"07070707", -3201 => x"07070707", -3202 => x"07070707", -3203 => x"07070707", -3204 => x"07070707", -3205 => x"07070707", -3206 => x"07070707", -3207 => x"07070707", -3208 => x"07070707", -3209 => x"07070707", -3210 => x"07070707", -3211 => x"07070707", -3212 => x"07070707", -3213 => x"07070707", -3214 => x"07070707", -3215 => x"08080808", -3216 => x"08080808", -3217 => x"08080808", -3218 => x"08080808", -3219 => x"08080808", -3220 => x"08080808", -3221 => x"08080808", -3222 => x"08080808", -3223 => x"08080808", -3224 => x"08080808", -3225 => x"08080808", -3226 => x"08080808", -3227 => x"08080808", -3228 => x"08080808", -3229 => x"08080808", -3230 => x"08080808", -3231 => x"08080808", -3232 => x"08080808", -3233 => x"08080808", -3234 => x"08080808", -3235 => x"08080808", -3236 => x"08080808", -3237 => x"08080808", -3238 => x"08080808", -3239 => x"08080808", -3240 => x"08080808", -3241 => x"08080808", -3242 => x"08080808", -3243 => x"08080808", -3244 => x"08080808", -3245 => x"08080808", -3246 => x"08080808", -3247 => x"00ffffff", -3248 => x"ff00ffff", -3249 => x"ffff00ff", -3250 => x"ffffff00", -3251 => x"00000000", -3252 => x"00000000", -3253 => x"00000000", -3254 => x"00003ab8", -3255 => x"000186a0", -- iterations -3256 => x"00000000", -3257 => x"00000000", -3258 => x"00000000", -3259 => x"00000000", -3260 => x"00000000", -3261 => x"00000000", -3262 => x"00000000", -3263 => x"00000000", -3264 => x"00000000", -3265 => x"00000000", -3266 => x"00000000", -3267 => x"00000000", -3268 => x"00000000", -3269 => x"ffffffff", -3270 => x"00000000", -3271 => x"00020000", -3272 => x"00000000", -3273 => x"00000000", -3274 => x"00003320", -3275 => x"00003320", -3276 => x"00003328", -3277 => x"00003328", -3278 => x"00003330", -3279 => x"00003330", -3280 => x"00003338", -3281 => x"00003338", -3282 => x"00003340", -3283 => x"00003340", -3284 => x"00003348", -3285 => x"00003348", -3286 => x"00003350", -3287 => x"00003350", -3288 => x"00003358", -3289 => x"00003358", -3290 => x"00003360", -3291 => x"00003360", -3292 => x"00003368", -3293 => x"00003368", -3294 => x"00003370", -3295 => x"00003370", -3296 => x"00003378", -3297 => x"00003378", -3298 => x"00003380", -3299 => x"00003380", -3300 => x"00003388", -3301 => x"00003388", -3302 => x"00003390", -3303 => x"00003390", -3304 => x"00003398", -3305 => x"00003398", -3306 => x"000033a0", -3307 => x"000033a0", -3308 => x"000033a8", -3309 => x"000033a8", -3310 => x"000033b0", -3311 => x"000033b0", -3312 => x"000033b8", -3313 => x"000033b8", -3314 => x"000033c0", -3315 => x"000033c0", -3316 => x"000033c8", -3317 => x"000033c8", -3318 => x"000033d0", -3319 => x"000033d0", -3320 => x"000033d8", -3321 => x"000033d8", -3322 => x"000033e0", -3323 => x"000033e0", -3324 => x"000033e8", -3325 => x"000033e8", -3326 => x"000033f0", -3327 => x"000033f0", -3328 => x"000033f8", -3329 => x"000033f8", -3330 => x"00003400", -3331 => x"00003400", -3332 => x"00003408", -3333 => x"00003408", -3334 => x"00003410", -3335 => x"00003410", -3336 => x"00003418", -3337 => x"00003418", -3338 => x"00003420", -3339 => x"00003420", -3340 => x"00003428", -3341 => x"00003428", -3342 => x"00003430", -3343 => x"00003430", -3344 => x"00003438", -3345 => x"00003438", -3346 => x"00003440", -3347 => x"00003440", -3348 => x"00003448", -3349 => x"00003448", -3350 => x"00003450", -3351 => x"00003450", -3352 => x"00003458", -3353 => x"00003458", -3354 => x"00003460", -3355 => x"00003460", -3356 => x"00003468", -3357 => x"00003468", -3358 => x"00003470", -3359 => x"00003470", -3360 => x"00003478", -3361 => x"00003478", -3362 => x"00003480", -3363 => x"00003480", -3364 => x"00003488", -3365 => x"00003488", -3366 => x"00003490", -3367 => x"00003490", -3368 => x"00003498", -3369 => x"00003498", -3370 => x"000034a0", -3371 => x"000034a0", -3372 => x"000034a8", -3373 => x"000034a8", -3374 => x"000034b0", -3375 => x"000034b0", -3376 => x"000034b8", -3377 => x"000034b8", -3378 => x"000034c0", -3379 => x"000034c0", -3380 => x"000034c8", -3381 => x"000034c8", -3382 => x"000034d0", -3383 => x"000034d0", -3384 => x"000034d8", -3385 => x"000034d8", -3386 => x"000034e0", -3387 => x"000034e0", -3388 => x"000034e8", -3389 => x"000034e8", -3390 => x"000034f0", -3391 => x"000034f0", -3392 => x"000034f8", -3393 => x"000034f8", -3394 => x"00003500", -3395 => x"00003500", -3396 => x"00003508", -3397 => x"00003508", -3398 => x"00003510", -3399 => x"00003510", -3400 => x"00003518", -3401 => x"00003518", -3402 => x"00003520", -3403 => x"00003520", -3404 => x"00003528", -3405 => x"00003528", -3406 => x"00003530", -3407 => x"00003530", -3408 => x"00003538", -3409 => x"00003538", -3410 => x"00003540", -3411 => x"00003540", -3412 => x"00003548", -3413 => x"00003548", -3414 => x"00003550", -3415 => x"00003550", -3416 => x"00003558", -3417 => x"00003558", -3418 => x"00003560", -3419 => x"00003560", -3420 => x"00003568", -3421 => x"00003568", -3422 => x"00003570", -3423 => x"00003570", -3424 => x"00003578", -3425 => x"00003578", -3426 => x"00003580", -3427 => x"00003580", -3428 => x"00003588", -3429 => x"00003588", -3430 => x"00003590", -3431 => x"00003590", -3432 => x"00003598", -3433 => x"00003598", -3434 => x"000035a0", -3435 => x"000035a0", -3436 => x"000035a8", -3437 => x"000035a8", -3438 => x"000035b0", -3439 => x"000035b0", -3440 => x"000035b8", -3441 => x"000035b8", -3442 => x"000035c0", -3443 => x"000035c0", -3444 => x"000035c8", -3445 => x"000035c8", -3446 => x"000035d0", -3447 => x"000035d0", -3448 => x"000035d8", -3449 => x"000035d8", -3450 => x"000035e0", -3451 => x"000035e0", -3452 => x"000035e8", -3453 => x"000035e8", -3454 => x"000035f0", -3455 => x"000035f0", -3456 => x"000035f8", -3457 => x"000035f8", -3458 => x"00003600", -3459 => x"00003600", -3460 => x"00003608", -3461 => x"00003608", -3462 => x"00003610", -3463 => x"00003610", -3464 => x"00003618", -3465 => x"00003618", -3466 => x"00003620", -3467 => x"00003620", -3468 => x"00003628", -3469 => x"00003628", -3470 => x"00003630", -3471 => x"00003630", -3472 => x"00003638", -3473 => x"00003638", -3474 => x"00003640", -3475 => x"00003640", -3476 => x"00003648", -3477 => x"00003648", -3478 => x"00003650", -3479 => x"00003650", -3480 => x"00003658", -3481 => x"00003658", -3482 => x"00003660", -3483 => x"00003660", -3484 => x"00003668", -3485 => x"00003668", -3486 => x"00003670", -3487 => x"00003670", -3488 => x"00003678", -3489 => x"00003678", -3490 => x"00003680", -3491 => x"00003680", -3492 => x"00003688", -3493 => x"00003688", -3494 => x"00003690", -3495 => x"00003690", -3496 => x"00003698", -3497 => x"00003698", -3498 => x"000036a0", -3499 => x"000036a0", -3500 => x"000036a8", -3501 => x"000036a8", -3502 => x"000036b0", -3503 => x"000036b0", -3504 => x"000036b8", -3505 => x"000036b8", -3506 => x"000036c0", -3507 => x"000036c0", -3508 => x"000036c8", -3509 => x"000036c8", -3510 => x"000036d0", -3511 => x"000036d0", -3512 => x"000036d8", -3513 => x"000036d8", -3514 => x"000036e0", -3515 => x"000036e0", -3516 => x"000036e8", -3517 => x"000036e8", -3518 => x"000036f0", -3519 => x"000036f0", -3520 => x"000036f8", -3521 => x"000036f8", -3522 => x"00003700", -3523 => x"00003700", -3524 => x"00003708", -3525 => x"00003708", -3526 => x"00003710", -3527 => x"00003710", -3528 => x"00003718", -3529 => x"00003718", -3530 => x"0000372c", -3531 => x"00000000", -3532 => x"00003994", -3533 => x"000039f0", -3534 => x"00003a4c", -3535 => x"00000000", -3536 => x"00000000", -3537 => x"00000000", -3538 => x"00000000", -3539 => x"00000000", -3540 => x"00000000", -3541 => x"00000000", -3542 => x"00000000", -3543 => x"00000000", -3544 => x"000031ac", -3545 => x"00000000", -3546 => x"00000000", -3547 => x"00000000", -3548 => x"00000000", -3549 => x"00000000", -3550 => x"00000000", -3551 => x"00000000", -3552 => x"00000000", -3553 => x"00000000", -3554 => x"00000000", -3555 => x"00000000", -3556 => x"00000000", -3557 => x"00000000", -3558 => x"00000000", -3559 => x"00000000", -3560 => x"00000000", -3561 => x"00000000", -3562 => x"00000000", -3563 => x"00000000", -3564 => x"00000000", -3565 => x"00000000", -3566 => x"00000000", -3567 => x"00000000", -3568 => x"00000000", -3569 => x"00000000", -3570 => x"00000000", -3571 => x"00000000", -3572 => x"00000000", -3573 => x"00000001", -3574 => x"330eabcd", -3575 => x"1234e66d", -3576 => x"deec0005", -3577 => x"000b0000", -3578 => x"00000000", -3579 => x"00000000", -3580 => x"00000000", -3581 => x"00000000", -3582 => x"00000000", -3583 => x"00000000", -3584 => x"00000000", -3585 => x"00000000", -3586 => x"00000000", -3587 => x"00000000", -3588 => x"00000000", -3589 => x"00000000", -3590 => x"00000000", -3591 => x"00000000", -3592 => x"00000000", -3593 => x"00000000", -3594 => x"00000000", -3595 => x"00000000", -3596 => x"00000000", -3597 => x"00000000", -3598 => x"00000000", -3599 => x"00000000", -3600 => x"00000000", -3601 => x"00000000", -3602 => x"00000000", -3603 => x"00000000", -3604 => x"00000000", -3605 => x"00000000", -3606 => x"00000000", -3607 => x"00000000", -3608 => x"00000000", -3609 => x"00000000", -3610 => x"00000000", -3611 => x"00000000", -3612 => x"00000000", -3613 => x"00000000", -3614 => x"00000000", -3615 => x"00000000", -3616 => x"00000000", -3617 => x"00000000", -3618 => x"00000000", -3619 => x"00000000", -3620 => x"00000000", -3621 => x"00000000", -3622 => x"00000000", -3623 => x"00000000", -3624 => x"00000000", -3625 => x"00000000", -3626 => x"00000000", -3627 => x"00000000", -3628 => x"00000000", -3629 => x"00000000", -3630 => x"00000000", -3631 => x"00000000", -3632 => x"00000000", -3633 => x"00000000", -3634 => x"00000000", -3635 => x"00000000", -3636 => x"00000000", -3637 => x"00000000", -3638 => x"00000000", -3639 => x"00000000", -3640 => x"00000000", -3641 => x"00000000", -3642 => x"00000000", -3643 => x"00000000", -3644 => x"00000000", -3645 => x"00000000", -3646 => x"00000000", -3647 => x"00000000", -3648 => x"00000000", -3649 => x"00000000", -3650 => x"00000000", -3651 => x"00000000", -3652 => x"00000000", -3653 => x"00000000", -3654 => x"00000000", -3655 => x"00000000", -3656 => x"00000000", -3657 => x"00000000", -3658 => x"00000000", -3659 => x"00000000", -3660 => x"00000000", -3661 => x"00000000", -3662 => x"00000000", -3663 => x"00000000", -3664 => x"00000000", -3665 => x"00000000", -3666 => x"00000000", -3667 => x"00000000", -3668 => x"00000000", -3669 => x"00000000", -3670 => x"00000000", -3671 => x"00000000", -3672 => x"00000000", -3673 => x"00000000", -3674 => x"00000000", -3675 => x"00000000", -3676 => x"00000000", -3677 => x"00000000", -3678 => x"00000000", -3679 => x"00000000", -3680 => x"00000000", -3681 => x"00000000", -3682 => x"00000000", -3683 => x"00000000", -3684 => x"00000000", -3685 => x"00000000", -3686 => x"00000000", -3687 => x"00000000", -3688 => x"00000000", -3689 => x"00000000", -3690 => x"00000000", -3691 => x"00000000", -3692 => x"00000000", -3693 => x"00000000", -3694 => x"00000000", -3695 => x"00000000", -3696 => x"00000000", -3697 => x"00000000", -3698 => x"00000000", -3699 => x"00000000", -3700 => x"00000000", -3701 => x"00000000", -3702 => x"00000000", -3703 => x"00000000", -3704 => x"00000000", -3705 => x"00000000", -3706 => x"00000000", -3707 => x"00000000", -3708 => x"00000000", -3709 => x"00000000", -3710 => x"00000000", -3711 => x"00000000", -3712 => x"00000000", -3713 => x"00000000", -3714 => x"00000000", -3715 => x"00000000", -3716 => x"00000000", -3717 => x"00000000", -3718 => x"00000000", -3719 => x"00000000", -3720 => x"00000000", -3721 => x"00000000", -3722 => x"00000000", -3723 => x"00000000", -3724 => x"00000000", -3725 => x"00000000", -3726 => x"00000000", -3727 => x"00000000", -3728 => x"00000000", -3729 => x"00000000", -3730 => x"00000000", -3731 => x"00000000", -3732 => x"00000000", -3733 => x"00000000", -3734 => x"00000000", -3735 => x"00000000", -3736 => x"00000000", -3737 => x"00000000", -3738 => x"00000000", -3739 => x"00000000", -3740 => x"00000000", -3741 => x"00000000", -3742 => x"00000000", -3743 => x"00000000", -3744 => x"00000000", -3745 => x"00000000", -3746 => x"00000000", -3747 => x"00000000", -3748 => x"00000000", -3749 => x"00000000", -3750 => x"00000000", -3751 => x"00000000", -3752 => x"00000000", -3753 => x"00000000", -3754 => x"000031b0", -3755 => x"ffffffff", -3756 => x"00000000", -3757 => x"ffffffff", -3758 => x"00000000", - others => x"00000000" -); - -begin - -mem_busy <= '0'; - -process (clk) -begin - if (clk'event and clk = '1') then - if (mem_writeEnable = '1') then - ram(conv_integer(mem_addr)) := mem_write; - end if; - mem_read <= ram(conv_integer(mem_addr)); - end if; -end process; - - - - -end dram_arch; diff --git a/zpu/hdl/zpu4/src/bram_dmips.vhd b/zpu/hdl/zpu4/src/bram_dmips.vhd deleted file mode 100644 index 1d62d21..0000000 --- a/zpu/hdl/zpu4/src/bram_dmips.vhd +++ /dev/null @@ -1,3717 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity dualport_ram is -port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); -end dualport_ram; - -architecture dualport_ram_arch of dualport_ram is - - -type ram_type is array(natural range 0 to ((2**(maxAddrBitBRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"0b0b0b0b", -1 => x"80700b0b", -2 => x"80e2a40c", -3 => x"3a0b0b80", -4 => x"c6fc0400", -5 => x"00000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80c7c32d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"04000000", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53510400", -38 => x"00000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51040000", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53510400", -55 => x"00000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51040000", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c4040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535104", -82 => x"00000000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"04000000", -102 => x"00000000", -103 => x"00000000", -104 => x"71715351", -105 => x"020d0406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51040000", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53510400", -125 => x"00000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52040000", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"04000000", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535104", -147 => x"00000000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"04000000", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80e2", -162 => x"90738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88aa0400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0baf", -171 => x"ac2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0baf", -179 => x"f02d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547106", -188 => x"73097274", -189 => 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x"4e470000", -2708 => x"44687279", -2709 => x"73746f6e", -2710 => x"65204265", -2711 => x"6e63686d", -2712 => x"61726b2c", -2713 => x"20566572", -2714 => x"73696f6e", -2715 => x"20322e31", -2716 => x"20284c61", -2717 => x"6e677561", -2718 => x"67653a20", -2719 => x"43290a00", -2720 => x"50726f67", -2721 => x"72616d20", -2722 => x"636f6d70", -2723 => x"696c6564", -2724 => x"20776974", -2725 => x"68202772", -2726 => x"65676973", -2727 => x"74657227", -2728 => x"20617474", -2729 => x"72696275", -2730 => x"74650a00", -2731 => x"45786563", -2732 => x"7574696f", -2733 => x"6e207374", -2734 => x"61727473", -2735 => x"2c202564", -2736 => x"2072756e", -2737 => x"73207468", -2738 => x"726f7567", -2739 => x"68204468", -2740 => x"72797374", -2741 => x"6f6e650a", -2742 => x"00000000", -2743 => x"44485259", -2744 => x"53544f4e", -2745 => x"45205052", -2746 => x"4f475241", -2747 => x"4d2c2032", -2748 => x"274e4420", -2749 => x"53545249", -2750 => x"4e470000", -2751 => x"45786563", -2752 => x"7574696f", -2753 => x"6e20656e", -2754 => x"64730a00", -2755 => x"46696e61", -2756 => x"6c207661", -2757 => x"6c756573", -2758 => x"206f6620", -2759 => x"74686520", -2760 => x"76617269", -2761 => x"61626c65", -2762 => x"73207573", -2763 => x"65642069", -2764 => x"6e207468", -2765 => x"65206265", -2766 => x"6e63686d", -2767 => x"61726b3a", -2768 => x"0a000000", -2769 => x"496e745f", -2770 => x"476c6f62", -2771 => x"3a202020", -2772 => x"20202020", -2773 => x"20202020", -2774 => x"2025640a", -2775 => x"00000000", -2776 => x"20202020", -2777 => x"20202020", -2778 => x"73686f75", -2779 => x"6c642062", -2780 => x"653a2020", -2781 => x"2025640a", -2782 => x"00000000", -2783 => x"426f6f6c", -2784 => x"5f476c6f", -2785 => x"623a2020", -2786 => x"20202020", -2787 => x"20202020", -2788 => x"2025640a", -2789 => x"00000000", -2790 => x"43685f31", -2791 => x"5f476c6f", -2792 => x"623a2020", -2793 => x"20202020", -2794 => x"20202020", -2795 => x"2025630a", -2796 => x"00000000", -2797 => x"20202020", -2798 => x"20202020", -2799 => x"73686f75", -2800 => x"6c642062", -2801 => x"653a2020", -2802 => x"2025630a", -2803 => x"00000000", -2804 => x"43685f32", -2805 => x"5f476c6f", -2806 => x"623a2020", -2807 => x"20202020", -2808 => x"20202020", -2809 => x"2025630a", -2810 => x"00000000", -2811 => x"4172725f", -2812 => x"315f476c", -2813 => x"6f625b38", -2814 => x"5d3a2020", -2815 => x"20202020", -2816 => x"2025640a", -2817 => x"00000000", -2818 => x"4172725f", -2819 => x"325f476c", -2820 => x"6f625b38", -2821 => x"5d5b375d", -2822 => x"3a202020", -2823 => x"2025640a", -2824 => x"00000000", -2825 => x"20202020", -2826 => x"20202020", -2827 => x"73686f75", -2828 => x"6c642062", -2829 => x"653a2020", -2830 => x"204e756d", -2831 => x"6265725f", -2832 => x"4f665f52", -2833 => x"756e7320", -2834 => x"2b203130", -2835 => x"0a000000", -2836 => x"5074725f", -2837 => x"476c6f62", -2838 => x"2d3e0a00", -2839 => x"20205074", -2840 => x"725f436f", -2841 => x"6d703a20", -2842 => x"20202020", -2843 => x"20202020", -2844 => x"2025640a", -2845 => x"00000000", -2846 => x"20202020", -2847 => x"20202020", -2848 => x"73686f75", -2849 => x"6c642062", -2850 => x"653a2020", -2851 => x"2028696d", -2852 => x"706c656d", -2853 => x"656e7461", -2854 => x"74696f6e", -2855 => x"2d646570", -2856 => x"656e6465", -2857 => x"6e74290a", -2858 => x"00000000", -2859 => x"20204469", -2860 => x"7363723a", -2861 => x"20202020", -2862 => x"20202020", -2863 => x"20202020", -2864 => x"2025640a", -2865 => x"00000000", -2866 => x"2020456e", -2867 => x"756d5f43", -2868 => x"6f6d703a", -2869 => x"20202020", -2870 => x"20202020", -2871 => x"2025640a", -2872 => x"00000000", -2873 => x"2020496e", -2874 => x"745f436f", -2875 => x"6d703a20", -2876 => x"20202020", -2877 => x"20202020", -2878 => x"2025640a", -2879 => x"00000000", -2880 => x"20205374", -2881 => x"725f436f", -2882 => x"6d703a20", -2883 => x"20202020", -2884 => x"20202020", -2885 => x"2025730a", -2886 => x"00000000", -2887 => x"20202020", -2888 => x"20202020", -2889 => x"73686f75", -2890 => x"6c642062", -2891 => x"653a2020", -2892 => x"20444852", -2893 => x"5953544f", -2894 => x"4e452050", -2895 => x"524f4752", -2896 => x"414d2c20", -2897 => x"534f4d45", -2898 => x"20535452", -2899 => x"494e470a", -2900 => x"00000000", -2901 => x"4e657874", -2902 => x"5f507472", -2903 => x"5f476c6f", -2904 => x"622d3e0a", -2905 => x"00000000", -2906 => x"20202020", -2907 => x"20202020", -2908 => x"73686f75", -2909 => x"6c642062", -2910 => x"653a2020", -2911 => x"2028696d", -2912 => x"706c656d", -2913 => x"656e7461", -2914 => x"74696f6e", -2915 => x"2d646570", -2916 => x"656e6465", -2917 => x"6e74292c", -2918 => x"2073616d", -2919 => x"65206173", -2920 => x"2061626f", -2921 => x"76650a00", -2922 => x"496e745f", -2923 => x"315f4c6f", -2924 => x"633a2020", -2925 => x"20202020", -2926 => x"20202020", -2927 => x"2025640a", -2928 => x"00000000", -2929 => x"496e745f", -2930 => x"325f4c6f", -2931 => x"633a2020", -2932 => x"20202020", -2933 => x"20202020", -2934 => x"2025640a", -2935 => x"00000000", -2936 => x"496e745f", -2937 => x"335f4c6f", -2938 => x"633a2020", -2939 => x"20202020", -2940 => x"20202020", -2941 => x"2025640a", -2942 => x"00000000", -2943 => x"456e756d", -2944 => x"5f4c6f63", -2945 => x"3a202020", -2946 => x"20202020", -2947 => x"20202020", -2948 => x"2025640a", -2949 => x"00000000", -2950 => x"5374725f", -2951 => x"315f4c6f", -2952 => x"633a2020", -2953 => x"20202020", -2954 => x"20202020", -2955 => x"2025730a", -2956 => x"00000000", -2957 => x"20202020", -2958 => x"20202020", -2959 => x"73686f75", -2960 => x"6c642062", -2961 => x"653a2020", -2962 => x"20444852", -2963 => x"5953544f", -2964 => x"4e452050", -2965 => x"524f4752", -2966 => x"414d2c20", -2967 => x"31275354", -2968 => x"20535452", -2969 => x"494e470a", -2970 => x"00000000", -2971 => x"5374725f", -2972 => x"325f4c6f", -2973 => x"633a2020", -2974 => x"20202020", -2975 => x"20202020", -2976 => x"2025730a", -2977 => x"00000000", -2978 => x"20202020", -2979 => x"20202020", -2980 => x"73686f75", -2981 => x"6c642062", -2982 => x"653a2020", -2983 => x"20444852", -2984 => x"5953544f", -2985 => x"4e452050", -2986 => x"524f4752", -2987 => x"414d2c20", -2988 => x"32274e44", -2989 => x"20535452", -2990 => x"494e470a", -2991 => x"00000000", -2992 => x"55736572", -2993 => x"2074696d", -2994 => x"653a2025", -2995 => x"640a0000", -2996 => x"4d696372", -2997 => x"6f736563", -2998 => x"6f6e6473", -2999 => x"20666f72", -3000 => x"206f6e65", -3001 => x"2072756e", -3002 => x"20746872", -3003 => x"6f756768", -3004 => x"20446872", -3005 => x"7973746f", -3006 => x"6e653a20", -3007 => x"00000000", -3008 => x"2564200a", -3009 => x"00000000", -3010 => x"44687279", -3011 => x"73746f6e", -3012 => x"65732070", -3013 => x"65722053", -3014 => x"65636f6e", -3015 => x"643a2020", -3016 => x"20202020", -3017 => x"20202020", -3018 => x"20202020", -3019 => x"20202020", -3020 => x"20202020", -3021 => x"00000000", -3022 => x"56415820", -3023 => x"4d495053", -3024 => x"20726174", -3025 => x"696e6720", -3026 => x"2a203130", -3027 => x"3030203d", -3028 => x"20256420", -3029 => x"0a000000", -3030 => x"50726f67", -3031 => x"72616d20", -3032 => x"636f6d70", -3033 => x"696c6564", -3034 => x"20776974", -3035 => x"686f7574", -3036 => x"20277265", -3037 => x"67697374", -3038 => x"65722720", -3039 => x"61747472", -3040 => x"69627574", -3041 => x"650a0000", -3042 => x"4d656173", -3043 => x"75726564", -3044 => x"2074696d", -3045 => x"6520746f", -3046 => x"6f20736d", -3047 => x"616c6c20", -3048 => x"746f206f", -3049 => x"62746169", -3050 => x"6e206d65", -3051 => x"616e696e", -3052 => x"6766756c", -3053 => x"20726573", -3054 => x"756c7473", -3055 => x"0a000000", -3056 => x"506c6561", -3057 => x"73652069", -3058 => x"6e637265", -3059 => x"61736520", -3060 => x"6e756d62", -3061 => x"6572206f", -3062 => x"66207275", -3063 => x"6e730a00", -3064 => x"44485259", -3065 => x"53544f4e", -3066 => x"45205052", -3067 => x"4f475241", -3068 => x"4d2c2033", -3069 => x"27524420", -3070 => x"53545249", -3071 => x"4e470000", -3072 => x"00010202", -3073 => x"03030303", -3074 => x"04040404", -3075 => x"04040404", -3076 => x"05050505", -3077 => x"05050505", -3078 => x"05050505", -3079 => x"05050505", -3080 => x"06060606", -3081 => x"06060606", -3082 => x"06060606", -3083 => x"06060606", -3084 => x"06060606", -3085 => x"06060606", -3086 => x"06060606", -3087 => x"06060606", -3088 => x"07070707", -3089 => x"07070707", -3090 => x"07070707", -3091 => x"07070707", -3092 => x"07070707", -3093 => x"07070707", -3094 => x"07070707", -3095 => x"07070707", -3096 => x"07070707", -3097 => x"07070707", -3098 => x"07070707", -3099 => x"07070707", -3100 => x"07070707", -3101 => x"07070707", -3102 => x"07070707", -3103 => x"07070707", -3104 => x"08080808", -3105 => x"08080808", -3106 => x"08080808", -3107 => x"08080808", -3108 => x"08080808", -3109 => x"08080808", -3110 => x"08080808", -3111 => x"08080808", -3112 => x"08080808", -3113 => x"08080808", -3114 => x"08080808", -3115 => x"08080808", -3116 => x"08080808", -3117 => x"08080808", -3118 => x"08080808", -3119 => x"08080808", -3120 => x"08080808", -3121 => x"08080808", -3122 => x"08080808", -3123 => x"08080808", -3124 => x"08080808", -3125 => x"08080808", -3126 => x"08080808", -3127 => x"08080808", -3128 => x"08080808", -3129 => x"08080808", -3130 => x"08080808", -3131 => x"08080808", -3132 => x"08080808", -3133 => x"08080808", -3134 => x"08080808", -3135 => x"08080808", -3136 => x"43000000", -3137 => x"64756d6d", -3138 => x"792e6578", -3139 => x"65000000", -3140 => x"00ffffff", -3141 => x"ff00ffff", -3142 => x"ffff00ff", -3143 => x"ffffff00", -3144 => x"00000000", -3145 => x"00000000", -3146 => x"00000000", -3147 => x"0000390c", -3148 => x"000004d2", -- iterations 0x4d2=1234 -3149 => x"00000000", -3150 => x"00000000", -3151 => x"00000000", -3152 => x"00000000", -3153 => x"00000000", -3154 => x"00000000", -3155 => x"00000000", -3156 => x"00000000", -3157 => x"00000000", -3158 => x"00000000", -3159 => x"00000000", -3160 => x"00000000", -3161 => x"00000000", -3162 => x"ffffffff", -3163 => x"00000000", -3164 => x"00020000", -3165 => x"00000000", -3166 => x"00000000", -3167 => x"00003174", -3168 => x"00003174", -3169 => x"0000317c", -3170 => x"0000317c", -3171 => x"00003184", -3172 => x"00003184", -3173 => x"0000318c", -3174 => x"0000318c", -3175 => x"00003194", -3176 => x"00003194", -3177 => x"0000319c", -3178 => x"0000319c", -3179 => x"000031a4", -3180 => x"000031a4", -3181 => x"000031ac", -3182 => x"000031ac", -3183 => x"000031b4", -3184 => x"000031b4", -3185 => x"000031bc", -3186 => x"000031bc", -3187 => x"000031c4", -3188 => x"000031c4", -3189 => x"000031cc", -3190 => x"000031cc", -3191 => x"000031d4", -3192 => x"000031d4", -3193 => x"000031dc", -3194 => x"000031dc", -3195 => x"000031e4", -3196 => x"000031e4", -3197 => x"000031ec", -3198 => x"000031ec", -3199 => x"000031f4", -3200 => x"000031f4", -3201 => x"000031fc", -3202 => x"000031fc", -3203 => x"00003204", -3204 => x"00003204", -3205 => x"0000320c", -3206 => x"0000320c", -3207 => x"00003214", -3208 => x"00003214", -3209 => x"0000321c", -3210 => x"0000321c", -3211 => x"00003224", -3212 => x"00003224", -3213 => x"0000322c", -3214 => x"0000322c", -3215 => x"00003234", -3216 => x"00003234", -3217 => x"0000323c", -3218 => x"0000323c", -3219 => x"00003244", -3220 => x"00003244", -3221 => x"0000324c", -3222 => x"0000324c", -3223 => x"00003254", -3224 => x"00003254", -3225 => x"0000325c", -3226 => x"0000325c", -3227 => x"00003264", -3228 => x"00003264", -3229 => x"0000326c", -3230 => x"0000326c", -3231 => x"00003274", -3232 => x"00003274", -3233 => x"0000327c", -3234 => x"0000327c", -3235 => x"00003284", -3236 => x"00003284", -3237 => x"0000328c", -3238 => x"0000328c", -3239 => x"00003294", -3240 => x"00003294", -3241 => x"0000329c", -3242 => x"0000329c", -3243 => x"000032a4", -3244 => x"000032a4", -3245 => x"000032ac", -3246 => x"000032ac", -3247 => x"000032b4", -3248 => x"000032b4", -3249 => x"000032bc", -3250 => x"000032bc", -3251 => x"000032c4", -3252 => x"000032c4", -3253 => x"000032cc", -3254 => x"000032cc", -3255 => x"000032d4", -3256 => x"000032d4", -3257 => x"000032dc", -3258 => x"000032dc", -3259 => x"000032e4", -3260 => x"000032e4", -3261 => x"000032ec", -3262 => x"000032ec", -3263 => x"000032f4", -3264 => x"000032f4", -3265 => x"000032fc", -3266 => x"000032fc", -3267 => x"00003304", -3268 => x"00003304", -3269 => x"0000330c", -3270 => x"0000330c", -3271 => x"00003314", -3272 => x"00003314", -3273 => x"0000331c", -3274 => x"0000331c", -3275 => x"00003324", -3276 => x"00003324", -3277 => x"0000332c", -3278 => x"0000332c", -3279 => x"00003334", -3280 => x"00003334", -3281 => x"0000333c", -3282 => x"0000333c", -3283 => x"00003344", -3284 => x"00003344", -3285 => x"0000334c", -3286 => x"0000334c", -3287 => x"00003354", -3288 => x"00003354", -3289 => x"0000335c", -3290 => x"0000335c", -3291 => x"00003364", -3292 => x"00003364", -3293 => x"0000336c", -3294 => x"0000336c", -3295 => x"00003374", -3296 => x"00003374", -3297 => x"0000337c", -3298 => x"0000337c", -3299 => x"00003384", -3300 => x"00003384", -3301 => x"0000338c", -3302 => x"0000338c", -3303 => x"00003394", -3304 => x"00003394", -3305 => x"0000339c", -3306 => x"0000339c", -3307 => x"000033a4", -3308 => x"000033a4", -3309 => x"000033ac", -3310 => x"000033ac", -3311 => x"000033b4", -3312 => x"000033b4", -3313 => x"000033bc", -3314 => x"000033bc", -3315 => x"000033c4", -3316 => x"000033c4", -3317 => x"000033cc", -3318 => x"000033cc", -3319 => x"000033d4", -3320 => x"000033d4", -3321 => x"000033dc", -3322 => x"000033dc", -3323 => x"000033e4", -3324 => x"000033e4", -3325 => x"000033ec", -3326 => x"000033ec", -3327 => x"000033f4", -3328 => x"000033f4", -3329 => x"000033fc", -3330 => x"000033fc", -3331 => x"00003404", -3332 => x"00003404", -3333 => x"0000340c", -3334 => x"0000340c", -3335 => x"00003414", -3336 => x"00003414", -3337 => x"0000341c", -3338 => x"0000341c", -3339 => x"00003424", -3340 => x"00003424", -3341 => x"0000342c", -3342 => x"0000342c", -3343 => x"00003434", -3344 => x"00003434", -3345 => x"0000343c", -3346 => x"0000343c", -3347 => x"00003444", -3348 => x"00003444", -3349 => x"0000344c", -3350 => x"0000344c", -3351 => x"00003454", -3352 => x"00003454", -3353 => x"0000345c", -3354 => x"0000345c", -3355 => x"00003464", -3356 => x"00003464", -3357 => x"0000346c", -3358 => x"0000346c", -3359 => x"00003474", -3360 => x"00003474", -3361 => x"0000347c", -3362 => x"0000347c", -3363 => x"00003484", -3364 => x"00003484", -3365 => x"0000348c", -3366 => x"0000348c", -3367 => x"00003494", -3368 => x"00003494", -3369 => x"0000349c", -3370 => x"0000349c", -3371 => x"000034a4", -3372 => x"000034a4", -3373 => x"000034ac", -3374 => x"000034ac", -3375 => x"000034b4", -3376 => x"000034b4", -3377 => x"000034bc", -3378 => x"000034bc", -3379 => x"000034c4", -3380 => x"000034c4", -3381 => x"000034cc", -3382 => x"000034cc", -3383 => x"000034d4", -3384 => x"000034d4", -3385 => x"000034dc", -3386 => x"000034dc", -3387 => x"000034e4", -3388 => x"000034e4", -3389 => x"000034ec", -3390 => x"000034ec", -3391 => x"000034f4", -3392 => x"000034f4", -3393 => x"000034fc", -3394 => x"000034fc", -3395 => x"00003504", -3396 => x"00003504", -3397 => x"0000350c", -3398 => x"0000350c", -3399 => x"00003514", -3400 => x"00003514", -3401 => x"0000351c", -3402 => x"0000351c", -3403 => x"00003524", -3404 => x"00003524", -3405 => x"0000352c", -3406 => x"0000352c", -3407 => x"00003534", -3408 => x"00003534", -3409 => x"0000353c", -3410 => x"0000353c", -3411 => x"00003544", -3412 => x"00003544", -3413 => x"0000354c", -3414 => x"0000354c", -3415 => x"00003554", -3416 => x"00003554", -3417 => x"0000355c", -3418 => x"0000355c", -3419 => x"00003564", -3420 => x"00003564", -3421 => x"0000356c", -3422 => x"0000356c", -3423 => x"00003580", -3424 => x"00000000", -3425 => x"000037e8", -3426 => x"00003844", -3427 => x"000038a0", -3428 => x"00000000", -3429 => x"00000000", -3430 => x"00000000", -3431 => x"00000000", -3432 => x"00000000", -3433 => x"00000000", -3434 => x"00000000", -3435 => x"00000000", -3436 => x"00000000", -3437 => x"00003100", -3438 => x"00000000", -3439 => x"00000000", -3440 => x"00000000", -3441 => x"00000000", -3442 => x"00000000", -3443 => x"00000000", -3444 => x"00000000", -3445 => x"00000000", -3446 => x"00000000", -3447 => x"00000000", -3448 => x"00000000", -3449 => x"00000000", -3450 => x"00000000", -3451 => x"00000000", -3452 => x"00000000", -3453 => x"00000000", -3454 => x"00000000", -3455 => x"00000000", -3456 => x"00000000", -3457 => x"00000000", -3458 => x"00000000", -3459 => x"00000000", -3460 => x"00000000", -3461 => x"00000000", -3462 => x"00000000", -3463 => x"00000000", -3464 => x"00000000", -3465 => x"00000000", -3466 => x"00000001", -3467 => x"330eabcd", -3468 => x"1234e66d", -3469 => x"deec0005", -3470 => x"000b0000", -3471 => x"00000000", -3472 => x"00000000", -3473 => x"00000000", -3474 => x"00000000", -3475 => x"00000000", -3476 => x"00000000", -3477 => x"00000000", -3478 => x"00000000", -3479 => x"00000000", -3480 => x"00000000", -3481 => x"00000000", -3482 => x"00000000", -3483 => x"00000000", -3484 => x"00000000", -3485 => x"00000000", -3486 => x"00000000", -3487 => x"00000000", -3488 => x"00000000", -3489 => x"00000000", -3490 => x"00000000", -3491 => x"00000000", -3492 => x"00000000", -3493 => x"00000000", -3494 => x"00000000", -3495 => x"00000000", -3496 => x"00000000", -3497 => x"00000000", -3498 => x"00000000", -3499 => x"00000000", -3500 => x"00000000", -3501 => x"00000000", -3502 => x"00000000", -3503 => x"00000000", -3504 => x"00000000", -3505 => x"00000000", -3506 => x"00000000", -3507 => x"00000000", -3508 => x"00000000", -3509 => x"00000000", -3510 => x"00000000", -3511 => x"00000000", -3512 => x"00000000", -3513 => x"00000000", -3514 => x"00000000", -3515 => x"00000000", -3516 => x"00000000", -3517 => x"00000000", -3518 => x"00000000", -3519 => x"00000000", -3520 => x"00000000", -3521 => x"00000000", -3522 => x"00000000", -3523 => x"00000000", -3524 => x"00000000", -3525 => x"00000000", -3526 => x"00000000", -3527 => x"00000000", -3528 => x"00000000", -3529 => x"00000000", -3530 => x"00000000", -3531 => x"00000000", -3532 => x"00000000", -3533 => x"00000000", -3534 => x"00000000", -3535 => x"00000000", -3536 => x"00000000", -3537 => x"00000000", -3538 => x"00000000", -3539 => x"00000000", -3540 => x"00000000", -3541 => x"00000000", -3542 => x"00000000", -3543 => x"00000000", -3544 => x"00000000", -3545 => x"00000000", -3546 => x"00000000", -3547 => x"00000000", -3548 => x"00000000", -3549 => x"00000000", -3550 => x"00000000", -3551 => x"00000000", -3552 => x"00000000", -3553 => x"00000000", -3554 => x"00000000", -3555 => x"00000000", -3556 => x"00000000", -3557 => x"00000000", -3558 => x"00000000", -3559 => x"00000000", -3560 => x"00000000", -3561 => x"00000000", -3562 => x"00000000", -3563 => x"00000000", -3564 => x"00000000", -3565 => x"00000000", -3566 => x"00000000", -3567 => x"00000000", -3568 => x"00000000", -3569 => x"00000000", -3570 => x"00000000", -3571 => x"00000000", -3572 => x"00000000", -3573 => x"00000000", -3574 => x"00000000", -3575 => x"00000000", -3576 => x"00000000", -3577 => x"00000000", -3578 => x"00000000", -3579 => x"00000000", -3580 => x"00000000", -3581 => x"00000000", -3582 => x"00000000", -3583 => x"00000000", -3584 => x"00000000", -3585 => x"00000000", -3586 => x"00000000", -3587 => x"00000000", -3588 => x"00000000", -3589 => x"00000000", -3590 => x"00000000", -3591 => x"00000000", -3592 => x"00000000", -3593 => x"00000000", -3594 => x"00000000", -3595 => x"00000000", -3596 => x"00000000", -3597 => x"00000000", -3598 => x"00000000", -3599 => x"00000000", -3600 => x"00000000", -3601 => x"00000000", -3602 => x"00000000", -3603 => x"00000000", -3604 => x"00000000", -3605 => x"00000000", -3606 => x"00000000", -3607 => x"00000000", -3608 => x"00000000", -3609 => x"00000000", -3610 => x"00000000", -3611 => x"00000000", -3612 => x"00000000", -3613 => x"00000000", -3614 => x"00000000", -3615 => x"00000000", -3616 => x"00000000", -3617 => x"00000000", -3618 => x"00000000", -3619 => x"00000000", -3620 => x"00000000", -3621 => x"00000000", -3622 => x"00000000", -3623 => x"00000000", -3624 => x"00000000", -3625 => x"00000000", -3626 => x"00000000", -3627 => x"00000000", -3628 => x"00000000", -3629 => x"00000000", -3630 => x"00000000", -3631 => x"00000000", -3632 => x"00000000", -3633 => x"00000000", -3634 => x"00000000", -3635 => x"00000000", -3636 => x"00000000", -3637 => x"00000000", -3638 => x"00000000", -3639 => x"00000000", -3640 => x"00000000", -3641 => x"00000000", -3642 => x"00000000", -3643 => x"00000000", -3644 => x"00000000", -3645 => x"00000000", -3646 => x"00000000", -3647 => x"00003104", -3648 => x"ffffffff", -3649 => x"00000000", -3650 => x"ffffffff", -3651 => x"00000000", - others => x"00000000" -); - -begin - -process (clk) -begin - if (clk'event and clk = '1') then - if (memAWriteEnable = '1') and (memBWriteEnable = '1') and (memAAddr=memBAddr) and (memAWrite/=memBWrite) then - report "write collision" severity failure; - end if; - - if (memAWriteEnable = '1') then - ram(to_integer(unsigned(memAAddr))) := memAWrite; - memARead <= memAWrite; - else - memARead <= ram(to_integer(unsigned(memAAddr))); - end if; - end if; -end process; - -process (clk) -begin - if (clk'event and clk = '1') then - if (memBWriteEnable = '1') then - ram(to_integer(unsigned(memBAddr))) := memBWrite; - memBRead <= memBWrite; - else - memBRead <= ram(to_integer(unsigned(memBAddr))); - end if; - end if; -end process; - - - - -end dualport_ram_arch; diff --git a/zpu/hdl/zpu4/src/dram_dmips.vhd b/zpu/hdl/zpu4/src/dram_dmips.vhd deleted file mode 100644 index a9fd59e..0000000 --- a/zpu/hdl/zpu4/src/dram_dmips.vhd +++ /dev/null @@ -1,3308 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity dram is -port (clk : in std_logic; -areset : std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); -end dram; - -architecture dram_arch of dram is - - -type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"0b0b0b0b", -1 => x"82700b0b", -2 => x"80d5f40c", -3 => x"3a0b0b80", -4 => x"c4fb0400", -5 => x"00000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80c5c22d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"04000000", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53510400", -38 => x"00000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51040000", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53510400", -55 => x"00000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51040000", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c3040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535104", -82 => x"00000000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a6", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"04000000", -102 => x"00000000", -103 => x"00000000", -104 => x"71715351", -105 => x"020d0406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51040000", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53510400", -125 => x"00000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52040000", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"04000000", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535104", -147 => x"00000000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"04000000", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80d5", -162 => x"e0738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88a90400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0bad", -171 => x"aa2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0bad", -179 => x"ee2d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547106", -188 => x"73097274", -189 => x"05ff0506", -190 => x"07515151", -191 => x"04000000", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"05705471", -196 => x"06730972", -197 => x"7405ff05", -198 => x"06075151", -199 => x"51040000", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"80d5f00c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"04000000", -218 => x"00000000", -219 => x"00000000", -220 => x"00000000", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"04000000", -235 => x"00000000", -236 => x"00000000", -237 => x"00000000", -238 => x"00000000", -239 => x"00000000", -240 => x"00000000", -241 => x"00000000", -242 => x"00000000", -243 => x"00000000", -244 => x"00000000", -245 => x"00000000", -246 => x"00000000", -247 => x"00000000", -248 => x"717105ff", -249 => x"05715351", -250 => x"020d0400", -251 => x"00000000", -252 => x"00000000", -253 => x"00000000", -254 => x"00000000", -255 => x"00000000", -256 => x"82fd3fbf", -257 => x"a03f0410", -258 => x"10101010", -259 => x"10101010", -260 => x"10101010", -261 => x"10101010", -262 => x"10101010", -263 => x"10101010", -264 => x"10101010", -265 => x"10105351", -266 => x"047381ff", -267 => x"06738306", -268 => x"09810583", -269 => x"05101010", -270 => x"2b0772fc", -271 => x"060c5151", -272 => x"043c0472", -273 => x"72807281", -274 => x"06ff0509", -275 => x"72060571", -276 => x"1052720a", -277 => x"100a5372", -278 => x"ed385151", -279 => x"535104ff", -280 => x"3d0d0b0b", -281 => x"80e5e408", -282 => x"52710870", -283 => x"882a8132", -284 => x"70810651", -285 => x"515170f1", -286 => x"3873720c", -287 => x"833d0d04", -288 => x"80d5f008", -289 => x"802ea438", -290 => x"80d5f408", -291 => x"822ebd38", -292 => x"8380800b", -293 => x"0b0b80e5", -294 => x"e40c82a0", -295 => x"800b80e5", -296 => x"e80c8290", -297 => x"800b80e5", -298 => x"ec0c04f8", -299 => x"808080a4", -300 => x"0b0b0b80", -301 => x"e5e40cf8", -302 => x"80808280", -303 => x"0b80e5e8", -304 => x"0cf88080", -305 => x"84800b80", -306 => x"e5ec0c04", -307 => x"80c0a880", -308 => x"8c0b0b0b", -309 => x"80e5e40c", -310 => x"80c0a880", -311 => x"940b80e5", -312 => x"e80c0b0b", -313 => x"80c7d00b", -314 => x"80e5ec0c", -315 => x"04f23d0d", -316 => x"6080e5e8", -317 => x"08565d82", -318 => x"750c8059", -319 => x"805a800b", -320 => x"8f3d5d5b", -321 => x"7a101015", -322 => x"70087108", -323 => x"719f2c7e", -324 => x"852b5855", -325 => x"557d5359", -326 => x"5799993f", -327 => x"7d7f7a72", -328 => x"077c7207", -329 => x"71716081", -330 => x"05415f5d", -331 => x"5b595755", -332 => x"817b278f", -333 => x"38767d0c", -334 => x"77841e0c", -335 => x"7c800c90", -336 => x"3d0d0480", -337 => x"e5e80855", -338 => x"ffba3970", -339 => x"7080e5f0", -340 => x"335170a7", -341 => x"3880d5fc", -342 => x"08700852", -343 => x"5270802e", -344 => x"94388412", -345 => x"80d5fc0c", -346 => x"702d80d5", -347 => x"fc087008", -348 => x"525270ee", -349 => x"38810b80", -350 => x"e5f03450", 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x"00002e0c", -2951 => x"00002e14", -2952 => x"00002e14", -2953 => x"00002e1c", -2954 => x"00002e1c", -2955 => x"00002e24", -2956 => x"00002e24", -2957 => x"00002e2c", -2958 => x"00002e2c", -2959 => x"00002e34", -2960 => x"00002e34", -2961 => x"00002e3c", -2962 => x"00002e3c", -2963 => x"00002e44", -2964 => x"00002e44", -2965 => x"00002e4c", -2966 => x"00002e4c", -2967 => x"00002e54", -2968 => x"00002e54", -2969 => x"00002e5c", -2970 => x"00002e5c", -2971 => x"00002e64", -2972 => x"00002e64", -2973 => x"00002e6c", -2974 => x"00002e6c", -2975 => x"00002e74", -2976 => x"00002e74", -2977 => x"00002e7c", -2978 => x"00002e7c", -2979 => x"00002e84", -2980 => x"00002e84", -2981 => x"00002e8c", -2982 => x"00002e8c", -2983 => x"00002e94", -2984 => x"00002e94", -2985 => x"00002e9c", -2986 => x"00002e9c", -2987 => x"00002ea4", -2988 => x"00002ea4", -2989 => x"00002eac", -2990 => x"00002eac", -2991 => x"00002eb4", -2992 => x"00002eb4", -2993 => x"00002ebc", -2994 => x"00002ebc", -2995 => x"00002ec4", -2996 => x"00002ec4", -2997 => x"00002ecc", -2998 => x"00002ecc", -2999 => x"00002ed4", -3000 => x"00002ed4", -3001 => x"00002edc", -3002 => x"00002edc", -3003 => x"00002ee4", -3004 => x"00002ee4", -3005 => x"00002eec", -3006 => x"00002eec", -3007 => x"00002ef4", -3008 => x"00002ef4", -3009 => x"00002efc", -3010 => x"00002efc", -3011 => x"00002f04", -3012 => x"00002f04", -3013 => x"00002f0c", -3014 => x"00002f0c", -3015 => x"00002f14", -3016 => x"00002f14", -3017 => x"00002f1c", -3018 => x"00002f1c", -3019 => x"00002f24", -3020 => x"00002f24", -3021 => x"00002f2c", -3022 => x"00002f2c", -3023 => x"00002f34", -3024 => x"00002f34", -3025 => x"00002f3c", -3026 => x"00002f3c", -3027 => x"00002f50", -3028 => x"00000000", -3029 => x"000031b8", -3030 => x"00003214", -3031 => x"00003270", -3032 => x"00000000", -3033 => x"00000000", -3034 => x"00000000", -3035 => x"00000000", -3036 => x"00000000", -3037 => x"00000000", -3038 => x"00000000", -3039 => x"00000000", -3040 => x"00000000", -3041 => x"00002ad0", -3042 => x"00000000", -3043 => x"00000000", -3044 => x"00000000", -3045 => x"00000000", -3046 => x"00000000", -3047 => x"00000000", -3048 => x"00000000", -3049 => x"00000000", -3050 => x"00000000", -3051 => x"00000000", -3052 => x"00000000", -3053 => x"00000000", -3054 => x"00000000", -3055 => x"00000000", -3056 => x"00000000", -3057 => x"00000000", -3058 => x"00000000", -3059 => x"00000000", -3060 => x"00000000", -3061 => x"00000000", -3062 => x"00000000", -3063 => x"00000000", -3064 => x"00000000", -3065 => x"00000000", -3066 => x"00000000", -3067 => x"00000000", -3068 => x"00000000", -3069 => x"00000000", -3070 => x"00000001", -3071 => x"330eabcd", -3072 => x"1234e66d", -3073 => x"deec0005", -3074 => x"000b0000", -3075 => x"00000000", -3076 => x"00000000", -3077 => x"00000000", -3078 => x"00000000", -3079 => x"00000000", -3080 => x"00000000", -3081 => x"00000000", -3082 => x"00000000", -3083 => x"00000000", -3084 => x"00000000", -3085 => x"00000000", -3086 => x"00000000", -3087 => x"00000000", -3088 => x"00000000", -3089 => x"00000000", -3090 => x"00000000", -3091 => x"00000000", -3092 => x"00000000", -3093 => x"00000000", -3094 => x"00000000", -3095 => x"00000000", -3096 => x"00000000", -3097 => x"00000000", -3098 => x"00000000", -3099 => x"00000000", -3100 => x"00000000", -3101 => x"00000000", -3102 => x"00000000", -3103 => x"00000000", -3104 => x"00000000", -3105 => x"00000000", -3106 => x"00000000", -3107 => x"00000000", -3108 => x"00000000", -3109 => x"00000000", -3110 => x"00000000", -3111 => x"00000000", -3112 => x"00000000", -3113 => x"00000000", -3114 => x"00000000", -3115 => x"00000000", -3116 => x"00000000", -3117 => x"00000000", -3118 => x"00000000", -3119 => x"00000000", -3120 => x"00000000", -3121 => x"00000000", -3122 => x"00000000", -3123 => x"00000000", -3124 => x"00000000", -3125 => x"00000000", -3126 => x"00000000", -3127 => x"00000000", -3128 => x"00000000", -3129 => x"00000000", -3130 => x"00000000", -3131 => x"00000000", -3132 => x"00000000", -3133 => x"00000000", -3134 => x"00000000", -3135 => x"00000000", -3136 => x"00000000", -3137 => x"00000000", -3138 => x"00000000", -3139 => x"00000000", -3140 => x"00000000", -3141 => x"00000000", -3142 => x"00000000", -3143 => x"00000000", -3144 => x"00000000", -3145 => x"00000000", -3146 => x"00000000", -3147 => x"00000000", -3148 => x"00000000", -3149 => x"00000000", -3150 => x"00000000", -3151 => x"00000000", -3152 => x"00000000", -3153 => x"00000000", -3154 => x"00000000", -3155 => x"00000000", -3156 => x"00000000", -3157 => x"00000000", -3158 => x"00000000", -3159 => x"00000000", -3160 => x"00000000", -3161 => x"00000000", -3162 => x"00000000", -3163 => x"00000000", -3164 => x"00000000", -3165 => x"00000000", -3166 => x"00000000", -3167 => x"00000000", -3168 => x"00000000", -3169 => x"00000000", -3170 => x"00000000", -3171 => x"00000000", -3172 => x"00000000", -3173 => x"00000000", -3174 => x"00000000", -3175 => x"00000000", -3176 => x"00000000", -3177 => x"00000000", -3178 => x"00000000", -3179 => x"00000000", -3180 => x"00000000", -3181 => x"00000000", -3182 => x"00000000", -3183 => x"00000000", -3184 => x"00000000", -3185 => x"00000000", -3186 => x"00000000", -3187 => x"00000000", -3188 => x"00000000", -3189 => x"00000000", -3190 => x"00000000", -3191 => x"00000000", -3192 => x"00000000", -3193 => x"00000000", -3194 => x"00000000", -3195 => x"00000000", -3196 => x"00000000", -3197 => x"00000000", -3198 => x"00000000", -3199 => x"00000000", -3200 => x"00000000", -3201 => x"00000000", -3202 => x"00000000", -3203 => x"00000000", -3204 => x"00000000", -3205 => x"00000000", -3206 => x"00000000", -3207 => x"00000000", -3208 => x"00000000", -3209 => x"00000000", -3210 => x"00000000", -3211 => x"00000000", -3212 => x"00000000", -3213 => x"00000000", -3214 => x"00000000", -3215 => x"00000000", -3216 => x"00000000", -3217 => x"00000000", -3218 => x"00000000", -3219 => x"00000000", -3220 => x"00000000", -3221 => x"00000000", -3222 => x"00000000", -3223 => x"00000000", -3224 => x"00000000", -3225 => x"00000000", -3226 => x"00000000", -3227 => x"00000000", -3228 => x"00000000", -3229 => x"00000000", -3230 => x"00000000", -3231 => x"00000000", -3232 => x"00000000", -3233 => x"00000000", -3234 => x"00000000", -3235 => x"00000000", -3236 => x"00000000", -3237 => x"00000000", -3238 => x"00000000", -3239 => x"00000000", -3240 => x"00000000", -3241 => x"00000000", -3242 => x"00000000", -3243 => x"00000000", -3244 => x"00000000", -3245 => x"00000000", -3246 => x"00000000", -3247 => x"00000000", -3248 => x"00000000", -3249 => x"00000000", -3250 => x"00000000", -3251 => x"00002ad4", -3252 => x"ffffffff", -3253 => x"00000000", -3254 => x"ffffffff", -3255 => x"00000000", - others => x"00000000" -); - -begin - -mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request - -process (clk, areset) -begin - if areset = '1' then - elsif (clk'event and clk = '1') then - if (mem_writeEnable = '1') then - ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; - end if; - if (mem_readEnable = '1') then - mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); - end if; - end if; -end process; - - - - -end dram_arch; diff --git a/zpu/hdl/zpu4/src/dram_hello.vhd b/zpu/hdl/zpu4/src/dram_hello.vhd deleted file mode 100644 index 4f02cca..0000000 --- a/zpu/hdl/zpu4/src/dram_hello.vhd +++ /dev/null @@ -1,3107 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity dram is -port (clk : in std_logic; -areset : std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); -end dram; - -architecture dram_arch of dram is - - -type ram_type is array(natural range 0 to ((2**(maxAddrBitDRAM+1))/4)-1) of std_logic_vector(wordSize-1 downto 0); - -shared variable ram : ram_type := -( -0 => x"0b0b0b0b", -1 => x"82700b0b", -2 => x"80cfd80c", -3 => x"3a0b0b80", -4 => x"c6d00400", -5 => x"00000000", -6 => x"00000000", -7 => x"00000000", -8 => x"80088408", -9 => x"88080b0b", -10 => x"80c7972d", -11 => x"880c840c", -12 => x"800c0400", -13 => x"00000000", -14 => x"00000000", -15 => x"00000000", -16 => x"71fd0608", -17 => x"72830609", -18 => x"81058205", -19 => x"832b2a83", -20 => x"ffff0652", -21 => x"04000000", -22 => x"00000000", -23 => x"00000000", -24 => x"71fd0608", -25 => x"83ffff73", -26 => x"83060981", -27 => x"05820583", -28 => x"2b2b0906", -29 => x"7383ffff", -30 => x"0b0b0b0b", -31 => x"83a70400", -32 => x"72098105", -33 => x"72057373", -34 => x"09060906", -35 => x"73097306", -36 => x"070a8106", -37 => x"53510400", -38 => x"00000000", -39 => x"00000000", -40 => x"72722473", -41 => x"732e0753", -42 => x"51040000", -43 => x"00000000", -44 => x"00000000", -45 => x"00000000", -46 => x"00000000", -47 => x"00000000", -48 => x"71737109", -49 => x"71068106", -50 => x"30720a10", -51 => x"0a720a10", -52 => x"0a31050a", -53 => x"81065151", -54 => x"53510400", -55 => x"00000000", -56 => x"72722673", -57 => x"732e0753", -58 => x"51040000", -59 => x"00000000", -60 => x"00000000", -61 => x"00000000", -62 => x"00000000", -63 => x"00000000", -64 => x"00000000", -65 => x"00000000", -66 => x"00000000", -67 => x"00000000", -68 => x"00000000", -69 => x"00000000", -70 => x"00000000", -71 => x"00000000", -72 => x"0b0b0b88", -73 => x"c4040000", -74 => x"00000000", -75 => x"00000000", -76 => x"00000000", -77 => x"00000000", -78 => x"00000000", -79 => x"00000000", -80 => x"720a722b", -81 => x"0a535104", -82 => x"00000000", -83 => x"00000000", -84 => x"00000000", -85 => x"00000000", -86 => x"00000000", -87 => x"00000000", -88 => x"72729f06", -89 => x"0981050b", -90 => x"0b0b88a7", -91 => x"05040000", -92 => x"00000000", -93 => x"00000000", -94 => x"00000000", -95 => x"00000000", -96 => x"72722aff", -97 => x"739f062a", -98 => x"0974090a", -99 => x"8106ff05", -100 => x"06075351", -101 => x"04000000", -102 => x"00000000", -103 => x"00000000", -104 => x"71715351", -105 => x"020d0406", -106 => x"73830609", -107 => x"81058205", -108 => x"832b0b2b", -109 => x"0772fc06", -110 => x"0c515104", -111 => x"00000000", -112 => x"72098105", -113 => x"72050970", -114 => x"81050906", -115 => x"0a810653", -116 => x"51040000", -117 => x"00000000", -118 => x"00000000", -119 => x"00000000", -120 => x"72098105", -121 => x"72050970", -122 => x"81050906", -123 => x"0a098106", -124 => x"53510400", -125 => x"00000000", -126 => x"00000000", -127 => x"00000000", -128 => x"71098105", -129 => x"52040000", -130 => x"00000000", -131 => x"00000000", -132 => x"00000000", -133 => x"00000000", -134 => x"00000000", -135 => x"00000000", -136 => x"72720981", -137 => x"05055351", -138 => x"04000000", -139 => x"00000000", -140 => x"00000000", -141 => x"00000000", -142 => x"00000000", -143 => x"00000000", -144 => x"72097206", -145 => x"73730906", -146 => x"07535104", -147 => x"00000000", -148 => x"00000000", -149 => x"00000000", -150 => x"00000000", -151 => x"00000000", -152 => x"71fc0608", -153 => x"72830609", -154 => x"81058305", -155 => x"1010102a", -156 => x"81ff0652", -157 => x"04000000", -158 => x"00000000", -159 => x"00000000", -160 => x"71fc0608", -161 => x"0b0b80cf", -162 => x"c4738306", -163 => x"10100508", -164 => x"060b0b0b", -165 => x"88aa0400", -166 => x"00000000", -167 => x"00000000", -168 => x"80088408", -169 => x"88087575", -170 => x"0b0b0b8b", -171 => x"9f2d5050", -172 => x"80085688", -173 => x"0c840c80", -174 => x"0c510400", -175 => x"00000000", -176 => x"80088408", -177 => x"88087575", -178 => x"0b0b0b8b", -179 => x"e32d5050", -180 => x"80085688", -181 => x"0c840c80", -182 => x"0c510400", -183 => x"00000000", -184 => x"72097081", -185 => x"0509060a", -186 => x"8106ff05", -187 => x"70547106", -188 => x"73097274", -189 => x"05ff0506", -190 => x"07515151", -191 => x"04000000", -192 => x"72097081", -193 => x"0509060a", -194 => x"098106ff", -195 => x"05705471", -196 => x"06730972", -197 => x"7405ff05", -198 => x"06075151", -199 => x"51040000", -200 => x"05ff0504", -201 => x"00000000", -202 => x"00000000", -203 => x"00000000", -204 => x"00000000", -205 => x"00000000", -206 => x"00000000", -207 => x"00000000", -208 => x"810b0b0b", -209 => x"80cfd40c", -210 => x"51040000", -211 => x"00000000", -212 => x"00000000", -213 => x"00000000", -214 => x"00000000", -215 => x"00000000", -216 => x"71810552", -217 => x"04000000", -218 => x"00000000", -219 => x"00000000", -220 => x"00000000", -221 => x"00000000", -222 => x"00000000", -223 => x"00000000", -224 => x"00000000", -225 => x"00000000", -226 => x"00000000", -227 => x"00000000", -228 => x"00000000", -229 => x"00000000", -230 => x"00000000", -231 => x"00000000", -232 => x"02840572", -233 => x"10100552", -234 => x"04000000", -235 => x"00000000", -236 => x"00000000", -237 => x"00000000", -238 => x"00000000", -239 => x"00000000", -240 => x"00000000", -241 => x"00000000", -242 => x"00000000", -243 => x"00000000", -244 => x"00000000", -245 => x"00000000", -246 => x"00000000", -247 => x"00000000", -248 => x"717105ff", -249 => x"05715351", -250 => x"020d0400", -251 => x"00000000", -252 => x"00000000", -253 => x"00000000", -254 => x"00000000", -255 => x"00000000", -256 => x"82c53f80", -257 => x"c6d93f04", -258 => x"10101010", -259 => x"10101010", -260 => x"10101010", -261 => x"10101010", -262 => x"10101010", -263 => x"10101010", -264 => x"10101010", -265 => x"10101053", -266 => x"51047381", -267 => x"ff067383", -268 => x"06098105", -269 => x"83051010", -270 => x"102b0772", -271 => x"fc060c51", -272 => x"51043c04", -273 => x"72728072", -274 => x"8106ff05", -275 => x"09720605", -276 => x"71105272", -277 => x"0a100a53", -278 => x"72ed3851", -279 => x"51535104", -280 => x"fe3d0d0b", -281 => x"0b80dfc0", -282 => x"08538413", -283 => x"0870882a", -284 => x"70810651", -285 => x"52527080", -286 => x"2ef03871", -287 => x"81ff0680", -288 => x"0c843d0d", -289 => x"04ff3d0d", -290 => x"0b0b80df", -291 => x"c0085271", -292 => x"0870882a", -293 => x"81327081", -294 => x"06515151", -295 => x"70f13873", -296 => x"720c833d", -297 => x"0d0480cf", -298 => x"d408802e", -299 => x"a43880cf", -300 => x"d808822e", -301 => x"bd388380", -302 => x"800b0b0b", -303 => x"80dfc00c", -304 => x"82a0800b", -305 => x"80dfc40c", -306 => x"8290800b", -307 => x"80dfc80c", -308 => x"04f88080", -309 => x"80a40b0b", -310 => x"0b80dfc0", -311 => x"0cf88080", -312 => x"82800b80", -313 => x"dfc40cf8", -314 => x"80808480", -315 => x"0b80dfc8", -316 => x"0c0480c0", -317 => x"a8808c0b", -318 => x"0b0b80df", -319 => x"c00c80c0", -320 => x"a880940b", -321 => x"80dfc40c", -322 => x"0b0b80cf", -323 => x"8c0b80df", -324 => x"c80c0470", -325 => x"7080dfcc", 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x"00002cf8", -2882 => x"00002d00", -2883 => x"00002d00", -2884 => x"00002d08", -2885 => x"00002d08", -2886 => x"00002d10", -2887 => x"00002d10", -2888 => x"00002d18", -2889 => x"00002d18", -2890 => x"00002d20", -2891 => x"00002d20", -2892 => x"00002d28", -2893 => x"00002d28", -2894 => x"00002d30", -2895 => x"00002d30", -2896 => x"00002d38", -2897 => x"00002d38", -2898 => x"00002d40", -2899 => x"00002d40", -2900 => x"00002d48", -2901 => x"00002d48", -2902 => x"00002d50", -2903 => x"00002d50", -2904 => x"00002d58", -2905 => x"00002d58", -2906 => x"00002d60", -2907 => x"00002d60", -2908 => x"00002d68", -2909 => x"00002d68", -2910 => x"00002d70", -2911 => x"00002d70", -2912 => x"00002d78", -2913 => x"00002d78", -2914 => x"00002d80", -2915 => x"00002d80", -2916 => x"00002d88", -2917 => x"00002d88", -2918 => x"00002d90", -2919 => x"00002d90", -2920 => x"00002d98", -2921 => x"00002d98", -2922 => x"00002da0", -2923 => x"00002da0", -2924 => x"00002da8", -2925 => x"00002da8", -2926 => x"00002db0", -2927 => x"00002db0", -2928 => x"00002db8", -2929 => x"00002db8", -2930 => x"00002dc0", -2931 => x"00002dc0", -2932 => x"00002dc8", -2933 => x"00002dc8", -2934 => x"00002dd0", -2935 => x"00002dd0", -2936 => x"00002dd8", -2937 => x"00002dd8", -2938 => x"00002de0", -2939 => x"00002de0", -2940 => x"00002de8", -2941 => x"00002de8", -2942 => x"00002df0", -2943 => x"00002df0", -2944 => x"00002df8", -2945 => x"00002df8", -2946 => x"00002e00", -2947 => x"00002e00", -2948 => x"00002e08", -2949 => x"00002e08", -2950 => x"00002e10", -2951 => x"00002e10", -2952 => x"00002e18", -2953 => x"00002e18", -2954 => x"00002e20", -2955 => x"00002e20", -2956 => x"00002e28", -2957 => x"00002e28", -2958 => x"00002e30", -2959 => x"00002e30", -2960 => x"00002e38", -2961 => x"00002e38", -2962 => x"00002e40", -2963 => x"00002e40", -2964 => x"00002e48", -2965 => x"00002e48", -2966 => x"00002e50", -2967 => x"00002e50", -2968 => x"00002e58", -2969 => x"00002e58", -2970 => x"00002e60", -2971 => x"00002e60", -2972 => x"00002e68", -2973 => x"00002e68", -2974 => x"00002e70", -2975 => x"00002e70", -2976 => x"00002e78", -2977 => x"00002e78", -2978 => x"00002e80", -2979 => x"00002e80", -2980 => x"00002e88", -2981 => x"00002e88", -2982 => x"00002e90", -2983 => x"00002e90", -2984 => x"00002e98", -2985 => x"00002e98", -2986 => x"00002ea0", -2987 => x"00002ea0", -2988 => x"00002ea8", -2989 => x"00002ea8", -2990 => x"00002eb0", -2991 => x"00002eb0", -2992 => x"00002eb8", -2993 => x"00002eb8", -2994 => x"00002ec0", -2995 => x"00002ec0", -2996 => x"00002ec8", -2997 => x"00002ec8", -2998 => x"00002ed0", -2999 => x"00002ed0", -3000 => x"00002ed8", -3001 => x"00002ed8", -3002 => x"00002ee0", -3003 => x"00002ee0", -3004 => x"00002ee8", -3005 => x"00002ee8", -3006 => x"00002ef0", -3007 => x"00002ef0", -3008 => x"00002ef8", -3009 => x"00002ef8", -3010 => x"00002f00", -3011 => x"00002f00", -3012 => x"00002f08", -3013 => x"00002f08", -3014 => x"00002f10", -3015 => x"00002f10", -3016 => x"00002f18", -3017 => x"00002f18", -3018 => x"00002f20", -3019 => x"00002f20", -3020 => x"00002f28", -3021 => x"00002f28", -3022 => x"00002f30", -3023 => x"00002f30", -3024 => x"00002f38", -3025 => x"00002f38", -3026 => x"00002f40", -3027 => x"00002f40", -3028 => x"00002f48", -3029 => x"00002f48", -3030 => x"00002f50", -3031 => x"00002f50", -3032 => x"00002f58", -3033 => x"00002f58", -3034 => x"00002f60", -3035 => x"00002f60", -3036 => x"00002f68", -3037 => x"00002f68", -3038 => x"00002f70", -3039 => x"00002f70", -3040 => x"00002f78", -3041 => x"00002f78", -3042 => x"00002f80", -3043 => x"00002f80", -3044 => x"00002f88", -3045 => x"00002f88", -3046 => x"00002f90", -3047 => x"00002f90", -3048 => x"00002f98", -3049 => x"00002f98", -3050 => x"000027b8", -3051 => x"ffffffff", -3052 => x"00000000", -3053 => x"ffffffff", -3054 => x"00000000", - others => x"00000000" -); - -begin - -mem_busy<=mem_readEnable; -- we're done on the cycle after we serve the read request - -process (clk, areset) -begin - if areset = '1' then - elsif (clk'event and clk = '1') then - if (mem_writeEnable = '1') then - ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))) := mem_write; - end if; - if (mem_readEnable = '1') then - mem_read <= ram(to_integer(unsigned(mem_addr(maxAddrBit downto minAddrBit)))); - end if; - end if; -end process; - - - - -end dram_arch; diff --git a/zpu/hdl/zpu4/src/zpu_config_trace.vhd b/zpu/hdl/zpu4/src/zpu_config_trace.vhd deleted file mode 100644 index d765d9a..0000000 --- a/zpu/hdl/zpu4/src/zpu_config_trace.vhd +++ /dev/null @@ -1,17 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -package zpu_config is - - constant Generate_Trace : boolean := true; - constant wordPower : integer := 5; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := '0'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; - constant maxAddrBitIncIO : integer := 27; - constant maxAddrBitDRAM : integer := 16; - constant maxAddrBitBRAM : integer := 16; - constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"001fff8"; - -end zpu_config; diff --git a/zpu/hdl/zpu4/test/interrupt/int.bin b/zpu/hdl/zpu4/test/interrupt/int.bin index 94cbe31..282f53b 100644 Binary files a/zpu/hdl/zpu4/test/interrupt/int.bin and b/zpu/hdl/zpu4/test/interrupt/int.bin differ diff --git a/zpu/hdl/zpu4/test/interrupt/int.c b/zpu/hdl/zpu4/test/interrupt/int.c index 1b6ec01..6ab28f7 100644 --- a/zpu/hdl/zpu4/test/interrupt/int.c +++ b/zpu/hdl/zpu4/test/interrupt/int.c @@ -4,11 +4,15 @@ #include -int counter; +volatile int counter; /* Example of single, fixed interval non-maskable, nested interrupt. The interrupt signal is * held high for enough cycles to guarantee that it will be noticed, i.e. longer than * any io access + 4 cycles roughly. + * + * Any non-trivial interrupt controller would have support for + * acknowledging interrupts(i.e. keep interrupts asserted until + * software acknowledges them via memory mapped IO). */ void _zpu_interrupt(void) { @@ -29,6 +33,7 @@ int main(int argc, char **argv) } else { puts("Got interrupt\n"); + t=counter; } } diff --git a/zpu/hdl/zpu4/test/interrupt/int.elf b/zpu/hdl/zpu4/test/interrupt/int.elf index a550987..346d148 100644 Binary files a/zpu/hdl/zpu4/test/interrupt/int.elf and b/zpu/hdl/zpu4/test/interrupt/int.elf differ diff --git a/zpu/hdl/zpu4/test/interrupt/int.ram b/zpu/hdl/zpu4/test/interrupt/int.ram index bcb424a..6751ec2 100644 --- a/zpu/hdl/zpu4/test/interrupt/int.ram +++ b/zpu/hdl/zpu4/test/interrupt/int.ram @@ -2,7 +2,7 @@ 1 => x"82700b0b", 2 => x"80cfe00c", 3 => x"3a0b0b80", -4 => x"c6e10400", +4 => x"c6e00400", 5 => x"00000000", 6 => x"00000000", 7 => x"00000000", @@ -169,7 +169,7 @@ 168 => x"80088408", 169 => x"88087575", 170 => x"0b0b0b8b", -171 => x"ac2d5050", +171 => x"ab2d5050", 172 => x"80085688", 173 => x"0c840c80", 174 => x"0c510400", @@ -177,7 +177,7 @@ 176 => x"80088408", 177 => x"88087575", 178 => x"0b0b0b8b", -179 => x"f02d5050", +179 => x"ef2d5050", 180 => x"80085688", 181 => x"0c840c80", 182 => x"0c510400", @@ -255,7 +255,7 @@ 254 => x"00000000", 255 => x"00000000", 256 => x"82c53f80", -257 => x"c6e73f04", +257 => x"c6e63f04", 258 => x"10101010", 259 => x"10101010", 260 => x"10101010", @@ -346,2192 +346,2192 @@ 345 => x"dfc4510b", 346 => x"0b0bf594", 347 => x"3f500404", -348 => x"80dfe008", -349 => x"810580df", -350 => x"e00c04fe", -351 => x"3d0d80df", -352 => x"e0087054", -353 => x"5272722e", -354 => x"953880cf", -355 => x"9c5182bb", -356 => x"3f80dfe0", -357 => x"08527272", -358 => x"2e098106", -359 => x"ed3880cf", -360 => x"ac5182a7", -361 => x"3f80dfe0", -362 => x"0852eb39", -363 => x"fb3d0d77", -364 => x"79555580", -365 => x"56757524", -366 => x"ab388074", -367 => x"249d3880", -368 => x"53735274", -369 => x"5180e13f", -370 => x"80085475", -371 => x"802e8538", -372 => x"80083054", -373 => x"73800c87", -374 => x"3d0d0473", -375 => x"30768132", -376 => x"5754dc39", -377 => x"74305581", -378 => x"56738025", -379 => x"d238ec39", -380 => x"fa3d0d78", -381 => x"7a575580", -382 => x"57767524", -383 => x"a438759f", -384 => x"2c548153", -385 => x"75743274", -386 => x"31527451", -387 => x"9b3f8008", -388 => x"5476802e", -389 => x"85388008", -390 => x"30547380", -391 => x"0c883d0d", -392 => x"04743055", -393 => x"8157d739", -394 => x"fc3d0d76", -395 => x"78535481", -396 => x"53807473", -397 => x"26525572", -398 => x"802e9838", -399 => x"70802eab", -400 => x"38807224", -401 => x"a6387110", -402 => x"73107572", -403 => x"26535452", -404 => x"72ea3873", -405 => x"51788338", -406 => x"74517080", -407 => x"0c863d0d", -408 => x"04720a10", -409 => x"0a720a10", -410 => x"0a535372", -411 => x"802ee438", -412 => x"717426ed", -413 => x"38737231", -414 => x"75740774", -415 => x"0a100a74", -416 => x"0a100a55", -417 => x"555654e3", -418 => x"39f73d0d", -419 => x"7c705253", -420 => x"80fd3f72", -421 => x"54800855", -422 => x"0b0b80cf", -423 => x"b8568157", -424 => x"80088105", -425 => x"5a8b3de4", -426 => x"11595382", -427 => x"59f41352", -428 => x"7b881108", -429 => x"525381b4", -430 => x"3f800830", -431 => x"70800807", -432 => x"9f2c8a07", -433 => x"800c538b", -434 => x"3d0d04f6", -435 => x"3d0d7c80", -436 => x"cfec0871", -437 => x"535553b7", -438 => x"3f725580", -439 => x"08560b0b", -440 => x"80cfb857", -441 => x"81588008", -442 => x"81055b8c", -443 => x"3de4115a", -444 => x"53825af4", -445 => x"13528814", -446 => x"085180f0", -447 => x"3f800830", -448 => x"70800807", -449 => x"9f2c8a07", -450 => x"800c548c", -451 => x"3d0d0470", -452 => x"70707075", -453 => x"70718306", -454 => x"53555270", -455 => x"b4387170", -456 => x"087009f7", -457 => x"fbfdff12", -458 => x"06f88482", -459 => x"81800654", -460 => x"5253719b", -461 => x"38841370", -462 => x"087009f7", -463 => x"fbfdff12", -464 => x"06f88482", -465 => x"81800654", -466 => x"52537180", -467 => x"2ee73872", -468 => x"52713353", -469 => x"72802e8a", -470 => x"38811270", -471 => x"33545272", -472 => x"f8387174", -473 => x"31800c50", -474 => x"50505004", -475 => x"f23d0d60", -476 => x"62881108", -477 => x"7058565f", -478 => x"5a73802e", -479 => x"818c388c", -480 => x"1a227083", -481 => x"2a813281", -482 => x"06565874", -483 => x"8638901a", -484 => x"08913879", -485 => x"5190b73f", -486 => x"ff558008", -487 => x"80ec388c", -488 => x"1a22587d", -489 => x"08558078", -490 => x"83ffff06", -491 => x"700a100a", -492 => x"8106415c", -493 => x"577e772e", -494 => x"80d73876", -495 => x"90387408", -496 => x"84160888", -497 => x"17575856", -498 => x"76802ef2", -499 => x"38765488", -500 => x"80772784", -501 => x"38888054", -502 => x"73537552", -503 => x"9c1a0851", -504 => x"a41a0858", -505 => x"772d800b", -506 => x"80082582", -507 => x"e0388008", -508 => x"16778008", -509 => x"317f8805", -510 => x"08800831", -511 => x"70618805", -512 => x"0c5b5856", -513 => x"78ffb438", -514 => x"80557480", -515 => x"0c903d0d", -516 => x"047a8132", -517 => x"81067740", -518 => x"5675802e", -519 => x"81bd3876", -520 => x"90387408", -521 => x"84160888", -522 => x"17575859", -523 => x"76802ef2", -524 => x"38881a08", -525 => x"7883ffff", -526 => x"0670892a", -527 => x"81065659", -528 => x"5673802e", -529 => x"82f83875", -530 => x"77278b38", -531 => x"77872a81", -532 => x"065c7b82", -533 => x"b5387676", -534 => x"27833876", -535 => x"56755378", -536 => x"52790851", -537 => x"85833f88", -538 => x"1a087631", -539 => x"881b0c79", -540 => x"08167a0c", -541 => x"76567519", -542 => x"7777317f", -543 => x"88050878", -544 => x"31706188", -545 => x"050c4158", -546 => x"597e802e", -547 => x"fefa388c", -548 => x"1a2258ff", -549 => x"8a397879", -550 => x"547c537b", -551 => x"525684c9", -552 => x"3f881a08", -553 => x"7931881b", -554 => x"0c790819", -555 => x"7a0c7c76", -556 => x"315d7c8e", -557 => x"3879518f", -558 => x"f23f8008", -559 => x"818f3880", -560 => x"085f751c", -561 => x"7777317f", -562 => x"88050878", -563 => x"31706188", -564 => x"050c5d58", -565 => x"5c7a802e", -566 => x"feae3876", -567 => x"81833874", -568 => x"08841608", -569 => x"88175758", -570 => x"5c76802e", -571 => x"f2387653", -572 => x"8a527b51", -573 => x"82d33f80", -574 => x"087c3181", -575 => x"055d8008", -576 => x"84388117", -577 => x"5d815f7c", -578 => x"59767d27", -579 => x"83387659", -580 => x"941a0888", -581 => x"1b081157", -582 => x"58807a08", -583 => x"5c54901a", -584 => x"087b2783", -585 => x"38815475", -586 => x"79258438", -587 => x"73ba3877", -588 => x"7924fee2", -589 => x"3877537b", -590 => x"529c1a08", -591 => x"51a41a08", -592 => x"59782d80", -593 => x"08568008", -594 => x"8024fee2", -595 => x"388c1a22", -596 => x"80c0075e", -597 => x"7d8c1b23", -598 => x"ff557480", -599 => x"0c903d0d", -600 => x"047effa3", -601 => x"38ff8739", -602 => x"75537b52", -603 => x"7a5182f9", -604 => x"3f790816", -605 => x"7a0c7951", -606 => x"8eb13f80", -607 => x"08cf387c", -608 => x"76315d7c", -609 => x"febc38fe", -610 => x"ac39901a", -611 => x"087a0871", -612 => x"31781170", -613 => x"565a5752", -614 => x"80cfec08", -615 => x"5184943f", -616 => x"8008802e", -617 => x"ffa73880", -618 => x"08901b0c", -619 => x"8008167a", -620 => x"0c77941b", -621 => x"0c76881b", -622 => x"0c7656fd", -623 => x"99397908", -624 => x"58901a08", -625 => x"78278338", -626 => x"81547577", -627 => x"27843873", -628 => x"b338941a", -629 => x"08547377", -630 => x"2680d338", -631 => x"73537852", -632 => x"9c1a0851", -633 => x"a41a0858", -634 => x"772d8008", -635 => x"56800880", -636 => x"24fd8338", -637 => x"8c1a2280", -638 => x"c0075e7d", -639 => x"8c1b23ff", -640 => x"55fed739", -641 => x"75537852", -642 => x"775181dd", -643 => x"3f790816", -644 => x"7a0c7951", -645 => x"8d953f80", -646 => x"08802efc", -647 => x"d9388c1a", -648 => x"2280c007", -649 => x"5e7d8c1b", -650 => x"23ff55fe", -651 => x"ad397677", -652 => x"54795378", -653 => x"525681b1", -654 => x"3f881a08", -655 => x"7731881b", -656 => x"0c790817", -657 => x"7a0cfcae", -658 => x"39fa3d0d", -659 => x"7a790288", -660 => x"05a70533", -661 => x"55535483", -662 => x"742780df", -663 => x"38718306", -664 => x"517080d7", -665 => x"38717157", -666 => x"55835175", -667 => x"82802913", -668 => x"ff125256", -669 => x"708025f3", -670 => x"38837427", -671 => x"bc387408", -672 => x"76327009", -673 => x"f7fbfdff", -674 => x"1206f884", -675 => x"82818006", -676 => x"51517080", -677 => x"2e983874", -678 => x"51805270", -679 => x"33577277", -680 => x"2eb93881", -681 => x"11811353", -682 => x"51837227", -683 => x"ee38fc14", -684 => x"84165654", -685 => x"738326c6", -686 => x"387452ff", -687 => x"145170ff", -688 => x"2e973871", -689 => x"33547274", -690 => x"2e983881", -691 => x"12ff1252", -692 => x"5270ff2e", -693 => x"098106eb", -694 => x"38805170", -695 => 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x"38767a23", +2386 => x"84195880", +2387 => x"70565798", +2388 => x"56741870", +2389 => x"3370782b", +2390 => x"79078118", +2391 => x"f81a5a58", +2392 => x"59515484", +2393 => x"7524ea38", +2394 => x"76821b23", +2395 => x"88195880", +2396 => x"70565798", +2397 => x"56741870", +2398 => x"3370782b", +2399 => x"79078118", +2400 => x"f81a5a58", +2401 => x"59515484", +2402 => x"7524ea38", +2403 => x"76841b0c", +2404 => x"8c195880", +2405 => x"70565798", +2406 => x"56741870", +2407 => x"3370782b", +2408 => x"79078118", +2409 => x"f81a5a58", +2410 => x"59515484", +2411 => x"7524ea38", +2412 => x"76881b23", +2413 => x"90195880", +2414 => x"70565798", +2415 => x"56741870", +2416 => x"3370782b", +2417 => x"79078118", +2418 => x"f81a5a58", +2419 => x"59515484", +2420 => x"7524ea38", +2421 => x"768a1b23", +2422 => x"94195880", +2423 => x"70565798", +2424 => x"56741870", +2425 => x"3370782b", +2426 => x"79078118", +2427 => x"f81a5a58", +2428 => x"59515484", +2429 => x"7524ea38", +2430 => x"768c1b23", +2431 => x"98195880", +2432 => x"70565798", +2433 => x"56741870", +2434 => x"3370782b", +2435 => x"79078118", +2436 => x"f81a5a58", +2437 => x"59515484", +2438 => x"7524ea38", +2439 => x"768e1b23", +2440 => x"9c195880", +2441 => x"705657b8", +2442 => x"56741870", +2443 => x"3370782b", +2444 => x"79078118", +2445 => x"f81a5a58", +2446 => x"595a5488", +2447 => x"7524ea38", +2448 => x"76901b0c", +2449 => x"8b3d0d04", +2450 => x"e93d0d6a", +2451 => x"80dfdc08", +2452 => x"57577593", +2453 => x"3880c080", +2454 => x"0b84180c", +2455 => x"75ac180c", +2456 => x"75800c99", +2457 => x"3d0d0489", +2458 => x"3d70556a", +2459 => x"54558a52", +2460 => x"993dffbc", +2461 => x"0551ffbb", +2462 => x"c93f8008", +2463 => x"77537552", +2464 => x"56fd953f", +2465 => x"bc3f7780", +2466 => x"080c7580", +2467 => x"0c993d0d", +2468 => x"04fc3d0d", +2469 => x"815480df", +2470 => x"dc088838", +2471 => x"73800c86", +2472 => x"3d0d0476", +2473 => x"5397b952", +2474 => x"863dfc05", +2475 => x"51ffbb92", +2476 => x"3f800854", +2477 => x"8c3f7480", +2478 => x"080c7380", +2479 => x"0c863d0d", +2480 => x"0480cfec", +2481 => x"08800c04", +2482 => x"f73d0d7b", +2483 => x"80cfec08", +2484 => x"82c81108", +2485 => x"5a545a77", +2486 => x"802e80da", +2487 => x"38818818", +2488 => x"841908ff", +2489 => x"0581712b", +2490 => x"59555980", +2491 => x"742480ea", +2492 => x"38807424", +2493 => x"b5387382", +2494 => x"2b781188", +2495 => x"05565681", +2496 => x"80190877", +2497 => x"06537280", +2498 => x"2eb63878", +2499 => x"16700853", +2500 => x"53795174", +2501 => x"0853722d", +2502 => x"ff14fc17", +2503 => x"fc177981", +2504 => x"2c5a5757", +2505 => x"54738025", +2506 => x"d6387708", +2507 => x"5877ffad", +2508 => x"3880cfec", +2509 => x"0853bc13", +2510 => x"08a53879", +2511 => x"51f8e53f", +2512 => x"74085372", +2513 => x"2dff14fc", +2514 => x"17fc1779", +2515 => x"812c5a57", +2516 => x"57547380", +2517 => x"25ffa838", +2518 => x"d1398057", +2519 => x"ff933972", +2520 => x"51bc1308", +2521 => x"54732d79", +2522 => x"51f8b93f", +2523 => x"707080df", +2524 => x"b80bfc05", +2525 => x"70085252", +2526 => x"70ff2e91", +2527 => x"38702dfc", +2528 => x"12700852", +2529 => x"5270ff2e", +2530 => x"098106f1", +2531 => x"38505004", +2532 => x"04ffbaff", +2533 => x"3f040000", 2534 => x"00000040", 2535 => x"476f7420", 2536 => x"696e7465", -- cgit v1.1 From 6647b91cf267e7e155c95c6adbcfbc43f083356b Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 17 Jun 2008 22:09:13 +0000 Subject: * io.vhd: fix address comparsion and added numerous outputs during simulation to make things a bit easier * zpu_config.vhd: do not use hardcoded startSp, allows more easily tinkering w/RAM size --- zpu/hdl/zpu4/src/io.vhd | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index 9e65929..f71f51d 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -37,6 +37,7 @@ signal timer_we : std_logic; signal serving : std_logic; file l_file : TEXT open write_mode is log_file; +constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0'); begin @@ -54,42 +55,50 @@ begin process(areset, clk) begin + taddr := (others => '0'); + taddr(maxAddrBit downto minAddrBit) := addr; + if (areset = '1') then -- timer_we <= '0'; elsif (clk'event and clk = '1') then -- timer_we <= '0'; if writeEnable = '1' then - -- external interface (fixed address) - -- extend compare to avoid waring messages - if ("000" & addr)=x"2028003" then + -- external interface (fixed address) + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits)=x"80a000c" then + report "Write to UART[0]" & " :0x" & hstr(write); -- Write to UART -- report "" & character'image(conv_integer(memBint)) severity note; print(l_file, character'val(to_integer(unsigned(write)))); elsif addr(12)='1' then + report "Write to TIMER" & " :0x" & hstr(write); -- report "xxx" severity failure; -- timer_we <= '1'; else print(l_file, character'val(to_integer(unsigned(write)))); - -- report "Illegal IO write" severity warning; + report "Illegal IO write @" & "0x" & hstr(taddr) severity warning; end if; end if; read <= (others => '0'); if (readEnable = '1') then - -- extend compare to avoid waring messages - if ("000" & addr)=x"0001001" then - read <= (0=>'1', others => '0'); -- recieve empty + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits)=x"80a000c" then + report "Read UART[0]"; + read(8) <= '0'; -- output fifo not full + read(9) <= '1'; -- receiver not empty + elsif ("1" & addr & lowAddrBits)=x"80a0010" then + report "Read UART[1]"; + read(8) <= '1'; -- receiver not empty + read(7 downto 0) <= (others => '0'); elsif addr(12)='1' then + report "Read TIMER"; read(7 downto 0) <= timer_read; elsif addr(11)='1' then + report "Read ZPU Freq"; read(7 downto 0) <= ZPU_Frequency; - -- extend compare to avoid waring messages - elsif ("000" & addr)=x"2028003" then - read <= (others => '0'); else - read <= (others => '0'); - read(8) <= '1'; - -- report "Illegal IO read" severity warning; + report "Illegal IO read @" & "0x" & hstr(taddr) severity warning; end if; end if; end if; -- cgit v1.1 From 8c213415fe0ddc1f9eae0b96e023eb89f89d1c47 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 18 Jun 2008 17:04:44 +0000 Subject: I'm also attaching another patch which removes unisim/roc dependency (it was used just to pulse the areset) and fixes paths for building the ghdl examples out of the box. I guess this is the easiest way to get zpu running on linux with minimum effort. You should check if the areset change doesn't break modelsim. It feels much simpler this way and seems to work the same, i might be missing something. --- zpu/hdl/zpu4/src/io.vhd | 1 + 1 file changed, 1 insertion(+) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index f71f51d..e2576e2 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -54,6 +54,7 @@ begin timer_we <= writeEnable and addr(12); process(areset, clk) + variable taddr : std_logic_vector(maxAddrBit downto 0); begin taddr := (others => '0'); taddr(maxAddrBit downto minAddrBit) := addr; -- cgit v1.1 From 24d353cdac17eca4851271c824f421e8ab5697f3 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 18 Jun 2008 17:21:36 +0000 Subject: take 2 --- zpu/hdl/zpu4/src/io.vhd | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index e2576e2..a0e494a 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -38,6 +38,8 @@ signal serving : std_logic; file l_file : TEXT open write_mode is log_file; constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0'); +constant tx_full: std_logic := '0'; +constant rx_empty: std_logic := '1'; begin @@ -86,11 +88,11 @@ begin -- extend compare to avoid waring messages if ("1" & addr & lowAddrBits)=x"80a000c" then report "Read UART[0]"; - read(8) <= '0'; -- output fifo not full - read(9) <= '1'; -- receiver not empty + read(8) <= not tx_full; -- output fifo not full + read(9) <= not rx_empty; -- receiver not empty elsif ("1" & addr & lowAddrBits)=x"80a0010" then report "Read UART[1]"; - read(8) <= '1'; -- receiver not empty + read(8) <= not rx_empty; -- receiver not empty read(7 downto 0) <= (others => '0'); elsif addr(12)='1' then report "Read TIMER"; -- cgit v1.1 From 10995e1545e11556e84665ff013313f5160f6161 Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 7 Aug 2008 13:23:43 +0000 Subject: add missing defs. --- zpu/hdl/zpu4/core/zpu_config.vhd | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd index a13c0bf..ffc144b 100644 --- a/zpu/hdl/zpu4/core/zpu_config.vhd +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; package zpu_config is -- generate trace output or not. @@ -12,5 +13,10 @@ package zpu_config is constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) constant maxAddrBitIncIO : integer := 15; + constant maxAddrBitBRAM : integer := 14; + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := + conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); end zpu_config; -- cgit v1.1 From f9ddc2d50943be4bb9d4864cc277af99b03ade1f Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 8 Aug 2008 12:13:24 +0000 Subject: 2008-08-08 Salvador E. Tropea * zpu/hdl/zpu4/core/histogram.perl - generate opcode histogram from HDL simulation output --- zpu/hdl/zpu4/core/histogram.perl | 218 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 218 insertions(+) create mode 100644 zpu/hdl/zpu4/core/histogram.perl (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/histogram.perl b/zpu/hdl/zpu4/core/histogram.perl new file mode 100644 index 0000000..479ee0f --- /dev/null +++ b/zpu/hdl/zpu4/core/histogram.perl @@ -0,0 +1,218 @@ +#!/usr/bin/perl +############################################################################## +# +# Copyright (c) 2008 Salvador E. Tropea +# Copyright (c) 2008 Instituto Nacional de Tecnología Industrial +# +############################################################################## +# +# Target: Any +# Language: Perl +# Interpreter used: v5.6.1/v5.8.4 +# Text editor: SETEdit 0.5.5 +# +############################################################################## +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA +# 02111-1307, USA +# +############################################################################## +# +# Description: Takes a ZPU trace and does some raw stats about opcodes +# frequency and speed. +# +############################################################################## +# +# TODO +# +# A lot ... +# + + +# 0x40-0x460 +# div y mod son especiales +@used=(); +@clks=(); + +$line=1; +$startLine=1; +#$endLine=10000; +$endLine=-1; +$lastClk=0; +$lastOpcode=-1; +while (<>) + { + if ($_=~/^(\S+) (\S+) (\S+) (\S+) (\S+) (\S+) (\S+)/) + { + $clk=hex($7); + #print "$line\n"; + if ($line>=$startLine) + { + #print $_; + $addr=hex($1); + $opcode=hex($2); + $sp=hex($3); + $a=hex($4); + $b=hex($5); + if ($addr>=0x40 and $addr<0x460) + { + @used[$opcode+0x100]++; + @clks[$lastOpcodeEmu]+=$clk-$lastClkEmu unless lastOpcodeEmu==-1; + $lastOpcodeEmu=$opcode+0x100; + $lastClkEmu=$clk; + } + else + { + @used[$opcode]++; + @clks[$lastOpcode]+=$clk-$lastClk unless $lastOpcode==-1; + #printf "%d+=%d\n",$lastOpcode,$clk-$lastClk; + $lastOpcode=$opcode; + $lastClk=$clk; + $lastOpcodeEmu=-1; + $lastClkEmu=$clk; + } + } + else + { + $lastClk=$clk; + } + last if $line==$endLine; + $line++; + } + } +@used[$lastOpcode]--; + +$id=0; +# Cluster them +AddSimple('breakpoint',0); +# 1=shiftleft, invalid +AddSimple('pushsp',2); +# 3=pushint, invalid +AddSimple('poppc',4); +AddSimple('add',5); +AddSimple('and',6); +AddSimple('or',7); +AddSimple('load',8); +AddSimple('not',9); +AddSimple('flip',10); +AddSimple('nop',11); +AddSimple('store',12); +AddSimple('popsp',13); +# 14=compare, invalid +# 15=popint, invalid +AddSimpleRange('addsp',16,31); +# 32-63 emulate +AddSimpleRange('storesp',64,95); +AddSimpleRange('loadsp',96,127); +AddSimpleRange('im',128,255); + +# 32 is the reset entry point +# 33 is the interrupt entry point +AddEmulate('loadh',34); +AddEmulate('storeh',35); +AddEmulate('lessthan',36); +AddEmulate('lessthanorequal',37); +AddEmulate('ulessthan',38); +AddEmulate('ulessthanorequal',39); +AddEmulate('swap',40); # unimplemented +AddEmulate('mult',41); +AddEmulate('lshiftright',42); +AddEmulate('ashiftleft',43); +AddEmulate('ashiftright',44); +AddEmulate('call',45); +AddEmulate('eq',46); +AddEmulate('neq',47); +AddEmulate('neg',48); +AddEmulate('sub',49); +AddEmulate('xor',50); +AddEmulate('loadb',51); +AddEmulate('storeb',52); +AddEmulate('div',53); +AddEmulate('mod',54); +AddEmulate('eqbranch',55); +AddEmulate('neqbranch',56); +AddEmulate('poppcrel',57); +AddEmulate('config',58); +AddEmulate('pushpc',59); +AddEmulate('syscall_emulate',60); # unimplemented +AddEmulate('pushspadd',61); +AddEmulate('halfmult',62); # unimplemented +AddEmulate('callpcrel',63); + +$maxID=$id; +print "Total clocks: $lastClk\n"; +print "Unsorted:\n\n"; +for ($i=0; $i<$maxID; $i++) + { + $used=@used_noemu[$i]; + $clkm=0; + $clkm=@clks_noemu[$i]/$used if $used; + printf "%-20s %8d %6.2f\n",$names[$i],$used,$clkm; + $by_times{$i}=$used; + $by_clks{$i}=@clks_noemu[$i]; + } +print "Sorted by consumed clocks:\n\n"; +foreach $key (sort { $by_clks{$b} <=> $by_clks{$a} } keys %by_clks) + { + printf "%5.2f %-20s %8d\n",$by_clks{$key}/$lastClk*100,$names[$key],$by_clks{$key}; + } + + +sub AddSimple +{ + my ($name, $opcode)=@_; + + $names[$id]=$name; + @used_noemu[$id]=@used[$opcode]; + @used_emu[$id]=@used[$opcode+0x100]; + @used_both[$id]=@used[$opcode]+@used[$opcode+0x100]; + @clks_noemu[$id]=@clks[$opcode]; + @clks_emu[$id]=@clks[$opcode+0x100]; + @clks_both[$id]=@clks[$opcode]+@clks[$opcode+0x100]; + $id++; +} + +sub AddEmulate +{ + my ($name, $opcode)=@_; + + $names[$id]=$name; + @used_noemu[$id]=@used[$opcode]; + @used_emu[$id]=@used[$opcode+0x100]; + @used_both[$id]=@used[$opcode]; + @clks_noemu[$id]=@clks[$opcode]; + @clks_emu[$id]=@clks[$opcode+0x100]; + @clks_both[$id]=@clks[$opcode]; + $id++; +} + +sub AddSimpleRange +{ + my ($name, $opStart, $opLast)=@_; + my $i; + + $names[$id]=$name; + for ($i=$opStart; $i<=$opLast; $i++) + { + @used_noemu[$id]+=@used[$i]; + @used_emu[$id]+=@used[$i+0x100]; + @used_both[$id]+=@used[$i]+@used[$i+0x100]; + @clks_noemu[$id]+=@clks[$i]; + @clks_emu[$id]+=@clks[$i+0x100]; + @clks_both[$id]+=@clks[$i]+@clks[$i+0x100]; + } + $id++; +} + + -- cgit v1.1 From eab67ae1b5d86c9c294ef057631d04a448e1727f Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 15 Aug 2008 10:53:01 +0000 Subject: marked unused instruction opcodes as OpCode_NAx --- zpu/hdl/zpu4/core/zpupkg.vhd | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd index f3800b0..e8d54a3 100644 --- a/zpu/hdl/zpu4/core/zpupkg.vhd +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -114,9 +114,9 @@ package zpupkg is constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; - constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001"; + constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001"; constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; - constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011"; + constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011"; constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; @@ -130,8 +130,8 @@ package zpupkg is constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; - constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110"; - constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111"; + constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_NA : std_logic_vector(3 downto 0) := "1111"; constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); -- cgit v1.1 From 5d329cc628e4174874382547397149e414ec0ad8 Mon Sep 17 00:00:00 2001 From: oharboe Date: Fri, 15 Aug 2008 20:11:36 +0000 Subject: added FreeBSD license. Finally. --- zpu/hdl/zpu4/core/zpu_config.vhd | 35 +++++++++++++++++++++++++++++++++++ zpu/hdl/zpu4/core/zpu_core.vhd | 36 +++++++++++++++++++++++++++++++++--- zpu/hdl/zpu4/core/zpu_core_small.vhd | 35 +++++++++++++++++++++++++++++++++-- zpu/hdl/zpu4/core/zpupkg.vhd | 34 ++++++++++++++++++++++++++++++++++ zpu/hdl/zpu4/src/trace.vhd | 34 ++++++++++++++++++++++++++++++++++ zpu/hdl/zpu4/src/txt_util.vhd | 34 ++++++++++++++++++++++++++++++++++ 6 files changed, 203 insertions(+), 5 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd index ffc144b..4fecf01 100644 --- a/zpu/hdl/zpu4/core/zpu_config.vhd +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -1,3 +1,38 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + + library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd index 37fa2d1..012fe1b 100644 --- a/zpu/hdl/zpu4/core/zpu_core.vhd +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -1,6 +1,36 @@ - --- Company: ZPU4 generic memory interface CPU --- Engineer: Øyvind Harboe +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. library IEEE; use IEEE.STD_LOGIC_1164.ALL; diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 03526bd..69bbe1a 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -1,5 +1,36 @@ --- Company: ZPU3 --- Engineer: Øyvind Harboe +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. library IEEE; use IEEE.STD_LOGIC_1164.ALL; diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd index e8d54a3..59d26e5 100644 --- a/zpu/hdl/zpu4/core/zpupkg.vhd +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd index e687aaf..2413970 100644 --- a/zpu/hdl/zpu4/src/trace.vhd +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd index d3bf01a..3d5297a 100644 --- a/zpu/hdl/zpu4/src/txt_util.vhd +++ b/zpu/hdl/zpu4/src/txt_util.vhd @@ -1,3 +1,37 @@ +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; use std.textio.all; -- cgit v1.1 From 1de92a77fd154c79d210df2e957ade2a0965243f Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 26 Aug 2008 19:09:30 +0000 Subject: fixed comments a bit. --- zpu/hdl/zpu4/core/zpu_core_small.vhd | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 69bbe1a..9946fb3 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -186,8 +186,7 @@ begin - -- not used in this design - + -- mem_writeMask is not used in this design, tie it to 1 mem_writeMask <= (others => '1'); -- cgit v1.1 From 76c3ea4351ea2f30ad948249e16d0253949f4f4e Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 26 Aug 2008 19:13:29 +0000 Subject: some more comments about dual port ram --- zpu/hdl/zpu4/core/zpu_core_small.vhd | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 9946fb3..5587189 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -195,6 +195,27 @@ begin memAWrite_stdlogic <= std_logic_vector(memAWrite); memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); memBWrite_stdlogic <= std_logic_vector(memBWrite); + + + -- dualport_ram must be defined by the application. + -- + -- How this can be implemented is highly dependent on the FPGA + -- and synthesis technology used. + -- + -- sometimes it can be instantiated as in the + -- zpu/example/helloworld.vhd, using inference, + -- but oftentimes it must be instantiated directly + -- portmapping to part specific FPGA resources + -- + -- + -- DANGER!!!!!! If inference fails, then synthesis will try + -- to implement the memory using basic logic resources. This + -- will almost certainly cause the compiler to get "stuck" + -- since synthesising such a huge number of basic logic resources + -- will take more or less forever. + -- + -- So: if your compiler gets "stuck" then inference is not + -- the way to go. memory: dualport_ram port map ( clk => clk, memAWriteEnable => memAWriteEnable, -- cgit v1.1 From 0cc528bc3fc6f11e7997a2f68bf4badb59b3117f Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 26 Aug 2008 19:56:25 +0000 Subject: commenting wip --- zpu/hdl/zpu4/core/zpu_core_small.vhd | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 5587189..f9484bb 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -43,7 +43,10 @@ use work.zpupkg.all; entity zpu_core is Port ( clk : in std_logic; + -- asynchronous reset signal areset : in std_logic; + -- this particular implementation of the ZPU does not + -- have a clocked enable signal enable : in std_logic; in_mem_busy : in std_logic; mem_read : in std_logic_vector(wordSize-1 downto 0); @@ -51,8 +54,16 @@ entity zpu_core is out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); out_mem_writeEnable : out std_logic; out_mem_readEnable : out std_logic; + -- this implementation of the ZPU *always* reads and writes entire + -- 32 bit words, so mem_writeMask is tied to (others => '1'). mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically interrupt : in std_logic; + -- Signal that the break instruction is executed, normally only used + -- in simulation to stop simulation break : out std_logic); end zpu_core; @@ -76,13 +87,13 @@ signal memBRead : unsigned(wordSize-1 downto 0); signal pc : unsigned(maxAddrBit downto 0); signal sp : unsigned(maxAddrBit downto minAddrBit); +-- this signal is set upon executing an IM instruction +-- the subsequence IM instruction will then behave differently. +-- all other instructions will clear the idim_flag. +-- this yields highly compact immediate instructions. signal idim_flag : std_logic; ---signal storeToStack : std_logic; ---signal fetchNextInstruction : std_logic; ---signal extraCycle : std_logic; signal busy : std_logic; ---signal fetching : std_logic; signal begin_inst : std_logic; @@ -169,6 +180,15 @@ signal inInterrupt : std_logic; begin + + -- generate a trace file. + -- + -- This is only used in simulation to see what instructions are + -- executed. + -- + -- a quick & dirty regression test is then to commit trace files + -- to CVS and compare the latest trace file against the last known + -- good trace file traceFileGenerate: if Generate_Trace generate trace_file: trace port map ( @@ -236,6 +256,8 @@ begin + -- move out calculation of the opcode to a seperate process + -- to make things a bit easier to read decodeControl: process(memBRead, pc,tOpcode_sel) variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); -- cgit v1.1 From 709f5ff71d918f10835d89ed6f349aee9dea340b Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 12 Nov 2008 20:50:06 +0000 Subject: =?UTF-8?q?2008-11-12=20=C1lvaro=20Lopes=20=20?= =?UTF-8?q?=09*=20zpu/hdl/zpu4/core/zpu=5Fcore.vhd:=20Basic=20interrupt=20?= =?UTF-8?q?implementation=20=09for=20zpu4=20core.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- zpu/hdl/zpu4/core/zpu_core.vhd | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd index 012fe1b..69da686 100644 --- a/zpu/hdl/zpu4/core/zpu_core.vhd +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -1,6 +1,7 @@ -- ZPU -- -- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com -- -- The FreeBSD license -- @@ -145,7 +146,8 @@ State_Mult5, State_Mult4, State_BinaryOpResult2, State_BinaryOpResult, -State_Idle +State_Idle, +State_Interrupt ); @@ -171,6 +173,8 @@ signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal mem_delayReadEnable : std_logic; +signal inInterrupt: std_logic; + signal decodeWord : std_logic_vector(wordSize-1 downto 0); @@ -244,6 +248,7 @@ begin pc <= (others => '0'); idim_flag <= '0'; begin_inst <= '0'; + inInterrupt <= '0'; mem_writeEnable <= '0'; mem_readEnable <= '0'; multA <= (others => '0'); @@ -288,6 +293,10 @@ begin trace_topOfStackB <= std_logic_vector(stackB); begin_inst <= '0'; + if (interrupt='0') then + -- Interrupt ended, we can serve ISR again + inInterrupt <= '0'; + end if; case state is when State_Idle => @@ -319,6 +328,27 @@ begin if in_mem_busy='0' then decodeWord <= mem_read; state <= State_Decode2; + -- Do not recurse into ISR while interrupt line is active + if interrupt='1' and inInterrupt='0' and idim_flag='0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + pc <= to_unsigned(32, maxAddrBitIncIO+1); + state <= State_Interrupt; + end if; + end if; + when State_Interrupt => + if in_mem_busy='0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + report "ZPU jumped to interrupt!" severity note; end if; when State_Decode2 => -- decode 4 instructions in parallel -- cgit v1.1 From c3a6c5f8c614919982ef31c9e8e324525ce105b1 Mon Sep 17 00:00:00 2001 From: Alvaro Date: Fri, 22 Oct 2010 18:18:33 +0200 Subject: zpu_core_small: load memAAddr is not being initialized during IO read operations (LOAD). This might cause spurious writes to invalid addresses, and invalid values to be loaded onto the stack. This patch explicitly sets memAAddr to correct value (sp). --- zpu/hdl/zpu4/core/zpu_core_small.vhd | 1 + 1 file changed, 1 insertion(+) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index f9484bb..681fb09 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -494,6 +494,7 @@ begin null; end case; when State_ReadIO => + memAAddr <= sp; if (in_mem_busy = '0') then state <= State_Fetch; memAWriteEnable <= '1'; -- cgit v1.1 From b103d820a57859fc4aad48f50029e12cc1db7611 Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Tue, 1 Mar 2011 17:36:01 +0100 Subject: beautify Signed-off-by: Bert Lange --- zpu/hdl/zpu4/core/zpu_config.vhd | 32 +- zpu/hdl/zpu4/core/zpu_core.vhd | 1820 ++++++++++++++++++---------------- zpu/hdl/zpu4/core/zpu_core_small.vhd | 1065 ++++++++++---------- zpu/hdl/zpu4/core/zpupkg.vhd | 338 ++++--- 4 files changed, 1679 insertions(+), 1576 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd index 4fecf01..112dd01 100644 --- a/zpu/hdl/zpu4/core/zpu_config.vhd +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -39,19 +39,21 @@ use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; package zpu_config is - -- generate trace output or not. - constant Generate_Trace : boolean := false; - constant wordPower : integer := 5; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := 'X'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; - -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) - constant maxAddrBitIncIO : integer := 15; - constant maxAddrBitBRAM : integer := 14; - - -- start byte address of stack. - -- point to top of RAM - 2*words - constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := - conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); + + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := 'X'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 15; + constant maxAddrBitBRAM : integer := 14; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := + conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); + end zpu_config; diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd index 69da686..ff9449f 100644 --- a/zpu/hdl/zpu4/core/zpu_core.vhd +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -33,8 +33,8 @@ -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +library ieee; +use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; @@ -58,899 +58,957 @@ use work.zpupkg.all; -- write request -- break - set to '1' when CPU hits break instruction -- interrupt - set to '1' until interrupts are cleared by CPU. - + entity zpu_core is - Port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); + port ( + clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask : out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic + ); end zpu_core; architecture behave of zpu_core is -type InsnType is -( -State_AddTop, -State_Dup, -State_DupStackB, -State_Pop, -State_Popdown, -State_Add, -State_Or, -State_And, -State_Store, -State_AddSP, -State_Shift, -State_Nop, -State_Im, -State_LoadSP, -State_StoreSP, -State_Emulate, -State_Load, -State_PushPC, -State_PushSP, -State_PopPC, -State_PopPCRel, -State_Not, -State_Flip, -State_PopSP, -State_Neqbranch, -State_Eq, -State_Loadb, -State_Mult, -State_Lessthan, -State_Lessthanorequal, -State_Ulessthanorequal, -State_Ulessthan, -State_Pushspadd, -State_Call, -State_Callpcrel, -State_Sub, -State_Break, -State_Storeb, -State_InsnFetch -); - -type StateType is -( -State_Load2, -State_Popped, -State_LoadSP2, -State_LoadSP3, -State_AddSP2, -State_Fetch, -State_Execute, -State_Decode, -State_Decode2, -State_Resync, - -State_StoreSP2, -State_Resync2, -State_Resync3, -State_Loadb2, -State_Storeb2, -State_Mult2, -State_Mult3, -State_Mult5, -State_Mult4, -State_BinaryOpResult2, -State_BinaryOpResult, -State_Idle, -State_Interrupt -); - - -signal pc : unsigned(maxAddrBitIncIO downto 0); -signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); -signal stackA : unsigned(wordSize-1 downto 0); -signal binaryOpResult : unsigned(wordSize-1 downto 0); -signal binaryOpResult2 : unsigned(wordSize-1 downto 0); -signal multResult2 : unsigned(wordSize-1 downto 0); -signal multResult3 : unsigned(wordSize-1 downto 0); -signal multResult : unsigned(wordSize-1 downto 0); -signal multA : unsigned(wordSize-1 downto 0); -signal multB : unsigned(wordSize-1 downto 0); -signal stackB : unsigned(wordSize-1 downto 0); -signal idim_flag : std_logic; -signal busy : std_logic; -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal mem_delayReadEnable : std_logic; - -signal inInterrupt: std_logic; - -signal decodeWord : std_logic_vector(wordSize-1 downto 0); - - -signal state : StateType; -signal insn : InsnType; -type InsnArray is array(0 to wordBytes-1) of InsnType; -signal decodedOpcode : InsnArray; - -type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); - -signal opcode : OpcodeArray; - - - - -signal begin_inst : std_logic; -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + type InsnType is ( + State_AddTop, + State_Dup, + State_DupStackB, + State_Pop, + State_Popdown, + State_Add, + State_Or, + State_And, + State_Store, + State_AddSP, + State_Shift, + State_Nop, + State_Im, + State_LoadSP, + State_StoreSP, + State_Emulate, + State_Load, + State_PushPC, + State_PushSP, + State_PopPC, + State_PopPCRel, + State_Not, + State_Flip, + State_PopSP, + State_Neqbranch, + State_Eq, + State_Loadb, + State_Mult, + State_Lessthan, + State_Lessthanorequal, + State_Ulessthanorequal, + State_Ulessthan, + State_Pushspadd, + State_Call, + State_Callpcrel, + State_Sub, + State_Break, + State_Storeb, + State_InsnFetch + ); + + type StateType is ( + State_Load2, + State_Popped, + State_LoadSP2, + State_LoadSP3, + State_AddSP2, + State_Fetch, + State_Execute, + State_Decode, + State_Decode2, + State_Resync, + + State_StoreSP2, + State_Resync2, + State_Resync3, + State_Loadb2, + State_Storeb2, + State_Mult2, + State_Mult3, + State_Mult5, + State_Mult4, + State_BinaryOpResult2, + State_BinaryOpResult, + State_Idle, + State_Interrupt + ); + + + signal pc : unsigned(maxAddrBitIncIO downto 0); + signal sp : unsigned(maxAddrBitIncIO downto minAddrBit); + signal incSp : unsigned(maxAddrBitIncIO downto minAddrBit); + signal incIncSp : unsigned(maxAddrBitIncIO downto minAddrBit); + signal decSp : unsigned(maxAddrBitIncIO downto minAddrBit); + signal stackA : unsigned(wordSize-1 downto 0); + signal binaryOpResult : unsigned(wordSize-1 downto 0); + signal binaryOpResult2 : unsigned(wordSize-1 downto 0); + signal multResult2 : unsigned(wordSize-1 downto 0); + signal multResult3 : unsigned(wordSize-1 downto 0); + signal multResult : unsigned(wordSize-1 downto 0); + signal multA : unsigned(wordSize-1 downto 0); + signal multB : unsigned(wordSize-1 downto 0); + signal stackB : unsigned(wordSize-1 downto 0); + signal idim_flag : std_logic; + signal busy : std_logic; + signal mem_writeEnable : std_logic; + signal mem_readEnable : std_logic; + signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); + signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); + signal mem_delayReadEnable : std_logic; + -- + signal inInterrupt : std_logic; + -- + signal decodeWord : std_logic_vector(wordSize-1 downto 0); + -- + -- + signal state : StateType; + signal insn : InsnType; + type InsnArray is array(0 to wordBytes-1) of InsnType; + signal decodedOpcode : InsnArray; + -- + type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); + -- + signal opcode : OpcodeArray; + + + + + signal begin_inst : std_logic; + signal trace_opcode : std_logic_vector(7 downto 0); + signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); + signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); + signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); + signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); -- state machine. begin - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - -- the memory subsystem will tell us one cycle later whether or - -- not it is busy - out_mem_writeEnable <= mem_writeEnable; - out_mem_readEnable <= mem_readEnable; - out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; - out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); - - incSp <= sp + 1; - incIncSp <= sp + 2; - decSp <= sp - 1; - - - opcodeControl: - process(clk, areset) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - variable spOffset : unsigned(4 downto 0); - variable tSpOffset : unsigned(4 downto 0); - variable nextPC : unsigned(maxAddrBitIncIO downto 0); - variable tNextState : InsnType; - variable tDecodedOpcode : InsnArray; - variable tMultResult : unsigned(wordSize*2-1 downto 0); - begin - if areset = '1' then - state <= State_Idle; - break <= '0'; - sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); - - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - inInterrupt <= '0'; - mem_writeEnable <= '0'; - mem_readEnable <= '0'; - multA <= (others => '0'); - multB <= (others => '0'); - mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then - -- we must multiply unconditionally to get pipelined multiplication - tMultResult := multA * multB; - multResult3 <= multResult2; - multResult2 <= multResult; - multResult <= tMultResult(wordSize-1 downto 0); - - - binaryOpResult2 <= binaryOpResult; -- pipeline a bit. - - - multA <= (others => DontCareValue); - multB <= (others => DontCareValue); - - - mem_addr <= (others => DontCareValue); - mem_readEnable <='0'; - mem_writeEnable <='0'; - mem_write <= (others => DontCareValue); - - if (mem_writeEnable = '1') and (mem_readEnable = '1') then - report "read/write collision" severity failure; - end if; - - - - - spOffset(4):=not opcode(to_integer(pc(byteBits-1 downto 0)))(4); - spOffset(3 downto 0):=unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); - nextPC := pc + 1; - - -- prepare trace snapshot - trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); - trace_pc <= std_logic_vector(pc); - trace_sp <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(stackA); - trace_topOfStackB <= std_logic_vector(stackB); - begin_inst <= '0'; - - if (interrupt='0') then - -- Interrupt ended, we can serve ISR again - inInterrupt <= '0'; - end if; - - case state is - when State_Idle => - if enable='1' then - state <= State_Resync; - end if; - -- Initial state of ZPU, fetch top of stack + first instruction - when State_Resync => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(sp); - mem_readEnable <= '1'; - state <= State_Resync2; - end if; - when State_Resync2 => - if in_mem_busy='0' then - stackA <= unsigned(mem_read); - mem_addr <= std_logic_vector(incSp); - mem_readEnable <= '1'; - state <= State_Resync3; - end if; - when State_Resync3 => - if in_mem_busy='0' then - stackB <= unsigned(mem_read); - mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Decode => - if in_mem_busy='0' then - decodeWord <= mem_read; - state <= State_Decode2; - -- Do not recurse into ISR while interrupt line is active - if interrupt='1' and inInterrupt='0' and idim_flag='0' then - -- We got an interrupt, execute interrupt instead of next instruction - inInterrupt <= '1'; - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc; - stackB <= stackA; - pc <= to_unsigned(32, maxAddrBitIncIO+1); - state <= State_Interrupt; - end if; - end if; - when State_Interrupt => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - state <= State_Decode; - report "ZPU jumped to interrupt!" severity note; - end if; - when State_Decode2 => - -- decode 4 instructions in parallel - for i in 0 to wordBytes-1 loop - tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); - - tSpOffset(4):=not tOpcode(4); - tSpOffset(3 downto 0):=unsigned(tOpcode(3 downto 0)); - - opcode(i) <= tOpcode; - if (tOpcode(7 downto 7)=OpCode_Im) then - tNextState:=State_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - if tSpOffset = 0 then - tNextState := State_Pop; - elsif tSpOffset=1 then - tNextState := State_PopDown; - else - tNextState :=State_StoreSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - if tSpOffset = 0 then - tNextState :=State_Dup; - elsif tSpOffset = 1 then - tNextState :=State_DupStackB; - else - tNextState :=State_LoadSP; - end if; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - tNextState :=State_Emulate; - if tOpcode(5 downto 0)=OpCode_Neqbranch then - tNextState :=State_Neqbranch; - elsif tOpcode(5 downto 0)=OpCode_Eq then - tNextState :=State_Eq; - elsif tOpcode(5 downto 0)=OpCode_Lessthan then - tNextState :=State_Lessthan; - elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then - --tNextState :=State_Lessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Ulessthan then - tNextState :=State_Ulessthan; - elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then - --tNextState :=State_Ulessthanorequal; - elsif tOpcode(5 downto 0)=OpCode_Loadb then - tNextState :=State_Loadb; - elsif tOpcode(5 downto 0)=OpCode_Mult then - tNextState :=State_Mult; - elsif tOpcode(5 downto 0)=OpCode_Storeb then - tNextState :=State_Storeb; - elsif tOpcode(5 downto 0)=OpCode_Pushspadd then - tNextState :=State_Pushspadd; - elsif tOpcode(5 downto 0)=OpCode_Callpcrel then - tNextState :=State_Callpcrel; - elsif tOpcode(5 downto 0)=OpCode_Call then - --tNextState :=State_Call; - elsif tOpcode(5 downto 0)=OpCode_Sub then - tNextState :=State_Sub; - elsif tOpcode(5 downto 0)=OpCode_PopPCRel then - --tNextState :=State_PopPCRel; - end if; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - if tSpOffset = 0 then - tNextState := State_Shift; - elsif tSpOffset = 1 then - tNextState := State_AddTop; - else - tNextState :=State_AddSP; - end if; - else - case tOpcode(3 downto 0) is - when OpCode_Nop => - tNextState :=State_Nop; - when OpCode_PushSP => - tNextState :=State_PushSP; - when OpCode_PopPC => - tNextState :=State_PopPC; - when OpCode_Add => - tNextState :=State_Add; - when OpCode_Or => - tNextState :=State_Or; - when OpCode_And => - tNextState :=State_And; - when OpCode_Load => - tNextState :=State_Load; - when OpCode_Not => - tNextState :=State_Not; - when OpCode_Flip => - tNextState :=State_Flip; - when OpCode_Store => - tNextState :=State_Store; - when OpCode_PopSP => - tNextState :=State_PopSP; - when others => - tNextState := State_Break; - - end case; - end if; - tDecodedOpcode(i) := tNextState; - - end loop; - - insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); - - -- once we wrap, we need to fetch - tDecodedOpcode(0) := State_InsnFetch; - - decodedOpcode <= tDecodedOpcode; - state <= State_Execute; - - - - -- Each instruction must: - -- - -- 1. set idim_flag - -- 2. increase pc if applicable - -- 3. set next state if appliable - -- 4. do it's operation - - when State_Execute => - insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); - - case insn is - when State_InsnFetch => - state <= State_Fetch; - when State_Im => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '1'; - pc <= pc + 1; - - if idim_flag='1' then - stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); - stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); - else - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - stackB <= stackA; - sp <= decSp; - for i in wordSize-1 downto 7 loop - stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); - end loop; - stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); - end if; - end if; - when State_StoreSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_StoreSP2; - - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(sp+spOffset); - mem_write <= std_logic_vector(stackA); - stackA <= stackB; - sp <= incSp; - end if; - - - when State_LoadSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_LoadSP2; - - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - end if; - when State_Emulate => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - sp <= decSp; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - stackB <= stackA; - - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); - state <= State_Fetch; - end if; - when State_Callpcrel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - - pc <= pc + stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_Call => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= (others => DontCareValue); - stackA(maxAddrBitIncIO downto 0) <= pc + 1; - pc <= stackA(maxAddrBitIncIO downto 0); - state <= State_Fetch; - end if; - when State_AddSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_AddSP2; - - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(sp+spOffset); - end if; - when State_PushSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= sp; - stackB <= stackA; - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - end if; - when State_PopPC => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0); - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - state <= State_Resync; - end if; - when State_PopPCRel => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - sp <= incSp; - - mem_writeEnable <= '1'; - mem_addr <= std_logic_vector(incSp); - mem_write <= std_logic_vector(stackB); - state <= State_Resync; - end if; - when State_Add => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA + stackB; - - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_Sub => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - binaryOpResult <= stackB - stackA; - state <= State_BinaryOpResult; - end if; - when State_Pop => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= std_logic_vector(incIncSp); - mem_readEnable <= '1'; - sp <= incSp; - stackA <= stackB; - state <= State_Popped; - end if; - when State_PopDown => - if in_mem_busy='0' then - -- PopDown leaves top of stack unchanged - begin_inst <= '1'; - idim_flag <= '0'; - mem_addr <= std_logic_vector(incIncSp); - mem_readEnable <= '1'; - sp <= incSp; - state <= State_Popped; - end if; - when State_Or => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - stackA <= stackA or stackB; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_And => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - stackA <= stackA and stackB; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_Eq => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Ulessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (stackA<=stackB) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Lessthan => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA) - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - - binaryOpResult <= (others => '0'); - if (signed(stackA)<=signed(stackB)) then - binaryOpResult(0) <= '1'; - end if; - state <= State_BinaryOpResult; - end if; - when State_Load => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Load2; - - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - end if; - - when State_Dup => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackB <= stackA; - mem_write <= std_logic_vector(stackB); - mem_addr <= std_logic_vector(incSp); - mem_writeEnable <= '1'; - end if; - when State_DupStackB => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - sp <= decSp; - stackA <= stackB; - stackB <= stackA; - mem_write <= std_logic_vector(stackB); - mem_addr <= std_logic_vector(incSp); - mem_writeEnable <= '1'; - end if; - when State_Store => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_write <= std_logic_vector(stackB); - mem_writeEnable <= '1'; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_PopSP => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - mem_write <= std_logic_vector(stackB); - mem_addr <= std_logic_vector(incSp); - mem_writeEnable <= '1'; - sp <= stackA(maxAddrBitIncIO downto minAddrBit); - state <= State_Resync; - end if; - when State_Nop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - when State_Not => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= not stackA; - when State_Flip => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - for i in 0 to wordSize-1 loop - stackA(i) <= stackA(wordSize-1-i); - end loop; - when State_AddTop => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= stackA + stackB; - when State_Shift => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); - stackA(0) <= '0'; - when State_Pushspadd => - begin_inst <= '1'; - idim_flag <= '0'; - pc <= pc + 1; - - stackA <= (others => '0'); - stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; - when State_Neqbranch => - -- branches are almost always taken as they form loops - begin_inst <= '1'; - idim_flag <= '0'; - sp <= incIncSp; - if (stackB/=0) then - pc <= stackA(maxAddrBitIncIO downto 0) + pc; - else - pc <= pc + 1; - end if; - -- need to fetch stack again. - state <= State_Resync; - when State_Mult => - begin_inst <= '1'; - idim_flag <= '0'; - - multA <= stackA; - multB <= stackB; - state <= State_Mult2; - when State_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - - when State_Loadb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Loadb2; - - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - end if; - when State_Storeb => - if in_mem_busy='0' then - begin_inst <= '1'; - idim_flag <= '0'; - state <= State_Storeb2; - - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - end if; - - when others => - sp <= (others => DontCareValue); - report "Illegal instruction" severity failure; - break <= '1'; - end case; - - - when State_StoreSP2 => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(incSp); - mem_readEnable <= '1'; - state <= State_Popped; - end if; - when State_LoadSP2 => - if in_mem_busy='0' then - state <= State_LoadSP3; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(sp+spOffset+1); - end if; - when State_LoadSP3 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackB <= stackA; - stackA <= unsigned(mem_read); - end if; - when State_AddSP2 => - if in_mem_busy='0' then - pc <= pc + 1; - state <= State_Execute; - stackA <= stackA + unsigned(mem_read); - end if; - when State_Load2 => - if in_mem_busy='0' then - stackA <= unsigned(mem_read); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Loadb2 => - if in_mem_busy='0' then - stackA <= (others => '0'); - stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); - pc <= pc + 1; - state <= State_Execute; - end if; - when State_Storeb2 => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); - mem_write <= mem_read; - mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); - mem_writeEnable <= '1'; - pc <= pc + 1; - sp <= incIncSp; - state <= State_Resync; - end if; - when State_Fetch => - if in_mem_busy='0' then - mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); - mem_readEnable <= '1'; - state <= State_Decode; - end if; - when State_Mult2 => - state <= State_Mult3; - when State_Mult3 => - state <= State_Mult4; - when State_Mult4 => - state <= State_Mult5; - when State_Mult5 => - if in_mem_busy='0' then - stackA <= multResult3; - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - state <= State_Popped; - end if; - when State_BinaryOpResult => - state <= State_BinaryOpResult2; - when State_BinaryOpResult2 => - mem_readEnable <= '1'; - mem_addr <= std_logic_vector(incIncSp); - sp <= incSp; - stackA <= binaryOpResult2; - state <= State_Popped; - when State_Popped => - if in_mem_busy='0' then - pc <= pc + 1; - stackB <= unsigned(mem_read); - state <= State_Execute; - end if; - when others => - sp <= (others => DontCareValue); - report "Illegal state" severity failure; - break <= '1'; - end case; - end if; - end process; + traceFileGenerate : + if Generate_Trace generate + trace_file : trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + out_mem_writeEnable <= mem_writeEnable; + out_mem_readEnable <= mem_readEnable; + out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; + out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); + + incSp <= sp + 1; + incIncSp <= sp + 2; + decSp <= sp - 1; + + + opcodeControl : process(clk, areset) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + variable spOffset : unsigned(4 downto 0); + variable tSpOffset : unsigned(4 downto 0); + variable nextPC : unsigned(maxAddrBitIncIO downto 0); + variable tNextState : InsnType; + variable tDecodedOpcode : InsnArray; + variable tMultResult : unsigned(wordSize*2-1 downto 0); + begin + if areset = '1' then + state <= State_Idle; + break <= '0'; + sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); + + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + inInterrupt <= '0'; + mem_writeEnable <= '0'; + mem_readEnable <= '0'; + multA <= (others => '0'); + multB <= (others => '0'); + mem_writeMask <= (others => '1'); + elsif (clk'event and clk = '1') then + -- we must multiply unconditionally to get pipelined multiplication + tMultResult := multA * multB; + multResult3 <= multResult2; + multResult2 <= multResult; + multResult <= tMultResult(wordSize-1 downto 0); + + + binaryOpResult2 <= binaryOpResult; -- pipeline a bit. + + + multA <= (others => DontCareValue); + multB <= (others => DontCareValue); + + + mem_addr <= (others => DontCareValue); + mem_readEnable <= '0'; + mem_writeEnable <= '0'; + mem_write <= (others => DontCareValue); + + if (mem_writeEnable = '1') and (mem_readEnable = '1') then + report "read/write collision" severity failure; + end if; + + + + + spOffset(4) := not opcode(to_integer(pc(byteBits-1 downto 0)))(4); + spOffset(3 downto 0) := unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(3 downto 0)); + nextPC := pc + 1; + + -- prepare trace snapshot + trace_opcode <= opcode(to_integer(pc(byteBits-1 downto 0))); + trace_pc <= std_logic_vector(pc); + trace_sp <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(stackA); + trace_topOfStackB <= std_logic_vector(stackB); + begin_inst <= '0'; + + if (interrupt = '0') then + -- Interrupt ended, we can serve ISR again + inInterrupt <= '0'; + end if; + + case state is + + when State_Idle => + if enable = '1' then + state <= State_Resync; + end if; + -- Initial state of ZPU, fetch top of stack + first instruction + + when State_Resync => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(sp); + mem_readEnable <= '1'; + state <= State_Resync2; + end if; + + when State_Resync2 => + if in_mem_busy = '0' then + stackA <= unsigned(mem_read); + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Resync3; + end if; + + when State_Resync3 => + if in_mem_busy = '0' then + stackB <= unsigned(mem_read); + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + + when State_Decode => + if in_mem_busy = '0' then + decodeWord <= mem_read; + state <= State_Decode2; + -- Do not recurse into ISR while interrupt line is active + if interrupt = '1' and inInterrupt = '0' and idim_flag = '0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc; + stackB <= stackA; + pc <= to_unsigned(32, maxAddrBitIncIO+1); + state <= State_Interrupt; + end if; -- interrupt + end if; -- in_mem_busy + + when State_Interrupt => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + report "ZPU jumped to interrupt!" severity note; + end if; + + when State_Decode2 => + -- decode 4 instructions in parallel + for i in 0 to wordBytes-1 loop + tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); + + tSpOffset(4) := not tOpcode(4); + tSpOffset(3 downto 0) := unsigned(tOpcode(3 downto 0)); + + opcode(i) <= tOpcode; + if (tOpcode(7 downto 7) = OpCode_Im) then + tNextState := State_Im; + elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then + if tSpOffset = 0 then + tNextState := State_Pop; + elsif tSpOffset = 1 then + tNextState := State_PopDown; + else + tNextState := State_StoreSP; + end if; + elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then + if tSpOffset = 0 then + tNextState := State_Dup; + elsif tSpOffset = 1 then + tNextState := State_DupStackB; + else + tNextState := State_LoadSP; + end if; + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then + tNextState := State_Emulate; + if tOpcode(5 downto 0) = OpCode_Neqbranch then + tNextState := State_Neqbranch; + elsif tOpcode(5 downto 0) = OpCode_Eq then + tNextState := State_Eq; + elsif tOpcode(5 downto 0) = OpCode_Lessthan then + tNextState := State_Lessthan; + elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then + --tNextState :=State_Lessthanorequal; + elsif tOpcode(5 downto 0) = OpCode_Ulessthan then + tNextState := State_Ulessthan; + elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then + --tNextState :=State_Ulessthanorequal; + elsif tOpcode(5 downto 0) = OpCode_Loadb then + tNextState := State_Loadb; + elsif tOpcode(5 downto 0) = OpCode_Mult then + tNextState := State_Mult; + elsif tOpcode(5 downto 0) = OpCode_Storeb then + tNextState := State_Storeb; + elsif tOpcode(5 downto 0) = OpCode_Pushspadd then + tNextState := State_Pushspadd; + elsif tOpcode(5 downto 0) = OpCode_Callpcrel then + tNextState := State_Callpcrel; + elsif tOpcode(5 downto 0) = OpCode_Call then + --tNextState :=State_Call; + elsif tOpcode(5 downto 0) = OpCode_Sub then + tNextState := State_Sub; + elsif tOpcode(5 downto 0) = OpCode_PopPCRel then + --tNextState :=State_PopPCRel; + end if; + elsif (tOpcode(7 downto 4) = OpCode_AddSP) then + if tSpOffset = 0 then + tNextState := State_Shift; + elsif tSpOffset = 1 then + tNextState := State_AddTop; + else + tNextState := State_AddSP; + end if; + else + case tOpcode(3 downto 0) is + when OpCode_Nop => + tNextState := State_Nop; + when OpCode_PushSP => + tNextState := State_PushSP; + when OpCode_PopPC => + tNextState := State_PopPC; + when OpCode_Add => + tNextState := State_Add; + when OpCode_Or => + tNextState := State_Or; + when OpCode_And => + tNextState := State_And; + when OpCode_Load => + tNextState := State_Load; + when OpCode_Not => + tNextState := State_Not; + when OpCode_Flip => + tNextState := State_Flip; + when OpCode_Store => + tNextState := State_Store; + when OpCode_PopSP => + tNextState := State_PopSP; + when others => + tNextState := State_Break; + + end case; -- tOpcode(3 downto 0) + end if; -- tOpcode + tDecodedOpcode(i) := tNextState; + + end loop; -- 0 to wordBytes-1 + + insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); + + -- once we wrap, we need to fetch + tDecodedOpcode(0) := State_InsnFetch; + + decodedOpcode <= tDecodedOpcode; + state <= State_Execute; + + + + -- Each instruction must: + -- + -- 1. set idim_flag + -- 2. increase pc if applicable + -- 3. set next state if appliable + -- 4. do it's operation + + when State_Execute => + insn <= decodedOpcode(to_integer(nextPC(byteBits-1 downto 0))); + + case insn is + + when State_InsnFetch => + state <= State_Fetch; + + when State_Im => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '1'; + pc <= pc + 1; + + if idim_flag = '1' then + stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + else + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackB <= stackA; + sp <= decSp; + for i in wordSize-1 downto 7 loop + stackA(i) <= opcode(to_integer(pc(byteBits-1 downto 0)))(6); + end loop; + stackA(6 downto 0) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(6 downto 0)); + end if; -- idim_flag + end if; -- in_mem_busy + + when State_StoreSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_StoreSP2; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + mem_write <= std_logic_vector(stackA); + stackA <= stackB; + sp <= incSp; + end if; + + + when State_LoadSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_LoadSP2; + + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + + when State_Emulate => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + sp <= decSp; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + stackB <= stackA; + + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(to_integer(pc(byteBits-1 downto 0)))(4 downto 0)); + state <= State_Fetch; + end if; -- in_mem_busy + + when State_Callpcrel => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + + pc <= pc + stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + + when State_Call => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= (others => DontCareValue); + stackA(maxAddrBitIncIO downto 0) <= pc + 1; + pc <= stackA(maxAddrBitIncIO downto 0); + state <= State_Fetch; + end if; + + when State_AddSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_AddSP2; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset); + end if; + + when State_PushSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= sp; + stackB <= stackA; + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + end if; + + when State_PopPC => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0); + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + + when State_PopPCRel => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + sp <= incSp; + + mem_writeEnable <= '1'; + mem_addr <= std_logic_vector(incSp); + mem_write <= std_logic_vector(stackB); + state <= State_Resync; + end if; + + when State_Add => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA + stackB; + + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + + when State_Sub => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + binaryOpResult <= stackB - stackA; + state <= State_BinaryOpResult; + end if; + + when State_Pop => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + stackA <= stackB; + state <= State_Popped; + end if; + + when State_PopDown => + if in_mem_busy = '0' then + -- PopDown leaves top of stack unchanged + begin_inst <= '1'; + idim_flag <= '0'; + mem_addr <= std_logic_vector(incIncSp); + mem_readEnable <= '1'; + sp <= incSp; + state <= State_Popped; + end if; + + when State_Or => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + stackA <= stackA or stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + + when State_And => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + stackA <= stackA and stackB; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + + when State_Eq => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA = stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when State_Ulessthan => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA < stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when State_Ulessthanorequal => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (stackA <= stackB) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when State_Lessthan => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) < signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when State_Lessthanorequal => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + + binaryOpResult <= (others => '0'); + if (signed(stackA) <= signed(stackB)) then + binaryOpResult(0) <= '1'; + end if; + state <= State_BinaryOpResult; + end if; + + when State_Load => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Load2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when State_Dup => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + + when State_DupStackB => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + sp <= decSp; + stackA <= stackB; + stackB <= stackA; + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + end if; + + when State_Store => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= std_logic_vector(stackB); + mem_writeEnable <= '1'; + sp <= incIncSp; + state <= State_Resync; + end if; + + when State_PopSP => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + mem_write <= std_logic_vector(stackB); + mem_addr <= std_logic_vector(incSp); + mem_writeEnable <= '1'; + sp <= stackA(maxAddrBitIncIO downto minAddrBit); + state <= State_Resync; + end if; + + when State_Nop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + when State_Not => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= not stackA; + + when State_Flip => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + for i in 0 to wordSize-1 loop + stackA(i) <= stackA(wordSize-1-i); + end loop; + + when State_AddTop => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= stackA + stackB; + + when State_Shift => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); + stackA(0) <= '0'; + + when State_Pushspadd => + begin_inst <= '1'; + idim_flag <= '0'; + pc <= pc + 1; + + stackA <= (others => '0'); + stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; + + when State_Neqbranch => + -- branches are almost always taken as they form loops + begin_inst <= '1'; + idim_flag <= '0'; + sp <= incIncSp; + if (stackB /= 0) then + pc <= stackA(maxAddrBitIncIO downto 0) + pc; + else + pc <= pc + 1; + end if; + -- need to fetch stack again. + state <= State_Resync; + + when State_Mult => + begin_inst <= '1'; + idim_flag <= '0'; + + multA <= stackA; + multB <= stackB; + state <= State_Mult2; + + when State_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when State_Loadb => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Loadb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when State_Storeb => + if in_mem_busy = '0' then + begin_inst <= '1'; + idim_flag <= '0'; + state <= State_Storeb2; + + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal instruction" severity failure; + break <= '1'; + + end case; -- insn/State_Execute + + + when State_StoreSP2 => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(incSp); + mem_readEnable <= '1'; + state <= State_Popped; + end if; + + when State_LoadSP2 => + if in_mem_busy = '0' then + state <= State_LoadSP3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(sp+spOffset+1); + end if; + + when State_LoadSP3 => + if in_mem_busy = '0' then + pc <= pc + 1; + state <= State_Execute; + stackB <= stackA; + stackA <= unsigned(mem_read); + end if; + + when State_AddSP2 => + if in_mem_busy = '0' then + pc <= pc + 1; + state <= State_Execute; + stackA <= stackA + unsigned(mem_read); + end if; + + when State_Load2 => + if in_mem_busy = '0' then + stackA <= unsigned(mem_read); + pc <= pc + 1; + state <= State_Execute; + end if; + + when State_Loadb2 => + if in_mem_busy = '0' then + stackA <= (others => '0'); + stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8)); + pc <= pc + 1; + state <= State_Execute; + end if; + + when State_Storeb2 => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(stackA(maxAddrBitIncIO downto minAddrBit)); + mem_write <= mem_read; + mem_write(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8) <= std_logic_vector(stackB(7 downto 0)); + mem_writeEnable <= '1'; + pc <= pc + 1; + sp <= incIncSp; + state <= State_Resync; + end if; + + when State_Fetch => + if in_mem_busy = '0' then + mem_addr <= std_logic_vector(pc(maxAddrBitIncIO downto minAddrBit)); + mem_readEnable <= '1'; + state <= State_Decode; + end if; + + when State_Mult2 => + state <= State_Mult3; + + when State_Mult3 => + state <= State_Mult4; + + when State_Mult4 => + state <= State_Mult5; + + when State_Mult5 => + if in_mem_busy = '0' then + stackA <= multResult3; + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + state <= State_Popped; + end if; + + when State_BinaryOpResult => + state <= State_BinaryOpResult2; + + when State_BinaryOpResult2 => + mem_readEnable <= '1'; + mem_addr <= std_logic_vector(incIncSp); + sp <= incSp; + stackA <= binaryOpResult2; + state <= State_Popped; + + when State_Popped => + if in_mem_busy = '0' then + pc <= pc + 1; + stackB <= unsigned(mem_read); + state <= State_Execute; + end if; + + when others => + sp <= (others => DontCareValue); + report "Illegal state" severity failure; + break <= '1'; + + end case; -- state + end if; -- clk'event + end process; diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 681fb09..1df9546 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -32,8 +32,8 @@ -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; +library ieee; +use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; @@ -42,531 +42,560 @@ use work.zpupkg.all; entity zpu_core is - Port ( clk : in std_logic; - -- asynchronous reset signal - areset : in std_logic; - -- this particular implementation of the ZPU does not - -- have a clocked enable signal - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - -- this implementation of the ZPU *always* reads and writes entire - -- 32 bit words, so mem_writeMask is tied to (others => '1'). - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - -- Set to one to jump to interrupt vector - -- The ZPU will communicate with the hardware that caused the - -- interrupt via memory mapped IO or the interrupt flag can - -- be cleared automatically - interrupt : in std_logic; - -- Signal that the break instruction is executed, normally only used - -- in simulation to stop simulation - break : out std_logic); + port ( + clk : in std_logic; + -- asynchronous reset signal + areset : in std_logic; + -- this particular implementation of the ZPU does not + -- have a clocked enable signal + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + -- this implementation of the ZPU *always* reads and writes entire + -- 32 bit words, so mem_writeMask is tied to (others => '1'). + mem_writeMask : out std_logic_vector(wordBytes-1 downto 0); + -- Set to one to jump to interrupt vector + -- The ZPU will communicate with the hardware that caused the + -- interrupt via memory mapped IO or the interrupt flag can + -- be cleared automatically + interrupt : in std_logic; + -- Signal that the break instruction is executed, normally only used + -- in simulation to stop simulation + break : out std_logic + ); end zpu_core; -architecture behave of zpu_core is -signal readIO : std_logic; - - -signal memAWriteEnable : std_logic; -signal memAAddr : unsigned(maxAddrBit downto minAddrBit); -signal memAWrite : unsigned(wordSize-1 downto 0); -signal memARead : unsigned(wordSize-1 downto 0); -signal memBWriteEnable : std_logic; -signal memBAddr : unsigned(maxAddrBit downto minAddrBit); -signal memBWrite : unsigned(wordSize-1 downto 0); -signal memBRead : unsigned(wordSize-1 downto 0); - - - -signal pc : unsigned(maxAddrBit downto 0); -signal sp : unsigned(maxAddrBit downto minAddrBit); - --- this signal is set upon executing an IM instruction --- the subsequence IM instruction will then behave differently. --- all other instructions will clear the idim_flag. --- this yields highly compact immediate instructions. -signal idim_flag : std_logic; - -signal busy : std_logic; - -signal begin_inst : std_logic; - - - -signal trace_opcode : std_logic_vector(7 downto 0); -signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); -signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); -signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); -signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. -type State_Type is -( -State_Fetch, -State_WriteIODone, -State_Execute, -State_StoreToStack, -State_Add, -State_Or, -State_And, -State_Store, -State_ReadIO, -State_WriteIO, -State_Load, -State_FetchNext, -State_AddSP, -State_ReadIODone, -State_Decode, -State_Resync, -State_Interrupt - -); - -type DecodedOpcodeType is -( -Decoded_Nop, -Decoded_Im, -Decoded_ImShift, -Decoded_LoadSP, -Decoded_StoreSP , -Decoded_AddSP, -Decoded_Emulate, -Decoded_Break, -Decoded_PushSP, -Decoded_PopPC, -Decoded_Add, -Decoded_Or, -Decoded_And, -Decoded_Load, -Decoded_Not, -Decoded_Flip, -Decoded_Store, -Decoded_PopSP, -Decoded_Interrupt -); - - - -signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); -signal opcode : std_logic_vector(OpCode_Size-1 downto 0); - -signal decodedOpcode : DecodedOpcodeType; -signal sampledDecodedOpcode : DecodedOpcodeType; - - -signal state : State_Type; - -subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; -signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); -signal memARead_stdlogic : std_logic_vector(memARead'range); -signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); -signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); -signal memBRead_stdlogic : std_logic_vector(memBRead'range); - -subtype index is integer range 0 to 3; - -signal tOpcode_sel : index; - - -signal inInterrupt : std_logic; +architecture behave of zpu_core is + + signal memAWriteEnable : std_logic; + signal memAAddr : unsigned(maxAddrBit downto minAddrBit); + signal memAWrite : unsigned(wordSize-1 downto 0); + signal memARead : unsigned(wordSize-1 downto 0); + signal memBWriteEnable : std_logic; + signal memBAddr : unsigned(maxAddrBit downto minAddrBit); + signal memBWrite : unsigned(wordSize-1 downto 0); + signal memBRead : unsigned(wordSize-1 downto 0); + + + + signal pc : unsigned(maxAddrBit downto 0); + signal sp : unsigned(maxAddrBit downto minAddrBit); + + -- this signal is set upon executing an IM instruction + -- the subsequence IM instruction will then behave differently. + -- all other instructions will clear the idim_flag. + -- this yields highly compact immediate instructions. + signal idim_flag : std_logic; + -- + signal busy : std_logic; + -- + signal begin_inst : std_logic; + + + signal trace_opcode : std_logic_vector(7 downto 0); + signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); + signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); + signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); + signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); + + -- state machine. + type State_Type is ( + State_Fetch, + State_WriteIODone, + State_Execute, + State_StoreToStack, + State_Add, + State_Or, + State_And, + State_Store, + State_ReadIO, + State_WriteIO, + State_Load, + State_FetchNext, + State_AddSP, + State_ReadIODone, + State_Decode, + State_Resync, + State_Interrupt + ); + + type DecodedOpcodeType is ( + Decoded_Nop, + Decoded_Im, + Decoded_ImShift, + Decoded_LoadSP, + Decoded_StoreSP , + Decoded_AddSP, + Decoded_Emulate, + Decoded_Break, + Decoded_PushSP, + Decoded_PopPC, + Decoded_Add, + Decoded_Or, + Decoded_And, + Decoded_Load, + Decoded_Not, + Decoded_Flip, + Decoded_Store, + Decoded_PopSP, + Decoded_Interrupt + ); + + + + signal sampledOpcode : std_logic_vector(OpCode_Size-1 downto 0); + signal opcode : std_logic_vector(OpCode_Size-1 downto 0); + -- + signal decodedOpcode : DecodedOpcodeType; + signal sampledDecodedOpcode : DecodedOpcodeType; + + + signal state : State_Type; + -- + subtype AddrBitBRAM_range is natural range maxAddrBitBRAM downto minAddrBit; + signal memAAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); + signal memAWrite_stdlogic : std_logic_vector(memAWrite'range); + signal memARead_stdlogic : std_logic_vector(memARead'range); + signal memBAddr_stdlogic : std_logic_vector(AddrBitBRAM_range); + signal memBWrite_stdlogic : std_logic_vector(memBWrite'range); + signal memBRead_stdlogic : std_logic_vector(memBRead'range); + -- + subtype index is integer range 0 to 3; + -- + signal tOpcode_sel : index; + -- + signal inInterrupt : std_logic; begin - -- generate a trace file. - -- - -- This is only used in simulation to see what instructions are - -- executed. - -- - -- a quick & dirty regression test is then to commit trace files - -- to CVS and compare the latest trace file against the last known - -- good trace file - traceFileGenerate: - if Generate_Trace generate - trace_file: trace port map ( - clk => clk, - begin_inst => begin_inst, - pc => trace_pc, - opcode => trace_opcode, - sp => trace_sp, - memA => trace_topOfStack, - memB => trace_topOfStackB, - busy => busy, - intsp => (others => 'U') - ); - end generate; - - - - -- mem_writeMask is not used in this design, tie it to 1 - mem_writeMask <= (others => '1'); - - - - memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); - memAWrite_stdlogic <= std_logic_vector(memAWrite); - memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); - memBWrite_stdlogic <= std_logic_vector(memBWrite); - - - -- dualport_ram must be defined by the application. - -- - -- How this can be implemented is highly dependent on the FPGA - -- and synthesis technology used. - -- - -- sometimes it can be instantiated as in the - -- zpu/example/helloworld.vhd, using inference, - -- but oftentimes it must be instantiated directly - -- portmapping to part specific FPGA resources - -- - -- - -- DANGER!!!!!! If inference fails, then synthesis will try - -- to implement the memory using basic logic resources. This - -- will almost certainly cause the compiler to get "stuck" - -- since synthesising such a huge number of basic logic resources - -- will take more or less forever. - -- - -- So: if your compiler gets "stuck" then inference is not - -- the way to go. - memory: dualport_ram port map ( - clk => clk, - memAWriteEnable => memAWriteEnable, - memAAddr => memAAddr_stdlogic, - memAWrite => memAWrite_stdlogic, - memARead => memARead_stdlogic, - memBWriteEnable => memBWriteEnable, - memBAddr => memBAddr_stdlogic, - memBWrite => memBWrite_stdlogic, - memBRead => memBRead_stdlogic - ); - memARead <= unsigned(memARead_stdlogic); - memBRead <= unsigned(memBRead_stdlogic); - - - - tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); - - - - -- move out calculation of the opcode to a seperate process - -- to make things a bit easier to read - decodeControl: - process(memBRead, pc,tOpcode_sel) - variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); - begin - - -- simplify opcode selection a bit so it passes more synthesizers - case (tOpcode_sel) is - - when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); - - when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); - - when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); - - when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); - - when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); - end case; - - sampledOpcode <= tOpcode; - - if (tOpcode(7 downto 7)=OpCode_Im) then - sampledDecodedOpcode<=Decoded_Im; - elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then - sampledDecodedOpcode<=Decoded_StoreSP; - elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then - sampledDecodedOpcode<=Decoded_LoadSP; - elsif (tOpcode(7 downto 5)=OpCode_Emulate) then - sampledDecodedOpcode<=Decoded_Emulate; - elsif (tOpcode(7 downto 4)=OpCode_AddSP) then - sampledDecodedOpcode<=Decoded_AddSP; - else - case tOpcode(3 downto 0) is - when OpCode_Break => - sampledDecodedOpcode<=Decoded_Break; - when OpCode_PushSP => - sampledDecodedOpcode<=Decoded_PushSP; - when OpCode_PopPC => - sampledDecodedOpcode<=Decoded_PopPC; - when OpCode_Add => - sampledDecodedOpcode<=Decoded_Add; - when OpCode_Or => - sampledDecodedOpcode<=Decoded_Or; - when OpCode_And => - sampledDecodedOpcode<=Decoded_And; - when OpCode_Load => - sampledDecodedOpcode<=Decoded_Load; - when OpCode_Not => - sampledDecodedOpcode<=Decoded_Not; - when OpCode_Flip => - sampledDecodedOpcode<=Decoded_Flip; - when OpCode_Store => - sampledDecodedOpcode<=Decoded_Store; - when OpCode_PopSP => - sampledDecodedOpcode<=Decoded_PopSP; - when others => - sampledDecodedOpcode<=Decoded_Nop; - end case; - end if; - end process; - - - opcodeControl: - process(clk, areset) - variable spOffset : unsigned(4 downto 0); - begin - if areset = '1' then - state <= State_Resync; - break <= '0'; - sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); - pc <= (others => '0'); - idim_flag <= '0'; - begin_inst <= '0'; - memAAddr <= (others => '0'); - memBAddr <= (others => '0'); - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - memAWrite <= (others => '0'); - memBWrite <= (others => '0'); - inInterrupt <= '0'; - elsif (clk'event and clk = '1') then - memAWriteEnable <= '0'; - memBWriteEnable <= '0'; - -- This saves ca. 100 LUT's, by explicitly declaring that the - -- memAWrite can be left at whatever value if memAWriteEnable is - -- not set. - memAWrite <= (others => DontCareValue); - memBWrite <= (others => DontCareValue); --- out_mem_addr <= (others => DontCareValue); --- mem_write <= (others => DontCareValue); - spOffset := (others => DontCareValue); - memAAddr <= (others => DontCareValue); - memBAddr <= (others => DontCareValue); - - out_mem_writeEnable <= '0'; - out_mem_readEnable <= '0'; - begin_inst <= '0'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - - decodedOpcode <= sampledDecodedOpcode; - opcode <= sampledOpcode; - if interrupt='0' then - inInterrupt <= '0'; -- no longer in an interrupt - end if; - - case state is - when State_Execute => - state <= State_Fetch; - -- at this point: - -- memBRead contains opcode word - -- memARead contains top of stack - pc <= pc + 1; - - -- trace - begin_inst <= '1'; - trace_pc <= (others => '0'); - trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); - trace_opcode <= opcode; - trace_sp <= (others => '0'); - trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); - trace_topOfStack <= std_logic_vector(memARead); - trace_topOfStackB <= std_logic_vector(memBRead); - - -- during the next cycle we'll be reading the next opcode - spOffset(4):=not opcode(4); - spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); - - idim_flag <= '0'; - case decodedOpcode is - when Decoded_Interrupt => - sp <= sp - 1; - memAAddr <= sp - 1; - memAWriteEnable <= '1'; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc; - pc <= to_unsigned(32, maxAddrBit+1); -- interrupt address - report "ZPU jumped to interrupt!" severity note; - when Decoded_Im => - idim_flag <= '1'; - memAWriteEnable <= '1'; - if (idim_flag='0') then - sp <= sp - 1; - memAAddr <= sp-1; - for i in wordSize-1 downto 7 loop - memAWrite(i) <= opcode(6); - end loop; - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - else - memAAddr <= sp; - memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); - memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); - end if; - when Decoded_StoreSP => - memBWriteEnable <= '1'; - memBAddr <= sp+spOffset; - memBWrite <= memARead; - sp <= sp + 1; - state <= State_Resync; - when Decoded_LoadSP => - sp <= sp - 1; - memAAddr <= sp+spOffset; - when Decoded_Emulate => - sp <= sp - 1; - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto 0) <= pc + 1; - -- The emulate address is: - -- 98 7654 3210 - -- 0000 00aa aaa0 0000 - pc <= (others => '0'); - pc(9 downto 5) <= unsigned(opcode(4 downto 0)); - when Decoded_AddSP => - memAAddr <= sp; - memBAddr <= sp+spOffset; - state <= State_AddSP; - when Decoded_Break => - report "Break instruction encountered" severity failure; - break <= '1'; - when Decoded_PushSP => - memAWriteEnable <= '1'; - memAAddr <= sp - 1; - sp <= sp - 1; - memAWrite <= (others => DontCareValue); - memAWrite(maxAddrBit downto minAddrBit) <= sp; - when Decoded_PopPC => - pc <= memARead(maxAddrBit downto 0); - sp <= sp + 1; - state <= State_Resync; - when Decoded_Add => - sp <= sp + 1; - state <= State_Add; - when Decoded_Or => - sp <= sp + 1; - state <= State_Or; - when Decoded_And => - sp <= sp + 1; - state <= State_And; - when Decoded_Load => - if (memARead(ioBit)='1') then - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - out_mem_readEnable <= '1'; - state <= State_ReadIO; - else - memAAddr <= memARead(maxAddrBit downto minAddrBit); - end if; - when Decoded_Not => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - memAWrite <= not memARead; - when Decoded_Flip => - memAAddr <= sp(maxAddrBit downto minAddrBit); - memAWriteEnable <= '1'; - for i in 0 to wordSize-1 loop - memAWrite(i) <= memARead(wordSize-1-i); - end loop; - when Decoded_Store => - memBAddr <= sp + 1; - sp <= sp + 1; - if (memARead(ioBit)='1') then - state <= State_WriteIO; - else - state <= State_Store; - end if; - when Decoded_PopSP => - sp <= memARead(maxAddrBit downto minAddrBit); - state <= State_Resync; - when Decoded_Nop => - memAAddr <= sp; - when others => - null; - end case; - when State_ReadIO => - memAAddr <= sp; - if (in_mem_busy = '0') then - state <= State_Fetch; - memAWriteEnable <= '1'; - memAWrite <= unsigned(mem_read); - end if; - when State_WriteIO => - sp <= sp + 1; - out_mem_writeEnable <= '1'; - out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); - mem_write <= std_logic_vector(memBRead); - state <= State_WriteIODone; - when State_WriteIODone => - if (in_mem_busy = '0') then - state <= State_Resync; - end if; - when State_Fetch => - -- We need to resync. During the *next* cycle - -- we'll fetch the opcode @ pc and thus it will - -- be available for State_Execute the cycle after - -- next - memBAddr <= pc(maxAddrBit downto minAddrBit); - state <= State_FetchNext; - when State_FetchNext => - -- at this point memARead contains the value that is either - -- from the top of stack or should be copied to the top of the stack - memAWriteEnable <= '1'; - memAWrite <= memARead; - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Decode; - when State_Decode => - if interrupt='1' and inInterrupt='0' and idim_flag='0' then - -- We got an interrupt, execute interrupt instead of next instruction - inInterrupt <= '1'; - decodedOpcode <= Decoded_Interrupt; - end if; - -- during the State_Execute cycle we'll be fetching SP+1 - memAAddr <= sp; - memBAddr <= sp + 1; - state <= State_Execute; - when State_Store => - sp <= sp + 1; - memAWriteEnable <= '1'; - memAAddr <= memARead(maxAddrBit downto minAddrBit); - memAWrite <= memBRead; - state <= State_Resync; - when State_AddSP => - state <= State_Add; - when State_Add => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead + memBRead; - state <= State_Fetch; - when State_Or => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead or memBRead; - state <= State_Fetch; - when State_Resync => - memAAddr <= sp; - state <= State_Fetch; - when State_And => - memAAddr <= sp; - memAWriteEnable <= '1'; - memAWrite <= memARead and memBRead; - state <= State_Fetch; - when others => - null; - end case; - - end if; - end process; + -- generate a trace file. + -- + -- This is only used in simulation to see what instructions are + -- executed. + -- + -- a quick & dirty regression test is then to commit trace files + -- to CVS and compare the latest trace file against the last known + -- good trace file + traceFileGenerate : if Generate_Trace generate + trace_file : trace port map ( + clk => clk, + begin_inst => begin_inst, + pc => trace_pc, + opcode => trace_opcode, + sp => trace_sp, + memA => trace_topOfStack, + memB => trace_topOfStackB, + busy => busy, + intsp => (others => 'U') + ); + end generate; + + + -- mem_writeMask is not used in this design, tie it to 1 + mem_writeMask <= (others => '1'); + + + + memAAddr_stdlogic <= std_logic_vector(memAAddr(AddrBitBRAM_range)); + memAWrite_stdlogic <= std_logic_vector(memAWrite); + memBAddr_stdlogic <= std_logic_vector(memBAddr(AddrBitBRAM_range)); + memBWrite_stdlogic <= std_logic_vector(memBWrite); + + + -- dualport_ram must be defined by the application. + -- + -- How this can be implemented is highly dependent on the FPGA + -- and synthesis technology used. + -- + -- sometimes it can be instantiated as in the + -- zpu/example/helloworld.vhd, using inference, + -- but oftentimes it must be instantiated directly + -- portmapping to part specific FPGA resources + -- + -- + -- DANGER!!!!!! If inference fails, then synthesis will try + -- to implement the memory using basic logic resources. This + -- will almost certainly cause the compiler to get "stuck" + -- since synthesising such a huge number of basic logic resources + -- will take more or less forever. + -- + -- So: if your compiler gets "stuck" then inference is not + -- the way to go. + memory : dualport_ram port map ( + clk => clk, + memAWriteEnable => memAWriteEnable, + memAAddr => memAAddr_stdlogic, + memAWrite => memAWrite_stdlogic, + memARead => memARead_stdlogic, + memBWriteEnable => memBWriteEnable, + memBAddr => memBAddr_stdlogic, + memBWrite => memBWrite_stdlogic, + memBRead => memBRead_stdlogic + ); + memARead <= unsigned(memARead_stdlogic); + memBRead <= unsigned(memBRead_stdlogic); + + + + tOpcode_sel <= to_integer(pc(minAddrBit-1 downto 0)); + + + + -- move out calculation of the opcode to a seperate process + -- to make things a bit easier to read + decodeControl : process(memBRead, pc, tOpcode_sel) + variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); + begin + + -- simplify opcode selection a bit so it passes more synthesizers + case (tOpcode_sel) is + + when 0 => tOpcode := std_logic_vector(memBRead(31 downto 24)); + + when 1 => tOpcode := std_logic_vector(memBRead(23 downto 16)); + + when 2 => tOpcode := std_logic_vector(memBRead(15 downto 8)); + + when 3 => tOpcode := std_logic_vector(memBRead(7 downto 0)); + + when others => tOpcode := std_logic_vector(memBRead(7 downto 0)); + end case; + + sampledOpcode <= tOpcode; + + if (tOpcode(7 downto 7) = OpCode_Im) then + sampledDecodedOpcode <= Decoded_Im; + elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then + sampledDecodedOpcode <= Decoded_StoreSP; + elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then + sampledDecodedOpcode <= Decoded_LoadSP; + elsif (tOpcode(7 downto 5) = OpCode_Emulate) then + sampledDecodedOpcode <= Decoded_Emulate; + elsif (tOpcode(7 downto 4) = OpCode_AddSP) then + sampledDecodedOpcode <= Decoded_AddSP; + else + case tOpcode(3 downto 0) is + when OpCode_Break => + sampledDecodedOpcode <= Decoded_Break; + when OpCode_PushSP => + sampledDecodedOpcode <= Decoded_PushSP; + when OpCode_PopPC => + sampledDecodedOpcode <= Decoded_PopPC; + when OpCode_Add => + sampledDecodedOpcode <= Decoded_Add; + when OpCode_Or => + sampledDecodedOpcode <= Decoded_Or; + when OpCode_And => + sampledDecodedOpcode <= Decoded_And; + when OpCode_Load => + sampledDecodedOpcode <= Decoded_Load; + when OpCode_Not => + sampledDecodedOpcode <= Decoded_Not; + when OpCode_Flip => + sampledDecodedOpcode <= Decoded_Flip; + when OpCode_Store => + sampledDecodedOpcode <= Decoded_Store; + when OpCode_PopSP => + sampledDecodedOpcode <= Decoded_PopSP; + when others => + sampledDecodedOpcode <= Decoded_Nop; + end case; -- tOpcode(3 downto 0) + end if; tOpcode + end process; + + + opcodeControl: process(clk, areset) + variable spOffset : unsigned(4 downto 0); + begin + + if areset = '1' then + state <= State_Resync; + break <= '0'; + sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); + pc <= (others => '0'); + idim_flag <= '0'; + begin_inst <= '0'; + memAAddr <= (others => '0'); + memBAddr <= (others => '0'); + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + memAWrite <= (others => '0'); + memBWrite <= (others => '0'); + inInterrupt <= '0'; + + elsif (clk'event and clk = '1') then + memAWriteEnable <= '0'; + memBWriteEnable <= '0'; + -- This saves ca. 100 LUT's, by explicitly declaring that the + -- memAWrite can be left at whatever value if memAWriteEnable is + -- not set. + memAWrite <= (others => DontCareValue); + memBWrite <= (others => DontCareValue); +-- out_mem_addr <= (others => DontCareValue); +-- mem_write <= (others => DontCareValue); + spOffset := (others => DontCareValue); + memAAddr <= (others => DontCareValue); + memBAddr <= (others => DontCareValue); + + out_mem_writeEnable <= '0'; + out_mem_readEnable <= '0'; + begin_inst <= '0'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + + decodedOpcode <= sampledDecodedOpcode; + opcode <= sampledOpcode; + if interrupt = '0' then + inInterrupt <= '0'; -- no longer in an interrupt + end if; + + case state is + + when State_Execute => + state <= State_Fetch; + -- at this point: + -- memBRead contains opcode word + -- memARead contains top of stack + pc <= pc + 1; + + -- trace + begin_inst <= '1'; + trace_pc <= (others => '0'); + trace_pc(maxAddrBit downto 0) <= std_logic_vector(pc); + trace_opcode <= opcode; + trace_sp <= (others => '0'); + trace_sp(maxAddrBit downto minAddrBit) <= std_logic_vector(sp); + trace_topOfStack <= std_logic_vector(memARead); + trace_topOfStackB <= std_logic_vector(memBRead); + + -- during the next cycle we'll be reading the next opcode + spOffset(4) := not opcode(4); + spOffset(3 downto 0) := unsigned(opcode(3 downto 0)); + + idim_flag <= '0'; + + case decodedOpcode is + + when Decoded_Interrupt => + sp <= sp - 1; + memAAddr <= sp - 1; + memAWriteEnable <= '1'; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc; + pc <= to_unsigned(32, maxAddrBit+1); -- interrupt address + report "ZPU jumped to interrupt!" severity note; + + when Decoded_Im => + idim_flag <= '1'; + memAWriteEnable <= '1'; + if (idim_flag = '0') then + sp <= sp - 1; + memAAddr <= sp-1; + for i in wordSize-1 downto 7 loop + memAWrite(i) <= opcode(6); + end loop; + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + else + memAAddr <= sp; + memAWrite(wordSize-1 downto 7) <= memARead(wordSize-8 downto 0); + memAWrite(6 downto 0) <= unsigned(opcode(6 downto 0)); + end if; -- idim_flag + + when Decoded_StoreSP => + memBWriteEnable <= '1'; + memBAddr <= sp+spOffset; + memBWrite <= memARead; + sp <= sp + 1; + state <= State_Resync; + + when Decoded_LoadSP => + sp <= sp - 1; + memAAddr <= sp+spOffset; + + when Decoded_Emulate => + sp <= sp - 1; + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto 0) <= pc + 1; + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc <= (others => '0'); + pc(9 downto 5) <= unsigned(opcode(4 downto 0)); + + when Decoded_AddSP => + memAAddr <= sp; + memBAddr <= sp+spOffset; + state <= State_AddSP; + + when Decoded_Break => + report "Break instruction encountered" severity failure; + break <= '1'; + + when Decoded_PushSP => + memAWriteEnable <= '1'; + memAAddr <= sp - 1; + sp <= sp - 1; + memAWrite <= (others => DontCareValue); + memAWrite(maxAddrBit downto minAddrBit) <= sp; + + when Decoded_PopPC => + pc <= memARead(maxAddrBit downto 0); + sp <= sp + 1; + state <= State_Resync; + + when Decoded_Add => + sp <= sp + 1; + state <= State_Add; + + when Decoded_Or => + sp <= sp + 1; + state <= State_Or; + + when Decoded_And => + sp <= sp + 1; + state <= State_And; + + when Decoded_Load => + if (memARead(ioBit) = '1') then + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + out_mem_readEnable <= '1'; + state <= State_ReadIO; + else + memAAddr <= memARead(maxAddrBit downto minAddrBit); + end if; + + when Decoded_Not => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + memAWrite <= not memARead; + + when Decoded_Flip => + memAAddr <= sp(maxAddrBit downto minAddrBit); + memAWriteEnable <= '1'; + for i in 0 to wordSize-1 loop + memAWrite(i) <= memARead(wordSize-1-i); + end loop; + + when Decoded_Store => + memBAddr <= sp + 1; + sp <= sp + 1; + if (memARead(ioBit) = '1') then + state <= State_WriteIO; + else + state <= State_Store; + end if; + + when Decoded_PopSP => + sp <= memARead(maxAddrBit downto minAddrBit); + state <= State_Resync; + + when Decoded_Nop => + memAAddr <= sp; + + when others => + null; + + end case; -- decodedOpcode + + when State_ReadIO => + memAAddr <= sp; + if (in_mem_busy = '0') then + state <= State_Fetch; + memAWriteEnable <= '1'; + memAWrite <= unsigned(mem_read); + end if; + + when State_WriteIO => + sp <= sp + 1; + out_mem_writeEnable <= '1'; + out_mem_addr <= std_logic_vector(memARead(maxAddrBitIncIO downto 0)); + mem_write <= std_logic_vector(memBRead); + state <= State_WriteIODone; + + when State_WriteIODone => + if (in_mem_busy = '0') then + state <= State_Resync; + end if; + + when State_Fetch => + -- We need to resync. During the *next* cycle + -- we'll fetch the opcode @ pc and thus it will + -- be available for State_Execute the cycle after + -- next + memBAddr <= pc(maxAddrBit downto minAddrBit); + state <= State_FetchNext; + + when State_FetchNext => + -- at this point memARead contains the value that is either + -- from the top of stack or should be copied to the top of the stack + memAWriteEnable <= '1'; + memAWrite <= memARead; + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Decode; + + when State_Decode => + if interrupt = '1' and inInterrupt = '0' and idim_flag = '0' then + -- We got an interrupt, execute interrupt instead of next instruction + inInterrupt <= '1'; + decodedOpcode <= Decoded_Interrupt; + end if; + -- during the State_Execute cycle we'll be fetching SP+1 + memAAddr <= sp; + memBAddr <= sp + 1; + state <= State_Execute; + + when State_Store => + sp <= sp + 1; + memAWriteEnable <= '1'; + memAAddr <= memARead(maxAddrBit downto minAddrBit); + memAWrite <= memBRead; + state <= State_Resync; + + when State_AddSP => + state <= State_Add; + + when State_Add => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead + memBRead; + state <= State_Fetch; + + when State_Or => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead or memBRead; + state <= State_Fetch; + + when State_Resync => + memAAddr <= sp; + state <= State_Fetch; + + when State_And => + memAAddr <= sp; + memAWriteEnable <= '1'; + memAWrite <= memARead and memBRead; + state <= State_Fetch; + + when others => + null; + + end case; -- state + + end if; -- reset, enable + end process; diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd index 59d26e5..f6823f5 100644 --- a/zpu/hdl/zpu4/core/zpupkg.vhd +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -32,173 +32,187 @@ -- are those of the authors and should not be interpreted as representing -- official policies, either expressed or implied, of the ZPU Project. -library IEEE; -use IEEE.STD_LOGIC_1164.all; +library ieee; +use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.zpu_config.all; + package zpupkg is - -- This bit is set for read/writes to IO - -- FIX!!! eventually this should be set to wordSize-1 so as to - -- to make the address of IO independent of amount of memory - -- reserved for CPU. Requires trivial tweaks in toolchain/runtime - -- libraries. - - constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes - constant maxAddrBit : integer := maxAddrBitIncIO-1; - constant ioBit : integer := maxAddrBit+1; - constant wordSize : integer := 2**wordPower; - constant wordBytes : integer := wordSize/8; - constant minAddrBit : integer := byteBits; - -- configurable internal stack size. Probably going to be 16 after toolchain is done - constant stack_bits : integer := 5; - constant stack_size : integer := 2**stack_bits; - - - component dualport_ram is - port (clk : in std_logic; - memAWriteEnable : in std_logic; - memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memAWrite : in std_logic_vector(wordSize-1 downto 0); - memARead : out std_logic_vector(wordSize-1 downto 0); - memBWriteEnable : in std_logic; - memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); - memBWrite : in std_logic_vector(wordSize-1 downto 0); - memBRead : out std_logic_vector(wordSize-1 downto 0)); - end component; - - - component dram is - port (clk : in std_logic; - areset : in std_logic; - mem_writeEnable : in std_logic; - mem_readEnable : in std_logic; - mem_addr : in std_logic_vector(maxAddrBit downto 0); - mem_write : in std_logic_vector(wordSize-1 downto 0); - mem_read : out std_logic_vector(wordSize-1 downto 0); - mem_busy : out std_logic; - mem_writeMask : in std_logic_vector(wordBytes-1 downto 0)); - end component; - - - component trace is - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBitIncIO downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); - memA : in std_logic_vector(wordSize-1 downto 0); - memB : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic; - intSp : in std_logic_vector(stack_bits-1 downto 0) - ); - end component; - - component zpu_core is - port ( clk : in std_logic; - areset : in std_logic; - enable : in std_logic; - in_mem_busy : in std_logic; - mem_read : in std_logic_vector(wordSize-1 downto 0); - mem_write : out std_logic_vector(wordSize-1 downto 0); - out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); - out_mem_writeEnable : out std_logic; - out_mem_readEnable : out std_logic; - mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); - interrupt : in std_logic; - break : out std_logic); - end component; - - - - component timer is - port( - clk : in std_logic; - areset : in std_logic; - we : in std_logic; - din : in std_logic_vector(7 downto 0); - adr : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(7 downto 0)); - end component; - - component zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); - end component; - - - - - -- opcode decode constants - constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; - constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; - constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; - constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; - constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; - constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; - - constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; - constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001"; - constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; - constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011"; - - constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; - constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; - constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; - constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; - - constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; - constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; - constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; - constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; - - constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; - constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; - constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110"; - constant OpCode_NA : std_logic_vector(3 downto 0) := "1111"; - - constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); - constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); - constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); - constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); - - constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); - constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); - - constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); - constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); - constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); - constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); - - constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); - constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); - - constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); - constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); - constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); - - constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); - constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); - constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); - - constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); - constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); - constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); - - - - constant OpCode_Size : integer := 8; - - - + -- This bit is set for read/writes to IO + -- FIX!!! eventually this should be set to wordSize-1 so as to + -- to make the address of IO independent of amount of memory + -- reserved for CPU. Requires trivial tweaks in toolchain/runtime + -- libraries. + + constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes + constant maxAddrBit : integer := maxAddrBitIncIO-1; + constant ioBit : integer := maxAddrBit+1; + constant wordSize : integer := 2**wordPower; + constant wordBytes : integer := wordSize/8; + constant minAddrBit : integer := byteBits; + -- configurable internal stack size. Probably going to be 16 after toolchain is done + constant stack_bits : integer := 5; + constant stack_size : integer := 2**stack_bits; + + + ------------------------------------------------------------ + -- components + + component dualport_ram is + port ( + clk : in std_logic; + memAWriteEnable : in std_logic; + memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memAWrite : in std_logic_vector(wordSize-1 downto 0); + memARead : out std_logic_vector(wordSize-1 downto 0); + memBWriteEnable : in std_logic; + memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit); + memBWrite : in std_logic_vector(wordSize-1 downto 0); + memBRead : out std_logic_vector(wordSize-1 downto 0) + ); + end component dualport_ram; + + + component dram is + port ( + clk : in std_logic; + areset : in std_logic; + mem_writeEnable : in std_logic; + mem_readEnable : in std_logic; + mem_addr : in std_logic_vector(maxAddrBit downto 0); + mem_write : in std_logic_vector(wordSize-1 downto 0); + mem_read : out std_logic_vector(wordSize-1 downto 0); + mem_busy : out std_logic; + mem_writeMask : in std_logic_vector(wordBytes-1 downto 0) + ); + end component dram; + + + component trace is + port ( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); + end component trace; + + + component zpu_core is + port ( + clk : in std_logic; + areset : in std_logic; + enable : in std_logic; + in_mem_busy : in std_logic; + mem_read : in std_logic_vector(wordSize-1 downto 0); + mem_write : out std_logic_vector(wordSize-1 downto 0); + out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); + out_mem_writeEnable : out std_logic; + out_mem_readEnable : out std_logic; + mem_writeMask : out std_logic_vector(wordBytes-1 downto 0); + interrupt : in std_logic; + break : out std_logic + ); + end component zpu_core; + + + component timer is + port ( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0) + ); + end component timer; + + + component zpuio is + port ( + areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0) + ); + end component zpuio; + + + ------------------------------------------------------------ + -- constants + + -- opcode decode constants + constant OpCode_Im : std_logic_vector(7 downto 7) := "1"; + constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010"; + constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011"; + constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001"; + constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001"; + constant OpCode_Short : std_logic_vector(7 downto 4) := "0000"; + -- + constant OpCode_Break : std_logic_vector(3 downto 0) := "0000"; + constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001"; + constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010"; + constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011"; + -- + constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100"; + constant OpCode_Add : std_logic_vector(3 downto 0) := "0101"; + constant OpCode_And : std_logic_vector(3 downto 0) := "0110"; + constant OpCode_Or : std_logic_vector(3 downto 0) := "0111"; + -- + constant OpCode_Load : std_logic_vector(3 downto 0) := "1000"; + constant OpCode_Not : std_logic_vector(3 downto 0) := "1001"; + constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010"; + constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011"; + -- + constant OpCode_Store : std_logic_vector(3 downto 0) := "1100"; + constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101"; + constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110"; + constant OpCode_NA : std_logic_vector(3 downto 0) := "1111"; + -- + constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6)); + constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6)); + constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6)); + constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6)); + -- + constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6)); + constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6)); + -- + constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6)); + constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6)); + constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6)); + constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6)); + -- + constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6)); + constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6)); + -- + constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6)); + constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6)); + constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6)); + -- + constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6)); + constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6)); + constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6)); + -- + constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6)); + constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6)); + constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6)); + -- + -- + constant OpCode_Size : integer := 8; + + + end zpupkg; -- cgit v1.1 From 04772b6a0bbe7017f5f7b44cfa203c3f7efbff64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 1 Mar 2011 20:52:55 +0100 Subject: whitespace fixes: use fromdos on all .vhd files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- zpu/hdl/zpu4/core/zpu_config.vhd | 84 +-- zpu/hdl/zpu4/core/zpu_core.vhd | 154 ++--- zpu/hdl/zpu4/core/zpu_core_small.vhd | 112 +-- zpu/hdl/zpu4/core/zpupkg.vhd | 86 +-- zpu/hdl/zpu4/src/clocks.vhd | 490 +++++++------- zpu/hdl/zpu4/src/io.vhd | 224 +++--- zpu/hdl/zpu4/src/timer.vhd | 122 ++-- zpu/hdl/zpu4/src/trace.vhd | 234 +++---- zpu/hdl/zpu4/src/txt_util.vhd | 1242 +++++++++++++++++----------------- zpu/hdl/zpu4/src/zpuio.vhd | 464 ++++++------- 10 files changed, 1606 insertions(+), 1606 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd index 112dd01..5b3110c 100644 --- a/zpu/hdl/zpu4/core/zpu_config.vhd +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -1,44 +1,44 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -package zpu_config is +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +package zpu_config is -- generate trace output or not. constant Generate_Trace : boolean := false; @@ -56,4 +56,4 @@ package zpu_config is constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); -end zpu_config; +end zpu_config; diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd index ff9449f..e2e4781 100644 --- a/zpu/hdl/zpu4/core/zpu_core.vhd +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -1,68 +1,68 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- Copyright 2008 alvieboy - Álvaro Lopes - alvieboy@alvie.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - --- mem_writeEnable - set to '1' for a single cycle to send off a write request. --- mem_write is valid only while mem_writeEnable='1'. --- mem_readEnable - set to '1' for a single cycle to send off a read request. --- --- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. --- Set to '0' when mem_read is valid after a read request. --- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable --- is '1'. --- mem_addr - address for read/write request --- mem_read - read data. Valid only on the cycle after mem_busy='0' after --- mem_readEnable='1' for a single cycle. --- mem_write - data to write --- mem_writeMask - set to '1' for those bits that are to be written to memory upon --- write request --- break - set to '1' when CPU hits break instruction --- interrupt - set to '1' until interrupts are cleared by CPU. - - - - -entity zpu_core is +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +-- mem_writeEnable - set to '1' for a single cycle to send off a write request. +-- mem_write is valid only while mem_writeEnable='1'. +-- mem_readEnable - set to '1' for a single cycle to send off a read request. +-- +-- mem_busy - It is illegal to send off a read/write request when mem_busy='1'. +-- Set to '0' when mem_read is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after mem_read/writeEnable +-- is '1'. +-- mem_addr - address for read/write request +-- mem_read - read data. Valid only on the cycle after mem_busy='0' after +-- mem_readEnable='1' for a single cycle. +-- mem_write - data to write +-- mem_writeMask - set to '1' for those bits that are to be written to memory upon +-- write request +-- break - set to '1' when CPU hits break instruction +-- interrupt - set to '1' until interrupts are cleared by CPU. + + + + +entity zpu_core is port ( clk : in std_logic; areset : in std_logic; @@ -77,10 +77,10 @@ entity zpu_core is interrupt : in std_logic; break : out std_logic ); -end zpu_core; - -architecture behave of zpu_core is - +end zpu_core; + +architecture behave of zpu_core is + type InsnType is ( State_AddTop, State_Dup, @@ -196,12 +196,12 @@ architecture behave of zpu_core is signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); - --- state machine. - -begin - - + +-- state machine. + +begin + + traceFileGenerate : if Generate_Trace generate trace_file : trace port map ( @@ -1009,7 +1009,7 @@ begin end case; -- state end if; -- clk'event end process; - - - -end behave; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 1df9546..757d056 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -1,47 +1,47 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - - -entity zpu_core is +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + + +entity zpu_core is port ( clk : in std_logic; -- asynchronous reset signal @@ -67,12 +67,12 @@ entity zpu_core is -- in simulation to stop simulation break : out std_logic ); -end zpu_core; - - - +end zpu_core; + + + architecture behave of zpu_core is - + signal memAWriteEnable : std_logic; signal memAAddr : unsigned(maxAddrBit downto minAddrBit); signal memAWrite : unsigned(wordSize-1 downto 0); @@ -171,11 +171,11 @@ architecture behave of zpu_core is signal tOpcode_sel : index; -- signal inInterrupt : std_logic; - - - -begin - + + + +begin + -- generate a trace file. -- -- This is only used in simulation to see what instructions are @@ -596,7 +596,7 @@ begin end if; -- reset, enable end process; - - - -end behave; + + + +end behave; diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd index f6823f5..a6e749d 100644 --- a/zpu/hdl/zpu4/core/zpupkg.vhd +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -1,47 +1,47 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + library ieee; use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.zpu_config.all; - - -package zpupkg is - +use ieee.numeric_std.all; + +library work; +use work.zpu_config.all; + + +package zpupkg is + -- This bit is set for read/writes to IO -- FIX!!! eventually this should be set to wordSize-1 so as to -- to make the address of IO independent of amount of memory @@ -215,4 +215,4 @@ package zpupkg is -end zpupkg; +end zpupkg; diff --git a/zpu/hdl/zpu4/src/clocks.vhd b/zpu/hdl/zpu4/src/clocks.vhd index a352b3c..704d790 100644 --- a/zpu/hdl/zpu4/src/clocks.vhd +++ b/zpu/hdl/zpu4/src/clocks.vhd @@ -1,246 +1,246 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity clocks is - port ( areset : in std_logic; - cpu_clk_p : in std_logic; - sdr_clk_fb_p : in std_logic; - cpu_clk : out std_logic; - cpu_clk_2x : out std_logic; - cpu_clk_4x : out std_logic; - ddr_in_clk : out std_logic; - ddr_in_clk_2x : out std_logic; - locked : out std_logic_vector(2 downto 0)); -end clocks; - -architecture behave of clocks is - -signal low : std_logic; - -signal cpu_clk_in : std_logic; -signal sdr_clk_fb_in : std_logic; - -signal dcm_cpu1 : std_logic; -signal dcm_cpu2 : std_logic; -signal dcm_cpu2_dum : std_logic; -signal dcm_cpu4 : std_logic; -signal dcm_ddr2 : std_logic; -signal dcm_ddr2_2x : std_logic; - -signal cpu_clk_int : std_logic; -signal cpu_clk_2x_int : std_logic; -signal cpu_clk_2x_dum_int : std_logic; -signal cpu_clk_4x_int : std_logic; -signal ddr_in_clk_int : std_logic; -signal ddr_in_clk_2x_int : std_logic; - -signal dcm1_locked_del : std_logic; -signal dcm2_locked_del : std_logic; -signal dcm2_reset : std_logic; -signal dcm3_reset : std_logic; - -signal locked_int : std_logic_vector(2 downto 0); -signal del_addr : std_logic_vector(3 downto 0); - -begin - - low <= '0'; - del_addr <= "1111"; - - cpu_clk <= cpu_clk_int; - cpu_clk_2x <= cpu_clk_2x_int; - cpu_clk_4x <= cpu_clk_4x_int; - ddr_in_clk <= ddr_in_clk_int; - ddr_in_clk_2x <= ddr_in_clk_2x_int; - locked <= locked_int; - - - CPU_IBUFG: - IBUFG port map ( - O => cpu_clk_in, - I => cpu_clk_p); - - SDR_FB_IBUFG: - IBUFG port map ( - O => sdr_clk_fb_in, - I => sdr_clk_fb_p); - - dcm2_rst: - SRL16 generic map ( - INIT => X"0000") - port map ( - Q => dcm1_locked_del, - A0 => del_addr(0), - A1 => del_addr(1), - A2 => del_addr(2), - A3 => del_addr(3), - CLK => cpu_clk_int, - D => locked_int(0)); - - dcm2_reset <= not(dcm1_locked_del); - - dcm3_rst: - SRL16 generic map ( - INIT => X"0000") - port map ( - Q => dcm2_locked_del, - A0 => del_addr(0), - A1 => del_addr(1), - A2 => del_addr(2), - A3 => del_addr(3), - CLK => cpu_clk_int, - D => locked_int(1)); - - dcm3_reset <= not(dcm2_locked_del); - - cpu1_dcm: - DCM generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 15.625, -- Specify period of input clock - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"8080", -- FACTORY JF Values - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => dcm_cpu2, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked_int(0), -- DCM LOCK status output - PSDONE => open, -- Dynamic phase adjust done output - STATUS => open, -- 8-bit DCM status bits output - CLKFB => cpu_clk_int, -- DCM clock feedback - CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) - PSCLK => low, -- Dynamic phase adjust clock input - PSEN => low, -- Dynamic phase adjust enable input - PSINCDEC => low, -- Dynamic phase adjust increment/decrement - RST => areset); -- DCM asynchronous reset input - - cpu2_dcm: - DCM generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 7.8125, -- Specify period of input clock - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"8080", -- FACTORY JF Values - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => dcm_cpu4, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked_int(1), -- DCM LOCK status output - PSDONE => open, -- Dynamic phase adjust done output - STATUS => open, -- 8-bit DCM status bits output - CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback - CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) - PSCLK => low, -- Dynamic phase adjust clock input - PSEN => low, -- Dynamic phase adjust enable input - PSINCDEC => low, -- Dynamic phase adjust increment/decrement - RST => dcm2_reset); -- DCM asynchronous reset input - - ddr_read_dcm: - DCM generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 7.8125, -- Specify period of input clock - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE --- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"8080", -- FACTORY JF Values - PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255 --- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked_int(2), -- DCM LOCK status output - PSDONE => open, -- Dynamic phase adjust done output - STATUS => open, -- 8-bit DCM status bits output - CLKFB => ddr_in_clk_int, -- DCM clock feedback - CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) - PSCLK => low, -- Dynamic phase adjust clock input - PSEN => low, -- Dynamic phase adjust enable input - PSINCDEC => low, -- Dynamic phase adjust increment/decrement - RST => dcm3_reset); -- DCM asynchronous reset input - - cpu1: - BUFG port map ( - I => dcm_cpu1, - O => cpu_clk_int); - - cpu2: - BUFG port map ( - I => dcm_cpu2, - O => cpu_clk_2x_int); - - cpu2_dum: - BUFG port map ( - I => dcm_cpu2_dum, - O => cpu_clk_2x_dum_int); - - cpu4: - BUFG port map ( - I => dcm_cpu4, - O => cpu_clk_4x_int); - - ddr_clk: - BUFG port map ( - I => dcm_ddr2, - O => ddr_in_clk_int); - - ddr_clk_2x: - BUFG port map ( - I => dcm_ddr2_2x, - O => ddr_in_clk_2x_int); - +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity clocks is + port ( areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0)); +end clocks; + +architecture behave of clocks is + +signal low : std_logic; + +signal cpu_clk_in : std_logic; +signal sdr_clk_fb_in : std_logic; + +signal dcm_cpu1 : std_logic; +signal dcm_cpu2 : std_logic; +signal dcm_cpu2_dum : std_logic; +signal dcm_cpu4 : std_logic; +signal dcm_ddr2 : std_logic; +signal dcm_ddr2_2x : std_logic; + +signal cpu_clk_int : std_logic; +signal cpu_clk_2x_int : std_logic; +signal cpu_clk_2x_dum_int : std_logic; +signal cpu_clk_4x_int : std_logic; +signal ddr_in_clk_int : std_logic; +signal ddr_in_clk_2x_int : std_logic; + +signal dcm1_locked_del : std_logic; +signal dcm2_locked_del : std_logic; +signal dcm2_reset : std_logic; +signal dcm3_reset : std_logic; + +signal locked_int : std_logic_vector(2 downto 0); +signal del_addr : std_logic_vector(3 downto 0); + +begin + + low <= '0'; + del_addr <= "1111"; + + cpu_clk <= cpu_clk_int; + cpu_clk_2x <= cpu_clk_2x_int; + cpu_clk_4x <= cpu_clk_4x_int; + ddr_in_clk <= ddr_in_clk_int; + ddr_in_clk_2x <= ddr_in_clk_2x_int; + locked <= locked_int; + + + CPU_IBUFG: + IBUFG port map ( + O => cpu_clk_in, + I => cpu_clk_p); + + SDR_FB_IBUFG: + IBUFG port map ( + O => sdr_clk_fb_in, + I => sdr_clk_fb_p); + + dcm2_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm1_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(0)); + + dcm2_reset <= not(dcm1_locked_del); + + dcm3_rst: + SRL16 generic map ( + INIT => X"0000") + port map ( + Q => dcm2_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(1)); + + dcm3_reset <= not(dcm2_locked_del); + + cpu1_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 15.625, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu2, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(0), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_int, -- DCM clock feedback + CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => areset); -- DCM asynchronous reset input + + cpu2_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_cpu4, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(1), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback + CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm2_reset); -- DCM asynchronous reset input + + ddr_read_dcm: + DCM generic map ( + CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 + CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 + CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature + CLKIN_PERIOD => 7.8125, -- Specify period of input clock + CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE +-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE + CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + -- an integer from 0 to 15 + DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis + DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL + DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE + FACTORY_JF => X"8080", -- FACTORY JF Values + PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255 +-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 + STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE + port map ( + CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput + CLK180 => open, -- 180 degree DCM CLK output + CLK270 => open, -- 270 degree DCM CLK output + CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output + CLK2X180 => open, -- 2X, 180 degree DCM CLK out + CLK90 => open, -- 90 degree DCM CLK output + CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) + CLKFX => open, -- DCM CLK synthesis out (M/D) + CLKFX180 => open, -- 180 degree CLK synthesis out + LOCKED => locked_int(2), -- DCM LOCK status output + PSDONE => open, -- Dynamic phase adjust done output + STATUS => open, -- 8-bit DCM status bits output + CLKFB => ddr_in_clk_int, -- DCM clock feedback + CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) + PSCLK => low, -- Dynamic phase adjust clock input + PSEN => low, -- Dynamic phase adjust enable input + PSINCDEC => low, -- Dynamic phase adjust increment/decrement + RST => dcm3_reset); -- DCM asynchronous reset input + + cpu1: + BUFG port map ( + I => dcm_cpu1, + O => cpu_clk_int); + + cpu2: + BUFG port map ( + I => dcm_cpu2, + O => cpu_clk_2x_int); + + cpu2_dum: + BUFG port map ( + I => dcm_cpu2_dum, + O => cpu_clk_2x_dum_int); + + cpu4: + BUFG port map ( + I => dcm_cpu4, + O => cpu_clk_4x_int); + + ddr_clk: + BUFG port map ( + I => dcm_ddr2, + O => ddr_in_clk_int); + + ddr_clk_2x: + BUFG port map ( + I => dcm_ddr2_2x, + O => ddr_in_clk_2x_int); + end behave; \ No newline at end of file diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index a0e494a..159df6f 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -1,112 +1,112 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use std.textio.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; -use work.txt_util.all; - -entity zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end zpu_io; - - -architecture behave of zpu_io is - - - -signal timer_read : std_logic_vector(7 downto 0); ---signal timer_write : std_logic_vector(7 downto 0); -signal timer_we : std_logic; - -signal serving : std_logic; - -file l_file : TEXT open write_mode is log_file; -constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0'); -constant tx_full: std_logic := '0'; -constant rx_empty: std_logic := '1'; - -begin - - - timerinst: timer port map ( - clk => clk, - areset => areset, - we => timer_we, - din => write(7 downto 0), - adr => addr(4 downto 2), - dout => timer_read); - - busy <= writeEnable or readEnable; - timer_we <= writeEnable and addr(12); - - process(areset, clk) - variable taddr : std_logic_vector(maxAddrBit downto 0); - begin - taddr := (others => '0'); - taddr(maxAddrBit downto minAddrBit) := addr; - - if (areset = '1') then --- timer_we <= '0'; - elsif (clk'event and clk = '1') then --- timer_we <= '0'; - if writeEnable = '1' then - -- external interface (fixed address) - -- extend compare to avoid waring messages - if ("1" & addr & lowAddrBits)=x"80a000c" then - report "Write to UART[0]" & " :0x" & hstr(write); - -- Write to UART - -- report "" & character'image(conv_integer(memBint)) severity note; - print(l_file, character'val(to_integer(unsigned(write)))); - elsif addr(12)='1' then - report "Write to TIMER" & " :0x" & hstr(write); --- report "xxx" severity failure; --- timer_we <= '1'; - else - print(l_file, character'val(to_integer(unsigned(write)))); - report "Illegal IO write @" & "0x" & hstr(taddr) severity warning; - end if; - - end if; - read <= (others => '0'); - if (readEnable = '1') then - -- extend compare to avoid waring messages - if ("1" & addr & lowAddrBits)=x"80a000c" then - report "Read UART[0]"; - read(8) <= not tx_full; -- output fifo not full - read(9) <= not rx_empty; -- receiver not empty - elsif ("1" & addr & lowAddrBits)=x"80a0010" then - report "Read UART[1]"; - read(8) <= not rx_empty; -- receiver not empty - read(7 downto 0) <= (others => '0'); - elsif addr(12)='1' then - report "Read TIMER"; - read(7 downto 0) <= timer_read; - elsif addr(11)='1' then - report "Read ZPU Freq"; - read(7 downto 0) <= ZPU_Frequency; - else - report "Illegal IO read @" & "0x" & hstr(taddr) severity warning; - end if; - end if; - end if; - end process; - - -end behave; - +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + +entity zpu_io is + generic ( + log_file: string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end zpu_io; + + +architecture behave of zpu_io is + + + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + +signal serving : std_logic; + +file l_file : TEXT open write_mode is log_file; +constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0'); +constant tx_full: std_logic := '0'; +constant rx_empty: std_logic := '1'; + +begin + + + timerinst: timer port map ( + clk => clk, + areset => areset, + we => timer_we, + din => write(7 downto 0), + adr => addr(4 downto 2), + dout => timer_read); + + busy <= writeEnable or readEnable; + timer_we <= writeEnable and addr(12); + + process(areset, clk) + variable taddr : std_logic_vector(maxAddrBit downto 0); + begin + taddr := (others => '0'); + taddr(maxAddrBit downto minAddrBit) := addr; + + if (areset = '1') then +-- timer_we <= '0'; + elsif (clk'event and clk = '1') then +-- timer_we <= '0'; + if writeEnable = '1' then + -- external interface (fixed address) + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits)=x"80a000c" then + report "Write to UART[0]" & " :0x" & hstr(write); + -- Write to UART + -- report "" & character'image(conv_integer(memBint)) severity note; + print(l_file, character'val(to_integer(unsigned(write)))); + elsif addr(12)='1' then + report "Write to TIMER" & " :0x" & hstr(write); +-- report "xxx" severity failure; +-- timer_we <= '1'; + else + print(l_file, character'val(to_integer(unsigned(write)))); + report "Illegal IO write @" & "0x" & hstr(taddr) severity warning; + end if; + + end if; + read <= (others => '0'); + if (readEnable = '1') then + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits)=x"80a000c" then + report "Read UART[0]"; + read(8) <= not tx_full; -- output fifo not full + read(9) <= not rx_empty; -- receiver not empty + elsif ("1" & addr & lowAddrBits)=x"80a0010" then + report "Read UART[1]"; + read(8) <= not rx_empty; -- receiver not empty + read(7 downto 0) <= (others => '0'); + elsif addr(12)='1' then + report "Read TIMER"; + read(7 downto 0) <= timer_read; + elsif addr(11)='1' then + report "Read ZPU Freq"; + read(7 downto 0) <= ZPU_Frequency; + else + report "Illegal IO read @" & "0x" & hstr(taddr) severity warning; + end if; + end if; + end if; + end process; + + +end behave; + diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd index be1dbb8..c60c172 100644 --- a/zpu/hdl/zpu4/src/timer.vhd +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -1,61 +1,61 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity timer is - port( - clk : in std_logic; - areset : in std_logic; - we : in std_logic; - din : in std_logic_vector(7 downto 0); - adr : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(7 downto 0)); -end timer; - - -architecture behave of timer is - -signal sample : std_logic; -signal reset : std_logic; - - -signal cnt : unsigned(63 downto 0); -signal cnt_smp : std_logic_vector(63 downto 0); - -begin - - reset <= '1' when (we = '1' and din(0) = '1') else '0'; - sample <= '1' when (we = '1' and din(1) = '1') else '0'; - - process(clk, areset) -- Carry generation - begin - if areset = '1' then - cnt <= (others => '0'); - cnt_smp <= (others => '0'); - elsif (clk'event and clk = '1') then - cnt <= cnt + 1; - if sample = '1' then --- report "sampling" severity failure; - cnt_smp <= std_logic_vector(cnt); - end if; - end if; - end process; - - - process(cnt_smp, adr) - begin - case adr is - when "000" => dout <= cnt_smp(7 downto 0); - when "001" => dout <= cnt_smp(15 downto 8); - when "010" => dout <= cnt_smp(23 downto 16); - when "011" => dout <= cnt_smp(31 downto 24); - when "100" => dout <= cnt_smp(39 downto 32); - when "101" => dout <= cnt_smp(47 downto 40); - when "110" => dout <= cnt_smp(55 downto 48); - when others => dout <= cnt_smp(63 downto 56); - end case; - end process; - - -end behave; - +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); +end timer; + + +architecture behave of timer is + +signal sample : std_logic; +signal reset : std_logic; + + +signal cnt : unsigned(63 downto 0); +signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + elsif (clk'event and clk = '1') then + cnt <= cnt + 1; + if sample = '1' then +-- report "sampling" severity failure; + cnt_smp <= std_logic_vector(cnt); + end if; + end if; + end process; + + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end behave; + diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd index 2413970..00ac3a8 100644 --- a/zpu/hdl/zpu4/src/trace.vhd +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -1,117 +1,117 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use std.textio.all; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; -use work.txt_util.all; - - -entity trace is - generic ( - log_file: string := "trace.txt" - ); - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBitIncIO downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBitIncIO downto 2); - memA : in std_logic_vector(wordSize-1 downto 0); - memB : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic; - intSp : in std_logic_vector(stack_bits-1 downto 0) - ); -end trace; - - -architecture behave of trace is - - -file l_file : TEXT open write_mode is log_file; - - -begin - - --- write data and control information to a file - -receive_data: process - -variable l: line; -variable t : std_logic_vector(wordSize-1 downto 0); -variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); -variable counter : unsigned(63 downto 0); - - - -begin - - t:= (others => '0'); - t2:= (others => '0'); - -counter := (others => '0'); - -- print header for the logfile - print(l_file, "#pc,opcode,sp,top_of_stack "); - print(l_file, "#----------"); - print(l_file, " "); - - wait until clk = '1'; - wait until clk = '0'; - - while true loop - - counter := counter + 1; - if begin_inst = '1' then - t(maxAddrBitIncIO downto 2):=sp; - t2:=pc; - print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter))); - end if; - - wait until clk = '0'; - - end loop; - - end process receive_data; - - - -end behave; - +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use std.textio.all; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; +use work.txt_util.all; + + +entity trace is + generic ( + log_file: string := "trace.txt" + ); + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); +end trace; + + +architecture behave of trace is + + +file l_file : TEXT open write_mode is log_file; + + +begin + + +-- write data and control information to a file + +receive_data: process + +variable l: line; +variable t : std_logic_vector(wordSize-1 downto 0); +variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); +variable counter : unsigned(63 downto 0); + + + +begin + + t:= (others => '0'); + t2:= (others => '0'); + +counter := (others => '0'); + -- print header for the logfile + print(l_file, "#pc,opcode,sp,top_of_stack "); + print(l_file, "#----------"); + print(l_file, " "); + + wait until clk = '1'; + wait until clk = '0'; + + while true loop + + counter := counter + 1; + if begin_inst = '1' then + t(maxAddrBitIncIO downto 2):=sp; + t2:=pc; + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter))); + end if; + + wait until clk = '0'; + + end loop; + + end process receive_data; + + + +end behave; + diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd index 3d5297a..6432294 100644 --- a/zpu/hdl/zpu4/src/txt_util.vhd +++ b/zpu/hdl/zpu4/src/txt_util.vhd @@ -1,621 +1,621 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; - -library work; - -package txt_util is - - -- prints a message to the screen - procedure print(text: string); - - -- prints the message when active - -- useful for debug switches - procedure print(active: boolean; text: string); - - -- converts std_logic into a character - function chr(sl: std_logic) return character; - - -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; - - -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; - - -- converts boolean into a string - function str(b: boolean) return string; - - -- converts an integer into a single character - -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; - - -- converts integer into string using specified base - function str(int: integer; base: integer) return string; - - -- converts integer to string, using base 10 - function str(int: integer) return string; - - -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; - - - -- functions to manipulate strings - ----------------------------------- - - -- convert a character to upper case - function to_upper(c: character) return character; - - -- convert a character to lower case - function to_lower(c: character) return character; - - -- convert a string to upper case - function to_upper(s: string) return string; - - -- convert a string to lower case - function to_lower(s: string) return string; - - - - -- functions to convert strings into other formats - -------------------------------------------------- - - -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - - -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; - - - - -- file I/O - ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - - - - -package body txt_util is - - - - - -- prints text to the screen - - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; - - - - - -- prints text to the screen when active - - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; - - - -- converts std_logic into a character - - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); - begin - s(1) := chr(sl); - return s; - end str; - - - - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is - - begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin - case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; - end case; - return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin - - -- bug fix for negative numbers - abs_int := abs(int); - - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is - - begin - - return str(int, 10) ; - - end str; - - - - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; - - - - -- functions to manipulate strings - ----------------------------------- - - - -- convert a character to upper case - - function to_upper(c: character) return character is - - variable u: character; - - begin - - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; - - begin - - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - - function to_upper(s: string) return string is - - variable uppercase: string (s'range); - - begin - - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - - end to_upper; - - - - -- convert a string to lower case - - function to_lower(s: string) return string is - - variable lowercase: string (s'range); - - begin - - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - - end to_lower; - - - --- functions to convert strings into other types - - --- converts a character into a std_logic - -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; - begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - - - - -end txt_util; - - - - +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + +library work; + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + + diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd index 09a1ddd..2c7fd41 100644 --- a/zpu/hdl/zpu4/src/zpuio.vhd +++ b/zpu/hdl/zpu4/src/zpuio.vhd @@ -1,232 +1,232 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.zpu_config.all; -use work.zpupkg.all; - -entity zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); -end zpuio; - -architecture behave of zpuio is - -signal timer_read : std_logic_vector(7 downto 0); ---signal timer_write : std_logic_vector(7 downto 0); -signal timer_we : std_logic; - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); ---signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal Enable : std_logic; - -signal din : std_logic_vector(7 downto 0); -signal dout : std_logic_vector(7 downto 0); -signal adr : std_logic_vector(15 downto 0); -signal break : std_logic; -signal we : std_logic; -signal re : std_logic; - - --- uart forwarding... - -signal uartTXPending : std_logic; -signal uartTXCleared : std_logic; -signal uartData : std_logic_vector(7 downto 0); - -signal readingTimer : std_logic; - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - - ---signal io_mem_read : std_logic_vector(7 downto 0); ---signal io_mem_writeEnable : std_logic; ---signal io_mem_readEnable : std_logic; -signal io_readEnable : std_logic; - - -signal dram_read : std_logic; - - - -begin - - io_addr <= mem_addr(maxAddrBit downto minAddrBit); - - timerinst: timer port map ( - clk => cpu_clk, - areset => areset, - we => timer_we, - din => mem_write(7 downto 0), - adr => io_addr(4 downto 2), - dout => timer_read); - - zpu: zpu_core port map ( - clk => cpu_clk , - areset => areset, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - -ram_imp: dram port map ( - clk => cpu_clk , - areset => areset, - mem_busy => dram_mem_busy, - mem_read => dram_mem_read, - mem_write => mem_write, - mem_addr => mem_addr(maxAddrBit downto 0), - mem_writeEnable => dram_mem_writeEnable, - mem_readEnable => dram_mem_readEnable, - mem_writeMask => mem_writeMask); - - - - fauxUart: - process(cpu_clk, areset) - begin - if areset = '1' then - io_busy <= '0'; - uartTXPending <= '0'; - timer_we <= '0'; - io_busy <= '0'; - uartData <= x"58"; -- 'X' - readingTimer <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - timer_we <= '0'; - io_busy <= '0'; - if uartTXCleared = '1' then - uartTXPending <= '0'; - end if; - - if io_writeEnable = '1' then - if io_addr=x"2028003" then - -- Write to UART - uartData <= mem_write(7 downto 0); - uartTXPending <= '1'; - io_busy <= '1'; - elsif io_addr(12)='1' then - timer_we <= '1'; - io_busy <= '1'; - else --- report "Illegal IO write" severity failure; - end if; - end if; - if (io_readEnable = '1') then - if io_addr=x"2028003" then - io_read <= (0=>'1', -- recieve empty - 1 => uartTXPending, -- tx full - others => '0'); - io_busy <= '1'; - elsif io_addr(12)='1' then - readingTimer <= '1'; - io_busy <= '1'; - elsif io_addr(11)='1' then - io_read <= ZPU_Frequency; - io_busy <= '1'; - else --- report "Illegal IO read" severity failure; - end if; - - else - if (readingTimer = '1') then - readingTimer <= '0'; - io_read <= timer_read; - io_busy <= '0'; - else - io_read <= (others => '1'); - end if; - end if; - end if; - end process; - - - forwardUARTOutputToARM: - process(cpu_clk, areset) - begin - if areset = '1' then - uartTXCleared <= '0'; - elsif (cpu_clk = '1' and cpu_clk'event) then - if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then - uartTXCleared <= cpu_din(0); - else - uartTXCleared <= uartTXCleared; - end if; - end if; - end process; - - cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); - cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_writeEnable <= mem_writeEnable and mem_addr(ioBit); --- io_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable; - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(cpu_clk, areset) - begin - if areset = '1' then - dram_read <= '0'; - io_readEnable <= '0'; - - - elsif (cpu_clk'event and cpu_clk = '1') then - mem_read <= (others => '0'); - if mem_addr(ioBit)='0' and mem_readEnable='1' then - dram_read <= '1'; - end if; - if dram_read='1' and dram_mem_busy='0' then - dram_read <= '0'; - mem_read <= dram_mem_read; - end if; - - if mem_addr(ioBit)='1' and mem_readEnable='1' then - io_readEnable <= '1'; - end if; - if io_readEnable='1' and io_busy='0' then - io_readEnable <= '0'; - mem_read(7 downto 0) <= io_read; - end if; - - end if; - end process; - - -end behave; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.zpu_config.all; +use work.zpupkg.all; + +entity zpuio is + port ( areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0)); +end zpuio; + +architecture behave of zpuio is + +signal timer_read : std_logic_vector(7 downto 0); +--signal timer_write : std_logic_vector(7 downto 0); +signal timer_we : std_logic; + + +signal io_busy : std_logic; +signal io_read : std_logic_vector(7 downto 0); +--signal io_write : std_logic_vector(7 downto 0); +signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); +signal io_writeEnable : std_logic; +signal Enable : std_logic; + +signal din : std_logic_vector(7 downto 0); +signal dout : std_logic_vector(7 downto 0); +signal adr : std_logic_vector(15 downto 0); +signal break : std_logic; +signal we : std_logic; +signal re : std_logic; + + +-- uart forwarding... + +signal uartTXPending : std_logic; +signal uartTXCleared : std_logic; +signal uartData : std_logic_vector(7 downto 0); + +signal readingTimer : std_logic; + + + + +signal mem_busy : std_logic; +signal mem_read : std_logic_vector(wordSize-1 downto 0); +signal mem_write : std_logic_vector(wordSize-1 downto 0); +signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); +signal mem_writeEnable : std_logic; +signal mem_readEnable : std_logic; +signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + +signal dram_mem_busy : std_logic; +signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); +signal dram_mem_writeEnable : std_logic; +signal dram_mem_readEnable : std_logic; +signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); + + + +--signal io_mem_read : std_logic_vector(7 downto 0); +--signal io_mem_writeEnable : std_logic; +--signal io_mem_readEnable : std_logic; +signal io_readEnable : std_logic; + + +signal dram_read : std_logic; + + + +begin + + io_addr <= mem_addr(maxAddrBit downto minAddrBit); + + timerinst: timer port map ( + clk => cpu_clk, + areset => areset, + we => timer_we, + din => mem_write(7 downto 0), + adr => io_addr(4 downto 2), + dout => timer_read); + + zpu: zpu_core port map ( + clk => cpu_clk , + areset => areset, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break); + + +ram_imp: dram port map ( + clk => cpu_clk , + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask); + + + + fauxUart: + process(cpu_clk, areset) + begin + if areset = '1' then + io_busy <= '0'; + uartTXPending <= '0'; + timer_we <= '0'; + io_busy <= '0'; + uartData <= x"58"; -- 'X' + readingTimer <= '0'; + elsif (cpu_clk'event and cpu_clk = '1') then + timer_we <= '0'; + io_busy <= '0'; + if uartTXCleared = '1' then + uartTXPending <= '0'; + end if; + + if io_writeEnable = '1' then + if io_addr=x"2028003" then + -- Write to UART + uartData <= mem_write(7 downto 0); + uartTXPending <= '1'; + io_busy <= '1'; + elsif io_addr(12)='1' then + timer_we <= '1'; + io_busy <= '1'; + else +-- report "Illegal IO write" severity failure; + end if; + end if; + if (io_readEnable = '1') then + if io_addr=x"2028003" then + io_read <= (0=>'1', -- recieve empty + 1 => uartTXPending, -- tx full + others => '0'); + io_busy <= '1'; + elsif io_addr(12)='1' then + readingTimer <= '1'; + io_busy <= '1'; + elsif io_addr(11)='1' then + io_read <= ZPU_Frequency; + io_busy <= '1'; + else +-- report "Illegal IO read" severity failure; + end if; + + else + if (readingTimer = '1') then + readingTimer <= '0'; + io_read <= timer_read; + io_busy <= '0'; + else + io_read <= (others => '1'); + end if; + end if; + end if; + end process; + + + forwardUARTOutputToARM: + process(cpu_clk, areset) + begin + if areset = '1' then + uartTXCleared <= '0'; + elsif (cpu_clk = '1' and cpu_clk'event) then + if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then + uartTXCleared <= cpu_din(0); + else + uartTXCleared <= uartTXCleared; + end if; + end if; + end process; + + cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); + cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_writeEnable <= mem_writeEnable and mem_addr(ioBit); +-- io_readEnable <= mem_readEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol: + process(cpu_clk, areset) + begin + if areset = '1' then + dram_read <= '0'; + io_readEnable <= '0'; + + + elsif (cpu_clk'event and cpu_clk = '1') then + mem_read <= (others => '0'); + if mem_addr(ioBit)='0' and mem_readEnable='1' then + dram_read <= '1'; + end if; + if dram_read='1' and dram_mem_busy='0' then + dram_read <= '0'; + mem_read <= dram_mem_read; + end if; + + if mem_addr(ioBit)='1' and mem_readEnable='1' then + io_readEnable <= '1'; + end if; + if io_readEnable='1' and io_busy='0' then + io_readEnable <= '0'; + mem_read(7 downto 0) <= io_read; + end if; + + end if; + end process; + + +end behave; -- cgit v1.1 From f54a7949bc551f4a4ecc20728453cfe09ae65aed Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Fri, 4 Mar 2011 10:40:56 +0100 Subject: change: switch to ieee.numeric_std.all library Signed-off-by: Bert Lange --- zpu/hdl/zpu4/core/zpu_config.vhd | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd index 5b3110c..b29c561 100644 --- a/zpu/hdl/zpu4/core/zpu_config.vhd +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -35,8 +35,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; package zpu_config is @@ -54,6 +53,6 @@ package zpu_config is -- start byte address of stack. -- point to top of RAM - 2*words constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := - conv_std_logic_vector((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1); + std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1)); end zpu_config; -- cgit v1.1 From 509095f846aa8b2393ab7bf974eb2932846b950f Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Thu, 9 Jun 2011 17:54:03 +0200 Subject: fix: missing comment --- zpu/hdl/zpu4/core/zpu_core_small.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index 757d056..b975977 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -308,7 +308,7 @@ begin when others => sampledDecodedOpcode <= Decoded_Nop; end case; -- tOpcode(3 downto 0) - end if; tOpcode + end if; -- tOpcode end process; -- cgit v1.1 From b9ad801c86a4bf2f37be4972737b9c401335a49c Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Thu, 9 Jun 2011 17:59:07 +0200 Subject: change: rename signal areset to reset --- zpu/hdl/zpu4/core/zpu_core.vhd | 6 +++--- zpu/hdl/zpu4/core/zpu_core_small.vhd | 6 +++--- zpu/hdl/zpu4/core/zpupkg.vhd | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd index e2e4781..1b95444 100644 --- a/zpu/hdl/zpu4/core/zpu_core.vhd +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -65,7 +65,7 @@ use work.zpupkg.all; entity zpu_core is port ( clk : in std_logic; - areset : in std_logic; + reset : in std_logic; enable : in std_logic; in_mem_busy : in std_logic; mem_read : in std_logic_vector(wordSize-1 downto 0); @@ -230,7 +230,7 @@ begin decSp <= sp - 1; - opcodeControl : process(clk, areset) + opcodeControl : process(clk, reset) variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); variable spOffset : unsigned(4 downto 0); variable tSpOffset : unsigned(4 downto 0); @@ -239,7 +239,7 @@ begin variable tDecodedOpcode : InsnArray; variable tMultResult : unsigned(wordSize*2-1 downto 0); begin - if areset = '1' then + if reset = '1' then state <= State_Idle; break <= '0'; sp <= unsigned(spStart(maxAddrBitIncIO downto minAddrBit)); diff --git a/zpu/hdl/zpu4/core/zpu_core_small.vhd b/zpu/hdl/zpu4/core/zpu_core_small.vhd index b975977..9ac35a8 100644 --- a/zpu/hdl/zpu4/core/zpu_core_small.vhd +++ b/zpu/hdl/zpu4/core/zpu_core_small.vhd @@ -45,7 +45,7 @@ entity zpu_core is port ( clk : in std_logic; -- asynchronous reset signal - areset : in std_logic; + reset : in std_logic; -- this particular implementation of the ZPU does not -- have a clocked enable signal enable : in std_logic; @@ -312,11 +312,11 @@ begin end process; - opcodeControl: process(clk, areset) + opcodeControl: process(clk, reset) variable spOffset : unsigned(4 downto 0); begin - if areset = '1' then + if reset = '1' then state <= State_Resync; break <= '0'; sp <= unsigned(spStart(maxAddrBit downto minAddrBit)); diff --git a/zpu/hdl/zpu4/core/zpupkg.vhd b/zpu/hdl/zpu4/core/zpupkg.vhd index a6e749d..0363aca 100644 --- a/zpu/hdl/zpu4/core/zpupkg.vhd +++ b/zpu/hdl/zpu4/core/zpupkg.vhd @@ -110,7 +110,7 @@ package zpupkg is component zpu_core is port ( clk : in std_logic; - areset : in std_logic; + reset : in std_logic; enable : in std_logic; in_mem_busy : in std_logic; mem_read : in std_logic_vector(wordSize-1 downto 0); -- cgit v1.1 From bb1b38ce7d74dbf5ff5bb57576011ed825a8330d Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Tue, 2 Aug 2011 14:17:00 +0200 Subject: change: prettier logifle output --- zpu/hdl/zpu4/src/io.vhd | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index 159df6f..f05b29b 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -56,7 +56,11 @@ begin timer_we <= writeEnable and addr(12); process(areset, clk) - variable taddr : std_logic_vector(maxAddrBit downto 0); + variable taddr : std_logic_vector(maxAddrBit downto 0); + -- pragma translate_off + variable line_out : line := new string'(""); + variable char : character; + -- pragma translate_on begin taddr := (others => '0'); taddr(maxAddrBit downto minAddrBit) := addr; @@ -69,17 +73,25 @@ begin -- external interface (fixed address) -- extend compare to avoid waring messages if ("1" & addr & lowAddrBits)=x"80a000c" then - report "Write to UART[0]" & " :0x" & hstr(write); -- Write to UART - -- report "" & character'image(conv_integer(memBint)) severity note; - print(l_file, character'val(to_integer(unsigned(write)))); + report "Write to UART[0]" & " :0x" & hstr(write); + -- pragma translate_off + char := character'val(to_integer(unsigned(write))); + if char = lf then + std.textio.writeline( l_file, line_out); + else + std.textio.write( line_out, char); + end if; + -- pragma translate_on + elsif addr(12)='1' then report "Write to TIMER" & " :0x" & hstr(write); -- report "xxx" severity failure; -- timer_we <= '1'; + else - print(l_file, character'val(to_integer(unsigned(write)))); - report "Illegal IO write @" & "0x" & hstr(taddr) severity warning; + + report "Illegal IO write @" & "0x" & hstr(taddr) severity warning; end if; end if; -- cgit v1.1 From ec177759929085f161b9a5c7c82016406d8867cb Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Tue, 16 Aug 2011 23:43:12 +0200 Subject: beautify indentation --- zpu/hdl/zpu4/core/zpu_config.vhd | 116 +++--- zpu/hdl/zpu4/src/clocks.vhd | 418 +++++++++---------- zpu/hdl/zpu4/src/io.vhd | 191 +++++---- zpu/hdl/zpu4/src/timer.vhd | 102 ++--- zpu/hdl/zpu4/src/trace.vhd | 106 +++-- zpu/hdl/zpu4/src/txt_util.vhd | 852 ++++++++++++++++++--------------------- zpu/hdl/zpu4/src/zpuio.vhd | 424 ++++++++++--------- 7 files changed, 1025 insertions(+), 1184 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_config.vhd b/zpu/hdl/zpu4/core/zpu_config.vhd index b29c561..c678044 100644 --- a/zpu/hdl/zpu4/core/zpu_config.vhd +++ b/zpu/hdl/zpu4/core/zpu_config.vhd @@ -1,58 +1,58 @@ --- ZPU --- --- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com --- --- The FreeBSD license --- --- Redistribution and use in source and binary forms, with or without --- modification, are permitted provided that the following conditions --- are met: --- --- 1. Redistributions of source code must retain the above copyright --- notice, this list of conditions and the following disclaimer. --- 2. Redistributions in binary form must reproduce the above --- copyright notice, this list of conditions and the following --- disclaimer in the documentation and/or other materials --- provided with the distribution. --- --- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY --- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE --- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, --- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS --- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) --- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, --- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF --- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --- --- The views and conclusions contained in the software and documentation --- are those of the authors and should not be interpreted as representing --- official policies, either expressed or implied, of the ZPU Project. - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package zpu_config is - - -- generate trace output or not. - constant Generate_Trace : boolean := false; - constant wordPower : integer := 5; - -- during simulation, set this to '0' to get matching trace.txt - constant DontCareValue : std_logic := 'X'; - -- Clock frequency in MHz. - constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; - -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) - constant maxAddrBitIncIO : integer := 15; - constant maxAddrBitBRAM : integer := 14; - - -- start byte address of stack. - -- point to top of RAM - 2*words - constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := - std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1)); - -end zpu_config; +-- ZPU +-- +-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com +-- +-- The FreeBSD license +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions +-- are met: +-- +-- 1. Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above +-- copyright notice, this list of conditions and the following +-- disclaimer in the documentation and/or other materials +-- provided with the distribution. +-- +-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY +-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-- The views and conclusions contained in the software and documentation +-- are those of the authors and should not be interpreted as representing +-- official policies, either expressed or implied, of the ZPU Project. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package zpu_config is + + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := 'X'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"64"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 15; + constant maxAddrBitBRAM : integer := 14; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := + std_logic_vector(to_unsigned((2**(maxAddrBitBRAM+1))-8, maxAddrBitIncIO+1)); + +end zpu_config; diff --git a/zpu/hdl/zpu4/src/clocks.vhd b/zpu/hdl/zpu4/src/clocks.vhd index 704d790..67433be 100644 --- a/zpu/hdl/zpu4/src/clocks.vhd +++ b/zpu/hdl/zpu4/src/clocks.vhd @@ -1,246 +1,198 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.ibufg; +use unisim.vcomponents.srl16; +use unisim.vcomponents.dcm; +use unisim.vcomponents.bufg; -library UNISIM; -use UNISIM.vcomponents.all; entity clocks is - port ( areset : in std_logic; - cpu_clk_p : in std_logic; - sdr_clk_fb_p : in std_logic; - cpu_clk : out std_logic; - cpu_clk_2x : out std_logic; - cpu_clk_4x : out std_logic; - ddr_in_clk : out std_logic; - ddr_in_clk_2x : out std_logic; - locked : out std_logic_vector(2 downto 0)); -end clocks; + port ( + areset : in std_logic; + cpu_clk_p : in std_logic; + sdr_clk_fb_p : in std_logic; + cpu_clk : out std_logic; + cpu_clk_2x : out std_logic; + cpu_clk_4x : out std_logic; + ddr_in_clk : out std_logic; + ddr_in_clk_2x : out std_logic; + locked : out std_logic_vector(2 downto 0) + ); +end entity clocks; architecture behave of clocks is -signal low : std_logic; + signal low : std_logic; + -- + signal cpu_clk_in : std_logic; + signal sdr_clk_fb_in : std_logic; + -- + signal dcm_cpu1 : std_logic; + signal dcm_cpu2 : std_logic; + signal dcm_cpu2_dum : std_logic; + signal dcm_cpu4 : std_logic; + signal dcm_ddr2 : std_logic; + signal dcm_ddr2_2x : std_logic; + -- + signal cpu_clk_int : std_logic; + signal cpu_clk_2x_int : std_logic; + signal cpu_clk_2x_dum_int : std_logic; + signal cpu_clk_4x_int : std_logic; + signal ddr_in_clk_int : std_logic; + signal ddr_in_clk_2x_int : std_logic; + -- + signal dcm1_locked_del : std_logic; + signal dcm2_locked_del : std_logic; + signal dcm2_reset : std_logic; + signal dcm3_reset : std_logic; + -- + signal locked_int : std_logic_vector(2 downto 0); + signal del_addr : std_logic_vector(3 downto 0); + +begin -signal cpu_clk_in : std_logic; -signal sdr_clk_fb_in : std_logic; + low <= '0'; + del_addr <= "1111"; + -- + cpu_clk <= cpu_clk_int; + cpu_clk_2x <= cpu_clk_2x_int; + cpu_clk_4x <= cpu_clk_4x_int; + ddr_in_clk <= ddr_in_clk_int; + ddr_in_clk_2x <= ddr_in_clk_2x_int; + locked <= locked_int; -signal dcm_cpu1 : std_logic; -signal dcm_cpu2 : std_logic; -signal dcm_cpu2_dum : std_logic; -signal dcm_cpu4 : std_logic; -signal dcm_ddr2 : std_logic; -signal dcm_ddr2_2x : std_logic; -signal cpu_clk_int : std_logic; -signal cpu_clk_2x_int : std_logic; -signal cpu_clk_2x_dum_int : std_logic; -signal cpu_clk_4x_int : std_logic; -signal ddr_in_clk_int : std_logic; -signal ddr_in_clk_2x_int : std_logic; + cpu_ibufg : ibufg + port map ( + O => cpu_clk_in, + I => cpu_clk_p + ); -signal dcm1_locked_del : std_logic; -signal dcm2_locked_del : std_logic; -signal dcm2_reset : std_logic; -signal dcm3_reset : std_logic; + sdr_fb_ibufg : ibufg + port map ( + O => sdr_clk_fb_in, + I => sdr_clk_fb_p + ); -signal locked_int : std_logic_vector(2 downto 0); -signal del_addr : std_logic_vector(3 downto 0); + dcm2_rst : srl16 + generic map ( + init => x"0000" + ) + port map ( + Q => dcm1_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(0) + ); -begin + dcm2_reset <= not(dcm1_locked_del); + + dcm3_rst : srl16 + generic map ( + init => x"0000" + ) + port map ( + Q => dcm2_locked_del, + A0 => del_addr(0), + A1 => del_addr(1), + A2 => del_addr(2), + A3 => del_addr(3), + CLK => cpu_clk_int, + D => locked_int(1) + ); + + dcm3_reset <= not(dcm2_locked_del); + + cpu1_dcm : + dcm generic map ( + clkin_period => 15.625, -- Specify period of input clock + factory_jf => X"8080" -- FACTORY JF Values + ) + port map ( + clk0 => dcm_cpu1, -- 0 degree DCM CLK ouptput + clk2x => dcm_cpu2, -- 2X DCM CLK output + locked => locked_int(0), -- DCM LOCK status output + clkfb => cpu_clk_int, -- DCM clock feedback + clkin => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) + psclk => low, -- Dynamic phase adjust clock input + psen => low, -- Dynamic phase adjust enable input + psincdec => low, -- Dynamic phase adjust increment/decrement + rst => areset -- DCM asynchronous reset input + ); + + cpu2_dcm : dcm + generic map ( + clkin_period => 7.8125, -- Specify period of input clock + factory_jf => X"8080" -- FACTORY JF Values + ) + port map ( + clk0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput + clk2x => dcm_cpu4, -- 2X DCM CLK output + locked => locked_int(1), -- DCM LOCK status output + clkfb => cpu_clk_2x_dum_int, -- DCM clock feedback + clkin => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) + psclk => low, -- Dynamic phase adjust clock input + psen => low, -- Dynamic phase adjust enable input + psincdec => low, -- Dynamic phase adjust increment/decrement + rst => dcm2_reset -- DCM asynchronous reset input + ); + + ddr_read_dcm : dcm + generic map ( + clkin_period => 7.8125, -- Specify period of input clock + clkout_phase_shift => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE + factory_jf => X"8080", -- FACTORY JF Values + phase_shift => 103 -- Amount of fixed phase shift from -255 to 255 + ) + port map ( + clk0 => dcm_ddr2, -- 0 degree DCM CLK ouptput + clk2x => dcm_ddr2_2x, -- 2X DCM CLK output + locked => locked_int(2), -- DCM LOCK status output + clkfb => ddr_in_clk_int, -- DCM clock feedback + clkin => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) + psclk => low, -- Dynamic phase adjust clock input + psen => low, -- Dynamic phase adjust enable input + psincdec => low, -- Dynamic phase adjust increment/decrement + rst => dcm3_reset -- DCM asynchronous reset input + ); + + cpu1 : bufg + port map ( + I => dcm_cpu1, + O => cpu_clk_int + ); + + cpu2 : bufg + port map ( + I => dcm_cpu2, + O => cpu_clk_2x_int + ); + + cpu2_dum : bufg + port map ( + i => dcm_cpu2_dum, + o => cpu_clk_2x_dum_int + ); + + cpu4 : bufg + port map ( + i => dcm_cpu4, + o => cpu_clk_4x_int + ); + + ddr_clk : bufg port map ( + i => dcm_ddr2, + o => ddr_in_clk_int + ); + + ddr_clk_2x : bufg port map ( + i => dcm_ddr2_2x, + o => ddr_in_clk_2x_int + ); - low <= '0'; - del_addr <= "1111"; - - cpu_clk <= cpu_clk_int; - cpu_clk_2x <= cpu_clk_2x_int; - cpu_clk_4x <= cpu_clk_4x_int; - ddr_in_clk <= ddr_in_clk_int; - ddr_in_clk_2x <= ddr_in_clk_2x_int; - locked <= locked_int; - - - CPU_IBUFG: - IBUFG port map ( - O => cpu_clk_in, - I => cpu_clk_p); - - SDR_FB_IBUFG: - IBUFG port map ( - O => sdr_clk_fb_in, - I => sdr_clk_fb_p); - - dcm2_rst: - SRL16 generic map ( - INIT => X"0000") - port map ( - Q => dcm1_locked_del, - A0 => del_addr(0), - A1 => del_addr(1), - A2 => del_addr(2), - A3 => del_addr(3), - CLK => cpu_clk_int, - D => locked_int(0)); - - dcm2_reset <= not(dcm1_locked_del); - - dcm3_rst: - SRL16 generic map ( - INIT => X"0000") - port map ( - Q => dcm2_locked_del, - A0 => del_addr(0), - A1 => del_addr(1), - A2 => del_addr(2), - A3 => del_addr(3), - CLK => cpu_clk_int, - D => locked_int(1)); - - dcm3_reset <= not(dcm2_locked_del); - - cpu1_dcm: - DCM generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 15.625, -- Specify period of input clock - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"8080", -- FACTORY JF Values - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_cpu1, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => dcm_cpu2, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked_int(0), -- DCM LOCK status output - PSDONE => open, -- Dynamic phase adjust done output - STATUS => open, -- 8-bit DCM status bits output - CLKFB => cpu_clk_int, -- DCM clock feedback - CLKIN => cpu_clk_in, -- Clock input (from IBUFG, BUFG or DCM) - PSCLK => low, -- Dynamic phase adjust clock input - PSEN => low, -- Dynamic phase adjust enable input - PSINCDEC => low, -- Dynamic phase adjust increment/decrement - RST => areset); -- DCM asynchronous reset input - - cpu2_dcm: - DCM generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 7.8125, -- Specify period of input clock - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"8080", -- FACTORY JF Values - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_cpu2_dum, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => dcm_cpu4, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked_int(1), -- DCM LOCK status output - PSDONE => open, -- Dynamic phase adjust done output - STATUS => open, -- 8-bit DCM status bits output - CLKFB => cpu_clk_2x_dum_int, -- DCM clock feedback - CLKIN => cpu_clk_2x_int, -- Clock input (from IBUFG, BUFG or DCM) - PSCLK => low, -- Dynamic phase adjust clock input - PSEN => low, -- Dynamic phase adjust enable input - PSINCDEC => low, -- Dynamic phase adjust increment/decrement - RST => dcm2_reset); -- DCM asynchronous reset input - - ddr_read_dcm: - DCM generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 7.8125, -- Specify period of input clock - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift of NONE, FIXED or VARIABLE --- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"8080", -- FACTORY JF Values - PHASE_SHIFT => 103, -- Amount of fixed phase shift from -255 to 255 --- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_ddr2, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => dcm_ddr2_2x, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked_int(2), -- DCM LOCK status output - PSDONE => open, -- Dynamic phase adjust done output - STATUS => open, -- 8-bit DCM status bits output - CLKFB => ddr_in_clk_int, -- DCM clock feedback - CLKIN => sdr_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) - PSCLK => low, -- Dynamic phase adjust clock input - PSEN => low, -- Dynamic phase adjust enable input - PSINCDEC => low, -- Dynamic phase adjust increment/decrement - RST => dcm3_reset); -- DCM asynchronous reset input - - cpu1: - BUFG port map ( - I => dcm_cpu1, - O => cpu_clk_int); - - cpu2: - BUFG port map ( - I => dcm_cpu2, - O => cpu_clk_2x_int); - - cpu2_dum: - BUFG port map ( - I => dcm_cpu2_dum, - O => cpu_clk_2x_dum_int); - - cpu4: - BUFG port map ( - I => dcm_cpu4, - O => cpu_clk_4x_int); - - ddr_clk: - BUFG port map ( - I => dcm_ddr2, - O => ddr_in_clk_int); - - ddr_clk_2x: - BUFG port map ( - I => dcm_ddr2_2x, - O => ddr_in_clk_2x_int); - -end behave; \ No newline at end of file +end architecture behave; diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd index f05b29b..56c7fb5 100644 --- a/zpu/hdl/zpu4/src/io.vhd +++ b/zpu/hdl/zpu4/src/io.vhd @@ -8,117 +8,112 @@ library work; use work.zpu_config.all; use work.zpupkg.all; use work.txt_util.all; - -entity zpu_io is - generic ( - log_file: string := "log.txt" - ); - port( - clk : in std_logic; - areset : in std_logic; - busy : out std_logic; - writeEnable : in std_logic; - readEnable : in std_logic; - write : in std_logic_vector(wordSize-1 downto 0); - read : out std_logic_vector(wordSize-1 downto 0); - addr : in std_logic_vector(maxAddrBit downto minAddrBit) - ); -end zpu_io; - - -architecture behave of zpu_io is +entity zpu_io is + generic ( + log_file : string := "log.txt" + ); + port( + clk : in std_logic; + areset : in std_logic; + busy : out std_logic; + writeEnable : in std_logic; + readEnable : in std_logic; + write : in std_logic_vector(wordSize-1 downto 0); + read : out std_logic_vector(wordSize-1 downto 0); + addr : in std_logic_vector(maxAddrBit downto minAddrBit) + ); +end entity zpu_io; -signal timer_read : std_logic_vector(7 downto 0); ---signal timer_write : std_logic_vector(7 downto 0); -signal timer_we : std_logic; -signal serving : std_logic; +architecture behave of zpu_io is -file l_file : TEXT open write_mode is log_file; -constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0'); -constant tx_full: std_logic := '0'; -constant rx_empty: std_logic := '1'; + signal timer_read : std_logic_vector(7 downto 0); + signal timer_we : std_logic; + -- + signal serving : std_logic; + -- + file l_file : text open write_mode is log_file; + constant lowAddrBits : std_logic_vector(minAddrBit-1 downto 0) := (others => '0'); + constant tx_full : std_logic := '0'; + constant rx_empty : std_logic := '1'; begin - - timerinst: timer port map ( - clk => clk, - areset => areset, - we => timer_we, - din => write(7 downto 0), - adr => addr(4 downto 2), - dout => timer_read); - - busy <= writeEnable or readEnable; - timer_we <= writeEnable and addr(12); - - process(areset, clk) - variable taddr : std_logic_vector(maxAddrBit downto 0); - -- pragma translate_off - variable line_out : line := new string'(""); - variable char : character; - -- pragma translate_on - begin - taddr := (others => '0'); - taddr(maxAddrBit downto minAddrBit) := addr; - - if (areset = '1') then --- timer_we <= '0'; - elsif (clk'event and clk = '1') then --- timer_we <= '0'; - if writeEnable = '1' then - -- external interface (fixed address) - -- extend compare to avoid waring messages - if ("1" & addr & lowAddrBits)=x"80a000c" then - -- Write to UART - report "Write to UART[0]" & " :0x" & hstr(write); + + timerinst : timer + port map ( + clk => clk, + areset => areset, + we => timer_we, + din => write(7 downto 0), + adr => addr(4 downto 2), + dout => timer_read + ); + + busy <= writeEnable or readEnable; + timer_we <= writeEnable and addr(12); + + process(areset, clk) + variable taddr : std_logic_vector(maxAddrBit downto 0); + -- pragma translate_off + variable line_out : line := new string'(""); + variable char : character; + -- pragma translate_on + begin + taddr := (others => '0'); + taddr(maxAddrBit downto minAddrBit) := addr; + + if (areset = '1') then + elsif (clk'event and clk = '1') then + if writeEnable = '1' then + -- external interface (fixed address) + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits) = x"80a000c" then + -- Write to UART + report "Write to UART[0]" & " :0x" & hstr(write); -- pragma translate_off - char := character'val(to_integer(unsigned(write))); + char := character'val(to_integer(unsigned(write))); if char = lf then - std.textio.writeline( l_file, line_out); + std.textio.writeline(l_file, line_out); else - std.textio.write( line_out, char); + std.textio.write(line_out, char); end if; -- pragma translate_on - elsif addr(12)='1' then - report "Write to TIMER" & " :0x" & hstr(write); --- report "xxx" severity failure; --- timer_we <= '1'; + elsif addr(12) = '1' then + report "Write to TIMER" & " :0x" & hstr(write); - else - + else + report "Illegal IO write @" & "0x" & hstr(taddr) severity warning; - end if; - - end if; - read <= (others => '0'); - if (readEnable = '1') then - -- extend compare to avoid waring messages - if ("1" & addr & lowAddrBits)=x"80a000c" then - report "Read UART[0]"; - read(8) <= not tx_full; -- output fifo not full - read(9) <= not rx_empty; -- receiver not empty - elsif ("1" & addr & lowAddrBits)=x"80a0010" then - report "Read UART[1]"; - read(8) <= not rx_empty; -- receiver not empty - read(7 downto 0) <= (others => '0'); - elsif addr(12)='1' then - report "Read TIMER"; - read(7 downto 0) <= timer_read; - elsif addr(11)='1' then - report "Read ZPU Freq"; - read(7 downto 0) <= ZPU_Frequency; - else - report "Illegal IO read @" & "0x" & hstr(taddr) severity warning; - end if; - end if; - end if; - end process; - - -end behave; - + end if; + + end if; + read <= (others => '0'); + if (readEnable = '1') then + -- extend compare to avoid waring messages + if ("1" & addr & lowAddrBits) = x"80a000c" then + report "Read UART[0]"; + read(8) <= not tx_full; -- output fifo not full + read(9) <= not rx_empty; -- receiver not empty + elsif ("1" & addr & lowAddrBits) = x"80a0010" then + report "Read UART[1]"; + read(8) <= not rx_empty; -- receiver not empty + read(7 downto 0) <= (others => '0'); + elsif addr(12) = '1' then + report "Read TIMER"; + read(7 downto 0) <= timer_read; + elsif addr(11) = '1' then + report "Read ZPU Freq"; + read(7 downto 0) <= ZPU_Frequency; + else + report "Illegal IO read @" & "0x" & hstr(taddr) severity warning; + end if; + end if; + end if; + end process; + +end architecture behave; + diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd index c60c172..d6d9358 100644 --- a/zpu/hdl/zpu4/src/timer.vhd +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -1,61 +1,61 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; - + entity timer is - port( - clk : in std_logic; - areset : in std_logic; - we : in std_logic; - din : in std_logic_vector(7 downto 0); - adr : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(7 downto 0)); -end timer; - - -architecture behave of timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0) + ); +end entity timer; -signal sample : std_logic; -signal reset : std_logic; +architecture behave of timer is -signal cnt : unsigned(63 downto 0); -signal cnt_smp : std_logic_vector(63 downto 0); + signal sample : std_logic; + signal reset : std_logic; + -- + signal cnt : unsigned(63 downto 0); + signal cnt_smp : std_logic_vector(63 downto 0); begin - reset <= '1' when (we = '1' and din(0) = '1') else '0'; - sample <= '1' when (we = '1' and din(1) = '1') else '0'; - - process(clk, areset) -- Carry generation - begin - if areset = '1' then - cnt <= (others => '0'); - cnt_smp <= (others => '0'); - elsif (clk'event and clk = '1') then - cnt <= cnt + 1; - if sample = '1' then --- report "sampling" severity failure; - cnt_smp <= std_logic_vector(cnt); - end if; - end if; - end process; - - - process(cnt_smp, adr) - begin - case adr is - when "000" => dout <= cnt_smp(7 downto 0); - when "001" => dout <= cnt_smp(15 downto 8); - when "010" => dout <= cnt_smp(23 downto 16); - when "011" => dout <= cnt_smp(31 downto 24); - when "100" => dout <= cnt_smp(39 downto 32); - when "101" => dout <= cnt_smp(47 downto 40); - when "110" => dout <= cnt_smp(55 downto 48); - when others => dout <= cnt_smp(63 downto 56); - end case; - end process; - - -end behave; - + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + elsif rising_edge(clk) then + cnt <= cnt + 1; + if sample = '1' then +-- report "sampling" severity failure; + cnt_smp <= std_logic_vector(cnt); + end if; + end if; + end process; + + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end architecture behave; + diff --git a/zpu/hdl/zpu4/src/trace.vhd b/zpu/hdl/zpu4/src/trace.vhd index 00ac3a8..01678c8 100644 --- a/zpu/hdl/zpu4/src/trace.vhd +++ b/zpu/hdl/zpu4/src/trace.vhd @@ -42,76 +42,66 @@ library work; use work.zpu_config.all; use work.zpupkg.all; use work.txt_util.all; - - -entity trace is - generic ( - log_file: string := "trace.txt" - ); - port( - clk : in std_logic; - begin_inst : in std_logic; - pc : in std_logic_vector(maxAddrBitIncIO downto 0); - opcode : in std_logic_vector(7 downto 0); - sp : in std_logic_vector(maxAddrBitIncIO downto 2); - memA : in std_logic_vector(wordSize-1 downto 0); - memB : in std_logic_vector(wordSize-1 downto 0); - busy : in std_logic; - intSp : in std_logic_vector(stack_bits-1 downto 0) - ); -end trace; - - -architecture behave of trace is - - -file l_file : TEXT open write_mode is log_file; -begin +entity trace is + generic ( + log_file : string := "trace.txt" + ); + port( + clk : in std_logic; + begin_inst : in std_logic; + pc : in std_logic_vector(maxAddrBitIncIO downto 0); + opcode : in std_logic_vector(7 downto 0); + sp : in std_logic_vector(maxAddrBitIncIO downto 2); + memA : in std_logic_vector(wordSize-1 downto 0); + memB : in std_logic_vector(wordSize-1 downto 0); + busy : in std_logic; + intSp : in std_logic_vector(stack_bits-1 downto 0) + ); +end entity trace; --- write data and control information to a file +architecture behave of trace is + + file l_file : text open write_mode is log_file; -receive_data: process +begin -variable l: line; -variable t : std_logic_vector(wordSize-1 downto 0); -variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); -variable counter : unsigned(63 downto 0); - - - -begin + -- write data and control information to a file + receive_data : process + variable l : line; + variable t : std_logic_vector(wordSize-1 downto 0); + variable t2 : std_logic_vector(maxAddrBitIncIO downto 0); + variable counter : unsigned(63 downto 0); + begin - t:= (others => '0'); - t2:= (others => '0'); + t := (others => '0'); + t2 := (others => '0'); -counter := (others => '0'); - -- print header for the logfile - print(l_file, "#pc,opcode,sp,top_of_stack "); - print(l_file, "#----------"); - print(l_file, " "); + counter := (others => '0'); - wait until clk = '1'; - wait until clk = '0'; + -- print header for the logfile + print(l_file, "#pc,opcode,sp,top_of_stack "); + print(l_file, "#----------"); + print(l_file, " "); - while true loop + wait until clk = '1'; + wait until clk = '0'; - counter := counter + 1; - if begin_inst = '1' then - t(maxAddrBitIncIO downto 2):=sp; - t2:=pc; - print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter))); - end if; - - wait until clk = '0'; - - end loop; + while true loop - end process receive_data; + counter := counter + 1; + if begin_inst = '1' then + t(maxAddrBitIncIO downto 2) := sp; + t2 := pc; + print(l_file, "0x" & hstr(t2) & " 0x" & hstr(opcode) & " 0x" & hstr(t) & " 0x" & hstr(memA) & " 0x" & hstr(memB) & " 0x" & hstr(intSp) & " 0x" & hstr(std_logic_vector(counter))); + end if; + wait until clk = '0'; + + end loop; + end process receive_data; +end architecture behave; -end behave; - diff --git a/zpu/hdl/zpu4/src/txt_util.vhd b/zpu/hdl/zpu4/src/txt_util.vhd index 6432294..4dca901 100644 --- a/zpu/hdl/zpu4/src/txt_util.vhd +++ b/zpu/hdl/zpu4/src/txt_util.vhd @@ -36,586 +36,504 @@ library ieee; use ieee.std_logic_1164.all; use std.textio.all; -library work; package txt_util is -- prints a message to the screen - procedure print(text: string); + procedure print(text : string); -- prints the message when active -- useful for debug switches - procedure print(active: boolean; text: string); + procedure print(active : boolean; text : string); -- converts std_logic into a character - function chr(sl: std_logic) return character; + function chr(sl : std_logic) return character; -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; + function str(sl : std_logic) return string; -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; + function str(slv : std_logic_vector) return string; -- converts boolean into a string - function str(b: boolean) return string; + function str(b : boolean) return string; -- converts an integer into a single character -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; + function chr(int : integer) return character; -- converts integer into string using specified base - function str(int: integer; base: integer) return string; + function str(int : integer; base : integer) return string; -- converts integer to string, using base 10 - function str(int: integer) return string; + function str(int : integer) return string; -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; + function hstr(slv : std_logic_vector) return string; -- functions to manipulate strings ----------------------------------- -- convert a character to upper case - function to_upper(c: character) return character; + function to_upper(c : character) return character; -- convert a character to lower case - function to_lower(c: character) return character; + function to_lower(c : character) return character; -- convert a string to upper case - function to_upper(s: string) return string; + function to_upper(s : string) return string; -- convert a string to lower case - function to_lower(s: string) return string; + function to_lower(s : string) return string; + + - - -- functions to convert strings into other formats -------------------------------------------------- - + -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - + function to_std_logic(c : character) return std_logic; + -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; + function to_std_logic_vector(s : string) return std_logic_vector; + - -- file I/O ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - + -- read variable length string from input file + procedure str_read(file in_file : text; res_string : out string); + -- print string to a file and start new line + procedure print(file out_file : text; new_string : in string); -package body txt_util is + -- print character to a file and start new line + procedure print(file out_file : text; char : in character); +end package txt_util; - -- prints text to the screen - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; +package body txt_util is + -- prints text to the screen + procedure print(text : string) is + variable msg_line : line; + begin + write(msg_line, text); + writeline(output, msg_line); + end procedure print; - -- prints text to the screen when active + -- prints text to the screen when active + procedure print(active : boolean; text : string) is + begin + if active then + print(text); + end if; + end procedure print; - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; + -- converts std_logic into a character + function chr(sl : std_logic) return character is + variable c : character; + begin + case sl is + when 'U' => c := 'U'; + when 'X' => c := 'X'; + when '0' => c := '0'; + when '1' => c := '1'; + when 'Z' => c := 'Z'; + when 'W' => c := 'W'; + when 'L' => c := 'L'; + when 'H' => c := 'H'; + when '-' => c := '-'; + end case; + return c; + end function chr; - -- converts std_logic into a character - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); + -- converts std_logic into a string (1 to 1) + function str(sl : std_logic) return string is + variable s : string(1 to 1); begin s(1) := chr(sl); return s; - end str; + end function str; + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + function str(slv : std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end function str; - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is + function str(b : boolean) return string is + begin + if b then + return "true"; + else + return "false"; + end if; + end function str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + function chr(int : integer) return character is + variable c : character; begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; end case; return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin + end function chr; - -- bug fix for negative numbers - abs_int := abs(int); - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + function str(int : integer; base : integer) return string is + variable temp : string(1 to 10); + variable num : integer; + variable abs_int : integer; + variable len : integer := 1; + variable power : integer := 1; + begin - begin + -- bug fix for negative numbers + abs_int := abs(int); - return str(int, 10) ; + num := abs_int; - end str; + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop; -- number. + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop; -- side. + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; + end function str; + -- convert integer to string, using base 10 + function str(int : integer) return string is + begin + return str(int, 10); + end function str; - -- functions to manipulate strings - ----------------------------------- + -- converts a std_logic_vector into a hex string. + function hstr(slv : std_logic_vector) return string is + variable hexlen : integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end function hstr; - -- convert a character to upper case - function to_upper(c: character) return character is - variable u: character; + -- functions to manipulate strings + ----------------------------------- + -- convert a character to upper case + function to_upper(c : character) return character is + variable u : character; begin + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + return u; + end function to_upper; - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; + -- convert a character to lower case + function to_lower(c : character) return character is + variable l : character; begin + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + return l; + end function to_lower; - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - function to_upper(s: string) return string is + -- convert a string to upper case + function to_upper(s : string) return string is + variable uppercase : string (s'range); + begin - variable uppercase: string (s'range); + for i in s'range loop + uppercase(i) := to_upper(s(i)); + end loop; + return uppercase; - begin + end function to_upper; - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - end to_upper; + -- convert a string to lower case + function to_lower(s : string) return string is + variable lowercase : string (s'range); + begin + for i in s'range loop + lowercase(i) := to_lower(s(i)); + end loop; + return lowercase; + end function to_lower; - -- convert a string to lower case + -- functions to convert strings into other types + ------------------------------------------------ - function to_lower(s: string) return string is + -- converts a character into a std_logic + function to_std_logic(c : character) return std_logic is + variable sl : std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end function to_std_logic; - variable lowercase: string (s'range); - begin + -- converts a string into std_logic_vector + function to_std_logic_vector(s : string) return std_logic_vector is + variable slv : std_logic_vector(s'high-s'low downto 0); + variable k : integer; + begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; + end function to_std_logic_vector; - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - end to_lower; + -- file I/O + ------------- + -- read variable length string from input file + procedure str_read(file in_file : text; res_string : out string) is + variable l : line; + variable c : character; + variable is_string : boolean; + begin + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + end procedure str_read; + + + -- print string to a file + procedure print(file out_file : text; new_string : in string) is + variable l : line; + begin + write(l, new_string); + writeline(out_file, l); + end procedure print; --- functions to convert strings into other types + -- print character to a file and start new line + procedure print(file out_file : text; char : in character) is + variable l : line; + begin + write(l, char); + writeline(out_file, l); + end procedure print; --- converts a character into a std_logic -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; + -- appends contents of a string to a file until line feed occurs + -- (LF is considered to be the end of the string) + procedure str_write(file out_file : text; new_string : in string) is begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - - - - -end txt_util; - + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + end procedure str_write; +end package body txt_util; diff --git a/zpu/hdl/zpu4/src/zpuio.vhd b/zpu/hdl/zpu4/src/zpuio.vhd index 2c7fd41..9ca9050 100644 --- a/zpu/hdl/zpu4/src/zpuio.vhd +++ b/zpu/hdl/zpu4/src/zpuio.vhd @@ -1,232 +1,218 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ieee; +use ieee.std_logic_1164.all; library work; use work.zpu_config.all; use work.zpupkg.all; entity zpuio is - port ( areset : in std_logic; - cpu_clk : in std_logic; - clk_status : in std_logic_vector(2 downto 0); - cpu_din : in std_logic_vector(15 downto 0); - cpu_a : in std_logic_vector(20 downto 0); - cpu_we : in std_logic_vector(1 downto 0); - cpu_re : in std_logic; - cpu_dout : inout std_logic_vector(15 downto 0)); + port ( + areset : in std_logic; + cpu_clk : in std_logic; + clk_status : in std_logic_vector(2 downto 0); + cpu_din : in std_logic_vector(15 downto 0); + cpu_a : in std_logic_vector(20 downto 0); + cpu_we : in std_logic_vector(1 downto 0); + cpu_re : in std_logic; + cpu_dout : inout std_logic_vector(15 downto 0) + ); end zpuio; architecture behave of zpuio is -signal timer_read : std_logic_vector(7 downto 0); ---signal timer_write : std_logic_vector(7 downto 0); -signal timer_we : std_logic; - - -signal io_busy : std_logic; -signal io_read : std_logic_vector(7 downto 0); ---signal io_write : std_logic_vector(7 downto 0); -signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); -signal io_writeEnable : std_logic; -signal Enable : std_logic; - -signal din : std_logic_vector(7 downto 0); -signal dout : std_logic_vector(7 downto 0); -signal adr : std_logic_vector(15 downto 0); -signal break : std_logic; -signal we : std_logic; -signal re : std_logic; - - --- uart forwarding... - -signal uartTXPending : std_logic; -signal uartTXCleared : std_logic; -signal uartData : std_logic_vector(7 downto 0); - -signal readingTimer : std_logic; - - - - -signal mem_busy : std_logic; -signal mem_read : std_logic_vector(wordSize-1 downto 0); -signal mem_write : std_logic_vector(wordSize-1 downto 0); -signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); -signal mem_writeEnable : std_logic; -signal mem_readEnable : std_logic; -signal mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - -signal dram_mem_busy : std_logic; -signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); -signal dram_mem_writeEnable : std_logic; -signal dram_mem_readEnable : std_logic; -signal dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0); - - - ---signal io_mem_read : std_logic_vector(7 downto 0); ---signal io_mem_writeEnable : std_logic; ---signal io_mem_readEnable : std_logic; -signal io_readEnable : std_logic; - - -signal dram_read : std_logic; - - + signal timer_read : std_logic_vector(7 downto 0); + signal timer_we : std_logic; + -- + signal io_busy : std_logic; + signal io_read : std_logic_vector(7 downto 0); + signal io_addr : std_logic_vector(maxAddrBit downto minAddrBit); + signal io_writeEnable : std_logic; + signal Enable : std_logic; + -- + signal din : std_logic_vector(7 downto 0); + signal dout : std_logic_vector(7 downto 0); + signal adr : std_logic_vector(15 downto 0); + signal break : std_logic; + signal we : std_logic; + signal re : std_logic; + -- + -- uart forwarding... + signal uartTXPending : std_logic; + signal uartTXCleared : std_logic; + signal uartData : std_logic_vector(7 downto 0); + -- + signal readingTimer : std_logic; + -- + -- + signal mem_busy : std_logic; + signal mem_read : std_logic_vector(wordSize-1 downto 0); + signal mem_write : std_logic_vector(wordSize-1 downto 0); + signal mem_addr : std_logic_vector(maxAddrBitIncIO downto 0); + signal mem_writeEnable : std_logic; + signal mem_readEnable : std_logic; + signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + -- + signal dram_mem_busy : std_logic; + signal dram_mem_read : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_write : std_logic_vector(wordSize-1 downto 0); + signal dram_mem_writeEnable : std_logic; + signal dram_mem_readEnable : std_logic; + signal dram_mem_writeMask : std_logic_vector(wordBytes-1 downto 0); + -- + signal io_readEnable : std_logic; + -- + signal dram_read : std_logic; begin - io_addr <= mem_addr(maxAddrBit downto minAddrBit); - - timerinst: timer port map ( - clk => cpu_clk, - areset => areset, - we => timer_we, - din => mem_write(7 downto 0), - adr => io_addr(4 downto 2), - dout => timer_read); - - zpu: zpu_core port map ( - clk => cpu_clk , - areset => areset, - in_mem_busy => mem_busy, - mem_read => mem_read, - mem_write => mem_write, - out_mem_addr => mem_addr, - out_mem_writeEnable => mem_writeEnable, - out_mem_readEnable => mem_readEnable, - mem_writeMask => mem_writeMask, - interrupt => '0', - break => break); - - -ram_imp: dram port map ( - clk => cpu_clk , - areset => areset, - mem_busy => dram_mem_busy, - mem_read => dram_mem_read, - mem_write => mem_write, - mem_addr => mem_addr(maxAddrBit downto 0), - mem_writeEnable => dram_mem_writeEnable, - mem_readEnable => dram_mem_readEnable, - mem_writeMask => mem_writeMask); - - - - fauxUart: - process(cpu_clk, areset) - begin - if areset = '1' then - io_busy <= '0'; - uartTXPending <= '0'; - timer_we <= '0'; - io_busy <= '0'; - uartData <= x"58"; -- 'X' - readingTimer <= '0'; - elsif (cpu_clk'event and cpu_clk = '1') then - timer_we <= '0'; - io_busy <= '0'; - if uartTXCleared = '1' then - uartTXPending <= '0'; - end if; - - if io_writeEnable = '1' then - if io_addr=x"2028003" then - -- Write to UART - uartData <= mem_write(7 downto 0); - uartTXPending <= '1'; - io_busy <= '1'; - elsif io_addr(12)='1' then - timer_we <= '1'; - io_busy <= '1'; - else --- report "Illegal IO write" severity failure; - end if; - end if; - if (io_readEnable = '1') then - if io_addr=x"2028003" then - io_read <= (0=>'1', -- recieve empty - 1 => uartTXPending, -- tx full - others => '0'); - io_busy <= '1'; - elsif io_addr(12)='1' then - readingTimer <= '1'; - io_busy <= '1'; - elsif io_addr(11)='1' then - io_read <= ZPU_Frequency; - io_busy <= '1'; - else --- report "Illegal IO read" severity failure; - end if; - - else - if (readingTimer = '1') then - readingTimer <= '0'; - io_read <= timer_read; - io_busy <= '0'; - else - io_read <= (others => '1'); - end if; - end if; - end if; - end process; - - - forwardUARTOutputToARM: - process(cpu_clk, areset) - begin - if areset = '1' then - uartTXCleared <= '0'; - elsif (cpu_clk = '1' and cpu_clk'event) then - if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then - uartTXCleared <= cpu_din(0); - else - uartTXCleared <= uartTXCleared; - end if; - end if; - end process; - - cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); - cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); - - dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); - dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); - io_writeEnable <= mem_writeEnable and mem_addr(ioBit); --- io_readEnable <= mem_readEnable and mem_addr(ioBit); - mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable; - - -- Memory reads either come from IO or DRAM. We need to pick the right one. - memorycontrol: - process(cpu_clk, areset) - begin - if areset = '1' then - dram_read <= '0'; - io_readEnable <= '0'; - - - elsif (cpu_clk'event and cpu_clk = '1') then - mem_read <= (others => '0'); - if mem_addr(ioBit)='0' and mem_readEnable='1' then - dram_read <= '1'; - end if; - if dram_read='1' and dram_mem_busy='0' then - dram_read <= '0'; - mem_read <= dram_mem_read; - end if; - - if mem_addr(ioBit)='1' and mem_readEnable='1' then - io_readEnable <= '1'; - end if; - if io_readEnable='1' and io_busy='0' then - io_readEnable <= '0'; - mem_read(7 downto 0) <= io_read; - end if; - - end if; - end process; - - -end behave; + io_addr <= mem_addr(maxAddrBit downto minAddrBit); + + timerinst : timer + port map ( + clk => cpu_clk, + areset => areset, + we => timer_we, + din => mem_write(7 downto 0), + adr => io_addr(4 downto 2), + dout => timer_read + ); + + zpu : zpu_core + port map ( + clk => cpu_clk , + areset => areset, + in_mem_busy => mem_busy, + mem_read => mem_read, + mem_write => mem_write, + out_mem_addr => mem_addr, + out_mem_writeEnable => mem_writeEnable, + out_mem_readEnable => mem_readEnable, + mem_writeMask => mem_writeMask, + interrupt => '0', + break => break + ); + + + ram_imp : dram + port map ( + clk => cpu_clk, + areset => areset, + mem_busy => dram_mem_busy, + mem_read => dram_mem_read, + mem_write => mem_write, + mem_addr => mem_addr(maxAddrBit downto 0), + mem_writeEnable => dram_mem_writeEnable, + mem_readEnable => dram_mem_readEnable, + mem_writeMask => mem_writeMask + ); + + + fauxUart : process(cpu_clk, areset) + begin + if areset = '1' then + io_busy <= '0'; + uartTXPending <= '0'; + timer_we <= '0'; + io_busy <= '0'; + uartData <= x"58"; -- 'X' + readingTimer <= '0'; + elsif rising_edge(cpu_clk) then + timer_we <= '0'; + io_busy <= '0'; + if uartTXCleared = '1' then + uartTXPending <= '0'; + end if; + + if io_writeEnable = '1' then + if io_addr = x"2028003" then + -- Write to UART + uartData <= mem_write(7 downto 0); + uartTXPending <= '1'; + io_busy <= '1'; + elsif io_addr(12) = '1' then + timer_we <= '1'; + io_busy <= '1'; + else + -- report "Illegal IO write" severity failure; + end if; + end if; + if (io_readEnable = '1') then + if io_addr = x"2028003" then + io_read <= (0 => '1', -- recieve empty + 1 => uartTXPending, -- tx full + others => '0'); + io_busy <= '1'; + elsif io_addr(12) = '1' then + readingTimer <= '1'; + io_busy <= '1'; + elsif io_addr(11) = '1' then + io_read <= ZPU_Frequency; + io_busy <= '1'; + else + -- report "Illegal IO read" severity failure; + end if; + + else + if (readingTimer = '1') then + readingTimer <= '0'; + io_read <= timer_read; + io_busy <= '0'; + else + io_read <= (others => '1'); + end if; + end if; + end if; + end process; + + + forwardUARTOutputToARM : process(cpu_clk, areset) + begin + if areset = '1' then + uartTXCleared <= '0'; + elsif rising_edge(cpu_clkt) then + if cpu_we(0) = '1' and cpu_a(3 downto 1) = "000" then + uartTXCleared <= cpu_din(0); + else + uartTXCleared <= uartTXCleared; + end if; + end if; + end process; + + cpu_dout(7 downto 0) <= uartData when (cpu_re = '1' and cpu_a(3 downto 1) = "001") else (others => 'Z'); + cpu_dout <= (0 => uartTXPending, others => '0') when (cpu_re = '1' and cpu_a(3 downto 1) = "000") else (others => 'Z'); + + dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit); + dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit); + io_writeEnable <= mem_writeEnable and mem_addr(ioBit); + mem_busy <= io_busy or dram_mem_busy or dram_read or io_readEnable; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memorycontrol : process(cpu_clk, areset) + begin + if areset = '1' then + dram_read <= '0'; + io_readEnable <= '0'; + + elsif rising_edge(cpu_clk) then + mem_read <= (others => '0'); + if mem_addr(ioBit) = '0' and mem_readEnable = '1' then + dram_read <= '1'; + end if; + if dram_read = '1' and dram_mem_busy = '0' then + dram_read <= '0'; + mem_read <= dram_mem_read; + end if; + + if mem_addr(ioBit) = '1' and mem_readEnable = '1' then + io_readEnable <= '1'; + end if; + if io_readEnable = '1' and io_busy = '0' then + io_readEnable <= '0'; + mem_read(7 downto 0) <= io_read; + end if; + + end if; + end process; + + +end architecture behave; -- cgit v1.1 From e0735185b998f1e0bf61831bb15d802fada4e4ae Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Tue, 25 Oct 2011 23:28:58 +0200 Subject: add: software test for gpio module --- zpu/hdl/zpu4/test/gpiotest/build.sh | 4 ++ zpu/hdl/zpu4/test/gpiotest/gpiotest.c | 72 +++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100755 zpu/hdl/zpu4/test/gpiotest/build.sh create mode 100644 zpu/hdl/zpu4/test/gpiotest/gpiotest.c (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/test/gpiotest/build.sh b/zpu/hdl/zpu4/test/gpiotest/build.sh new file mode 100755 index 0000000..c0385ad --- /dev/null +++ b/zpu/hdl/zpu4/test/gpiotest/build.sh @@ -0,0 +1,4 @@ +zpu-elf-gcc -O3 -phi `pwd`/gpiotest.c -o gpiotest.elf -Wl,--relax -Wl,--gc-sections -g +zpu-elf-objdump --disassemble-all >gpiotest.dis gpiotest.elf +zpu-elf-objcopy -O binary gpiotest.elf gpiotest.bin +java -classpath ../../../../sw/simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam gpiotest.bin >gpiotest.ram diff --git a/zpu/hdl/zpu4/test/gpiotest/gpiotest.c b/zpu/hdl/zpu4/test/gpiotest/gpiotest.c new file mode 100644 index 0000000..393ab9f --- /dev/null +++ b/zpu/hdl/zpu4/test/gpiotest/gpiotest.c @@ -0,0 +1,72 @@ +/* + * Small test program to check GPIOs + * + * LED chaser until keypress + * + */ + +// addresses refer to Phi memory layout +#define GPIO_DATA *((volatile unsigned int *) 0x080a0004) +#define GPIO_DIR *((volatile unsigned int *) 0x080a0008) + + +#define BUTTON_EAST (3) +#define BUTTON_NORTH (2) +#define BUTTON_SOUTH (1) +#define BUTTON_WEST (0) + + +#define bit_is_set(var, bit) ((var) & (1 << (bit))) +#define bit_is_clear(var, bit) ((!(var)) & (1 << (bit))) +#define loop_until_bit_is_set(var, bit) do { } while (bit_is_clear(var, bit)) +#define loop_until_bit_is_clear(var, bit) do { } while (bit_is_set(var, bit)) + + +void led_test( void) +{ + unsigned char runs; + unsigned char leds; + + runs = 1; + leds = 0x01; + + while( runs) + { + // output + GPIO_DATA = leds; + + // read button status + if bit_is_set(GPIO_DATA, BUTTON_NORTH) + { + runs = 0; + } + + // LED chaser + leds = leds << 1; + if (leds == 0) + { + leds = 0x01; + } + } +} + + +void header_test( void) +{ + // this test is special for the SP601 header connector + // check the output in simulation + GPIO_DATA = 0x00550000; + GPIO_DIR = 0xff00ffff; + GPIO_DATA = 0x00aa0000; + GPIO_DIR = 0xffffffff; +} + + +int main(int argc, char **argv) +{ + + led_test(); + header_test(); + + abort(); +} -- cgit v1.1 From 5d41e2b45c7ccf2cb48a20aa77127e4ba1fa3eda Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Tue, 25 Oct 2011 23:30:29 +0200 Subject: minor fix: permission of build-scripts --- zpu/hdl/zpu4/test/dmips/build.sh | 0 zpu/hdl/zpu4/test/hello/build.sh | 0 zpu/hdl/zpu4/test/interrupt/build.sh | 0 3 files changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 zpu/hdl/zpu4/test/dmips/build.sh mode change 100644 => 100755 zpu/hdl/zpu4/test/hello/build.sh mode change 100644 => 100755 zpu/hdl/zpu4/test/interrupt/build.sh (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/test/dmips/build.sh b/zpu/hdl/zpu4/test/dmips/build.sh old mode 100644 new mode 100755 diff --git a/zpu/hdl/zpu4/test/hello/build.sh b/zpu/hdl/zpu4/test/hello/build.sh old mode 100644 new mode 100755 diff --git a/zpu/hdl/zpu4/test/interrupt/build.sh b/zpu/hdl/zpu4/test/interrupt/build.sh old mode 100644 new mode 100755 -- cgit v1.1 From 6f2e0ea6433ae0042e75bf668c5f10b77e6e2bf7 Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Fri, 30 Mar 2012 08:59:26 +0200 Subject: change: rename 'State' to 'Insn' --- zpu/hdl/zpu4/core/zpu_core.vhd | 243 ++++++++++++++++++++--------------------- 1 file changed, 121 insertions(+), 122 deletions(-) (limited to 'zpu/hdl/zpu4') diff --git a/zpu/hdl/zpu4/core/zpu_core.vhd b/zpu/hdl/zpu4/core/zpu_core.vhd index 1b95444..f423f80 100644 --- a/zpu/hdl/zpu4/core/zpu_core.vhd +++ b/zpu/hdl/zpu4/core/zpu_core.vhd @@ -79,48 +79,48 @@ entity zpu_core is ); end zpu_core; + architecture behave of zpu_core is type InsnType is ( - State_AddTop, - State_Dup, - State_DupStackB, - State_Pop, - State_Popdown, - State_Add, - State_Or, - State_And, - State_Store, - State_AddSP, - State_Shift, - State_Nop, - State_Im, - State_LoadSP, - State_StoreSP, - State_Emulate, - State_Load, - State_PushPC, - State_PushSP, - State_PopPC, - State_PopPCRel, - State_Not, - State_Flip, - State_PopSP, - State_Neqbranch, - State_Eq, - State_Loadb, - State_Mult, - State_Lessthan, - State_Lessthanorequal, - State_Ulessthanorequal, - State_Ulessthan, - State_Pushspadd, - State_Call, - State_Callpcrel, - State_Sub, - State_Break, - State_Storeb, - State_InsnFetch + Insn_AddTop, + Insn_Dup, + Insn_DupStackB, + Insn_Pop, + Insn_PopDown, + Insn_Add, + Insn_Or, + Insn_And, + Insn_Store, + Insn_AddSP, + Insn_Shift, + Insn_Nop, + Insn_Im, + Insn_LoadSP, + Insn_StoreSP, + Insn_Emulate, + Insn_Load, + Insn_PushSP, + Insn_PopPC, + Insn_PopPCrel, + Insn_Not, + Insn_Flip, + Insn_PopSP, + Insn_Neqbranch, + Insn_Eq, + Insn_Loadb, + Insn_Mult, + Insn_Lessthan, + Insn_Lessthanorequal, + Insn_Ulessthanorequal, + Insn_Ulessthan, + Insn_PushSPadd, + Insn_Call, + Insn_CallPCrel, + Insn_Sub, + Insn_Break, + Insn_Storeb, + Insn_InsnFetch ); type StateType is ( @@ -189,7 +189,6 @@ architecture behave of zpu_core is - signal begin_inst : std_logic; signal trace_opcode : std_logic_vector(7 downto 0); signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); @@ -235,7 +234,7 @@ begin variable spOffset : unsigned(4 downto 0); variable tSpOffset : unsigned(4 downto 0); variable nextPC : unsigned(maxAddrBitIncIO downto 0); - variable tNextState : InsnType; + variable tNextInsn : InsnType; variable tDecodedOpcode : InsnArray; variable tMultResult : unsigned(wordSize*2-1 downto 0); begin @@ -253,7 +252,7 @@ begin multA <= (others => '0'); multB <= (others => '0'); mem_writeMask <= (others => '1'); - elsif (clk'event and clk = '1') then + elsif rising_edge(clk) then -- we must multiply unconditionally to get pipelined multiplication tMultResult := multA * multB; multResult3 <= multResult2; @@ -366,99 +365,99 @@ begin opcode(i) <= tOpcode; if (tOpcode(7 downto 7) = OpCode_Im) then - tNextState := State_Im; + tNextInsn := Insn_Im; elsif (tOpcode(7 downto 5) = OpCode_StoreSP) then if tSpOffset = 0 then - tNextState := State_Pop; + tNextInsn := Insn_Pop; elsif tSpOffset = 1 then - tNextState := State_PopDown; + tNextInsn := Insn_PopDown; else - tNextState := State_StoreSP; + tNextInsn := Insn_StoreSP; end if; elsif (tOpcode(7 downto 5) = OpCode_LoadSP) then if tSpOffset = 0 then - tNextState := State_Dup; + tNextInsn := Insn_Dup; elsif tSpOffset = 1 then - tNextState := State_DupStackB; + tNextInsn := Insn_DupStackB; else - tNextState := State_LoadSP; + tNextInsn := Insn_LoadSP; end if; elsif (tOpcode(7 downto 5) = OpCode_Emulate) then - tNextState := State_Emulate; + tNextInsn := Insn_Emulate; if tOpcode(5 downto 0) = OpCode_Neqbranch then - tNextState := State_Neqbranch; + tNextInsn := Insn_Neqbranch; elsif tOpcode(5 downto 0) = OpCode_Eq then - tNextState := State_Eq; + tNextInsn := Insn_Eq; elsif tOpcode(5 downto 0) = OpCode_Lessthan then - tNextState := State_Lessthan; + tNextInsn := Insn_Lessthan; elsif tOpcode(5 downto 0) = OpCode_Lessthanorequal then - --tNextState :=State_Lessthanorequal; + --tNextInsn :=Insn_Lessthanorequal; elsif tOpcode(5 downto 0) = OpCode_Ulessthan then - tNextState := State_Ulessthan; + tNextInsn := Insn_Ulessthan; elsif tOpcode(5 downto 0) = OpCode_Ulessthanorequal then - --tNextState :=State_Ulessthanorequal; + --tNextInsn :=Insn_Ulessthanorequal; elsif tOpcode(5 downto 0) = OpCode_Loadb then - tNextState := State_Loadb; + tNextInsn := Insn_Loadb; elsif tOpcode(5 downto 0) = OpCode_Mult then - tNextState := State_Mult; + tNextInsn := Insn_Mult; elsif tOpcode(5 downto 0) = OpCode_Storeb then - tNextState := State_Storeb; + tNextInsn := Insn_Storeb; elsif tOpcode(5 downto 0) = OpCode_Pushspadd then - tNextState := State_Pushspadd; + tNextInsn := Insn_PushSPadd; elsif tOpcode(5 downto 0) = OpCode_Callpcrel then - tNextState := State_Callpcrel; + tNextInsn := Insn_CallPCrel; elsif tOpcode(5 downto 0) = OpCode_Call then - --tNextState :=State_Call; + --tNextInsn :=Insn_Call; elsif tOpcode(5 downto 0) = OpCode_Sub then - tNextState := State_Sub; + tNextInsn := Insn_Sub; elsif tOpcode(5 downto 0) = OpCode_PopPCRel then - --tNextState :=State_PopPCRel; + --tNextInsn :=Insn_PopPCrel; end if; elsif (tOpcode(7 downto 4) = OpCode_AddSP) then if tSpOffset = 0 then - tNextState := State_Shift; + tNextInsn := Insn_Shift; elsif tSpOffset = 1 then - tNextState := State_AddTop; + tNextInsn := Insn_AddTop; else - tNextState := State_AddSP; + tNextInsn := Insn_AddSP; end if; else case tOpcode(3 downto 0) is when OpCode_Nop => - tNextState := State_Nop; + tNextInsn := Insn_Nop; when OpCode_PushSP => - tNextState := State_PushSP; + tNextInsn := Insn_PushSP; when OpCode_PopPC => - tNextState := State_PopPC; + tNextInsn := Insn_PopPC; when OpCode_Add => - tNextState := State_Add; + tNextInsn := Insn_Add; when OpCode_Or => - tNextState := State_Or; + tNextInsn := Insn_Or; when OpCode_And => - tNextState := State_And; + tNextInsn := Insn_And; when OpCode_Load => - tNextState := State_Load; + tNextInsn := Insn_Load; when OpCode_Not => - tNextState := State_Not; + tNextInsn := Insn_Not; when OpCode_Flip => - tNextState := State_Flip; + tNextInsn := Insn_Flip; when OpCode_Store => - tNextState := State_Store; + tNextInsn := Insn_Store; when OpCode_PopSP => - tNextState := State_PopSP; + tNextInsn := Insn_PopSP; when others => - tNextState := State_Break; + tNextInsn := Insn_Break; end case; -- tOpcode(3 downto 0) end if; -- tOpcode - tDecodedOpcode(i) := tNextState; + tDecodedOpcode(i) := tNextInsn; end loop; -- 0 to wordBytes-1 insn <= tDecodedOpcode(to_integer(pc(byteBits-1 downto 0))); -- once we wrap, we need to fetch - tDecodedOpcode(0) := State_InsnFetch; + tDecodedOpcode(0) := Insn_InsnFetch; decodedOpcode <= tDecodedOpcode; state <= State_Execute; @@ -468,7 +467,7 @@ begin -- Each instruction must: -- -- 1. set idim_flag - -- 2. increase pc if applicable + -- 2. increase PC if applicable -- 3. set next state if appliable -- 4. do it's operation @@ -477,10 +476,10 @@ begin case insn is - when State_InsnFetch => + when Insn_InsnFetch => state <= State_Fetch; - when State_Im => + when Insn_Im => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '1'; @@ -502,7 +501,7 @@ begin end if; -- idim_flag end if; -- in_mem_busy - when State_StoreSP => + when Insn_StoreSP => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -516,7 +515,7 @@ begin end if; - when State_LoadSP => + when Insn_LoadSP => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -528,7 +527,7 @@ begin mem_write <= std_logic_vector(stackB); end if; - when State_Emulate => + when Insn_Emulate => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -548,7 +547,7 @@ begin state <= State_Fetch; end if; -- in_mem_busy - when State_Callpcrel => + when Insn_CallPCrel => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -559,7 +558,7 @@ begin state <= State_Fetch; end if; - when State_Call => + when Insn_Call => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -569,7 +568,7 @@ begin state <= State_Fetch; end if; - when State_AddSP => + when Insn_AddSP => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -579,7 +578,7 @@ begin mem_addr <= std_logic_vector(sp+spOffset); end if; - when State_PushSP => + when Insn_PushSP => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -594,7 +593,7 @@ begin mem_write <= std_logic_vector(stackB); end if; - when State_PopPC => + when Insn_PopPC => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -607,7 +606,7 @@ begin state <= State_Resync; end if; - when State_PopPCRel => + when Insn_PopPCrel => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -620,7 +619,7 @@ begin state <= State_Resync; end if; - when State_Add => + when Insn_Add => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -632,7 +631,7 @@ begin state <= State_Popped; end if; - when State_Sub => + when Insn_Sub => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -640,7 +639,7 @@ begin state <= State_BinaryOpResult; end if; - when State_Pop => + when Insn_Pop => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -651,7 +650,7 @@ begin state <= State_Popped; end if; - when State_PopDown => + when Insn_PopDown => if in_mem_busy = '0' then -- PopDown leaves top of stack unchanged begin_inst <= '1'; @@ -662,7 +661,7 @@ begin state <= State_Popped; end if; - when State_Or => + when Insn_Or => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -673,7 +672,7 @@ begin state <= State_Popped; end if; - when State_And => + when Insn_And => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -685,7 +684,7 @@ begin state <= State_Popped; end if; - when State_Eq => + when Insn_Eq => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -697,7 +696,7 @@ begin state <= State_BinaryOpResult; end if; - when State_Ulessthan => + when Insn_Ulessthan => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -709,7 +708,7 @@ begin state <= State_BinaryOpResult; end if; - when State_Ulessthanorequal => + when Insn_Ulessthanorequal => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -721,7 +720,7 @@ begin state <= State_BinaryOpResult; end if; - when State_Lessthan => + when Insn_Lessthan => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -733,7 +732,7 @@ begin state <= State_BinaryOpResult; end if; - when State_Lessthanorequal => + when Insn_Lessthanorequal => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -745,7 +744,7 @@ begin state <= State_BinaryOpResult; end if; - when State_Load => + when Insn_Load => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -755,7 +754,7 @@ begin mem_readEnable <= '1'; end if; - when State_Dup => + when Insn_Dup => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -768,7 +767,7 @@ begin mem_writeEnable <= '1'; end if; - when State_DupStackB => + when Insn_DupStackB => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -782,7 +781,7 @@ begin mem_writeEnable <= '1'; end if; - when State_Store => + when Insn_Store => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -794,7 +793,7 @@ begin state <= State_Resync; end if; - when State_PopSP => + when Insn_PopSP => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -807,19 +806,19 @@ begin state <= State_Resync; end if; - when State_Nop => + when Insn_Nop => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; - when State_Not => + when Insn_Not => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; - stackA <= not stackA; + stackA <= not stackA; - when State_Flip => + when Insn_Flip => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; @@ -828,14 +827,14 @@ begin stackA(i) <= stackA(wordSize-1-i); end loop; - when State_AddTop => + when Insn_AddTop => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; - stackA <= stackA + stackB; + stackA <= stackA + stackB; - when State_Shift => + when Insn_Shift => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; @@ -843,7 +842,7 @@ begin stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); stackA(0) <= '0'; - when State_Pushspadd => + when Insn_PushSPadd => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; @@ -851,7 +850,7 @@ begin stackA <= (others => '0'); stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; - when State_Neqbranch => + when Insn_Neqbranch => -- branches are almost always taken as they form loops begin_inst <= '1'; idim_flag <= '0'; @@ -864,7 +863,7 @@ begin -- need to fetch stack again. state <= State_Resync; - when State_Mult => + when Insn_Mult => begin_inst <= '1'; idim_flag <= '0'; @@ -872,11 +871,11 @@ begin multB <= stackB; state <= State_Mult2; - when State_Break => + when Insn_Break => report "Break instruction encountered" severity failure; break <= '1'; - when State_Loadb => + when Insn_Loadb => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; @@ -886,7 +885,7 @@ begin mem_readEnable <= '1'; end if; - when State_Storeb => + when Insn_Storeb => if in_mem_busy = '0' then begin_inst <= '1'; idim_flag <= '0'; -- cgit v1.1