From f2b214b0dff95d6bb79cbb5b6ff5ba9d90f655c9 Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 2 Jan 2008 21:52:27 +0000 Subject: Initial import from www.ecosforge.net --- zpu/hdl/zpu4/src/timer.vhd | 61 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 zpu/hdl/zpu4/src/timer.vhd (limited to 'zpu/hdl/zpu4/src/timer.vhd') diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd new file mode 100644 index 0000000..60c8fe2 --- /dev/null +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -0,0 +1,61 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); +end timer; + + +architecture behave of timer is + +signal sample : std_logic; +signal reset : std_logic; + + +signal cnt : std_logic_vector(63 downto 0); +signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + elsif (clk'event and clk = '1') then + cnt <= cnt + 1; + if sample = '1' then +-- report "sampling" severity failure; + cnt_smp <= cnt; + end if; + end if; + end process; + + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end behave; + -- cgit v1.1 From d09fa3de9df02a66c5084623076ac3e167b58274 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 22 Apr 2008 05:52:16 +0000 Subject: * zpu/hdl/example_ghdl/ghdl_import.sh, zpu/hdl/example_ghdl/ghdl_make.sh, zpu/hdl/example_ghdl/ghdl_options.sh, zpu/hdl/example_ghdl/README: GHDL example * zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh: testcase for GHDL * zpu/hdl/zpu4/src/dmipstrace_ghdl.sh: testcase for GHDL * zpu/hdl/zpu4/src/simzpu_medium_ghdl.sh: testcase for GHDL * zpu/hdl/example/helloworld.vhd, zpu/hdl/zpu4/src/bram_dmips.vhd, zpu/hdl/zpu4/src/dmipssmalltrace_ghdl.sh, zpu/hdl/zpu4/src/dram_dmips.vhd, zpu/hdl/zpu4/src/dram_hello.vhd, zpu/hdl/zpu4/src/io.vhd, zpu/hdl/zpu4/src/sim_fpga_top.vhd, zpu/hdl/zpu4/src/sim_small_fpga_top.vhd, zpu/hdl/zpu4/src/timer.vhd, zpu/hdl/zpu4/src/trace.vhd, zpu/hdl/zpu4/src/zpu_config_trace.vhd, zpu/hdl/zpu4/src/zpu_core_small.vhd, zpu/hdl/zpu4/src/zpu_core.vhd, zpu/hdl/zpu4/src/zpupkg.vhd: conversion to numeric_std --- zpu/hdl/zpu4/src/timer.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'zpu/hdl/zpu4/src/timer.vhd') diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd index 60c8fe2..be1dbb8 100644 --- a/zpu/hdl/zpu4/src/timer.vhd +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -1,6 +1,6 @@ library ieee; use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; entity timer is port( @@ -19,7 +19,7 @@ signal sample : std_logic; signal reset : std_logic; -signal cnt : std_logic_vector(63 downto 0); +signal cnt : unsigned(63 downto 0); signal cnt_smp : std_logic_vector(63 downto 0); begin @@ -36,7 +36,7 @@ begin cnt <= cnt + 1; if sample = '1' then -- report "sampling" severity failure; - cnt_smp <= cnt; + cnt_smp <= std_logic_vector(cnt); end if; end if; end process; -- cgit v1.1 From 04772b6a0bbe7017f5f7b44cfa203c3f7efbff64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 1 Mar 2011 20:52:55 +0100 Subject: whitespace fixes: use fromdos on all .vhd files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- zpu/hdl/zpu4/src/timer.vhd | 122 ++++++++++++++++++++++----------------------- 1 file changed, 61 insertions(+), 61 deletions(-) (limited to 'zpu/hdl/zpu4/src/timer.vhd') diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd index be1dbb8..c60c172 100644 --- a/zpu/hdl/zpu4/src/timer.vhd +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -1,61 +1,61 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity timer is - port( - clk : in std_logic; - areset : in std_logic; - we : in std_logic; - din : in std_logic_vector(7 downto 0); - adr : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(7 downto 0)); -end timer; - - -architecture behave of timer is - -signal sample : std_logic; -signal reset : std_logic; - - -signal cnt : unsigned(63 downto 0); -signal cnt_smp : std_logic_vector(63 downto 0); - -begin - - reset <= '1' when (we = '1' and din(0) = '1') else '0'; - sample <= '1' when (we = '1' and din(1) = '1') else '0'; - - process(clk, areset) -- Carry generation - begin - if areset = '1' then - cnt <= (others => '0'); - cnt_smp <= (others => '0'); - elsif (clk'event and clk = '1') then - cnt <= cnt + 1; - if sample = '1' then --- report "sampling" severity failure; - cnt_smp <= std_logic_vector(cnt); - end if; - end if; - end process; - - - process(cnt_smp, adr) - begin - case adr is - when "000" => dout <= cnt_smp(7 downto 0); - when "001" => dout <= cnt_smp(15 downto 8); - when "010" => dout <= cnt_smp(23 downto 16); - when "011" => dout <= cnt_smp(31 downto 24); - when "100" => dout <= cnt_smp(39 downto 32); - when "101" => dout <= cnt_smp(47 downto 40); - when "110" => dout <= cnt_smp(55 downto 48); - when others => dout <= cnt_smp(63 downto 56); - end case; - end process; - - -end behave; - +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0)); +end timer; + + +architecture behave of timer is + +signal sample : std_logic; +signal reset : std_logic; + + +signal cnt : unsigned(63 downto 0); +signal cnt_smp : std_logic_vector(63 downto 0); + +begin + + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + elsif (clk'event and clk = '1') then + cnt <= cnt + 1; + if sample = '1' then +-- report "sampling" severity failure; + cnt_smp <= std_logic_vector(cnt); + end if; + end if; + end process; + + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end behave; + -- cgit v1.1 From ec177759929085f161b9a5c7c82016406d8867cb Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Tue, 16 Aug 2011 23:43:12 +0200 Subject: beautify indentation --- zpu/hdl/zpu4/src/timer.vhd | 102 ++++++++++++++++++++++----------------------- 1 file changed, 51 insertions(+), 51 deletions(-) (limited to 'zpu/hdl/zpu4/src/timer.vhd') diff --git a/zpu/hdl/zpu4/src/timer.vhd b/zpu/hdl/zpu4/src/timer.vhd index c60c172..d6d9358 100644 --- a/zpu/hdl/zpu4/src/timer.vhd +++ b/zpu/hdl/zpu4/src/timer.vhd @@ -1,61 +1,61 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; - + entity timer is - port( - clk : in std_logic; - areset : in std_logic; - we : in std_logic; - din : in std_logic_vector(7 downto 0); - adr : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(7 downto 0)); -end timer; - - -architecture behave of timer is + port( + clk : in std_logic; + areset : in std_logic; + we : in std_logic; + din : in std_logic_vector(7 downto 0); + adr : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(7 downto 0) + ); +end entity timer; -signal sample : std_logic; -signal reset : std_logic; +architecture behave of timer is -signal cnt : unsigned(63 downto 0); -signal cnt_smp : std_logic_vector(63 downto 0); + signal sample : std_logic; + signal reset : std_logic; + -- + signal cnt : unsigned(63 downto 0); + signal cnt_smp : std_logic_vector(63 downto 0); begin - reset <= '1' when (we = '1' and din(0) = '1') else '0'; - sample <= '1' when (we = '1' and din(1) = '1') else '0'; - - process(clk, areset) -- Carry generation - begin - if areset = '1' then - cnt <= (others => '0'); - cnt_smp <= (others => '0'); - elsif (clk'event and clk = '1') then - cnt <= cnt + 1; - if sample = '1' then --- report "sampling" severity failure; - cnt_smp <= std_logic_vector(cnt); - end if; - end if; - end process; - - - process(cnt_smp, adr) - begin - case adr is - when "000" => dout <= cnt_smp(7 downto 0); - when "001" => dout <= cnt_smp(15 downto 8); - when "010" => dout <= cnt_smp(23 downto 16); - when "011" => dout <= cnt_smp(31 downto 24); - when "100" => dout <= cnt_smp(39 downto 32); - when "101" => dout <= cnt_smp(47 downto 40); - when "110" => dout <= cnt_smp(55 downto 48); - when others => dout <= cnt_smp(63 downto 56); - end case; - end process; - - -end behave; - + reset <= '1' when (we = '1' and din(0) = '1') else '0'; + sample <= '1' when (we = '1' and din(1) = '1') else '0'; + + process(clk, areset) -- Carry generation + begin + if areset = '1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + elsif rising_edge(clk) then + cnt <= cnt + 1; + if sample = '1' then +-- report "sampling" severity failure; + cnt_smp <= std_logic_vector(cnt); + end if; + end if; + end process; + + + process(cnt_smp, adr) + begin + case adr is + when "000" => dout <= cnt_smp(7 downto 0); + when "001" => dout <= cnt_smp(15 downto 8); + when "010" => dout <= cnt_smp(23 downto 16); + when "011" => dout <= cnt_smp(31 downto 24); + when "100" => dout <= cnt_smp(39 downto 32); + when "101" => dout <= cnt_smp(47 downto 40); + when "110" => dout <= cnt_smp(55 downto 48); + when others => dout <= cnt_smp(63 downto 56); + end case; + end process; + + +end architecture behave; + -- cgit v1.1