From 6647b91cf267e7e155c95c6adbcfbc43f083356b Mon Sep 17 00:00:00 2001
From: oharboe <oharboe>
Date: Tue, 17 Jun 2008 22:09:13 +0000
Subject: 	* io.vhd: fix address comparsion and added numerous outputs 
 during simulation to make things a bit easier 	* zpu_config.vhd: do not use
 hardcoded startSp, allows more easily 	tinkering w/RAM size

---
 zpu/hdl/zpu4/src/io.vhd | 35 ++++++++++++++++++++++-------------
 1 file changed, 22 insertions(+), 13 deletions(-)

(limited to 'zpu/hdl/zpu4/src/io.vhd')

diff --git a/zpu/hdl/zpu4/src/io.vhd b/zpu/hdl/zpu4/src/io.vhd
index 9e65929..f71f51d 100644
--- a/zpu/hdl/zpu4/src/io.vhd
+++ b/zpu/hdl/zpu4/src/io.vhd
@@ -37,6 +37,7 @@ signal timer_we : std_logic;
 signal serving : std_logic;
 
 file 		l_file		: TEXT open write_mode is log_file;
+constant lowAddrBits: std_logic_vector(minAddrBit-1 downto 0) := (others=>'0');
 
 begin
 
@@ -54,42 +55,50 @@ begin
 	
 	process(areset, clk)
 	begin
+		taddr := (others => '0');
+		taddr(maxAddrBit downto minAddrBit) := addr;
+
 		if (areset = '1') then
 --			timer_we <= '0';
 		elsif (clk'event and clk = '1') then
 --			timer_we <= '0';
 			if writeEnable = '1' then
-				-- external interface (fixed address)
-				--<JK> extend compare to avoid waring messages
-				if ("000" & addr)=x"2028003" then
+				-- external interface (fixed address)
+				--<JK> extend compare to avoid waring messages
+				if ("1" & addr & lowAddrBits)=x"80a000c" then
+					report "Write to UART[0]" & " :0x" & hstr(write);
 					-- Write to UART
 					-- report "" & character'image(conv_integer(memBint)) severity note;
 				    print(l_file, character'val(to_integer(unsigned(write))));
 				elsif addr(12)='1' then
+					report "Write to TIMER" & " :0x" & hstr(write);
 --				    report "xxx" severity failure;
 -- 					timer_we <= '1';
 				else
 					print(l_file, character'val(to_integer(unsigned(write))));
-					-- report "Illegal IO write" severity warning;
+					report "Illegal IO write @" & "0x" & hstr(taddr) severity warning;
 				end if;
 				
 			end if;
 			read <= (others => '0');
 			if (readEnable = '1') then
-				--<JK> extend compare to avoid waring messages
-				if ("000" & addr)=x"0001001" then
-					read <= (0=>'1', others => '0'); -- recieve empty
+				--<JK> extend compare to avoid waring messages
+				if ("1" & addr & lowAddrBits)=x"80a000c" then
+					report "Read UART[0]";
+					read(8) <= '0'; -- output fifo not full
+					read(9) <= '1'; -- receiver not empty
+				elsif ("1" & addr & lowAddrBits)=x"80a0010" then
+					report "Read UART[1]";
+					read(8) <= '1'; -- receiver not empty
+					read(7 downto 0) <= (others => '0');
  				elsif addr(12)='1' then
+					report "Read TIMER";
  					read(7 downto 0) <= timer_read;
  				elsif addr(11)='1' then
+					report "Read ZPU Freq";
  					read(7 downto 0) <= ZPU_Frequency;
-				--<JK> extend compare to avoid waring messages
-				elsif ("000" & addr)=x"2028003" then
-					read <= (others => '0');
 				else
-					read <= (others => '0');
-					read(8) <= '1';
-					-- report "Illegal IO read" severity warning;
+					report "Illegal IO read @" & "0x" & hstr(taddr) severity warning;
 				end if;
 			end if;
 		end if;
-- 
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