From 974f0707def69428579ee4b9d21bf3a920de8938 Mon Sep 17 00:00:00 2001 From: oharboe Date: Mon, 8 Sep 2008 15:05:26 +0000 Subject: 2008-09-08 Salvador Eduardo Tropea * zpu/hdl/zealot: a complete ZPU implementation cleaned up and with a UART. --- zpu/hdl/zealot/0README.txt | 152 + zpu/hdl/zealot/BSD | 20 + zpu/hdl/zealot/GPL_V2 | 341 ++ zpu/hdl/zealot/devices/br_gen.vhdl | 91 + zpu/hdl/zealot/devices/phi_io.vhdl | 209 ++ zpu/hdl/zealot/devices/rx_unit.vhdl | 108 + zpu/hdl/zealot/devices/timer.vhdl | 91 + zpu/hdl/zealot/devices/trace.vhdl | 258 ++ zpu/hdl/zealot/devices/tx_unit.vhdl | 109 + zpu/hdl/zealot/devices/txt_util.vhdl | 541 +++ zpu/hdl/zealot/fpga/dmips_med1.vhdl | 115 + zpu/hdl/zealot/fpga/hello_med1.vhdl | 115 + zpu/hdl/zealot/helpers/zpu_med1.vhdl | 170 + zpu/hdl/zealot/roms/dmips_bram.vhdl | 4462 +++++++++++++++++++++++++ zpu/hdl/zealot/roms/hello_bram.vhdl | 3056 +++++++++++++++++ zpu/hdl/zealot/roms/rom_pkg.vhdl | 80 + zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl | 129 + zpu/hdl/zealot/zpu_medium.vhdl | 948 ++++++ zpu/hdl/zealot/zpu_pkg.vhdl | 270 ++ 19 files changed, 11265 insertions(+) create mode 100644 zpu/hdl/zealot/0README.txt create mode 100644 zpu/hdl/zealot/BSD create mode 100644 zpu/hdl/zealot/GPL_V2 create mode 100644 zpu/hdl/zealot/devices/br_gen.vhdl create mode 100644 zpu/hdl/zealot/devices/phi_io.vhdl create mode 100644 zpu/hdl/zealot/devices/rx_unit.vhdl create mode 100644 zpu/hdl/zealot/devices/timer.vhdl create mode 100644 zpu/hdl/zealot/devices/trace.vhdl create mode 100644 zpu/hdl/zealot/devices/tx_unit.vhdl create mode 100644 zpu/hdl/zealot/devices/txt_util.vhdl create mode 100644 zpu/hdl/zealot/fpga/dmips_med1.vhdl create mode 100644 zpu/hdl/zealot/fpga/hello_med1.vhdl create mode 100644 zpu/hdl/zealot/helpers/zpu_med1.vhdl create mode 100644 zpu/hdl/zealot/roms/dmips_bram.vhdl create mode 100644 zpu/hdl/zealot/roms/hello_bram.vhdl create mode 100644 zpu/hdl/zealot/roms/rom_pkg.vhdl create mode 100644 zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl create mode 100644 zpu/hdl/zealot/zpu_medium.vhdl create mode 100644 zpu/hdl/zealot/zpu_pkg.vhdl (limited to 'zpu/hdl/zealot') diff --git a/zpu/hdl/zealot/0README.txt b/zpu/hdl/zealot/0README.txt new file mode 100644 index 0000000..364806c --- /dev/null +++ b/zpu/hdl/zealot/0README.txt @@ -0,0 +1,152 @@ +This is a test release of the ZPU. +ZPU is a 32 bits stack CPU. This package contains a VHDL implementation +suitable for FPGAs. It was tested using a Xilinx Spartan 3 1500 FPGA. + +The author of the ZPU is Øyvind Harboe (oyvind.harboe zylin.com) and the +license is the BSD one. Portions of this package were developed by Salvador E. +Tropea (salvador inti.gob.ar) and others. Some portions are under the GPL +license. + +Øyvind also added a ZPU target to the gcc/gdb. + +For more information about the ZPU core please visit: +http://www.zylin.com/zpu.htm +http://www.opencores.org/projects.cgi/web/zpu/overview + +What are the files? +------------------- + +zpu_medium.vhdl +ZPU CPU, medium version. + +zpu_pkg.vhdl +Package containing the declarations for the ZPU library. + +devices/phi_io.vhdl +The very basic I/O peripherals needed for the standard C library. It includes a +timer (64 bits clock counter) and an UART (8N1 without FIFO). +This is known as the PHI I/O layout, this implementation isn't complete. Only +the above mentioned peripherals are available. + +devices/timer.vhdl +64 bits clock counter maped by the PHI I/O. + +devices/trace.vhdl +This is used for debug purposes. The ZPU have a debug port to connect this +module. It can generate an execution trace log during the simulation. + +devices/txt_util.vhdl +Useful text handling routines for the simulation. + +devices/br_gen.vhdl +Fixed baud rate generator for the UART. + +devices/rx_unit.vhdl +UART Rx module. + +devices/tx_unit.vhdl +UART Tx module. + +roms/rom_pkg.vhdl +Package containing the declarations for the memories used by the small and +medium ZPU. + +roms/dmips_bram.vhdl +A memory that maps to Xilinx BRAMs and contains the Dhrystone Benchmark, +Version 2.1 (Language: C). This memory can be connected to the ZPU for +simulation or hardware implementations. The code assumes a 50 MHz clock to +compute the benchmark. The minimum size for this block should be 32 kB. + +roms/hello_bram.vhdl +A memory that maps to Xilinx BRAMs and contains a simple "Hello World!" +program (C compiled). This memory can be connected to the ZPU for +simulation or hardware implementations. The minimum size for this block +should be 16 kB. + +helpers/zpu_med1.vhdl +This is a helper that connects a ZPU to its memory and the PHI I/O space. + +testbenches/dmips_med1_tb.vhdl +A simple testbench to simulate the ZPU (behavior). + +fpga/dmips_med1.vhdl +A wrapper to implement the ZPU in an FPGA. This example was designed for a +GR-XC3S board from Pender, but should be easily adapted to other boards. + + +ZPU library? +------------ + +The following files are part of a library I called ZPU: + +zpu_pkg.vhdl, zpu_medium.vhdl, txt_util.vhdl, timer.vhdl, rx_unit.vhdl, +tx_unit.vhdl, br_gen.vhdl, phi_io.vhdl and trace.vhdl. + +You should group them inside a library called zpu. This procedure is tool-chain +dependent. In the ISE tool you must add a library and them move these files to +the library. + +If you don't know how to do it with your tools you can just replace all the: + +library zpu; +use zpu.xxxxxx.all; + +code by: + +library work; +use work.xxxxxx.all; + + +Which files are needed for simulation? +-------------------------------------- + +You need all the files that compose the zpu library plus: +1) A memory containing a program, i.e.: +roms/rom_pkg.vhdl and roms/dmips_bram.vhdl +2) A testbench (including the memory and I/O interconnections): +aux/zpu_med1.vhdl and testbenches/dmips_med1_tb.vhdl + + +Which files are needed for synthesis? +------------------------------------- + +This is similar to simulation, but: +1) You should avoid trace.vhdl. +2) The top level should connect to the FPGA pins, replace dmips_med1_tb.vhdl +by fpga/dmips_med1.vhdl or fpga/hello_med1.vhdl + + +What resources are needed in the FPGA? +-------------------------------------- + +The DMIPS benchmarks needs aprox (Xilinx Spartan 3): + +Flip Flops: 498 +LUTs: 1877 +Slices: 1032 +BRAMs: 16 +Multipliers: 3 + +The hello world example needs less memory: + +Flip Flops: 496 +LUTs: 1872 +Slices: 1027 +BRAMs: 8 +Multipliers: 3 + +The board should contain an RS-232 transceiver. A push button (active when +pressed) is also used, for reset. + + +Ok, I synthetized it and put in the FPGA, what now? +--------------------------------------------------- + +Connect the RS-232 board output to a terminal (a PC). Setup the terminal for +115200 8N1 reception and press the reset push button. You should get the +program output. You can change the baudrate in the toplevel VHDL. + + +Please tell me if you succeed or failed! +Enjoy, Salvador E. Tropea + diff --git a/zpu/hdl/zealot/BSD b/zpu/hdl/zealot/BSD new file mode 100644 index 0000000..cca2a5c --- /dev/null +++ b/zpu/hdl/zealot/BSD @@ -0,0 +1,20 @@ +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. 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If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/zpu/hdl/zealot/devices/br_gen.vhdl b/zpu/hdl/zealot/devices/br_gen.vhdl new file mode 100644 index 0000000..d14440e --- /dev/null +++ b/zpu/hdl/zealot/devices/br_gen.vhdl @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------ +---- ---- +---- RS-232 baudrate generator ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This counter is a parametrizable clock divider. The count value is ---- +---- the generic parameter COUNT. It has a chip enable ce_i input. ---- +---- (will count only if CE is high). ---- +---- When it overflows, will emit a pulse on o_o. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Philippe Carton, philippe.carton2 libertysurf.fr ---- +---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2001-2003 Philippe Carton ---- +---- Copyright (c) 2005 Juan Pablo Daniel Borgna ---- +---- Copyright (c) 2005-2008 Salvador E. Tropea ---- +---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: BRGen(Behaviour) (Entity and architecture) ---- +---- File name: br_gen.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- Target FPGA: Spartan ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity BRGen is + generic( + COUNT : integer range 0 to 65535);-- Count revolution + port ( + clk_i : in std_logic; -- Clock + reset_i : in std_logic; -- Reset input + ce_i : in std_logic; -- Chip Enable + o_o : out std_logic); -- Output +end entity BRGen; + +architecture Behaviour of BRGen is + +begin + CountGen: + if COUNT/=1 generate + Counter: + process (clk_i) + variable cnt : integer range 0 to COUNT-1; + begin + if rising_edge(clk_i) then + o_o <= '0'; + if reset_i='1' then + cnt:=COUNT-1; + elsif ce_i='1' then + if cnt=0 then + o_o <= '1'; + cnt:=COUNT-1; + else + cnt:=cnt-1; + end if; -- cnt/=0 + end if; -- ce_i='1' + end if; -- rising_edge(clk_i) + end process Counter; + end generate CountGen; + + CountWire: + if COUNT=1 generate + o_o <= '0' when reset_i='1' else ce_i; + end generate CountWire; +end architecture Behaviour; -- Entity: BRGen + diff --git a/zpu/hdl/zealot/devices/phi_io.vhdl b/zpu/hdl/zealot/devices/phi_io.vhdl new file mode 100644 index 0000000..267ff54 --- /dev/null +++ b/zpu/hdl/zealot/devices/phi_io.vhdl @@ -0,0 +1,209 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Phi I/O ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is the minimum I/O devices ---- +---- assumed by the libc. They are a timer and an UART.@p ---- +---- Important! this is currently a simulation only model, no UART ---- +---- provided and it unconditionally generates a log. ---- +---- Important! not all peripherals implemented! ---- +---- Important! The enable signals assumes this is mapped @ 0x80A00xx. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPUPhiIO(Behave) (Entity and architecture) ---- +---- File name: phi_io.vhdl ---- +---- Note: None ---- +---- Limitations: Only for simulation. ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- std.textio ---- +---- zpu.zpupkg ---- +---- zpu.txt_util ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: N/A ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use std.textio.all; + +library zpu; +use zpu.zpupkg.all; +use zpu.UART.all; +use zpu.txt_util.all; + +entity ZPUPhiIO is + generic( + BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4 + ENA_LOG : boolean:=true; -- Enable log + LOG_FILE : string:="log.txt"); -- Name for the log file + port( + clk_i : in std_logic; -- System Clock + reset_i : in std_logic; -- Synchronous Reset + busy_o : out std_logic; -- I/O is busy + we_i : in std_logic; -- Write Enable + re_i : in std_logic; -- Read Enable + data_i : in unsigned(31 downto 0); + data_o : out unsigned(31 downto 0); + addr_i : in unsigned(2 downto 0); -- Address bits 4-2 + rs232_rx_i : in std_logic; -- UART Rx input + rs232_tx_o : out std_logic; -- UART Tx output + br_clk_i : in std_logic); -- UART base clock (enable) +end entity ZPUPhiIO; + + +architecture Behave of ZPUPhiIO is + constant LOW_BITS : unsigned(1 downto 0):=(others=>'0'); + constant TX_FULL : std_logic:='0'; + constant RX_EMPTY : std_logic:='1'; + + -- "000" 0x00 is CPU enable ... useful? + -- "001" 0x04 Unused + -- "010" 0x08 Unused + constant UART_TX : unsigned(2 downto 0):="011"; -- 0x0C + constant UART_RX : unsigned(2 downto 0):="100"; -- 0x10 + constant CNT_1 : unsigned(2 downto 0):="101"; -- 0x14 + constant CNT_2 : unsigned(2 downto 0):="110"; -- 0x18 + -- "111" 0x1C Unused + -- Unimplemented: Interrupt control and timer (not counter ...?) + + signal timer_read : unsigned(31 downto 0); + signal timer_we : std_logic; + signal is_timer : std_logic; + + -- UART + -- Rx + signal rx_br : std_logic; -- Rx timing + signal uart_read : std_logic; -- ZPU read the value + signal rx_avail : std_logic; -- Rx data available + signal rx_data : std_logic_vector(7 downto 0); -- Rx data + -- Tx + signal tx_br : std_logic; -- Tx timing + signal uart_write : std_logic; -- ZPU is writing + signal tx_busy : std_logic; -- Tx can't get a new value + + file l_file : text open write_mode is LOG_FILE; +begin + ----------- + -- Timer -- + ----------- + timerinst: Timer + port map( + clk_i => clk_i, reset_i => reset_i, we_i => timer_we, + data_i => data_i, addr_i => addr_i(1 downto 1), + data_o => timer_read); + + busy_o <= we_i or re_i; + is_timer <= '1' when addr_i=CNT_1 or addr_i=CNT_2 else '0'; -- 0x80A0014/8 + timer_we <= we_i and is_timer; + + ---------- + -- UART -- + ---------- + -- Rx section + rx_core : RxUnit + port map( + clk_i => clk_i, reset_i => reset_i, enable_i => rx_br, + read_i => uart_read, rxd_i => rs232_rx_i, rxav_o => rx_avail, + datao_o => rx_data); + uart_read <= '1' when re_i='1' and addr_i=UART_RX else '0'; + + -- Tx section + tx_core : TxUnit + port map( + clk_i => clk_i, reset_i => reset_i, enable_i => tx_br, + load_i => uart_write, txd_o => rs232_tx_o, busy_o => tx_busy, + datai_i => std_logic_vector(data_i(7 downto 0))); + uart_write <= '1' when we_i='1' and addr_i=UART_TX else '0'; + + -- Rx timing + rx_timer : BRGen + generic map(COUNT => BRDIVISOR) + port map( + clk_i => clk_i, reset_i => reset_i, ce_i => br_clk_i, o_o => rx_br); + + -- Tx timing + tx_timer : BRGen -- 4 Divider for Tx + generic map(COUNT => 4) + port map( + clk_i => clk_i, reset_i => reset_i, ce_i => rx_br, o_o => tx_br); + + do_io: + process(clk_i) + begin + if rising_edge(clk_i) then + if reset_i/='1' then + --synopsys translate off + if we_i='1' then + if addr_i=UART_TX and ENA_LOG then -- 0x80a000c + -- Write to UART + print("- Write to UART Tx: 0x" &hstr(data_i)&" ("& + character'val(to_integer(data_i) mod 256)&")"); + if to_integer(data_i)<256 then + print(l_file,character'val(to_integer(data_i))); + end if; + elsif is_timer='1' and ENA_LOG then + print("- Write to TIMER: 0x"&hstr(data_i)); + else + --print(l_file,character'val(to_integer(data_i))); + report "Illegal IO data_i=0x"&hstr(data_i)&" @0x"& + hstr(x"80a00"&"000"&addr_i&"00") severity warning; + end if; + end if; + --synopsys translate on + data_o <= (others => '0'); + if re_i='1' then + if addr_i=UART_TX then + if ENA_LOG then + print("- Read UART Tx"); + end if; + data_o(8) <= not(tx_busy); -- output fifo not full + elsif addr_i=UART_RX then + if ENA_LOG then + print("- Read UART Rx"); + end if; + data_o(8) <= rx_avail; -- receiver not empty + data_o(7 downto 0) <= unsigned(rx_data); + elsif is_timer='1' then + if ENA_LOG then + print("- Read TIMER: 0x"&hstr(timer_read)); + end if; + data_o <= timer_read; + else + report "Illegal IO data_o @0x"& + hstr(x"80a00"&"000"&addr_i&"00") severity warning; + end if; + end if; -- re_i='1' + end if; -- reset_i/='1' + end if; -- rising_edge(clk_i) + end process do_io; +end Behave; + diff --git a/zpu/hdl/zealot/devices/rx_unit.vhdl b/zpu/hdl/zealot/devices/rx_unit.vhdl new file mode 100644 index 0000000..e9b3251 --- /dev/null +++ b/zpu/hdl/zealot/devices/rx_unit.vhdl @@ -0,0 +1,108 @@ +------------------------------------------------------------------------------ +---- ---- +---- RS-232 simple Rx module ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- Implements a simple 8N1 rx module for RS-232. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Philippe Carton, philippe.carton2 libertysurf.fr ---- +---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2001-2003 Philippe Carton ---- +---- Copyright (c) 2005 Juan Pablo Daniel Borgna ---- +---- Copyright (c) 2005-2008 Salvador E. Tropea ---- +---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: RxUnit(Behaviour) (Entity and architecture) ---- +---- File name: rx_unit.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- Target FPGA: Spartan ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity RxUnit is + port( + clk_i : in std_logic; -- System clock signal + reset_i : in std_logic; -- Reset input (sync) + enable_i : in std_logic; -- Enable input (rate*4) + read_i : in std_logic; -- Received Byte Read + rxd_i : in std_logic; -- RS-232 data input + rxav_o : out std_logic; -- Byte available + datao_o : out std_logic_vector(7 downto 0)); -- Byte received +end entity RxUnit; + +architecture Behaviour of RxUnit is + signal r_r : std_logic_vector(7 downto 0); -- Receive register + signal bavail_r : std_logic:='0'; -- Byte received +begin + rxav_o <= bavail_r; + -- Rx Process + RxProc: + process (clk_i) + variable bitpos : integer range 0 to 10; -- Position of the bit in the frame + variable samplecnt : integer range 0 to 3; -- Count from 0 to 3 in each bit + begin + if rising_edge(clk_i) then + if reset_i='1' then + bavail_r <= '0'; + bitpos:=0; + else -- reset_i='0' + if read_i='1' then + bavail_r <= '0'; + end if; + if enable_i='1' then + case bitpos is + when 0 => -- idle + bavail_r <= '0'; + if rxd_i='0' then -- Start Bit + samplecnt:=0; + bitpos:=1; + end if; + when 10 => -- Stop Bit + bitpos:=0; -- next is idle + bavail_r <= '1'; -- Indicate byte received + datao_o <= r_r; -- Store received byte + when others => + if samplecnt=1 and bitpos>=2 then -- Sample RxD on 1 + r_r(bitpos-2) <= rxd_i; -- Deserialisation + end if; + if samplecnt=3 then -- Increment BitPos on 3 + bitpos:=bitpos+1; + end if; + end case; + if samplecnt=3 then + samplecnt:=0; + else + samplecnt:=samplecnt+1; + end if; + end if; -- enable_i='1' + end if; -- reset_i='0' + end if; -- rising_edge(clk_i) + end process RxProc; +end architecture Behaviour; + diff --git a/zpu/hdl/zealot/devices/timer.vhdl b/zpu/hdl/zealot/devices/timer.vhdl new file mode 100644 index 0000000..f485e4d --- /dev/null +++ b/zpu/hdl/zealot/devices/timer.vhdl @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------ +---- ---- +---- 64 bits clock counter ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a peripheral used by the PHI I/O layout. It just counts the ---- +---- elapsed number of clocks. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Timer(Behave) (Entity and architecture) ---- +---- File name: timer.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity Timer is + port( + clk_i : in std_logic; + reset_i : in std_logic; + we_i : in std_logic; + data_i : in unsigned(31 downto 0); + addr_i : in unsigned(0 downto 0); + data_o : out unsigned(31 downto 0)); +end entity Timer; + +architecture Behave of Timer is + signal sample : std_logic; + signal reset : std_logic; + + signal cnt : unsigned(63 downto 0); + signal cnt_smp : unsigned(63 downto 0); +begin + reset <= '1' when (we_i='1' and data_i(0)='1') else '0'; + sample <= '1' when (we_i='1' and data_i(1)='1') else '0'; + + -- Carry generation + do_timer: + process (clk_i) + begin + if rising_edge(clk_i) then + if reset_i='1' or reset='1' then + cnt <= (others => '0'); + cnt_smp <= (others => '0'); + else + cnt <= cnt+1; + if sample='1' then + -- report "sampling" severity failure; + cnt_smp <= cnt; + end if; + end if; -- else reset_i='1' + end if; -- rising_edge(clk_i) + end process do_timer; + + data_o <= cnt_smp(31 downto 0) when addr_i="0" else + cnt_smp(63 downto 32); +end architecture Behave; -- Entity: Timer + diff --git a/zpu/hdl/zealot/devices/trace.vhdl b/zpu/hdl/zealot/devices/trace.vhdl new file mode 100644 index 0000000..83d3782 --- /dev/null +++ b/zpu/hdl/zealot/devices/trace.vhdl @@ -0,0 +1,258 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Trace Module ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is a module to log an ---- +---- execution trace. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Trace(Behave) (Entity and architecture) ---- +---- File name: trace.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- std.textio ---- +---- zpu.zpupkg ---- +---- zpu.txt_util ---- +---- Target FPGA: N/A ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: N/A ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use std.textio.all; + +library zpu; +use zpu.zpupkg.all; +use zpu.txt_util.all; + +entity Trace is + generic( + LOG_FILE : string:="trace.txt"; -- Name of the trace file + ADDR_W : integer:=16; -- Address width + WORD_SIZE : integer:=32); -- 16/32 + port( + clk_i : in std_logic; + dbg_i : in zpu_dbgo_t; + stop_i : in std_logic; + busy_i : in std_logic + ); +end entity Trace; + +architecture Behave of Trace is + file l_file : text open write_mode is LOG_FILE; + signal counter : unsigned(63 downto 0); +begin + -- write data and control information to a file + receive_data: + process + variable l : line; + variable stk_min : unsigned(31 downto 0):=(others => '1'); + variable stk_ini : unsigned(31 downto 0); + variable first : boolean:=true; + variable sp_off : unsigned(4 downto 0); + variable idim : boolean:=false; + variable im_val : unsigned(31 downto 0):=(others => '0'); + begin + counter <= to_unsigned(1,64); + -- print header for the logfile + print(l_file,"#PC Opcode SP A=[SP] B=[SP+1] Clk Counter Assembler"); + print(l_file,"#---------------------------------------------------------------------------"); + print(l_file," "); + + wait until clk_i='1'; + wait until clk_i='0'; + + while true loop + counter <= counter+1; + if dbg_i.b_inst='1' then + write(l, "0x"&hstr(dbg_i.pc(ADDR_W-1 downto 0))& + " 0x"&hstr(dbg_i.opcode)& + " 0x"&hstr(dbg_i.sp)& + " 0x"&hstr(dbg_i.stk_a)& + " 0x"&hstr(dbg_i.stk_b)& + " 0x"&hstr(counter)&" "); + -------------------------- + -- Instruction Decoder -- + -------------------------- + sp_off(4):=not dbg_i.opcode(4); + sp_off(3 downto 0):=dbg_i.opcode(3 downto 0); + if dbg_i.opcode(7 downto 7)=OPCODE_IM then + if idim then + im_val(31 downto 7):=im_val(24 downto 0); + im_val(6 downto 0):=dbg_i.opcode(6 downto 0); + else + im_val:=unsigned(resize(signed(dbg_i.opcode(6 downto 0)),32)); + end if; + idim:=true; + write(l,"im 0x"&hstr(dbg_i.opcode(6 downto 0))&" ; 0x"&hstr(im_val)); + elsif dbg_i.opcode(7 downto 5)=OPCODE_STORESP then + if sp_off=0 then + write(l,string'("storesp 0 ; pop")); + elsif sp_off=1 then + write(l,string'("storesp 4 ; 1*4 = popdown")); + else + write(l,"storesp "&integer'image(to_integer(sp_off)*4)&" ; "& + integer'image(to_integer(sp_off))&"*4"); + end if; + elsif dbg_i.opcode(7 downto 5)=OPCODE_LOADSP then + if sp_off=0 then + write(l,string'("loadsp 0 ; dup")); + elsif sp_off=1 then + write(l,string'("loadsp 4 ; 1*4 = dupstkb")); + else + write(l,"loadsp "&integer'image(to_integer(sp_off)*4)&" ; "& + integer'image(to_integer(sp_off))&"*4"); + end if; + elsif dbg_i.opcode(7 downto 5)=OPCODE_EMULATE then + if dbg_i.opcode(5 downto 0)=OPCODE_EQ then + write(l,string'("eq")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADB then + write(l,string'("loadb")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQBRANCH then + write(l,string'("neqbranch")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHSPADD then + write(l,string'("pushspadd")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHAN then + write(l,string'("lessthan")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHAN then + write(l,string'("ulessthan")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_MULT then + write(l,string'("mult")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREB then + write(l,string'("storeb")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_CALLPCREL then + write(l,string'("callpcrel")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_SUB then + write(l,string'("sub")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then + write(l,string'("lessthanorequal")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then + write(l,string'("ulessthanorequal")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_CALL then + write(l,string'("call")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_POPPCREL then + write(l,string'("poppcrel")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LSHIFTRIGHT then + write(l,string'("lshiftright")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_LOADH then + write(l,string'("loadh")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_STOREH then + write(l,string'("storeh")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTLEFT then + write(l,string'("ashiftleft")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_ASHIFTRIGHT then + write(l,string'("ashiftright")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_NEQ then + write(l,string'("neq")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_NEG then + write(l,string'("neg")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_XOR then + write(l,string'("xor")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_DIV then + write(l,string'("div")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_MOD then + write(l,string'("mod")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_EQBRANCH then + write(l,string'("eqbranch")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_CONFIG then + write(l,string'("config")); + elsif dbg_i.opcode(5 downto 0)=OPCODE_PUSHPC then + write(l,string'("pushpc")); + else + write(l,integer'image(to_integer(dbg_i.opcode(5 downto 0)))& + " ; invalid emulated instruction"); + end if; + elsif dbg_i.opcode(7 downto 4)=OPCODE_ADDSP then + if sp_off=0 then + write(l,string'("addsp 0 ; shift")); + elsif sp_off=1 then + write(l,string'("addsp 4 ; 1*4 = addtop")); + else + write(l,"addsp "&integer'image(to_integer(sp_off)*4)&" ; "& + integer'image(to_integer(sp_off))&"*4"); + end if; + else -- OPCODE_SHORT + case dbg_i.opcode(3 downto 0) is + when OPCODE_BREAK => + write(l,string'("break")); + when OPCODE_PUSHSP => + write(l,string'("pushsp")); + when OPCODE_POPPC => + write(l,string'("poppc")); + when OPCODE_ADD => + write(l,string'("add")); + when OPCODE_OR => + write(l,string'("or")); + when OPCODE_AND => + write(l,string'("and")); + when OPCODE_LOAD => + write(l,string'("load")); + when OPCODE_NOT => + write(l,string'("not")); + when OPCODE_FLIP => + write(l,string'("flip")); + when OPCODE_STORE => + write(l,string'("store")); + when OPCODE_POPSP => + write(l,string'("popsp")); + when OPCODE_NOP => + write(l,string'("nop")); + when others => + write(l,integer'image(to_integer(dbg_i.opcode))& + " ; invalid instruction"); + end case; + end if; + if dbg_i.opcode(7 downto 7)/=OPCODE_IM then + idim:=false; + end if; + ----------------------------- + -- End Instruction Decoder -- + ----------------------------- + writeline(l_file,l); + if dbg_i.sp -- idle or stop bit + txd_r <= '1'; + if loaded_r='1' then -- start transmit. next is start bit + t_r <= tbuff_r; + loaded_r <= '0'; + bitpos:=1; + end if; + when 1 => -- Start bit + txd_r <= '0'; + bitpos:=2; + when others => + txd_r <= t_r(bitpos-2); -- Serialisation of t_r + bitpos:=bitpos+1; + end case; + if bitpos=10 then -- bit8. next is stop bit + bitpos:=0; + end if; + end if; -- enable_i='1' + end if; -- reset_i='0' + end if; -- rising_edge(clk_i) + end process TxProc; +end architecture Behaviour; diff --git a/zpu/hdl/zealot/devices/txt_util.vhdl b/zpu/hdl/zealot/devices/txt_util.vhdl new file mode 100644 index 0000000..862611c --- /dev/null +++ b/zpu/hdl/zealot/devices/txt_util.vhdl @@ -0,0 +1,541 @@ +------------------------------------------------------------------------------ +---- ---- +---- Text Utils ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- Utils to handle text. Used for the testbenches. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: txt_util (Package) ---- +---- File name: txt_util.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- std.textio ---- +---- Target FPGA: N/A ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use std.textio.all; + +library zpu; + +package txt_util is + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + function hstr(slv: unsigned) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + procedure str_write(file out_file: TEXT; + new_string: in string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); +end package txt_util; + + + + +package body txt_util is + -- prints text to the screen + procedure print(text: string) is + variable msg_line: line; + begin + --synopsys translate off + write(msg_line, text); + writeline(output, msg_line); + --synopsys translate on + end procedure print; + + -- prints text to the screen when active + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end procedure print; + + -- converts std_logic into a character + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end function chr; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1):=chr(sl); + return s; + end function str; + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r:=1; + for i in slv'range loop + result(r) := chr(slv(i)); + r:=r+1; + end loop; + return result; + end function str; + + + function str(b: boolean) return string is + begin + if b then + return "true"; + else + return "false"; + end if; + end function str; + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end function chr; + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + function str(int: integer; base: integer) return string is + variable temp : string(1 to 10); + variable num : integer; + variable abs_int : integer; + variable len : integer:=1; + variable power : integer:=1; + begin + -- bug fix for negative numbers + abs_int:=abs(int); + + num :=abs_int; + + while num>=base loop -- Determine how many + len:=len+1; -- characters required + num:=num/base; -- to represent the + end loop; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i):=chr(abs_int/power mod base); -- a string starting + power:=power*base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int<0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + end function str; + + -- convert integer to string, using base 10 + function str(int: integer) return string is + begin + return str(int, 10) ; + end function str; + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0):=(others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen:=(slv'left+1)/4; + if (slv'left+1) mod 4/=0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen-1) downto 0 loop + fourbit:=longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen-I):='0'; + when "0001" => hex(hexlen-I):='1'; + when "0010" => hex(hexlen-I):='2'; + when "0011" => hex(hexlen-I):='3'; + when "0100" => hex(hexlen-I):='4'; + when "0101" => hex(hexlen-I):='5'; + when "0110" => hex(hexlen-I):='6'; + when "0111" => hex(hexlen-I):='7'; + when "1000" => hex(hexlen-I):='8'; + when "1001" => hex(hexlen-I):='9'; + when "1010" => hex(hexlen-I):='A'; + when "1011" => hex(hexlen-I):='B'; + when "1100" => hex(hexlen-I):='C'; + when "1101" => hex(hexlen-I):='D'; + when "1110" => hex(hexlen-I):='E'; + when "1111" => hex(hexlen-I):='F'; + when "ZZZZ" => hex(hexlen-I):='z'; + when "UUUU" => hex(hexlen-I):='u'; + when "XXXX" => hex(hexlen-I):='x'; + when others => hex(hexlen-I):='?'; + end case; + end loop; + return hex(1 to hexlen); + end function hstr; + + function hstr(slv: unsigned) return string is + begin + return hstr(std_logic_vector(slv)); + end function hstr; + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + function to_upper(c: character) return character is + variable u: character; + begin + case c is + when 'a' => u:='A'; + when 'b' => u:='B'; + when 'c' => u:='C'; + when 'd' => u:='D'; + when 'e' => u:='E'; + when 'f' => u:='F'; + when 'g' => u:='G'; + when 'h' => u:='H'; + when 'i' => u:='I'; + when 'j' => u:='J'; + when 'k' => u:='K'; + when 'l' => u:='L'; + when 'm' => u:='M'; + when 'n' => u:='N'; + when 'o' => u:='O'; + when 'p' => u:='P'; + when 'q' => u:='Q'; + when 'r' => u:='R'; + when 's' => u:='S'; + when 't' => u:='T'; + when 'u' => u:='U'; + when 'v' => u:='V'; + when 'w' => u:='W'; + when 'x' => u:='X'; + when 'y' => u:='Y'; + when 'z' => u:='Z'; + when others => u:=c; + end case; + return u; + end function to_upper; + + + -- convert a character to lower case + function to_lower(c: character) return character is + variable l: character; + begin + case c is + when 'A' => l:='a'; + when 'B' => l:='b'; + when 'C' => l:='c'; + when 'D' => l:='d'; + when 'E' => l:='e'; + when 'F' => l:='f'; + when 'G' => l:='g'; + when 'H' => l:='h'; + when 'I' => l:='i'; + when 'J' => l:='j'; + when 'K' => l:='k'; + when 'L' => l:='l'; + when 'M' => l:='m'; + when 'N' => l:='n'; + when 'O' => l:='o'; + when 'P' => l:='p'; + when 'Q' => l:='q'; + when 'R' => l:='r'; + when 'S' => l:='s'; + when 'T' => l:='t'; + when 'U' => l:='u'; + when 'V' => l:='v'; + when 'W' => l:='w'; + when 'X' => l:='x'; + when 'Y' => l:='y'; + when 'Z' => l:='z'; + when others => l:=c; + end case; + return l; + end function to_lower; + + -- convert a string to upper case + function to_upper(s: string) return string is + variable uppercase: string (s'range); + begin + for i in s'range loop + uppercase(i):=to_upper(s(i)); + end loop; + return uppercase; + end to_upper; + + -- convert a string to lower case + function to_lower(s: string) return string is + variable lowercase: string (s'range); + begin + for i in s'range loop + lowercase(i):=to_lower(s(i)); + end loop; + return lowercase; + end to_lower; + + -- functions to convert strings into other types + + -- converts a character into a std_logic + + function to_std_logic(c: character) return std_logic is + variable sl : std_logic; + begin + case c is + when 'U' => + sl:='U'; + when 'X' => + sl:='X'; + when '0' => + sl:='0'; + when '1' => + sl:='1'; + when 'Z' => + sl:='Z'; + when 'W' => + sl:='W'; + when 'L' => + sl:='L'; + when 'H' => + sl:='H'; + when '-' => + sl:='-'; + when others => + sl:='X'; + end case; + return sl; + end function to_std_logic; + + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector is + variable slv : std_logic_vector(s'high-s'low downto 0); + variable k : integer; + begin + k:=s'high-s'low; + for i in s'range loop + slv(k):=to_std_logic(s(i)); + k :=k-1; + end loop; + return slv; + end function to_std_logic_vector; + + + ---------------- + -- file I/O -- + ---------------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string) is + variable l : line; + variable c : character; + variable is_string : boolean; + begin + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i):=' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l,c,is_string); + res_string(i):=c; + if not is_string then -- found end of line + exit; + end if; + end loop; + end procedure str_read; + + -- print string to a file + procedure print(file out_file: TEXT; + new_string: in string) is + variable l: line; + begin + write(l,new_string); + writeline(out_file,l); + end procedure print; + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character) is + variable l: line; + begin + write(l,char); + writeline(out_file,l); + end procedure print; + + -- appends contents of a string to a file until line feed occurs + -- (LF is considered to be the end of the string) + procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + for i in new_string'range loop + print(out_file,new_string(i)); + if new_string(i)=LF then -- end of string + exit; + end if; + end loop; + end str_write; +end package body txt_util; + diff --git a/zpu/hdl/zealot/fpga/dmips_med1.vhdl b/zpu/hdl/zealot/fpga/dmips_med1.vhdl new file mode 100644 index 0000000..9920c2c --- /dev/null +++ b/zpu/hdl/zealot/fpga/dmips_med1.vhdl @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ---- +---- 3 1500 Xilinx FPGA available in the GR-XC3S board from Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DMIPS_Med1(FPGA) (Entity and architecture) ---- +---- File name: dmips_med1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity DMIPS_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity DMIPS_Med1; + +architecture FPGA of DMIPS_Med1 is + component ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + end component ZPU_Med1; +begin + zpu : ZPU_Med1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open); +end architecture FPGA; -- Entity: DMIPS_Med1 + diff --git a/zpu/hdl/zealot/fpga/hello_med1.vhdl b/zpu/hdl/zealot/fpga/hello_med1.vhdl new file mode 100644 index 0000000..7356c72 --- /dev/null +++ b/zpu/hdl/zealot/fpga/hello_med1.vhdl @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium connection to the FPGA pins ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This module connects the ZPU_Med1 (zpu_med1.vhdl) core to a Spartan ---- +---- 3 1500 Xilinx FPGA available in the GR-XC3S board from Pender. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the GPL license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: Hello_Med1(FPGA) (Entity and architecture) ---- +---- File name: hello_med1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpu_pkg ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: N/A ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity Hello_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='0'; -- Fill value, I got better results with it + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=115200; -- RS-232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=14); -- 14 bits RAM space=16 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + + constant BRD_PB1_I : string:="D19"; -- SWITCH8==S2 + constant BRD_CLK1_I : string:="AA12"; -- 50 MHz clock + --constant BRD_CLK1_I : string:="AB12"; -- 40 MHz clock + -- UART: direct 1:1 cable + constant BRD_TX_O : string:="L4"; -- UART 1 (J1) TXD1 DB9 pin 2 + constant BRD_RX_I : string:="L3"; -- UART 1 (J1) RXD1 DB9 pin 3 + + ------------ + -- Pinout -- + ------------ + attribute LOC : string; + attribute IOSTANDARD : string; + constant IOSTD : string:="LVTTL"; + + attribute LOC of rst_i : signal is BRD_PB1_I; + attribute IOSTANDARD of rst_i : signal is IOSTD; + attribute LOC of clk_i : signal is BRD_CLK1_I; + attribute LOC of rs232_tx_o : signal is BRD_TX_O; + attribute IOSTANDARD of rs232_tx_o : signal is IOSTD; + attribute LOC of rs232_rx_i : signal is BRD_RX_I; + attribute IOSTANDARD of rs232_rx_i : signal is IOSTD; +end entity Hello_Med1; + +architecture FPGA of Hello_Med1 is + component ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + end component ZPU_Med1; +begin + zpu : ZPU_Med1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk_i, rst_i => rst_i, rs232_tx_o => rs232_tx_o, + rs232_rx_i => rs232_rx_i, dbg_o => open); +end architecture FPGA; -- Entity: Hello_Med1 + diff --git a/zpu/hdl/zealot/helpers/zpu_med1.vhdl b/zpu/hdl/zealot/helpers/zpu_med1.vhdl new file mode 100644 index 0000000..fb19e0c --- /dev/null +++ b/zpu/hdl/zealot/helpers/zpu_med1.vhdl @@ -0,0 +1,170 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium + PHI I/O + BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is a helper that joins the ---- +---- medium version, the PHI I/O basic layout and a program BRAM. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPU_Med1(Structural) (Entity and architecture) ---- +---- File name: zpu_med1.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- work.zpu_memory ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +-- RAM declaration +library work; +use work.zpu_memory.all; + +entity ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx +end entity ZPU_Med1; + +architecture Structural of ZPU_Med1 is + constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes + constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O + constant BRDIVISOR : positive:=CLK_FREQ*1e6/BRATE/4; + + -- I/O & memory (ZPU) + signal mem_busy : std_logic; + signal mem_read : unsigned(WORD_SIZE-1 downto 0); + signal mem_write : unsigned(WORD_SIZE-1 downto 0); + signal mem_addr : unsigned(ADDR_W-1 downto 0); + signal mem_we : std_logic; + signal mem_re : std_logic; + + -- Memory (SinglePort_RAM) + signal ram_busy : std_logic; + signal ram_read : unsigned(WORD_SIZE-1 downto 0); + signal ram_addr : unsigned(BRAM_W-1 downto BYTE_BITS); + signal ram_we : std_logic; + signal ram_re : std_logic; + signal ram_ready_r : std_logic:='0'; + + -- I/O (ZPU_IO) + signal io_busy : std_logic; + signal io_re : std_logic; + signal io_we : std_logic; + signal io_read : unsigned(WORD_SIZE-1 downto 0); + signal io_ready : std_logic; + signal io_reading_r : std_logic:='0'; + signal io_addr : unsigned(2 downto 0); +begin + memory: SinglePortRAM + generic map( + WORD_SIZE => WORD_SIZE, BYTE_BITS => BYTE_BITS, BRAM_W => BRAM_W) + port map( + clk_i => clk_i, + we_i => ram_we, re_i => ram_re, addr_i => ram_addr, + write_i => mem_write, read_o => ram_read, busy_o => ram_busy); + ram_addr <= mem_addr(BRAM_W-1 downto BYTE_BITS); + ram_we <= mem_we and not(mem_addr(IO_BIT)); + ram_re <= mem_re and not(mem_addr(IO_BIT)); + + -- I/O: Phi layout + io_map: ZPUPhiIO + generic map( + BRDIVISOR => BRDIVISOR, LOG_FILE => "zpu_med1_io.log") + port map( + clk_i => clk_i, reset_i => rst_i, busy_o => io_busy, we_i => io_we, + re_i => io_re, data_i => mem_write, data_o => io_read, + addr_i => io_addr, rs232_rx_i => rs232_rx_i, rs232_tx_o => rs232_tx_o, + br_clk_i => '1'); + io_addr <= mem_addr(4 downto 2); + -- Here we decode 0x8xxxx as I/O and not just 0x80A00xx + -- Note: We define the address space as 256 kB, so writing to 0x80A00xx + -- will be as wrting to 0x200xx and hence we decode it as I/O space. + io_we <= mem_we and mem_addr(IO_BIT); + io_re <= mem_re and mem_addr(IO_BIT); + io_ready <= (io_reading_r or io_re) and not io_busy; + + zpu : ZPUMediumCore + generic map( + WORD_SIZE => WORD_SIZE, ADDR_W => ADDR_W, MEM_W => BRAM_W, + D_CARE_VAL => D_CARE_VAL) + port map( + clk_i => clk_i, reset_i => rst_i, enable_i => '1', + break_o => break_o, dbg_o => dbg_o, + -- Memory + mem_busy_i => mem_busy, data_i => mem_read, data_o => mem_write, + addr_o => mem_addr, write_en_o => mem_we, read_en_o => mem_re); + mem_busy <= io_busy or ram_busy; + + -- Memory reads either come from IO or DRAM. We need to pick the right one. + memory_control: + process (ram_read, ram_ready_r, io_ready, io_read) + begin + mem_read <= (others => '0'); + if ram_ready_r='1' then + mem_read <= ram_read; + end if; + if io_ready='1' then + mem_read <= io_read; + end if; + end process memory_control; + + memory_control_sync: + process (clk_i) + begin + if rising_edge(clk_i) then + if rst_i='1' then + io_reading_r <= '0'; + ram_ready_r <= '0'; + else + io_reading_r <= io_busy or io_re; + ram_ready_r <= ram_re; + end if; + end if; + end process memory_control_sync; +end architecture Structural; -- Entity: ZPU_Med1 + diff --git a/zpu/hdl/zealot/roms/dmips_bram.vhdl b/zpu/hdl/zealot/roms/dmips_bram.vhdl new file mode 100644 index 0000000..977626c --- /dev/null +++ b/zpu/hdl/zealot/roms/dmips_bram.vhdl @@ -0,0 +1,4462 @@ +------------------------------------------------------------------------------ +---- ---- +---- Single Port RAM that maps to a Xilinx BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ---- +---- File name: rom_s.in.vhdl (template used) ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity SinglePortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + we_i : in std_logic; + re_i : in std_logic; + addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + write_i : in unsigned(WORD_SIZE-1 downto 0); + read_o : out unsigned(WORD_SIZE-1 downto 0); + busy_o : out std_logic); +end entity SinglePortRAM; + +architecture Xilinx of SinglePortRAM is + type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0); + signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS); + + signal ram : ram_type := +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80f8ec0c", + 3 => x"3a0b0b80", + 4 => x"e7ea0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80e8b72d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80f8", + 162 => x"d8738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88aa0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b80ce", + 171 => x"b62d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"80088408", + 177 => x"88087575", + 178 => x"0b0b80cf", + 179 => x"e82d5050", + 180 => x"80085688", + 181 => x"0c840c80", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"810b0b0b", + 209 => x"80f8e80c", + 210 => x"51040000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"00000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"83803f80", + 257 => x"e2953f04", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10101053", + 266 => x"51047381", + 267 => x"ff067383", + 268 => x"06098105", + 269 => x"83051010", + 270 => x"102b0772", + 271 => x"fc060c51", + 272 => x"51043c04", + 273 => x"72728072", + 274 => x"8106ff05", + 275 => x"09720605", + 276 => x"71105272", + 277 => x"0a100a53", + 278 => x"72ed3851", + 279 => x"51535104", + 280 => x"ff3d0d0b", + 281 => x"0b8188e0", + 282 => x"08527108", + 283 => x"70882a81", + 284 => x"32708106", + 285 => x"51515170", + 286 => x"f1387372", + 287 => x"0c833d0d", + 288 => x"0480f8e8", + 289 => x"08802ea4", + 290 => x"3880f8ec", + 291 => x"08822ebd", + 292 => x"38838080", + 293 => x"0b0b0b81", + 294 => x"88e00c82", + 295 => x"a0800b81", + 296 => x"88e40c82", + 297 => x"90800b81", + 298 => x"88e80c04", + 299 => x"f8808080", + 300 => x"a40b0b0b", + 301 => x"8188e00c", + 302 => x"f8808082", + 303 => x"800b8188", + 304 => x"e40cf880", + 305 => x"8084800b", + 306 => x"8188e80c", + 307 => x"0480c0a8", + 308 => x"808c0b0b", + 309 => x"0b8188e0", + 310 => x"0c80c0a8", + 311 => x"80940b81", + 312 => x"88e40c0b", + 313 => x"0b80eac8", + 314 => x"0b8188e8", + 315 => x"0c04f23d", + 316 => x"0d608188", + 317 => x"e408565d", + 318 => x"82750c80", + 319 => x"59805a80", + 320 => x"0b8f3d5d", + 321 => x"5b7a1010", + 322 => x"15700871", + 323 => x"08719f2c", + 324 => x"7e852b58", + 325 => x"55557d53", + 326 => x"59579d94", + 327 => x"3f7d7f7a", + 328 => x"72077c72", + 329 => x"07717160", + 330 => x"8105415f", + 331 => x"5d5b5957", + 332 => x"55817b27", + 333 => x"8f38767d", + 334 => x"0c77841e", + 335 => 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x"00004020", + 4107 => x"00004020", + 4108 => x"00004028", + 4109 => x"00004028", + 4110 => x"00004030", + 4111 => x"00004030", + 4112 => x"00004038", + 4113 => x"00004038", + 4114 => x"00004040", + 4115 => x"00004040", + 4116 => x"00004048", + 4117 => x"00004048", + 4118 => x"00004050", + 4119 => x"00004050", + 4120 => x"00004058", + 4121 => x"00004058", + 4122 => x"00004060", + 4123 => x"00004060", + 4124 => x"00004068", + 4125 => x"00004068", + 4126 => x"00004070", + 4127 => x"00004070", + 4128 => x"00004078", + 4129 => x"00004078", + 4130 => x"00004080", + 4131 => x"00004080", + 4132 => x"00004088", + 4133 => x"00004088", + 4134 => x"00004090", + 4135 => x"00004090", + 4136 => x"00004098", + 4137 => x"00004098", + 4138 => x"000040a0", + 4139 => x"000040a0", + 4140 => x"000040a8", + 4141 => x"000040a8", + 4142 => x"000040b0", + 4143 => x"000040b0", + 4144 => x"000040b8", + 4145 => x"000040b8", + 4146 => x"000040cc", + 4147 => x"00000000", + 4148 => x"00004334", + 4149 => x"00004390", + 4150 => x"000043ec", + 4151 => x"00000000", + 4152 => x"00000000", + 4153 => x"00000000", + 4154 => x"00000000", + 4155 => x"00000000", + 4156 => x"00000000", + 4157 => x"00000000", + 4158 => x"00000000", + 4159 => x"00000000", + 4160 => x"00003c48", + 4161 => x"00000000", + 4162 => x"00000000", + 4163 => x"00000000", + 4164 => x"00000000", + 4165 => x"00000000", + 4166 => x"00000000", + 4167 => x"00000000", + 4168 => x"00000000", + 4169 => x"00000000", + 4170 => x"00000000", + 4171 => x"00000000", + 4172 => x"00000000", + 4173 => x"00000000", + 4174 => x"00000000", + 4175 => x"00000000", + 4176 => x"00000000", + 4177 => x"00000000", + 4178 => x"00000000", + 4179 => x"00000000", + 4180 => x"00000000", + 4181 => x"00000000", + 4182 => x"00000000", + 4183 => x"00000000", + 4184 => x"00000000", + 4185 => x"00000000", + 4186 => x"00000000", + 4187 => x"00000000", + 4188 => x"00000000", + 4189 => x"00000001", + 4190 => x"330eabcd", + 4191 => x"1234e66d", + 4192 => x"deec0005", + 4193 => x"000b0000", + 4194 => x"00000000", + 4195 => x"00000000", + 4196 => x"00000000", + 4197 => x"00000000", + 4198 => x"00000000", + 4199 => x"00000000", + 4200 => x"00000000", + 4201 => x"00000000", + 4202 => x"00000000", + 4203 => x"00000000", + 4204 => x"00000000", + 4205 => x"00000000", + 4206 => x"00000000", + 4207 => x"00000000", + 4208 => x"00000000", + 4209 => x"00000000", + 4210 => x"00000000", + 4211 => x"00000000", + 4212 => x"00000000", + 4213 => x"00000000", + 4214 => x"00000000", + 4215 => x"00000000", + 4216 => x"00000000", + 4217 => x"00000000", + 4218 => x"00000000", + 4219 => x"00000000", + 4220 => x"00000000", + 4221 => x"00000000", + 4222 => x"00000000", + 4223 => x"00000000", + 4224 => x"00000000", + 4225 => x"00000000", + 4226 => x"00000000", + 4227 => x"00000000", + 4228 => x"00000000", + 4229 => x"00000000", + 4230 => x"00000000", + 4231 => x"00000000", + 4232 => x"00000000", + 4233 => x"00000000", + 4234 => x"00000000", + 4235 => x"00000000", + 4236 => x"00000000", + 4237 => x"00000000", + 4238 => x"00000000", + 4239 => x"00000000", + 4240 => x"00000000", + 4241 => x"00000000", + 4242 => x"00000000", + 4243 => x"00000000", + 4244 => x"00000000", + 4245 => x"00000000", + 4246 => x"00000000", + 4247 => x"00000000", + 4248 => x"00000000", + 4249 => x"00000000", + 4250 => x"00000000", + 4251 => x"00000000", + 4252 => x"00000000", + 4253 => x"00000000", + 4254 => x"00000000", + 4255 => x"00000000", + 4256 => x"00000000", + 4257 => x"00000000", + 4258 => x"00000000", + 4259 => x"00000000", + 4260 => x"00000000", + 4261 => x"00000000", + 4262 => x"00000000", + 4263 => x"00000000", + 4264 => x"00000000", + 4265 => x"00000000", + 4266 => x"00000000", + 4267 => x"00000000", + 4268 => x"00000000", + 4269 => x"00000000", + 4270 => x"00000000", + 4271 => x"00000000", + 4272 => x"00000000", + 4273 => x"00000000", + 4274 => x"00000000", + 4275 => x"00000000", + 4276 => x"00000000", + 4277 => x"00000000", + 4278 => x"00000000", + 4279 => x"00000000", + 4280 => x"00000000", + 4281 => x"00000000", + 4282 => x"00000000", + 4283 => x"00000000", + 4284 => x"00000000", + 4285 => x"00000000", + 4286 => x"00000000", + 4287 => x"00000000", + 4288 => x"00000000", + 4289 => x"00000000", + 4290 => x"00000000", + 4291 => x"00000000", + 4292 => x"00000000", + 4293 => x"00000000", + 4294 => x"00000000", + 4295 => x"00000000", + 4296 => x"00000000", + 4297 => x"00000000", + 4298 => x"00000000", + 4299 => x"00000000", + 4300 => x"00000000", + 4301 => x"00000000", + 4302 => x"00000000", + 4303 => x"00000000", + 4304 => x"00000000", + 4305 => x"00000000", + 4306 => x"00000000", + 4307 => x"00000000", + 4308 => x"00000000", + 4309 => x"00000000", + 4310 => x"00000000", + 4311 => x"00000000", + 4312 => x"00000000", + 4313 => x"00000000", + 4314 => x"00000000", + 4315 => x"00000000", + 4316 => x"00000000", + 4317 => x"00000000", + 4318 => x"00000000", + 4319 => x"00000000", + 4320 => x"00000000", + 4321 => x"00000000", + 4322 => x"00000000", + 4323 => x"00000000", + 4324 => x"00000000", + 4325 => x"00000000", + 4326 => x"00000000", + 4327 => x"00000000", + 4328 => x"00000000", + 4329 => x"00000000", + 4330 => x"00000000", + 4331 => x"00000000", + 4332 => x"00000000", + 4333 => x"00000000", + 4334 => x"00000000", + 4335 => x"00000000", + 4336 => x"00000000", + 4337 => x"00000000", + 4338 => x"00000000", + 4339 => x"00000000", + 4340 => x"00000000", + 4341 => x"00000000", + 4342 => x"00000000", + 4343 => x"00000000", + 4344 => x"00000000", + 4345 => x"00000000", + 4346 => x"00000000", + 4347 => x"00000000", + 4348 => x"00000000", + 4349 => x"00000000", + 4350 => x"00000000", + 4351 => x"00000000", + 4352 => x"00000000", + 4353 => x"00000000", + 4354 => x"00000000", + 4355 => x"00000000", + 4356 => x"00000000", + 4357 => x"00000000", + 4358 => x"00000000", + 4359 => x"00000000", + 4360 => x"00000000", + 4361 => x"00000000", + 4362 => x"00000000", + 4363 => x"00000000", + 4364 => x"00000000", + 4365 => x"00000000", + 4366 => x"00000000", + 4367 => x"00000000", + 4368 => x"00000000", + 4369 => x"00000000", + 4370 => x"00003c4c", + 4371 => x"ffffffff", + 4372 => x"00000000", + 4373 => x"ffffffff", + 4374 => x"00000000", + 4375 => x"00000000", + +others => x"00000000" +); +begin + busy_o <= re_i; -- we're done on the cycle after we serve the read request + + do_ram: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + if we_i='1' then + ram(to_integer(addr_i)) <= write_i; + end if; + addr_r <= addr_i; + end if; + end process do_ram; + read_o <= ram(to_integer(addr_r)); +end architecture Xilinx; -- Entity: SinglePortRAM + diff --git a/zpu/hdl/zealot/roms/hello_bram.vhdl b/zpu/hdl/zealot/roms/hello_bram.vhdl new file mode 100644 index 0000000..7724423 --- /dev/null +++ b/zpu/hdl/zealot/roms/hello_bram.vhdl @@ -0,0 +1,3056 @@ +------------------------------------------------------------------------------ +---- ---- +---- Single Port RAM that maps to a Xilinx BRAM ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: SinglePortRAM(Xilinx) (Entity and architecture) ---- +---- File name: rom_s.in.vhdl (template used) ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity SinglePortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + we_i : in std_logic; + re_i : in std_logic; + addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + write_i : in unsigned(WORD_SIZE-1 downto 0); + read_o : out unsigned(WORD_SIZE-1 downto 0); + busy_o : out std_logic); +end entity SinglePortRAM; + +architecture Xilinx of SinglePortRAM is + type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0); + signal addr_r : unsigned(BRAM_W-1 downto BYTE_BITS); + + signal ram : ram_type := +( + 0 => x"0b0b0b0b", + 1 => x"82700b0b", + 2 => x"80cd800c", + 3 => x"3a0b0b80", + 4 => x"c58f0400", + 5 => x"00000000", + 6 => x"00000000", + 7 => x"00000000", + 8 => x"80088408", + 9 => x"88080b0b", + 10 => x"80c5d62d", + 11 => x"880c840c", + 12 => x"800c0400", + 13 => x"00000000", + 14 => x"00000000", + 15 => x"00000000", + 16 => x"71fd0608", + 17 => x"72830609", + 18 => x"81058205", + 19 => x"832b2a83", + 20 => x"ffff0652", + 21 => x"04000000", + 22 => x"00000000", + 23 => x"00000000", + 24 => x"71fd0608", + 25 => x"83ffff73", + 26 => x"83060981", + 27 => x"05820583", + 28 => x"2b2b0906", + 29 => x"7383ffff", + 30 => x"0b0b0b0b", + 31 => x"83a70400", + 32 => x"72098105", + 33 => x"72057373", + 34 => x"09060906", + 35 => x"73097306", + 36 => x"070a8106", + 37 => x"53510400", + 38 => x"00000000", + 39 => x"00000000", + 40 => x"72722473", + 41 => x"732e0753", + 42 => x"51040000", + 43 => x"00000000", + 44 => x"00000000", + 45 => x"00000000", + 46 => x"00000000", + 47 => x"00000000", + 48 => x"71737109", + 49 => x"71068106", + 50 => x"30720a10", + 51 => x"0a720a10", + 52 => x"0a31050a", + 53 => x"81065151", + 54 => x"53510400", + 55 => x"00000000", + 56 => x"72722673", + 57 => x"732e0753", + 58 => x"51040000", + 59 => x"00000000", + 60 => x"00000000", + 61 => x"00000000", + 62 => x"00000000", + 63 => x"00000000", + 64 => x"00000000", + 65 => x"00000000", + 66 => x"00000000", + 67 => x"00000000", + 68 => x"00000000", + 69 => x"00000000", + 70 => x"00000000", + 71 => x"00000000", + 72 => x"0b0b0b88", + 73 => x"c4040000", + 74 => x"00000000", + 75 => x"00000000", + 76 => x"00000000", + 77 => x"00000000", + 78 => x"00000000", + 79 => x"00000000", + 80 => x"720a722b", + 81 => x"0a535104", + 82 => x"00000000", + 83 => x"00000000", + 84 => x"00000000", + 85 => x"00000000", + 86 => x"00000000", + 87 => x"00000000", + 88 => x"72729f06", + 89 => x"0981050b", + 90 => x"0b0b88a7", + 91 => x"05040000", + 92 => x"00000000", + 93 => x"00000000", + 94 => x"00000000", + 95 => x"00000000", + 96 => x"72722aff", + 97 => x"739f062a", + 98 => x"0974090a", + 99 => x"8106ff05", + 100 => x"06075351", + 101 => x"04000000", + 102 => x"00000000", + 103 => x"00000000", + 104 => x"71715351", + 105 => x"020d0406", + 106 => x"73830609", + 107 => x"81058205", + 108 => x"832b0b2b", + 109 => x"0772fc06", + 110 => x"0c515104", + 111 => x"00000000", + 112 => x"72098105", + 113 => x"72050970", + 114 => x"81050906", + 115 => x"0a810653", + 116 => x"51040000", + 117 => x"00000000", + 118 => x"00000000", + 119 => x"00000000", + 120 => x"72098105", + 121 => x"72050970", + 122 => x"81050906", + 123 => x"0a098106", + 124 => x"53510400", + 125 => x"00000000", + 126 => x"00000000", + 127 => x"00000000", + 128 => x"71098105", + 129 => x"52040000", + 130 => x"00000000", + 131 => x"00000000", + 132 => x"00000000", + 133 => x"00000000", + 134 => x"00000000", + 135 => x"00000000", + 136 => x"72720981", + 137 => x"05055351", + 138 => x"04000000", + 139 => x"00000000", + 140 => x"00000000", + 141 => x"00000000", + 142 => x"00000000", + 143 => x"00000000", + 144 => x"72097206", + 145 => x"73730906", + 146 => x"07535104", + 147 => x"00000000", + 148 => x"00000000", + 149 => x"00000000", + 150 => x"00000000", + 151 => x"00000000", + 152 => x"71fc0608", + 153 => x"72830609", + 154 => x"81058305", + 155 => x"1010102a", + 156 => x"81ff0652", + 157 => x"04000000", + 158 => x"00000000", + 159 => x"00000000", + 160 => x"71fc0608", + 161 => x"0b0b80cc", + 162 => x"ec738306", + 163 => x"10100508", + 164 => x"060b0b0b", + 165 => x"88aa0400", + 166 => x"00000000", + 167 => x"00000000", + 168 => x"80088408", + 169 => x"88087575", + 170 => x"0b0b0b8b", + 171 => x"8a2d5050", + 172 => x"80085688", + 173 => x"0c840c80", + 174 => x"0c510400", + 175 => x"00000000", + 176 => x"80088408", + 177 => x"88087575", + 178 => x"0b0b0b8c", + 179 => x"bc2d5050", + 180 => x"80085688", + 181 => x"0c840c80", + 182 => x"0c510400", + 183 => x"00000000", + 184 => x"72097081", + 185 => x"0509060a", + 186 => x"8106ff05", + 187 => x"70547106", + 188 => x"73097274", + 189 => x"05ff0506", + 190 => x"07515151", + 191 => x"04000000", + 192 => x"72097081", + 193 => x"0509060a", + 194 => x"098106ff", + 195 => x"05705471", + 196 => x"06730972", + 197 => x"7405ff05", + 198 => x"06075151", + 199 => x"51040000", + 200 => x"05ff0504", + 201 => x"00000000", + 202 => x"00000000", + 203 => x"00000000", + 204 => x"00000000", + 205 => x"00000000", + 206 => x"00000000", + 207 => x"00000000", + 208 => x"810b0b0b", + 209 => x"80ccfc0c", + 210 => x"51040000", + 211 => x"00000000", + 212 => x"00000000", + 213 => x"00000000", + 214 => x"00000000", + 215 => x"00000000", + 216 => x"71810552", + 217 => x"04000000", + 218 => x"00000000", + 219 => x"00000000", + 220 => x"00000000", + 221 => x"00000000", + 222 => x"00000000", + 223 => x"00000000", + 224 => x"00000000", + 225 => x"00000000", + 226 => x"00000000", + 227 => x"00000000", + 228 => x"00000000", + 229 => x"00000000", + 230 => x"00000000", + 231 => x"00000000", + 232 => x"02840572", + 233 => x"10100552", + 234 => x"04000000", + 235 => x"00000000", + 236 => x"00000000", + 237 => x"00000000", + 238 => x"00000000", + 239 => x"00000000", + 240 => x"00000000", + 241 => x"00000000", + 242 => x"00000000", + 243 => x"00000000", + 244 => x"00000000", + 245 => x"00000000", + 246 => x"00000000", + 247 => x"00000000", + 248 => x"717105ff", + 249 => x"05715351", + 250 => x"020d0400", + 251 => x"00000000", + 252 => x"00000000", + 253 => x"00000000", + 254 => x"00000000", + 255 => x"00000000", + 256 => x"82c73f80", + 257 => x"c4913f04", + 258 => x"10101010", + 259 => x"10101010", + 260 => x"10101010", + 261 => x"10101010", + 262 => x"10101010", + 263 => x"10101010", + 264 => x"10101010", + 265 => x"10101053", + 266 => x"51047381", + 267 => x"ff067383", + 268 => x"06098105", + 269 => x"83051010", + 270 => x"102b0772", + 271 => x"fc060c51", + 272 => x"51043c04", + 273 => x"72728072", + 274 => x"8106ff05", + 275 => x"09720605", + 276 => x"71105272", + 277 => x"0a100a53", + 278 => x"72ed3851", + 279 => x"51535104", + 280 => x"fe3d0d0b", + 281 => x"0b80dce8", + 282 => x"08538413", + 283 => x"0870882a", + 284 => x"70810651", + 285 => x"52527080", + 286 => x"2ef03871", + 287 => x"81ff0680", + 288 => x"0c843d0d", + 289 => x"04ff3d0d", + 290 => x"0b0b80dc", + 291 => x"e8085271", + 292 => x"0870882a", + 293 => x"81327081", + 294 => x"06515151", + 295 => x"70f13873", + 296 => x"720c833d", + 297 => x"0d0480cc", + 298 => x"fc08802e", + 299 => x"a43880cd", + 300 => x"8008822e", + 301 => x"bd388380", + 302 => x"800b0b0b", + 303 => x"80dce80c", + 304 => x"82a0800b", + 305 => x"80dcec0c", + 306 => x"8290800b", + 307 => x"80dcf00c", + 308 => x"04f88080", + 309 => x"80a40b0b", + 310 => x"0b80dce8", + 311 => x"0cf88080", + 312 => x"82800b80", + 313 => x"dcec0cf8", + 314 => x"80808480", + 315 => x"0b80dcf0", + 316 => x"0c0480c0", + 317 => x"a8808c0b", + 318 => x"0b0b80dc", + 319 => x"e80c80c0", + 320 => x"a880940b", + 321 => x"80dcec0c", + 322 => x"0b0b80cc", + 323 => x"c40b80dc", + 324 => x"f00c04ff", + 325 => x"3d0d80dc", + 326 => x"f4335170", + 327 => x"a73880cd", + 328 => x"88087008", + 329 => x"52527080", + 330 => x"2e943884", + 331 => x"1280cd88", + 332 => x"0c702d80", + 333 => x"cd880870", + 334 => x"08525270", + 335 => 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x"00002df8", + 2946 => x"00002e00", + 2947 => x"00002e00", + 2948 => x"00002e08", + 2949 => x"00002e08", + 2950 => x"00002e10", + 2951 => x"00002e10", + 2952 => x"00002e18", + 2953 => x"00002e18", + 2954 => x"00002e20", + 2955 => x"00002e20", + 2956 => x"00002e28", + 2957 => x"00002e28", + 2958 => x"00002e30", + 2959 => x"00002e30", + 2960 => x"00002e38", + 2961 => x"00002e38", + 2962 => x"00002e40", + 2963 => x"00002e40", + 2964 => x"00002660", + 2965 => x"ffffffff", + 2966 => x"00000000", + 2967 => x"ffffffff", + 2968 => x"00000000", + 2969 => x"00000000", + +others => x"00000000" +); +begin + busy_o <= re_i; -- we're done on the cycle after we serve the read request + + do_ram: + process (clk_i) + variable iaddr : integer; + begin + if rising_edge(clk_i) then + if we_i='1' then + ram(to_integer(addr_i)) <= write_i; + end if; + addr_r <= addr_i; + end if; + end process do_ram; + read_o <= ram(to_integer(addr_r)); +end architecture Xilinx; -- Entity: SinglePortRAM + diff --git a/zpu/hdl/zealot/roms/rom_pkg.vhdl b/zpu/hdl/zealot/roms/rom_pkg.vhdl new file mode 100644 index 0000000..c5a4161 --- /dev/null +++ b/zpu/hdl/zealot/roms/rom_pkg.vhdl @@ -0,0 +1,80 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU memories package ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a package with the memories used for the ZPU core. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: zpu_memory (Package) ---- +---- File name: rom_pkg.vhdl (template used) ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package zpu_memory is + component DualPortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + -- Port A + a_we_i : in std_logic; + a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + a_write_i : in unsigned(WORD_SIZE-1 downto 0); + a_read_o : out unsigned(WORD_SIZE-1 downto 0); + -- Port B + b_we_i : in std_logic; + b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + b_write_i : in unsigned(WORD_SIZE-1 downto 0); + b_read_o : out unsigned(WORD_SIZE-1 downto 0)); + end component DualPortRAM; + + component SinglePortRAM is + generic( + WORD_SIZE : integer:=32; -- Word Size 16/32 + BYTE_BITS : integer:=2; -- Bits used to address bytes + BRAM_W : integer:=15); -- Address Width + port( + clk_i : in std_logic; + we_i : in std_logic; + re_i : in std_logic; + addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS); + write_i : in unsigned(WORD_SIZE-1 downto 0); + read_o : out unsigned(WORD_SIZE-1 downto 0); + busy_o : out std_logic); + end component SinglePortRAM; +end package zpu_memory; diff --git a/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl new file mode 100644 index 0000000..4361b9c --- /dev/null +++ b/zpu/hdl/zealot/testbenches/dmips_med1_tb.vhdl @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------ +---- ---- +---- Testbench for the ZPU Medium connection to the FPGA ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- This is a testbench to simulate the ZPU_Med1 core as used in the ---- +---- dmips_med1.vhdl ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: DMIPS_Med1_TB(Behave) (Entity and architecture) ---- +---- File name: dmips_med1_tb.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: work ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- zpu.txt_util ---- +---- work.zpu_memory ---- +---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: N/A ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; +use zpu.txt_util.all; + +library work; +use work.zpu_memory.all; + +entity DMIPS_Med1_TB is +end entity DMIPS_Med1_TB; + +architecture Behave of DMIPS_Med1_TB is + constant WORD_SIZE : natural:=32; -- 32 bits data path + constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB + constant D_CARE_VAL : std_logic:='0'; -- Fill value + constant CLK_FREQ : positive:=50; -- 50 MHz clock + constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period + constant BRATE : positive:=115200; + + component ZPU_Med1 is + generic( + WORD_SIZE : natural:=32; -- 32 bits data path + D_CARE_VAL : std_logic:='X'; -- Fill value + CLK_FREQ : positive:=50; -- 50 MHz clock + BRATE : positive:=9600; -- RS232 baudrate + ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O + BRAM_W : natural:=15); -- 15 bits RAM space=32 kB + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic); -- UART Rx + end component ZPU_Med1; + + signal clk : std_logic; + signal reset : std_logic:='1'; + + signal break : std_logic; + signal dbg : zpu_dbgo_t; -- Debug info + signal rs232_tx : std_logic; + signal rs232_rx : std_logic; +begin + zpu : ZPU_Med1 + generic map( + WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL, + CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W, + BRAM_W => BRAM_W) + port map( + clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx, + rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg); + + trace_mod : Trace + generic map( + ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE, + LOG_FILE => "dmips_med1.log") + port map( + clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0'); + + do_clock: + process + begin + clk <= '0'; + wait for CLK_S_PER; + clk <= '1'; + wait for CLK_S_PER; + if break='1' then + print("* Break asserted, end of test"); + wait; + end if; + end process do_clock; + + do_reset: + process + begin + wait until rising_edge(clk); + reset <= '0'; + end process do_reset; +end architecture Behave; -- Entity: DMIPS_Med1_TB diff --git a/zpu/hdl/zealot/zpu_medium.vhdl b/zpu/hdl/zealot/zpu_medium.vhdl new file mode 100644 index 0000000..47950fe --- /dev/null +++ b/zpu/hdl/zealot/zpu_medium.vhdl @@ -0,0 +1,948 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Medium ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is the medium size version. ---- +---- Supports external memories. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: ZPUMediumCore(Behave) (Entity and architecture) ---- +---- File name: zpu_medium.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- zpu.zpupkg ---- +---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ +-- +-- write_en_o - set to '1' for a single cycle to send off a write request. +-- data_o is valid only while write_en_o='1'. +-- read_en_o - set to '1' for a single cycle to send off a read request. +-- mem_busy_i - It is illegal to send off a read/write request when +-- mem_busy_i='1'. +-- Set to '0' when data_i is valid after a read request. +-- If it goes to '1'(busy), it is on the cycle after read/ +-- write_en_o is '1'. +-- addr_o - address for read/write request +-- data_i - read data. Valid only on the cycle after mem_busy_i='0' +-- after read_en_o='1' for a single cycle. +-- data_o - data to write +-- break_o - set to '1' when CPU hits break instruction + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library zpu; +use zpu.zpupkg.all; + +entity ZPUMediumCore is + generic( + WORD_SIZE : integer:=32; -- 16/32 (2**wordPower) + ADDR_W : integer:=16; -- Total address space width (incl. I/O) + MEM_W : integer:=15; -- Memory (prog+data+stack) width + D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits + MULT_PIPE : boolean:=false; -- Pipeline multiplication + BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=) + ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd + ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub + ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel + ENA_LSHR : boolean:=true; -- lshiftright + ENA_IDLE : boolean:=false; -- Enable the enable_i input + FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states + port( + clk_i : in std_logic; -- CPU Clock + reset_i : in std_logic; -- Sync Reset + enable_i : in std_logic; -- Hold the CPU (after reset) + break_o : out std_logic; -- Break instruction executed + dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) + -- Memory interface + mem_busy_i : in std_logic; -- Memory is busy + data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem + data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem + addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address + write_en_o : out std_logic; -- Memory write enable + read_en_o : out std_logic); -- Memory read enable +end entity ZPUMediumCore; + +architecture Behave of ZPUMediumCore is + constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes + constant WORD_BYTES : integer:=WORD_SIZE/OPCODE_W; + constant MAX_ADDR_BIT : integer:=ADDR_W-2; + -- Stack Pointer initial value: BRAM size-8 + constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W); + constant SP_START : unsigned(ADDR_W-1 downto BYTE_BITS):= + SP_START_1(ADDR_W-1 downto BYTE_BITS); + + -- Update [SP+1]. We hold it in b_r, this writes the value to memory. + procedure FlushB(signal we : out std_logic; + signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS); + signal inc_sp : in unsigned(ADDR_W-1 downto BYTE_BITS); + signal data : out unsigned(WORD_SIZE-1 downto 0); + signal b : in unsigned(WORD_SIZE-1 downto 0)) is + begin + we <= '1'; + addr <= inc_sp; + data <= b; + end procedure FlushB; + + -- Do a simple stack push, it is performed in the internal cache registers, + -- not in the real memory. + procedure Push(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS); + signal a : in unsigned(WORD_SIZE-1 downto 0); + signal b : out unsigned(WORD_SIZE-1 downto 0)) is + begin + b <= a; -- Update cache [SP+1]=[SP] + sp <= sp-1; + end procedure Push; + + -- Do a simple stack pop, it is performed in the internal cache registers, + -- not in the real memory. + procedure Pop(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS); + signal a : out unsigned(WORD_SIZE-1 downto 0); + signal b : in unsigned(WORD_SIZE-1 downto 0)) is + begin + a <= b; -- Update cache [SP]=[SP+1] + sp <= sp+1; + end procedure Pop; + + -- Expand a PC value to WORD_SIZE + function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is + variable nv : unsigned(WORD_SIZE-1 downto 0); + begin + nv:=(others => '0'); + nv(ADDR_W-1 downto 0):=v; + return nv; + end function ExpandPC; + + -- Program counter + signal pc_r : unsigned(ADDR_W-1 downto 0):=(others => '0'); + -- Stack pointer + signal sp_r : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START; + -- SP+1, SP+2 and SP-1 are very used, these are shortcuts + signal inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS); + signal inc_inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS); + -- a_r is a cache for the top of the stack [SP] + -- Note: as this is a stack CPU this is a very important register. + signal a_r : unsigned(WORD_SIZE-1 downto 0); + -- b_r is a cache for the next value in the stack [SP+1] + signal b_r : unsigned(WORD_SIZE-1 downto 0); + signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + signal mult_res1_r : unsigned(WORD_SIZE-1 downto 0); + signal mult_res2_r : unsigned(WORD_SIZE-1 downto 0); + signal mult_res3_r : unsigned(WORD_SIZE-1 downto 0); + signal mult_a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + signal mult_b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + signal idim_r : std_logic; + signal write_en_r : std_logic; + signal read_en_r : std_logic; + signal addr_r : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0'); + signal fetched_w_r : unsigned(WORD_SIZE-1 downto 0); + + type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2, + st_fetch, st_execute, st_decode, st_decode2, st_resync, + st_store_sp2, st_resync2, st_resync3, st_loadb2, st_storeb2, + st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2, + st_binary_op_res, st_idle); + signal state : state_t:=st_resync; + + -- Go to st_fetch state or just do its work + procedure DoFetch(constant FAST : boolean; + signal state : out state_t; + signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS); + signal pc : in unsigned(ADDR_W-1 downto 0); + signal re : out std_logic; + signal busy : in std_logic) is + begin + if FAST then + -- Equivalent to st_fetch + if busy='0' then + addr <= pc(ADDR_W-1 downto BYTE_BITS); + re <= '1'; + state <= st_decode; + end if; + else + state <= st_fetch; + end if; + end procedure DoFetch; + + -- Perform a "binary operation" (2 operands) + procedure DoBinOp(result : in unsigned(WORD_SIZE-1 downto 0); + signal state : out state_t; + signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS); + signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS); + signal re : out std_logic; + signal dest : out unsigned(WORD_SIZE-1 downto 0); + signal dest_p : out unsigned(WORD_SIZE-1 downto 0); + constant DEPTH : natural) is + begin + if DEPTH=2 then + -- 2 clocks: st_binary_op_res+st_binary_op_res2 + state <= st_binary_op_res; + dest_p <= result; + elsif DEPTH=1 then + -- 1 clock: st_binary_op_res2 + state <= st_binary_op_res2; + dest_p <= result; + else -- 0 clocks + re <= '1'; + addr <= sp+2; + sp <= sp+1; + dest <= result; + state <= st_popped; + end if; + end procedure DoBinOp; + + -- Perform a boolean "binary operation" (2 operands) + procedure DoBinOpBool(result : in boolean; + signal state : out state_t; + signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS); + signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS); + signal re : out std_logic; + signal dest : out unsigned(WORD_SIZE-1 downto 0); + signal dest_p : out unsigned(WORD_SIZE-1 downto 0); + constant DEPTH : natural) is + variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0'); + begin + if result then + res(0):='1'; + end if; + DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH); + end procedure DoBinOpBool; + + type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add, + dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop, + dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load, + dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip, + dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult, + dec_less_than, dec_less_than_or_equal, dec_lshr, + dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add, + dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb, + dec_insn_fetch, dec_pop_down); + signal insn : insn_t; + type insn_array_t is array(0 to WORD_BYTES-1) of insn_t; + signal insns : insn_array_t; + type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0); + signal opcode_r : opcode_array_t; +begin + -- the memory subsystem will tell us one cycle later whether or + -- not it is busy + write_en_o <= write_en_r; + read_en_o <= read_en_r; + addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r; + addr_o(BYTE_BITS-1 downto 0) <= (others => '0'); + + -- SP+1 and +2 + inc_sp <= sp_r+1; + inc_inc_sp <= sp_r+2; + + opcode_control: + process (clk_i) + variable topcode : unsigned(OPCODE_W-1 downto 0); + variable ex_opcode : unsigned(OPCODE_W-1 downto 0); + variable sp_offset : unsigned(4 downto 0); + variable tsp_offset : unsigned(4 downto 0); + variable next_pc : unsigned(ADDR_W-1 downto 0); + variable tdecoded : insn_t; + variable tinsns : insn_array_t; + variable mult_res : unsigned(WORD_SIZE*2-1 downto 0); + variable ipc_low : integer range 0 to 3; -- Address inside a word (pc_r) + variable inpc_low : integer range 0 to 3; -- Address inside a word (next_pc) + variable h_bit : integer; + variable l_bit : integer; + variable not_lshr : std_logic:='1'; + begin + if rising_edge(clk_i) then + break_o <= '0'; + if reset_i='1' then + if ENA_IDLE then + state <= st_idle; + else + state <= st_resync; + end if; + sp_r <= SP_START; + pc_r <= (others => '0'); + idim_r <= '0'; + write_en_r <= '0'; + read_en_r <= '0'; + mult_a_r <= (others => '0'); + mult_b_r <= (others => '0'); + dbg_o.b_inst <= '0'; + -- Reseting add_r here makes XST fail to use BRAMs ?! + else -- reset_i='1' + if MULT_PIPE then + -- We must multiply unconditionally to get pipelined multiplication + mult_res:=mult_a_r*mult_b_r; + mult_res1_r <= mult_res(WORD_SIZE-1 downto 0); + mult_res2_r <= mult_res1_r; + mult_res3_r <= mult_res2_r; + mult_a_r <= (others => D_CARE_VAL); + mult_b_r <= (others => D_CARE_VAL); + end if; + + if BINOP_PIPE=2 then + bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit. + end if; + + read_en_r <='0'; + write_en_r <='0'; + -- Allow synthesis tools to load bogus values when we don't + -- care about the address and output data. + addr_r <= (others => D_CARE_VAL); + data_o <= (others => D_CARE_VAL); + + if (write_en_r='1') and (read_en_r='1') then + report "read/write collision" severity failure; + end if; + + ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0)); + sp_offset(4):=not opcode_r(ipc_low)(4); + sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0); + next_pc:=pc_r+1; + + -- Prepare trace snapshot + dbg_o.opcode <= opcode_r(ipc_low); + dbg_o.pc <= resize(pc_r,32); + dbg_o.stk_a <= resize(a_r,32); + dbg_o.stk_b <= resize(b_r,32); + dbg_o.b_inst <= '0'; + dbg_o.sp <= (others => '0'); + dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r; + + case state is + when st_idle => + if enable_i='1' then + state <= st_resync; + end if; + -- Initial state of ZPU, fetch top of stack (A/B) + first instruction + when st_resync => + if mem_busy_i='0' then + addr_r <= sp_r; + read_en_r <= '1'; + state <= st_resync2; + end if; + when st_resync2 => + if mem_busy_i='0' then + a_r <= data_i; + addr_r <= inc_sp; + read_en_r <= '1'; + state <= st_resync3; + end if; + when st_resync3 => + if mem_busy_i='0' then + b_r <= data_i; + addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + state <= st_decode; + end if; + when st_decode => + if mem_busy_i='0' then + -- Here we latch the fetched word to give one full clock + -- cycle to the instruction decoder. This could be removed + -- if using BRAMs and the decoder delay isn't important. + fetched_w_r <= data_i; + state <= st_decode2; + end if; + when st_decode2 => + -- decode 4 instructions in parallel + for i in 0 to WORD_BYTES-1 loop + topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8); + + tsp_offset(4):=not topcode(4); + tsp_offset(3 downto 0):=topcode(3 downto 0); + + opcode_r(i) <= topcode; + if topcode(7 downto 7)=OPCODE_IM then + tdecoded:=dec_im; + elsif topcode(7 downto 5)=OPCODE_STORESP then + if tsp_offset=0 then + -- Special case, we can avoid a write + tdecoded:=dec_pop; + elsif tsp_offset=1 then + -- Special case, collision + tdecoded:=dec_pop_down; + else + tdecoded:=dec_store_sp; + end if; + elsif topcode(7 downto 5)=OPCODE_LOADSP then + if tsp_offset=0 then + tdecoded:=dec_dup; + elsif tsp_offset=1 then + tdecoded:=dec_dup_stk_b; + else + tdecoded:=dec_load_sp; + end if; + elsif topcode(7 downto 5)=OPCODE_EMULATE then + tdecoded:=dec_emulate; + if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then + tdecoded:=dec_neq_branch; + elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then + tdecoded:=dec_eq; + elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then + tdecoded:=dec_loadb; + elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then + tdecoded:=dec_push_sp_add; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then + tdecoded:=dec_less_than; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then + tdecoded:=dec_u_less_than; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then + tdecoded:=dec_mult; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then + tdecoded:=dec_storeb; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then + tdecoded:=dec_call_pc_rel; + elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then + tdecoded:=dec_sub; + elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then + tdecoded:=dec_less_than_or_equal; + elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then + tdecoded:=dec_u_less_than_or_equal; + elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then + tdecoded:=dec_call; + elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then + tdecoded:=dec_pop_pc_rel; + elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then + tdecoded:=dec_lshr; + end if; + elsif topcode(7 downto 4)=OPCODE_ADDSP then + if tsp_offset=0 then + tdecoded:=dec_shift; + elsif tsp_offset=1 then + tdecoded:=dec_add_top; + else + tdecoded:=dec_add_sp; + end if; + else -- OPCODE_SHORT + case topcode(3 downto 0) is + when OPCODE_BREAK => + tdecoded:=dec_break; + when OPCODE_PUSHSP => + tdecoded:=dec_push_sp; + when OPCODE_POPPC => + tdecoded:=dec_pop_pc; + when OPCODE_ADD => + tdecoded:=dec_add; + when OPCODE_OR => + tdecoded:=dec_or; + when OPCODE_AND => + tdecoded:=dec_and; + when OPCODE_LOAD => + tdecoded:=dec_load; + when OPCODE_NOT => + tdecoded:=dec_not; + when OPCODE_FLIP => + tdecoded:=dec_flip; + when OPCODE_STORE => + tdecoded:=dec_store; + when OPCODE_POPSP => + tdecoded:=dec_pop_sp; + when others => -- OPCODE_NOP and others + tdecoded:=dec_nop; + end case; + end if; + tinsns(i):=tdecoded; + end loop; + + insn <= tinsns(ipc_low); + -- once we wrap, we need to fetch + tinsns(0):=dec_insn_fetch; + insns <= tinsns; + state <= st_execute; + + -- Each instruction must: + -- + -- 1. increase pc_r if applicable + -- 2. set next state if applicable + -- 3. do it's operation + when st_execute => + -- Some shortcut to make the code readable: + inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0)); + ex_opcode:=opcode_r(ipc_low); + insn <= insns(inpc_low); + -- Defaults used by most instructions + if insn/=dec_insn_fetch and insn/=dec_im then + dbg_o.b_inst <= '1'; + idim_r <= '0'; + end if; + case insn is + when dec_insn_fetch => + -- Not a real instruction, fetch new instructions + DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i); + when dec_im => + -- Push(immediate value), IDIM=1 + -- if IDIM=0 Push(signed(opcode & 0x7F)) else + -- Push((Pop()<<7)|(opcode&0x7F)) + if mem_busy_i='0' then + dbg_o.b_inst <= '1'; + idim_r <= '1'; + pc_r <= pc_r+1; + if idim_r='1' then + -- We already started an IM sequence + -- Shift left 7 bits + a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0); + -- Put the new value + a_r(6 downto 0) <= ex_opcode(6 downto 0); + else + -- First IM, push the value sign extended + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE)); + Push(sp_r,a_r,b_r); + end if; + end if; + when dec_store_sp => + -- [SP+Offset]=Pop() + if mem_busy_i='0' then + write_en_r <= '1'; + addr_r <= sp_r+sp_offset; + data_o <= a_r; + Pop(sp_r,a_r,b_r); + -- We need to fetch B + state <= st_store_sp2; + end if; + when dec_load_sp => + -- Push([SP+Offset]) + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + Push(sp_r,a_r,b_r); + -- We are flushing B cache, so we need more time to + -- read the value. + state <= st_load_sp2; + end if; + when dec_emulate => + -- Push(PC+1), PC=Opcode[4:0]*32 + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + state <= st_fetch; + a_r <= ExpandPC(pc_r+1); + Push(sp_r,a_r,b_r); + -- The emulate address is: + -- 98 7654 3210 + -- 0000 00aa aaa0 0000 + pc_r <= (others => '0'); + pc_r(9 downto 5) <= ex_opcode(4 downto 0); + end if; + when dec_call_pc_rel => + -- t=Pop(), Push(PC+1), PC=PC+t + if mem_busy_i='0' and ENA_LEVEL1 then + state <= st_fetch; + a_r <= ExpandPC(pc_r+1); + pc_r <= pc_r+a_r(ADDR_W-1 downto 0); + end if; + when dec_call => + -- t=Pop(), Push(PC+1), PC=t + if mem_busy_i='0' and ENA_LEVEL2 then + state <= st_fetch; + a_r <= ExpandPC(pc_r+1); + pc_r <= a_r(ADDR_W-1 downto 0); + end if; + when dec_add_sp => + -- Push(Pop()+[SP+Offset]) + if mem_busy_i='0' then + -- Read SP+Offset + state <= st_add_sp2; + read_en_r <= '1'; + addr_r <= sp_r+sp_offset; + pc_r <= pc_r+1; + end if; + when dec_push_sp => + -- Push(SP) + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + pc_r <= pc_r+1; + a_r <= (others => '0'); + a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r; + Push(sp_r,a_r,b_r); + end if; + when dec_pop_pc => + -- PC=Pop() (return) + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + state <= st_resync; + pc_r <= a_r(ADDR_W-1 downto 0); + sp_r <= inc_sp; + end if; + when dec_pop_pc_rel => + -- PC=PC+Pop() + if mem_busy_i='0' and ENA_LEVEL2 then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + state <= st_resync; + pc_r <= a_r(ADDR_W-1 downto 0)+pc_r; + sp_r <= inc_sp; + end if; + when dec_add => + -- Push(Pop()+Pop()) [A=A+B, SP++, update B] + if mem_busy_i='0' then + state <= st_popped; + a_r <= a_r+b_r; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + end if; + when dec_sub => + -- a=Pop(), b=Pop(), Push(b-a) + if mem_busy_i='0' and ENA_LEVEL1 then + DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r, + a_r,bin_op_res1_r,BINOP_PIPE); + end if; + when dec_pop => + -- Pop() + if mem_busy_i='0' then + state <= st_popped; + addr_r <= inc_inc_sp; + read_en_r <= '1'; + Pop(sp_r,a_r,b_r); + end if; + when dec_pop_down => + -- t=Pop(), Pop(), Push(t) + if mem_busy_i='0' then + -- PopDown leaves top of stack unchanged + state <= st_popped; + addr_r <= inc_inc_sp; + read_en_r <= '1'; + sp_r <= inc_sp; + end if; + when dec_or => + -- Push(Pop() or Pop()) + if mem_busy_i='0' then + state <= st_popped; + a_r <= a_r or b_r; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + end if; + when dec_and => + -- Push(Pop() and Pop()) + if mem_busy_i='0' then + state <= st_popped; + a_r <= a_r and b_r; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + end if; + when dec_eq => + -- a=Pop(), b=Pop(), Push(a=b ? 1 : 0) + if mem_busy_i='0' and ENA_LEVEL0 then + DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r, + a_r,bin_op_res1_r,BINOP_PIPE); + end if; + when dec_u_less_than => + -- a=Pop(), b=Pop(), Push(a + -- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0) + if mem_busy_i='0' and ENA_LEVEL2 then + DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r, + a_r,bin_op_res1_r,BINOP_PIPE); + end if; + when dec_less_than => + -- a=signed(Pop()), b=signed(Pop()), Push(a + -- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0) + if mem_busy_i='0' and ENA_LEVEL2 then + DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r, + addr_r,read_en_r,a_r,bin_op_res1_r, + BINOP_PIPE); + end if; + when dec_load => + -- Push([Pop()]) + if mem_busy_i='0' then + state <= st_load2; + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + pc_r <= pc_r+1; + end if; + when dec_dup => + -- t=Pop(), Push(t), Push(t) + if mem_busy_i='0' then + pc_r <= pc_r+1; + -- A is dupped, no change + Push(sp_r,a_r,b_r); + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + end if; + when dec_dup_stk_b => + -- Pop(), t=Pop(), Push(t), Push(t), Push(t) + if mem_busy_i='0' then + pc_r <= pc_r+1; + a_r <= b_r; + -- B goes to A + Push(sp_r,a_r,b_r); + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + end if; + when dec_store => + -- a=Pop(), b=Pop(), [a]=b + if mem_busy_i='0' then + state <= st_resync; + pc_r <= pc_r+1; + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + data_o <= b_r; + write_en_r <= '1'; + sp_r <= inc_inc_sp; + end if; + when dec_pop_sp => + -- SP=Pop() + if mem_busy_i='0' then + FlushB(write_en_r,addr_r,inc_sp,data_o,b_r); + state <= st_resync; + pc_r <= pc_r+1; + sp_r <= a_r(ADDR_W-1 downto BYTE_BITS); + end if; + when dec_nop => + pc_r <= pc_r+1; + when dec_not => + -- Push(not(Pop())) + pc_r <= pc_r+1; + a_r <= not a_r; + when dec_flip => + -- Push(flip(Pop())) + pc_r <= pc_r+1; + for i in 0 to WORD_SIZE-1 loop + a_r(i) <= a_r(WORD_SIZE-1-i); + end loop; + when dec_add_top => + -- a=Pop(), b=Pop(), Push(b), Push(a+b) + pc_r <= pc_r+1; + a_r <= a_r+b_r; + when dec_shift => + -- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)] + pc_r <= pc_r+1; + a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0); + a_r(0) <= '0'; + when dec_push_sp_add => + -- Push(Pop()+SP) + if ENA_LEVEL0 then + pc_r <= pc_r+1; + a_r <= (others => '0'); + a_r(ADDR_W-1 downto BYTE_BITS) <= + a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r; + end if; + when dec_neq_branch => + -- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a + -- Branches are almost always taken as they form loops + if ENA_LEVEL0 then + sp_r <= inc_inc_sp; + -- Need to fetch stack again. + state <= st_resync; + if b_r/=0 then + pc_r <= a_r(ADDR_W-1 downto 0)+pc_r; + else + pc_r <= pc_r+1; + end if; + end if; + when dec_mult => + -- Push(Pop()*Pop()) + if ENA_LEVEL1 then + if MULT_PIPE then + mult_a_r <= a_r; + mult_b_r <= b_r; + state <= st_mult2; + else + mult_res:=a_r*b_r; + mult_res1_r <= mult_res(WORD_SIZE-1 downto 0); + state <= st_mult5; + end if; + end if; + when dec_break => + -- Assert the break_o signal + --report "Break instruction encountered" severity failure; + break_o <= '1'; + pc_r <= pc_r+1; + when dec_loadb => + -- Push([Pop()] & 0xFF) (byte address) + if mem_busy_i='0' and ENA_LEVEL0 then + state <= st_loadb2; + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + pc_r <= pc_r+1; + end if; + when dec_storeb => + -- [Pop()]=Pop() & 0xFF (byte address) + if mem_busy_i='0' and ENA_LEVEL1 then + state <= st_storeb2; + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + pc_r <= pc_r+1; + end if; + when dec_lshr => + -- a=Pop(), b=Pop(), Push(b>>(a&0x3F)) + if ENA_LSHR then + -- This instruction takes more than one cycle. + -- We must avoid duplications in the trace log. + dbg_o.b_inst <= not_lshr; + not_lshr:='0'; + if a_r(5 downto 0)=0 then -- Only 6 bits used + -- No more shifts + if mem_busy_i='0' then + state <= st_popped; + a_r <= b_r; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + not_lshr:='1'; + end if; + else -- More shifts needed + b_r <= "0"&b_r(WORD_SIZE-1 downto 1); + a_r(5 downto 0) <= a_r(5 downto 0)-1; + insn <= insn; + end if; + end if; + when others => + -- Undefined behavior, we shouldn't get here. + -- It only helps synthesis tools. + sp_r <= (others => D_CARE_VAL); + report "Illegal decode instruction?!" severity failure; + --break_o <= '1'; + end case; + -- The followup of operations that takes more than one execution clock + when st_store_sp2 => + if mem_busy_i='0' then + addr_r <= inc_sp; + read_en_r <= '1'; + state <= st_popped; + end if; + when st_load_sp2 => + if mem_busy_i='0' then + state <= st_load_sp3; + -- Now we can read SP+Offset (SP already decremented) + read_en_r <= '1'; + addr_r <= sp_r+sp_offset+1; + end if; + when st_load_sp3 => + if mem_busy_i='0' then + -- Note: We can't increment PC in the decode stage + -- because it will modify sp_offset. + pc_r <= pc_r+1; + -- Finally we have the result in A + state <= st_execute; + a_r <= data_i; + end if; + when st_add_sp2 => + if mem_busy_i='0' then + state <= st_execute; + a_r <= a_r+data_i; + end if; + when st_load2 => + if mem_busy_i='0' then + a_r <= data_i; + state <= st_execute; + end if; + when st_loadb2 => + if mem_busy_i='0' then + a_r <= (others => '0'); + -- Select the source bits using the less significant bits (byte address) + h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1; + l_bit:=h_bit-7; + a_r(7 downto 0) <= data_i(h_bit downto l_bit); + state <= st_execute; + end if; + when st_storeb2 => + if mem_busy_i='0' then + addr_r <= a_r(ADDR_W-1 downto BYTE_BITS); + data_o <= data_i; + -- Select the source bits using the less significant bits (byte address) + h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1; + l_bit:=h_bit-7; + data_o(h_bit downto l_bit) <= b_r(7 downto 0); + write_en_r <= '1'; + sp_r <= inc_inc_sp; + state <= st_resync; + end if; + when st_fetch => + if mem_busy_i='0' then + addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS); + read_en_r <= '1'; + state <= st_decode; + end if; + -- The following states can be used to leave cycles free for + -- tools that can automagically decompose the multiplication + -- in various stages. Xilinx tools can do it to increase the + -- multipliers performance. + when st_mult2 => + state <= st_mult3; + when st_mult3 => + state <= st_mult4; + when st_mult4 => + state <= st_mult5; + when st_mult5 => + if mem_busy_i='0' then + if MULT_PIPE then + a_r <= mult_res3_r; + else + a_r <= mult_res1_r; + end if; + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + state <= st_popped; + end if; + when st_binary_op_res => + -- BINOP_PIPE=2 + state <= st_binary_op_res2; + when st_binary_op_res2 => + -- BINOP_PIPE>=1 + read_en_r <= '1'; + addr_r <= inc_inc_sp; + sp_r <= inc_sp; + state <= st_popped; + if BINOP_PIPE=2 then + a_r <= bin_op_res2_r; + else -- 1 + a_r <= bin_op_res1_r; + end if; + when st_popped => + if mem_busy_i='0' then + -- Note: Moving this PC++ to the decoder seems to + -- consume more LUTs. + pc_r <= pc_r+1; + b_r <= data_i; + state <= st_execute; + end if; + when others => + -- Undefined behavior, we shouldn't get here. + -- It only helps synthesis tools. + sp_r <= (others => D_CARE_VAL); + report "Illegal state?!" severity failure; + --break_o <= '1'; + end case; -- state + end if; -- else reset_i='1' + end if; -- rising_edge(clk_i) + end process opcode_control; +end architecture Behave; -- Entity: ZPUMediumCore + diff --git a/zpu/hdl/zealot/zpu_pkg.vhdl b/zpu/hdl/zealot/zpu_pkg.vhdl new file mode 100644 index 0000000..15ac700 --- /dev/null +++ b/zpu/hdl/zealot/zpu_pkg.vhdl @@ -0,0 +1,270 @@ +------------------------------------------------------------------------------ +---- ---- +---- ZPU Package ---- +---- ---- +---- http://www.opencores.org/ ---- +---- ---- +---- Description: ---- +---- ZPU is a 32 bits small stack cpu. This is the package. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author: ---- +---- - Øyvind Harboe, oyvind.harboe zylin.com ---- +---- - Salvador E. Tropea, salvador inti.gob.ar ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Copyright (c) 2008 Øyvind Harboe ---- +---- Copyright (c) 2008 Salvador E. Tropea ---- +---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- +---- ---- +---- Distributed under the BSD license ---- +---- ---- +------------------------------------------------------------------------------ +---- ---- +---- Design unit: zpupkg, UART (Package) ---- +---- File name: zpu_medium.vhdl ---- +---- Note: None ---- +---- Limitations: None known ---- +---- Errors: None known ---- +---- Library: zpu ---- +---- Dependencies: IEEE.std_logic_1164 ---- +---- IEEE.numeric_std ---- +---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ---- +---- Language: VHDL ---- +---- Wishbone: No ---- +---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ---- +---- Simulation tools: GHDL [Sokcho edition] (0.2x) ---- +---- Text editor: SETEdit 0.5.x ---- +---- ---- +------------------------------------------------------------------------------ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package zpupkg is + constant OPCODE_W : integer:=8; + + -- Debug structure, currently only for the trace module + type zpu_dbgo_t is record + b_inst : std_logic; + opcode : unsigned(OPCODE_W-1 downto 0); + pc : unsigned(31 downto 0); + sp : unsigned(31 downto 0); + stk_a : unsigned(31 downto 0); + stk_b : unsigned(31 downto 0); + end record; + + component Trace is + generic( + LOG_FILE : string:="trace.txt"; -- Name of the trace file + ADDR_W : integer:=16; -- Address width + WORD_SIZE : integer:=32); -- 16/32 + port( + clk_i : in std_logic; + dbg_i : in zpu_dbgo_t; + stop_i : in std_logic; + busy_i : in std_logic + ); + end component Trace; + + component ZPUSmallCore is + generic( + WORD_SIZE : integer:=32; -- 16/32 (2**wordPower) + ADDR_W : integer:=16; -- maxAddrBitIncIO+1 + BRAM_W : integer:=15; -- maxAddrBitBRAM+1 + D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits + port( + clk_i : in std_logic; -- System Clock + reset_i : in std_logic; -- Synchronous Reset + enable_i : in std_logic; -- Not used + interrupt_i : in std_logic; -- Interrupt + break_o : out std_logic; -- Breakpoint opcode executed + dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) + -- BRAM (text, data, bss and stack) + a_we_o : out std_logic; -- BRAM A port Write Enable + a_addr_o : out unsigned(BRAM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address + a_write_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port + a_read_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port + b_we_o : out std_logic; -- BRAM B port Write Enable + b_addr_o : out unsigned(BRAM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address + b_write_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port + b_read_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port + -- Memory mapped I/O + mem_busy_i : in std_logic; + data_i : in unsigned(WORD_SIZE-1 downto 0); + data_o : out unsigned(WORD_SIZE-1 downto 0); + addr_o : out unsigned(ADDR_W-1 downto 0); + write_en_o : out std_logic; + read_en_o : out std_logic); + end component ZPUSmallCore; + + component ZPUMediumCore is + generic( + WORD_SIZE : integer:=32; -- 16/32 (2**wordPower) + ADDR_W : integer:=16; -- Total address space width (incl. I/O) + MEM_W : integer:=15; -- Memory (prog+data+stack) width + D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits + MULT_PIPE : boolean:=false; -- Pipeline multiplication + BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=) + ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd + ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub + ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel + ENA_LSHR : boolean:=true; -- lshiftright + ENA_IDLE : boolean:=false; -- Enable the enable_i input + FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states + port( + clk_i : in std_logic; -- CPU Clock + reset_i : in std_logic; -- Sync Reset + enable_i : in std_logic; -- Hold the CPU (after reset) + break_o : out std_logic; -- Break instruction executed + dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) + -- Memory interface + mem_busy_i : in std_logic; -- Memory is busy + data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem + data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem + addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address + write_en_o : out std_logic; -- Memory write enable + read_en_o : out std_logic); -- Memory read enable + end component ZPUMediumCore; + + component Timer is + port( + clk_i : in std_logic; + reset_i : in std_logic; + we_i : in std_logic; + data_i : in unsigned(31 downto 0); + addr_i : in unsigned(0 downto 0); + data_o : out unsigned(31 downto 0)); + end component Timer; + + component ZPUPhiIO is + generic( + BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4 + ENA_LOG : boolean:=true; -- Enable log + LOG_FILE : string:="log.txt"); -- Name for the log file + port( + clk_i : in std_logic; -- System Clock + reset_i : in std_logic; -- Synchronous Reset + busy_o : out std_logic; -- I/O is busy + we_i : in std_logic; -- Write Enable + re_i : in std_logic; -- Read Enable + data_i : in unsigned(31 downto 0); + data_o : out unsigned(31 downto 0); + addr_i : in unsigned(2 downto 0); -- Address bits 4-2 + rs232_rx_i : in std_logic; -- UART Rx input + rs232_tx_o : out std_logic; -- UART Tx output + br_clk_i : in std_logic); -- UART base clock (enable) + end component ZPUPhiIO; + + -- Opcode decode constants + -- Note: these are the basic opcodes, always implemented using hardware. + constant OPCODE_IM : unsigned(7 downto 7):="1"; + constant OPCODE_STORESP : unsigned(7 downto 5):="010"; + constant OPCODE_LOADSP : unsigned(7 downto 5):="011"; + constant OPCODE_EMULATE : unsigned(7 downto 5):="001"; + constant OPCODE_ADDSP : unsigned(7 downto 4):="0001"; + constant OPCODE_SHORT : unsigned(7 downto 4):="0000"; + + constant OPCODE_BREAK : unsigned(3 downto 0):="0000"; + constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001"; + constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010"; + constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011"; + + constant OPCODE_POPPC : unsigned(3 downto 0):="0100"; + constant OPCODE_ADD : unsigned(3 downto 0):="0101"; + constant OPCODE_AND : unsigned(3 downto 0):="0110"; + constant OPCODE_OR : unsigned(3 downto 0):="0111"; + + constant OPCODE_LOAD : unsigned(3 downto 0):="1000"; + constant OPCODE_NOT : unsigned(3 downto 0):="1001"; + constant OPCODE_FLIP : unsigned(3 downto 0):="1010"; + constant OPCODE_NOP : unsigned(3 downto 0):="1011"; + + constant OPCODE_STORE : unsigned(3 downto 0):="1100"; + constant OPCODE_POPSP : unsigned(3 downto 0):="1101"; + constant OPCODE_COMPARE : unsigned(3 downto 0):="1110"; + constant OPCODE_POPINT : unsigned(3 downto 0):="1111"; + + -- The following instructions are emulated in the small version and + -- implemented as hardware in the full version. + -- The constants correpond to the "emulated" instruction number. + + -- Enabled by the ENA_LEVEL0 generic: + constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6); + constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6); + constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6); + constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6); + -- Enabled by the ENA_LEVEL1 generic: + constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6); + constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6); + constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6); + constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6); + constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6); + constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6); + -- Enabled by the ENA_LEVEL2 generic: + constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6); + constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6); + constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6); + constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6); + -- Enabled by the ENA_LSHR generic: + constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6); + -- The following opcodes are always emulated. + constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6); + constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6); + constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6); + constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6); + constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6); + constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6); + constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6); + constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6); + constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6); + constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6); + constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6); + constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6); +end package zpupkg; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +package UART is + ---------------------- + -- Very simple UART -- + ---------------------- + component RxUnit is + port( + clk_i : in std_logic; -- System clock signal + reset_i : in std_logic; -- Reset input (sync) + enable_i : in std_logic; -- Enable input (rate*4) + read_i : in std_logic; -- Received Byte Read + rxd_i : in std_logic; -- RS-232 data input + rxav_o : out std_logic; -- Byte available + datao_o : out std_logic_vector(7 downto 0)); -- Byte received + end component RxUnit; + + component TxUnit is + port ( + clk_i : in std_logic; -- Clock signal + reset_i : in std_logic; -- Reset input + enable_i : in std_logic; -- Enable input + load_i : in std_logic; -- Load input + txd_o : out std_logic; -- RS-232 data output + busy_o : out std_logic; -- Tx Busy + datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit + end component TxUnit; + + component BRGen is + generic( + COUNT : integer range 0 to 65535);-- Count revolution + port ( + clk_i : in std_logic; -- Clock + reset_i : in std_logic; -- Reset input + ce_i : in std_logic; -- Chip Enable + o_o : out std_logic); -- Output + end component BRGen; +end package UART; + -- cgit v1.1