From 73c11e7ba18d3415d61d03c4a1da588fe77e0466 Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Sat, 22 Oct 2011 08:49:57 +0200 Subject: add: one more ZPU reference design for zealot --- .../zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh | 16 + .../zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh | 48 +++ .../avnet-eval-xc5vfx30t/simulation_config/run.do | 2 + .../avnet-eval-xc5vfx30t/simulation_config/wave.do | 26 ++ .../zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh | 36 ++ .../synthesis_config/avnet-eval-xc5vfx30t.ucf | 469 +++++++++++++++++++++ .../avnet-eval-xc5vfx30t/synthesis_config/top.prj | 18 + .../avnet-eval-xc5vfx30t/synthesis_config/top.ut | 39 ++ .../avnet-eval-xc5vfx30t/synthesis_config/top.xst | 60 +++ zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd | 411 ++++++++++++++++++ .../zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd | 268 ++++++++++++ 11 files changed, 1393 insertions(+) create mode 100755 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh create mode 100755 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh create mode 100644 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do create mode 100644 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do create mode 100755 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh create mode 100644 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf create mode 100644 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj create mode 100644 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut create mode 100644 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst create mode 100644 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd create mode 100644 zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd (limited to 'zpu/hdl/zealot') diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh new file mode 100755 index 0000000..3855f16 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/clean_up.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# ise build stuff +rm -rf build +rm -f top.bit + +# modelsim compile stuff +rm -rf work +rm -rf zpu + +# modelsim simulation stuff +rm -f vsim.wlf +rm -f transcript +rm -f zpu_trace.log +rm -f zpu_med1_io.log +rm -f zpu_small1_io.log diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh new file mode 100755 index 0000000..febf588 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation.sh @@ -0,0 +1,48 @@ +#!/bin/sh + +# need project files: +# run.do +# wave.do + +# need ModelSim tools: +# vlib +# vcom +# vsim + + +echo "###############" +echo "compile zpu lib" +echo "###############" +vlib zpu +vcom -work zpu ../../roms/hello_dbram.vhdl +vcom -work zpu ../../roms/hello_bram.vhdl +#vcom -work zpu ../../roms/dmips_dbram.vhdl +#vcom -work zpu ../../roms/dmips_bram.vhdl + +vcom -work zpu ../../roms/rom_pkg.vhdl +vcom -work zpu ../../zpu_pkg.vhdl +vcom -work zpu ../../zpu_small.vhdl +vcom -work zpu ../../zpu_medium.vhdl +vcom -work zpu ../../helpers/zpu_small1.vhdl +vcom -work zpu ../../helpers/zpu_med1.vhdl +vcom -work zpu ../../devices/txt_util.vhdl +vcom -work zpu ../../devices/phi_io.vhdl +vcom -work zpu ../../devices/timer.vhdl +vcom -work zpu ../../devices/rx_unit.vhdl +vcom -work zpu ../../devices/tx_unit.vhdl +vcom -work zpu ../../devices/br_gen.vhdl +vcom -work zpu ../../devices/trace.vhdl + + +echo "################" +echo "compile work lib" +echo "################" +vlib work +vcom top.vhd +vcom top_tb.vhd + + +echo "###################" +echo "start simulator gui" +echo "###################" +vsim -gui top_tb -do simulation_config/run.do diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do new file mode 100644 index 0000000..acc1710 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/run.do @@ -0,0 +1,2 @@ +do wave.do +run -all diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do new file mode 100644 index 0000000..20e68e0 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/simulation_config/wave.do @@ -0,0 +1,26 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /top_tb/tb_gpio_button(0) +add wave -noupdate /top_tb/tb_clk_100mhz +add wave -noupdate -divider +add wave -noupdate /top_tb/tb_rs232_rx +add wave -noupdate /top_tb/tb_rs232_tx +add wave -noupdate /top_tb/tb_rs232_rts +add wave -noupdate /top_tb/tb_rs232_cts +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 2 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {1188293312 ps} diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh new file mode 100755 index 0000000..d8d7603 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis.sh @@ -0,0 +1,36 @@ +#!/bin/sh + +# need project files: +# top.xst +# top.prj +# top.ut + +# need Xilinx tools: +# xst +# ngdbuild +# map +# par +# trce +# bitgen + +echo "########################" +echo "generate build directory" +echo "########################" +mkdir build +cd build +mkdir tmp + +echo "###############" +echo "start processes" +echo "###############" +xst -ifn "../synthesis_config/top.xst" -ofn "top.syr" +ngdbuild -dd _ngo -nt timestamp -uc ../synthesis_config/avnet-eval-xc5vfx30t.ucf -p xc5vfx30t-ff665-1 top.ngc top.ngd +map -p xc5vfx30t-ff665-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o top_map.ncd top.ngd top.pcf +par -w -ol high -mt off top_map.ncd top.ncd top.pcf +trce -v 3 -s 1 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf +bitgen -f ../synthesis_config/top.ut top.ncd + +echo "###########" +echo "get bitfile" +echo "###########" +cp top.bit .. diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf new file mode 100644 index 0000000..30b3982 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/avnet-eval-xc5vfx30t.ucf @@ -0,0 +1,469 @@ +############################################################ +# Avnet Virtex 5 FX Evaluation Board constraints file +# +# Familiy: Virtex5 +# Device: XC5VFX30T +# Package: FF665 +# Speed: -1 +# +# +# Bank 0 3.3V +# Bank 1 3.3V +# Bank 2 3.3V +# Bank 3 3.3V +# Bank 4 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V +# Bank 11 1.8V +# Bank 12 3.3V +# Bank 13 1.8V +# Bank 15 3.3V +# Bank 16 2.5V or 3.3V (JP3, VIO_EXP1_SE), here 2.5V +# Bank 17 1.8V +# Bank 18 2.5V or 3.3V (JP2, VIO_EXP1_DP), here 2.5V + + +############################################################ +## clock/timing constraints +############################################################ + +TIMESPEC "TS_clk_100" = PERIOD "clk_100" 100 MHz; + + +############################################################ +## pin placement constraints +############################################################ + +NET "clk_100MHz" LOC= E18 | IOSTANDARD = LVCMOS33 | TNM_NET = "clk_100"; +NET "clk_socket" LOC= E13 | IOSTANDARD = LVCMOS33; +NET "user_clk_p" LOC= AB15 ; +NET "user_clk_n" LOC= AC16 ; + +# RS232 +NET "RS232_RX" LOC= K8 | IOSTANDARD = LVCMOS33; +NET "RS232_TX" LOC= L8 | IOSTANDARD = LVCMOS33; +NET "RS232_RTS" LOC= N8 | IOSTANDARD = LVCMOS33; # Jumper J3 +NET "RS232_CTS" LOC= R8 | IOSTANDARD = LVCMOS33; # Jumper J4 + +# RS232_USB +NET "RS232_USB_RX" LOC= AA10 | IOSTANDARD = LVCMOS33; +NET "RS232_USB_TX" LOC= AA19 | IOSTANDARD = LVCMOS33; +NET "RS232_USB_reset_n" LOC= Y20 | IOSTANDARD = LVCMOS33; + +# GPIO LEDs, active low +NET "GPIO_LED_n<0>" LOC= AF22 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<1>" LOC= AF23 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<2>" LOC= AF25 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<3>" LOC= AE25 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<4>" LOC= AD25 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<5>" LOC= AE26 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<6>" LOC= AD26 | IOSTANDARD = LVCMOS18 | PULLUP; +NET "GPIO_LED_n<7>" LOC= AC26 | IOSTANDARD = LVCMOS18 | PULLUP; + +# GPIO DIP_Switches +NET "GPIO_DIPswitch<0>" LOC= AD13 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<1>" LOC= AE13 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<2>" LOC= AF13 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<3>" LOC= AD15 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<4>" LOC= AD14 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<5>" LOC= AF14 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<6>" LOC= AE15 | IOSTANDARD = LVCMOS18; +NET "GPIO_DIPswitch<7>" LOC= AF15 | IOSTANDARD = LVCMOS18; + +# Push Buttons +NET "GPIO_button<0>" LOC= AF20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB1 +NET "GPIO_button<1>" LOC= AE20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB2 +NET "GPIO_button<2>" LOC= AD19 | IOSTANDARD = LVCMOS18 | PULLUP; #PB3 +NET "GPIO_button<3>" LOC= AD20 | IOSTANDARD = LVCMOS18 | PULLUP; #PB4 + +# FLASH_8Mx16 +NET "FLASH_A<31>" LOC= Y11 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<30>" LOC= H9 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<29>" LOC= G10 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<28>" LOC= H21 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<27>" LOC= G20 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<26>" LOC= H11 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<25>" LOC= G11 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<24>" LOC= H19 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<23>" LOC= H18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<22>" LOC= G12 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<21>" LOC= F13 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<20>" LOC= G19 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<19>" LOC= F18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<18>" LOC= F14 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<17>" LOC= F15 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<16>" LOC= F17 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<15>" LOC= G17 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<14>" LOC= G14 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<13>" LOC= H13 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<12>" LOC= G16 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<11>" LOC= G15 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<10>" LOC= Y18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<9>" LOC= AA18 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<8>" LOC= Y10 | IOSTANDARD = LVCMOS33; +NET "FLASH_A<7>" LOC= W11 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<0>" LOC= AA15 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<1>" LOC= Y15 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<2>" LOC= W14 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<3>" LOC= Y13 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<4>" LOC= W16 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<5>" LOC= Y16 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<6>" LOC= AA14 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<7>" LOC= AA13 | IOSTANDARD = LVCMOS33; +NET "FLASH_DQ<8>" LOC= AB12 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<9>" LOC= AC11 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<10>" LOC= AB20 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<11>" LOC= AB21 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<12>" LOC= AB11 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<13>" LOC= AB10 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<14>" LOC= AA20 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_DQ<15>" LOC= Y21 | IOSTANDARD = LVCMOS25; # with level shifter +NET "FLASH_WEN" LOC= AA17 | IOSTANDARD = LVCMOS33; +NET "FLASH_OEN<0>" LOC= AA12 | IOSTANDARD = LVCMOS33; +NET "FLASH_CEN<0>" LOC= Y12 | IOSTANDARD = LVCMOS33; +NET "FLASH_rp_n" LOC= D13 | IOSTANDARD = LVCMOS33; +NET "FLASH_byte_n" LOC= Y17 | IOSTANDARD = LVCMOS33; +NET "FLASH_adv_n" LOC= F19 | IOSTANDARD = LVCMOS33; +NET "FLASH_clk" LOC= E12 | IOSTANDARD = LVCMOS33; +NET "FLASH_wait" LOC= D16 | IOSTANDARD = LVCMOS33; + +# DDR2_SDRAM_16Mx32 +NET "DDR2_ODT<0>" LOC= AF24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<0>" LOC= U25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<1>" LOC= T25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<2>" LOC= T24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<3>" LOC= T23 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<4>" LOC= U24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<5>" LOC= V24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<6>" LOC= Y23 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<7>" LOC= W23 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<8>" LOC= AA25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<9>" LOC= AB26 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<10>" LOC= AB25 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<11>" LOC= AB24 | IOSTANDARD = SSTL18_II; +NET "DDR2_A<12>" LOC= AA23 | IOSTANDARD = SSTL18_II; +NET "DDR2_BA<0>" LOC= U21 | IOSTANDARD = SSTL18_II; +NET "DDR2_BA<1>" LOC= V22 | IOSTANDARD = SSTL18_II; +NET "DDR2_CAS_N" LOC= W24 | IOSTANDARD = SSTL18_II; +NET "DDR2_CKE" LOC= T22 | IOSTANDARD = SSTL18_II; +NET "DDR2_CS_N" LOC= AD24 | IOSTANDARD = SSTL18_II; +NET "DDR2_RAS_N" LOC= Y22 | IOSTANDARD = SSTL18_II; +NET "DDR2_WE_N" LOC= AA22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<0>" LOC= U26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<1>" LOC= N24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<2>" LOC= M24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DM<3>" LOC= M25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<0>" LOC= W26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<1>" LOC= L23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<2>" LOC= K22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_P<3>" LOC= J21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<0>" LOC= W25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<1>" LOC= L22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<2>" LOC= K23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQS_N<3>" LOC= K21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<0>" LOC= R22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<1>" LOC= R23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<2>" LOC= P23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<3>" LOC= P24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<4>" LOC= R25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<5>" LOC= P25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<6>" LOC= R26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<7>" LOC= P26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<8>" LOC= M26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<9>" LOC= N26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<10>" LOC= K25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<11>" LOC= L24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<12>" LOC= K26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<13>" LOC= J26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<14>" LOC= J25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<15>" LOC= N21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<16>" LOC= M21 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<17>" LOC= J23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<18>" LOC= H23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<19>" LOC= H22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<20>" LOC= G22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<21>" LOC= F22 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<22>" LOC= F23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<23>" LOC= E23 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<24>" LOC= G24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<25>" LOC= F24 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<26>" LOC= G25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<27>" LOC= H26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<28>" LOC= G26 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<29>" LOC= F25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<30>" LOC= E25 | IOSTANDARD = SSTL18_II; +NET "DDR2_DQ<31>" LOC= E26 | IOSTANDARD = SSTL18_II; +NET "DDR2_CK_p<0>" LOC= V21 | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CK_p<1>" LOC= N22 | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CK_n<0>" LOC= W21 | IOSTANDARD = DIFF_SSTL18_II; +NET "DDR2_CK_n<1>" LOC= M22 | IOSTANDARD = DIFF_SSTL18_II; + +# Ethernet MAC +NET "GMII_txer" LOC= A22 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_clk" LOC= E17 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps; +NET "GMII_rx_clk" LOC= E20 | IOSTANDARD = LVCMOS33 | PERIOD=40000 ps; +NET "GMII_gtc_clk" LOC= A19 | IOSTANDARD = LVCMOS33; +NET "GMII_crs" LOC= A25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_dv" LOC= C21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<0>" LOC= D24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<1>" LOC= D23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<2>" LOC= D21 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<3>" LOC= C26 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<4>" LOC= D20 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<5>" LOC= C23 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<6>" LOC= B25 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_data<7>" LOC= C22 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_col" LOC= A24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_rx_er" LOC= B24 | IOSTANDARD = LVCMOS33 | IOBDELAY=NONE; +NET "GMII_tx_en" LOC= A23 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<0>" LOC= D19 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<1>" LOC= C19 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<2>" LOC= A20 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<3>" LOC= B20 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<4>" LOC= B19 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<5>" LOC= A15 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<6>" LOC= B22 | IOSTANDARD = LVCMOS33; +NET "GMII_tx_data<7>" LOC= B21 | IOSTANDARD = LVCMOS33; +NET "GBE_rst_n" LOC= B26 | IOSTANDARD = LVCMOS33; +NET "GBE_mdc" LOC= D26 | IOSTANDARD = LVCMOS33; +NET "GBE_mdio" LOC= D25 | IOSTANDARD = LVCMOS33; +NET "GBE_int_n" LOC= C24 | IOSTANDARD = LVCMOS33; +NET "GBE_mclk" LOC= F20 | IOSTANDARD = LVCMOS33; + +# SysACE CompactFlash +NET "SAM_CLK" LOC= F12 | IOSTANDARD = LVCMOS33; +NET "SAM_A<0>" LOC= Y5 | IOSTANDARD = LVCMOS33; +NET "SAM_A<1>" LOC= V7 | IOSTANDARD = LVCMOS33; +NET "SAM_A<2>" LOC= W6 | IOSTANDARD = LVCMOS33; +NET "SAM_A<3>" LOC= W5 | IOSTANDARD = LVCMOS33; +NET "SAM_A<4>" LOC= K6 | IOSTANDARD = LVCMOS33; +NET "SAM_A<5>" LOC= J5 | IOSTANDARD = LVCMOS33; +NET "SAM_A<6>" LOC= J6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<0>" LOC= F5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<1>" LOC= U7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<2>" LOC= V6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<3>" LOC= U5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<4>" LOC= U6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<5>" LOC= T5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<6>" LOC= T7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<7>" LOC= R6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<8>" LOC= R7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<9>" LOC= R5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<10>" LOC= P6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<11>" LOC= P8 | IOSTANDARD = LVCMOS33; +NET "SAM_D<12>" LOC= N6 | IOSTANDARD = LVCMOS33; +NET "SAM_D<13>" LOC= M7 | IOSTANDARD = LVCMOS33; +NET "SAM_D<14>" LOC= K5 | IOSTANDARD = LVCMOS33; +NET "SAM_D<15>" LOC= L7 | IOSTANDARD = LVCMOS33; +NET "SAM_CEN" LOC= G4 | IOSTANDARD = LVCMOS33; +NET "SAM_OEN" LOC= Y6 | IOSTANDARD = LVCMOS33; +NET "SAM_WEN" LOC= Y4 | IOSTANDARD = LVCMOS33; +NET "SAM_MPIRQ" LOC= H4 | IOSTANDARD = LVCMOS33; +NET "SAM_BRDY" LOC= G5 | IOSTANDARD = LVCMOS33; +NET "SAM_RESET_n" LOC= H6 | IOSTANDARD = LVCMOS33; + +# Expansion Header +NET "EXP1_SE_IO<0>" LOC= A8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<1>" LOC= A12 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<2>" LOC= B10 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<3>" LOC= A10 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<4>" LOC= B9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<5>" LOC= A9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<6>" LOC= A5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<7>" LOC= B11 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<8>" LOC= B6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<9>" LOC= A7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<10>" LOC= D8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<11>" LOC= C9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<12>" LOC= B7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<13>" LOC= A4 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<14>" LOC= B5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<15>" LOC= C8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<16>" LOC= C7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<17>" LOC= A3 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<18>" LOC= C6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<19>" LOC= B4 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<20>" LOC= D6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<21>" LOC= D9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<22>" LOC= E8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<23>" LOC= D5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<24>" LOC= F7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<25>" LOC= E7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<26>" LOC= E5 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<27>" LOC= E6 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<28>" LOC= F8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<29>" LOC= H7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<30>" LOC= G7 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<31>" LOC= H8 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<32>" LOC= G9 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_IO<33>" LOC= J8 | IOSTANDARD = LVCMOS25; +NET "EXP1_DIFF_P<0>" LOC= AF9 ; +NET "EXP1_DIFF_N<0>" LOC= AF10 ; +NET "EXP1_DIFF_P<1>" LOC= AF12 ; +NET "EXP1_DIFF_N<1>" LOC= AE12 ; +NET "EXP1_DIFF_P<2>" LOC= AF7 ; +NET "EXP1_DIFF_N<2>" LOC= AF8 ; +NET "EXP1_DIFF_P<3>" LOC= AE11 ; +NET "EXP1_DIFF_N<3>" LOC= AD11 ; +NET "EXP1_DIFF_P<4>" LOC= AF4 ; +NET "EXP1_DIFF_N<4>" LOC= AF3 ; +NET "EXP1_DIFF_P<5>" LOC= AD10 ; +NET "EXP1_DIFF_N<5>" LOC= AE10 ; +NET "EXP1_DIFF_P<6>" LOC= AE8 ; +NET "EXP1_DIFF_N<6>" LOC= AE7 ; +NET "EXP1_DIFF_P<7>" LOC= AC8 ; +NET "EXP1_DIFF_N<7>" LOC= AD8 ; +NET "EXP1_DIFF_P<8>" LOC= AD9 ; +NET "EXP1_DIFF_N<8>" LOC= AC9 ; +NET "EXP1_DIFF_P<9>" LOC= AE6 ; +NET "EXP1_DIFF_N<9>" LOC= AF5 ; +NET "EXP1_DIFF_P<10>" LOC= AB6 ; +NET "EXP1_DIFF_N<10>" LOC= AB7 ; +NET "EXP1_DIFF_P<11>" LOC= AC6 ; +NET "EXP1_DIFF_N<11>" LOC= AD5 ; +NET "EXP1_DIFF_P<12>" LOC= AD6 ; +NET "EXP1_DIFF_N<12>" LOC= AC7 ; +NET "EXP1_DIFF_P<13>" LOC= AE5 ; +NET "EXP1_DIFF_N<13>" LOC= AD4 ; +NET "EXP1_DIFF_P<14>" LOC= AB9 ; +NET "EXP1_DIFF_N<14>" LOC= AA9 ; +NET "EXP1_DIFF_P<15>" LOC= AC12 ; +NET "EXP1_DIFF_N<15>" LOC= AC13 ; +NET "EXP1_DIFF_P<16>" LOC= AA7 ; +NET "EXP1_DIFF_N<16>" LOC= AA8 ; +NET "EXP1_DIFF_P<17>" LOC= AA5 ; +NET "EXP1_DIFF_N<17>" LOC= AB5 ; +NET "EXP1_DIFF_P<18>" LOC= AB19 ; +NET "EXP1_DIFF_N<18>" LOC= AC19 ; +NET "EXP1_DIFF_P<19>" LOC= Y7 ; +NET "EXP1_DIFF_N<19>" LOC= Y8 ; +NET "EXP1_DIFF_P<20>" LOC= W9 ; +NET "EXP1_DIFF_N<20>" LOC= W8 ; +NET "EXP1_DIFF_P<21>" LOC= V8 ; +NET "EXP1_DIFF_N<21>" LOC= V9 ; +NET "EXP1_SE_CLK_OUT" LOC= B12 | IOSTANDARD = LVCMOS25; +NET "EXP1_SE_CLK_IN" LOC= E10 | IOSTANDARD = LVCMOS33; +NET "EXP1_DIFF_CLK_OUT_P" LOC= AC18 ; +NET "EXP1_DIFF_CLK_OUT_N" LOC= AB17 ; +NET "EXP1_DIFF_CLK_IN_P" LOC= AB14 ; +NET "EXP1_DIFF_CLK_IN_N" LOC= AC14 ; +#NET "EXP1_RCLK_DIFF_P" LOC= AB6 ; +#NET "EXP1_RCLK_DIFF_N" LOC= AB7 ; + +# CPU Debug Trace +NET "ATDD<8>" LOC= C16 | IOSTANDARD = LVCMOS33; +NET "ATDD<9>" LOC= A17 | IOSTANDARD = LVCMOS33; +NET "ATDD<10>" LOC= B15 | IOSTANDARD = LVCMOS33; +NET "ATDD<11>" LOC= E15 | IOSTANDARD = LVCMOS33; +NET "ATDD<12>" LOC= A14 | IOSTANDARD = LVCMOS33; +NET "ATDD<13>" LOC= D18 | IOSTANDARD = LVCMOS33; +NET "ATDD<14>" LOC= A13 | IOSTANDARD = LVCMOS33; +NET "ATDD<15>" LOC= C13 | IOSTANDARD = LVCMOS33; +NET "ATDD<16>" LOC= D14 | IOSTANDARD = LVCMOS33; +NET "ATDD<17>" LOC= C17 | IOSTANDARD = LVCMOS33; +NET "ATDD<18>" LOC= E16 | IOSTANDARD = LVCMOS33; +NET "ATDD<19>" LOC= C14 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS10" LOC= B16 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS20" LOC= E21 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS1E" LOC= B14 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS2E" LOC= B17 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS3" LOC= C18 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS4" LOC= G21 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS5" LOC= A18 | IOSTANDARD = LVCMOS33; +NET "TRACE_TS6" LOC= F10 | IOSTANDARD = LVCMOS33; +NET "TRACE_CLK" LOC= D15 | IOSTANDARD = LVCMOS33; +NET "CPU_HRESET" LOC= E11 | IOSTANDARD = LVCMOS33; +NET "CPU_TDO" LOC= K7 | IOSTANDARD = LVCMOS33; +NET "CPU_TMS" LOC= L5 | IOSTANDARD = LVCMOS33; +NET "CPU_TDI" LOC= M6 | IOSTANDARD = LVCMOS33; +NET "CPU_TRST" LOC= N7 | IOSTANDARD = LVCMOS33; +NET "CPU_TCK" LOC= T8 | IOSTANDARD = LVCMOS33; +NET "CPU_HALT_n" LOC= W4 | IOSTANDARD = LVCMOS33; + + +# voltage termination +CONFIG PROHIBIT = AA24; +CONFIG PROHIBIT = AE23; +CONFIG PROHIBIT = AF17; +CONFIG PROHIBIT = V26; +CONFIG PROHIBIT = E22; +CONFIG PROHIBIT = L25; + +# unused pins +CONFIG PROHIBIT = F9; +CONFIG PROHIBIT = D10; +CONFIG PROHIBIT = C12; +CONFIG PROHIBIT = C11; +CONFIG PROHIBIT = D11; +CONFIG PROHIBIT = AB16; +CONFIG PROHIBIT = AB22; +CONFIG PROHIBIT = AC17; +CONFIG PROHIBIT = AC21; +CONFIG PROHIBIT = AE22; +CONFIG PROHIBIT = AD23; +CONFIG PROHIBIT = AC24; +CONFIG PROHIBIT = AC23; +CONFIG PROHIBIT = AC22; +CONFIG PROHIBIT = AB22; +CONFIG PROHIBIT = AE21; +CONFIG PROHIBIT = AD21; +CONFIG PROHIBIT = AF19; +CONFIG PROHIBIT = AF18; +CONFIG PROHIBIT = AE18; +CONFIG PROHIBIT = AD18; +CONFIG PROHIBIT = AE17; +CONFIG PROHIBIT = AE16; +CONFIG PROHIBIT = AD16; +CONFIG PROHIBIT = G6; +CONFIG PROHIBIT = H24; +CONFIG PROHIBIT = J24; +CONFIG PROHIBIT = N23; +CONFIG PROHIBIT = N15; +CONFIG PROHIBIT = P14; +CONFIG PROHIBIT = V23; +CONFIG PROHIBIT = Y26; +CONFIG PROHIBIT = Y25; +CONFIG PROHIBIT = P21; +CONFIG PROHIBIT = R21; +CONFIG PROHIBIT = U22; + +# grounded pins from gigabit transcievers +CONFIG PROHIBIT = K4; +CONFIG PROHIBIT = K3; +CONFIG PROHIBIT = J1; +CONFIG PROHIBIT = K1; +CONFIG PROHIBIT = M1; +CONFIG PROHIBIT = L1; +CONFIG PROHIBIT = T3; +CONFIG PROHIBIT = T4; +CONFIG PROHIBIT = R1; +CONFIG PROHIBIT = T1; +CONFIG PROHIBIT = V1; +CONFIG PROHIBIT = U1; +CONFIG PROHIBIT = D3; +CONFIG PROHIBIT = D4; +CONFIG PROHIBIT = C1; +CONFIG PROHIBIT = D1; +CONFIG PROHIBIT = E1; +CONFIG PROHIBIT = F1; +CONFIG PROHIBIT = AB3; +CONFIG PROHIBIT = AB4; +CONFIG PROHIBIT = AA1; +CONFIG PROHIBIT = AB1; +CONFIG PROHIBIT = AC1; +CONFIG PROHIBIT = AD1; +CONFIG PROHIBIT = H2; +CONFIG PROHIBIT = J2; +CONFIG PROHIBIT = N2; +CONFIG PROHIBIT = M2; +CONFIG PROHIBIT = P2; +CONFIG PROHIBIT = R2; +CONFIG PROHIBIT = V2; +CONFIG PROHIBIT = W2; +CONFIG PROHIBIT = B2; +CONFIG PROHIBIT = C2; +CONFIG PROHIBIT = G2; +CONFIG PROHIBIT = F2; +CONFIG PROHIBIT = Y2; +CONFIG PROHIBIT = AA2; +CONFIG PROHIBIT = AD2; +CONFIG PROHIBIT = AE2; + diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj new file mode 100644 index 0000000..81d56ef --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.prj @@ -0,0 +1,18 @@ +vhdl work ../top.vhd +vhdl zpu ../../../zpu_pkg.vhdl +vhdl zpu ../../../zpu_small.vhdl +vhdl zpu ../../../zpu_medium.vhdl +vhdl zpu ../../../roms/rom_pkg.vhdl +#vhdl zpu ../../../roms/hello_dbram.vhdl +#vhdl zpu ../../../roms/hello_bram.vhdl +vhdl zpu ../../../roms/dmips_dbram.vhdl +vhdl zpu ../../../roms/dmips_bram.vhdl +vhdl zpu ../../../helpers/zpu_small1.vhdl +vhdl zpu ../../../helpers/zpu_med1.vhdl +vhdl zpu ../../../devices/txt_util.vhdl +vhdl zpu ../../../devices/phi_io.vhdl +vhdl zpu ../../../devices/timer.vhdl +vhdl zpu ../../../devices/rx_unit.vhdl +vhdl zpu ../../../devices/tx_unit.vhdl +vhdl zpu ../../../devices/br_gen.vhdl +vhdl zpu ../../../devices/trace.vhdl diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut new file mode 100644 index 0000000..e0159fb --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.ut @@ -0,0 +1,39 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:2 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g HswapenPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ConfigFallback:Enable +-g SelectMAPAbort:Enable +-g BPI_page_size:1 +-g OverTempPowerDown:Disable +-g JTAG_SysMon:Enable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Match_cycle:Auto +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst new file mode 100644 index 0000000..7ca54bc --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/synthesis_config/top.xst @@ -0,0 +1,60 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../synthesis_config/top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc5vfx30t-1-ff665 +-top top +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Off +-reduce_control_sets Off +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 32 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd new file mode 100644 index 0000000..1e2fa97 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top.vhd @@ -0,0 +1,411 @@ +-- top module of +-- Avnet Virtex 5 FX Evaluation Board +-- +-- using following external connections: +-- pushbutton PB1 as reset +-- LEDs for output +-- RS232 (non USB) +-- + + +library ieee; +use ieee.std_logic_1164.all; + +library zpu; +use zpu.zpupkg.all; -- zpu_dbgo_t + +library unisim; +use unisim.vcomponents.ibufds; +use unisim.vcomponents.dcm_base; + + +entity top is + port ( + -- pragma translate_off + stop_simulation : out std_logic; + -- pragma translate_on + clk_100MHz : in std_logic; -- 100 MHz clock + clk_socket : in std_logic; -- user clock + user_clk_p : in std_logic; -- differential user clock + user_clk_n : in std_logic; -- differential user clock + -- + -- RS232 + rs232_rx : in std_logic; + rs232_tx : out std_logic; + rs232_rts : in std_logic; + rs232_cts : out std_logic; + -- RS232 USB + rs232_usb_rx : in std_logic; + rs232_usb_tx : out std_logic; + rs232_usb_reset_n : out std_logic; + -- + gpio_led_n : out std_logic_vector(7 downto 0); + gpio_dipswitch : in std_logic_vector(7 downto 0); + gpio_button : in std_logic_vector(3 downto 0); + -- + -- FLASH 8Mx16 + flash_a : out std_logic_vector(31 downto 7); + flash_dq : inout std_logic_vector(15 downto 0); + flash_wen : out std_logic; + flash_oen : out std_logic_vector(0 downto 0); + flash_cen : out std_logic_vector(0 downto 0); + flash_rp_n : out std_logic; + flash_byte_n : out std_logic; + flash_adv_n : out std_logic; + flash_clk : out std_logic; + flash_wait : in std_logic; + -- + -- DDR2 SDRAM 16Mx32 + ddr2_odt : in std_logic_vector(0 downto 0); + ddr2_a : out std_logic_vector(12 downto 0); + ddr2_ba : out std_logic_vector(1 downto 0); + ddr2_cas_n : out std_logic; + ddr2_cke : out std_logic; + ddr2_cs_n : out std_logic; + ddr2_ras_n : out std_logic; + ddr2_we_n : out std_logic; + ddr2_dm : out std_logic_vector(3 downto 0); + ddr2_dqs_p : inout std_logic_vector(3 downto 0); + ddr2_dqs_n : inout std_logic_vector(3 downto 0); + ddr2_dq : inout std_logic_vector(31 downto 0); + ddr2_ck_p : in std_logic_vector(1 downto 0); + ddr2_ck_n : in std_logic_vector(1 downto 0); + -- + -- Ethernet MAC + gmii_txer : out std_logic; + gmii_tx_clk : in std_logic; -- 25 MHz + gmii_rx_clk : in std_logic; -- 25 MHz + gmii_gtc_clk : out std_logic; + gmii_crs : in std_logic; + gmii_dv : in std_logic; + gmii_rx_data : in std_logic_vector(7 downto 0); + gmii_col : in std_logic; + gmii_rx_er : in std_logic; + gmii_tx_en : out std_logic; + gmii_tx_data : out std_logic_vector(7 downto 0); + gbe_rst_n : out std_logic; + gbe_mdc : out std_logic; + gbe_mdio : inout std_logic; + gbe_int_n : inout std_logic; + gbe_mclk : in std_logic; + -- + -- SysACE CompactFlash + sam_clk : in std_logic; + sam_a : out std_logic_vector(6 downto 0); + sam_d : inout std_logic_vector(15 downto 0); + sam_cen : out std_logic; + sam_oen : out std_logic; + sam_wen : out std_logic; + sam_mpirq : in std_logic; + sam_brdy : in std_logic; + sam_reset_n : out std_logic; + -- + -- Expansion Header + exp1_se_io : inout std_logic_vector(33 downto 0); + exp1_diff_p : inout std_logic_vector(21 downto 0); + exp1_diff_n : inout std_logic_vector(21 downto 0); + exp1_se_clk_out : out std_logic; + exp1_se_clk_in : in std_logic; + exp1_diff_clk_out_p : out std_logic; + exp1_diff_clk_out_n : out std_logic; + exp1_diff_clk_in_p : in std_logic; + exp1_diff_clk_in_n : in std_logic; + -- + -- Debug/Trace + atdd : inout std_logic_vector(19 downto 8); + trace_ts10 : inout std_logic; + trace_ts20 : inout std_logic; + trace_ts1e : inout std_logic; + trace_ts2e : inout std_logic; + trace_ts3 : inout std_logic; + trace_ts4 : inout std_logic; + trace_ts5 : inout std_logic; + trace_ts6 : inout std_logic; + trace_clk : in std_logic; + cpu_hreset : in std_logic; + cpu_tdo : out std_logic; + cpu_tms : in std_logic; + cpu_tdi : in std_logic; + cpu_trst : in std_logic; + cpu_tck : in std_logic; + cpu_halt_n : in std_logic + ); +end entity top; + + +architecture rtl of top is + + --------------------------- + -- type declarations + type zpu_type is (zpu_small, zpu_medium); + + --------------------------- + -- constant declarations + constant zpu_flavour : zpu_type := zpu_medium; -- choose your flavour HERE + -- modify frequency here + constant clk_multiply : positive := 5; -- 7 for small, 5 for medium + constant clk_divide : positive := 4; -- 4 for small, 4 for medium + -- + -- + constant word_size_c : natural := 32; -- 32 bits data path + constant addr_w_c : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + -- + constant clk_frequency : positive := 100; -- input frequency for correct calculation + + --------------------------- + -- component declarations + component zpu_small1 is + generic ( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 16; -- 16 bits address space=64 kB, 32 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port ( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic -- UART Rx + ); + end component zpu_small1; + + component zpu_med1 is + generic( + word_size : natural := 32; -- 32 bits data path + d_care_val : std_logic := '0'; -- Fill value + clk_freq : positive := 50; -- 50 MHz clock + brate : positive := 115200; -- RS232 baudrate + addr_w : natural := 18; -- 18 bits address space=256 kB, 128 kB I/O + bram_w : natural := 15 -- 15 bits RAM space=32 kB + ); + port( + clk_i : in std_logic; -- CPU clock + rst_i : in std_logic; -- Reset + break_o : out std_logic; -- Break executed + dbg_o : out zpu_dbgo_t; -- Debug info + rs232_tx_o : out std_logic; -- UART Tx + rs232_rx_i : in std_logic -- UART Rx + ); + end component zpu_med1; + + + + --------------------------- + -- signal declarations + signal sys_clk : std_ulogic; + signal dcm_base_i0_clk0 : std_ulogic; + signal dcm_base_i0_clkfx : std_ulogic; + signal clk_fb : std_ulogic; + signal clk : std_ulogic; + -- + signal reset_shift_reg : std_ulogic_vector(3 downto 0); + signal reset_sync : std_ulogic; + -- + signal zpu_i0_dbg : zpu_dbgo_t; -- Debug info + signal zpu_i0_break : std_logic; + -- + signal ibufds_i0_o : std_ulogic; + signal ibufds_i1_o : std_ulogic; + +begin + + -- default output drivers + -- to pass bitgen DRC + -- other used outputs are only commented + --rs232_tx <= '1'; + rs232_cts <= '1'; + rs232_usb_tx <= '1'; + rs232_usb_reset_n <= '1'; + -- + --gpio_led_n <= (others => '1'); + -- + flash_cen <= "1"; + flash_oen <= "1"; + flash_wen <= '1'; + flash_rp_n <= '1'; + flash_byte_n <= '1'; + flash_adv_n <= '1'; + flash_clk <= '0'; + flash_a <= (others => '0'); + flash_dq <= (others => 'Z'); + -- + ddr2_a <= (others => '0'); + ddr2_ba <= (others => '0'); + ddr2_dm <= (others => '0'); + ddr2_cs_n <= '1'; + ddr2_we_n <= '1'; + ddr2_cke <= '1'; + ddr2_cas_n <= '1'; + ddr2_ras_n <= '1'; + ddr2_dqs_p <= (others => 'Z'); + ddr2_dqs_n <= (others => 'Z'); + ddr2_dq <= (others => 'Z'); + -- + gmii_gtc_clk <= '0'; + gmii_tx_data <= (others => '0'); + gmii_tx_en <= '0'; + gmii_txer <= '0'; + gbe_rst_n <= '1'; + gbe_mdc <= '1'; + gbe_mdio <= 'Z'; + gbe_int_n <= 'Z'; + -- + sam_cen <= '1'; + sam_oen <= '1'; + sam_wen <= '1'; + sam_a <= (others => '0'); + sam_d <= (others => 'Z'); + sam_reset_n <= '1'; + -- + exp1_se_io <= (others => 'Z'); + exp1_diff_p <= (others => 'Z'); + exp1_diff_n <= (others => 'Z'); + exp1_se_clk_out <= '0'; + exp1_diff_clk_out_p <= '0'; + exp1_diff_clk_out_n <= '1'; + -- + atdd <= (others => 'Z'); + trace_ts10 <= 'Z'; + trace_ts20 <= 'Z'; + trace_ts1e <= 'Z'; + trace_ts2e <= 'Z'; + trace_ts3 <= 'Z'; + trace_ts4 <= 'Z'; + trace_ts5 <= 'Z'; + trace_ts6 <= 'Z'; + cpu_tdo <= '1'; + + + -- global differential input buffer + ibufds_i0 : ibufds + generic map ( + diff_term => true + ) + port map ( + o => ibufds_i0_o, + i => ddr2_ck_p(0), + ib => ddr2_ck_n(0) + ); + + -- global differential input buffer + ibufds_i1 : ibufds + generic map ( + diff_term => true + ) + port map ( + o => ibufds_i1_o, + i => ddr2_ck_p(1), + ib => ddr2_ck_n(1) + ); + + -- digital clock manager (DCM) + -- to generate higher/other system clock frequencys + dcm_base_i0: dcm_base + generic map ( + startup_wait => true, -- wait with DONE till locked + --dfs_frequency_mode => "HIGH", -- use this with zpu_small for 175 MHz + clkfx_multiply => clk_multiply, + clkfx_divide => clk_divide, + clk_feedback => "1X" + ) + port map ( + rst => '0', + clkin => clk_100MHz, + clk0 => dcm_base_i0_clk0, + clkfx => dcm_base_i0_clkfx, + clkfb => clk_fb + ); + + -- speaking names for dcm output + clk_fb <= dcm_base_i0_clk0; + clk <= dcm_base_i0_clkfx; + + + -- reset synchronizer + -- generate synchronous reset + reset_synchronizer : process(clk, gpio_button) + begin + if (gpio_button(0) = '1') then + reset_shift_reg <= (others => '1'); + elsif rising_edge(clk) then + reset_shift_reg <= reset_shift_reg(reset_shift_reg'high-1 downto 0) & '0'; + end if; + end process; + reset_sync <= reset_shift_reg(reset_shift_reg'high); + + + + -- select instance of zpu + zpu_i0_small: if zpu_flavour = zpu_small generate + zpu_i0 : zpu_small1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; - CPU clock + rst_i => reset_sync, -- : in std_logic; - Reset + break_o => zpu_i0_break, -- : out std_logic; - Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx + rs232_rx_i => rs232_rx -- : in std_logic - UART Rx + ); + end generate zpu_i0_small; + + zpu_i0_medium: if zpu_flavour = zpu_medium generate + zpu_i0 : zpu_med1 + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + clk_freq => clk_frequency * clk_multiply / clk_divide + ) + port map ( + clk_i => clk, -- : in std_logic; - CPU clock + rst_i => reset_sync, -- : in std_logic; - Reset + break_o => zpu_i0_break, -- : out std_logic; - Break executed + dbg_o => zpu_i0_dbg, -- : out zpu_dbgo_t; - Debug info + rs232_tx_o => rs232_tx, -- : out std_logic; - UART Tx + rs232_rx_i => rs232_rx -- : in std_logic - UART Rx + ); + end generate zpu_i0_medium; + + -- pragma translate_off + stop_simulation <= zpu_i0_break; -- abort() causes to stop the simulation + + + trace_mod : trace + generic map ( + addr_w => addr_w_c, + word_size => word_size_c, + log_file => "zpu_trace.log" + ) + port map ( + clk_i => clk, + dbg_i => zpu_i0_dbg, + stop_i => zpu_i0_break, + busy_i => '0' + ); + -- pragma translate_on + + + -- switch on all LEDs in case of break + process + begin + wait until rising_edge(clk); + if zpu_i0_break = '1' then + gpio_led_n <= (others => '0'); + end if; + if reset_sync = '1' then + gpio_led_n <= (others => '1'); + end if; + end process; + + + +end architecture rtl; + diff --git a/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd new file mode 100644 index 0000000..0d173e2 --- /dev/null +++ b/zpu/hdl/zealot/fpga/avnet-eval-xc5vfx30t/top_tb.vhd @@ -0,0 +1,268 @@ +-- testbench for +-- Avnet Virtex 5 FX Evaluation Board +-- +-- includes "model" for clock generation +-- simulate press on gpio_button(0) (=PB1) as reset +-- +-- place models for external components (PHY, DDR2-RAM) in this file +-- + + +library ieee; +use ieee.std_logic_1164.all; + + +entity top_tb is +end entity top_tb; + +architecture testbench of top_tb is + + --------------------------- + -- constant declarations + constant clk_100MHz_period : time := 1 sec / 100_000_000; -- 100 MHz + + + --------------------------- + -- signal declarations + signal simulation_run : boolean := true; + signal tb_stop_simulation : std_logic; + -- + signal tb_clk_100MHz : std_logic := '0'; -- 100 MHz clock + signal tb_clk_socket : std_logic := '0'; -- user clock + signal tb_user_clk_p : std_logic := '0'; -- diff user clock + signal tb_user_clk_n : std_logic := '0'; -- diff user clock + -- + -- RS232 + signal tb_rs232_rx : std_logic := '0'; + signal tb_rs232_tx : std_logic; + signal tb_rs232_rts : std_logic := '0'; + signal tb_rs232_cts : std_logic; + -- RS232 USB + signal tb_rs232_usb_rx : std_logic := '0'; + signal tb_rs232_usb_tx : std_logic; + signal tb_rs232_usb_reset_n : std_logic; + -- + signal tb_gpio_led_n : std_logic_vector(7 downto 0); + signal tb_gpio_dipswitch : std_logic_vector(7 downto 0) := (others => '0'); + signal tb_gpio_button : std_logic_vector(3 downto 0) := (others => '0'); + -- + -- FLASH 8Mx16 + signal tb_flash_a : std_logic_vector(31 downto 7); + signal tb_flash_dq : std_logic_vector(15 downto 0); + signal tb_flash_wen : std_logic; + signal tb_flash_oen : std_logic_vector(0 downto 0); + signal tb_flash_cen : std_logic_vector(0 downto 0); + signal tb_flash_rp_n : std_logic; + signal tb_flash_byte_n : std_logic; + signal tb_flash_adv_n : std_logic; + signal tb_flash_clk : std_logic; + signal tb_flash_wait : std_logic := '0'; + -- + -- DDR2 SDRAM 16Mx32 + signal tb_ddr2_odt : std_logic_vector(0 downto 0) := (others => '0'); + signal tb_ddr2_a : std_logic_vector(12 downto 0); + signal tb_ddr2_ba : std_logic_vector(1 downto 0); + signal tb_ddr2_cas_n : std_logic; + signal tb_ddr2_cke : std_logic; + signal tb_ddr2_cs_n : std_logic; + signal tb_ddr2_ras_n : std_logic; + signal tb_ddr2_we_n : std_logic; + signal tb_ddr2_dm : std_logic_vector(3 downto 0); + signal tb_ddr2_dqs_p : std_logic_vector(3 downto 0); + signal tb_ddr2_dqs_n : std_logic_vector(3 downto 0); + signal tb_ddr2_dq : std_logic_vector(31 downto 0); + signal tb_ddr2_ck_p : std_logic_vector(1 downto 0) := (others => '0'); + signal tb_ddr2_ck_n : std_logic_vector(1 downto 0) := (others => '0'); + -- + -- Ethernet MAC + signal tb_gmii_txer : std_logic; + signal tb_gmii_tx_clk : std_logic := '0'; -- 25 MHz + signal tb_gmii_rx_clk : std_logic := '0'; -- 25 MHz + signal tb_gmii_gtc_clk : std_logic; + signal tb_gmii_crs : std_logic := '0'; + signal tb_gmii_dv : std_logic := '0'; + signal tb_gmii_rx_data : std_logic_vector(7 downto 0); + signal tb_gmii_col : std_logic := '0'; + signal tb_gmii_rx_er : std_logic := '0'; + signal tb_gmii_tx_en : std_logic; + signal tb_gmii_tx_data : std_logic_vector(7 downto 0); + signal tb_gbe_rst_n : std_logic; + signal tb_gbe_mdc : std_logic; + signal tb_gbe_mdio : std_logic; + signal tb_gbe_int_n : std_logic; + signal tb_gbe_mclk : std_logic := '0'; + -- + -- SysACE CompactFlash + signal tb_sam_clk : std_logic := '0'; + signal tb_sam_a : std_logic_vector(6 downto 0); + signal tb_sam_d : std_logic_vector(15 downto 0); + signal tb_sam_cen : std_logic; + signal tb_sam_oen : std_logic; + signal tb_sam_wen : std_logic; + signal tb_sam_mpirq : std_logic := '0'; + signal tb_sam_brdy : std_logic := '0'; + signal tb_sam_reset_n : std_logic; + -- + -- Expansion Header + signal tb_exp1_se_io : std_logic_vector(33 downto 0); + signal tb_exp1_diff_p : std_logic_vector(21 downto 0); + signal tb_exp1_diff_n : std_logic_vector(21 downto 0); + signal tb_exp1_se_clk_out : std_logic; + signal tb_exp1_se_clk_in : std_logic := '0'; + signal tb_exp1_diff_clk_out_p : std_logic; + signal tb_exp1_diff_clk_out_n : std_logic; + signal tb_exp1_diff_clk_in_p : std_logic := '0'; + signal tb_exp1_diff_clk_in_n : std_logic := '0'; + -- + -- Debug/Trace + signal tb_atdd : std_logic_vector(19 downto 8); + signal tb_trace_ts10 : std_logic; + signal tb_trace_ts20 : std_logic; + signal tb_trace_ts1e : std_logic; + signal tb_trace_ts2e : std_logic; + signal tb_trace_ts3 : std_logic; + signal tb_trace_ts4 : std_logic; + signal tb_trace_ts5 : std_logic; + signal tb_trace_ts6 : std_logic; + signal tb_trace_clk : std_logic := '0'; + signal tb_cpu_hreset : std_logic := '0'; + signal tb_cpu_tdo : std_logic; + signal tb_cpu_tms : std_logic := '0'; + signal tb_cpu_tdi : std_logic := '0'; + signal tb_cpu_trst : std_logic := '0'; + signal tb_cpu_tck : std_logic := '0'; + signal tb_cpu_halt_n : std_logic := '0'; + + +begin + + + -- generate clocks + tb_clk_100MHz <= not tb_clk_100MHz after clk_100MHz_period / 2 when simulation_run; + + -- generate reset + tb_gpio_button(0) <= '1', '0' after 6.66 * clk_100MHz_period; + + + -- dut + top_i0 : entity work.top + port map ( + stop_simulation => tb_stop_simulation, -- : out std_logic; + clk_100MHz => tb_clk_100MHz, -- : in std_logic; + clk_socket => tb_clk_socket, -- : in std_logic; + user_clk_p => tb_user_clk_p, -- : in std_logic; + user_clk_n => tb_user_clk_n, -- : in std_logic; + -- + -- RS232 + rs232_rx => tb_rs232_rx, -- : in std_logic; + rs232_tx => tb_rs232_tx, -- : out std_logic; + rs232_rts => tb_rs232_rts, -- : in std_logic; + rs232_cts => tb_rs232_cts, -- : out std_logic; + -- RS232 USB + rs232_usb_rx => tb_rs232_usb_rx, -- : in std_logic; + rs232_usb_tx => tb_rs232_usb_tx, -- : out std_logic; + rs232_usb_reset_n => tb_rs232_usb_reset_n, -- : out std_logic; + -- + gpio_led_n => tb_gpio_led_n, -- : out std_logic_vector(7 downto 0); + gpio_dipswitch => tb_gpio_dipswitch, -- : in std_logic_vector(7 downto 0); + gpio_button => tb_gpio_button, -- : in std_logic_vector(3 downto 0); + -- + -- FLASH 8Mx16 + flash_a => tb_flash_a, -- : out std_logic_vector(31 downto 7); + flash_dq => tb_flash_dq, -- : inout std_logic_vector(15 downto 0); + flash_wen => tb_flash_wen, -- : out std_logic; + flash_oen => tb_flash_oen, -- : out std_logic_vector(0 downto 0); + flash_cen => tb_flash_cen, -- : out std_logic_vector(0 downto 0); + flash_rp_n => tb_flash_rp_n, -- : out std_logic; + flash_byte_n => tb_flash_byte_n, -- : out std_logic; + flash_adv_n => tb_flash_adv_n, -- : out std_logic; + flash_clk => tb_flash_clk, -- : out std_logic; + flash_wait => tb_flash_wait, -- : in std_logic; + -- + -- DDR2 SDRAM 16Mx32 + ddr2_odt => tb_ddr2_odt, -- : in std_logic_vector(0 downto 0); + ddr2_a => tb_ddr2_a, -- : out std_logic_vector(12 downto 0); + ddr2_ba => tb_ddr2_ba, -- : out std_logic_vector(1 downto 0); + ddr2_cas_n => tb_ddr2_cas_n, -- : out std_logic; + ddr2_cke => tb_ddr2_cke, -- : out std_logic; + ddr2_cs_n => tb_ddr2_cs_n, -- : out std_logic; + ddr2_ras_n => tb_ddr2_ras_n, -- : out std_logic; + ddr2_we_n => tb_ddr2_we_n, -- : out std_logic; + ddr2_dm => tb_ddr2_dm, -- : out std_logic_vector(3 downto 0); + ddr2_dqs_p => tb_ddr2_dqs_p, -- : inout std_logic_vector(3 downto 0); + ddr2_dqs_n => tb_ddr2_dqs_n, -- : inout std_logic_vector(3 downto 0); + ddr2_dq => tb_ddr2_dq, -- : inout std_logic_vector(31 downto 0); + ddr2_ck_p => tb_ddr2_ck_p, -- : in std_logic_vector(1 downto 0); + ddr2_ck_n => tb_ddr2_ck_n, -- : in std_logic_vector(1 downto 0); + -- + -- Ethernet MAC + gmii_txer => tb_gmii_txer, -- : out std_logic; + gmii_tx_clk => tb_gmii_tx_clk, -- : in std_logic; + gmii_rx_clk => tb_gmii_rx_clk, -- : in std_logic; + gmii_gtc_clk => tb_gmii_gtc_clk, -- : out std_logic; + gmii_crs => tb_gmii_crs, -- : in std_logic; + gmii_dv => tb_gmii_dv, -- : in std_logic; + gmii_rx_data => tb_gmii_rx_data, -- : in std_logic_vector(7 downto 0); + gmii_col => tb_gmii_col, -- : in std_logic; + gmii_rx_er => tb_gmii_rx_er, -- : in std_logic; + gmii_tx_en => tb_gmii_tx_en, -- : out std_logic; + gmii_tx_data => tb_gmii_tx_data, -- : out std_logic_vector(7 downto 0); + gbe_rst_n => tb_gbe_rst_n, -- : out std_logic; + gbe_mdc => tb_gbe_mdc, -- : out std_logic; + gbe_mdio => tb_gbe_mdio, -- : inout std_logic; + gbe_int_n => tb_gbe_int_n, -- : inout std_logic; + gbe_mclk => tb_gbe_mclk, -- : in std_logic; + -- + -- SysACE CompactFlash + sam_clk => tb_sam_clk, -- : in std_logic; + sam_a => tb_sam_a, -- : out std_logic_vector(6 downto 0); + sam_d => tb_sam_d, -- : inout std_logic_vector(15 downto 0); + sam_cen => tb_sam_cen, -- : out std_logic; + sam_oen => tb_sam_oen, -- : out std_logic; + sam_wen => tb_sam_wen, -- : out std_logic; + sam_mpirq => tb_sam_mpirq, -- : in std_logic; + sam_brdy => tb_sam_brdy, -- : in std_logic; + sam_reset_n => tb_sam_reset_n, -- : out std_logic; + -- + -- Expansion Header + exp1_se_io => tb_exp1_se_io, -- : inout std_logic_vector(33 downto 0); + exp1_diff_p => tb_exp1_diff_p, -- : inout std_logic_vector(21 downto 0); + exp1_diff_n => tb_exp1_diff_n, -- : inout std_logic_vector(21 downto 0); + exp1_se_clk_out => tb_exp1_se_clk_out, -- : out std_logic; + exp1_se_clk_in => tb_exp1_se_clk_in, -- : in std_logic; + exp1_diff_clk_out_p => tb_exp1_diff_clk_out_p, -- : out std_logic; + exp1_diff_clk_out_n => tb_exp1_diff_clk_out_n, -- : out std_logic; + exp1_diff_clk_in_p => tb_exp1_diff_clk_in_p, -- : in std_logic; + exp1_diff_clk_in_n => tb_exp1_diff_clk_in_n, -- : in std_logic; + -- + -- Debug/Trace + atdd => tb_atdd, -- : inout std_logic_vector(19 downto 8); + trace_ts10 => tb_trace_ts10, -- : inout std_logic; + trace_ts20 => tb_trace_ts20, -- : inout std_logic; + trace_ts1e => tb_trace_ts1e, -- : inout std_logic; + trace_ts2e => tb_trace_ts2e, -- : inout std_logic; + trace_ts3 => tb_trace_ts3, -- : inout std_logic; + trace_ts4 => tb_trace_ts4, -- : inout std_logic; + trace_ts5 => tb_trace_ts5, -- : inout std_logic; + trace_ts6 => tb_trace_ts6, -- : inout std_logic; + trace_clk => tb_trace_clk, -- : in std_logic; + cpu_hreset => tb_cpu_hreset, -- : in std_logic; + cpu_tdo => tb_cpu_tdo, -- : out std_logic; + cpu_tms => tb_cpu_tms, -- : in std_logic; + cpu_tdi => tb_cpu_tdi, -- : in std_logic; + cpu_trst => tb_cpu_trst, -- : in std_logic; + cpu_tck => tb_cpu_tck, -- : in std_logic; + cpu_halt_n => tb_cpu_halt_n -- : in std_logic + ); + + + -- check for simulation stopping + process (tb_stop_simulation) + begin + if tb_stop_simulation = '1' then + report "Simulation end." severity note; + simulation_run <= false; + end if; + end process; + +end architecture testbench; -- cgit v1.1