From 0bf783475d6610a14f71884737aeae33246bb9be Mon Sep 17 00:00:00 2001
From: Bert Lange <b.lange@hzdr.de>
Date: Thu, 13 Oct 2011 12:37:49 +0200
Subject: add: ZPU reference designs for zealot

---
 .../synthesis_config/top.ut                        | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut

(limited to 'zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut')

diff --git a/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
new file mode 100644
index 0000000..06de8d5
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/digilent-starter-xc3s500e/synthesis_config/top.ut
@@ -0,0 +1,22 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
-- 
cgit v1.1