From 662a6952bc04419ac063cf3eb2b5917978eec0a1 Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Fri, 28 Oct 2011 10:59:45 +0200 Subject: add: Spartan3 reference design for zealot --- .../synthesis_config/top.xst | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst (limited to 'zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst') diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst new file mode 100644 index 0000000..14873ea --- /dev/null +++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.xst @@ -0,0 +1,56 @@ +set -tmpdir "tmp" +set -xsthdpdir "xst" +run +-ifn ../synthesis_config/top.prj +-ifmt mixed +-ofn top +-ofmt NGC +-p xc3s1000-4-fg456 +-top top +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 -- cgit v1.1