From 662a6952bc04419ac063cf3eb2b5917978eec0a1 Mon Sep 17 00:00:00 2001
From: Bert Lange <b.lange@hzdr.de>
Date: Fri, 28 Oct 2011 10:59:45 +0200
Subject: add: Spartan3 reference design for zealot

---
 .../synthesis_config/top.ut                        | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut

(limited to 'zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut')

diff --git a/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
new file mode 100644
index 0000000..765a6f3
--- /dev/null
+++ b/zpu/hdl/zealot/fpga/altium-livedesign-xc3s1000/synthesis_config/top.ut
@@ -0,0 +1,29 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g HswapenPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Match_cycle:Auto
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
-- 
cgit v1.1