From af5b54efbbcbe6e80478ddb24ac2e95a33e63a2d Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 16 Apr 2008 12:49:31 +0000 Subject: * zpu/doc/zpupresentation_old.odt: interesting bits moved into zpu_arch.html * zpu/doc/zpupresentation.*: interesting bits moved into zpu_arch.html --- zpu/docs/zpu_arch.html | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) (limited to 'zpu/docs/zpu_arch.html') diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index df692a7..a1f61a1 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -1,5 +1,52 @@ +

Introduction

+The ZPU is a zero operand, or stack based CPU. The opcodes have a fixed width of 8 bits. +

+Example: +

+

+ + IM 5 ; push 5 onto the stack + LOADSP 20 ; push value at memory location SP+20 + ADD ; pop 2 values on the stack and push the result + +
+As can be seen, a lot of information is packed into the 8 bits, e.g. the IM instruction pushes a 7 bit signed integer onto the stack. +

+The choice of opcodes is intimately tied to the GCC toolchain capabilities. +

+

+ + /* simple program showing some interesting qualities of the ZPU toolchain */ + void bar(int); + int j; + void foo(int a, int b, int c) + { + a++; + b+=a; + j=c; + bar(b); + } + +foo: + loadsp 4 ; a is at memory location SP+4 + im 1 + add + loadsp 12 ; b is now at memory location SP+12 + add + loadsp 16 ; c is now at memory location SP+16 + im 24 ; «j» is at absolute memory location 24. +; Notice how the ZPU toolchain is using link-time relaxation +; to squeeze the address into a single no-op + store + im 22 ; the fn bar is at address 22 + call + im 12 + return ; 12 bytes of arguments + return from fn + +
+

Instruction set

Only the base instructions are implemented in the architecture. More advanced instructions, like ASHIFTLEFT are emulated in the illegal instruction vector. -- cgit v1.1