From 952bcd56f3b4e412594920ef02d9d740b3ce119a Mon Sep 17 00:00:00 2001 From: oharboe Date: Thu, 21 Aug 2008 21:12:57 +0000 Subject: merging in some docs to zpu_arch.html --- zpu/docs/zpu_arch.html | 106 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 98 insertions(+), 8 deletions(-) (limited to 'zpu/docs/zpu_arch.html') diff --git a/zpu/docs/zpu_arch.html b/zpu/docs/zpu_arch.html index f6fd8d1..84ccc1a 100644 --- a/zpu/docs/zpu_arch.html +++ b/zpu/docs/zpu_arch.html @@ -2,8 +2,9 @@

Index

- -

Getting started

-The ZPU comes with a few simulation examples. + + +

Getting started - FPGA

+The simplest version of the ZPU uses BRAM. When getting accustomed to the ZPU, a BRAM ZPU with a UART +is a good place to start. +

+You'll find a working simulation script in hdl/example/simzpu_small.do and hdl/example_medium/simzpu_medium.do, which +show simulation of the small(zpu_core_small.vhd) and medium sized ZPU(zpu_core.vhd). hdl/example/simzpu_interrupt.do +shows use of interrupts. +

+When implementing the ZPU, copy the following files and modify them to your needs: +

    +
  1. hdl/example/zpu_config.vhd - set up RAM size here +
  2. hdl/example/helloworld.vhd - dual port BRAM implementation. +
+Obviously you must also connect the ZPU to the rest of your IO subsystem. IO is memory mapped(read/write) in the ZPU. +

Generating VHDL BRAM initialization

+ + +../install/bin/zpu-elf-objcopy -O binary hello.elf hello.bin
+java -classpath ../simulator/zpusim.jar com.zylin.zpu.simulator.tools.MakeRam hello.bin >hello.bram
+ + +

Running example simulation

+The hdl/example directory has a simulation written for Xilinx WebPack ModelSim. From the ModelSim command prompt: +
    +
  1. cd c:/<installfolder>/hdl/example +
  2. do zpusim_small.do +
+

+After running the hello world simulation (see zpusim.do), two files are written to the hdl/example directory: +

    +
  1. log.txt - contains the "Hello world!" text written to the debug channel/simplified UART. +
  2. trace.txt - a trace file for the CPU. The instruction set simulator has the capability of taking +this file as input in order to verify that the HDL implementation matches the instruction set simulator. +When a mismatch is found, the GDB debugger will break. Very handy for debugging custom ZPU implementations. +
+

HDL Directories & files

+ + +The HDL files need a bit of spit and polish! + + +

Getting started - software

+The ZPU comes with a standard GCC toolchain and an instruction set simulator. This allows compiling, running & debugging simple test programs. The Simulator has +some very basic peripherals defined: counter, timer interrupt and a debug output port. +

Installing

+
    +
  1. Install Cygwin. http://www.cygwin.com +
  2. Install Java +
  3. Start Cygwin bash +
  4. cd zpu/sw +
  5. sh setup.sh +
  6. /tmp/zpu/install/bin now has the .exe files for the GCC toolchain & GDB +
  7. Optionally you may set up PATH variables to point to /tmp/zpu/install/bin
    +source env.sh +
+

Hello world example

+The ZPU toolchain comes with newlib & libstdc++ support which means that many C/C++ programs can be compiled without modification. +

+ +cd zpu/sw/helloworld
+../install/bin/zpu-elf-gcc -phi hello.c -o hello.elf
+ +

Running the hello world example in GDB

+
    +
  1. cd zpu/sw/helloworld +
  2. Launch the simulator from a seperate bash shell:

    +java -classpath ../simulator/zpusim.jar -Xmx512m com.zylin.zpu.simulator.Phi 4444 +

    + +

  3. Launch GDB:

    +../install/bin/zpu-elf-gdb hello.elf +

  4. Connect to target, load and run application:

    + +(gdb) target remote localhost:4444
    +(gdb) load
    +(gdb) continue
    +

    -Start with VHDL synthesis examples + + +

+ + -

Introduction

+

Architecture introduction

The ZPU is a zero operand, or stack based CPU. The opcodes have a fixed width of 8 bits.

Example: @@ -893,7 +980,8 @@ the right choices w.r.t. optimisation for your application.

Phi memory map

The ZPU architecture does not define a memory map as such, but the GCC + libgloss + ecos hal library uses the -memory map below. +memory map below. "Phi" is just a three letter word for the particular memory layout below that came about +while developing the ZPU.

@@ -1387,5 +1475,7 @@ For this to make sense, the performance must hit 20 DMIPS w/DRAM & cache. This ZPU could run a TCP/IP stack with relevant performance to compete with stripped down ARM7 type systems. + + \ No newline at end of file -- cgit v1.1