From 04772b6a0bbe7017f5f7b44cfa203c3f7efbff64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 1 Mar 2011 20:52:55 +0100 Subject: whitespace fixes: use fromdos on all .vhd files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- misc/wishbone/src/atomic32_access.vhd | 262 +++++++++++++++++----------------- misc/wishbone/src/wishbone_pkg.vhd | 104 +++++++------- 2 files changed, 183 insertions(+), 183 deletions(-) (limited to 'misc/wishbone/src') diff --git a/misc/wishbone/src/atomic32_access.vhd b/misc/wishbone/src/atomic32_access.vhd index b062f98..9bc9825 100644 --- a/misc/wishbone/src/atomic32_access.vhd +++ b/misc/wishbone/src/atomic32_access.vhd @@ -1,132 +1,132 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; ---use work.phi_config.all; -use work.wishbone_pkg.all; - -entity atomic32_access is - port ( cpu_clk : in std_logic; - areset : in std_logic; - - -- Wishbone from CPU interface - wb_16_i : in wishbone_bus_in; - wb_16_o : out wishbone_bus_out; - - -- Wishbone to FPGA registers and ethernet core - wb_32_i : in wishbone_bus_out; - wb_32_o : out wishbone_bus_in); -end atomic32_access; - -architecture behave of atomic32_access is - -type eth_state_wr_type is (idle, lsb_msb, lsb, msb, write, ack, wait_st); -signal eth_state_wr : eth_state_wr_type; -type eth_state_rd_type is (idle, lsb_msb, lsb_read, lsb, wait_st2, msb); -signal eth_state_rd : eth_state_rd_type; -signal core_data : std_logic_vector(31 downto 0); -signal core_addr : std_logic_vector(31 downto 0); - -begin - process(cpu_clk, areset) - begin - if areset = '1' then - eth_state_wr <= idle; - eth_state_rd <= idle; - wb_32_o.stb <= '0'; - wb_32_o.cyc <= '0'; - wb_16_o.ack <= '0'; - core_data <= (others => '0'); - core_addr <= (others => '0'); - elsif (rising_edge(cpu_clk)) then - - case eth_state_wr is --write cycle - when idle => - if wb_16_i.cyc = '1' and wb_16_i.we = '1' then - eth_state_wr <= lsb_msb; - end if; - when lsb_msb => - if wb_16_i.adr(1) = '0' then - eth_state_wr <= lsb; - end if; - if wb_16_i.adr(1) = '1' then - eth_state_wr <= msb; - end if; - when lsb => - core_data(15 downto 0) <= wb_16_i.dat(15 downto 0); - wb_16_o.ack <= '1'; - eth_state_wr <= wait_st; - when msb => - core_data(31 downto 16) <= wb_16_i.dat(31 downto 16); - core_addr <= wb_16_i.adr(31 downto 2) & "00"; - eth_state_wr <= write; - when write => - wb_32_o.dat <= core_data; - wb_32_o.adr <= core_addr; - wb_32_o.sel <= "1111"; - wb_32_o.we <= '1'; - wb_32_o.stb <= '1'; - wb_32_o.cyc <= '1'; - eth_state_wr <= ack; - when ack => - if wb_32_i.ack = '1' then - wb_16_o.ack <= '1'; - eth_state_wr <= wait_st; - wb_32_o.stb <= '0'; - wb_32_o.cyc <= '0'; - wb_32_o.sel <= "0000"; - wb_32_o.we <= '0'; - end if; - when wait_st => - wb_16_o.ack <= '0'; - eth_state_wr <= idle; - when others => - eth_state_wr <= idle; - end case; - - case eth_state_rd is --read cycle - when idle => - if wb_16_i.cyc = '1' and wb_16_i.we = '0' then - core_addr <= wb_16_i.adr(31 downto 2) & "00"; - eth_state_rd <= lsb_msb; - end if; - when lsb_msb => - if wb_16_i.adr(1) = '0' then - wb_32_o.adr <= core_addr; - eth_state_rd <= lsb_read; - end if; - if wb_16_i.adr(1) = '1' then - wb_32_o.adr <= core_addr; - eth_state_rd <= msb; - end if; - when lsb_read => - wb_32_o.sel <= "1111"; - wb_32_o.we <= '0'; - wb_32_o.stb <= '1'; - wb_32_o.cyc <= '1'; - eth_state_rd <= lsb; - when lsb => - if wb_32_i.ack = '1' then - wb_32_o.sel <= "0000"; - wb_32_o.stb <= '0'; - wb_32_o.cyc <= '0'; - core_data <= wb_32_i.dat; - wb_16_o.dat <= x"0000" & wb_32_i.dat(15 downto 0); - wb_16_o.ack <= '1'; - eth_state_rd <= wait_st2; - end if; - when wait_st2 => - wb_16_o.ack <= '0'; - eth_state_rd <= idle; - when msb => - wb_16_o.ack <= '1'; - wb_16_o.dat <= core_data(31 downto 16) & x"0000"; - eth_state_rd <= wait_st2; - when others => - eth_state_rd <= idle; - end case; - end if; - end process; - +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +--use work.phi_config.all; +use work.wishbone_pkg.all; + +entity atomic32_access is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from CPU interface + wb_16_i : in wishbone_bus_in; + wb_16_o : out wishbone_bus_out; + + -- Wishbone to FPGA registers and ethernet core + wb_32_i : in wishbone_bus_out; + wb_32_o : out wishbone_bus_in); +end atomic32_access; + +architecture behave of atomic32_access is + +type eth_state_wr_type is (idle, lsb_msb, lsb, msb, write, ack, wait_st); +signal eth_state_wr : eth_state_wr_type; +type eth_state_rd_type is (idle, lsb_msb, lsb_read, lsb, wait_st2, msb); +signal eth_state_rd : eth_state_rd_type; +signal core_data : std_logic_vector(31 downto 0); +signal core_addr : std_logic_vector(31 downto 0); + +begin + process(cpu_clk, areset) + begin + if areset = '1' then + eth_state_wr <= idle; + eth_state_rd <= idle; + wb_32_o.stb <= '0'; + wb_32_o.cyc <= '0'; + wb_16_o.ack <= '0'; + core_data <= (others => '0'); + core_addr <= (others => '0'); + elsif (rising_edge(cpu_clk)) then + + case eth_state_wr is --write cycle + when idle => + if wb_16_i.cyc = '1' and wb_16_i.we = '1' then + eth_state_wr <= lsb_msb; + end if; + when lsb_msb => + if wb_16_i.adr(1) = '0' then + eth_state_wr <= lsb; + end if; + if wb_16_i.adr(1) = '1' then + eth_state_wr <= msb; + end if; + when lsb => + core_data(15 downto 0) <= wb_16_i.dat(15 downto 0); + wb_16_o.ack <= '1'; + eth_state_wr <= wait_st; + when msb => + core_data(31 downto 16) <= wb_16_i.dat(31 downto 16); + core_addr <= wb_16_i.adr(31 downto 2) & "00"; + eth_state_wr <= write; + when write => + wb_32_o.dat <= core_data; + wb_32_o.adr <= core_addr; + wb_32_o.sel <= "1111"; + wb_32_o.we <= '1'; + wb_32_o.stb <= '1'; + wb_32_o.cyc <= '1'; + eth_state_wr <= ack; + when ack => + if wb_32_i.ack = '1' then + wb_16_o.ack <= '1'; + eth_state_wr <= wait_st; + wb_32_o.stb <= '0'; + wb_32_o.cyc <= '0'; + wb_32_o.sel <= "0000"; + wb_32_o.we <= '0'; + end if; + when wait_st => + wb_16_o.ack <= '0'; + eth_state_wr <= idle; + when others => + eth_state_wr <= idle; + end case; + + case eth_state_rd is --read cycle + when idle => + if wb_16_i.cyc = '1' and wb_16_i.we = '0' then + core_addr <= wb_16_i.adr(31 downto 2) & "00"; + eth_state_rd <= lsb_msb; + end if; + when lsb_msb => + if wb_16_i.adr(1) = '0' then + wb_32_o.adr <= core_addr; + eth_state_rd <= lsb_read; + end if; + if wb_16_i.adr(1) = '1' then + wb_32_o.adr <= core_addr; + eth_state_rd <= msb; + end if; + when lsb_read => + wb_32_o.sel <= "1111"; + wb_32_o.we <= '0'; + wb_32_o.stb <= '1'; + wb_32_o.cyc <= '1'; + eth_state_rd <= lsb; + when lsb => + if wb_32_i.ack = '1' then + wb_32_o.sel <= "0000"; + wb_32_o.stb <= '0'; + wb_32_o.cyc <= '0'; + core_data <= wb_32_i.dat; + wb_16_o.dat <= x"0000" & wb_32_i.dat(15 downto 0); + wb_16_o.ack <= '1'; + eth_state_rd <= wait_st2; + end if; + when wait_st2 => + wb_16_o.ack <= '0'; + eth_state_rd <= idle; + when msb => + wb_16_o.ack <= '1'; + wb_16_o.dat <= core_data(31 downto 16) & x"0000"; + eth_state_rd <= wait_st2; + when others => + eth_state_rd <= idle; + end case; + end if; + end process; + end behave; \ No newline at end of file diff --git a/misc/wishbone/src/wishbone_pkg.vhd b/misc/wishbone/src/wishbone_pkg.vhd index c3b0d9b..359a33f 100644 --- a/misc/wishbone/src/wishbone_pkg.vhd +++ b/misc/wishbone/src/wishbone_pkg.vhd @@ -1,52 +1,52 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -package wishbone_pkg is - - type wishbone_bus_in is record - adr : std_logic_vector(31 downto 0); - sel : std_logic_vector(3 downto 0); - we : std_logic; - dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we' - cyc : std_logic; - stb : std_logic; - end record; - - type wishbone_bus_out is record - dat : std_logic_vector(31 downto 0); - ack : std_logic; - end record; - - type wishbone_bus is record - insig : wishbone_bus_in; - outsig : wishbone_bus_out; - end record; - - component atomic32_access is - port ( cpu_clk : in std_logic; - areset : in std_logic; - - -- Wishbone from CPU interface - wb_16_i : in wishbone_bus_in; - wb_16_o : out wishbone_bus_out; - -- Wishbone to FPGA registers and ethernet core - wb_32_i : in wishbone_bus_out; - wb_32_o : out wishbone_bus_in); - end component; - - component eth_access_corr is - port ( cpu_clk : in std_logic; - areset : in std_logic; - - -- Wishbone from Wishbone MUX - eth_raw_o : out wishbone_bus_out; - eth_raw_i : in wishbone_bus_in; - - -- Wishbone ethernet core - eth_slave_i : in wishbone_bus_out; - eth_slave_o : out wishbone_bus_in); - end component; - - -end wishbone_pkg; +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +package wishbone_pkg is + + type wishbone_bus_in is record + adr : std_logic_vector(31 downto 0); + sel : std_logic_vector(3 downto 0); + we : std_logic; + dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we' + cyc : std_logic; + stb : std_logic; + end record; + + type wishbone_bus_out is record + dat : std_logic_vector(31 downto 0); + ack : std_logic; + end record; + + type wishbone_bus is record + insig : wishbone_bus_in; + outsig : wishbone_bus_out; + end record; + + component atomic32_access is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from CPU interface + wb_16_i : in wishbone_bus_in; + wb_16_o : out wishbone_bus_out; + -- Wishbone to FPGA registers and ethernet core + wb_32_i : in wishbone_bus_out; + wb_32_o : out wishbone_bus_in); + end component; + + component eth_access_corr is + port ( cpu_clk : in std_logic; + areset : in std_logic; + + -- Wishbone from Wishbone MUX + eth_raw_o : out wishbone_bus_out; + eth_raw_i : in wishbone_bus_in; + + -- Wishbone ethernet core + eth_slave_i : in wishbone_bus_out; + eth_slave_o : out wishbone_bus_in); + end component; + + +end wishbone_pkg; -- cgit v1.1