From 0711a2b4fc2dec8bf65e5821095bed895976b83a Mon Sep 17 00:00:00 2001 From: oharboe Date: Wed, 18 Jun 2008 09:22:21 +0000 Subject: * Various ZY2000 vhdl files of more general interest made available as part of the ZPU project under the same license(FreeBSD). Files should have headers updated. --- misc/ddrsdram/simscripts/ddr_tb.do | 16 ++++++ misc/ddrsdram/simscripts/ddr_top.do | 104 ++++++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 misc/ddrsdram/simscripts/ddr_tb.do create mode 100644 misc/ddrsdram/simscripts/ddr_top.do (limited to 'misc/ddrsdram/simscripts') diff --git a/misc/ddrsdram/simscripts/ddr_tb.do b/misc/ddrsdram/simscripts/ddr_tb.do new file mode 100644 index 0000000..1f643f1 --- /dev/null +++ b/misc/ddrsdram/simscripts/ddr_tb.do @@ -0,0 +1,16 @@ +vlib work +vcom -93 -explicit ../src/ddr_pkg.vhd +vcom -93 -explicit ../src/ddr_top.vhd +vcom -93 -explicit ../src/mt46v16m16.vhd +vcom -93 -explicit ../simsrc/ddr_tb.vhd +vsim -t 1ps ddr_tb +view wave +view signals +radix hex +add wave * +add wave sim:/ddr_tb/ddr_ctrl/* +force -freeze sim:/ddr_tb/areset 1 0 +run 10 ns +force -freeze sim:/ddr_tb/areset 0 0 +when sim:/ddr_tb/break_out stop +run 10 ms \ No newline at end of file diff --git a/misc/ddrsdram/simscripts/ddr_top.do b/misc/ddrsdram/simscripts/ddr_top.do new file mode 100644 index 0000000..141e164 --- /dev/null +++ b/misc/ddrsdram/simscripts/ddr_top.do @@ -0,0 +1,104 @@ +vlib work +vcom -93 -explicit ../src/ddr_pkg.vhd +vcom -93 -explicit ../src/ddr_top.vhd +vsim -t 1ps ddr_top +view wave +view signals +radix hex +# Add wave signals + +add wave -divider "System" +add wave sim:/ddr_top/areset +add wave sim:/ddr_top/cpu_clk +add wave sim:/ddr_top/cpu_clk_2x +add wave sim:/ddr_top/cpu_clk_4x +add wave sim:/ddr_top/ddr_in_clk +add wave sim:/ddr_top/ddr_in_clk_2x + +add wave -divider "Ctrl interface" +add wave sim:/ddr_top/cpu_clk +add wave sim:/ddr_top/ddr_data_read +add wave sim:/ddr_top/ddr_data_write +add wave sim:/ddr_top/ddr_req +add wave sim:/ddr_top/ddr_rd_wr_n +add wave sim:/ddr_top/ddr_req_len +add wave sim:/ddr_top/ddr_read_en +add wave sim:/ddr_top/ddr_write_en +add wave sim:/ddr_top/ddr_command +add wave sim:/ddr_top/ddr_command_we + +add wave -divider "DDR interface" +add wave sim:/ddr_top/sdr_clk_p +add wave sim:/ddr_top/sdr_clk_n_p +add wave sim:/ddr_top/cke_q_p +add wave sim:/ddr_top/cs_qn_p +add wave sim:/ddr_top/ras_qn_p +add wave sim:/ddr_top/cas_qn_p +add wave sim:/ddr_top/we_qn_p +add wave sim:/ddr_top/dm_q_p +add wave sim:/ddr_top/dqs_q_p +add wave sim:/ddr_top/ba_q_p +add wave sim:/ddr_top/sdr_a_p +add wave sim:/ddr_top/sdr_d_p + +add wave -divider "Internal signals" +add wave sim:/ddr_top/clk2_phase +add wave sim:/ddr_top/clk4_phase +add wave sim:/ddr_top/ddr_state +add wave sim:/ddr_top/sdr_oe_n +add wave sim:/ddr_top/sdr_smp +add wave sim:/ddr_top/sdr_d + + +# Add input signals +force -freeze sim:/ddr_top/cpu_clk_4x 1 0, 0 {1.875 ns} -r 3.75 ns +run 100 ps +force -freeze sim:/ddr_top/cpu_clk_2x 1 0, 0 {3.75 ns} -r 7.5 ns +run 100 ps +force -freeze sim:/ddr_top/cpu_clk 1 0, 0 {7.5 ns} -r 15 ns +force -freeze sim:/ddr_top/ddr_in_clk 1 2ns, 0 {5.75 ns} -r 7.5 ns +force -freeze sim:/ddr_top/ddr_in_clk_2x 0 0.125ns, 1 {2 ns} -r 3.75 ns + +force -freeze sim:/ddr_top/areset 1 0 +force -freeze sim:/ddr_top/ddr_command 0000 0 +force -freeze sim:/ddr_top/ddr_command_we 0 0 +force -freeze sim:/ddr_top/ddr_data_write 1234abcd 0 +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 + +# Start simulation +run 45 ns +force -freeze sim:/ddr_top/areset 0 0 +run 92 ns +# DDR Command +force -freeze sim:/ddr_top/ddr_command 000A 0 +force -freeze sim:/ddr_top/ddr_command_we 1 0 +run 15 ns +force -freeze sim:/ddr_top/ddr_command 0000 0 +force -freeze sim:/ddr_top/ddr_command_we 0 0 +run 90 ns +# DDR Read +force -freeze sim:/ddr_top/ddr_req 1 0 +force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 1 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 +run 15 ns +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 +run 150 ns +# DDR Write +force -freeze sim:/ddr_top/ddr_req 1 0 +force -freeze sim:/ddr_top/ddr_req_adr 00ABCD 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 +run 15 ns +force -freeze sim:/ddr_top/ddr_req 0 0 +force -freeze sim:/ddr_top/ddr_req_adr 000000 0 +force -freeze sim:/ddr_top/ddr_rd_wr_n 0 0 +force -freeze sim:/ddr_top/ddr_req_len 0 0 +run 180 ns + -- cgit v1.1