From 02431f006669785afdf8e12ef1e91e06cb6318b4 Mon Sep 17 00:00:00 2001
From: Bert Lange <b.lange@hzdr.de>
Date: Fri, 18 Jul 2014 14:45:17 +0200
Subject: change: to minimal zpu system

---
 mig_test/vhdl_files.txt | 61 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

(limited to 'mig_test/vhdl_files.txt')

diff --git a/mig_test/vhdl_files.txt b/mig_test/vhdl_files.txt
index c19a027..693137b 100644
--- a/mig_test/vhdl_files.txt
+++ b/mig_test/vhdl_files.txt
@@ -1,2 +1,63 @@
 work        rtl/top.vhd
+work        rtl/box.vhd
+work        rtl/timestamp.vhd
 work        rtl_tb/top_tb.vhd
+
+grlib       ../grlib/rtl/ahbctrl.vhd
+grlib       ../grlib/rtl/amba.vhd
+grlib       ../grlib/rtl/apbctrl.vhd
+grlib       ../grlib/rtl/config.vhd
+grlib       ../grlib/rtl/devices.vhd
+grlib       ../grlib/rtl/stdlib.vhd
+grlib       ../grlib/rtl/testlib.vhd
+grlib       ../grlib/rtl/util.vhd
+grlib       ../grlib/rtl/version.vhd
+grlib       ../grlib/rtl_tb/stdio.vhd
+
+hzdr        ../hzdr/rtl/devices_hzdr.vhd
+hzdr        ../hzdr/rtl/component_package.vhd
+hzdr        ../hzdr/rtl/debug_con_apb.vhd
+
+gaisler     ../gaisler/rtl/ahbdpram.vhd
+gaisler     ../gaisler/rtl/ahbram.vhd
+gaisler     ../gaisler/rtl/apbuart.vhd
+gaisler     ../gaisler/rtl/grgpio.vhd
+gaisler     ../gaisler/rtl/uart.vhd
+gaisler     ../gaisler/rtl/gptimer.vhd
+gaisler     ../gaisler/rtl/misc.vhd
+gaisler     ../gaisler/rtl/net.vhd
+gaisler     ../gaisler/rtl/memctrl.vhd
+gaisler     ../gaisler/rtl/memoryctrl.vhd
+gaisler     ../gaisler/rtl_tb/sim.vhd
+gaisler     ../gaisler/rtl/greth.vhd
+gaisler     ../gaisler/rtl/ethernet_mac.vhd
+
+eth         ../gaisler/rtl/greth_pkg.vhd
+eth         ../gaisler/rtl/greth_rx.vhd
+eth         ../gaisler/rtl/greth_tx.vhd
+eth         ../gaisler/rtl/grethc.vhd
+eth         ../gaisler/rtl/eth_ahb_mst.vhd
+eth         ../gaisler/rtl/eth_rstgen.vhd
+eth         ../gaisler/rtl/ethcomp.vhd
+
+techmap     ../techmap/rtl/allmem.vhd
+techmap     ../techmap/rtl/gencomp.vhd
+techmap     ../techmap/rtl/memory_inferred.vhd
+techmap     ../techmap/rtl/memory_unisim.vhd
+techmap     ../techmap/rtl/syncram_2p.vhd
+techmap     ../techmap/rtl/syncram_dp.vhd
+techmap     ../techmap/rtl/syncrambw.vhd
+techmap     ../techmap/rtl/syncram.vhd
+techmap     ../techmap/rtl/netcomp.vhd
+
+zpu         rtl/zpu_config.vhd
+zpu         rtl/dualport_ram.vhd
+zpu         ../zpu/rtl/dualport_ram_ahb_wrapper.vhd
+zpu         ../zpu/rtl/zpu_ahb.vhd
+zpu         ../zpu/rtl/zpu_bus_trace.vhd
+zpu         ../zpu/rtl/zpu_core_medium.vhd
+zpu         ../zpu/rtl/zpu_core_small.vhd
+zpu         ../zpu/rtl/zpu_wrapper_package.vhd
+zpu         ../zpu/rtl/zpupkg.vhd
+zpu         ../zpu/rtl_tb/sim_small_fpga_top_noint.vhd
+zpu         ../zpu/rtl_tb/txt_util.vhd
-- 
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