From d190f1c37139ec38667a3d6e566dbe1b0549f84d Mon Sep 17 00:00:00 2001 From: Bert Lange Date: Mon, 7 Nov 2011 15:41:50 +0100 Subject: initial commit --- uc_str912/erase_flash/Makefile | 10 + uc_str912/erase_flash/erase.S | 3 + uc_str912/erase_flash/erase_jlink.gdb | 7 + uc_str912/openocd/amontec.sh | 3 + uc_str912/openocd/openocd_amontec.cfg | 26 + uc_str912/openocd/openocd_segger.cfg | 6 + uc_str912/openocd/segger.sh | 2 + uc_str912/openocd/str912.cfg | 131 +++ uc_str912/prj_TEST_LED/Makefile | 496 +++++++++ uc_str912/prj_TEST_LED/STR91x-RAM.ld | 218 ++++ uc_str912/prj_TEST_LED/STR91x-ROM.ld | 221 ++++ uc_str912/prj_TEST_LED/include/91x_ahbapb.h | 60 ++ uc_str912/prj_TEST_LED/include/91x_conf.h | 115 ++ uc_str912/prj_TEST_LED/include/91x_fmi.h | 184 ++++ uc_str912/prj_TEST_LED/include/91x_gpio.h | 93 ++ uc_str912/prj_TEST_LED/include/91x_lib.h | 114 ++ uc_str912/prj_TEST_LED/include/91x_map.h | 878 +++++++++++++++ uc_str912/prj_TEST_LED/include/91x_scu.h | 196 ++++ uc_str912/prj_TEST_LED/include/91x_type.h | 50 + uc_str912/prj_TEST_LED/led.c | 122 +++ uc_str912/prj_TEST_LED/load_segger.gdb | 20 + uc_str912/prj_TEST_LED/startup.s | 233 ++++ uc_str912/prj_TEST_LED/str91x_lib/91x_ahbapb.c | 177 +++ uc_str912/prj_TEST_LED/str91x_lib/91x_fmi.c | 519 +++++++++ uc_str912/prj_TEST_LED/str91x_lib/91x_gpio.c | 407 +++++++ uc_str912/prj_TEST_LED/str91x_lib/91x_lib.c | 281 +++++ uc_str912/prj_TEST_LED/str91x_lib/91x_scu.c | 661 ++++++++++++ uc_str912/prj_TEST_LED/vector.s | 202 ++++ uc_str912/prj_TEST_LED/vectors.c | 462 ++++++++ uc_str912/prj_TEST_LED/vectors.h | 67 ++ uc_str912/prj_blinky_complex_startup/91x_conf.h | 118 ++ uc_str912/prj_blinky_complex_startup/Makefile | 463 ++++++++ uc_str912/prj_blinky_complex_startup/defines.h | 67 ++ .../prj_blinky_complex_startup/include/91x_adc.h | 124 +++ .../include/91x_ahbapb.h | 60 ++ .../prj_blinky_complex_startup/include/91x_can.h | 165 +++ .../prj_blinky_complex_startup/include/91x_dma.h | 247 +++++ .../prj_blinky_complex_startup/include/91x_emi.h | 83 ++ .../prj_blinky_complex_startup/include/91x_fmi.h | 184 ++++ .../prj_blinky_complex_startup/include/91x_gpio.h | 93 ++ .../prj_blinky_complex_startup/include/91x_i2c.h | 112 ++ .../prj_blinky_complex_startup/include/91x_it.h | 73 ++ .../prj_blinky_complex_startup/include/91x_lib.h | 114 ++ .../prj_blinky_complex_startup/include/91x_map.h | 878 +++++++++++++++ .../prj_blinky_complex_startup/include/91x_mc.h | 144 +++ .../prj_blinky_complex_startup/include/91x_rtc.h | 109 ++ .../prj_blinky_complex_startup/include/91x_scu.h | 196 ++++ .../prj_blinky_complex_startup/include/91x_ssp.h | 119 +++ .../prj_blinky_complex_startup/include/91x_tim.h | 155 +++ .../prj_blinky_complex_startup/include/91x_type.h | 50 + .../prj_blinky_complex_startup/include/91x_uart.h | 174 +++ .../prj_blinky_complex_startup/include/91x_vic.h | 94 ++ .../prj_blinky_complex_startup/include/91x_wdg.h | 82 ++ .../prj_blinky_complex_startup/include/91x_wiu.h | 99 ++ .../prj_blinky_complex_startup/include/usb_core.h | 145 +++ .../prj_blinky_complex_startup/include/usb_def.h | 68 ++ .../prj_blinky_complex_startup/include/usb_init.h | 45 + .../prj_blinky_complex_startup/include/usb_lib.h | 25 + .../prj_blinky_complex_startup/include/usb_mem.h | 23 + .../prj_blinky_complex_startup/include/usb_regs.h | 442 ++++++++ .../prj_blinky_complex_startup/include/usb_type.h | 31 + uc_str912/prj_blinky_complex_startup/interrupt.c | 295 +++++ uc_str912/prj_blinky_complex_startup/inthandler.S | 94 ++ .../prj_blinky_complex_startup/load_segger.gdb | 23 + uc_str912/prj_blinky_complex_startup/main.c | 173 +++ uc_str912/prj_blinky_complex_startup/main.h | 55 + uc_str912/prj_blinky_complex_startup/src/91x_adc.c | 590 ++++++++++ .../prj_blinky_complex_startup/src/91x_ahbapb.c | 177 +++ uc_str912/prj_blinky_complex_startup/src/91x_can.c | 769 +++++++++++++ uc_str912/prj_blinky_complex_startup/src/91x_dma.c | 1125 ++++++++++++++++++++ uc_str912/prj_blinky_complex_startup/src/91x_emi.c | 167 +++ uc_str912/prj_blinky_complex_startup/src/91x_fmi.c | 519 +++++++++ .../prj_blinky_complex_startup/src/91x_gpio.c | 407 +++++++ uc_str912/prj_blinky_complex_startup/src/91x_i2c.c | 616 +++++++++++ uc_str912/prj_blinky_complex_startup/src/91x_lib.c | 281 +++++ uc_str912/prj_blinky_complex_startup/src/91x_mc.c | 932 ++++++++++++++++ uc_str912/prj_blinky_complex_startup/src/91x_rtc.c | 400 +++++++ uc_str912/prj_blinky_complex_startup/src/91x_scu.c | 661 ++++++++++++ uc_str912/prj_blinky_complex_startup/src/91x_ssp.c | 469 ++++++++ uc_str912/prj_blinky_complex_startup/src/91x_tim.c | 694 ++++++++++++ .../prj_blinky_complex_startup/src/91x_uart.c | 658 ++++++++++++ uc_str912/prj_blinky_complex_startup/src/91x_vic.c | 830 +++++++++++++++ uc_str912/prj_blinky_complex_startup/src/91x_wdg.c | 277 +++++ uc_str912/prj_blinky_complex_startup/src/91x_wiu.c | 190 ++++ .../prj_blinky_complex_startup/src/usb_core.c | 860 +++++++++++++++ .../prj_blinky_complex_startup/src/usb_init.c | 64 ++ uc_str912/prj_blinky_complex_startup/src/usb_int.c | 95 ++ uc_str912/prj_blinky_complex_startup/src/usb_mem.c | 85 ++ .../prj_blinky_complex_startup/src/usb_regs.c | 1000 +++++++++++++++++ uc_str912/prj_blinky_complex_startup/startup912.S | 405 +++++++ .../prj_blinky_complex_startup/startup912.S_old | 361 +++++++ .../prj_blinky_complex_startup/startup_generic.S | 162 +++ uc_str912/prj_blinky_complex_startup/syscalls.c | 180 ++++ uc_str912/prj_blinky_simple_startup/Makefile | 495 +++++++++ uc_str912/prj_blinky_simple_startup/STR91x-RAM.ld | 218 ++++ uc_str912/prj_blinky_simple_startup/STR91x-ROM.ld | 221 ++++ .../prj_blinky_simple_startup/include/vectors.h | 67 ++ .../prj_blinky_simple_startup/load_segger.gdb | 20 + uc_str912/prj_blinky_simple_startup/src/main.c | 102 ++ uc_str912/prj_blinky_simple_startup/src/startup.s | 233 ++++ uc_str912/prj_blinky_simple_startup/src/vector.s | 202 ++++ uc_str912/prj_blinky_simple_startup/src/vectors.c | 462 ++++++++ .../prj_blinky_simple_startup/str91x_lib/Makefile | 38 + .../str91x_lib/include/91x_adc.h | 124 +++ .../str91x_lib/include/91x_ahbapb.h | 60 ++ .../str91x_lib/include/91x_can.h | 165 +++ .../str91x_lib/include/91x_conf.h | 117 ++ .../str91x_lib/include/91x_dma.h | 247 +++++ .../str91x_lib/include/91x_emi.h | 83 ++ .../str91x_lib/include/91x_fmi.h | 184 ++++ .../str91x_lib/include/91x_gpio.h | 93 ++ .../str91x_lib/include/91x_i2c.h | 112 ++ .../str91x_lib/include/91x_it.h | 73 ++ .../str91x_lib/include/91x_lib.h | 113 ++ .../str91x_lib/include/91x_map.h | 878 +++++++++++++++ .../str91x_lib/include/91x_mc.h | 144 +++ .../str91x_lib/include/91x_rtc.h | 109 ++ .../str91x_lib/include/91x_scu.h | 198 ++++ .../str91x_lib/include/91x_ssp.h | 119 +++ .../str91x_lib/include/91x_tim.h | 155 +++ .../str91x_lib/include/91x_type.h | 50 + .../str91x_lib/include/91x_uart.h | 174 +++ .../str91x_lib/include/91x_vic.h | 94 ++ .../str91x_lib/include/91x_wdg.h | 82 ++ .../str91x_lib/include/91x_wiu.h | 99 ++ .../str91x_lib/src/91x_adc.c | 590 ++++++++++ .../str91x_lib/src/91x_ahbapb.c | 177 +++ .../str91x_lib/src/91x_can.c | 768 +++++++++++++ .../str91x_lib/src/91x_dma.c | 1125 ++++++++++++++++++++ .../str91x_lib/src/91x_emi.c | 167 +++ .../str91x_lib/src/91x_fmi.c | 519 +++++++++ .../str91x_lib/src/91x_gpio.c | 407 +++++++ .../str91x_lib/src/91x_i2c.c | 616 +++++++++++ .../str91x_lib/src/91x_lib.c | 281 +++++ .../str91x_lib/src/91x_mc.c | 932 ++++++++++++++++ .../str91x_lib/src/91x_rtc.c | 400 +++++++ .../str91x_lib/src/91x_scu.c | 661 ++++++++++++ .../str91x_lib/src/91x_ssp.c | 469 ++++++++ .../str91x_lib/src/91x_tim.c | 694 ++++++++++++ .../str91x_lib/src/91x_uart.c | 658 ++++++++++++ .../str91x_lib/src/91x_vic.c | 830 +++++++++++++++ .../str91x_lib/src/91x_wdg.c | 277 +++++ .../str91x_lib/src/91x_wiu.c | 190 ++++ uc_str912/prj_main_add/Makefile | 146 +++ uc_str912/prj_main_add/dram.bat | 1 + uc_str912/prj_main_add/inc/typedefs.h | 50 + uc_str912/prj_main_add/prj/eclipse_ram.gdb | 24 + uc_str912/prj_main_add/prj/eclipse_rom.gdb | 24 + uc_str912/prj_main_add/prj/jtagkey.cfg | 59 + uc_str912/prj_main_add/prj/str912_program.script | 2 + uc_str912/prj_main_add/prj/str912_ram.gdb | 22 + uc_str912/prj_main_add/prj/str912_ram.ld | 218 ++++ uc_str912/prj_main_add/prj/str912_reset.script | 2 + uc_str912/prj_main_add/prj/str912_rom.gdb | 22 + uc_str912/prj_main_add/prj/str912_rom.ld | 249 +++++ uc_str912/prj_main_add/segger.gdb | 17 + uc_str912/prj_main_add/src/main.c | 91 ++ uc_str912/prj_main_add/src/startup.s | 222 ++++ uc_str912/prj_template91x/Makefile | 495 +++++++++ uc_str912/prj_template91x/STR91x-RAM.ld | 218 ++++ uc_str912/prj_template91x/STR91x-ROM.ld | 221 ++++ uc_str912/prj_template91x/include/vectors.h | 67 ++ uc_str912/prj_template91x/load_segger.gdb | 23 + uc_str912/prj_template91x/src/main.c | 43 + uc_str912/prj_template91x/src/startup.S | 233 ++++ uc_str912/prj_template91x/src/vector.S | 202 ++++ uc_str912/prj_template91x/src/vectors.c | 462 ++++++++ uc_str912/prj_template91x/str91x_lib/Makefile | 38 + .../prj_template91x/str91x_lib/include/91x_adc.h | 124 +++ .../str91x_lib/include/91x_ahbapb.h | 60 ++ .../prj_template91x/str91x_lib/include/91x_can.h | 165 +++ .../prj_template91x/str91x_lib/include/91x_conf.h | 117 ++ .../prj_template91x/str91x_lib/include/91x_dma.h | 247 +++++ .../prj_template91x/str91x_lib/include/91x_emi.h | 83 ++ .../prj_template91x/str91x_lib/include/91x_fmi.h | 184 ++++ .../prj_template91x/str91x_lib/include/91x_gpio.h | 93 ++ .../prj_template91x/str91x_lib/include/91x_i2c.h | 112 ++ .../prj_template91x/str91x_lib/include/91x_it.h | 73 ++ .../prj_template91x/str91x_lib/include/91x_lib.h | 113 ++ .../prj_template91x/str91x_lib/include/91x_map.h | 878 +++++++++++++++ .../prj_template91x/str91x_lib/include/91x_mc.h | 144 +++ .../prj_template91x/str91x_lib/include/91x_rtc.h | 109 ++ .../prj_template91x/str91x_lib/include/91x_scu.h | 198 ++++ .../prj_template91x/str91x_lib/include/91x_ssp.h | 119 +++ .../prj_template91x/str91x_lib/include/91x_tim.h | 155 +++ .../prj_template91x/str91x_lib/include/91x_type.h | 50 + .../prj_template91x/str91x_lib/include/91x_uart.h | 174 +++ .../prj_template91x/str91x_lib/include/91x_vic.h | 94 ++ .../prj_template91x/str91x_lib/include/91x_wdg.h | 82 ++ .../prj_template91x/str91x_lib/include/91x_wiu.h | 99 ++ uc_str912/prj_template91x/str91x_lib/src/91x_adc.c | 590 ++++++++++ .../prj_template91x/str91x_lib/src/91x_ahbapb.c | 177 +++ uc_str912/prj_template91x/str91x_lib/src/91x_can.c | 768 +++++++++++++ uc_str912/prj_template91x/str91x_lib/src/91x_dma.c | 1125 ++++++++++++++++++++ uc_str912/prj_template91x/str91x_lib/src/91x_emi.c | 167 +++ uc_str912/prj_template91x/str91x_lib/src/91x_fmi.c | 519 +++++++++ .../prj_template91x/str91x_lib/src/91x_gpio.c | 407 +++++++ uc_str912/prj_template91x/str91x_lib/src/91x_i2c.c | 616 +++++++++++ uc_str912/prj_template91x/str91x_lib/src/91x_lib.c | 281 +++++ uc_str912/prj_template91x/str91x_lib/src/91x_mc.c | 932 ++++++++++++++++ uc_str912/prj_template91x/str91x_lib/src/91x_rtc.c | 400 +++++++ uc_str912/prj_template91x/str91x_lib/src/91x_scu.c | 661 ++++++++++++ uc_str912/prj_template91x/str91x_lib/src/91x_ssp.c | 469 ++++++++ uc_str912/prj_template91x/str91x_lib/src/91x_tim.c | 694 ++++++++++++ .../prj_template91x/str91x_lib/src/91x_uart.c | 658 ++++++++++++ uc_str912/prj_template91x/str91x_lib/src/91x_vic.c | 830 +++++++++++++++ uc_str912/prj_template91x/str91x_lib/src/91x_wdg.c | 277 +++++ uc_str912/prj_template91x/str91x_lib/src/91x_wiu.c | 190 ++++ uc_str912/prj_test_lcd/Makefile | 496 +++++++++ uc_str912/prj_test_lcd/STR91x-ROM.ld | 221 ++++ uc_str912/prj_test_lcd/include/91x_ahbapb.h | 60 ++ uc_str912/prj_test_lcd/include/91x_conf.h | 115 ++ uc_str912/prj_test_lcd/include/91x_fmi.h | 184 ++++ uc_str912/prj_test_lcd/include/91x_gpio.h | 93 ++ uc_str912/prj_test_lcd/include/91x_lib.h | 114 ++ uc_str912/prj_test_lcd/include/91x_map.h | 878 +++++++++++++++ uc_str912/prj_test_lcd/include/91x_scu.h | 196 ++++ uc_str912/prj_test_lcd/include/91x_type.h | 50 + uc_str912/prj_test_lcd/include/char_code.h | 79 ++ uc_str912/prj_test_lcd/include/lcd_lib_91x.h | 63 ++ uc_str912/prj_test_lcd/include/vectors.h | 67 ++ uc_str912/prj_test_lcd/load_amontec.gdb | 15 + uc_str912/prj_test_lcd/load_segger.gdb | 20 + uc_str912/prj_test_lcd/src/lcd.c | 93 ++ uc_str912/prj_test_lcd/src/lcd_lib_91x.c | 455 ++++++++ uc_str912/prj_test_lcd/src/startup.s | 233 ++++ uc_str912/prj_test_lcd/src/vector.s | 202 ++++ uc_str912/prj_test_lcd/src/vectors.c | 462 ++++++++ uc_str912/prj_test_lcd/str91x_lib/91x_ahbapb.c | 177 +++ uc_str912/prj_test_lcd/str91x_lib/91x_fmi.c | 519 +++++++++ uc_str912/prj_test_lcd/str91x_lib/91x_gpio.c | 407 +++++++ uc_str912/prj_test_lcd/str91x_lib/91x_lib.c | 281 +++++ uc_str912/prj_test_lcd/str91x_lib/91x_scu.c | 661 ++++++++++++ uc_str912/scripts/flash_str9.ld | 137 +++ uc_str912/scripts/load.gdb | 24 + uc_str912/scripts/load_amontec.gdb | 20 + uc_str912/scripts/load_segger.gdb | 18 + uc_str912/scripts/str912_rom.ld | 249 +++++ uc_str912/scripts/str912fw44.ld | 61 ++ uc_str912/scripts/str91x-configs/str91x_flash.gdb | 6 + .../scripts/str91x-configs/str91x_flasherase.ocd | 6 + .../scripts/str91x-configs/str91x_flashprobe.gdb | 10 + .../scripts/str91x-configs/str91x_flashprogram.ocd | 7 + .../str91x-configs/str91x_jtagkey-flash-erase.cfg | 43 + .../str91x_jtagkey-flash-program.cfg | 43 + .../scripts/str91x-configs/str91x_jtagkey.cfg | 42 + uc_str912/scripts/str91x-configs/str91x_ram.gdb | 6 + uc_str912/scripts/test.gdb | 42 + uc_str912/segger.gdb | 17 + 249 files changed, 62909 insertions(+) create mode 100644 uc_str912/erase_flash/Makefile create mode 100644 uc_str912/erase_flash/erase.S create mode 100644 uc_str912/erase_flash/erase_jlink.gdb create mode 100755 uc_str912/openocd/amontec.sh create mode 100644 uc_str912/openocd/openocd_amontec.cfg create mode 100644 uc_str912/openocd/openocd_segger.cfg create mode 100755 uc_str912/openocd/segger.sh create mode 100644 uc_str912/openocd/str912.cfg create mode 100644 uc_str912/prj_TEST_LED/Makefile create mode 100644 uc_str912/prj_TEST_LED/STR91x-RAM.ld create mode 100644 uc_str912/prj_TEST_LED/STR91x-ROM.ld create mode 100644 uc_str912/prj_TEST_LED/include/91x_ahbapb.h create mode 100644 uc_str912/prj_TEST_LED/include/91x_conf.h create mode 100644 uc_str912/prj_TEST_LED/include/91x_fmi.h create mode 100644 uc_str912/prj_TEST_LED/include/91x_gpio.h create mode 100644 uc_str912/prj_TEST_LED/include/91x_lib.h create mode 100644 uc_str912/prj_TEST_LED/include/91x_map.h create mode 100644 uc_str912/prj_TEST_LED/include/91x_scu.h create mode 100644 uc_str912/prj_TEST_LED/include/91x_type.h create mode 100644 uc_str912/prj_TEST_LED/led.c create mode 100644 uc_str912/prj_TEST_LED/load_segger.gdb create mode 100644 uc_str912/prj_TEST_LED/startup.s create mode 100644 uc_str912/prj_TEST_LED/str91x_lib/91x_ahbapb.c create mode 100644 uc_str912/prj_TEST_LED/str91x_lib/91x_fmi.c create mode 100644 uc_str912/prj_TEST_LED/str91x_lib/91x_gpio.c create mode 100644 uc_str912/prj_TEST_LED/str91x_lib/91x_lib.c create mode 100644 uc_str912/prj_TEST_LED/str91x_lib/91x_scu.c create mode 100644 uc_str912/prj_TEST_LED/vector.s create mode 100644 uc_str912/prj_TEST_LED/vectors.c create mode 100644 uc_str912/prj_TEST_LED/vectors.h create mode 100644 uc_str912/prj_blinky_complex_startup/91x_conf.h create mode 100644 uc_str912/prj_blinky_complex_startup/Makefile create mode 100644 uc_str912/prj_blinky_complex_startup/defines.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_adc.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_ahbapb.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_can.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_dma.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_emi.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_fmi.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_gpio.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_i2c.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_it.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_lib.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_map.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_mc.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_rtc.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_scu.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_ssp.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_tim.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_type.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_uart.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_vic.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_wdg.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/91x_wiu.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/usb_core.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/usb_def.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/usb_init.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/usb_lib.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/usb_mem.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/usb_regs.h create mode 100644 uc_str912/prj_blinky_complex_startup/include/usb_type.h create mode 100644 uc_str912/prj_blinky_complex_startup/interrupt.c create mode 100644 uc_str912/prj_blinky_complex_startup/inthandler.S create mode 100644 uc_str912/prj_blinky_complex_startup/load_segger.gdb create mode 100644 uc_str912/prj_blinky_complex_startup/main.c create mode 100644 uc_str912/prj_blinky_complex_startup/main.h create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_adc.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_ahbapb.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_can.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_dma.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_emi.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_fmi.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_gpio.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_i2c.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_lib.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_mc.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_rtc.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_scu.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_ssp.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_tim.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_uart.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_vic.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_wdg.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/91x_wiu.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/usb_core.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/usb_init.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/usb_int.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/usb_mem.c create mode 100644 uc_str912/prj_blinky_complex_startup/src/usb_regs.c create mode 100644 uc_str912/prj_blinky_complex_startup/startup912.S create mode 100644 uc_str912/prj_blinky_complex_startup/startup912.S_old create mode 100644 uc_str912/prj_blinky_complex_startup/startup_generic.S create mode 100644 uc_str912/prj_blinky_complex_startup/syscalls.c create mode 100644 uc_str912/prj_blinky_simple_startup/Makefile create mode 100644 uc_str912/prj_blinky_simple_startup/STR91x-RAM.ld create mode 100644 uc_str912/prj_blinky_simple_startup/STR91x-ROM.ld create mode 100644 uc_str912/prj_blinky_simple_startup/include/vectors.h create mode 100644 uc_str912/prj_blinky_simple_startup/load_segger.gdb create mode 100644 uc_str912/prj_blinky_simple_startup/src/main.c create mode 100644 uc_str912/prj_blinky_simple_startup/src/startup.s create mode 100644 uc_str912/prj_blinky_simple_startup/src/vector.s create mode 100644 uc_str912/prj_blinky_simple_startup/src/vectors.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/Makefile create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_adc.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_ahbapb.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_can.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_conf.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_dma.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_emi.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_fmi.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_gpio.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_i2c.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_it.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_lib.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_map.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_mc.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_rtc.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_scu.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_ssp.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_tim.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_type.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_uart.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_vic.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_wdg.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_wiu.h create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_adc.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_ahbapb.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_can.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_dma.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_emi.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_fmi.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_gpio.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_i2c.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_lib.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_mc.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_rtc.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_scu.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_ssp.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_tim.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_uart.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_vic.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_wdg.c create mode 100644 uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_wiu.c create mode 100644 uc_str912/prj_main_add/Makefile create mode 100644 uc_str912/prj_main_add/dram.bat create mode 100644 uc_str912/prj_main_add/inc/typedefs.h create mode 100644 uc_str912/prj_main_add/prj/eclipse_ram.gdb create mode 100644 uc_str912/prj_main_add/prj/eclipse_rom.gdb create mode 100644 uc_str912/prj_main_add/prj/jtagkey.cfg create mode 100644 uc_str912/prj_main_add/prj/str912_program.script create mode 100644 uc_str912/prj_main_add/prj/str912_ram.gdb create mode 100644 uc_str912/prj_main_add/prj/str912_ram.ld create mode 100644 uc_str912/prj_main_add/prj/str912_reset.script create mode 100644 uc_str912/prj_main_add/prj/str912_rom.gdb create mode 100644 uc_str912/prj_main_add/prj/str912_rom.ld create mode 100644 uc_str912/prj_main_add/segger.gdb create mode 100644 uc_str912/prj_main_add/src/main.c create mode 100644 uc_str912/prj_main_add/src/startup.s create mode 100644 uc_str912/prj_template91x/Makefile create mode 100644 uc_str912/prj_template91x/STR91x-RAM.ld create mode 100644 uc_str912/prj_template91x/STR91x-ROM.ld create mode 100644 uc_str912/prj_template91x/include/vectors.h create mode 100644 uc_str912/prj_template91x/load_segger.gdb create mode 100644 uc_str912/prj_template91x/src/main.c create mode 100755 uc_str912/prj_template91x/src/startup.S create mode 100755 uc_str912/prj_template91x/src/vector.S create mode 100644 uc_str912/prj_template91x/src/vectors.c create mode 100644 uc_str912/prj_template91x/str91x_lib/Makefile create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_adc.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_ahbapb.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_can.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_conf.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_dma.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_emi.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_fmi.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_gpio.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_i2c.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_it.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_lib.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_map.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_mc.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_rtc.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_scu.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_ssp.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_tim.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_type.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_uart.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_vic.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_wdg.h create mode 100644 uc_str912/prj_template91x/str91x_lib/include/91x_wiu.h create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_adc.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_ahbapb.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_can.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_dma.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_emi.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_fmi.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_gpio.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_i2c.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_lib.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_mc.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_rtc.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_scu.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_ssp.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_tim.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_uart.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_vic.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_wdg.c create mode 100644 uc_str912/prj_template91x/str91x_lib/src/91x_wiu.c create mode 100644 uc_str912/prj_test_lcd/Makefile create mode 100644 uc_str912/prj_test_lcd/STR91x-ROM.ld create mode 100644 uc_str912/prj_test_lcd/include/91x_ahbapb.h create mode 100644 uc_str912/prj_test_lcd/include/91x_conf.h create mode 100644 uc_str912/prj_test_lcd/include/91x_fmi.h create mode 100644 uc_str912/prj_test_lcd/include/91x_gpio.h create mode 100644 uc_str912/prj_test_lcd/include/91x_lib.h create mode 100644 uc_str912/prj_test_lcd/include/91x_map.h create mode 100644 uc_str912/prj_test_lcd/include/91x_scu.h create mode 100644 uc_str912/prj_test_lcd/include/91x_type.h create mode 100644 uc_str912/prj_test_lcd/include/char_code.h create mode 100644 uc_str912/prj_test_lcd/include/lcd_lib_91x.h create mode 100644 uc_str912/prj_test_lcd/include/vectors.h create mode 100644 uc_str912/prj_test_lcd/load_amontec.gdb create mode 100644 uc_str912/prj_test_lcd/load_segger.gdb create mode 100644 uc_str912/prj_test_lcd/src/lcd.c create mode 100644 uc_str912/prj_test_lcd/src/lcd_lib_91x.c create mode 100644 uc_str912/prj_test_lcd/src/startup.s create mode 100644 uc_str912/prj_test_lcd/src/vector.s create mode 100644 uc_str912/prj_test_lcd/src/vectors.c create mode 100644 uc_str912/prj_test_lcd/str91x_lib/91x_ahbapb.c create mode 100644 uc_str912/prj_test_lcd/str91x_lib/91x_fmi.c create mode 100644 uc_str912/prj_test_lcd/str91x_lib/91x_gpio.c create mode 100644 uc_str912/prj_test_lcd/str91x_lib/91x_lib.c create mode 100644 uc_str912/prj_test_lcd/str91x_lib/91x_scu.c create mode 100644 uc_str912/scripts/flash_str9.ld create mode 100644 uc_str912/scripts/load.gdb create mode 100644 uc_str912/scripts/load_amontec.gdb create mode 100644 uc_str912/scripts/load_segger.gdb create mode 100644 uc_str912/scripts/str912_rom.ld create mode 100644 uc_str912/scripts/str912fw44.ld create mode 100644 uc_str912/scripts/str91x-configs/str91x_flash.gdb create mode 100644 uc_str912/scripts/str91x-configs/str91x_flasherase.ocd create mode 100644 uc_str912/scripts/str91x-configs/str91x_flashprobe.gdb create mode 100644 uc_str912/scripts/str91x-configs/str91x_flashprogram.ocd create mode 100644 uc_str912/scripts/str91x-configs/str91x_jtagkey-flash-erase.cfg create mode 100644 uc_str912/scripts/str91x-configs/str91x_jtagkey-flash-program.cfg create mode 100644 uc_str912/scripts/str91x-configs/str91x_jtagkey.cfg create mode 100644 uc_str912/scripts/str91x-configs/str91x_ram.gdb create mode 100644 uc_str912/scripts/test.gdb create mode 100644 uc_str912/segger.gdb diff --git a/uc_str912/erase_flash/Makefile b/uc_str912/erase_flash/Makefile new file mode 100644 index 0000000..b8b8b61 --- /dev/null +++ b/uc_str912/erase_flash/Makefile @@ -0,0 +1,10 @@ +all: erase + +erase: erase.o erase_jlink.gdb + arm-none-eabi-gdb -x erase_jlink.gdb + +erase.o: erase.S + arm-none-eabi-as erase.S -o erase.o + +clean: + rm -f erase.o diff --git a/uc_str912/erase_flash/erase.S b/uc_str912/erase_flash/erase.S new file mode 100644 index 0000000..6abf4fc --- /dev/null +++ b/uc_str912/erase_flash/erase.S @@ -0,0 +1,3 @@ +/* erase.S */ +.text +.space 1024*512 diff --git a/uc_str912/erase_flash/erase_jlink.gdb b/uc_str912/erase_flash/erase_jlink.gdb new file mode 100644 index 0000000..ddf866e --- /dev/null +++ b/uc_str912/erase_flash/erase_jlink.gdb @@ -0,0 +1,7 @@ +target remote :2331 +monitor endian little +monitor flash download = 1 +monitor flash device = STR912FAW44 +load erase.o +monitor reset +quit diff --git a/uc_str912/openocd/amontec.sh b/uc_str912/openocd/amontec.sh new file mode 100755 index 0000000..c49c229 --- /dev/null +++ b/uc_str912/openocd/amontec.sh @@ -0,0 +1,3 @@ +#!/bin/sh +openocd -f openocd_amontec.cfg +#--debug 3 diff --git a/uc_str912/openocd/openocd_amontec.cfg b/uc_str912/openocd/openocd_amontec.cfg new file mode 100644 index 0000000..16e806c --- /dev/null +++ b/uc_str912/openocd/openocd_amontec.cfg @@ -0,0 +1,26 @@ +source [find interface/jtagkey-tiny.cfg] + +#avoid warning bei detection +set BSTAPID 0x2457f041 +source str912.cfg + +# at 25 MHz JTAG should run with 4166 kHz +# 16 = 450 bytes/sec +# 32 = 870 bytes/sec +# 64 = 1 kbyte/sec c bleibt nicht stehen +# 127 = 2 kbyte/sec c bleibt nicht stehen +# 250 = 4 kbyte/sec +# 500 = 5 kbyte/sec +# 1000 = 7 kbyte/sec +# 2000 = 8 kbyte/sec +# 3000 = 8 kbyte/sec + +#jtag_rclk 4166 # enable later + +# gdb_breakpoint_override hard # geht +# gdb_flash_program enable # geht nicht +# gdb_memory_map enable # geht nicht +# gdb_report_data_abort # geht nicht + +arm7_9 dcc_downloads enable +arm7_9 fast_memory_access enable diff --git a/uc_str912/openocd/openocd_segger.cfg b/uc_str912/openocd/openocd_segger.cfg new file mode 100644 index 0000000..3a1fc14 --- /dev/null +++ b/uc_str912/openocd/openocd_segger.cfg @@ -0,0 +1,6 @@ +#gdb_memory_map enable # fehler bei openocd start +#gdb_flash_program enable # fehler bei openocd start +source [find interface/jlink.cfg] +# avoid warning bei detection +set BSTAPID 0x2457f041 +source str912.cfg diff --git a/uc_str912/openocd/segger.sh b/uc_str912/openocd/segger.sh new file mode 100755 index 0000000..47cf43d --- /dev/null +++ b/uc_str912/openocd/segger.sh @@ -0,0 +1,2 @@ +#!/bin/sh +openocd -f openocd_segger.cfg diff --git a/uc_str912/openocd/str912.cfg b/uc_str912/openocd/str912.cfg new file mode 100644 index 0000000..108ae9c --- /dev/null +++ b/uc_str912/openocd/str912.cfg @@ -0,0 +1,131 @@ +# script for str9 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str912 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# jtag speed. We need to stick to 16kHz until we've finished reset. +jtag_rclk 16 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst +#reset_config trst_only + +if { [info exists FLASHTAPID ] } { + set _FLASHTAPID $FLASHTAPID +} else { + set _FLASHTAPID 0x04570041 +} +jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966041 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + +if { [info exists BSTAPID ] } { + set _BSTAPID $BSTAPID +} else { + set _BSTAPID 0x1457f041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e + +$_TARGETNAME configure -event reset-start { jtag_rclk 16 } + +$_TARGETNAME configure -event reset-init { + # We can increase speed now that we know the target is halted. + jtag_rclk 2000 + + # -- Enable 96K RAM + # PFQBC enabled / DTCM & AHB wait-states disabled + mww 0x5C002034 0x0191 + + flash banks + flash probe 0 + + #str9x flash_config + str9x flash_config 0 4 2 0x0 0x80000 + + #nbsize register = 0 : means 8kBytes (written in the STR9 flash programming manual) + #nbsize register = 2 : means 32kBytes (written in the STR9 flash programming manual) + #bbsize register = 4 : means 512kBytes (written in the STR9 flash programming manual) + + + flash protect 0 0 7 off + flash protect_check 0 +# flash info 0 + + flash protect 1 0 3 off + flash protect_check 1 +# flash info 1 + + flash auto_erase on +} + +#$_TARGETNAME configure -work-area-phys 0x04000000 -work-area-size 16384 -work-area-backup 0 +$_TARGETNAME configure -work-area-phys 0x04000000 -work-area-size 0x18000 -work-area-backup 0 + +#flash bank str9x 0 0 +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 $_TARGETNAME + + + + +$_TARGETNAME configure -event debug-halted { + puts "Running debug halted script for EBx00 Board" +} + + +$_TARGETNAME configure -event gdb-attach { + puts "Running gdb-attach script for EBx00 Board" +} + + +$_TARGETNAME configure -event gdb-detach { + puts "Running gdb-detach script for EBx00 Board" +} + + +$_TARGETNAME configure -event gdb-flash-erase-start { + puts "Running gdb-flash-erase-start script for EBx00 Board" +} + + +$_TARGETNAME configure -event gdb-flash-erase-end { + puts "Running gdb-flash-erase-end script for EBx00 Board" +} + + +$_TARGETNAME configure -event gdb-start { + puts "Running gdb_start script for EBx00 Board" +} + + + +$_TARGETNAME configure -event gdb-end { + puts "Running gdb_halted script for EBx00 Board" +} + + +# For more information about the configuration files, take a look at: +# openocd.texi diff --git a/uc_str912/prj_TEST_LED/Makefile b/uc_str912/prj_TEST_LED/Makefile new file mode 100644 index 0000000..a7f04ba --- /dev/null +++ b/uc_str912/prj_TEST_LED/Makefile @@ -0,0 +1,496 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# WinARM template makefile +# by Giacomo Fazio and Antonio Nasca, Catania, Italy +# +# +# +# based on the WinARM template makefile written by Martin Thomas +# Released to the Public Domain +# Please read the make user manual! +# +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make program = Download the hex file to the device +# +# (TODO: make filename.s = Just compile filename.c into the assembler code only) +# +# To rebuild project do "make clean" then "make all". +# Toolchain prefix (i.e arm-elf -> arm-elf-gcc.exe) +#TCHAIN = arm-elf +TCHAIN = arm-none-eabi + +#USE_THUMB_MODE = YES +USE_THUMB_MODE = NO + +# MCU name and submodel +MCU = arm966e-s +SUBMDL = STR91x + +## Create ROM-Image +RUN_MODE=ROM_RUN +## Create RAM-Image +#RUN_MODE=RAM_RUN + +## not supported in this example: +## Exception-Vector placement only supported for "ROM_RUN" +## (placement settings ignored when using "RAM_RUN") +## - Exception vectors in ROM: +#VECTOR_LOCATION=VECTORS_IN_ROM +## - Exception vectors in RAM: +#VECTOR_LOCATION=VECTORS_IN_RAM + + +# Target file name (without extension). +TARGET = led + +# List C source files here. (C dependencies are automatically generated.) +# use file-extension c for "c-only"-files +SRC = $(TARGET).c str91x_lib/91x_scu.c str91x_lib/91x_gpio.c + +# List C source files here which must be compiled in ARM-Mode. +# use file-extension c for "c-only"-files +SRCARM = vectors.c +# thumb is possible too for vectors.c - keep ARM, TODO: profile + +# List C++ source files here. +# use file-extension cpp for C++-files (use extension .cpp) +CPPSRC = + +# List C++ source files here which must be compiled in ARM-Mode. +# use file-extension cpp for C++-files (use extension .cpp) +#CPPSRCARM = $(TARGET).cpp +CPPSRCARM = + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +# List Assembler source files here which must be assembled in ARM-Mode.. +ASRCARM = vector.S startup.S + +# Path to Linker-Scripts +LINKERSCRIPTPATH = . + +## Output format. (can be ihex or binary or both) +## (binary i.e. for openocd and SAM-BA, hex i.e. for lpc21isp and uVision) +#FORMAT = ihex +#FORMAT = binary +FORMAT = both + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +#OPT = s +OPT = 0 + +## Using the Atmel AT91_lib produces warning with +## the default warning-levels. +## yes - disable these warnings; no - keep default settings +#AT91LIBNOWARN = yes +AT91LIBNOWARN = no + +# Debugging format. +# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2. +# AVR (extended) COFF requires stabs, plus an avr-objcopy run. +#DEBUG = stabs +DEBUG = dwarf-2 + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +EXTRAINCDIRS = ./include ./str91x_lib/include + +# List any extra directories to look for library files here. +# Each directory must be seperated by a space. +#EXTRA_LIBDIRS = ../arm7_efsl_0_2_4 +EXTRA_LIBDIRS = ./str91x_lib + + +# Compiler flag to set the C Standard level. +# c89 - "ANSI" C +# gnu89 - c89 plus GCC extensions +# c99 - ISO C99 standard (not yet fully implemented) +# gnu99 - c99 plus GCC extensions +CSTANDARD = -std=gnu99 + +# Place -D or -U options for C here +CDEFS = -D$(RUN_MODE) + +# Place -I options here +CINCS = + +# Place -D or -U options for ASM here +ADEFS = -D$(RUN_MODE) + +ifdef VECTOR_LOCATION +CDEFS += -D$(VECTOR_LOCATION) +ADEFS += -D$(VECTOR_LOCATION) +endif + +CDEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__ +ADEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__ + +# Compiler flags. + +ifeq ($(USE_THUMB_MODE),YES) +THUMB = -mthumb +THUMB_IW = -mthumb-interwork +else +THUMB = +THUMB_IW = +endif + +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +# +# Flags for C and C++ (arm-elf-gcc/arm-elf-g++) +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) $(CINCS) +CFLAGS += -O$(OPT) +CFLAGS += -Wall -Wcast-align -Wimplicit +CFLAGS += -Wpointer-arith -Wswitch +CFLAGS += -ffunction-sections -fdata-sections +CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused +CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +# flags only for C +CONLYFLAGS += -Wnested-externs +CONLYFLAGS += $(CSTANDARD) + +ifneq ($(AT91LIBNOWARN),yes) +#AT91-lib warnings with: +CFLAGS += -Wcast-qual +CONLYFLAGS += -Wmissing-prototypes +CONLYFLAGS += -Wstrict-prototypes +CONLYFLAGS += -Wmissing-declarations +endif + +# flags only for C++ (arm-elf-g++) +# CPPFLAGS = -fno-rtti -fno-exceptions +CPPFLAGS = + +# Assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlns: create listing +# -g$(DEBUG): have the assembler create line number information +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG) + + +#Additional libraries. + +# Extra libraries +# Each library-name must be seperated by a space. +# To add libxyz.a, libabc.a and libefsl.a: +# EXTRA_LIBS = xyz abc efsl +#EXTRA_LIBS = efsl +EXTRA_LIBS = +#STR91x_lib + +#Support for newlibc-lpc (file: libnewlibc-lpc.a) +#NEWLIBLPC = -lnewlib-lpc + +MATH_LIB = -lm + +# CPLUSPLUS_LIB = -lstdc++ + + +# Linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref,--gc-sections,--no-warn-mismatch +LDFLAGS += -lc +LDFLAGS += $(NEWLIBLPC) $(MATH_LIB) +LDFLAGS += -lc -lgcc +LDFLAGS += $(CPLUSPLUS_LIB) +LDFLAGS += $(patsubst %,-L%,$(EXTRA_LIBDIRS)) +LDFLAGS += $(patsubst %,-l%,$(EXTRA_LIBS)) + +# Set Linker-Script Depending On Selected Memory and Controller +ifeq ($(RUN_MODE),RAM_RUN) +LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-RAM.ld +else +LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-ROM.ld +endif + + +# Define directories, if needed. +## DIRARM = c:/WinARM/ +## DIRARMBIN = $(DIRAVR)/bin/ +## DIRAVRUTILS = $(DIRAVR)/utils/bin/ + +# Define programs and commands. +SHELL = sh +CC = $(TCHAIN)-gcc +CPP = $(TCHAIN)-g++ +AR = $(TCHAIN)-ar +OBJCOPY = $(TCHAIN)-objcopy +OBJDUMP = $(TCHAIN)-objdump +SIZE = $(TCHAIN)-size +NM = $(TCHAIN)-nm +REMOVE = rm -f +REMOVEDIR = rm -f -r +COPY = cp + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = "-------- begin (mode: $(RUN_MODE)) --------" +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_FLASH = Creating load file for Flash: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_ARM = "Compiling C (ARM-only):" +MSG_COMPILINGCPP = Compiling C++: +MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):" +MSG_ASSEMBLING = Assembling: +MSG_ASSEMBLING_ARM = "Assembling (ARM-only):" +MSG_CLEANING = Cleaning project: +MSG_FORMATERROR = Can not handle output-format +MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now. + +# Define all object files. +COBJ = $(SRC:.c=.o) +AOBJ = $(ASRC:.S=.o) +COBJARM = $(SRCARM:.c=.o) +AOBJARM = $(ASRCARM:.S=.o) +CPPOBJ = $(CPPSRC:.cpp=.o) +CPPOBJARM = $(CPPSRCARM:.cpp=.o) + +# Define all listing files. +LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst) +LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst) + +# Compiler flags to generate dependency files. +### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d +GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS) + + +# Default target. +all: begin gccversion sizebefore build sizeafter finished end + +ifeq ($(FORMAT),ihex) +build: elf hex lss sym +hex: $(TARGET).hex +IMGEXT=hex +else +ifeq ($(FORMAT),binary) +build: elf bin lss sym +bin: $(TARGET).bin +IMGEXT=bin +else +ifeq ($(FORMAT),both) +build: elf hex bin lss sym +hex: $(TARGET).hex +bin: $(TARGET).bin +else +$(error "$(MSG_FORMATERROR) $(FORMAT)") +endif +endif +endif + +elf: $(TARGET).elf +lss: $(TARGET).lss +sym: $(TARGET).sym + +# Eye candy. +begin: + @echo + @echo $(MSG_BEGIN) + +finished: + @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf +sizebefore: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + + +# Display compiler version information. +gccversion : + @$(CC) --version + +# FLASH Programming with OPENOCD + +# specify the directory where openocd executable resides (openocd-ftd2xx.exe or openocd-pp.exe) +# Note: you may have to adjust this if a newer version of YAGARTO has been downloaded +OPENOCD_DIR = 'c:\Programmi\openocd\bin\' + +# specify OpenOCD executable (pp is for the wiggler, ftd2xx is for the USB debugger) +OPENOCD = $(OPENOCD_DIR)openocd-pp.exe +#OPENOCD = $(OPENOCD_DIR)openocd-ftd2xx.exe + +# specify OpenOCD configuration file (pick the one for your device) +#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_signalyzer-flash-program.cfg +#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_jtagkey-flash-program.cfg +#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_armusbocd-flash-program.cfg +OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_pp-flash-program.cfg + +program: + @echo + @echo "Flash Programming with OpenOCD..." + $(OPENOCD) -f $(OPENOCD_CFG) + @echo + @echo + @echo "Flash Programming Finished." + + +# Create final output file (.hex) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O ihex $< $@ + +# Create final output file (.bin) from ELF output file. +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary $< $@ + + +# Create extended listing file from ELF output file. +# testing: option -C +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S -C $< > $@ + + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) +%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) +# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) + +# Compile: create object files from C source files. ARM/Thumb +$(COBJ) : %.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C source files. ARM-only +$(COBJARM) : %.o : %.c + @echo + @echo $(MSG_COMPILING_ARM) $< + $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM/Thumb +$(CPPOBJ) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP) $< + $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM-only +$(CPPOBJARM) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP_ARM) $< + $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. ARM/Thumb +## does not work - TODO - hints welcome +##$(COBJ) : %.s : %.c +## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM/Thumb +$(AOBJ) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM-only +$(AOBJARM) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING_ARM) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list finished end + + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).a90 + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lnk + $(REMOVE) $(TARGET).lss + $(REMOVE) $(COBJ) + $(REMOVE) $(CPPOBJ) + $(REMOVE) $(AOBJ) + $(REMOVE) $(COBJARM) + $(REMOVE) $(CPPOBJARM) + $(REMOVE) $(AOBJARM) + $(REMOVE) $(LST) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRCARM:.c=.s) + $(REMOVE) $(SRCARM:.c=.d) + $(REMOVE) $(CPPSRC:.cpp=.s) + $(REMOVE) $(CPPSRC:.cpp=.d) + $(REMOVE) $(CPPSRCARM:.cpp=.s) + $(REMOVE) $(CPPSRCARM:.cpp=.d) + $(REMOVEDIR) .dep | exit 0 + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin lss sym clean clean_list program + diff --git a/uc_str912/prj_TEST_LED/STR91x-RAM.ld b/uc_str912/prj_TEST_LED/STR91x-RAM.ld new file mode 100644 index 0000000..aced384 --- /dev/null +++ b/uc_str912/prj_TEST_LED/STR91x-RAM.ld @@ -0,0 +1,218 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 256; + _STACKSIZE_SVC = 0; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t .glue_7) + KEEP(*(.fini)) + *(.gcc_except_table) + } >DATA =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >DATA + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >DATA + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >DATA + . = ALIGN(4); + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } >DATA + . = ALIGN(4); + + __data_start = .; + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/prj_TEST_LED/STR91x-ROM.ld b/uc_str912/prj_TEST_LED/STR91x-ROM.ld new file mode 100644 index 0000000..ed2979b --- /dev/null +++ b/uc_str912/prj_TEST_LED/STR91x-ROM.ld @@ -0,0 +1,221 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 256; + _STACKSIZE_SVC = 0; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t .glue_7) + KEEP(*(.fini)) + *(.gcc_except_table) + } >CODE =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >CODE + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >CODE + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >CODE + . = ALIGN(4); + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + __data_start = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + . = ALIGN(4); + *(.fastrun .fastrun.*) + } >DATA + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/prj_TEST_LED/include/91x_ahbapb.h b/uc_str912/prj_TEST_LED/include/91x_ahbapb.h new file mode 100644 index 0000000..1828d48 --- /dev/null +++ b/uc_str912/prj_TEST_LED/include/91x_ahbapb.h @@ -0,0 +1,60 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* AHBAPB software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _91x_AHBAPB_H +#define _91x_AHBAPB_H + +#include "91x_map.h" + +#define AHBAPB_Split_Enable 0x01000000 +#define AHBAPB_Split_Disable 0xFEFFFFFF +#define AHBAPB_Error_Enable 0x0000100 +#define AHBAPB_Error_Disable 0xFFFFEFF + +/*FLAG*/ +#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/ +#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */ +#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */ +#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/ + +/* Includes ------------------------------------------------------------------*/ + + +/* AHBAPB Init structure definition */ +typedef struct +{ + u32 AHBAPB_SetTimeOut; + u32 AHBAPB_Error; + u32 AHBAPB_Split; + u8 AHBAPB_SplitCounter; +}AHBAPB_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx); +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct); +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct); +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx); + + +#endif /* _91x_AHBAPB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/include/91x_conf.h b/uc_str912/prj_TEST_LED/include/91x_conf.h new file mode 100644 index 0000000..578335d --- /dev/null +++ b/uc_str912/prj_TEST_LED/include/91x_conf.h @@ -0,0 +1,115 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_conf.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Library configuration. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +#ifndef __91x_CONF_H +#define __91x_CONF_H + +/* To work in buffered mode just decomment the following line */ + +//#define Buffered + +/* Comment the line below to put the library in release mode */ +//#define DEBUG + +/************************* AHBAPB *************************/ +//#define _AHBAPB +//#define _AHBAPB0 +//#define _AHBAPB1 +/************************* VIC *************************/ +//#define _VIC +//#define _VIC0 +//#define _VIC1 +/************************* DMA *************************/ +//#define _DMA +//#define _DMA_Channel0 +//#define _DMA_Channel1 +//#define _DMA_Channel2 +//#define _DMA_Channel3 +//#define _DMA_Channel4 +//#define _DMA_Channel5 +//#define _DMA_Channel6 +//#define _DMA_Channel7 + +/************************* EMI *************************/ +//#define _EMI +//#define _EMI_Bank0 +//#define _EMI_Bank1 +//#define _EMI_Bank2 +//#define _EMI_Bank3 +/************************* FMI *************************/ +//#define _FMI +/************************* WIU *************************/ +//#define _WIU +/************************* TIM *************************/ +//#define _TIM +//#define _TIM0 +//#define _TIM1 +//#define _TIM2 +//#define _TIM3 +/************************* GPIO ************************/ +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 +#define _GPIO3 +#define _GPIO4 +#define _GPIO5 +#define _GPIO6 +#define _GPIO7 +#define _GPIO8 +#define _GPIO9 +/************************* RTC *************************/ +//#define _RTC +/************************* SCU *************************/ +#define _SCU +/************************* MC **************************/ +//#define _MC +/************************* UART ************************/ +//#define _UART +//#define _UART0 +//#define _UART1 +//#define _UART2 +/************************* SSP *************************/ +//#define _SSP +//#define _SSP0 +//#define _SSP1 +/************************* CAN *************************/ +//#define _CAN +/************************* ADC *************************/ +//#define _ADC +/************************* WDG *************************/ +//#define _WDG +/************************* I2C *************************/ +//#define _I2C +//#define _I2C0 +//#define _I2C1 +/************************ ENET *************************/ +//#define _ENET + +/*---------------------------- _Main_Crystal frequency value (KHz)------------*/ + +#ifndef _Main_Crystal +#define _Main_Crystal 25000 +#endif +/*------------------------------------------------------------------------------*/ + + +#endif /* __91x_CONF_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/include/91x_fmi.h b/uc_str912/prj_TEST_LED/include/91x_fmi.h new file mode 100644 index 0000000..06e8115 --- /dev/null +++ b/uc_str912/prj_TEST_LED/include/91x_fmi.h @@ -0,0 +1,184 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* FMI software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef __91x_FMI_H +#define __91x_FMI_H + +/* ========================================================================== */ +/* When bank 1 is remapped at address 0x0, decomment the following line */ +/* ========================================================================== */ + +//#define Remap_Bank_1 + + +/* Includes ------------------------------------------------------------------*/ + +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* FMI banks */ + +#ifdef Remap_Bank_1 + +#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */ + +#else /* Remap Bank 0 */ + +#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */ + +#endif + +/* FMI sectors */ + +#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */ +#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */ +#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */ +#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */ +#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */ +#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */ +#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */ +#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */ + +#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */ +#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */ +#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */ +#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */ + +/* FMI Flags */ + +#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */ +#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */ +#define FMI_FLAG_PS 0x10 /* Program Status Flag */ +#define FMI_FLAG_ES 0x20 /* Erase Status Flag */ +#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */ +#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */ + +/* FMI read wait states */ + +#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */ +#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */ +#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */ + +/* FMI write wait states */ + +#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */ +#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */ + +/* FMI power down configuration */ + +#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */ +#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */ + +/* FMI low voltage detector */ + +#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */ +#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */ + +/* FMI frequency range */ + +#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */ +#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */ + /* Above 66 MHz*/ +/* FMI OTP word addresses */ + +#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */ +#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */ +#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */ +#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */ +#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */ +#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */ +#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */ +#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */ + +/* FMI OTP halfword addresses */ + +#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */ +#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */ +#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */ +#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */ +#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */ +#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */ +#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */ +#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */ +#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */ +#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */ +#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */ +#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */ +#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */ +#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */ +#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */ +#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */ + +/* FMI sectors Masks */ + +#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */ +#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */ +#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */ +#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */ +#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */ +#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */ +#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */ +#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */ + +#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */ +#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */ +#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */ +#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */ + +/* Timeout error */ + +#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */ +#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress); +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange); +void FMI_EraseSector(vu32 FMI_Sector); +void FMI_EraseBank(vu32 FMI_Bank); +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data); +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData); +u32 FMI_ReadWord(u32 FMI_Address); +u32 FMI_ReadOTPData(u8 FMI_OTPAddress); +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank); +u16 FMI_GetReadWaitStateValue(void); +u16 FMI_GetWriteWaitStateValue(void); +void FMI_SuspendEnable(vu32 FMI_Bank); +void FMI_ResumeEnable(vu32 FMI_Bank); +void FMI_ClearFlag(vu32 FMI_Bank); +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState); +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection); +u8 FMI_WaitForLastOperation(vu32 FMI_Bank); + +#endif /* __91x_FMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_TEST_LED/include/91x_gpio.h b/uc_str912/prj_TEST_LED/include/91x_gpio.h new file mode 100644 index 0000000..4beab75 --- /dev/null +++ b/uc_str912/prj_TEST_LED/include/91x_gpio.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef _91x_GPIO_H +#define _91x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* GPIO Init structure definition */ +typedef struct +{ + u8 GPIO_Pin; + u8 GPIO_Direction; + u8 GPIO_Type; + u8 GPIO_IPConnected; + u16 GPIO_Alternate; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + + +/* Exported constants --------------------------------------------------------*/ +#define GPIO_Pin_None 0x00 +#define GPIO_Pin_0 0x01 +#define GPIO_Pin_1 0x02 +#define GPIO_Pin_2 0x04 +#define GPIO_Pin_3 0x08 +#define GPIO_Pin_4 0x10 +#define GPIO_Pin_5 0x20 +#define GPIO_Pin_6 0x40 +#define GPIO_Pin_7 0x80 +#define GPIO_Pin_All 0xFF + +#define GPIO_PinInput 0x00 +#define GPIO_PinOutput 0x01 + +#define GPIO_Type_PushPull 0x00 +#define GPIO_Type_OpenCollector 0x01 + +#define GPIO_IPConnected_Disable 0x00 +#define GPIO_IPConnected_Enable 0x01 + +#define GPIO_InputAlt1 0x00 +#define GPIO_OutputAlt1 0x01 +#define GPIO_OutputAlt2 0x02 +#define GPIO_OutputAlt3 0x03 + +#define GPIO_ANAChannel0 0x01 +#define GPIO_ANAChannel1 0x02 +#define GPIO_ANAChannel2 0x04 +#define GPIO_ANAChannel3 0x08 +#define GPIO_ANAChannel4 0x10 +#define GPIO_ANAChannel5 0x20 +#define GPIO_ANAChannel6 0x40 +#define GPIO_ANAChannel7 0x80 +#define GPIO_ANAChannelALL 0xFF + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin); +u8 GPIO_Read(GPIO_TypeDef* GPIOx); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal); +void GPIO_EMIConfig(FunctionalState NewState); +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState); + +#endif /* _91x_GPIO_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/include/91x_lib.h b/uc_str912/prj_TEST_LED/include/91x_lib.h new file mode 100644 index 0000000..823b250 --- /dev/null +++ b/uc_str912/prj_TEST_LED/include/91x_lib.h @@ -0,0 +1,114 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Used to include the peripherals header file in the +* user application. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __91x_LIB_H +#define __91x_LIB_H + +#include "91x_map.h" +#include "91x_conf.h" + +#ifdef _AHBAPB + #include "91x_ahbapb.h" +#endif /* _AHBAPB */ + +#ifdef _EMI + #include "91x_emi.h" +#endif /* _EMI */ + +#ifdef _DMA + #include "91x_dma.h" +#endif /* _DMA */ + +#ifdef _FMI + #include "91x_fmi.h" +#endif /* _FMI */ + +#ifdef _VIC + #include "91x_vic.h" +#endif /* _VIC */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif /* _WIU */ + +#ifdef _TIM + #include "91x_tim.h" +#endif /* _TIM */ + +#ifdef _GPIO + #include "91x_gpio.h" +#endif /* _GPIO */ + +#ifdef _RTC + #include "91x_rtc.h" +#endif /* _RTC */ + +#ifdef _SCU + #include "91x_scu.h" +#endif /* _SCU */ + +#ifdef _UART + #include "91x_uart.h" +#endif /* _UART */ + +#ifdef _SSP + #include "91x_ssp.h" +#endif /* _SSP */ + +#ifdef _CAN + #include "91x_can.h" +#endif /* _CAN */ + +#ifdef _ADC + #include "91x_adc.h" +#endif /* _ADC */ + +#ifdef _WDG + #include "91x_wdg.h" +#endif /* _WDG */ + +#ifdef _I2C + #include "91x_i2c.h" +#endif /* _I2C */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif + +#ifdef _MC + #include "91x_mc.h" +#endif + +#ifdef _ENET + #include "91x_enet.h" +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + void debug( void ); + + +#endif /* __91x_LIB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/include/91x_map.h b/uc_str912/prj_TEST_LED/include/91x_map.h new file mode 100644 index 0000000..2e94a91 --- /dev/null +++ b/uc_str912/prj_TEST_LED/include/91x_map.h @@ -0,0 +1,878 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_map.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Peripherals registers definition and memory mapping. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_MAP_H +#define __91x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_conf.h" +#include "91x_type.h" + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------------------ FMI -----------------------------------*/ + +typedef struct +{ + vu32 BBSR; /* Boot Bank Size Register */ + vu32 NBBSR; /* Non-Boot Bank Size Register */ + vu32 EMPTY1; + vu32 BBADR; /* Boot Bank Base Address Register */ + vu32 NBBADR; /* Non-Boot Bank Base Address Register */ + vu32 EMPTY2; + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */ +} FMI_TypeDef; + +/*---------------------- Analog to Digital Convertor ------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 CCR; /* Channel Configuration Register */ + vu16 EMPTY2; + vu16 HTR; /* Higher Threshold Register */ + vu16 EMPTY3; + vu16 LTR; /* Lower Threshold Register */ + vu16 EMPTY4; + vu16 CRR; /* Compare Result Register */ + vu16 EMPTY5; + vu16 DR0; /* Data Register for Channel 0 */ + vu16 EMPTY6; + vu16 DR1; /* Data Register for Channel 1 */ + vu16 EMPTY7; + vu16 DR2; /* Data Register for Channel 2 */ + vu16 EMPTY8; + vu16 DR3; /* Data Register for Channel 3 */ + vu16 EMPTY9; + vu16 DR4; /* Data Register for Channel 4 */ + vu16 EMPTY10; + vu16 DR5; /* Data Register for Channel 5 */ + vu16 EMPTY11; + vu16 DR6; /* Data Register for Channel 6 */ + vu16 EMPTY12; + vu16 DR7; /* Data Register for Channel 7 */ + vu16 EMPTY13; + vu16 PRS; /* Prescaler Value Register */ + vu16 EMPTY14; +} ADC_TypeDef; + +/*--------------------- AHB APB BRIDGE registers strcture --------------------*/ + +typedef struct +{ + vu32 BSR; /* Bridge Status Register */ + vu32 BCR; /* Bridge Configuration Register */ + vu32 PAER; /* Peripheral Address Error register */ +} AHBAPB_TypeDef; + +/*--------------- Controller Area Network Interface Register -----------------*/ + +typedef struct +{ + vu16 CRR; /* IFn Command request Register */ + vu16 EMPTY1; + vu16 CMR; /* IFn Command Mask Register */ + vu16 EMPTY2; + vu16 M1R; /* IFn Message Mask 1 Register */ + vu16 EMPTY3; + vu16 M2R; /* IFn Message Mask 2 Register */ + vu16 EMPTY4; + vu16 A1R; /* IFn Message Arbitration 1 Register */ + vu16 EMPTY5; + vu16 A2R; /* IFn Message Arbitration 2 Register */ + vu16 EMPTY6; + vu16 MCR; /* IFn Message Control Register */ + vu16 EMPTY7; + vu16 DA1R; /* IFn DATA A 1 Register */ + vu16 EMPTY8; + vu16 DA2R; /* IFn DATA A 2 Register */ + vu16 EMPTY9; + vu16 DB1R; /* IFn DATA B 1 Register */ + vu16 EMPTY10; + vu16 DB2R; /* IFn DATA B 2 Register */ + vu16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 SR; /* Status Register */ + vu16 EMPTY2; + vu16 ERR; /* Error counter Register */ + vu16 EMPTY3; + vu16 BTR; /* Bit Timing Register */ + vu16 EMPTY4; + vu16 IDR; /* Interrupt Identifier Register */ + vu16 EMPTY5; + vu16 TESTR; /* Test Register */ + vu16 EMPTY6; + vu16 BRPR; /* BRP Extension Register */ + vu16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + vu16 EMPTY8[16]; + vu16 TXR1R; /* Transmission request 1 Register */ + vu16 EMPTY9; + vu16 TXR2R; /* Transmission Request 2 Register */ + vu16 EMPTY10[13]; + vu16 ND1R; /* New Data 1 Register */ + vu16 EMPTY11; + vu16 ND2R; /* New Data 2 Register */ + vu16 EMPTY12[13]; + vu16 IP1R; /* Interrupt Pending 1 Register */ + vu16 EMPTY13; + vu16 IP2R; /* Interrupt Pending 2 Register */ + vu16 EMPTY14[13]; + vu16 MV1R; /* Message Valid 1 Register */ + vu16 EMPTY15; + vu16 MV2R; /* Message VAlid 2 Register */ + vu16 EMPTY16; +} CAN_TypeDef; + +/*----------------------- System Control Unit---------------------------------*/ + +typedef struct +{ + vu32 CLKCNTR; /* Clock Control Register */ + vu32 PLLCONF; /* PLL Configuration Register */ + vu32 SYSSTATUS; /* System Status Register */ + vu32 PWRMNG; /* Power Management Register */ + vu32 ITCMSK; /* Interrupt Mask Register */ + vu32 PCGRO; /* Peripheral Clock Gating Register 0 */ + vu32 PCGR1; /* Peripheral Clock Gating Register 1 */ + vu32 PRR0; /* Peripheral Reset Register 0 */ + vu32 PRR1; /* Peripheral Reset Register 1 */ + vu32 MGR0; /* Idle Mode Mask Gating Register 0 */ + vu32 MGR1; /* Idle Mode Mask Gating Register 1 */ + vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */ + vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */ + vu32 SCR0; /* System Configuration Register 0 */ + vu32 SCR1; /* System Configuration Register 1 */ + vu32 SCR2; /* System Configuration Register 2 */ + u32 EMPTY1; + vu32 GPIOOUT[8]; /* GPIO Output Registers */ + vu32 GPIOIN[8]; /* GPIO Input Registers */ + vu32 GPIOTYPE[10];/* GPIO Type Registers */ + vu32 GPIOEMI; /* GPIO EMI Selector Register */ + vu32 WKUPSEL; /* Wake-Up Selection Register */ + u32 EMPTY2[2]; + vu32 GPIOANA; /* GPIO Analag mode Register */ +} SCU_TypeDef; + +/*------------------------- DMA Channelx Registers ---------------------------*/ + +typedef struct +{ + vu32 SRC; /* Channelx Source Address Register */ + vu32 DES; /* Channelx Destination Address Register */ + vu32 LLI; /* Channelx Lincked List Item Register */ + vu32 CC; /* Channelx Contol Register */ + vu32 CCNF; /* Channelx Configuration Register */ +} DMA_Channel_TypeDef; + +/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */ + +/*----------------------------- DMA Controller -------------------------------*/ + +typedef struct +{ + vu32 ISR; /* Interrupt Status Register */ + vu32 TCISR; /* Terminal Count Interrupt Status Register */ + vu32 TCICR; /* Terminal CountInterrupt Clear Register */ + vu32 EISR; /* Error Interrupt Status Register */ + vu32 EICR; /* Error Interrupt Clear Register */ + vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */ + vu32 ERISR; /* Raw Error Interrupt Status Register */ + vu32 ENCSR; /* Enabled Channel Status Register */ + vu32 SBRR; /* Software Burst Request Register */ + vu32 SSRR; /* Software Single Request Register */ + vu32 SLBRR; /* Software Last Burst Request Register */ + vu32 SLSRR; /* Software Last Single Request Register */ + vu32 CNFR; /* Configuration Register */ + vu32 SYNR; /* Syncronization Register */ + } DMA_TypeDef; + +/*--------------------------------- TIM Timer --------------------------------*/ + +typedef struct +{ + vu16 IC1R; /* Input Capture 1 Register */ + vu16 EMPTY1; + vu16 IC2R; /* Input Capture 2 Register */ + vu16 EMPTY2; + vu16 OC1R; /* Output Compare 1 Register */ + vu16 EMPTY3; + vu16 OC2R; /* Output Compare 2 Register */ + vu16 EMPTY4; + vu16 CNTR; /* Counter Register */ + vu16 EMPTY5; + vu16 CR1; /* Control Register 1 */ + vu16 EMPTY6; + vu16 CR2; /* Control Register 2 */ + vu16 EMPTY7; + vu16 SR; /* Status Register */ + vu16 EMPTY8; +} TIM_TypeDef; + +/*---------------------------- EMI Bankx Registers ---------------------------*/ + +typedef struct +{ + vu32 ICR; /* Bankx Idle Cycle Control Register */ + vu32 RCR; /* Bankx Read Wait State Control Register */ + vu32 WCR; /* Bankx Write Wait State Control Register */ + vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */ + vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */ + vu32 BCR; /* Bankx Control Register */ + } EMI_Bank_TypeDef; + +/*---------------------------- Ethernet Controller ---------------------------*/ + +/* MAC Registers */ +typedef struct +{ + vu32 MCR; /* ENET Control Register */ + vu32 MAH; /* ENET Address High Register */ + vu32 MAL; /* ENET Address Low Register */ + vu32 MCHA; /* Multicast Address High Register */ + vu32 MCLA; /* Multicast Address Low Register */ + vu32 MIIA; /* MII Address Register */ + vu32 MIID; /* MII Data Register */ + vu32 MCF; /* ENET Control Frame Register */ + vu32 VL1; /* VLAN1 Register */ + vu32 VL2; /* VLAN2 register */ + vu32 MTS; /* ENET Transmission Status Register */ + vu32 MRS; /* ENET Reception Status Register */ +} ENET_MAC_TypeDef; + +/* DMA Registers */ +typedef struct +{ + vu32 SCR; /* DMA Status and Control Register */ + vu32 IER; /* DMA Interrupt Sources Enable Register */ + vu32 ISR; /* DMA Interrupt Status Register */ + vu32 CCR; /* Clock Control Relation : HCLK, PCLK and + ENET_CLK phase relations */ + vu32 RXSTR; /* Rx DMA start Register */ + vu32 RXCR; /* Rx DMA Control Register */ + vu32 RXSAR; /* Rx DMA Base Address Register */ + vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */ + vu32 RXCAR; /* Rx DMA Current Address Register */ + vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */ + vu32 RXTOR; /* Rx DMA FIFO Time Out Register */ + vu32 RXSR; /* Rx DMA FIFO Status Register */ + vu32 TXSTR; /* Tx DMA start Register */ + vu32 TXCR; /* Tx DMA Control Register */ + vu32 TXSAR; /* Tx DMA Base Address Register */ + vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */ + vu32 TXCAR; /* Tx DMA Current Address Register */ + vu32 TXTCR; /* Tx DMA Current Transfer Count Register */ + vu32 TXTOR; /* Tx DMA FIFO Time Out Register */ + vu32 TXSR; /* Tx DMA FIFO Status Register */ +} ENET_DMA_TypeDef; + +/*------------------------------------- GPIO ---------------------------------*/ + +typedef struct +{ + vu8 DR[1021]; /* Data Register */ + vu32 DDR; /* Data Direction Register */ +} GPIO_TypeDef; + +/*-------------------------------- I2C interface -----------------------------*/ + +typedef struct +{ + vu8 CR; /* Control Register */ + vu8 EMPTY1[3]; + vu8 SR1; /* Status Register 1 */ + vu8 EMPTY2[3]; + vu8 SR2; /* Status Register 2 */ + vu8 EMPTY3[3]; + vu8 CCR; /* Clock Control Register */ + vu8 EMPTY4[3]; + vu8 OAR1; /* Own Address Register 1 */ + vu8 EMPTY5[3]; + vu8 OAR2; /* Own Address Register 2 */ + vu8 EMPTY6[3]; + vu8 DR; /* Data Register */ + vu8 EMPTY7[3]; + vu8 ECCR; /* Extended Clock Control Register */ + vu8 EMPTY8[3]; +} I2C_TypeDef; + +/*------------------------------------- VIC ----------------------------------*/ + +typedef struct +{ + vu32 ISR; /* IRQ Status Register */ + vu32 FSR; /* FIQ Status Register */ + vu32 RINTSR; /* Raw Interrupt Status Register */ + vu32 INTSR; /* Interrupt Select Register */ + vu32 INTER; /* Interrupt Enable Register */ + vu32 INTECR; /* Interrupt Enable Clear Register */ + vu32 SWINTR; /* Software Interrupt Register */ + vu32 SWINTCR; /* Software Interrupt clear Register */ + vu32 PER; /* Protection Enable Register */ + vu32 EMPTY1[3]; + vu32 VAR; /* Vector Address Register */ + vu32 DVAR; /* Default Vector Address Register */ + vu32 EMPTY2[50]; + vu32 VAiR[16]; /* Vector Address 0-15 Register */ + vu32 EMPTY3[48]; + vu32 VCiR[16]; /* Vector Control 0-15 Register */ +} VIC_TypeDef; + +/*-------------------------------- Motor Control -----------------------------*/ + +typedef struct +{ + vu16 TCPT; /* Tacho Capture Register */ + vu16 EMPTY1; + vu16 TCMP; /* Tacho Compare Register */ + vu16 EMPTY2; + vu16 IPR; /* Input Pending Register */ + vu16 EMPTY3; + vu16 TPRS; /* Tacho Prescaler Register */ + vu16 EMPTY4; + vu16 CPRS; /* PWM Counter Prescaler Register */ + vu16 EMPTY5; + vu16 REP; /* Repetition Counter Register */ + vu16 EMPTY6; + vu16 CMPW; /* Compare Phase W Preload Register */ + vu16 EMPTY7; + vu16 CMPV; /* Compare Phase V Preload Register */ + vu16 EMPTY8; + vu16 CMPU; /* Compare Phase U Preload Register */ + vu16 EMPTY9; + vu16 CMP0; /* Compare 0 Preload Register */ + vu16 EMPTY10; + vu16 PCR0; /* Peripheral Control Register 0 */ + vu16 EMPTY11; + vu16 PCR1; /* Peripheral Control Register 1 */ + vu16 EMPTY12; + vu16 PCR2; /* Peripheral Control Register 2 */ + vu16 EMPTY13; + vu16 PSR; /* Polarity Selection Register */ + vu16 EMPTY14; + vu16 OPR; /* Output Peripheral Register */ + vu16 EMPTY15; + vu16 IMR; /* Interrupt Mask Register */ + vu16 EMPTY16; + vu16 DTG; /* Dead Time Generator Register */ + vu16 EMPTY17; + vu16 ESC; /* Emergency Stop Clear Register */ + vu16 EMPTY18; +}MC_TypeDef; + +/*------------------------------------- RTC ----------------------------------*/ + +typedef struct +{ + vu32 TR; /* Time Register */ + vu32 DTR; /* Date Register */ + vu32 ATR; /* Alarm time Register */ + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 MILR; /* Millisec Register */ +}RTC_TypeDef; + +/*------------------------------------- SSP ----------------------------------*/ + +typedef struct +{ + vu16 CR0; /* Control Register 1 */ + vu16 EMPTY1; + vu16 CR1; /* Control Register 2 */ + vu16 EMPTY2; + vu16 DR; /* Data Register */ + vu16 EMPTY3; + vu16 SR; /* Status Register */ + vu16 EMPTY4; + vu16 PR; /* Clock Prescale Register */ + vu16 EMPTY5; + vu16 IMSCR; /* Interrupt Mask Set or Clear Register */ + vu16 EMPTY6; + vu16 RISR; /* Raw Interrupt Status Register */ + vu16 EMPTY7; + vu16 MISR; /* Masked Interrupt Status Register */ + vu16 EMPTY8; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY9; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY10; +}SSP_TypeDef; + +/*------------------------------------ UART ----------------------------------*/ + +typedef struct +{ + vu16 DR; /* Data Register */ + vu16 EMPTY1; + vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */ + vu16 EMPTY2[9]; + vu16 FR; /* Flag Register */ + vu16 EMPTY3[3]; + vu16 ILPR; /* IrDA Low-Power counter Register */ + vu16 EMPTY4; + vu16 IBRD; /* Integer Baud Rate Divisor Register */ + vu16 EMPTY5; + vu16 FBRD; /* Fractional Baud Rate Divisor Register */ + vu16 EMPTY6; + vu16 LCR; /* Line Control Register, High byte */ + vu16 EMPTY7; + vu16 CR; /* Control Register */ + vu16 EMPTY8; + vu16 IFLS; /* Interrupt FIFO Level Select Register */ + vu16 EMPTY9; + vu16 IMSC; /* Interrupt Mask Set/Clear Register */ + vu16 EMPTY10; + vu16 RIS; /* Raw Interrupt Status Register */ + vu16 EMPTY11; + vu16 MIS; /* Masked Interrupt Status Register */ + vu16 EMPTY12; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY13; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY14; +}UART_TypeDef; + +/*------------------------------- Wake-up System -----------------------------*/ + +typedef struct +{ + vu32 CTRL; /* Control Register */ + vu32 MR; /* Mask Register */ + vu32 TR; /* Trigger Register */ + vu32 PR; /* Pending Register */ + vu32 INTR; /* Software Interrupt Register */ +} WIU_TypeDef; + +/*------------------------------- WatchDog Timer -----------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 PR; /* Presclar Register */ + vu16 EMPTY2; + vu16 VR; /* Pre-load Value Register */ + vu16 EMPTY3; + vu16 CNT; /* Counter Register */ + vu16 EMPTY4; + vu16 SR; /* Status Register */ + vu16 EMPTY5; + vu16 MR; /* Mask Register */ + vu16 EMPTY6; + vu16 KR; /* Key Register */ + vu16 EMPTY7; +} WDG_TypeDef; + +/******************************************************************************* +* Memory Mapping of STR91x * +*******************************************************************************/ + +#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */ +#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */ + +#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */ +#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */ + +#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */ +#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */ + +#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */ +#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */ + +#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */ +#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */ + +#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */ +#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */ + +#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */ +#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */ + +#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */ +#define AHB_FMI_B (0x44000000) /* FMI buffered Space */ + +/******************************************************************************* +* Addresses related to the VICs' peripherals * +*******************************************************************************/ + +#define VIC0_BASE (AHB_VIC0_U) +#define VIC1_BASE (AHB_VIC1_U) + +/******************************************************************************* +* Addresses related to the EMI banks * +*******************************************************************************/ + +#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */ +#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */ +#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */ +#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */ + +/******************************************************************************* +* Addresses related to the DMA peripheral * +*******************************************************************************/ + +#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */ +#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */ +#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */ +#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */ +#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */ +#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */ +#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */ +#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */ + +/******************************************************************************* +* Addresses related to the APB0 sub-system * +*******************************************************************************/ + +#define APB_WIU_OFST (0x00001000) /* Offset of WIU */ +#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */ +#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */ +#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */ +#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */ +#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */ +#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */ +#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */ +#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */ +#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */ +#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */ +#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */ +#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */ +#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */ +#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */ + +/******************************************************************************* +* Addresses related to the APB1 sub-system * +*******************************************************************************/ + +#define APB_RTC_OFST (0x00001000) /* Offset of RTC */ +#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */ +#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */ +#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */ +#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */ +#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */ +#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */ +#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */ +#define APB_CAN_OFST (0x00009000) /* Offset of CAN */ +#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */ +#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */ +#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */ +#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */ + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Unbuffered Mode ------------------------------*/ +/*----------------------------------------------------------------------------*/ + +#ifndef Buffered + +/******************************************************************************* +* AHBAPB peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_U) +#define AHBAPB1_BASE (AHB_APB_BRDG1_U) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_U) +#define ENET_DMA_BASE (AHB_ENET_DMA_U) + +/******************************************************************************* +* DMA peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_U) + +/******************************************************************************* +* EMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_U) + +/******************************************************************************* +* FMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_U) + + +#else /* Buffered */ + +/*----------------------------------------------------------------------------*/ +/*------------------------------ Buffered Mode -------------------------------*/ +/*----------------------------------------------------------------------------*/ + +/******************************************************************************* +* AHBAPB peripheral Buffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_B) +#define AHBAPB1_BASE (AHB_APB_BRDG1_B) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_B) +#define ENET_DMA_BASE (AHB_ENET_DMA_B) + +/******************************************************************************* +* DMA peripheral Buffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_B) + +/******************************************************************************* +* EMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_B) + +/******************************************************************************* +* FMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_B) + +#endif /* Buffered */ + +/******************************************************************************* +* DMA channels Base Address * +*******************************************************************************/ +#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST) +#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST) +#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST) +#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST) +#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST) +#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST) +#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST) +#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST) + +/******************************************************************************* +* EMI Banks peripheral Base Address * +*******************************************************************************/ + +#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST) +#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST) +#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST) +#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST) + +/******************************************************************************* +* APB0 Peripherals' Base addresses * +*******************************************************************************/ + +#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST) +#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST) +#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST) +#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST) +#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST) +#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST) +#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST) +#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST) +#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST) +#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST) +#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST) +#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST) +#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST) +#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST) +#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST) + +/******************************************************************************* +* APB1 Peripherals' Base addresses * +*******************************************************************************/ + +#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST) +#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST) +#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST) +#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST) +#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST) +#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST) +#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST) +#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST) +#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST) +#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST) +#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST) +#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST) +#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST) + +/******************************************************************************* +* IPs' declaration * +*******************************************************************************/ + +/*------------------------------ Non Debug Mode ------------------------------*/ +#undef DEBUG +#ifndef DEBUG + +/*********************************** AHBAPB ***********************************/ + +#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE) +#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE) + +/************************************* EMI ************************************/ + +#define EMI ((EMI_TypeDef *)EMI_BASE) + +/************************************* DMA ************************************/ + +#define DMA ((DMA_TypeDef *)DMA_BASE) +#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) +#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) +#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) +#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) +#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) +#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE) +#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE) +#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE) + +/************************************* EMI ************************************/ + +#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE) +#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE) +#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE) +#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE) + +/************************************* ENET_MAC ************************************/ + +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) + +/************************************* ENET_DMA ************************************/ + +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +/************************************* FMI ************************************/ + +#define FMI ((FMI_TypeDef *)FMI_BASE) + +/************************************* VIC ************************************/ + +#define VIC0 ((VIC_TypeDef *)VIC0_BASE) +#define VIC1 ((VIC_TypeDef *)VIC1_BASE) + +/******************************************************************************* +* APB0 Peripherals' * +*******************************************************************************/ +#define WIU ((WIU_TypeDef *)WIU_BASE) +#define TIM0 ((TIM_TypeDef *)TIM0_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) +#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) +#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) +#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE) +#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE) +#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE) +#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE) +#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE) +#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE) +#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE) +/******************************************************************************* +* APB1 Peripherals' * +*******************************************************************************/ +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define SCU ((SCU_TypeDef *)SCU_BASE) +#define MC ((MC_TypeDef *)MC_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define SSP0 ((SSP_TypeDef *)SSP0_BASE) +#define SSP1 ((SSP_TypeDef *)SSP1_BASE) +#define CAN ((CAN_TypeDef *)CAN_BASE) +#define ADC ((ADC_TypeDef *)ADC_BASE) +#define WDG ((WDG_TypeDef *)WDG_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +#else /* DEBUG */ + +/*-------------------------------- Debug Mode --------------------------------*/ + +EXT AHBAPB_TypeDef *AHBAPB0; +EXT AHBAPB_TypeDef *AHBAPB1; +EXT DMA_TypeDef *DMA; +EXT DMA_Channel_TypeDef *DMA_Channel0; +EXT DMA_Channel_TypeDef *DMA_Channel1; +EXT DMA_Channel_TypeDef *DMA_Channel2; +EXT DMA_Channel_TypeDef *DMA_Channel3; +EXT DMA_Channel_TypeDef *DMA_Channel4; +EXT DMA_Channel_TypeDef *DMA_Channel5; +EXT DMA_Channel_TypeDef *DMA_Channel6; +EXT DMA_Channel_TypeDef *DMA_Channel7; +EXT EMI_Bank_TypeDef *EMI_Bank0; +EXT EMI_Bank_TypeDef *EMI_Bank1; +EXT EMI_Bank_TypeDef *EMI_Bank2; +EXT EMI_Bank_TypeDef *EMI_Bank3; +EXT FMI_TypeDef *FMI; +EXT VIC_TypeDef *VIC0; +EXT VIC_TypeDef *VIC1; +EXT WIU_TypeDef *WIU; +EXT TIM_TypeDef *TIM0; +EXT TIM_TypeDef *TIM1; +EXT TIM_TypeDef *TIM2; +EXT TIM_TypeDef *TIM3; +EXT GPIO_TypeDef *GPIO0; +EXT GPIO_TypeDef *GPIO1; +EXT GPIO_TypeDef *GPIO2; +EXT GPIO_TypeDef *GPIO3; +EXT GPIO_TypeDef *GPIO4; +EXT GPIO_TypeDef *GPIO5; +EXT GPIO_TypeDef *GPIO6; +EXT GPIO_TypeDef *GPIO7; +EXT GPIO_TypeDef *GPIO8; +EXT GPIO_TypeDef *GPIO9; +EXT RTC_TypeDef *RTC; +EXT SCU_TypeDef *SCU; +EXT MC_TypeDef *MC; +EXT UART_TypeDef *UART0; +EXT UART_TypeDef *UART1; +EXT UART_TypeDef *UART2; +EXT SSP_TypeDef *SSP0; +EXT SSP_TypeDef *SSP1; +EXT CAN_TypeDef *CAN; +EXT ADC_TypeDef *ADC; +EXT WDG_TypeDef *WDG; +EXT I2C_TypeDef *I2C0; +EXT I2C_TypeDef *I2C1; +EXT ENET_MAC_TypeDef *ENET_MAC; +EXT ENET_DMA_TypeDef *ENET_DMA; + + +#endif /* DEBUG */ + +#endif /* __91x_MAP_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_TEST_LED/include/91x_scu.h b/uc_str912/prj_TEST_LED/include/91x_scu.h new file mode 100644 index 0000000..b9d04f5 --- /dev/null +++ b/uc_str912/prj_TEST_LED/include/91x_scu.h @@ -0,0 +1,196 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +* prototypes & definitions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_SCU_H +#define __91x_SCU_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported constants --------------------------------------------------------*/ + +/*MCLK_Source*/ +#define SCU_MCLK_PLL 0x0 +#define SCU_MCLK_RTC 0x1 +#define SCU_MCLK_OSC 0x2 + +/*RCLK_Divisor*/ +#define SCU_RCLK_Div1 0xFFFFFFE3 +#define SCU_RCLK_Div2 0x4 +#define SCU_RCLK_Div4 0x8 +#define SCU_RCLK_Div8 0xC +#define SCU_RCLK_Div16 0x10 +#define SCU_RCLK_Div1024 0x14 + +/*HCLK_Divisor*/ +#define SCU_HCLK_Div1 0xFFFFFF9F +#define SCU_HCLK_Div2 0x20 +#define SCU_HCLK_Div4 0x40 + +/*PCLK_Divisor*/ +#define SCU_PCLK_Div1 0xFFFFFE7F +#define SCU_PCLK_Div2 0x80 +#define SCU_PCLK_Div4 0x100 +#define SCU_PCLK_Div8 0x180 + +/*FMICLK_Divisor*/ +#define SCU_FMICLK_Div1 0xFFFEFFFF +#define SCU_FMICLK_Div2 0x10000 + +/*BRCLK_Divisor*/ +#define SCU_BRCLK_Div1 0xFFFFFDFF +#define SCU_BRCLK_Div2 0x200 + +/*TIMCLK_Source*/ +#define SCU_TIMCLK_EXT 0x1 +#define SCU_TIMCLK_INT 0x0 + +/*TIMx*/ +#define SCU_TIM01 0x0 +#define SCU_TIM23 0x1 + + +/*USBCLK_Source*/ +#define SCU_USBCLK_MCLK 0xFFFFF3FF +#define SCU_USBCLK_MCLK2 0x400 +#define SCU_USBCLK_EXT 0x800 + +/*SCU_EMIBCLK*/ +#define SCU_EMIBCLK_Div1 0xFFF9FFFF +#define SCU_EMIBCLK_Div2 0x20000 + +/*SCU_EMIMODE*/ +#define SCU_EMI_MUX 0xFFFFFFBF +#define SCU_EMI_DEMUX 0x40 + +/*SCU_EMIALE_LEN*/ +#define SCU_EMIALE_LEN1 0xFFFFFEFF +#define SCU_EMIALE_LEN2 0x100 + +/*SCU_EMIALE_POL*/ +#define SCU_EMIALE_POLLow 0xFFFFFF7F +#define SCU_EMIALE_POLHigh 0x80 + +/*UART_IrDA_Mode*/ +#define SCU_UARTMode_IrDA 0x1 +#define SCU_UARTMode_UART 0x0 + +/*APBPeriph*/ +#define __TIM01 0x1 +#define __TIM23 0x2 +#define __MC 0x4 +#define __UART0 0x8 +#define __UART1 0x10 +#define __UART2 0x20 +#define __I2C0 0x40 +#define __I2C1 0x80 +#define __SSP0 0x100 +#define __SSP1 0x200 +#define __CAN 0x400 +#define __ADC 0x800 +#define __WDG 0x1000 +#define __WIU 0x2000 +#define __GPIO0 0x4000 +#define __GPIO1 0x8000 +#define __GPIO2 0x10000 +#define __GPIO3 0x20000 +#define __GPIO4 0x40000 +#define __GPIO5 0x80000 +#define __GPIO6 0x100000 +#define __GPIO7 0x200000 +#define __GPIO8 0x400000 +#define __GPIO9 0x800000 +#define __RTC 0x1000000 + +/*AHBPeriph*/ +#define __FMI 0x1 +#define __FPQBC 0x2 +#define __SRAM 0x8 +#define __SRAM_ARBITER 0x10 +#define __VIC 0x20 +#define __EMI 0x40 +#define __EMI_MEM_CLK 0x80 +#define __DMA 0x100 +#define __USB 0x200 +#define __USB48M 0x400 +#define __ENET 0x800 +#define __PFQBC_AHB 0x1000 + +/*SCU_IT*/ +#define SCU_IT_LVD_RST 0x10 +#define SCU_IT_SRAM_ERROR 0x8 +#define SCU_IT_ACK_PFQBC 0x4 +#define SCU_IT_LOCK_LOST 0x2 +#define SCU_IT_LOCK 0x1 + +/*SCU_FLAG*/ +#define SCU_FLAG_SRAM_ERROR 0x20 +#define SCU_FLAG_ACK_PFQBC 0x10 +#define SCU_FLAG_LVD_RESET 0x8 +#define SCU_FLAG_WDG_RST 0x4 +#define SCU_FLAG_LOCK_LOST 0x2 +#define SCU_FLAG_LOCK 0x1 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source); +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP); +ErrorStatus SCU_PLLCmd(FunctionalState NewState); +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor); +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor); +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor); +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor); +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source); +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler); +void SCU_USBCLKConfig(u32 USBCLK_Source); +void SCU_PHYCLKConfig(FunctionalState NewState); +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor); +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK); +void SCU_EMIModeConfig(u32 SCU_EMIMODE); +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL); +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState); +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag); +void SCU_ClearFlag(u32 SCU_Flag); +u32 SCU_GetPLLFreqValue(void); +u32 SCU_GetMCLKFreqValue(void); +u32 SCU_GetRCLKFreqValue(void); +u32 SCU_GetHCLKFreqValue(void); +u32 SCU_GetPCLKFreqValue(void); +void SCU_WakeUpLineConfig(u8 EXTint); +void SCU_SpecIntRunModeConfig(FunctionalState NewState); +void SCU_EnterIdleMode(void); +void SCU_EnterSleepMode(void); +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode); +void SCU_PFQBCCmd(FunctionalState NewState); + +#endif /*__91x_SCU_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/include/91x_type.h b/uc_str912/prj_TEST_LED/include/91x_type.h new file mode 100644 index 0000000..916d81c --- /dev/null +++ b/uc_str912/prj_TEST_LED/include/91x_type.h @@ -0,0 +1,50 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_type.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : It contains common types and constants used in all the +* peripherals' drivers. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +#ifndef __91x_type_H +#define __91x_type_H + + typedef long long u64; + typedef unsigned long u32; + typedef unsigned short u16; + typedef unsigned char u8; + + typedef signed long s32; + typedef signed short s16; + typedef signed char s8; + + typedef volatile unsigned long vu32; + typedef volatile unsigned short vu16; + typedef volatile unsigned char vu8; + + typedef volatile signed long vs32; + typedef volatile signed short vs16; + typedef volatile signed char vs8; + +typedef enum { FALSE = 0, TRUE = !FALSE } bool; + +typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; + +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#endif /* __91x_type_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/led.c b/uc_str912/prj_TEST_LED/led.c new file mode 100644 index 0000000..c46fd85 --- /dev/null +++ b/uc_str912/prj_TEST_LED/led.c @@ -0,0 +1,122 @@ +/****************************************************************************** + * www.propox.com + * MMstr912 - Minimodu³ Ethernetowy z procesorem ARM9 STR912. + * Ethernet minimodule with ARM9 STR912 microcontroller. + * + * LED Test - efekt swietlny na diodach led + * light effect on LEDs + * + * Do GPIO8 podlaczyc diody (Connect LEDs o GPIO8) + + * Includes ------------------------------------------------------------------*/ +/* Pliki nag³ówkowe ----------------------------------------------------------*/ +/* Library includes. */ +#include "91x_lib.h" +#include "91x_gpio.h" +#include "91x_map.h" +#include "91x_scu.h" + +//#include rem Bla + + +/* Port 8 Configuration */ +/* Konfiguracja protu 8 */ +void HardwareConf(void) +{ + //Disable reset for GPIO8 + //wylaczenie resetu na GPIO8 + SCU_APBPeriphReset(__GPIO8, DISABLE); + //Enable clock for GPIO8 + //W³¹czenie zegara na GPIO8 + SCU_APBPeriphClockConfig(__GPIO8, ENABLE); +} + + +/* Port 8 Configuration */ +/* Konfiguracja protu 8 */ +void LED_DataLinesConfig() +{ + /* Private typedef */ + /* Deklaracja struktury */ + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; + /* Configure D0~D7 lines in Output Push-Pull mode */ + /* Konfiguracja lini portu 8 jako wyjsc w trybie push-pull */ + GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt1; + GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput; + GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull; + + GPIO_Init(GPIO8, &GPIO_InitStructure); +} + + +/* Delay */ +/* Opoznienie */ +void delay(int time) +{ + while(time--) + asm volatile ("nop"); +} + +/******************** LEDs Functions **************************/ +/**************************************************************/ +/* LED Flashing */ +/* Miganie diody LED */ +void LEDflashing(int GPIO_Pin_x) +{ + /* Reset pin P8.x */ + GPIO_WriteBit(GPIO8, GPIO_Pin_x, Bit_RESET); + delay(200000); + /* Set pin P8.x */ + GPIO_WriteBit(GPIO8, GPIO_Pin_x, Bit_SET); + delay(200000); +} +/* LED on */ +/* zapalenie diody LED */ +void LEDon(int GPIO_Pin_x) +{ + /* Reset pin P8.x */ + GPIO_WriteBit(GPIO8, GPIO_Pin_x, Bit_RESET); +} +/* LED off */ +/* zgaszenie diody LED */ +void LEDoff(int GPIO_Pin_x) +{ + /* Set pin P8.x */ + GPIO_WriteBit(GPIO8, GPIO_Pin_x, Bit_SET); +} +/**************************************************************/ + + +int main() +{ +//Hardware Configuration +//Konfiguracja sprzetu +HardwareConf(); +//Port Configuration +//Konfiguracja portu +LED_DataLinesConfig(); + +while(1) +{ + LEDflashing(GPIO_Pin_0); + delay(5000); + LEDflashing(GPIO_Pin_1); + delay(5000); + LEDflashing(GPIO_Pin_2); + delay(5000); + LEDflashing(GPIO_Pin_3); + delay(5000); + LEDflashing(GPIO_Pin_4); + delay(5000); + LEDflashing(GPIO_Pin_5); + delay(5000); + LEDflashing(GPIO_Pin_6); + delay(5000); + LEDflashing(GPIO_Pin_7); + delay(5000); +} + +return 0; +} diff --git a/uc_str912/prj_TEST_LED/load_segger.gdb b/uc_str912/prj_TEST_LED/load_segger.gdb new file mode 100644 index 0000000..dc1736e --- /dev/null +++ b/uc_str912/prj_TEST_LED/load_segger.gdb @@ -0,0 +1,20 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:2331 + +monitor speed adaptive +monitor endian little + +monitor reset +monitor flash device = STR912FAW44 +monitor flash breakpoints = 1 +monitor flash download = 1 +monitor halt + + +pwd +load led.elf +file led.elf diff --git a/uc_str912/prj_TEST_LED/startup.s b/uc_str912/prj_TEST_LED/startup.s new file mode 100644 index 0000000..cef54d8 --- /dev/null +++ b/uc_str912/prj_TEST_LED/startup.s @@ -0,0 +1,233 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/**** Startup Code (executed after Reset) ****/ + +/* Frequency values kHz */ +/* set to suit target hardware */ + + .equ FOSC, 25000 + +/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */ + + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + .equ SRAM32, 0x00 + .equ SRAM64, 0x08 + .equ SRAM96, 0x10 + +/* --- System memory locations */ + + .equ SCRO_AHB_UMB, 0x5C002034 /* System configuration register 0 (unbuffered) */ + + .equ FMI_BASE_UMB, 0x54000000 /* Flash FMI base address (unbuffered) */ + .equ BBSR_off_addr, 0x00 + .equ NBBSR_off_addr, 0x04 + .equ BBADR_off_addr, 0x0C + .equ NBBADR_off_addr, 0x10 + .equ CR_off_addr, 0x18 + +.ifndef LIBUFF + .equ LIBUFF, 0 +.endif + +/* Startup Code must be linked first at Address at which it expects to run. */ + + .text + .arm + .section .init, "ax" + + .global _start + .global _Main_Crystal + +/* After remap this will be our reset handler */ + +_start: + LDR pc, =NextInst +NextInst: + + NOP /* Wait for OSC stabilization */ + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +/* Enable buffered mode */ + +.if LIBUFF + MRC p15, 0, r0, c1, c0, 0 /* Read CP15 register 1 into r0 */ + ORR r0, r0, #0x8 /* Enable Write Buffer on AHB */ + MCR p15, 0, r0, c1, c0, 0 /* Write CP15 register 1 */ +.endif + +/* Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, */ +/* when the bank 0 is the boot bank, then enable the Bank 1. */ + + LDR r0, =FMI_BASE_UMB + LDR r1, =0x4 /* configure 512KB Boot bank 0 */ + STR r1, [r0, #BBSR_off_addr] + + LDR r1, =0x2 /* configure 32KB Non Boot bank 1 */ + STR r1, [r0, #NBBSR_off_addr] + + LDR r1, =(0x00000000 >> 2) /* Boot Bank Base Address */ + STR r1, [r0, #BBADR_off_addr] + + LDR r1, =(0x00080000 >> 2) /* Non Boot Bank Base Address */ + STR r1, [r0, #NBBADR_off_addr] + + LDR r1, =0x18 /* Flash Banks 0 1 enabled */ + STR r1, [r0, #CR_off_addr] + +/* Enable 96K RAM */ + + LDR r0, =SCRO_AHB_UMB +# LDR r1, =0x0196 /* prefetch disabled, default enabled */ + LDR r1, =0x0187|SRAM96 + STR r1, [r0] + +/* Set bits 17-18 (Instruction/Data TCM order) of the */ +/* Core Configuration Control Register */ + + MOV r0, #0x60000 + MCR p15, 0x1, r0, c15, c1, 0 + +/* Setup Stack for each mode */ + +/* Enter Abort Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_ABT|I_Bit|F_Bit + LDR sp, =__stack_abt_end__ + +/* Enter Undefined Instruction Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_UND|I_Bit|F_Bit + LDR sp, =__stack_und_end__ + +/* Enter Supervisor Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SVC|I_Bit|F_Bit + LDR sp, =__stack_svc_end__ + +/* Enter FIQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_FIQ|I_Bit|F_Bit + LDR sp, =__stack_fiq_end__ + +/* Enter IRQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit + LDR sp, =__stack_irq_end__ + +/* Enter System/User Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SYS + LDR sp, =__stack_end__ + +/* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */ + + LDR sl, =__bss_end__ + +/* Relocate .data section (Copy from ROM to RAM) */ + + LDR r1, =_etext + LDR r2, =__data_start + LDR r3, =_edata +LoopRel: + CMP r2, r3 + LDRLO r0, [r1], #4 + STRLO r0, [r2], #4 + BLO LoopRel + +/* Clear .bss section (Zero init) */ + + MOV r0, #0 + LDR r1, =__bss_start__ + LDR r2, =__bss_end__ +LoopZI: + CMP r1, r2 + STRLO r0, [r1], #4 + BLO LoopZI + +/* Call C++ constructors */ + + LDR r0, =__ctors_start__ + LDR r1, =__ctors_end__ +ctor_loop: + CMP r0, r1 + BEQ ctor_end + LDR r2, [r0], #4 + STMFD sp!, {r0-r1} + BLX r2 + LDMFD sp!, {r0-r1} + B ctor_loop +ctor_end: + +/* Need to set up standard file handles */ +/* Only used under simulator, normally overide syscall.c */ + +# BL initialise_monitor_handles + +/* if we use debug version of str9lib this will call the init function */ + + BL libdebug +libdebug: + +/* Enter the C code, use B instruction so as to never return */ +/* use BL main if you want to use c++ destructors below */ + + B main + +/* Call destructors */ + +# LDR r0, =__dtors_start__ +# LDR r1, =__dtors_end__ +#dtor_loop: +# CMP r0, r1 +# BEQ dtor_end +# LDR r2, [r0], #4 +# STMFD sp!, {r0-r1} +# BLX r2 +# LDMFD sp!, {r0-r1} +# B dtor_loop +#dtor_end: + +/* Return from main, loop forever. */ + +#exit_loop: +# B exit_loop + +/* Fosc values, used by libstr9 */ + +_Main_Crystal: .long FOSC + + .weak libdebug + + .end diff --git a/uc_str912/prj_TEST_LED/str91x_lib/91x_ahbapb.c b/uc_str912/prj_TEST_LED/str91x_lib/91x_ahbapb.c new file mode 100644 index 0000000..41489ac --- /dev/null +++ b/uc_str912/prj_TEST_LED/str91x_lib/91x_ahbapb.c @@ -0,0 +1,177 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the AHBAPB software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_ahbapb.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#define AHBAPB_SplitCounter_Mask 0xFFE0FFFF +#define AHBAPB_SetTimeOut_Mask 0xFFFFFFE0 +#define AHBAPB_Address_Mask 0xFEFFFFFF +#define AHBAPB_FLAG_RW_Mask 0x01000000 +/******************************************************************************* +* Function Name : AHBAPB_DeInit +* Description : Deinitializes the AHBAPBx peripheral registers to their default +* reset values. +* Input : AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx) +{ + AHBAPBx->BCR = 0x00000000; + AHBAPBx->BSR = 0x00000000; +} +/******************************************************************************* +* Function Name : AHBAPB_Init +* Description : Initializes the AHBAPBx peripheral according to the specified +* parameters in the AHBAPB_InitStruct . +* Input :- AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* - AHBAPB_InitStruct: pointer to a AHBAPB_InitTypeDef structure that +* contains the configuration information for the specified AHBAPB +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + + if(AHBAPB_InitStruct->AHBAPB_Split == AHBAPB_Split_Enable) + { + /* Set SPLITEN bit;*/ + AHBAPBx->BCR |= AHBAPB_Split_Enable; + /*Split_CNT bits[20:16]*/ + AHBAPBx->BCR &= AHBAPB_SplitCounter_Mask; + AHBAPBx->BCR |= (AHBAPB_InitStruct->AHBAPB_SplitCounter)<<16; + } + else + { + /*/ Clear SPLITEN bit;*/ + AHBAPBx->BCR &= AHBAPB_Split_Disable; + } + /*APB Time out*/ + if(AHBAPB_InitStruct->AHBAPB_Error == AHBAPB_Error_Enable) + { + /* Set ERREN bit*/ + AHBAPBx->BCR |= AHBAPB_Error_Enable; + /*Time ouit counter*/ + AHBAPBx->BCR &= AHBAPB_SetTimeOut_Mask; + AHBAPBx->BCR |= AHBAPB_InitStruct->AHBAPB_SetTimeOut; + } + else + { + /* Clear ERREN bit*/ + AHBAPBx->BCR &= AHBAPB_Error_Disable; + } +} + +/******************************************************************************* +* Function Name : AHBAPB_StructInit +* Description : Initialize the AHBAPB Init Structure parameters +* Input : AHBAPB_InitStruct : pointer to a AHBAPB_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + /* Reset AHBAPB init structure parameters values */ + AHBAPB_InitStruct->AHBAPB_Split = AHBAPB_Split_Enable; + AHBAPB_InitStruct->AHBAPB_SplitCounter = 0xFF; + AHBAPB_InitStruct->AHBAPB_Error = AHBAPB_Error_Enable; + AHBAPB_InitStruct->AHBAPB_SetTimeOut = 0xFF; + +} + +/******************************************************************************* +* Function Name : AHBAPB_GetFlagStatus +* Description : Checks whether the specified AHBAPB flag is set or not. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* - AHBAPB_FLAG_RW : Access type flag +* Output : None +* Return : The new state of AHBAPB_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + if(AHBAPB_FLAG == AHBAPB_FLAG_RW) + { + if ((AHBAPBx->PAER & AHBAPB_FLAG_RW_Mask) == RESET) + { + return RESET; + } + else + { + return SET; + } + } + else + { + if ((AHBAPBx->BSR & AHBAPB_FLAG) == RESET) + { + return RESET; + } + else + { + return SET; + } + } +} +/******************************************************************************* +* Function Name : AHBAPB_ClearFlag +* Description : Clears the AHBAPBx flags. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: flags to clear. This parameter one of the +* following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + /* Clear the flag */ + AHBAPBx->BSR &= AHBAPB_FLAG; +} +/******************************************************************************* +* Function Name : AHBAPB_GetPeriphAddrError +* Description : Gets the AHBAPB error address peripherals. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* Output : None +* Return : The Peropheral address error +*******************************************************************************/ +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx) +{ + u32 AHBAPB_Address = 0x00000000; + + /*Return Oeripheral address without RW bit*/ + AHBAPB_Address = (AHBAPBx->PAER)& AHBAPB_Address_Mask; + return (AHBAPB_Address); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/str91x_lib/91x_fmi.c b/uc_str912/prj_TEST_LED/str91x_lib/91x_fmi.c new file mode 100644 index 0000000..fb558ad --- /dev/null +++ b/uc_str912/prj_TEST_LED/str91x_lib/91x_fmi.c @@ -0,0 +1,519 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the FMI software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_fmi.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define TIMEOUT 0xFFFFFF /* Timeout value */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/******************************************************************************* +* Function Name : FMI_BankRemapConfig +* Description : Configure the addresses and sizes of bank 0 and bank 1. +* Input1 : FMI_BootBankSize: specifies the boot bank size. +* This parameter can be one of the following values: +* - 0x0: 32KBytes. +* - 0x1: 64KBytes. +* - 0x2: 128KBytes. +* - 0x3: 256KBytes. +* - 0x4: 512KBytes. +* .... +* - 0xB: 64MBytes. +* Input2 : FMI_NonBootBankSize: specifies the non boot bank size. +* This parameter can be one of the following values: +* - 0x0: 8KBytes. +* - 0x1: 16KBytes. +* - 0x2: 32KBytes. +* - 0x3: 64KBytes. +* .... +* - 0xD: 64MBytes. +* Input3 : FMI_BootBankAddress: specifies the address of the boot bank. +* Input4 : FMI_NonBootBankAddress: specifies the address of the non +* boot bank. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress) +{ + FMI->BBSR = FMI_BootBankSize; + FMI->NBBSR = FMI_NonBootBankSize; + FMI->BBADR = (FMI_BootBankAddress >> 2); + FMI->NBBADR = (FMI_NonBootBankAddress >> 2); + FMI->CR |= 0x18; /* Enable bank 1 */ +} + +/******************************************************************************* +* Function Name : FMI_Config +* Description : Configure the FMI. +* Input1 : FMI_ReadWaitState: specifies the needed read wait states. +* This parameter can be one of the following values: +* - FMI_READ_WAIT_STATE_1: One read wait state. +* - FMI_READ_WAIT_STATE_2: Two read wait states. +* - FMI_READ_WAIT_STATE_3: Three read wait states. +* Input2 : FMI_WriteWaitState: specifies the needed write wait states. +* This parameter can be one of the following values: +* - FMI_WRITE_WAIT_STATE_1: One write wait state. +* - FMI_WRITE_WAIT_STATE_2: Two write wait states. +* Input3 : FMI_PWD: specifies the power down mode status. +* This parameter can be one of the following values: +* - FMI_PWD_ENABLE: Enable the PWD. +* - FMI_PWD_DISABLE: Disable the PWD. +* Input4 : FMI_LVDEN: specifies the low voltage detector status. +* This parameter can be one of the following values: +* - FMI_LVD_ENABLE: Enable the LVD. +* - FMI_LVD_DISABLE: Disable the LVD. +* Input5 : FMI_FreqRange: specifies the working frequency range. +* This parameter can be one of the following values: +* - FMI_FREQ_LOW: Low working frequency (up to 66MHz). +* - FMI_FREQ_HIGH: High working frequency (above 66MHz) . +* Output : None +* Return : None +*******************************************************************************/ +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange) +{ + /* Configure the write wait state value */ + if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1) + { + FMI->CR |= FMI_WRITE_WAIT_STATE_1; + } + else + { + FMI->CR &= FMI_WRITE_WAIT_STATE_0; + } + + /* Write a write flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x60; + + /* Configure the flash configuration register */ + *(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03; +} + +/******************************************************************************* +* Function Name : FMI_EraseSector +* Description : Erase the needed sector. +* Input : FMI_Sector: specifies the sector to be erased. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseSector(vu32 FMI_Sector) +{ + /* Write an erase set-up command to the sector */ + *(vu16 *)FMI_Sector = 0x20; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Sector = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_EraseBank +* Description : Erase the needed bank. +* Input : FMI_Bank: specifies the bank to be erased. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseBank(vu32 FMI_Bank) +{ + /* Write a bank erase set-up command to the bank */ + *(vu16 *)FMI_Bank = 0x80; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_WriteHalfWord +* Description : Write a halfword to the needed Flash memory address. +* Input 1 : FMI_Address: specifies the address offset where the data will +* be written. +* Input 2 : FMI_Data: the needed data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data) +{ + /* Write a program command to the sector to be written */ + *(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40; + + /* Write the halfword to the destination address */ + *(vu16 *)FMI_Address = FMI_Data; +} + +/******************************************************************************* +* Function Name : FMI_WriteOTPHalfWord +* Description : Write a halfword to the needed OTP sector address. +* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset +* where the data will be written. +* This parameter can be one of the following values: +* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0. +* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0. +* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1. +* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1. +* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2. +* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2. +* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3. +* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3. +* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4. +* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4. +* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5. +* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5. +* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6. +* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6. +* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7. +* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7. +* Input 2 : FMI_OTPData: The needed OTP data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData) +{ + /* Write a write OTP command to the needed address */ + *(vu16 *)(FMI_BANK_1) = 0xC0; + + /* Write the halfword to the destination address */ + *(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData; +} + +/******************************************************************************* +* Function Name : FMI_ReadWord +* Description : Read the correspondent data. +* Input : FMI_Address: specifies the needed address. +* Output : None +* Return : The data contained in the specified address. +*******************************************************************************/ +u32 FMI_ReadWord(u32 FMI_Address) +{ + return(*(u32*)FMI_Address); +} + +/******************************************************************************* +* Function Name : FMI_ReadOTPData +* Description : Read data from the OTP sector. +* Input : FMI_OTPAddress: specifies the address of the data to be read. +* This parameter can be one of the following values: +* - FMI_OTP_WORD_0: FMI bank 0 sector 0. +* - FMI_OTP_WORD_1: FMI bank 0 sector 1. +* - FMI_OTP_WORD_2: FMI bank 0 sector 2. +* - FMI_OTP_WORD_3: FMI bank 0 sector 3. +* - FMI_OTP_WORD_4: FMI bank 0 sector 4. +* - FMI_OTP_WORD_5: FMI bank 0 sector 5. +* - FMI_OTP_WORD_6: FMI bank 0 sector 6. +* - FMI_OTP_WORD_7: FMI bank 0 sector 7. +* Output : None +* Return : The needed OTP words. +*******************************************************************************/ +u32 FMI_ReadOTPData(u8 FMI_OTPAddress) +{ + u32 OTP_Data = 0x0; + /* write a read OTP sector command */ + *(vu16 *)(FMI_BANK_1) = 0x98; + + /* Read the correspondent data */ + OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress)); + + /* Write a read array command */ + *(vu16 *)(FMI_BANK_1) = 0xFF; + + return OTP_Data; +} + +/******************************************************************************* +* Function Name : FMI_GetFlagStatus +* Description : Check whether the specified FMI flag is set or not. +* Input1 : FMI_Flag: flag to check. +* This parameter can be one of the following values: +* - FMI_FLAG_SPS: Sector Protection Status Flag. +* - FMI_FLAG_PSS: Program Suspend Status Flag. +* - FMI_FLAG_PS: Program Status Flag. +* - FMI_FLAG_ES: Erase Status Flag. +* - FMI_FLAG_ESS: Erase Suspend Status Flag. +* - FMI_FLAG_PECS: FPEC Status Flag. +* Input2 : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank) +{ + u16 FMI_Status_Register = 0; + + /* Write a read status register command */ + *(vu16 *)FMI_Bank = 0x70; + + /* Wait until operation completion */ + while(!((*(vu16 *)FMI_Bank) & 0x80)); + + /* Read the status register */ + FMI_Status_Register = *(vu16 *)FMI_Bank; + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if((FMI_Status_Register & FMI_Flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_GetReadWaitStateValue +* Description : Get the current Read wait state value. +* Input : None +* Output : None +* Return : The current read wait states value. +*******************************************************************************/ +u16 FMI_GetReadWaitStateValue(void) +{ + u16 FMI_Configuration_Register = 0; + /* Write a read flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash configuration register */ + FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3; + + /* Return the wait states value */ + return FMI_Configuration_Register; +} + +/******************************************************************************* +* Function Name : FMI_GetWriteWaitStateValue +* Description : Get the current write wait state value. +* Input : None +* Output : None +* Return : The current write wait states value. +*******************************************************************************/ +u16 FMI_GetWriteWaitStateValue(void) +{ + return ((u16)((FMI->CR & 0x100) >> 8)); +} + +/******************************************************************************* +* Function Name : FMI_SuspendEnable +* Description : Suspend command enable. +* Input : FMI_Bank: specifies the bank to be suspended. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_SuspendEnable(vu32 FMI_Bank) +{ + /* Write a suspend command to the bank */ + *(vu16 *)FMI_Bank = 0xB0; +} + +/******************************************************************************* +* Function Name : FMI_ResumeEnable +* Description : Resume the suspended command. +* Input : FMI_Bank: specifies the suspended bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ResumeEnable(vu32 FMI_Bank) +{ + /* Write a resume command to the bank */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_ClearFlag +* Description : Clear the FMI Flags on the correspondent bank. +* Input : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ClearFlag(vu32 FMI_Bank) +{ + /* Write a clear status register command */ + *(vu16 *)FMI_Bank = 0x50; +} + +/******************************************************************************* +* Function Name : FMI_WriteProtectionCmd +* Description : Enable or disable the write protection for the needed sector. +* Input1 : FMI_Sector: specifies the sector to be protected or +* unprotected. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Input2 : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: Enable the protection. +* - DISABLE: Disable the protection. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState) +{ + if (FMI_NewState == ENABLE) + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0x01; + *(vu16*)FMI_Sector = 0xFF; + } + else /* DISABLE */ + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0xD0; + *(vu16*)FMI_Sector = 0xFF; + } +} + +/******************************************************************************* +* Function Name : FMI_GetWriteProtectionStatus +* Description : Get the write protection status for the needed sector. +* Input : FMI_Sector_Mask: specifies the needed sector mask. +* This parameter can be one of the following values: +* - FMI_B0S0_MASK: FMI bank 0 sector 0. +* - FMI_B0S1_MASK: FMI bank 0 sector 1. +* - FMI_B0S2_MASK: FMI bank 0 sector 2. +* - FMI_B0S3_MASK: FMI bank 0 sector 3. +* - FMI_B0S4_MASK: FMI bank 0 sector 4. +* - FMI_B0S5_MASK: FMI bank 0 sector 5. +* - FMI_B0S6_MASK: FMI bank 0 sector 6. +* - FMI_B0S7_MASK: FMI bank 0 sector 7. +* - FMI_B1S0_MASK: FMI bank 1 sector 0. +* - FMI_B1S1_MASK: FMI bank 1 sector 1. +* - FMI_B1S2_MASK: FMI bank 1 sector 2. +* - FMI_B1S3_MASK: FMI bank 1 sector 3. +* Output : None +* Return : The Protection Status of the needed sector. +* - RESET: The needed sector is not write protected. +* - SET : The needed sector is write protected. +*******************************************************************************/ +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask) +{ + u16 Protection_Level_1_Register = 0; + /* Write a read flash protection level 1 register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash protection level 1 register */ + Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + if (Protection_Level_1_Register &= FMI_Sector_Mask) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_WaitForLastOperation +* Description : Wait until the last operation (Write halfword, Write OTP +* halfword, Erase sector and Erase bank) completion. +* Input : FMI_Bank: specifies the bank where the operation is on going. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : The timeout status. +* This parameter can be one of the following values: +* - FMI_TIME_OUT_ERROR: Timeout error occurred. +* - FMI_NO_TIME_OUT_ERROR: No timeout error. +*******************************************************************************/ +u8 FMI_WaitForLastOperation(vu32 FMI_Bank) +{ + u32 Time_Out = 0; + + /* Write a read status register command */ + *(vu16 *)(FMI_Bank) = 0x70; + + /* Wait until operation compeletion */ + while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT )) + { + Time_Out ++; /* Time Out */ + } + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if (Time_Out == TIMEOUT) + { + return FMI_TIME_OUT_ERROR; + } + else + { + return FMI_NO_TIME_OUT_ERROR; + } +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/str91x_lib/91x_gpio.c b/uc_str912/prj_TEST_LED/str91x_lib/91x_gpio.c new file mode 100644 index 0000000..f2d0941 --- /dev/null +++ b/uc_str912/prj_TEST_LED/str91x_lib/91x_gpio.c @@ -0,0 +1,407 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the GPIO software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_gpio.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + + /* Reset the GPIO registers values */ + if(GPIOx == GPIO0) + { + SCU_APBPeriphReset(__GPIO0,ENABLE); + SCU_APBPeriphReset(__GPIO0,DISABLE); + SCU->GPIOTYPE[0x00] = 0x0000 ; + SCU->GPIOOUT[0x00] = 0x0000; + SCU->GPIOIN[0x00] = 0x0000; + } + + if(GPIOx == GPIO1) + { + SCU_APBPeriphReset(__GPIO1,ENABLE); + SCU_APBPeriphReset(__GPIO1,DISABLE); + SCU->GPIOTYPE[0x01] = 0x0000 ; + SCU->GPIOOUT[0x01] = 0x0000; + SCU->GPIOIN[0x01] = 0x0000; + } + + if(GPIOx == GPIO2) + { + SCU_APBPeriphReset(__GPIO2,ENABLE); + SCU_APBPeriphReset(__GPIO2,DISABLE); + SCU->GPIOTYPE[0x02] = 0x0000 ; + SCU->GPIOOUT[0x02] = 0x0000; + SCU->GPIOIN[0x02] = 0x0000; + } + + if(GPIOx == GPIO3) + { + SCU_APBPeriphReset(__GPIO3,ENABLE); + SCU_APBPeriphReset(__GPIO3,DISABLE); + SCU->GPIOTYPE[0x03] = 0x0000 ; + SCU->GPIOOUT[0x03] = 0x0000; + SCU->GPIOIN[0x03] = 0x0000; + } + + if(GPIOx == GPIO4) + { + SCU_APBPeriphReset(__GPIO4,ENABLE); + SCU_APBPeriphReset(__GPIO4,DISABLE); + SCU->GPIOTYPE[0x04] = 0x0000 ; + SCU->GPIOOUT[0x04] = 0x0000; + SCU->GPIOIN[0x04] = 0x0000; + SCU->GPIOANA = 0x00; + } + + if(GPIOx == GPIO5) + { + SCU_APBPeriphReset(__GPIO5,ENABLE); + SCU_APBPeriphReset(__GPIO5,DISABLE); + SCU->GPIOTYPE[0x05] = 0x0000 ; + SCU->GPIOOUT[0x05] = 0x0000; + SCU->GPIOIN[0x05] = 0x0000; + } + + if(GPIOx == GPIO6) + { + SCU_APBPeriphReset(__GPIO6,ENABLE); + SCU_APBPeriphReset(__GPIO6,DISABLE); + SCU->GPIOTYPE[0x06] = 0x0000 ; + SCU->GPIOOUT[0x06] = 0x0000; + SCU->GPIOIN[0x06] = 0x0000; + } + + if(GPIOx == GPIO7) + { + SCU_APBPeriphReset(__GPIO7,ENABLE); + SCU_APBPeriphReset(__GPIO7,DISABLE); + SCU->GPIOOUT[0x07] = 0xAAAA; + SCU->GPIOOUT[0x07] = 0x0000; + SCU->GPIOIN[0x07] = 0x0000; + } + + if(GPIOx == GPIO8) + { + SCU_APBPeriphReset(__GPIO8,ENABLE); + SCU_APBPeriphReset(__GPIO8,DISABLE); + SCU->GPIOEMI = 0x00; + } + + if(GPIOx == GPIO9) + { + SCU_APBPeriphReset(__GPIO9,ENABLE); + SCU_APBPeriphReset(__GPIO9,DISABLE); + SCU->GPIOEMI = 0x00; + } +} +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct . +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Select pin direction */ + u8 PinNumber = 0; + u8 Counter = 0; + u8 GPIO_Number = 0; + + GPIO_Number = GPIO_GetGPIONumber(GPIOx); + + + if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput) + { + GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin; + } + else + { + GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin; + } + + for (Counter = 0; Counter < 8;Counter++) + { + /*Search pin number*/ + PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <> Counter) == 1) + { + /*Output ALternate 0*/ + SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2)); + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1) + { + /*Output ALternate 1*/ + SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2) + { + /*Output ALternate 2*/ + SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3) + { + /*Output ALternate 3*/ + SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2); + } + + /*Type configuration: PushPull or Open Collector*/ + SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector) + { + /*Open Drain configuration*/ + SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter; + } + + /*IP Connected disable*/ + SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable) + { + /*IP Connected enable*/ + SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter; + } + } + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Initialize the GPIO Init Structure parameters +* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Direction = GPIO_PinInput; + GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull; + GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable; + GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1; +} + +/******************************************************************************* +* Function Name : GPIO_ReadBit +* Description : Reads the specified port pin +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* Output : None +* Return : The port pin value +*******************************************************************************/ +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin) +{ + if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET ) + { + return Bit_SET; + } + else + { + return Bit_RESET; + } +} + +/******************************************************************************* +* Function Name : GPIO_Read +* Description : Reads the specified GPIO data port +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO data port word value. +*******************************************************************************/ +u8 GPIO_Read(GPIO_TypeDef* GPIOx) +{ + return (GPIOx->DR[0x3FC]); +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* - BitVal: this parameter specifies the value to be written +* to the selected bit. +* BitVal must be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal) +{ + if(BitVal == Bit_SET) + { + GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin; + } + else + { + GPIOx->DR[GPIO_Pin <<2] = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes the passed value in the selected data GPIOx port +* register. +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - PortVal: the value to be written to the data port register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal) +{ + GPIOx->DR[0x3FC] = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_EMIConfig +* Description : Enables or disables GPIO 8 and 9 in EMI mode. +* Input : - NewState: new state of the EMI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EMIConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SCU->GPIOEMI = 0x01; + } + else + { + SCU->GPIOEMI = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_ANAPinConfig +* Description : Enables or disables pins from GPIO 4 in Analogue mode. +* Input :- GPIO_ANAChannel: selects the ADC channel pin. +* This parameter can be one of the following values: +* GPIO_ANAChannel0 +* GPIO_ANAChannel1 +* GPIO_ANAChannel2 +* GPIO_ANAChannel3 +* GPIO_ANAChannel4 +* GPIO_ANAChannel5 +* GPIO_ANAChannel6 +* GPIO_ANAChannel7 +* GPIO_ANAChannelALL +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState) +{ + + if(NewState == ENABLE) + { + if(GPIO_ANAChannel == GPIO_ANAChannelALL) + { + SCU->GPIOOUT[4] = 0x0000; + SCU->GPIOIN[4] = 0x00; + } + else + { + SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1)); + SCU->GPIOIN[4] &= ~GPIO_ANAChannel; + } + SCU->GPIOANA |= GPIO_ANAChannel; + + } + else + { + SCU->GPIOANA &= ~GPIO_ANAChannel; + } +} + +/******************************************************************************* +* Function Name : GPIO_GetGPIONumber +* Description : searche the GPIO number. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO number +*******************************************************************************/ +u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx) +{ + + if(GPIOx == GPIO1) + { + return 1; + } + if(GPIOx == GPIO2) + { + return 2; + } + if(GPIOx == GPIO3) + { + return 3; + } + if(GPIOx == GPIO4) + { + return 4; + } + if(GPIOx == GPIO5) + { + return 5; + } + if(GPIOx == GPIO6) + { + return 6; + } + if(GPIOx == GPIO7) + { + return 7; + } + if(GPIOx == GPIO8) + { + return 8; + } + if(GPIOx == GPIO9) + { + return 9; + } + return 0; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/str91x_lib/91x_lib.c b/uc_str912/prj_TEST_LED/str91x_lib/91x_lib.c new file mode 100644 index 0000000..c0eadbb --- /dev/null +++ b/uc_str912/prj_TEST_LED/str91x_lib/91x_lib.c @@ -0,0 +1,281 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all peripherals pointers + : initialization. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#define EXT + +/* Standard include ----------------------------------------------------------*/ +#include "91x_map.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#ifdef DEBUG + +/******************************************************************************* +* Function Name : debug +* Description : this function initialize peripherals pointers +* Input : no one +* Output : no one +* Return : no one +*******************************************************************************/ +void debug(void) +{ + + +/************************* DMA *************************/ + +#ifdef _DMA + DMA = (DMA_TypeDef *)DMA_BASE; +#endif /* _DMA */ + +/************************* DMA *************************/ + + +#ifdef _DMA_Channel0 + DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE; +#endif /* _DMA_Channel0 */ + +#ifdef _DMA_Channel1 + DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE; +#endif /* _DMA_Channel1 */ + +#ifdef _DMA_Channel2 + DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE; +#endif /* _DMA_Channel2 */ + +#ifdef _DMA_Channel3 + DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE; +#endif /* _DMA_Channel3 */ + +#ifdef _DMA_Channel4 + DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE; +#endif /* _DMA_Channel4 */ + +#ifdef _DMA_Channel5 + DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE; +#endif /* _DMA_Channel5*/ + + +#ifdef _DMA_Channel6 + DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE; +#endif /* _DMA_Channel6 */ + +#ifdef _DMA_Channel7 + DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE; +#endif /* _DMA_Channel7 */ + + + + /************************* EMI *************************/ + +#ifdef _EMI_Bank0 + EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE; +#endif /* _EMI_Bank0 */ + +#ifdef _EMI_Bank1 + EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE; +#endif /* _EMI_Bank1 */ + +#ifdef _EMI_Bank2 + EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE; +#endif /* _EMI_Bank2 */ + +#ifdef _EMI_Bank3 + EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE; + #endif /* _EMI_Bank3 */ + + + +/************************* AHBAPB *************************/ + +#ifdef _AHBAPB0 + AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE; +#endif /* _AHBAPB0 */ + +#ifdef _AHBAPB1 + AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE; +#endif /*_AHBAPB1 */ + + + +/************************* FMI *************************/ + +#ifdef _FMI + FMI = (FMI_TypeDef *)FMI_BASE; +#endif /* _FMI */ + +/************************* VIC *************************/ + +#ifdef _VIC0 + VIC0 = (VIC_TypeDef *)VIC0_BASE; +#endif /* _VIC0 */ + +#ifdef _VIC1 + VIC1 = (VIC_TypeDef *)VIC1_BASE; +#endif /* _VIC1 */ + +/************************* WIU *************************/ + +#ifdef _WIU + WIU = (WIU_TypeDef *)WIU_BASE; +#endif /* _WIU */ + +/************************* TIM *************************/ + +#ifdef _TIM0 + TIM0 = (TIM_TypeDef *)TIM0_BASE; +#endif /* _TIM0 */ + +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *)TIM1_BASE; +#endif /* _TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *)TIM2_BASE; +#endif /* _TIM2 */ + +#ifdef _TIM3 + TIM3 = (TIM_TypeDef *)TIM3_BASE; +#endif /* _TIM3 */ + +/************************* GPIO ************************/ + +#ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; +#endif /* _GPIO0 */ + +#ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; +#endif /* _GPIO1 */ + +#ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; +#endif /* _GPIO2 */ + +#ifdef _GPIO3 + GPIO3 = (GPIO_TypeDef *)GPIO3_BASE; +#endif /* _GPIO3 */ + +#ifdef _GPIO4 + GPIO4 = (GPIO_TypeDef *)GPIO4_BASE; +#endif /* _GPIO4 */ + +#ifdef _GPIO5 + GPIO5 = (GPIO_TypeDef *)GPIO5_BASE; +#endif /* _GPIO5 */ + +#ifdef _GPIO6 + GPIO6 = (GPIO_TypeDef *)GPIO6_BASE; +#endif /* _GPIO6 */ + +#ifdef _GPIO7 + GPIO7 = (GPIO_TypeDef *)GPIO7_BASE; +#endif /* _GPIO7 */ + +#ifdef _GPIO8 + GPIO8 = (GPIO_TypeDef *)GPIO8_BASE; +#endif /* _GPIO8 */ + +#ifdef _GPIO9 + GPIO9 = (GPIO_TypeDef *)GPIO9_BASE; +#endif /* _GPIO9 */ + +/************************* RTC *************************/ + +#ifdef _RTC + RTC = (RTC_TypeDef *)RTC_BASE; +#endif /* _RTC */ + +/************************* PRCCU ***********************/ + +#ifdef _SCU + SCU = (SCU_TypeDef *)SCU_BASE; +#endif /* _PRCCU */ + +/************************** MC *************************/ + +#ifdef _MC + MC = (MC_TypeDef *)MC_BASE; +#endif /* _MC */ + +/************************* UART ************************/ + +#ifdef _UART0 + UART0 = (UART_TypeDef *)UART0_BASE; +#endif /* _UART0 */ + +#ifdef _UART1 + UART1 = (UART_TypeDef *)UART1_BASE; +#endif /* _UART1 */ + +#ifdef _UART2 + UART2 = (UART_TypeDef *)UART2_BASE; +#endif /* _UART2 */ + +/************************* SSP *************************/ + +#ifdef _SSP0 + SSP0 = (SSP_TypeDef *)SSP0_BASE; +#endif /* _SSP0 */ + +#ifdef _SSP1 + SSP1 = (SSP_TypeDef *)SSP1_BASE; +#endif /* _SSP1 */ + +/************************* CAN *************************/ + +#ifdef _CAN + CAN = (CAN_TypeDef *)CAN_BASE; +#endif /* _CAN */ + +/************************* ADC *************************/ + +#ifdef _ADC + ADC = (ADC_TypeDef *)ADC_BASE; +#endif /* _ADC */ + +/************************* WDG *************************/ + +#ifdef _WDG + WDG = (WDG_TypeDef *)WDG_BASE; +#endif /* _WDG */ + +/************************* I2C *************************/ + +#ifdef _I2C0 + I2C0 = (I2C_TypeDef *)I2C0_BASE; +#endif /* _I2C0 */ + +#ifdef _I2C1 + I2C1 = (I2C_TypeDef *)I2C1_BASE; +#endif /* _I2C1 */ +/********************** ENET **************************/ +#ifdef _ENET + ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE; + ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE; +#endif /* _ENET */ +} +#endif /* DEBUG */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/str91x_lib/91x_scu.c b/uc_str912/prj_TEST_LED/str91x_lib/91x_scu.c new file mode 100644 index 0000000..21116b2 --- /dev/null +++ b/uc_str912/prj_TEST_LED/str91x_lib/91x_scu.c @@ -0,0 +1,661 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SCU_PLLEN 0x80000 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SCU_MCLKSourceConfig +* Description : Configures the MCLK source clock +* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : this function returns ERROR if trying to select the PLL as +* clock source while the PLL is disabled or not locked. +*******************************************************************************/ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source) +{ + u32 CLKCNTR_Value; + + CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/ + CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/ + if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/ + { + /*check if PLL enabled & locked*/ + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + return ERROR; + } + else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/ + SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/ + return SUCCESS; +} + +/******************************************************************************* +* Function Name : SCU_PLLFactorsConfig +* Description : Sets the PLL factors +* Input : PLLN, PLLM and PLLP +* Output : None +* Return : ErrorStatus: ERROR or SUCCESS +* Notes : -The PLL factors must respect the PLL specification requirements +* -The function returns ERROR if trying to change PLL +* factors while PLL is selected as Main Clock source (MCLK) +* -This function disables the PLL, to enable the PLL use +* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors +******************************************************************************/ +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP) +{ + if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/ + { + SCU->PLLCONF =0; /*clear PLLCONF register*/ + SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/ + SCU->PLLCONF |=PLLM; /*update PLLM field*/ + SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/ + return SUCCESS; + } + return ERROR; +} + +/******************************************************************************* +* Function Name : SCU_PLLCmd +* Description : Enable or Disable the PLL +* Input : NewState = ENABLE or DISABLE +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : -The function returns ERROR if: +* *trying to disable the PLL while it is selected as the MCLK +* *trying to enable the PLL while it is already enabled and +* locked +*******************************************************************************/ +ErrorStatus SCU_PLLCmd(FunctionalState NewState) +{ + vu32 i; + if (NewState==ENABLE) + { + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + { + SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/ + SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/ + while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/ + return SUCCESS; + } + else return ERROR; + } + else /*NewState = DISABLE*/ + { + if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/ + { + for(i=10;i>0;i--); /*delay before PLL disabling*/ + SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/ + return SUCCESS; + } + else return ERROR; + } +} + +/******************************************************************************* +* Function Name : SCU_RCLKDivisorConfig +* Description : Sets the RCLK divisor value +* Input : RCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/ + if (RCLK_Divisor!=SCU_RCLK_Div1) + SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_HCLKDivisorConfig +* Description : Sets the HCLK divisor value +* Input : HCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/ + if (HCLK_Divisor!=SCU_HCLK_Div1) + SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_PCLKDivisorConfig +* Description : Sets the PCLK divisor value +* Input : PCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/ + if (PCLK_Divisor!=SCU_PCLK_Div1) + SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphClockConfig +* Description : Enable the clock for an APB peripheral +* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for APB peripheral*/ + SCU->PCGR1 |=APBPeriph; + else + SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphClockConfig +* Description : Enable the clock for an AHB peripheral +* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for AHB peripheral*/ + SCU->PCGRO |=AHBPeriph; + else + SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphReset +* Description : Assert or deassert Reset on APB peripheral +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) /*APB peripheral not held in Reset*/ + SCU->PRR1 |=APBPeriph; + else + SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphReset +* Description : Assert or deassert Reset on AHB peripheral +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) + SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/ + else + SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/ + else + SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/ + else + SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/ +} +/******************************************************************************* +* Function Name : SCU_BRCLKDivisorConfig +* Description : Sets the BRCLK divisor value +* Input : BRCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/ + if (BRCLK_Divisor!=SCU_BRCLK_Div1) + SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/ +} + +/******************************************************************************* +* Function Name : SCU_TIMCLKSourceConfig +* Description : Sets the TIMx clock source +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source) +{ + if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/ + { + SCU->CLKCNTR &=0xFFFFDFFF; + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x2000; + } + else + { + SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/ + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x4000; + } +} + +/******************************************************************************* +* Function Name : SCU_TIMPresConfig +* Description : Sets the TIMx Prescaler Value +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - Prescaler (16 bit value) +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler) +{ + if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/ + SCU->SCR1 = Prescaler&0xFFFF; + else + SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/ +} + +/******************************************************************************* +* Function Name : SCU_USBCLKConfig +* Description : Configures the clock source for the 48MHz USBCLK +* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_USBCLKConfig(u32 USBCLK_Source) +{ + SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/ + if (USBCLK_Source!=SCU_USBCLK_MCLK) + SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/ +} + +/******************************************************************************* +* Function Name : SCU_PHYCLKConfig +* Description : Enable or Disable PHY clock output +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PHYCLKConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/ + else + SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/ +} + +/******************************************************************************* +* Function Name : SCU_FMICLKDivisorConfig +* Description : Set the FMI clock divisor +* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor) +{ + SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/ + if (FMICLK_Divisor!=SCU_FMICLK_Div1) + SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIBCLKDivisorConfig +* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2 +* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK) +{ + SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */ + if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1) + SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIModeConfig +* Description : Configure the EMI as Multiplexed or Demultiplexed +* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIModeConfig(u32 SCU_EMIMODE) +{ + SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/ + if (SCU_EMIMODE!=SCU_EMI_MUX) + SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/ +} + +/******************************************************************************* +* Function Name : SCU_EMIALEConfig +* Description : Configure the ALE signal (length & polarity) +* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2 +* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL) +{ + /*Configure EMI ALE Length*/ + SCU->SCR0 &=SCU_EMIALE_LEN1; + if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1) + SCU->SCR0 |= SCU_EMIALE_LEN2; + + /*Configure EMI ALE POL*/ + SCU->SCR0 &=SCU_EMIALE_POLLow; + if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow) + SCU->SCR0 |= SCU_EMIALE_POLHigh; +} + +/******************************************************************************* +* Function Name : SCU_ITConfig +* Description : ENBALE or DISABLE an SCU interrupt +* Input : -SCU_IT: interrupt mask +* -NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->ITCMSK&=~SCU_IT; /*IT enable */ + else + SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/ +} + +/******************************************************************************* +* Function Name : SCU_GetFlagStatus +* Description : Returns flag status +* Input : SCU_Flag +* Output : NONE +* Return : SET or RESET +*******************************************************************************/ +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag) +{ + if (SCU->SYSSTATUS&SCU_Flag) + return SET; + else return RESET; +} + +/******************************************************************************* +* Function Name : SCU_ClearFlag +* Description : Clears a SYSTATUS Flag +* Input : SCU_Flag +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ClearFlag(u32 SCU_Flag) +{ + SCU->SYSSTATUS = SCU_Flag; +} +/******************************************************************************* +* Function Name : SCU_GetPLLfreqValue +* Description : Gets the current PLL frequency +* Input : None +* Output : None +* Return : PLL frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPLLFreqValue(void) +{ + u8 PLL_M; + u8 PLL_N; + u8 PLL_P; + + PLL_M = SCU->PLLCONF&0xFF; + PLL_N = (SCU->PLLCONF&0xFF00)>>8; + PLL_P = (SCU->PLLCONF&0x70000)>>16; + + if ((PLL_M>0)&&(PLL_N>0)) + return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal); + if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32); + else return (SCU_GetPLLFreqValue()); +} + +/******************************************************************************* +* Function Name : SCU_GetRCLKFreqValue +* Description : Gets the current RCLK frequency +* Input : None +* Output : None +* Return : RCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetRCLKFreqValue(void) +{ + u8 RCLK_Div; + RCLK_Div = (SCU->CLKCNTR&0x1C)>>2; + if (RCLK_Div==0x5) RCLK_Div=10; + return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetHCLKFreqValue +* Description : Gets the current PCLK frequency +* Input : None +* Output : None +* Return : HCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetHCLKFreqValue(void) +{ + u8 HCLK_Div; + HCLK_Div = (SCU->CLKCNTR&0x60)>>5; + return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetPCLKFreqValue +* Description : Gets the current HCLK frequency +* Input : None +* Output : None +* Return : PCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPCLKFreqValue(void) +{ + u8 PCLK_Div; + PCLK_Div = (SCU->CLKCNTR&0x180)>>7; + return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_WakeUpLineConfig +* Description : Configures an External interrupt as WakeUp line +* Input : EXTint : 0 -> 31 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_WakeUpLineConfig(u8 EXTint) +{ + if (EXTint < 8) + { + SCU->WKUPSEL&=~0x7; + SCU->WKUPSEL|=EXTint; + } + else if (EXTint<16) + { + SCU->WKUPSEL&=~0x38; + SCU->WKUPSEL|=(EXTint-8)<<3; + } + else if (EXTint<24) + { + SCU->WKUPSEL&=~0x1C0; + SCU->WKUPSEL|=(EXTint-16)<<6; + } + else + { + SCU->WKUPSEL&=~0xE00; + SCU->WKUPSEL|=(EXTint-24)<<9; + } +} + +/******************************************************************************* +* Function Name : SCU_SpecIntRunModeConfig +* Description : Enables or Disables the Special Run mode +* Input : newstate = ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_SpecIntRunModeConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + SCU->PWRMNG |=0x8; + else + SCU->PWRMNG &=~0x8; +} +/******************************************************************************* +* Function Name : SCU_EnterIdleMode +* Description : Enters in Idle mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterIdleMode(void) +{ + SCU->PWRMNG |=0x1; +} +/******************************************************************************* +* Function Name : SCU_EnterSleepMode +* Description : Enters in Sleep mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterSleepMode(void) +{ + SCU->PWRMNG |=0x2; +} + +/******************************************************************************* +* Function Name : SCU_UARTIrDAConfig +* Description : Enable or Disable the Irda mode for UARTx +* Input : - UARTx :x=0,1 or 2 +* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART +* Output : None +* Return : None +*******************************************************************************/ +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode) +{ + if (UART_IrDA_Mode == SCU_UARTMode_IrDA) + { + if (UARTx== UART0) SCU->SCR0 |=0x400; + else if (UARTx==UART1) SCU->SCR0 |=0x800; + else SCU->SCR0 |=0x1000; + } + else + { + if (UARTx== UART0) SCU->SCR0 &=~0x400; + else if (UARTx==UART1) SCU->SCR0 &=~0x800; + else SCU->SCR0 &=~0x1000; + } +} +/******************************************************************************* +* Function Name : SCU_PFQBCCmd +* Description : Enable or Disable PFQBC +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PFQBCCmd(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->SCR0 |=0x1; + else SCU->SCR0 &=~0x1; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_TEST_LED/vector.s b/uc_str912/prj_TEST_LED/vector.s new file mode 100644 index 0000000..7708f54 --- /dev/null +++ b/uc_str912/prj_TEST_LED/vector.s @@ -0,0 +1,202 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + + .equ VectorAddress, 0xFFFFF030 /* VIC Vector address register address. */ + .equ VectorAddressDaisy, 0xFC000030 /* Daisy VIC Vector address register */ + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */ + + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + .text + .arm + .section .vectors, "ax" + + .global Reset_Vec + +/* Note: LDR PC instructions are used here, though branch (B) instructions */ +/* could also be used, unless the ROM is at an address >32MB. */ + +/******************************************************************************* + Exception vectors +*******************************************************************************/ + +Reset_Vec: LDR pc, Reset_Addr /* Reset Handler */ +Undef_Vec: LDR pc, Undefined_Addr +SWI_Vec: LDR pc, SWI_Addr +PAbt_Vec: LDR pc, Prefetch_Addr +DAbt_Vec: LDR pc, Abort_Addr + NOP /* Reserved vector */ +IRQ_Vec: LDR pc, IRQ_Addr +FIQ_Vec: LDR pc, FIQ_Addr + +/******************************************************************************* + Exception handlers address table +*******************************************************************************/ + +Reset_Addr: .word _start +Undefined_Addr: .word UndefinedHandler +SWI_Addr: .word SWIHandler +Prefetch_Addr: .word PrefetchHandler +Abort_Addr: .word AbortHandler + .word 0 /* reserved */ +IRQ_Addr: .word IRQHandler +FIQ_Addr: .word FIQHandler + +/******************************************************************************* + Exception Handlers +*******************************************************************************/ + +/******************************************************************************* +* Macro Name : SaveContext +* Description : This macro used to save the context before entering + an exception handler. +* Input : The range of registers to store. +* Output : none +*******************************************************************************/ + +.macro SaveContext reg1 reg2 + STMFD sp!,{\reg1-\reg2,lr} /* Save The workspace plus the current return */ + /* address lr_ mode into the stack */ + MRS r1, spsr /* Save the spsr_mode into r1 */ + STMFD sp!, {r1} /* Save spsr */ +.endm + +/******************************************************************************* +* Macro Name : RestoreContext +* Description : This macro used to restore the context to return from + an exception handler and continue the program execution. +* Input : The range of registers to restore. +* Output : none +*******************************************************************************/ + +.macro RestoreContext reg1 reg2 + LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */ + MSR spsr_cxsf, r1 /* Restore spsr_mode */ + LDMFD sp!, {\reg1-\reg2,pc}^ /* Return to the instruction following */ + /* the exception interrupt */ +.endm + +/******************************************************************************* +* Function Name : IRQHandler +* Description : This function called when IRQ exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +IRQHandler: + SUB lr, lr, #4 /* Update the link register */ + SaveContext r0, r12 /* Save the workspace plus the current */ + /* return address lr_irq and spsr_irq */ + LDR r0, =VectorAddress + LDR r0, [r0] /* Read the routine address */ + LDR r1, =VectorAddressDaisy + LDR r1, [r1] + /* Padding between the acknowledge and re-enable of interrupts */ + /* For more details, please refer to the following URL */ + /* http://www.arm.com/support/faqip/3682.html */ + NOP + NOP + MSR cpsr_c, #Mode_SYS /* Switch to SYS mode and enable IRQ */ + STMFD sp!, {lr} /* Save the link register. */ + LDR lr, =ReturnAddress /* Read the return address. */ + MOV pc, r0 /* Branch to the IRQ handler. */ +ReturnAddress: + LDMFD sp!, {lr} /* Restore the link register. */ + MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit /* Switch to IRQ mode and disable IRQ */ + LDR r0, =VectorAddress /* Write to the VectorAddress to clear the */ + STR r0, [r0] /* respective interrupt in the internal interrupt */ + LDR r1, =VectorAddressDaisy /* Write to the VectorAddressDaisy to clear the */ + STR r1, [r1] /* respective interrupt in the internal interrupt */ + RestoreContext r0, r12 /* Restore the context and return to the program execution. */ + +/******************************************************************************* +* Function Name : SWIHandler +* Description : This function called when SWI instruction executed. +* Input : none +* Output : none +*******************************************************************************/ + +SWIHandler: + SaveContext r0, r12 /* r0 holds swi number */ + MOV r1, sp /* load regs */ + BL SWI_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : UndefinedHandler +* Description : This function called when undefined instruction + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +UndefinedHandler: + SaveContext r0, r12 + BL Undefined_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : PrefetchAbortHandler +* Description : This function called when Prefetch Abort + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +PrefetchHandler: + SUB lr, lr, #4 /* Update the link register. */ + SaveContext r0, r12 + BL Prefetch_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : DataAbortHandler +* Description : This function is called when Data Abort + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +AbortHandler: + SUB lr, lr, #8 /* Update the link register. */ + SaveContext r0, r12 + BL Abort_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : FIQHandler +* Description : This function is called when FIQ + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +FIQHandler: + SUB lr, lr, #4 /* Update the link register. */ + SaveContext r0, r7 + BL FIQ_Handler + RestoreContext r0, r7 + + .end diff --git a/uc_str912/prj_TEST_LED/vectors.c b/uc_str912/prj_TEST_LED/vectors.c new file mode 100644 index 0000000..4022391 --- /dev/null +++ b/uc_str912/prj_TEST_LED/vectors.c @@ -0,0 +1,462 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +#include "vectors.h" + +/******************************************************************************* +* Function Name : Undefined_Handler +* Description : This function Undefined instruction exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Undefined_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SWI_Handler +* Description : This function handles SW exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SWI_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles preftetch abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Prefetch_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : Abort_Handler +* Description : This function handles data abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Abort_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : FIQ_Handler +* Description : This function handles FIQ exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FIQ_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : WDG_IRQHandler +* Description : This function handles the WDG interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SW_IRQHandler +* Description : This function handles the SW interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SW_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ARMRX_IRQHandler +* Description : This function handles the ARMRX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMRX_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ARMTX_IRQHandler +* Description : This function handles the ARMTX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMTX_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM0_IRQHandler +* Description : This function handles the TIM0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM1_IRQHandler +* Description : This function handles the TIM1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM2_IRQHandler +* Description : This function handles the TIM2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM3_IRQHandler +* Description : This function handles the TIM3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM3_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBHP_IRQHandler +* Description : This function handles the USBHP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBHP_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBLP_IRQHandler +* Description : This function handles the USBLP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBLP_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SCU_IRQHandler +* Description : This function handles the SCU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ENET_IRQHandler +* Description : This function handles the ENET interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ENET_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : DMA_IRQHandler +* Description : This function handles the DMA interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : CAN_IRQHandler +* Description : This function handles the CAN interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : MC_IRQHandler +* Description : This function handles the MC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ADC_IRQHandler +* Description : This function handles the ADC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART0_IRQHandler +* Description : This function handles the UART0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART1_IRQHandler +* Description : This function handles the UART1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART2_IRQHandler +* Description : This function handles the UART2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : I2C0_IRQHandler +* Description : This function handles the I2C0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : I2C1_IRQHandler +* Description : This function handles the I2C1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SSP0_IRQHandler +* Description : This function handles the SSP0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SSP1_IRQHandler +* Description : This function handles the SSP1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : LVD_IRQHandler +* Description : This function handles the LVD interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LVD_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles the RTC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : WIU_IRQHandler +* Description : This function handles the WIU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WIU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT0_IRQHandler +* Description : This function handles the EXTIT0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT1_IRQHandler +* Description : This function handles the EXTIT1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT2_IRQHandler +* Description : This function handles the EXTIT2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT3_IRQHandler +* Description : This function handles the EXTIT3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT3_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBWU_IRQHandler +* Description : This function handles the USBWU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBWU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : PFQBC_IRQHandler +* Description : This function handles the PFQBC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PFQBC_IRQHandler(void) +{ + while(1); +} diff --git a/uc_str912/prj_TEST_LED/vectors.h b/uc_str912/prj_TEST_LED/vectors.h new file mode 100644 index 0000000..d48e61f --- /dev/null +++ b/uc_str912/prj_TEST_LED/vectors.h @@ -0,0 +1,67 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +#ifndef _VECTOR_H +#define _VECTOR_H + +#ifdef __cplusplus +extern "C" { +#endif + +void Undefined_Handler(void); +void FIQ_Handler(void); +void SWI_Handler(void); +void Prefetch_Handler(void); +void Abort_Handler(void); +void WDG_IRQHandler(void); +void SW_IRQHandler(void); +void ARMRX_IRQHandler(void); +void ARMTX_IRQHandler(void); +void TIM0_IRQHandler(void); +void TIM1_IRQHandler(void); +void TIM2_IRQHandler(void); +void TIM3_IRQHandler(void); +void USBHP_IRQHandler(void); +void USBLP_IRQHandler(void); +void SCU_IRQHandler(void); +void ENET_IRQHandler(void); +void DMA_IRQHandler(void); +void CAN_IRQHandler(void); +void MC_IRQHandler(void); +void ADC_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void I2C0_IRQHandler(void); +void I2C1_IRQHandler(void); +void SSP0_IRQHandler(void); +void SSP1_IRQHandler(void); +void LVD_IRQHandler(void); +void RTC_IRQHandler(void); +void WIU_IRQHandler(void); +void EXTIT0_IRQHandler(void); +void EXTIT1_IRQHandler(void); +void EXTIT2_IRQHandler(void); +void EXTIT3_IRQHandler(void); +void USBWU_IRQHandler(void); +void PFQBC_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif //_VECTOR_H diff --git a/uc_str912/prj_blinky_complex_startup/91x_conf.h b/uc_str912/prj_blinky_complex_startup/91x_conf.h new file mode 100644 index 0000000..2abcae5 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/91x_conf.h @@ -0,0 +1,118 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_conf.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Library configuration. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +#ifndef __91x_CONF_H +#define __91x_CONF_H + +/* To work in buffered mode just decomment the following line */ + +//#define Buffered + +/* Comment the line below to put the library in release mode */ +#define DEBUG + +/************************* AHBAPB *************************/ +//#define _AHBAPB +//#define _AHBAPB0 +//#define _AHBAPB1 +/************************* VIC *************************/ +#define _VIC +#define _VIC0 +#define _VIC1 +/************************* DMA *************************/ +//#define _DMA +//#define _DMA_Channel0 +//#define _DMA_Channel1 +//#define _DMA_Channel2 +//#define _DMA_Channel3 +//#define _DMA_Channel4 +//#define _DMA_Channel5 +//#define _DMA_Channel6 +//#define _DMA_Channel7 + +/************************* EMI *************************/ +//#define _EMI +//#define _EMI_Bank0 +//#define _EMI_Bank1 +//#define _EMI_Bank2 +//#define _EMI_Bank3 +/************************* FMI *************************/ +#define _FMI +/************************* WIU *************************/ +//#define _WIU +/************************* TIM *************************/ +#define _TIM +#define _TIM0 +#define _TIM1 +#define _TIM2 +#define _TIM3 +/************************* GPIO ************************/ +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 +#define _GPIO3 +#define _GPIO4 +#define _GPIO5 +#define _GPIO6 +#define _GPIO7 +#define _GPIO8 +#define _GPIO9 +/************************* RTC *************************/ +//#define _RTC +/************************* SCU *************************/ +#define _SCU +/************************* MC **************************/ +//#define _MC +/************************* UART ************************/ +#define _UART +#define _UART0 +#define _UART1 +#define _UART2 +/************************* SSP *************************/ +//#define _SSP +//#define _SSP0 +//#define _SSP1 +/************************* CAN *************************/ +//#define _CAN +/************************* ADC *************************/ +//#define _ADC +/************************* WDG *************************/ +//#define _WDG +/************************* I2C *************************/ +//#define _I2C +//#define _I2C0 +//#define _I2C1 + +/************************ ENET *************************/ +//#define _ENET +/************************ USB *************************/ +//#define _USB + +/*---------------------------- _Main_Crystal frequency value (KHz)------------*/ + +#ifndef _Main_Crystal +#define _Main_Crystal 25000 +#endif +/*------------------------------------------------------------------------------*/ + + +#endif /* __91x_CONF_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/Makefile b/uc_str912/prj_blinky_complex_startup/Makefile new file mode 100644 index 0000000..325838f --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/Makefile @@ -0,0 +1,463 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# +# based on +# WinARM template makefile +# by Martin Thomas, Kaiserslautern, Germany +# +# +# based on the WinAVR makefile written by Eric B. Weddington, J?g Wunsch, et al. +# Released to the Public Domain +# Please read the make user manual! +# +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# To rebuild project do "make clean" then "make all". +# +# Requires: +# - CodeSourcery Toolchain (tested & working with Lite version under Windows & Linux) +# - startup912.s and startup_generic.s to be renamed to .S with capital "S" to avoid deletion when calling "make clean" +# - Changes in file: scripts/flash_str9.ld +# replace: ./obj/startup912.o (.text) /* Startup code */ +# to: ./startup912.o (.text) /* Startup code */ +# or else change it to where this file is relative to current dir. +# + + + +# Toolchain prefix (i.e arm-elf -> arm-elf-gcc.exe) +TCHAIN = arm-none-eabi + +#USE_THUMB_MODE = YES +USE_THUMB_MODE = NO + +#------------------------------------------------------------------- + +# MCU name and submodel +MCU = arm966e-s +HEX_NAME = STR9 + +# Target file name (without extension). +TARGET = main + +# List C source files here. (C dependencies are automatically generated.) +# use file-extension c for "c-only"-files +#SRC = $(TARGET).c + +# List C source files here which must be compiled in ARM-Mode. +# use file-extension c for "c-only"-files +#SRCARM = vectors.c + +SRCARM += ./src/91x_adc.c +SRCARM += ./src/91x_ahbapb.c +SRCARM += ./src/91x_can.c +SRCARM += ./src/91x_dma.c +SRCARM += ./src/91x_emi.c +SRCARM += ./src/91x_fmi.c +SRCARM += ./src/91x_gpio.c +SRCARM += ./src/91x_i2c.c +SRCARM += ./src/91x_lib.c +SRCARM += ./src/91x_mc.c +SRCARM += ./src/91x_rtc.c +SRCARM += ./src/91x_scu.c +SRCARM += ./src/91x_ssp.c +SRCARM += ./src/91x_tim.c +SRCARM += ./src/91x_uart.c +SRCARM += ./src/91x_vic.c +SRCARM += ./src/91x_wdg.c +SRCARM += ./src/91x_wiu.c +#SRCARM += ./src/usb_core.c +#SRCARM += ./src/usb_init.c +#SRCARM += ./src/usb_int.c +#SRCARM += ./src/usb_mem.c +#SRCARM += ./src/usb_regs.c +SRCARM += main.c +SRCARM += interrupt.c +SRCARM += syscalls.c + +# thumb is possible too for vectors.c - keep ARM, TODO: profile + +# List C++ source files here. +# use file-extension cpp for C++-files (use extension .cpp) +CPPSRC = + +# List C++ source files here which must be compiled in ARM-Mode. +# use file-extension cpp for C++-files (use extension .cpp) +#CPPSRCARM = $(TARGET).cpp +CPPSRCARM = + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +# List Assembler source files here which must be assembled in ARM-Mode.. +#ASRCARM = startup.S vector.S +ASRCARM = startup912.S + +# Path to Linker-Scripts +LINKERSCRIPTPATH = ../scripts + +## Output format. (can be ihex or binary or both) +## (binary i.e. for openocd and SAM-BA, hex i.e. for lpc21isp and uVision) +#FORMAT = ihex +#FORMAT = binary +FORMAT = both + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = s +#OPT = 0 + +# Debugging format. +DEBUG = + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +EXTRAINCDIRS = ./include + +# List any extra directories to look for library files here. +# Each directory must be seperated by a space. +#EXTRA_LIBDIRS = ../arm7_efsl_0_2_4 +EXTRA_LIBDIRS = + + +# Compiler flag to set the C Standard level. +# c89 - "ANSI" C +# gnu89 - c89 plus GCC extensions +# c99 - ISO C99 standard (not yet fully implemented) +# gnu99 - c99 plus GCC extensions +CSTANDARD = -std=gnu99 + +# Place -D or -U options for C here +CDEFS = + + +# Place -I options here +CINCS = + +# Place -D or -U options for ASM here +ADEFS = + +# Compiler flags. + +ifeq ($(USE_THUMB_MODE),YES) +THUMB = -mthumb +THUMB_IW = -mthumb-interwork +else +THUMB = +THUMB_IW = +endif + +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +# +# Flags for C and C++ (arm-elf-gcc/arm-elf-g++) +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) $(CINCS) +CFLAGS += -O$(OPT) +CFLAGS += -Wall -Wcast-align -Wimplicit +#CFLAGS += -Wpointer-arith -Wswitch +CFLAGS += -ffunction-sections -fdata-sections +CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused +CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +# flags only for C +CONLYFLAGS += -Wnested-externs +CONLYFLAGS += $(CSTANDARD) + +# flags only for C++ (arm-elf-g++) +# CPPFLAGS = -fno-rtti -fno-exceptions +CPPFLAGS = + +# Assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlns: create listing +# -g$(DEBUG): have the assembler create line number information +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG) + + +#Additional libraries. + +# Extra libraries +# Each library-name must be seperated by a space. +# To add libxyz.a, libabc.a and libefsl.a: +# EXTRA_LIBS = xyz abc efsl +#EXTRA_LIBS = efsl +EXTRA_LIBS = + + +# Linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS += -nostartfiles +#LDFLAGS += -nostdlib +#LDFLAGS += -nodefaultlibs +LDFLAGS += -Wl,-Map=$(TARGET).map +LDFLAGS += -Wl,--cref +#LDFLAGS += -Wl,--gc-sections +#LDFLAGS += -Wl,-Ttext=0x000000,-Tdata=0x4000000 + +#LDFLAGS += -lm +#LDFLAGS += -lc +LDFLAGS += -lgcc +#LDFLAGS += -lstdc++ +#LDFLAGS += $(patsubst %,-L%,$(EXTRA_LIBDIRS)) +#LDFLAGS += $(patsubst %,-l%,$(EXTRA_LIBS)) + +# Set Linker-Script +LDFLAGS +=-T$(LINKERSCRIPTPATH)/str912fw44.ld +#LDFLAGS +=-T$(LINKERSCRIPTPATH)/flash_str9.ld +#LDFLAGS +=-T$(LINKERSCRIPTPATH)/str912_rom.ld + + +# Define programs and commands. +SHELL = sh +CC = $(TCHAIN)-gcc +CPP = $(TCHAIN)-g++ +AR = $(TCHAIN)-ar +OBJCOPY = $(TCHAIN)-objcopy +OBJDUMP = $(TCHAIN)-objdump +SIZE = $(TCHAIN)-size +NM = $(TCHAIN)-nm +REMOVE = rm -f +REMOVEDIR = rm -f -r +COPY = cp + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = "-------- begin (mode: $(RUN_MODE)) --------" +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_FLASH = Creating load file for Flash: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_ARM = "Compiling C (ARM-only):" +MSG_COMPILINGCPP = Compiling C++: +MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):" +MSG_ASSEMBLING = Assembling: +MSG_ASSEMBLING_ARM = "Assembling (ARM-only):" +MSG_CLEANING = Cleaning project: +MSG_FORMATERROR = Can not handle output-format +MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now. + +# Define all object files. +COBJ = $(SRC:.c=.o) +AOBJ = $(ASRC:.S=.o) +COBJARM = $(SRCARM:.c=.o) +AOBJARM = $(ASRCARM:.S=.o) +CPPOBJ = $(CPPSRC:.cpp=.o) +CPPOBJARM = $(CPPSRCARM:.cpp=.o) + +# Define all listing files. +LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst) +LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst) + +# Compiler flags to generate dependency files. +### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d +GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS) + + +# Default target. +all: begin gccversion sizebefore build sizeafter finished end + +ifeq ($(FORMAT),ihex) +build: elf hex lss sym +hex: $(TARGET).hex +IMGEXT=hex +else +ifeq ($(FORMAT),binary) +build: elf bin lss sym +bin: $(TARGET).bin +IMGEXT=bin +else +ifeq ($(FORMAT),both) +build: elf hex bin lss sym +hex: $(TARGET).hex +bin: $(TARGET).bin +else +$(error "$(MSG_FORMATERROR) $(FORMAT)") +endif +endif +endif + +elf: $(TARGET).elf +lss: $(TARGET).lss +sym: $(TARGET).sym + +# Eye candy +begin: + @echo + @echo $(MSG_BEGIN) + +finished: + @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf +sizebefore: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + + +# Display compiler version information. +gccversion : + @$(CC) --version + +# Create final output file (.hex) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O ihex $< $@ + +# Create final output file (.bin) from ELF output file. +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary $< $@ + + +# Create extended listing file from ELF output file. +# testing: option -C +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S -C $< > $@ + + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) +%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) + @# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) + +# Compile: create object files from C source files. ARM/Thumb +$(COBJ) : %.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C source files. ARM-only +$(COBJARM) : %.o : %.c + @echo + @echo $(MSG_COMPILING_ARM) $< + $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM/Thumb +$(CPPOBJ) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP) $< + $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM-only + $(CPPOBJARM) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP_ARM) $< + $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. ARM/Thumb +## does not work - TODO - hints welcome +##$(COBJ) : %.s : %.c +## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM/Thumb +$(AOBJ) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM-only +$(AOBJARM) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING_ARM) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list finished end + + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).a90 + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lnk + $(REMOVE) $(TARGET).lss + $(REMOVE) $(COBJ) + $(REMOVE) $(CPPOBJ) + $(REMOVE) $(AOBJ) + $(REMOVE) $(COBJARM) + $(REMOVE) $(CPPOBJARM) + $(REMOVE) $(AOBJARM) + $(REMOVE) $(LST) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRCARM:.c=.s) + $(REMOVE) $(SRCARM:.c=.d) + $(REMOVE) $(CPPSRC:.cpp=.s) + $(REMOVE) $(CPPSRC:.cpp=.d) + $(REMOVE) $(CPPSRCARM:.cpp=.s) + $(REMOVE) $(CPPSRCARM:.cpp=.d) + $(REMOVEDIR) .dep | exit 0 + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin lss sym clean clean_list program diff --git a/uc_str912/prj_blinky_complex_startup/defines.h b/uc_str912/prj_blinky_complex_startup/defines.h new file mode 100644 index 0000000..42d3b32 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/defines.h @@ -0,0 +1,67 @@ +/******************************************************************** + * Project: STR9-comStick GNU(UART) + * File: defines.h + * + * System: ARM9TDMI 32 Bit (STR912FW44X) + * Compiler: GCC 4.0.3 + * + * Date: 2006-12-20 + * Author: Applications@Hitex.de + * + * Rights: Hitex Development Tools GmbH + * Greschbachstr. 12 + * D-76229 Karlsruhe + ******************************************************************** + * Description: + * + * This file is part of the GNU Example chain for STR9-comStick + * The code is bassed on usage of the STmicro library functions + * This is a small implementation of UART1 feature with command interface + * The application runs in ARM mode with high optimization level. + * + ******************************************************************** + * History: + * + * Revision 1.0 2006/12/20 Gn + * Initial revision + ******************************************************************** + * This is a preliminary version. + * + * WARRANTY: HITEX warrants that the media on which the SOFTWARE is + * furnished is free from defects in materials and workmanship under + * normal use and service for a period of ninety (90) days. HITEX entire + * liability and your exclusive remedy shall be the replacement of the + * SOFTWARE if the media is defective. This Warranty is void if failure + * of the media resulted from unauthorized modification, accident, abuse, + * or misapplication. + * + * DISCLAIMER: OTHER THAN THE ABOVE WARRANTY, THE SOFTWARE IS FURNISHED + * "AS IS" WITHOUT WARRANTY OF ANY KIND. HITEX DISCLAIMS ALL OTHER WARRANTIES, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * NEITHER HITEX NOR ITS AFFILIATES SHALL BE LIABLE FOR ANY DAMAGES ARISING + * OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE, INCLUDING DAMAGES FOR + * LOSS OF PROFITS, BUSINESS INTERRUPTION, OR ANY SPECIAL, INCIDENTAL, INDIRECT + * OR CONSEQUENTIAL DAMAGES EVEN IF HITEX HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGES. + ********************************************************************/ + +/* length specific types recommended by MISRA rule 13 */ + +#ifndef __DEFINES_H__ +#define __DEFINES_H__ + +#define int8_t signed char +#define uint8_t unsigned char +#define int16_t signed short +#define uint16_t unsigned short +#define int32_t signed long +#define uint32_t unsigned long + +#define float16 float +#define float32 double + +#endif /* __DEFINES_H__ */ + +/************************************ EOF ***********************************/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_adc.h b/uc_str912/prj_blinky_complex_startup/include/91x_adc.h new file mode 100644 index 0000000..25a396d --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_adc.h @@ -0,0 +1,124 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_adc.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* ADC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef __91x_ADC_H +#define __91x_ADC_H + +/* Includes ------------------------------------------------------------------*/ + +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* ADC Init structure define */ +typedef struct +{ + u16 ADC_WDG_High_Threshold; + u16 ADC_WDG_Low_Threshold; + u16 ADC_Channel_0_Mode; + u16 ADC_Channel_1_Mode; + u16 ADC_Channel_2_Mode; + u16 ADC_Channel_3_Mode; + u16 ADC_Channel_4_Mode; + u16 ADC_Channel_5_Mode; + u16 ADC_Channel_6_Mode; + u16 ADC_Channel_7_Mode; + u16 ADC_Select_Channel; + FunctionalState ADC_Scan_Mode; + u16 ADC_Conversion_Mode; +}ADC_InitTypeDef; + +/* ADC watchdog thresholds */ +typedef enum +{ + ADC_HighThreshold, + ADC_LowThreshold +}ADC_ThresholdType; + +/* Exported constants --------------------------------------------------------*/ + +/* ADC channels */ +#define ADC_Channel_0 0x00 /* Channel 0 */ +#define ADC_Channel_1 0x01 /* Channel 1 */ +#define ADC_Channel_2 0x02 /* Channel 2 */ +#define ADC_Channel_3 0x03 /* Channel 3 */ +#define ADC_Channel_4 0x04 /* Channel 4 */ +#define ADC_Channel_5 0x05 /* Channel 5 */ +#define ADC_Channel_6 0x06 /* Channel 6 */ +#define ADC_Channel_7 0x07 /* Channel 7 */ + +/* ADC modes */ +#define ADC_Continuous_Mode 0x0010 /* Continuous mode conversion */ +#define ADC_Single_Mode 0xFFEF /* Single mode conversion */ + +/* ADC Flags */ +#define ADC_FLAG_ECV 0x002F /* End of Conversion Flag */ +#define ADC_FLAG_AWD 0x002E /* Analog WatchDog Flag */ + +#define ADC_FLAG_OV_CH_0 0x00CF /* Overflow Flag for channel 0 */ +#define ADC_FLAG_OV_CH_1 0x00EF /* Overflow Flag for channel 1 */ +#define ADC_FLAG_OV_CH_2 0x010F /* Overflow Flag for channel 2 */ +#define ADC_FLAG_OV_CH_3 0x012F /* Overflow Flag for channel 3 */ +#define ADC_FLAG_OV_CH_4 0x014F /* Overflow Flag for channel 4 */ +#define ADC_FLAG_OV_CH_5 0x016F /* Overflow Flag for channel 5 */ +#define ADC_FLAG_OV_CH_6 0x018F /* Overflow Flag for channel 6 */ +#define ADC_FLAG_OV_CH_7 0x01AF /* Overflow Flag for channel 7 */ + +/* ADC conversion modes */ +#define ADC_NoThreshold_Conversion 0x0003 /* Conversion w/o thresholds */ +#define ADC_LowThreshold_Conversion 0x0002 /* Low threshold conversion */ +#define ADC_HighThreshold_Conversion 0x0001 /* High threshold conversion */ +#define ADC_No_Conversion 0x0000 /* No ADC conversion */ + +/* ADC interrupts */ +#define ADC_IT_ECV 0x0400 /* End of Conversion Interrupt */ +#define ADC_IT_AWD 0x0200 /* Analog Watchdog Interrupt */ + +/* ADC Start/Stop conversion */ +#define ADC_Conversion_Start 0x0001 /* ADC start conversion */ +#define ADC_Conversion_Stop 0xFFFE /* ADC stop conversion */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void ADC_DeInit(void); +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_PrescalerConfig(u8 ADC_Prescaler); +u8 ADC_GetPrescalerValue(void); +FlagStatus ADC_GetFlagStatus(u16 ADC_Flag); +void ADC_ClearFlag(u16 ADC_Flag); +u16 ADC_GetConversionValue(u16 ADC_Channel); +FlagStatus ADC_GetAnalogWatchdogResult(u16 ADC_Channel); +void ADC_ClearAnalogWatchdogResult(u16 ADC_Channel); +u16 ADC_GetWatchdogThreshold(ADC_ThresholdType ADC_Threshold); +void ADC_ITConfig(u16 ADC_IT, FunctionalState ADC_NewState); +void ADC_StandbyModeCmd(FunctionalState ADC_NewState); +void ADC_Cmd(FunctionalState ADC_NewState); +void ADC_ConversionCmd(u16 ADC_Conversion); + +#endif /* __91x_ADC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_ahbapb.h b/uc_str912/prj_blinky_complex_startup/include/91x_ahbapb.h new file mode 100644 index 0000000..1828d48 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_ahbapb.h @@ -0,0 +1,60 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* AHBAPB software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _91x_AHBAPB_H +#define _91x_AHBAPB_H + +#include "91x_map.h" + +#define AHBAPB_Split_Enable 0x01000000 +#define AHBAPB_Split_Disable 0xFEFFFFFF +#define AHBAPB_Error_Enable 0x0000100 +#define AHBAPB_Error_Disable 0xFFFFEFF + +/*FLAG*/ +#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/ +#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */ +#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */ +#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/ + +/* Includes ------------------------------------------------------------------*/ + + +/* AHBAPB Init structure definition */ +typedef struct +{ + u32 AHBAPB_SetTimeOut; + u32 AHBAPB_Error; + u32 AHBAPB_Split; + u8 AHBAPB_SplitCounter; +}AHBAPB_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx); +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct); +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct); +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx); + + +#endif /* _91x_AHBAPB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_can.h b/uc_str912/prj_blinky_complex_startup/include/91x_can.h new file mode 100644 index 0000000..b3d0653 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_can.h @@ -0,0 +1,165 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_can.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* CAN bus software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_CAN_H +#define __91x_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* CAN Init structure define */ +typedef struct +{ + u8 CAN_ConfigParameters; + u32 CAN_Bitrate; +}CAN_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Standard bitrates available*/ +enum +{ + CAN_BITRATE_100K, + CAN_BITRATE_125K, + CAN_BITRATE_250K, + CAN_BITRATE_500K, + CAN_BITRATE_1M +}; + +/* Control register*/ +#define CAN_CR_TEST 0x0080 +#define CAN_CR_CCE 0x0040 +#define CAN_CR_DAR 0x0020 +#define CAN_CR_EIE 0x0008 +#define CAN_CR_SIE 0x0004 +#define CAN_CR_IE 0x0002 +#define CAN_CR_INIT 0x0001 + +/* Status register */ +#define CAN_SR_BOFF 0x0080 +#define CAN_SR_EWARN 0x0040 +#define CAN_SR_EPASS 0x0020 +#define CAN_SR_RXOK 0x0010 +#define CAN_SR_TXOK 0x0008 +#define CAN_SR_LEC 0x0007 + +/* Test register*/ +#define CAN_TESTR_RX 0x0080 +#define CAN_TESTR_TX1 0x0040 +#define CAN_TESTR_TX0 0x0020 +#define CAN_TESTR_LBACK 0x0010 +#define CAN_TESTR_SILENT 0x0008 +#define CAN_TESTR_BASIC 0x0004 + +/* IFn / Command Request register*/ +#define CAN_CRR_BUSY 0x8000 + +/* IFn / Command Mask register*/ +#define CAN_CMR_WRRD 0x0080 +#define CAN_CMR_MASK 0x0040 +#define CAN_CMR_ARB 0x0020 +#define CAN_CMR_CONTROL 0x0010 +#define CAN_CMR_CLRINTPND 0x0008 +#define CAN_CMR_TXRQSTNEWDAT 0x0004 +#define CAN_CMR_DATAA 0x0002 +#define CAN_CMR_DATAB 0x0001 + +/* IFn / Mask 2 register*/ +#define CAN_M2R_MXTD 0x8000 +#define CAN_M2R_MDIR 0x4000 + +/* IFn / Arbitration 2 register*/ +#define CAN_A2R_MSGVAL 0x8000 +#define CAN_A2R_XTD 0x4000 +#define CAN_A2R_DIR 0x2000 + +/* IFn / Message Control register*/ +#define CAN_MCR_NEWDAT 0x8000 +#define CAN_MCR_MSGLST 0x4000 +#define CAN_MCR_INTPND 0x2000 +#define CAN_MCR_UMASK 0x1000 +#define CAN_MCR_TXIE 0x0800 +#define CAN_MCR_RXIE 0x0400 +#define CAN_MCR_RMTEN 0x0200 +#define CAN_MCR_TXRQST 0x0100 +#define CAN_MCR_EOB 0x0080 + + +/* Wake-up modes*/ +enum +{ + CAN_WAKEUP_ON_EXT, + CAN_WAKEUP_ON_CAN +}; + + +/* CAN message structure*/ +typedef struct +{ + u32 IdType; + u32 Id; + u8 Dlc; + u8 Data[8]; +} canmsg; + +/* Message ID types*/ +enum +{ + CAN_STD_ID, + CAN_EXT_ID +}; + +/* Message ID limits*/ + +#define CAN_LAST_STD_ID ((1<<11) - 1) +#define CAN_LAST_EXT_ID ((1L<<29) - 1) + +/* Exported functions ------------------------------------------------------- */ + +void CAN_Init (CAN_InitTypeDef *CAN_InitStruct); +void CAN_DeInit (void); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SetBitrate(u32 bitrate); +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj); +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType); +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); +void CAN_InvalidateAllMsgObj(void); +ErrorStatus CAN_ReleaseMessage(u32 msgobj); +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); +ErrorStatus CAN_WaitEndOfTx(void); +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg); +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg); +void CAN_EnterTestMode(u8 TestMask); +void CAN_EnterInitMode(u8 InitMask); +void CAN_LeaveInitMode(void); +void CAN_LeaveTestMode(void); +void CAN_ReleaseTxMessage(u32 msgobj); +void CAN_ReleaseRxMessage(u32 msgobj); +u32 CAN_IsMessageWaiting(u32 msgobj); +u32 CAN_IsTransmitRequested(u32 msgobj); +u32 CAN_IsInterruptPending(u32 msgobj); +u32 CAN_IsObjectValid(u32 msgobj); + +#endif /* __91x_CAN_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_dma.h b/uc_str912/prj_blinky_complex_startup/include/91x_dma.h new file mode 100644 index 0000000..6a383aa --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_dma.h @@ -0,0 +1,247 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : template.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : provide a short description of the source file indicating +* its purpose. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_DMA_H +#define __91x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include"91x_map.h" + + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/ + + u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/ + + u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */ + + u32 DMA_Channel_DesWidth; /* Destination transfer width. */ + + u32 DMA_Channel_SrcWidth; /* Source transfer width. */ + + u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/ + + u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */ + + u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/ + + u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */ + + u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */ + + u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */ + +} DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + /* Interrupts masks */ + +#define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */ +#define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/ +#define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/ + + /* Sources Request (used as masks) */ + +#define DMA_USB_RX_Mask 0x0001 +#define DMA_USB_TX_Mask 0x0002 +#define DMA_TIM0_Mask 0x0004 +#define DMA_TIM1_Mask 0x0008 +#define DMA_UART0_RX_Mask 0x0010 +#define DMA_UART0_TX_Mask 0x0020 +#define DMA_UART1_RX_Mask 0x0040 +#define DMA_UART1_TX_Mask 0x0080 +#define DMA_External_Req0_Mask 0x0100 +#define DMA_External_Req1_Mask 0x0200 +#define DMA_I2C0_Mask 0x0400 +#define DMA_I2C1_Mask 0x0800 +#define DMA_SSP0_RX_Mask 0x1000 +#define DMA_SSP0_TX_Mask 0x2000 +#define DMA_SSP1_RX_Mask 0x4000 +#define DMA_SSP1_TX_Mask 0x8000 + + +/* Previleged Mode and user mode */ + +#define DMA_PrevilegedMode 0x10000000 +#define DMA_UserMode 0xEFFFFFFF + + +/* Error and Terminal Count interrupts Status, after and before"raw" masking */ +#define DMA_IS 0x01 +#define DMA_TCS 0x02 +#define DMA_ES 0x03 +#define DMA_TCRS 0x04 +#define DMA_ERS 0x05 + + +/* interrupt clear: Terminal Count flag Clear and Error flag clear*/ + +#define DMA_TCC 0x01 +#define DMA_EC 0x02 + +/* channel index "0...7"*/ + +#define Channel0 0 +#define Channel1 1 +#define Channel2 2 +#define Channel3 3 +#define Channel4 4 +#define Channel5 5 +#define Channel6 6 +#define Channel7 7 + + + +/* Destination request selection: selects the DMA Destination request peripheral */ + +#define DMA_DES_USB_RX 0x00 +#define DMA_DES_USB_TX 0x40 +#define DMA_DES_TIM1 0x80 +#define DMA_DES_TIM2 0xC0 +#define DMA_DES_UART0_RX 0x100 +#define DMA_DES_UART0_TX 0x140 +#define DMA_DES_UART1_RX 0x180 +#define DMA_DES_UART1_TX 0x1C0 +#define DMA_DES_External_Req0 0x200 +#define DMA_DES_External_Req1 0x240 +#define DMA_DES_I2C0 0x280 +#define DMA_DES_I2C1 0x2C0 +#define DMA_DES_SSP0_RX 0x300 +#define DMA_DES_SSP0_TX 0x340 +#define DMA_DES_SSP1_RX 0x380 +#define DMA_DES_SSP1_TX 0x3C0 + + + + +/* Source request selection: selects the DMA Source request peripheral */ + +#define DMA_SRC_USB_RX 0x00 +#define DMA_SRC_USB_TX 0x02 +#define DMA_SRC_TIM1 0x04 +#define DMA_SRC_TIM2 0x06 +#define DMA_SRC_UART0_RX 0x08 +#define DMA_SRC_UART0_TX 0x0A +#define DMA_SRC_UART1_RX 0x0C +#define DMA_SRC_UART1_TX 0x0E +#define DMA_SRC_External_Req0 0x10 +#define DMA_SRC_External_Req1 0x12 +#define DMA_SRC_I2C0 0x14 +#define DMA_SRC_I2C1 0x16 +#define DMA_SRC_SSP0_RX 0x18 +#define DMA_SRC_SSP0_TX 0x1A +#define DMA_SRC_SSP1_RX 0x1C +#define DMA_SRC_SSP1_TX 0x1E + + + + + +#define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */ +#define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */ +#define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */ +#define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */ +#define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */ +#define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */ +#define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */ +#define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */ + + + + +#define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */ +#define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */ +#define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */ +#define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */ +#define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */ +#define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */ +#define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */ +#define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */ + + + + +#define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */ +#define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */ +#define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */ +#define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */ +#define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */ +#define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */ +#define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */ +#define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */ + + + + + +#define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */ +#define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */ +#define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */ + + + + +#define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */ +#define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */ +#define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */ + + + + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void DMA_DeInit(void); +void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(FunctionalState NewState); +void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); +FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ); +ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq); +void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr); +void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState); +FlagStatus DMA_GetSReq(u16 DMA_SrcReq); +FlagStatus DMA_GetLSReq(u16 DMA_SrcReq); +FlagStatus DMA_GetBReq(u16 DMA_SrcReq); +FlagStatus DMA_GetLBReq(u16 DMA_SrcReq); +FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx); +void DMA_SetSReq(u16 DMA_SrcReq); +void DMA_SetLSReq(u16 DMA_SrcReq); +void DMA_SetBReq(u16 DMA_SrcReq); +void DMA_SetLBReq(u16 DMA_SrcReq); +void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode); +void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); +void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); + +#endif /* __91x_DMA_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_emi.h b/uc_str912/prj_blinky_complex_startup/include/91x_emi.h new file mode 100644 index 0000000..4633020 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_emi.h @@ -0,0 +1,83 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_emi.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* EMI software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_EMI_H +#define __91x_EMI_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ + typedef struct + { + u32 EMI_Bank_IDCY; + + u32 EMI_Bank_WSTRD; + + u32 EMI_Bank_WSTWR; + + u32 EMI_Bank_WSTROEN; + + u32 EMI_Bank_WSTWEN; + + u32 EMI_Bank_MemWidth ; + + u32 EMI_Bank_WriteProtection; + + u32 EMI_PageModeRead_TransferLength; + + u32 EMI_PageModeRead_Selection; + + } EMI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + +/* page transfer length for page mode read */ +#define EMI_4Data 0x00000000 /*4 transfers burst*/ +#define EMI_8Data 0x00000400 /*8 transfers burst*/ + + +/*Select or deselect the page mode read*/ +#define EMI_NormalMode 0x00000000 /*Normal Mode*/ +#define EMI_PageModeRead 0x00000100 /*Page Mode Read*/ + + +/*memory width*/ +#define EMI_Width_Byte 0x00000000 /*8 bits width*/ +#define EMI_Width_HalfWord 0x00000010 /*16 bits width*/ + +/*Write protection feature */ +#define EMI_Bank_NonWriteProtect 0x00000000 /*No write protection*/ +#define EMI_Bank_WriteProtect 0x00000008 /*bank is write protected*/ + + +/* Exported macro ------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ + +void EMI_DeInit(void); +void EMI_Init( EMI_Bank_TypeDef* EMI_Bankx, EMI_InitTypeDef* EMI_InitStruct); +void EMI_StructInit(EMI_InitTypeDef* EMI_InitStruct); + +#endif /* __EMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_fmi.h b/uc_str912/prj_blinky_complex_startup/include/91x_fmi.h new file mode 100644 index 0000000..06e8115 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_fmi.h @@ -0,0 +1,184 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* FMI software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef __91x_FMI_H +#define __91x_FMI_H + +/* ========================================================================== */ +/* When bank 1 is remapped at address 0x0, decomment the following line */ +/* ========================================================================== */ + +//#define Remap_Bank_1 + + +/* Includes ------------------------------------------------------------------*/ + +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* FMI banks */ + +#ifdef Remap_Bank_1 + +#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */ + +#else /* Remap Bank 0 */ + +#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */ + +#endif + +/* FMI sectors */ + +#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */ +#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */ +#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */ +#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */ +#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */ +#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */ +#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */ +#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */ + +#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */ +#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */ +#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */ +#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */ + +/* FMI Flags */ + +#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */ +#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */ +#define FMI_FLAG_PS 0x10 /* Program Status Flag */ +#define FMI_FLAG_ES 0x20 /* Erase Status Flag */ +#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */ +#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */ + +/* FMI read wait states */ + +#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */ +#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */ +#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */ + +/* FMI write wait states */ + +#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */ +#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */ + +/* FMI power down configuration */ + +#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */ +#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */ + +/* FMI low voltage detector */ + +#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */ +#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */ + +/* FMI frequency range */ + +#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */ +#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */ + /* Above 66 MHz*/ +/* FMI OTP word addresses */ + +#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */ +#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */ +#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */ +#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */ +#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */ +#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */ +#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */ +#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */ + +/* FMI OTP halfword addresses */ + +#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */ +#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */ +#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */ +#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */ +#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */ +#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */ +#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */ +#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */ +#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */ +#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */ +#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */ +#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */ +#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */ +#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */ +#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */ +#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */ + +/* FMI sectors Masks */ + +#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */ +#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */ +#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */ +#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */ +#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */ +#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */ +#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */ +#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */ + +#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */ +#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */ +#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */ +#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */ + +/* Timeout error */ + +#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */ +#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress); +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange); +void FMI_EraseSector(vu32 FMI_Sector); +void FMI_EraseBank(vu32 FMI_Bank); +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data); +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData); +u32 FMI_ReadWord(u32 FMI_Address); +u32 FMI_ReadOTPData(u8 FMI_OTPAddress); +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank); +u16 FMI_GetReadWaitStateValue(void); +u16 FMI_GetWriteWaitStateValue(void); +void FMI_SuspendEnable(vu32 FMI_Bank); +void FMI_ResumeEnable(vu32 FMI_Bank); +void FMI_ClearFlag(vu32 FMI_Bank); +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState); +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection); +u8 FMI_WaitForLastOperation(vu32 FMI_Bank); + +#endif /* __91x_FMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_gpio.h b/uc_str912/prj_blinky_complex_startup/include/91x_gpio.h new file mode 100644 index 0000000..4beab75 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_gpio.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef _91x_GPIO_H +#define _91x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* GPIO Init structure definition */ +typedef struct +{ + u8 GPIO_Pin; + u8 GPIO_Direction; + u8 GPIO_Type; + u8 GPIO_IPConnected; + u16 GPIO_Alternate; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + + +/* Exported constants --------------------------------------------------------*/ +#define GPIO_Pin_None 0x00 +#define GPIO_Pin_0 0x01 +#define GPIO_Pin_1 0x02 +#define GPIO_Pin_2 0x04 +#define GPIO_Pin_3 0x08 +#define GPIO_Pin_4 0x10 +#define GPIO_Pin_5 0x20 +#define GPIO_Pin_6 0x40 +#define GPIO_Pin_7 0x80 +#define GPIO_Pin_All 0xFF + +#define GPIO_PinInput 0x00 +#define GPIO_PinOutput 0x01 + +#define GPIO_Type_PushPull 0x00 +#define GPIO_Type_OpenCollector 0x01 + +#define GPIO_IPConnected_Disable 0x00 +#define GPIO_IPConnected_Enable 0x01 + +#define GPIO_InputAlt1 0x00 +#define GPIO_OutputAlt1 0x01 +#define GPIO_OutputAlt2 0x02 +#define GPIO_OutputAlt3 0x03 + +#define GPIO_ANAChannel0 0x01 +#define GPIO_ANAChannel1 0x02 +#define GPIO_ANAChannel2 0x04 +#define GPIO_ANAChannel3 0x08 +#define GPIO_ANAChannel4 0x10 +#define GPIO_ANAChannel5 0x20 +#define GPIO_ANAChannel6 0x40 +#define GPIO_ANAChannel7 0x80 +#define GPIO_ANAChannelALL 0xFF + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin); +u8 GPIO_Read(GPIO_TypeDef* GPIOx); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal); +void GPIO_EMIConfig(FunctionalState NewState); +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState); + +#endif /* _91x_GPIO_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_i2c.h b/uc_str912/prj_blinky_complex_startup/include/91x_i2c.h new file mode 100644 index 0000000..f4d0c66 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_i2c.h @@ -0,0 +1,112 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_i2c.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* I2C software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_I2C_H +#define __91x_I2C_H + +/* Includes ----------------------------------------------------------------- */ +#include "91x_map.h" + +/* Exported types ----------------------------------------------------------- */ +/* I2C Init structure definition */ +typedef struct +{ + u32 I2C_CLKSpeed; + u16 I2C_OwnAddress; + u8 I2C_GeneralCall; + u8 I2C_Ack; +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +#define I2C_GeneralCall_Enable 0x10 +#define I2C_GeneralCall_Disable 0xEF +/* Acknowledgement */ +#define I2C_Ack_Enable 0x04 +#define I2C_Ack_Disable 0xFB + +/* I2C Flags */ +#define I2C_FLAG_SB 0x0001 +#define I2C_FLAG_M_SL 0x0002 +#define I2C_FLAG_ADSL 0x0004 +#define I2C_FLAG_BTF 0x0008 +#define I2C_FLAG_BUSY 0x0010 +#define I2C_FLAG_TRA 0x0020 +#define I2C_FLAG_ADD10 0x0040 +#define I2C_FLAG_EVF 0x0080 +#define I2C_FLAG_GCAL 0x0100 +#define I2C_FLAG_BERR 0x0200 +#define I2C_FLAG_ARLO 0x0400 +#define I2C_FLAG_STOPF 0x0800 +#define I2C_FLAG_AF 0x1000 +#define I2C_FLAG_ENDAD 0x2000 +#define I2C_FLAG_ACK 0x4000 + +/* I2C Events */ +#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_ADSL) +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF ) +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB ) +#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD ) +#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF ) +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 ) +#define I2C_EVENT_SLAVE_STOP_DETECTED I2C_FLAG_STOPF +#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF) + +#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR +#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO +#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL) + +/* Master/Receiver Mode */ +#define I2C_MODE_TRANSMITTER 0x00 +#define I2C_MODE_RECEIVER 0x01 + +/* I2C Registers offset */ +#define I2C_CR 0x00 +#define I2C_SR1 0x04 +#define I2C_SR2 0x08 +#define I2C_CCR 0x0C +#define I2C_OAR1 0x10 +#define I2C_OAR2 0x14 +#define I2C_DR 0x18 +#define I2C_ECCR 0x1C + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateStart(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 Direction); +u8 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u16 I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u16 I2C_FLAG, ...); +void I2C_SendData(I2C_TypeDef* I2Cx, u8 bData); +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx); +u16 I2C_GetLastEvent(I2C_TypeDef* I2Cx); +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,u16 I2C_Event); + +#endif /* __91x_I2C_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_it.h b/uc_str912/prj_blinky_complex_startup/include/91x_it.h new file mode 100644 index 0000000..a8e35fc --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_it.h @@ -0,0 +1,73 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_it.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains the headers of the interrupt +* handlers'routines +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef _91x_IT_H +#define _91x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void Undefined_Handler (void); +void SWI_Handler (void); +void Prefetch_Handler (void); +void Abort_Handler (void); +void FIQ_Handler (void); +void WDG_IRQHandler (void); +void SW_IRQHandler (void); +void ARMRX_IRQHandler (void); +void ARMTX_IRQHandler (void); +void TIM0_IRQHandler (void); +void TIM1_IRQHandler (void); +void TIM2_IRQHandler (void); +void TIM3_IRQHandler (void); +void USBHP_IRQHandler (void); +void USBLP_IRQHandler (void); +void SCU_IRQHandler (void); +void ENET_IRQHandler (void); +void DMA_IRQHandler (void); +void CAN_IRQHandler (void); +void MC_IRQHandler (void); +void ADC_IRQHandler (void); +void UART0_IRQHandler (void); +void UART1_IRQHandler (void); +void UART2_IRQHandler (void); +void I2C0_IRQHandler (void); +void I2C1_IRQHandler (void); +void SSP0_IRQHandler (void); +void SSP1_IRQHandler (void); +void LVD_IRQHandler (void); +void RTC_IRQHandler (void); +void WIU_IRQHandler (void); +void EXTIT0_IRQHandler (void); +void EXTIT1_IRQHandler (void); +void EXTIT2_IRQHandler (void); +void EXTIT3_IRQHandler (void); +void USBWU_IRQHandler (void); +void PFQBC_IRQHandler (void); + +#endif /* _91x_IT_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_lib.h b/uc_str912/prj_blinky_complex_startup/include/91x_lib.h new file mode 100644 index 0000000..823b250 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_lib.h @@ -0,0 +1,114 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Used to include the peripherals header file in the +* user application. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __91x_LIB_H +#define __91x_LIB_H + +#include "91x_map.h" +#include "91x_conf.h" + +#ifdef _AHBAPB + #include "91x_ahbapb.h" +#endif /* _AHBAPB */ + +#ifdef _EMI + #include "91x_emi.h" +#endif /* _EMI */ + +#ifdef _DMA + #include "91x_dma.h" +#endif /* _DMA */ + +#ifdef _FMI + #include "91x_fmi.h" +#endif /* _FMI */ + +#ifdef _VIC + #include "91x_vic.h" +#endif /* _VIC */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif /* _WIU */ + +#ifdef _TIM + #include "91x_tim.h" +#endif /* _TIM */ + +#ifdef _GPIO + #include "91x_gpio.h" +#endif /* _GPIO */ + +#ifdef _RTC + #include "91x_rtc.h" +#endif /* _RTC */ + +#ifdef _SCU + #include "91x_scu.h" +#endif /* _SCU */ + +#ifdef _UART + #include "91x_uart.h" +#endif /* _UART */ + +#ifdef _SSP + #include "91x_ssp.h" +#endif /* _SSP */ + +#ifdef _CAN + #include "91x_can.h" +#endif /* _CAN */ + +#ifdef _ADC + #include "91x_adc.h" +#endif /* _ADC */ + +#ifdef _WDG + #include "91x_wdg.h" +#endif /* _WDG */ + +#ifdef _I2C + #include "91x_i2c.h" +#endif /* _I2C */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif + +#ifdef _MC + #include "91x_mc.h" +#endif + +#ifdef _ENET + #include "91x_enet.h" +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + void debug( void ); + + +#endif /* __91x_LIB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_map.h b/uc_str912/prj_blinky_complex_startup/include/91x_map.h new file mode 100644 index 0000000..2e94a91 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_map.h @@ -0,0 +1,878 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_map.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Peripherals registers definition and memory mapping. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_MAP_H +#define __91x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_conf.h" +#include "91x_type.h" + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------------------ FMI -----------------------------------*/ + +typedef struct +{ + vu32 BBSR; /* Boot Bank Size Register */ + vu32 NBBSR; /* Non-Boot Bank Size Register */ + vu32 EMPTY1; + vu32 BBADR; /* Boot Bank Base Address Register */ + vu32 NBBADR; /* Non-Boot Bank Base Address Register */ + vu32 EMPTY2; + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */ +} FMI_TypeDef; + +/*---------------------- Analog to Digital Convertor ------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 CCR; /* Channel Configuration Register */ + vu16 EMPTY2; + vu16 HTR; /* Higher Threshold Register */ + vu16 EMPTY3; + vu16 LTR; /* Lower Threshold Register */ + vu16 EMPTY4; + vu16 CRR; /* Compare Result Register */ + vu16 EMPTY5; + vu16 DR0; /* Data Register for Channel 0 */ + vu16 EMPTY6; + vu16 DR1; /* Data Register for Channel 1 */ + vu16 EMPTY7; + vu16 DR2; /* Data Register for Channel 2 */ + vu16 EMPTY8; + vu16 DR3; /* Data Register for Channel 3 */ + vu16 EMPTY9; + vu16 DR4; /* Data Register for Channel 4 */ + vu16 EMPTY10; + vu16 DR5; /* Data Register for Channel 5 */ + vu16 EMPTY11; + vu16 DR6; /* Data Register for Channel 6 */ + vu16 EMPTY12; + vu16 DR7; /* Data Register for Channel 7 */ + vu16 EMPTY13; + vu16 PRS; /* Prescaler Value Register */ + vu16 EMPTY14; +} ADC_TypeDef; + +/*--------------------- AHB APB BRIDGE registers strcture --------------------*/ + +typedef struct +{ + vu32 BSR; /* Bridge Status Register */ + vu32 BCR; /* Bridge Configuration Register */ + vu32 PAER; /* Peripheral Address Error register */ +} AHBAPB_TypeDef; + +/*--------------- Controller Area Network Interface Register -----------------*/ + +typedef struct +{ + vu16 CRR; /* IFn Command request Register */ + vu16 EMPTY1; + vu16 CMR; /* IFn Command Mask Register */ + vu16 EMPTY2; + vu16 M1R; /* IFn Message Mask 1 Register */ + vu16 EMPTY3; + vu16 M2R; /* IFn Message Mask 2 Register */ + vu16 EMPTY4; + vu16 A1R; /* IFn Message Arbitration 1 Register */ + vu16 EMPTY5; + vu16 A2R; /* IFn Message Arbitration 2 Register */ + vu16 EMPTY6; + vu16 MCR; /* IFn Message Control Register */ + vu16 EMPTY7; + vu16 DA1R; /* IFn DATA A 1 Register */ + vu16 EMPTY8; + vu16 DA2R; /* IFn DATA A 2 Register */ + vu16 EMPTY9; + vu16 DB1R; /* IFn DATA B 1 Register */ + vu16 EMPTY10; + vu16 DB2R; /* IFn DATA B 2 Register */ + vu16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 SR; /* Status Register */ + vu16 EMPTY2; + vu16 ERR; /* Error counter Register */ + vu16 EMPTY3; + vu16 BTR; /* Bit Timing Register */ + vu16 EMPTY4; + vu16 IDR; /* Interrupt Identifier Register */ + vu16 EMPTY5; + vu16 TESTR; /* Test Register */ + vu16 EMPTY6; + vu16 BRPR; /* BRP Extension Register */ + vu16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + vu16 EMPTY8[16]; + vu16 TXR1R; /* Transmission request 1 Register */ + vu16 EMPTY9; + vu16 TXR2R; /* Transmission Request 2 Register */ + vu16 EMPTY10[13]; + vu16 ND1R; /* New Data 1 Register */ + vu16 EMPTY11; + vu16 ND2R; /* New Data 2 Register */ + vu16 EMPTY12[13]; + vu16 IP1R; /* Interrupt Pending 1 Register */ + vu16 EMPTY13; + vu16 IP2R; /* Interrupt Pending 2 Register */ + vu16 EMPTY14[13]; + vu16 MV1R; /* Message Valid 1 Register */ + vu16 EMPTY15; + vu16 MV2R; /* Message VAlid 2 Register */ + vu16 EMPTY16; +} CAN_TypeDef; + +/*----------------------- System Control Unit---------------------------------*/ + +typedef struct +{ + vu32 CLKCNTR; /* Clock Control Register */ + vu32 PLLCONF; /* PLL Configuration Register */ + vu32 SYSSTATUS; /* System Status Register */ + vu32 PWRMNG; /* Power Management Register */ + vu32 ITCMSK; /* Interrupt Mask Register */ + vu32 PCGRO; /* Peripheral Clock Gating Register 0 */ + vu32 PCGR1; /* Peripheral Clock Gating Register 1 */ + vu32 PRR0; /* Peripheral Reset Register 0 */ + vu32 PRR1; /* Peripheral Reset Register 1 */ + vu32 MGR0; /* Idle Mode Mask Gating Register 0 */ + vu32 MGR1; /* Idle Mode Mask Gating Register 1 */ + vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */ + vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */ + vu32 SCR0; /* System Configuration Register 0 */ + vu32 SCR1; /* System Configuration Register 1 */ + vu32 SCR2; /* System Configuration Register 2 */ + u32 EMPTY1; + vu32 GPIOOUT[8]; /* GPIO Output Registers */ + vu32 GPIOIN[8]; /* GPIO Input Registers */ + vu32 GPIOTYPE[10];/* GPIO Type Registers */ + vu32 GPIOEMI; /* GPIO EMI Selector Register */ + vu32 WKUPSEL; /* Wake-Up Selection Register */ + u32 EMPTY2[2]; + vu32 GPIOANA; /* GPIO Analag mode Register */ +} SCU_TypeDef; + +/*------------------------- DMA Channelx Registers ---------------------------*/ + +typedef struct +{ + vu32 SRC; /* Channelx Source Address Register */ + vu32 DES; /* Channelx Destination Address Register */ + vu32 LLI; /* Channelx Lincked List Item Register */ + vu32 CC; /* Channelx Contol Register */ + vu32 CCNF; /* Channelx Configuration Register */ +} DMA_Channel_TypeDef; + +/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */ + +/*----------------------------- DMA Controller -------------------------------*/ + +typedef struct +{ + vu32 ISR; /* Interrupt Status Register */ + vu32 TCISR; /* Terminal Count Interrupt Status Register */ + vu32 TCICR; /* Terminal CountInterrupt Clear Register */ + vu32 EISR; /* Error Interrupt Status Register */ + vu32 EICR; /* Error Interrupt Clear Register */ + vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */ + vu32 ERISR; /* Raw Error Interrupt Status Register */ + vu32 ENCSR; /* Enabled Channel Status Register */ + vu32 SBRR; /* Software Burst Request Register */ + vu32 SSRR; /* Software Single Request Register */ + vu32 SLBRR; /* Software Last Burst Request Register */ + vu32 SLSRR; /* Software Last Single Request Register */ + vu32 CNFR; /* Configuration Register */ + vu32 SYNR; /* Syncronization Register */ + } DMA_TypeDef; + +/*--------------------------------- TIM Timer --------------------------------*/ + +typedef struct +{ + vu16 IC1R; /* Input Capture 1 Register */ + vu16 EMPTY1; + vu16 IC2R; /* Input Capture 2 Register */ + vu16 EMPTY2; + vu16 OC1R; /* Output Compare 1 Register */ + vu16 EMPTY3; + vu16 OC2R; /* Output Compare 2 Register */ + vu16 EMPTY4; + vu16 CNTR; /* Counter Register */ + vu16 EMPTY5; + vu16 CR1; /* Control Register 1 */ + vu16 EMPTY6; + vu16 CR2; /* Control Register 2 */ + vu16 EMPTY7; + vu16 SR; /* Status Register */ + vu16 EMPTY8; +} TIM_TypeDef; + +/*---------------------------- EMI Bankx Registers ---------------------------*/ + +typedef struct +{ + vu32 ICR; /* Bankx Idle Cycle Control Register */ + vu32 RCR; /* Bankx Read Wait State Control Register */ + vu32 WCR; /* Bankx Write Wait State Control Register */ + vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */ + vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */ + vu32 BCR; /* Bankx Control Register */ + } EMI_Bank_TypeDef; + +/*---------------------------- Ethernet Controller ---------------------------*/ + +/* MAC Registers */ +typedef struct +{ + vu32 MCR; /* ENET Control Register */ + vu32 MAH; /* ENET Address High Register */ + vu32 MAL; /* ENET Address Low Register */ + vu32 MCHA; /* Multicast Address High Register */ + vu32 MCLA; /* Multicast Address Low Register */ + vu32 MIIA; /* MII Address Register */ + vu32 MIID; /* MII Data Register */ + vu32 MCF; /* ENET Control Frame Register */ + vu32 VL1; /* VLAN1 Register */ + vu32 VL2; /* VLAN2 register */ + vu32 MTS; /* ENET Transmission Status Register */ + vu32 MRS; /* ENET Reception Status Register */ +} ENET_MAC_TypeDef; + +/* DMA Registers */ +typedef struct +{ + vu32 SCR; /* DMA Status and Control Register */ + vu32 IER; /* DMA Interrupt Sources Enable Register */ + vu32 ISR; /* DMA Interrupt Status Register */ + vu32 CCR; /* Clock Control Relation : HCLK, PCLK and + ENET_CLK phase relations */ + vu32 RXSTR; /* Rx DMA start Register */ + vu32 RXCR; /* Rx DMA Control Register */ + vu32 RXSAR; /* Rx DMA Base Address Register */ + vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */ + vu32 RXCAR; /* Rx DMA Current Address Register */ + vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */ + vu32 RXTOR; /* Rx DMA FIFO Time Out Register */ + vu32 RXSR; /* Rx DMA FIFO Status Register */ + vu32 TXSTR; /* Tx DMA start Register */ + vu32 TXCR; /* Tx DMA Control Register */ + vu32 TXSAR; /* Tx DMA Base Address Register */ + vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */ + vu32 TXCAR; /* Tx DMA Current Address Register */ + vu32 TXTCR; /* Tx DMA Current Transfer Count Register */ + vu32 TXTOR; /* Tx DMA FIFO Time Out Register */ + vu32 TXSR; /* Tx DMA FIFO Status Register */ +} ENET_DMA_TypeDef; + +/*------------------------------------- GPIO ---------------------------------*/ + +typedef struct +{ + vu8 DR[1021]; /* Data Register */ + vu32 DDR; /* Data Direction Register */ +} GPIO_TypeDef; + +/*-------------------------------- I2C interface -----------------------------*/ + +typedef struct +{ + vu8 CR; /* Control Register */ + vu8 EMPTY1[3]; + vu8 SR1; /* Status Register 1 */ + vu8 EMPTY2[3]; + vu8 SR2; /* Status Register 2 */ + vu8 EMPTY3[3]; + vu8 CCR; /* Clock Control Register */ + vu8 EMPTY4[3]; + vu8 OAR1; /* Own Address Register 1 */ + vu8 EMPTY5[3]; + vu8 OAR2; /* Own Address Register 2 */ + vu8 EMPTY6[3]; + vu8 DR; /* Data Register */ + vu8 EMPTY7[3]; + vu8 ECCR; /* Extended Clock Control Register */ + vu8 EMPTY8[3]; +} I2C_TypeDef; + +/*------------------------------------- VIC ----------------------------------*/ + +typedef struct +{ + vu32 ISR; /* IRQ Status Register */ + vu32 FSR; /* FIQ Status Register */ + vu32 RINTSR; /* Raw Interrupt Status Register */ + vu32 INTSR; /* Interrupt Select Register */ + vu32 INTER; /* Interrupt Enable Register */ + vu32 INTECR; /* Interrupt Enable Clear Register */ + vu32 SWINTR; /* Software Interrupt Register */ + vu32 SWINTCR; /* Software Interrupt clear Register */ + vu32 PER; /* Protection Enable Register */ + vu32 EMPTY1[3]; + vu32 VAR; /* Vector Address Register */ + vu32 DVAR; /* Default Vector Address Register */ + vu32 EMPTY2[50]; + vu32 VAiR[16]; /* Vector Address 0-15 Register */ + vu32 EMPTY3[48]; + vu32 VCiR[16]; /* Vector Control 0-15 Register */ +} VIC_TypeDef; + +/*-------------------------------- Motor Control -----------------------------*/ + +typedef struct +{ + vu16 TCPT; /* Tacho Capture Register */ + vu16 EMPTY1; + vu16 TCMP; /* Tacho Compare Register */ + vu16 EMPTY2; + vu16 IPR; /* Input Pending Register */ + vu16 EMPTY3; + vu16 TPRS; /* Tacho Prescaler Register */ + vu16 EMPTY4; + vu16 CPRS; /* PWM Counter Prescaler Register */ + vu16 EMPTY5; + vu16 REP; /* Repetition Counter Register */ + vu16 EMPTY6; + vu16 CMPW; /* Compare Phase W Preload Register */ + vu16 EMPTY7; + vu16 CMPV; /* Compare Phase V Preload Register */ + vu16 EMPTY8; + vu16 CMPU; /* Compare Phase U Preload Register */ + vu16 EMPTY9; + vu16 CMP0; /* Compare 0 Preload Register */ + vu16 EMPTY10; + vu16 PCR0; /* Peripheral Control Register 0 */ + vu16 EMPTY11; + vu16 PCR1; /* Peripheral Control Register 1 */ + vu16 EMPTY12; + vu16 PCR2; /* Peripheral Control Register 2 */ + vu16 EMPTY13; + vu16 PSR; /* Polarity Selection Register */ + vu16 EMPTY14; + vu16 OPR; /* Output Peripheral Register */ + vu16 EMPTY15; + vu16 IMR; /* Interrupt Mask Register */ + vu16 EMPTY16; + vu16 DTG; /* Dead Time Generator Register */ + vu16 EMPTY17; + vu16 ESC; /* Emergency Stop Clear Register */ + vu16 EMPTY18; +}MC_TypeDef; + +/*------------------------------------- RTC ----------------------------------*/ + +typedef struct +{ + vu32 TR; /* Time Register */ + vu32 DTR; /* Date Register */ + vu32 ATR; /* Alarm time Register */ + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 MILR; /* Millisec Register */ +}RTC_TypeDef; + +/*------------------------------------- SSP ----------------------------------*/ + +typedef struct +{ + vu16 CR0; /* Control Register 1 */ + vu16 EMPTY1; + vu16 CR1; /* Control Register 2 */ + vu16 EMPTY2; + vu16 DR; /* Data Register */ + vu16 EMPTY3; + vu16 SR; /* Status Register */ + vu16 EMPTY4; + vu16 PR; /* Clock Prescale Register */ + vu16 EMPTY5; + vu16 IMSCR; /* Interrupt Mask Set or Clear Register */ + vu16 EMPTY6; + vu16 RISR; /* Raw Interrupt Status Register */ + vu16 EMPTY7; + vu16 MISR; /* Masked Interrupt Status Register */ + vu16 EMPTY8; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY9; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY10; +}SSP_TypeDef; + +/*------------------------------------ UART ----------------------------------*/ + +typedef struct +{ + vu16 DR; /* Data Register */ + vu16 EMPTY1; + vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */ + vu16 EMPTY2[9]; + vu16 FR; /* Flag Register */ + vu16 EMPTY3[3]; + vu16 ILPR; /* IrDA Low-Power counter Register */ + vu16 EMPTY4; + vu16 IBRD; /* Integer Baud Rate Divisor Register */ + vu16 EMPTY5; + vu16 FBRD; /* Fractional Baud Rate Divisor Register */ + vu16 EMPTY6; + vu16 LCR; /* Line Control Register, High byte */ + vu16 EMPTY7; + vu16 CR; /* Control Register */ + vu16 EMPTY8; + vu16 IFLS; /* Interrupt FIFO Level Select Register */ + vu16 EMPTY9; + vu16 IMSC; /* Interrupt Mask Set/Clear Register */ + vu16 EMPTY10; + vu16 RIS; /* Raw Interrupt Status Register */ + vu16 EMPTY11; + vu16 MIS; /* Masked Interrupt Status Register */ + vu16 EMPTY12; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY13; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY14; +}UART_TypeDef; + +/*------------------------------- Wake-up System -----------------------------*/ + +typedef struct +{ + vu32 CTRL; /* Control Register */ + vu32 MR; /* Mask Register */ + vu32 TR; /* Trigger Register */ + vu32 PR; /* Pending Register */ + vu32 INTR; /* Software Interrupt Register */ +} WIU_TypeDef; + +/*------------------------------- WatchDog Timer -----------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 PR; /* Presclar Register */ + vu16 EMPTY2; + vu16 VR; /* Pre-load Value Register */ + vu16 EMPTY3; + vu16 CNT; /* Counter Register */ + vu16 EMPTY4; + vu16 SR; /* Status Register */ + vu16 EMPTY5; + vu16 MR; /* Mask Register */ + vu16 EMPTY6; + vu16 KR; /* Key Register */ + vu16 EMPTY7; +} WDG_TypeDef; + +/******************************************************************************* +* Memory Mapping of STR91x * +*******************************************************************************/ + +#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */ +#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */ + +#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */ +#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */ + +#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */ +#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */ + +#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */ +#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */ + +#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */ +#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */ + +#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */ +#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */ + +#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */ +#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */ + +#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */ +#define AHB_FMI_B (0x44000000) /* FMI buffered Space */ + +/******************************************************************************* +* Addresses related to the VICs' peripherals * +*******************************************************************************/ + +#define VIC0_BASE (AHB_VIC0_U) +#define VIC1_BASE (AHB_VIC1_U) + +/******************************************************************************* +* Addresses related to the EMI banks * +*******************************************************************************/ + +#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */ +#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */ +#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */ +#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */ + +/******************************************************************************* +* Addresses related to the DMA peripheral * +*******************************************************************************/ + +#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */ +#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */ +#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */ +#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */ +#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */ +#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */ +#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */ +#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */ + +/******************************************************************************* +* Addresses related to the APB0 sub-system * +*******************************************************************************/ + +#define APB_WIU_OFST (0x00001000) /* Offset of WIU */ +#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */ +#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */ +#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */ +#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */ +#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */ +#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */ +#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */ +#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */ +#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */ +#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */ +#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */ +#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */ +#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */ +#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */ + +/******************************************************************************* +* Addresses related to the APB1 sub-system * +*******************************************************************************/ + +#define APB_RTC_OFST (0x00001000) /* Offset of RTC */ +#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */ +#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */ +#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */ +#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */ +#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */ +#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */ +#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */ +#define APB_CAN_OFST (0x00009000) /* Offset of CAN */ +#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */ +#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */ +#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */ +#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */ + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Unbuffered Mode ------------------------------*/ +/*----------------------------------------------------------------------------*/ + +#ifndef Buffered + +/******************************************************************************* +* AHBAPB peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_U) +#define AHBAPB1_BASE (AHB_APB_BRDG1_U) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_U) +#define ENET_DMA_BASE (AHB_ENET_DMA_U) + +/******************************************************************************* +* DMA peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_U) + +/******************************************************************************* +* EMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_U) + +/******************************************************************************* +* FMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_U) + + +#else /* Buffered */ + +/*----------------------------------------------------------------------------*/ +/*------------------------------ Buffered Mode -------------------------------*/ +/*----------------------------------------------------------------------------*/ + +/******************************************************************************* +* AHBAPB peripheral Buffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_B) +#define AHBAPB1_BASE (AHB_APB_BRDG1_B) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_B) +#define ENET_DMA_BASE (AHB_ENET_DMA_B) + +/******************************************************************************* +* DMA peripheral Buffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_B) + +/******************************************************************************* +* EMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_B) + +/******************************************************************************* +* FMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_B) + +#endif /* Buffered */ + +/******************************************************************************* +* DMA channels Base Address * +*******************************************************************************/ +#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST) +#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST) +#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST) +#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST) +#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST) +#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST) +#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST) +#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST) + +/******************************************************************************* +* EMI Banks peripheral Base Address * +*******************************************************************************/ + +#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST) +#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST) +#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST) +#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST) + +/******************************************************************************* +* APB0 Peripherals' Base addresses * +*******************************************************************************/ + +#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST) +#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST) +#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST) +#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST) +#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST) +#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST) +#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST) +#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST) +#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST) +#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST) +#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST) +#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST) +#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST) +#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST) +#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST) + +/******************************************************************************* +* APB1 Peripherals' Base addresses * +*******************************************************************************/ + +#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST) +#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST) +#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST) +#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST) +#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST) +#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST) +#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST) +#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST) +#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST) +#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST) +#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST) +#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST) +#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST) + +/******************************************************************************* +* IPs' declaration * +*******************************************************************************/ + +/*------------------------------ Non Debug Mode ------------------------------*/ +#undef DEBUG +#ifndef DEBUG + +/*********************************** AHBAPB ***********************************/ + +#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE) +#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE) + +/************************************* EMI ************************************/ + +#define EMI ((EMI_TypeDef *)EMI_BASE) + +/************************************* DMA ************************************/ + +#define DMA ((DMA_TypeDef *)DMA_BASE) +#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) +#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) +#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) +#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) +#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) +#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE) +#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE) +#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE) + +/************************************* EMI ************************************/ + +#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE) +#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE) +#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE) +#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE) + +/************************************* ENET_MAC ************************************/ + +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) + +/************************************* ENET_DMA ************************************/ + +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +/************************************* FMI ************************************/ + +#define FMI ((FMI_TypeDef *)FMI_BASE) + +/************************************* VIC ************************************/ + +#define VIC0 ((VIC_TypeDef *)VIC0_BASE) +#define VIC1 ((VIC_TypeDef *)VIC1_BASE) + +/******************************************************************************* +* APB0 Peripherals' * +*******************************************************************************/ +#define WIU ((WIU_TypeDef *)WIU_BASE) +#define TIM0 ((TIM_TypeDef *)TIM0_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) +#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) +#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) +#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE) +#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE) +#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE) +#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE) +#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE) +#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE) +#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE) +/******************************************************************************* +* APB1 Peripherals' * +*******************************************************************************/ +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define SCU ((SCU_TypeDef *)SCU_BASE) +#define MC ((MC_TypeDef *)MC_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define SSP0 ((SSP_TypeDef *)SSP0_BASE) +#define SSP1 ((SSP_TypeDef *)SSP1_BASE) +#define CAN ((CAN_TypeDef *)CAN_BASE) +#define ADC ((ADC_TypeDef *)ADC_BASE) +#define WDG ((WDG_TypeDef *)WDG_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +#else /* DEBUG */ + +/*-------------------------------- Debug Mode --------------------------------*/ + +EXT AHBAPB_TypeDef *AHBAPB0; +EXT AHBAPB_TypeDef *AHBAPB1; +EXT DMA_TypeDef *DMA; +EXT DMA_Channel_TypeDef *DMA_Channel0; +EXT DMA_Channel_TypeDef *DMA_Channel1; +EXT DMA_Channel_TypeDef *DMA_Channel2; +EXT DMA_Channel_TypeDef *DMA_Channel3; +EXT DMA_Channel_TypeDef *DMA_Channel4; +EXT DMA_Channel_TypeDef *DMA_Channel5; +EXT DMA_Channel_TypeDef *DMA_Channel6; +EXT DMA_Channel_TypeDef *DMA_Channel7; +EXT EMI_Bank_TypeDef *EMI_Bank0; +EXT EMI_Bank_TypeDef *EMI_Bank1; +EXT EMI_Bank_TypeDef *EMI_Bank2; +EXT EMI_Bank_TypeDef *EMI_Bank3; +EXT FMI_TypeDef *FMI; +EXT VIC_TypeDef *VIC0; +EXT VIC_TypeDef *VIC1; +EXT WIU_TypeDef *WIU; +EXT TIM_TypeDef *TIM0; +EXT TIM_TypeDef *TIM1; +EXT TIM_TypeDef *TIM2; +EXT TIM_TypeDef *TIM3; +EXT GPIO_TypeDef *GPIO0; +EXT GPIO_TypeDef *GPIO1; +EXT GPIO_TypeDef *GPIO2; +EXT GPIO_TypeDef *GPIO3; +EXT GPIO_TypeDef *GPIO4; +EXT GPIO_TypeDef *GPIO5; +EXT GPIO_TypeDef *GPIO6; +EXT GPIO_TypeDef *GPIO7; +EXT GPIO_TypeDef *GPIO8; +EXT GPIO_TypeDef *GPIO9; +EXT RTC_TypeDef *RTC; +EXT SCU_TypeDef *SCU; +EXT MC_TypeDef *MC; +EXT UART_TypeDef *UART0; +EXT UART_TypeDef *UART1; +EXT UART_TypeDef *UART2; +EXT SSP_TypeDef *SSP0; +EXT SSP_TypeDef *SSP1; +EXT CAN_TypeDef *CAN; +EXT ADC_TypeDef *ADC; +EXT WDG_TypeDef *WDG; +EXT I2C_TypeDef *I2C0; +EXT I2C_TypeDef *I2C1; +EXT ENET_MAC_TypeDef *ENET_MAC; +EXT ENET_DMA_TypeDef *ENET_DMA; + + +#endif /* DEBUG */ + +#endif /* __91x_MAP_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_mc.h b/uc_str912/prj_blinky_complex_startup/include/91x_mc.h new file mode 100644 index 0000000..b33b7c3 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_mc.h @@ -0,0 +1,144 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_mc.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* MC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_MC_H +#define __91x_MC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u16 MC_OperatingMode; + u16 MC_TachoMode; + u16 MC_TachoEvent_Mode; + u8 MC_Prescaler; + u8 MC_ForcedPWMState; + u16 MC_TachoPrescaler; + u16 MC_PWMMode; + u16 MC_Complementary; + u16 MC_Emergency; + u16 MC_Period; + u16 MC_TachoPeriod; + u16 MC_Channel; + u16 MC_PulseU; + u16 MC_PulseV; + u16 MC_PulseW; + u16 MC_PolarityUL; + u16 MC_PolarityUH; + u16 MC_PolarityVL; + u16 MC_PolarityVH; + u16 MC_PolarityWL; + u16 MC_PolarityWH; + u16 MC_TachoPolarity; + u16 MC_DeadTime; + u8 MC_RepetitionCounter; +} MC_InitTypeDef; + +typedef enum { DOWN = 0, UP = !DOWN} CountingStatus; + +/* Exported constants --------------------------------------------------------*/ +#define MC_Complementary_Enable 0x0001 +#define MC_Complementary_Disable 0x0002 + +#define MC_HardwareOperating_Mode 0x0001 +#define MC_SoftwareOperating_Mode 0x0002 + +#define MC_PWMClassical_Mode 0x0001 +#define MC_PWMZeroCentered_Mode 0x0002 + +#define MC_Emergency_Enable 0x0001 +#define MC_Emergency_Disable 0x0002 + +#define MC_Polarity_Inverted 0x0001 +#define MC_Polarity_NonInverted 0x0002 + +#define MC_TachoOneShot_Mode 0x0001 +#define MC_TachoContinuous_Mode 0x0002 + +#define MC_TachoEventEdge_None 0x0000 +#define MC_TachoEventEdge_Falling 0x0001 +#define MC_TachoEventEdge_Rising 0x0002 +#define MC_TachoEventEdge_RisingFalling 0x0003 + +#define MC_Channel_U 0x0001 +#define MC_Channel_V 0x0002 +#define MC_Channel_W 0x0003 +#define MC_Channel_ALL 0x0004 + + +#define MC_TachoEvent_Hardware_Mode 0x0001 +#define MC_TachoEvent_Software_Mode 0x0002 + +#define MC_IT_CMPW 0x0001 +#define MC_IT_CMPV 0x0002 +#define MC_IT_CMPU 0x0004 +#define MC_IT_ZPC 0x0008 +#define MC_IT_ADT 0x0010 +#define MC_IT_OTC 0x0020 +#define MC_IT_CPT 0x0040 +#define MC_IT_CM0 0x0080 + +#define MC_FLAG_CMPW 0x0001 +#define MC_FLAG_CMPV 0x0002 +#define MC_FLAG_CMPU 0x0004 +#define MC_FLAG_ZPC 0x0008 +#define MC_FLAG_ADT 0x0010 +#define MC_FLAG_OTC 0x0020 +#define MC_FLAG_CPT 0x0040 +#define MC_FLAG_CM0 0x0080 +#define MC_FLAG_EST 0x0100 +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void MC_Init(MC_InitTypeDef* MC_InitStruct); +void MC_DeInit(void); +void MC_StructInit(MC_InitTypeDef* MC_InitStruct); +void MC_Cmd(FunctionalState NewState); +void MC_CtrlPWMOutputs(FunctionalState Newstate); +void MC_ITConfig(u16 MC_IT, FunctionalState NewState); +void MC_SetPrescaler(u8 Prescaler); +void MC_SetPeriod(u16 MC_Period); +void MC_SetPulseU(u16 MC_PulseU); +void MC_SetPulseV(u16 MC_PulseV); +void MC_SetPulseW(u16 MC_PulseW); +void MC_SetTachoCompare(u8 MC_Compare); +void MC_PWMModeConfig(u16 MC_PWMMode); +void MC_SetDeadTime(u16 MC_DeadTime); +void MC_EmergencyCmd(FunctionalState NewState); +void MC_EmergencyClear(void); +u16 MC_GetPeriod(void); +u16 MC_GetPulseU(void); +u16 MC_GetPulseV(void); +u16 MC_GetPulseW(void); +u16 MC_GetTachoCapture(void); +void MC_ClearOnTachoCapture(FunctionalState NewState); +void MC_ForceDataTransfer(u8 MC_ForcedData); +void MC_SoftwarePreloadConfig(void); +void MC_SoftwareTachoCapture(void); +CountingStatus MC_GetCountingStatus(void); +FlagStatus MC_GetFlagStatus(u16 MC_FLAG); +void MC_ClearFlag(u16 MC_FLAG); +ITStatus MC_GetITStatus(u16 MC_IT); +void MC_ClearITPendingBit(u16 MC_IT); + +#endif /* __91x_MC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_rtc.h b/uc_str912/prj_blinky_complex_startup/include/91x_rtc.h new file mode 100644 index 0000000..25a2805 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_rtc.h @@ -0,0 +1,109 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_rtc.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the RTC library software functions +* prototypes & definitions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_RTC_H +#define __91x_RTC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Private typedef -----------------------------------------------------------*/ +typedef struct +{ + u8 century; + u8 year; + u8 month; + u8 day; + u8 weekday; +}RTC_DATE; + +typedef struct +{ + u8 hours; + u8 minutes; + u8 seconds; + u16 milliseconds; +}RTC_TIME; + +typedef struct +{ + u8 day; + u8 hours; + u8 minutes; + u8 seconds; +}RTC_ALARM; + +/* Exported constants --------------------------------------------------------*/ + +#define BINARY 0 +#define BCD 1 + +/*TamperMode*/ +#define RTC_TamperMode_Edge 0xFFFFFFEF +#define RTC_TamperMode_Level 0x10 + +/*TamperPol*/ +#define RTC_TamperPol_High 0x4 +#define RTC_TamperPol_Low 0xFFFFFFFB + +/*PeriodicClock*/ +#define RTC_Per_2Hz 0x10000 +#define RTC_Per_16Hz 0x20000 +#define RTC_Per_128Hz 0x40000 +#define RTC_Per_1024Hz 0x80000 +#define RTC_Per_DISABLE 0x0 + +/*RTC_IT*/ +#define RTC_IT_Per 0x200000 +#define RTC_IT_Alarm 0x800000 +#define RTC_IT_Tamper 0x400000 + +/*RTC_FLAG*/ +#define RTC_FLAG_Per 0x80000000 +#define RTC_FLAG_Alarm 0x40000000 +#define RTC_FLAG_Tamper 0x10000000 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RTC_DeInit(void); +void RTC_SetDate(RTC_DATE Date); +void RTC_SetTime(RTC_TIME Time); +void RTC_SetAlarm(RTC_ALARM Alarm); +void RTC_GetDate(u8 Format, RTC_DATE * Date); +void RTC_GetTime(u8 Format, RTC_TIME * Time); +void RTC_GetAlarm(u8 Format, RTC_ALARM * Alarm); +void RTC_TamperConfig(u32 TamperMode, u32 TamperPol); +void RTC_TamperCmd(FunctionalState NewState); +void RTC_AlarmCmd(FunctionalState NewState); +void RTC_CalibClockCmd(FunctionalState NewState); +void RTC_SRAMBattPowerCmd(FunctionalState NewState); +void RTC_PeriodicIntConfig(u32 PeriodicClock); +void RTC_ITConfig(u32 RTC_IT, FunctionalState NewState); +FlagStatus RTC_GetFlagStatus(u32 RTC_FLAG); +void RTC_ClearFlag(u32 RTC_FLAG); +#endif /*__91x_RTC_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + + + diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_scu.h b/uc_str912/prj_blinky_complex_startup/include/91x_scu.h new file mode 100644 index 0000000..b9d04f5 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_scu.h @@ -0,0 +1,196 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +* prototypes & definitions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_SCU_H +#define __91x_SCU_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported constants --------------------------------------------------------*/ + +/*MCLK_Source*/ +#define SCU_MCLK_PLL 0x0 +#define SCU_MCLK_RTC 0x1 +#define SCU_MCLK_OSC 0x2 + +/*RCLK_Divisor*/ +#define SCU_RCLK_Div1 0xFFFFFFE3 +#define SCU_RCLK_Div2 0x4 +#define SCU_RCLK_Div4 0x8 +#define SCU_RCLK_Div8 0xC +#define SCU_RCLK_Div16 0x10 +#define SCU_RCLK_Div1024 0x14 + +/*HCLK_Divisor*/ +#define SCU_HCLK_Div1 0xFFFFFF9F +#define SCU_HCLK_Div2 0x20 +#define SCU_HCLK_Div4 0x40 + +/*PCLK_Divisor*/ +#define SCU_PCLK_Div1 0xFFFFFE7F +#define SCU_PCLK_Div2 0x80 +#define SCU_PCLK_Div4 0x100 +#define SCU_PCLK_Div8 0x180 + +/*FMICLK_Divisor*/ +#define SCU_FMICLK_Div1 0xFFFEFFFF +#define SCU_FMICLK_Div2 0x10000 + +/*BRCLK_Divisor*/ +#define SCU_BRCLK_Div1 0xFFFFFDFF +#define SCU_BRCLK_Div2 0x200 + +/*TIMCLK_Source*/ +#define SCU_TIMCLK_EXT 0x1 +#define SCU_TIMCLK_INT 0x0 + +/*TIMx*/ +#define SCU_TIM01 0x0 +#define SCU_TIM23 0x1 + + +/*USBCLK_Source*/ +#define SCU_USBCLK_MCLK 0xFFFFF3FF +#define SCU_USBCLK_MCLK2 0x400 +#define SCU_USBCLK_EXT 0x800 + +/*SCU_EMIBCLK*/ +#define SCU_EMIBCLK_Div1 0xFFF9FFFF +#define SCU_EMIBCLK_Div2 0x20000 + +/*SCU_EMIMODE*/ +#define SCU_EMI_MUX 0xFFFFFFBF +#define SCU_EMI_DEMUX 0x40 + +/*SCU_EMIALE_LEN*/ +#define SCU_EMIALE_LEN1 0xFFFFFEFF +#define SCU_EMIALE_LEN2 0x100 + +/*SCU_EMIALE_POL*/ +#define SCU_EMIALE_POLLow 0xFFFFFF7F +#define SCU_EMIALE_POLHigh 0x80 + +/*UART_IrDA_Mode*/ +#define SCU_UARTMode_IrDA 0x1 +#define SCU_UARTMode_UART 0x0 + +/*APBPeriph*/ +#define __TIM01 0x1 +#define __TIM23 0x2 +#define __MC 0x4 +#define __UART0 0x8 +#define __UART1 0x10 +#define __UART2 0x20 +#define __I2C0 0x40 +#define __I2C1 0x80 +#define __SSP0 0x100 +#define __SSP1 0x200 +#define __CAN 0x400 +#define __ADC 0x800 +#define __WDG 0x1000 +#define __WIU 0x2000 +#define __GPIO0 0x4000 +#define __GPIO1 0x8000 +#define __GPIO2 0x10000 +#define __GPIO3 0x20000 +#define __GPIO4 0x40000 +#define __GPIO5 0x80000 +#define __GPIO6 0x100000 +#define __GPIO7 0x200000 +#define __GPIO8 0x400000 +#define __GPIO9 0x800000 +#define __RTC 0x1000000 + +/*AHBPeriph*/ +#define __FMI 0x1 +#define __FPQBC 0x2 +#define __SRAM 0x8 +#define __SRAM_ARBITER 0x10 +#define __VIC 0x20 +#define __EMI 0x40 +#define __EMI_MEM_CLK 0x80 +#define __DMA 0x100 +#define __USB 0x200 +#define __USB48M 0x400 +#define __ENET 0x800 +#define __PFQBC_AHB 0x1000 + +/*SCU_IT*/ +#define SCU_IT_LVD_RST 0x10 +#define SCU_IT_SRAM_ERROR 0x8 +#define SCU_IT_ACK_PFQBC 0x4 +#define SCU_IT_LOCK_LOST 0x2 +#define SCU_IT_LOCK 0x1 + +/*SCU_FLAG*/ +#define SCU_FLAG_SRAM_ERROR 0x20 +#define SCU_FLAG_ACK_PFQBC 0x10 +#define SCU_FLAG_LVD_RESET 0x8 +#define SCU_FLAG_WDG_RST 0x4 +#define SCU_FLAG_LOCK_LOST 0x2 +#define SCU_FLAG_LOCK 0x1 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source); +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP); +ErrorStatus SCU_PLLCmd(FunctionalState NewState); +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor); +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor); +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor); +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor); +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source); +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler); +void SCU_USBCLKConfig(u32 USBCLK_Source); +void SCU_PHYCLKConfig(FunctionalState NewState); +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor); +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK); +void SCU_EMIModeConfig(u32 SCU_EMIMODE); +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL); +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState); +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag); +void SCU_ClearFlag(u32 SCU_Flag); +u32 SCU_GetPLLFreqValue(void); +u32 SCU_GetMCLKFreqValue(void); +u32 SCU_GetRCLKFreqValue(void); +u32 SCU_GetHCLKFreqValue(void); +u32 SCU_GetPCLKFreqValue(void); +void SCU_WakeUpLineConfig(u8 EXTint); +void SCU_SpecIntRunModeConfig(FunctionalState NewState); +void SCU_EnterIdleMode(void); +void SCU_EnterSleepMode(void); +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode); +void SCU_PFQBCCmd(FunctionalState NewState); + +#endif /*__91x_SCU_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_ssp.h b/uc_str912/prj_blinky_complex_startup/include/91x_ssp.h new file mode 100644 index 0000000..e356d4f --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_ssp.h @@ -0,0 +1,119 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ssp.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* SSP software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_SSP_H +#define __91x_SSP_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* SSP Init structure definition */ +typedef struct +{ + u16 SSP_FrameFormat ; + u16 SSP_Mode ; + u16 SSP_CPOL ; + u16 SSP_CPHA ; + u16 SSP_DataSize ; + u16 SSP_SlaveOutput ; + u8 SSP_ClockRate ; + u8 SSP_ClockPrescaler ; +}SSP_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SSP Frame Format Select */ +#define SSP_FrameFormat_TI 0x0010 +#define SSP_FrameFormat_Motorola 0xFFCF +#define SSP_FrameFormat_Microwire 0x0020 + +/* SSP Master/Slave Select */ +#define SSP_Mode_Master 0xFFFB +#define SSP_Mode_Slave 0x0004 + +/* SSP Clock Polarity */ +#define SSP_CPOL_Low 0xFFBF +#define SSP_CPOL_High 0x0040 + +/* SSP Clock Phase */ +#define SSP_CPHA_1Edge 0xFF7F +#define SSP_CPHA_2Edge 0x0080 + +/* SSP Data Size */ +#define SSP_DataSize_16b 0x000F +#define SSP_DataSize_15b 0x000E +#define SSP_DataSize_14b 0x000D +#define SSP_DataSize_13b 0x000C +#define SSP_DataSize_12b 0x000B +#define SSP_DataSize_11b 0x000A +#define SSP_DataSize_10b 0x0009 +#define SSP_DataSize_9b 0x0008 +#define SSP_DataSize_8b 0x0007 +#define SSP_DataSize_7b 0x0006 +#define SSP_DataSize_6b 0x0005 +#define SSP_DataSize_5b 0x0004 +#define SSP_DataSize_4b 0x0003 + +/* SSP Slave output config */ +#define SSP_SlaveOutput_Enable 0xFFF7 +#define SSP_SlaveOutput_Disable 0x0008 + +/* SSP Interrupts */ +#define SSP_IT_TxFifo 0x0008 +#define SSP_IT_RxFifo 0x0004 +#define SSP_IT_RxTimeOut 0x0002 +#define SSP_IT_RxOverrun 0x0001 + +/* SSP Flags */ +#define SSP_FLAG_Busy 0x0024 +#define SSP_FLAG_RxFifoFull 0x0023 +#define SSP_FLAG_RxFifoNotEmpty 0x0022 +#define SSP_FLAG_TxFifoNotFull 0x0021 +#define SSP_FLAG_TxFifoEmpty 0x0020 +#define SSP_FLAG_TxFifo 0x0043 +#define SSP_FLAG_RxFifo 0x0042 +#define SSP_FLAG_RxTimeOut 0x0041 +#define SSP_FLAG_RxOverrun 0x0040 + +/* SSP DMA Requests */ +#define SSP_DMA_Transmit 0x0002 +#define SSP_DMA_Receive 0x0001 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void SSP_DeInit(SSP_TypeDef* SSPx); +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct); +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct); +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState); +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState); +void SSP_DMACmd(SSP_TypeDef* SSPx, u16 SSP_DMATransfert, FunctionalState NewState); +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data); +u16 SSP_ReceiveData(SSP_TypeDef* SSPx); +void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState); +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG); +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG); +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT); +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT); + +#endif /* __91x_SSP_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_tim.h b/uc_str912/prj_blinky_complex_startup/include/91x_tim.h new file mode 100644 index 0000000..b587c27 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_tim.h @@ -0,0 +1,155 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_tim.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* TIM software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_TIM_H +#define __91x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" +#include "91x_scu.h" + +/* Exported types ----------------------------------------------------------- */ + +/* TIM Init structure define */ +typedef struct +{ + u16 TIM_Mode; /* Timer mode */ + u16 TIM_OC1_Modes; /* Output Compare 1 Mode: Timing or Wave */ + u16 TIM_OC2_Modes; /* Output Compare 2 Mode: Timing or Wave */ + u16 TIM_Clock_Source; /* Timer Clock source APB/SCU/EXTERNAL */ + u16 TIM_Clock_Edge; /* Timer Clock Edge: Rising or Falling Edge */ + u16 TIM_OPM_INPUT_Edge; /* Timer Input Capture 1 Edge used in OPM Mode */ + u16 TIM_ICAP1_Edge; /* Timer Input Capture 1 Edge used in ICAP1 Mode */ + u16 TIM_ICAP2_Edge; /* Timer Input Capture 2 Edge used in ICAP2 Mode */ + u8 TIM_Prescaler; /* Timer Prescaler factor */ + u16 TIM_Pulse_Level_1; /* Level applied on the Output Compare Pin 1 */ + u16 TIM_Pulse_Level_2; /* Level applied on the Output Compare Pin 2 */ + u16 TIM_Period_Level; /* Level applied during the Period of a PWM Mode */ + u16 TIM_Pulse_Length_1; /* Pulse 1 Length used in Output Compare 1 Mode */ + u16 TIM_Pulse_Length_2; /* Pulse 2 Length used in Output Compare 2 Mode */ + u16 TIM_Full_Period; /* Period Length used in PWM Mode */ +} TIM_InitTypeDef; + +typedef enum +{ + TIM_START, + TIM_STOP, + TIM_CLEAR +} TIM_CounterOperations; + +/* Exported constants --------------------------------------------------------*/ + +/* TIM MODE */ +#define TIM_PWMI 0x4000 /* PWM INPUT Mode */ +#define TIM_OCM_CHANNEL_1 0x0040 /* OUTPUT COMPARE CHANNEL 1 Mode */ +#define TIM_OCM_CHANNEL_2 0x0080 /* OUTPUT COMPARE CHANNEL 2 Mode */ +#define TIM_OCM_CHANNEL_12 0x00C0 /* OUTPUT COMPARE CHANNEL 1 & 2 Mode */ +#define TIM_PWM 0x0010 /* PWM Mode */ +#define TIM_OPM 0x0020 /* ONE PULSE Mode */ +#define TIM_ICAP_CHANNEL_1 0x0400 /* INPUT CAPTURE 1 Mode */ +#define TIM_ICAP_CHANNEL_2 0x0500 /* INPUT CAPTURE 2 Mode */ +#define TIM_ICAP_CHANNEL_12 0x0600 /* INPUT CAPTURE 1 & 2 Mode */ + +/* TIM OUTPUT COMPARE MODE */ +#define TIM_WAVE 0x0001 +#define TIM_TIMING 0x0002 + +/* TIM CLOCK SOURCE */ +#define TIM_CLK_APB 0xFFFE +#define TIM_CLK_EXTERNAL 0x0001 +#define TIM_CLK_SCU 0x0001 + +/* TIM CLOCK EDGE */ +#define TIM_CLK_EDGE_FALLING 0xFFFD +#define TIM_CLK_EDGE_RISING 0x0002 + +/* TIM OPM INPUT EDGE */ +#define TIM_OPM_EDGE_FALLING 0xFFFB +#define TIM_OPM_EDGE_RISING 0x0004 + +/* TIM ICAPA INPUT EDGE */ +#define TIM_ICAP1_EDGE_FALLING 0xFFFB +#define TIM_ICAP1_EDGE_RISING 0x0004 + +/* TIM ICAPB INPUT EDGE */ +#define TIM_ICAP2_EDGE_FALLING 0xFFF7 +#define TIM_ICAP2_EDGE_RISING 0x0008 + +/* TIM OUTPUT LEVEL */ +#define TIM_HIGH 0x0200 +#define TIM_LOW 0x0300 + +/* TIM OUTPUT EDGE */ +#define TIM_OUTPUT_EDGE_RISING 0x8000 +#define TIM_OUTPUT_EDGE_FALLING 0x0800 + +/* TIM channels */ +#define TIM_PWM_OC1_Channel 0x1 /* PWM/Output Compare 1 Channel */ +#define TIM_OC2_Channel 0x2 /* Output Compare 2 Channel */ + +/* TIM DMA SOURCE */ +#define TIM_DMA_IC1 0x0000 /* Input Capture Channel 1 DMA Source */ +#define TIM_DMA_OC1 0x1000 /* OUTPUT Compare Channel 1 DMA Source */ +#define TIM_DMA_IC2 0x2000 /* Input Capture Channel 2 DMA Source */ +#define TIM_DMA_OC2 0x3000 /* OUTPUT Compare Channel 2 DMA Source */ + +/* TIM DMA ENABLE or DISABLE */ +#define TIM_DMA_ENABLE 0x0400 /* DMA Enable */ +#define TIM_DMA_DISABLE 0xFBFF /* DMA Disable */ + +/* TIM Interruption Sources*/ +#define TIM_IT_IC1 0x8000 /* Input Capture Channel 1 Interrupt Source */ +#define TIM_IT_OC1 0x4000 /* Output Compare Channel 1 Interrupt Source */ +#define TIM_IT_TO 0x2000 /* Timer OverFlow Interrupt Source */ +#define TIM_IT_IC2 0x1000 /* Input Capture Channel 2 Interrupt Source */ +#define TIM_IT_OC2 0x0800 /* Output Compare Channel 2 Interrupt Source */ + +/* TIM Flags */ +#define TIM_FLAG_IC1 0x8000 /* Input Capture Channel 1 Flag */ +#define TIM_FLAG_OC1 0x4000 /* Output Compare Channel 1 Flag */ +#define TIM_FLAG_TO 0x2000 /* Timer OverFlow Flag */ +#define TIM_FLAG_IC2 0x1000 /* Input Capture Channel 2 Flag */ +#define TIM_FLAG_OC2 0x0800 /* Output Compare Channel 2 Flag */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct); +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); +void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler); +u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx); +u16 TIM_GetCounterValue(TIM_TypeDef *TIMx); +u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx); +u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx); +void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag); +void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag); +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate); +void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources); +void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate); + +#endif /* __91x_TIM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_type.h b/uc_str912/prj_blinky_complex_startup/include/91x_type.h new file mode 100644 index 0000000..916d81c --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_type.h @@ -0,0 +1,50 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_type.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : It contains common types and constants used in all the +* peripherals' drivers. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +#ifndef __91x_type_H +#define __91x_type_H + + typedef long long u64; + typedef unsigned long u32; + typedef unsigned short u16; + typedef unsigned char u8; + + typedef signed long s32; + typedef signed short s16; + typedef signed char s8; + + typedef volatile unsigned long vu32; + typedef volatile unsigned short vu16; + typedef volatile unsigned char vu8; + + typedef volatile signed long vs32; + typedef volatile signed short vs16; + typedef volatile signed char vs8; + +typedef enum { FALSE = 0, TRUE = !FALSE } bool; + +typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; + +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#endif /* __91x_type_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_uart.h b/uc_str912/prj_blinky_complex_startup/include/91x_uart.h new file mode 100644 index 0000000..b979438 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_uart.h @@ -0,0 +1,174 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_uart.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* UART software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_UART_H +#define __91x_UART_H + +/* Includes ------------------------------------------------------------------*/ +#include <91x_map.h> + +/* Exported types ------------------------------------------------------------*/ +/* UART FIFO Level enumeration */ +typedef enum +{ + UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ + UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ + UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ + UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ +}UART_FIFOLevel; + +/* UART Init Structure definition */ +typedef struct +{ + u16 UART_WordLength; + u16 UART_StopBits; + u16 UART_Parity; + u32 UART_BaudRate; + u16 UART_HardwareFlowControl; + u16 UART_Mode; + u16 UART_FIFO; + UART_FIFOLevel UART_TxFIFOLevel; + UART_FIFOLevel UART_RxFIFOLevel; +}UART_InitTypeDef; + + +/* UART RTS enumeration */ +typedef enum +{ + LowLevel = 0, + HighLevel +}UART_LevelTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* UART Data Length */ +#define UART_WordLength_5D 0x0000 /* 5 bits Data */ +#define UART_WordLength_6D 0x0020 /* 6 bits Data */ +#define UART_WordLength_7D 0x0040 /* 7 bits Data */ +#define UART_WordLength_8D 0x0060 /* 8 bits Data */ + +/* UART Stop Bits */ +#define UART_StopBits_1 0xFFF7 /* Disable two stop bit is transmitted + at the end of frame */ +#define UART_StopBits_2 0x0008 /* Enable Two stop bits are transmitted + at the end of frame */ +/* UART Parity */ +#define UART_Parity_No 0x0000 /* Parity Disable */ +#define UART_Parity_Even 0x0006 /* Even Parity */ +#define UART_Parity_Odd 0x0002 /* Odd Parity */ +#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ +#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ + +/* UART Hardware Flow Control */ +#define UART_HardwareFlowControl_None 0x0000 /* HFC Disable */ +#define UART_HardwareFlowControl_RTS 0x4000 /* RTS Enable */ +#define UART_HardwareFlowControl_CTS 0x8000 /* CTS Enable */ +#define UART_HardwareFlowControl_RTS_CTS 0xC000 /* CTS and RTS Enable */ + +/* UART Mode */ +#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ +#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ +#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ + +/* UART FIFO */ +#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ +#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ + +/* UART Interrupt definition */ +#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt mask */ +#define UART_IT_BreakError 0x0200 /* Break Error interrupt mask */ +#define UART_IT_ParityError 0x0100 /* Parity Error interrupt mask */ +#define UART_IT_FrameError 0x0080 /* Frame Error interrupt mask */ +#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt mask */ +#define UART_IT_Transmit 0x0020 /* Transmit interrupt mask */ +#define UART_IT_Receive 0x0010 /* Receive interrupt mask */ +#define UART_IT_DSR 0x0008 /* DSR interrupt mask */ +#define UART_IT_DCD 0x0004 /* DCD interrupt mask */ +#define UART_IT_CTS 0x0002 /* CTS interrupt mask */ +#define UART_IT_RI 0x0001 /* RI interrupt mask */ + +/* UART DMA On Error */ +#define UART_DMAOnError_Enable 0xFFFB /* DMA receive request enabled + when the UART error interrupt + is asserted. */ +#define UART_DMAOnError_Disable 0x0004 /* DMA receive request disabled + when the UART error interrupt + is asserted. */ +/* UART DMA Request */ +#define UART_DMAReq_Tx 0x02 /* Transmit DMA Enable */ +#define UART_DMAReq_Rx 0x01 /* Receive DMA Enable */ + +/* UART FLAG */ +#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ +#define UART_FLAG_Break 0x22 /* break error flag */ +#define UART_FLAG_ParityError 0x21 /* parity error flag */ +#define UART_FLAG_FrameError 0x20 /* frame error flag */ +#define UART_FLAG_RI 0x48 /* RI flag */ +#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ +#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ +#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ +#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ +#define UART_FLAG_Busy 0x43 /* UART Busy flag */ +#define UART_FLAG_DCD 0x42 /* DCD flag */ +#define UART_FLAG_DSR 0x41 /* DSR flag */ +#define UART_FLAG_CTS 0x40 /* CTS flag */ +#define UART_RawIT_OverrunError 0x6A /* Overrun Error Raw IT flag */ +#define UART_RawIT_BreakError 0x69 /* Break Error Raw IT flag */ +#define UART_RawIT_ParityError 0x68 /* Parity Error Raw IT flag */ +#define UART_RawIT_FrameError 0x67 /* Frame Error Raw IT flag */ +#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Raw IT flag */ +#define UART_RawIT_Transmit 0x65 /* Transmit Raw IT flag */ +#define UART_RawIT_Receive 0x64 /* Receive Raw IT flag */ +#define UART_RawIT_DSR 0x63 /* DSR Raw IT flag */ +#define UART_RawIT_DCD 0x62 /* DCD Raw IT flag */ +#define UART_RawIT_CTS 0x61 /* CTS Raw IT flag */ +#define UART_RawIT_RI 0x60 /* RI Raw IT flag */ + +/*IrDAx select*/ +#define IrDA0 0x01 /*IrDA0 select*/ +#define IrDA1 0x02 /*IrDA0 select*/ +#define IrDA2 0x03 /*IrDA0 select*/ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void UART_DeInit(UART_TypeDef* UARTx); +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); +void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError); +void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState); +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); +void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState); +void UART_IrDACmd(u8 IrDAx, FunctionalState NewState); +void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter); +void UART_SendData(UART_TypeDef* UARTx, u8 Data); +u8 UART_ReceiveData(UART_TypeDef* UARTx); +void UART_SendBreak(UART_TypeDef* UARTx); +void UART_DTRConfig(UART_LevelTypeDef LevelState); +void UART_RTSConfig(UART_LevelTypeDef LevelState); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); + +#endif /* __91x_UART_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_vic.h b/uc_str912/prj_blinky_complex_startup/include/91x_vic.h new file mode 100644 index 0000000..127716a --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_vic.h @@ -0,0 +1,94 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_vic.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* VIC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_VIC_H +#define __91x_VIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" +#include "91x_it.h" + +/* Exported types ------------------------------------------------------------*/ +/* Type of interrupt */ +typedef enum +{ + VIC_IRQ, + VIC_FIQ +} VIC_ITLineMode; + +/* Exported constants --------------------------------------------------------*/ + +/* VIC sources*/ + +#define WDG_ITLine 0 +#define SW_ITLine 1 +#define ARMRX_ITLine 2 +#define ARMTX_ITLine 3 +#define TIM0_ITLine 4 +#define TIM1_ITLine 5 +#define TIM2_ITLine 6 +#define TIM3_ITLine 7 +#define USBHP_ITLine 8 +#define USBLP_ITLine 9 +#define SCU_ITLine 10 +#define ENET_ITLine 11 +#define DMA_ITLine 12 +#define CAN_ITLine 13 +#define MC_ITLine 14 +#define ADC_ITLine 15 +#define UART0_ITLine 16 +#define UART1_ITLine 17 +#define UART2_ITLine 18 +#define I2C0_ITLine 19 +#define I2C1_ITLine 20 +#define SSP0_ITLine 21 +#define SSP1_ITLine 22 +#define LVD_ITLine 23 +#define RTC_ITLine 24 +#define WIU_ITLine 25 +#define EXTIT0_ITLine 26 +#define EXTIT1_ITLine 27 +#define EXTIT2_ITLine 28 +#define EXTIT3_ITLine 29 +#define USBWU_ITLine 30 +#define PFQBC_ITLine 31 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void VIC_DeInit(void); +FlagStatus VIC_GetIRQStatus(u16 VIC_Source); +FlagStatus VIC_GetFIQStatus(u16 VIC_Source); +FlagStatus VIC_GetSourceITStatus(u16 VIC_Source); +void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState); +void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState); +void VIC_ProtectionCmd(FunctionalState VIC_NewState); +u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx); +u32 VIC_GetISRVectAdd(u16 VIC_Source); +void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority); + +#endif /* __91x_VIC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_wdg.h b/uc_str912/prj_blinky_complex_startup/include/91x_wdg.h new file mode 100644 index 0000000..fc70547 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_wdg.h @@ -0,0 +1,82 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wdg.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* WDG software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_WDG_H +#define __91x_WDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ +u16 WDG_Mode; +u16 WDG_ClockSource; +u16 WDG_Prescaler; +u16 WDG_Preload; + +} WDG_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/* WDG_Mode */ +#define WDG_Mode_Wdg 0x0001 /*WDG configured to run in watchdog mode.*/ +#define WDG_Mode_Timer 0xFFFE /*WDG configured to be in Free-running Timer mode.*/ + + +/* WDG_ClockSource */ +#define WDG_ClockSource_Rtc 0x0004 /* External clock ( 32 khz RTC clock ) will be used as counting clock.*/ +#define WDG_ClockSource_Apb 0xFFFB /*The APB clock signal will be used as counting clock.*/ + +/* WDG_Prescaler */ +/*This member must be a number between 0x00 and 0xFF. +Specifies the Prescaler value to divide the clock source. +The clock of the Watchdog Timer Counter is divided by " WDG_Prescaler + 1".*/ + + + +/* WDG_Preload */ +/*This member must be a number between 0x0000 and 0xFFFF. +This value is loaded in the WDG Counter when it starts counting.*/ + + +/* WDG Sequence */ +#define WDG_KeyValue1 0xA55A +#define WDG_KeyValue2 0x5AA5 + +/* Exported macro ------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ + +void WDG_DeInit(void); +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); +void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); +void WDG_Cmd(FunctionalState NewState); +void WDG_ITConfig(FunctionalState NewState); +u16 WDG_GetCounter(void); +FlagStatus WDG_GetFlagStatus(void); +void WDG_ClearFlag(void); +ITStatus WDG_GetITStatus(void); +void WDG_ClearITPendingBit(void); + +#endif /* __WDG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/include/91x_wiu.h b/uc_str912/prj_blinky_complex_startup/include/91x_wiu.h new file mode 100644 index 0000000..8b0349c --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/91x_wiu.h @@ -0,0 +1,99 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wiu.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* WIU software library. +********************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_WIU_H +#define __91x_WIU_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* WIU Init structure type define */ +typedef struct +{ + u8 WIU_Mode ; + u8 WIU_TriggerEdge; + u32 WIU_Line ; +}WIU_InitTypeDef ; + +/* Exported constants --------------------------------------------------------*/ +/* Wake-up line triggering edge */ +#define WIU_FallingEdge 0x00 +#define WIU_RisingEdge 0x01 + +/* Wake-up unit modes */ +#define WIU_Mode_WakeUp 0x01 +#define WIU_Mode_Interrupt 0x02 +#define WIU_Mode_WakeUpInterrupt 0x03 +#define WIU_Mode_SWInterrupt 0x04 + +/* Wake-up lines*/ +#define WIU_Line0 0x0001 +#define WIU_Line1 (WIU_Line0<<1) +#define WIU_Line2 (WIU_Line1<<1) +#define WIU_Line3 (WIU_Line2<<1) +#define WIU_Line4 (WIU_Line3<<1) +#define WIU_Line5 (WIU_Line4<<1) +#define WIU_Line6 (WIU_Line5<<1) +#define WIU_Line7 (WIU_Line6<<1) +#define WIU_Line8 (WIU_Line7<<1) +#define WIU_Line9 (WIU_Line8<<1) +#define WIU_Line10 (WIU_Line9<<1) +#define WIU_Line11 (WIU_Line10<<1) +#define WIU_Line12 (WIU_Line11<<1) +#define WIU_Line13 (WIU_Line12<<1) +#define WIU_Line14 (WIU_Line13<<1) +#define WIU_Line15 (WIU_Line14<<1) +#define WIU_Line16 (WIU_Line15<<1) +#define WIU_Line17 (WIU_Line16<<1) +#define WIU_Line18 (WIU_Line17<<1) +#define WIU_Line19 (WIU_Line18<<1) +#define WIU_Line20 (WIU_Line19<<1) +#define WIU_Line21 (WIU_Line20<<1) +#define WIU_Line22 (WIU_Line21<<1) +#define WIU_Line23 (WIU_Line22<<1) +#define WIU_Line24 (WIU_Line23<<1) +#define WIU_Line25 (WIU_Line24<<1) +#define WIU_Line26 (WIU_Line25<<1) +#define WIU_Line27 (WIU_Line26<<1) +#define WIU_Line28 (WIU_Line27<<1) +#define WIU_Line29 (WIU_Line28<<1) +#define WIU_Line30 (WIU_Line29<<1) +#define WIU_Line31 (WIU_Line30<<1) + +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void WIU_DeInit(void); +void WIU_StructInit(WIU_InitTypeDef* WIU_InitStruct); +void WIU_Init(WIU_InitTypeDef* WIU_InitStruct); +void WIU_GenerateSWInterrupt(u32 WIU_Line); +FlagStatus WIU_GetFlagStatus(u32 WIU_Line); +void WIU_ClearFlag(u32 WIU_Line); +ITStatus WIU_GetITStatus(u32 WIU_Line); +void WIU_ClearITPendingBit(u32 WIU_Line); + +#endif /* __91x_WIU_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_complex_startup/include/usb_core.h b/uc_str912/prj_blinky_complex_startup/include/usb_core.h new file mode 100644 index 0000000..72feb08 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/usb_core.h @@ -0,0 +1,145 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_core.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : USB state machine structures and functions prototypes +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#define Type_Recipient (pInfo->USBbmRequestType & (REQUEST_TYPE | RECIPIENT)) + +#define STD_MAXPACKETSIZE 0x40 /* 64 bytes*/ + +typedef enum _CONTROL_STATE { + WAIT_SETUP, + SETTING_UP, + IN_DATA, + OUT_DATA, + LAST_IN_DATA, + LAST_OUT_DATA, + WAIT_STATUS_IN, + WAIT_STATUS_OUT, + STALLED, + PAUSE +} CONTROL_STATE; /* The state machine states of a control pipe */ + + +typedef struct OneDescriptor { + BYTE *Descriptor; + WORD Descriptor_Size; +} ONE_DESCRIPTOR, *PONE_DESCRIPTOR; + + +typedef enum _RESULT { + USB_SUCCESS = 0, /* Process sucessfully */ + USB_ERROR, + UNSUPPORT, + NOT_READY /* The process has not been finished, */ + /* endpoint will be NAK to further rquest */ +} RESULT; + + +/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/ + +typedef struct _ENDPOINT_INFO { + WORD Usb_wLength; + WORD Usb_wOffset; + WORD PacketSize; + BYTE *(*CopyData)(WORD Length); +} ENDPOINT_INFO; + +#define Usb_rLength Usb_wLength +#define Usb_rOffset Usb_wOffset + + +/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/ + +typedef struct _DEVICE { + BYTE Total_Endpoint; /* Number of endpoints that are used */ + BYTE Total_Configuration;/* Number of configuration available */ +} DEVICE; + +typedef union { + WORD w; + struct BW { + BYTE bb1; + BYTE bb0; + } bw; +} WORD_BYTE; + +typedef struct _DEVICE_INFO { + BYTE USBbmRequestType; /* bmRequestType */ + BYTE USBbRequest; /* bRequest */ + WORD_BYTE USBwValues; /* wValue */ + WORD_BYTE USBwIndexs; /* wIndex */ + WORD_BYTE USBwLengths; /* wLength */ + + BYTE ControlState; /* of type CONTROL_STATE */ + BYTE Current_Feature; /*selected features*/ + + BYTE Current_Configuration; /* Selected configuration */ + BYTE Current_Interface; /* Selected interface of current configuration */ + BYTE Current_AlternateSetting;/* Selected Alternate Setting of current interface*/ + ENDPOINT_INFO Ctrl_Info; +} DEVICE_INFO; + +typedef struct _DEVICE_PROP { + void (*Init)(void); + void (*Reset)(void); + void (*Process_Status_IN)(void); + void (*Process_Status_OUT)(void); + RESULT (*Class_Data_Setup)(BYTE RequestNo); + RESULT (*Class_NoData_Setup)(BYTE RequestNo); + RESULT (*Class_Get_Interface_Setting)(BYTE Interface,BYTE AlternateSetting); + BYTE* (*GetDeviceDescriptor)(WORD Length); + BYTE* (*GetConfigDescriptor)(WORD Length); + BYTE* (*GetStringDescriptor)(WORD Length); + BYTE* RxEP_buffer; + WORD MaxPacketSize; +} DEVICE_PROP; + +extern DEVICE_PROP Device_Property; +extern DEVICE Device_Table; +extern DEVICE_INFO Device_Info; + +/* cells saving status during interrupt servicing */ +extern WORD SaveRState; +extern WORD SaveTState; + +#define USBwValue USBwValues.w +#define USBwValue0 USBwValues.bw.bb0 +#define USBwValue1 USBwValues.bw.bb1 +#define USBwIndex USBwIndexs.w +#define USBwIndex0 USBwIndexs.bw.bb0 +#define USBwIndex1 USBwIndexs.bw.bb1 +#define USBwLength USBwLengths.w +#define USBwLength0 USBwLengths.bw.bb0 +#define USBwLength1 USBwLengths.bw.bb1 + +BYTE Setup0_Process(void); +BYTE Post0_Process(void); +BYTE Out0_Process(void); +BYTE In0_Process(void); + +RESULT Standard_SetEndPointFeature(void); +RESULT Standard_SetDeviceFeature(void); + +BYTE *Standard_GetConfiguration(WORD Length); +RESULT Standard_SetConfiguration(void); +BYTE *Standard_GetInterface(WORD Length); +RESULT Standard_SetInterface(void); +BYTE *Standard_GetDescriptorData(WORD Length, PONE_DESCRIPTOR pDesc); +BYTE *Standard_GetStringDescriptor(WORD Length, PONE_DESCRIPTOR pDesc); + +void SetDeviceAddress(BYTE); +void NOP_Process(void); + diff --git a/uc_str912/prj_blinky_complex_startup/include/usb_def.h b/uc_str912/prj_blinky_complex_startup/include/usb_def.h new file mode 100644 index 0000000..7b69666 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/usb_def.h @@ -0,0 +1,68 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_def.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : definitions related to usb +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Definition of "USBbmRequestType" */ +#define REQUEST_TYPE 0x60 /* Mask to get request type */ +#define STANDARD_REQUEST 0x00 /* Standard request */ +#define CLASS_REQUEST 0x20 /* Class request */ +#define VENDOR_REQUEST 0x40 /* Vendor request */ + +#define RECIPIENT 0x1F /* Mask to get recipient */ + +typedef enum _RECIPIENT_TYPE { + DEVICE_RECIPIENT, /* Recipient device */ + INTERFACE_RECIPIENT, /* Recipient interface */ + ENDPOINT_RECIPIENT, /* Recipient endpoint */ + OTHER_RECIPIENT +} RECIPIENT_TYPE; + + +typedef enum _STANDARD_REQUESTS { + GET_STATUS = 0, + CLEAR_FEATURE, + RESERVED1, + SET_FEATURE, + RESERVED2, + SET_ADDRESS, + GET_DESCRIPTOR, + SET_DESCRIPTOR, + GET_CONFIGURATION, + SET_CONFIGURATION, + GET_INTERFACE, + SET_INTERFACE, + TOTAL_sREQUEST, /* Total number of Standard request */ + SYNCH_FRAME = 12 +} STANDARD_REQUESTS; + +/* Definition of "USBwValue" */ +typedef enum _DESCRIPTOR_TYPE { + DEVICE_DESCRIPTOR = 1, + CONFIG_DESCRIPTOR, + STRING_DESCRIPTOR, + INTERFACE_DESCRIPTOR, + ENDPOINT_DESCRIPTOR +} DESCRIPTOR_TYPE; + +/* Feature selector of a SET_FEATURE or CLEAR_FEATURE */ +typedef enum _FEATURE_SELECTOR { + ENDPOINT_STALL, + DEVICE_REMOTE_WAKEUP +} FEATURE_SELECTOR; + + diff --git a/uc_str912/prj_blinky_complex_startup/include/usb_init.h b/uc_str912/prj_blinky_complex_startup/include/usb_init.h new file mode 100644 index 0000000..9d94750 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/usb_init.h @@ -0,0 +1,45 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_init.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : initialization routines & global variables +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +/* Save token on endpoint 0 */ +extern BYTE EP0_Token ; + +/* Interrupt flags.*/ +/* Each bit represents an interrupt is coming to that endpoint */ +extern WORD Token_Event ; + +/* The number of current endpoint, it will be used to specify an endpoint */ +extern BYTE EPindex; + +/* Points to the DEVICE_INFO structure of current device */ +/* The purpose of this register is to speed up the execution */ +extern DEVICE_INFO* pInformation; + +/* Points to the DEVICE_PROP structure of current device */ +/* The purpose of this register is to speed up the execution */ +extern DEVICE_PROP* pProperty; + +/* Temporary save the state of Rx & Tx status. */ +/* Whenever the Rx or Tx state is changed, its value is saved */ +/* in this variable first and will be set to the EPRB or EPRA */ +/* at the end of interrupt process */ +extern WORD SaveState ; + +extern WORD wInterrupt_Mask; + +void USB_Init(void); + diff --git a/uc_str912/prj_blinky_complex_startup/include/usb_lib.h b/uc_str912/prj_blinky_complex_startup/include/usb_lib.h new file mode 100644 index 0000000..f33fa73 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/usb_lib.h @@ -0,0 +1,25 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_lib.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : USB library include files +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +#include "USB_type.h" +#include "USB_regs.h" +#include "USB_def.h" +#include "USB_core.h" +#include "USB_init.h" +void CTR_ISR(void); diff --git a/uc_str912/prj_blinky_complex_startup/include/usb_mem.h b/uc_str912/prj_blinky_complex_startup/include/usb_mem.h new file mode 100644 index 0000000..3b4c958 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/usb_mem.h @@ -0,0 +1,23 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_mem.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : utility functions for memory transfers +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* function prototypes */ +void UserToPMABufferCopy(BYTE *pbUsrBuf,WORD wPMABufAddr, WORD wNBytes); +void PMAToUserBufferCopy(BYTE *pbUsrBuf,WORD wPMABufAddr, WORD wNBytes); + + diff --git a/uc_str912/prj_blinky_complex_startup/include/usb_regs.h b/uc_str912/prj_blinky_complex_startup/include/usb_regs.h new file mode 100644 index 0000000..fd1ac1b --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/usb_regs.h @@ -0,0 +1,442 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_regs.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Interface functions to USB cell registers +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#define RegBase (0x70000800L) /* USB_IP Peripheral Registers base address */ +#define PMAAddr (0x70000000L) /* USB_IP Packet Memory Area base address */ + +/* General registers */ +#define CNTR ((volatile unsigned *)(RegBase + 0x40)) /* Control register */ +#define ISTR ((volatile unsigned *)(RegBase + 0x44)) /* Interrupt status register */ +#define FNR ((volatile unsigned *)(RegBase + 0x48)) /* Frame number register */ +#define DADDR ((volatile unsigned *)(RegBase + 0x4C)) /* Device address register */ +#define BTABLE ((volatile unsigned *)(RegBase + 0x50)) /* Buffer Table address register */ +#define DMACR1 ((volatile unsigned *)(RegBase + 0x54)) /* DMA control register 1 */ +#define DMACR2 ((volatile unsigned *)(RegBase + 0x58)) /* DMA control register 2 */ +#define DMACR3 ((volatile unsigned *)(RegBase + 0x5C)) /* DMA control register 3 */ +#define DMABSIZE ((volatile unsigned *)(RegBase + 0x60))/* DMA burst size register */ +#define DMALLI ((volatile unsigned *)(RegBase + 0x64)) /* DMA LLI register */ + + +/* Endpoint registers */ +#define EP0REG ((volatile unsigned *)(RegBase)) /* endpoint 0 register address */ +/* endpoints enumeration */ +#define ENDP0 ((BYTE)0) +#define ENDP1 ((BYTE)1) +#define ENDP2 ((BYTE)2) +#define ENDP3 ((BYTE)3) +#define ENDP4 ((BYTE)4) +#define ENDP5 ((BYTE)5) +#define ENDP6 ((BYTE)6) +#define ENDP7 ((BYTE)7) +#define ENDP8 ((BYTE)8) +#define ENDP9 ((BYTE)9) + +/******************************************************************************/ +/* ISTR interrupt events */ +/******************************************************************************/ +#define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */ +#define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ +#define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */ +#define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */ +#define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */ +#define ISTR_RESET (0x0400) /* RESET (clear-only bit) */ +#define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */ +#define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */ +#define ISTR_SZDPR (0x0080) /* Short or Zero-Length Received Data Packet */ +#define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */ +#define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ + +#define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */ +#define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/ +#define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */ +#define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */ +#define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */ +#define CLR_RESET (~ISTR_RESET)/* clear RESET bit */ +#define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */ +#define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */ +#define CLR_SZDPR (~ISTR_SZDPR)/* clear SZDPR bit */ + +/******************************************************************************/ +/* CNTR control register bits definitions */ +/******************************************************************************/ +#define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */ +#define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ +#define CNTR_ERRM (0x2000) /* ERRor Mask */ +#define CNTR_WKUPM (0x1000) /* WaKe UP Mask */ +#define CNTR_SUSPM (0x0800) /* SUSPend Mask */ +#define CNTR_RESETM (0x0400) /* RESET Mask */ +#define CNTR_SOFM (0x0200) /* Start Of Frame Mask */ +#define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */ +#define CNTR_SZDPRM (0x0080) /* Short or Zero-Length Received Data Packet Mask*/ +#define CNTR_RESUME (0x0010) /* RESUME request */ +#define CNTR_FSUSP (0x0008) /* Force SUSPend */ +#define CNTR_LPMODE (0x0004) /* Low-power MODE */ +#define CNTR_PDWN (0x0002) /* Power DoWN */ +#define CNTR_FRES (0x0001) /* Force USB RESet */ + +/******************************************************************************/ +/* FNR Frame Number Register bit definitions */ +/******************************************************************************/ +#define FNR_RXDP (0x8000) /* status of D+ data line */ +#define FNR_RXDM (0x4000) /* status of D- data line */ +#define FNR_LCK (0x2000) /* LoCKed */ +#define FNR_LSOF (0x1800) /* Lost SOF */ +#define FNR_FN (0x07FF) /* Frame Number */ +/******************************************************************************/ +/* DADDR Device ADDRess bit definitions */ +/******************************************************************************/ +#define DADDR_EF (0x80) +#define DADDR_ADD (0x7F) + +/******************************************************************************/ +/* Endpoint register */ +/******************************************************************************/ +/* bit positions */ +#define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */ +#define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */ +#define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */ +#define EP_SETUP (0x0800) /* EndPoint SETUP */ +#define EP_T_FIELD (0x0600) /* EndPoint TYPE */ +#define EP_KIND (0x0100) /* EndPoint KIND */ +#define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */ +#define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */ +#define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */ +#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define EPREG_MASK (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD) + +/* EP_TYPE[1:0] EndPoint TYPE */ +#define EP_BULK (0x0000) /* EndPoint BULK */ +#define EP_CONTROL (0x0200) /* EndPoint CONTROL */ +#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */ +#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */ +#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK) + + +/* EP_KIND EndPoint KIND */ +#define EPKIND_MASK (~EP_KIND & EPREG_MASK) + +/* STAT_TX[1:0] STATus for TX transfer */ +#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */ +#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */ +#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */ +#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */ +#define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */ +#define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */ +#define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK) + +/* STAT_RX[1:0] STATus for RX transfer */ +#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */ +#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */ +#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */ +#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */ +#define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */ +#define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */ +#define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK) + + +typedef enum _EP_DBUF_DIR{ /* double buffered endpoint direction */ + EP_DBUF_ERR, + EP_DBUF_OUT, + EP_DBUF_IN +}EP_DBUF_DIR; + +enum EP_BUF_NUM{ /* endpoint buffer number */ + EP_NOBUF, + EP_BUF0 , + EP_BUF1 +}; + + +extern volatile WORD wIstr; /* ISTR register last read value */ + +/******************************************************************************/ +/* FUNCTION PROTOTYPES */ +/* & */ +/* M A C R O s */ +/******************************************************************************/ + +/* SetCNTR */ +void SetCNTR(WORD /*wRegValue*/); +#define _SetCNTR(wRegValue) (*CNTR = (WORD)wRegValue) +/*----------------------------------------------------------------------------*/ +/* SetISTR */ +void SetISTR(WORD /*wRegValue*/); +#define _SetISTR(wRegValue) (*ISTR = (WORD)wRegValue) +/*----------------------------------------------------------------------------*/ +/* SetDADDR */ +void SetDADDR(WORD /*wRegValue*/); +#define _SetDADDR(wRegValue) (*DADDR = (WORD)wRegValue) +/*----------------------------------------------------------------------------*/ +/* SetBTABLE */ +void SetBTABLE(WORD /*wRegValue*/); +#define _SetBTABLE(wRegValue)(*BTABLE = (WORD)(wRegValue & 0xFFF8)) +/*----------------------------------------------------------------------------*/ +/* GetCNTR */ +WORD GetCNTR(void); +#define _GetCNTR() ((WORD) *CNTR) +/*----------------------------------------------------------------------------*/ +/* GetISTR */ +WORD GetISTR(void); +#define _GetISTR() ((WORD) *ISTR) +/*----------------------------------------------------------------------------*/ +/* GetFNR */ +WORD GetFNR(void); +#define _GetFNR() ((WORD) *FNR) +/*----------------------------------------------------------------------------*/ +/* GetDADDR */ +WORD GetDADDR(void); +#define _GetDADDR() ((WORD) *DADDR) +/*----------------------------------------------------------------------------*/ +/* GetBTABLE */ +WORD GetBTABLE(void); +#define _GetBTABLE() ((WORD) *BTABLE) +/*----------------------------------------------------------------------------*/ +/* Pointers on endpoint(bEpNum) Count & Addr registers on PMA */ +#define _pEPBufCount(bEpNum) ((DWORD *)(_GetBTABLE()+bEpNum*8 + 4 + PMAAddr)) +#define _pEPBufAddr(bEpNum) ((DWORD *)(_GetBTABLE()+bEpNum*8 + PMAAddr)) +/*----------------------------------------------------------------------------*/ +/* SetENDPOINT */ +void SetENDPOINT(BYTE /*bEpNum*/,WORD /*wRegValue*/); +#define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \ +/*----------------------------------------------------------------------------*/ (WORD)wRegValue) +/* GetENDPOINT */ +WORD GetENDPOINT(BYTE /*bEpNum*/); +#define _GetENDPOINT(bEpNum) ((WORD)(*(EP0REG + bEpNum))) +/*----------------------------------------------------------------------------*/ +/* SetEPType */ +void SetEPType(BYTE /*bEpNum*/,WORD /*wType*/); +#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\ + ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType))) +/*----------------------------------------------------------------------------*/ +/* GetEPType */ +WORD GetEPType(BYTE /*bEpNum*/); +#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD) +/*----------------------------------------------------------------------------*/ +/* SetEPTxStatus */ +void SetEPTxStatus(BYTE /*bEpNum*/,WORD /*wState*/); +#define _SetEPTxStatus(bEpNum,wState) {\ + register WORD _wRegVal; \ + _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK; \ + /* toggle first bit ? */ \ + if((EPTX_DTOG1 & wState)!= 0) \ + _wRegVal ^= EPTX_DTOG1; \ + /* toggle second bit ? */ \ + if((EPTX_DTOG2 & wState)!= 0) \ + _wRegVal ^= EPTX_DTOG2; \ + _SetENDPOINT(bEpNum, _wRegVal); \ +} /* _SetEPTxStatus */ +/*----------------------------------------------------------------------------*/ +/* SetEPRxStatus */ +void SetEPRxStatus(BYTE /*bEpNum*/,WORD /*wState*/); +#define _SetEPRxStatus(bEpNum,wState) {\ + register WORD _wRegVal; \ + _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\ + /* toggle first bit ? */ \ + if((EPRX_DTOG1 & wState)!= 0) \ + _wRegVal ^= EPRX_DTOG1; \ + /* toggle second bit ? */ \ + if((EPRX_DTOG2 & wState)!= 0) \ + _wRegVal ^= EPRX_DTOG2; \ + _SetENDPOINT(bEpNum, _wRegVal); \ +} /* _SetEPRxStatus */ +/*----------------------------------------------------------------------------*/ +/* GetEPTxStatus / GetEPRxStatus */ +WORD GetEPTxStatus(BYTE /*bEpNum*/); +WORD GetEPRxStatus(BYTE /*bEpNum*/); +#define _GetEPTxStatus(bEpNum) ((WORD)_GetENDPOINT(bEpNum) & EPTX_STAT) +#define _GetEPRxStatus(bEpNum) ((WORD)_GetENDPOINT(bEpNum) & EPRX_STAT) +/*----------------------------------------------------------------------------*/ +/* SetEPTxValid / SetEPRxValid */ +void SetEPTxValid(BYTE /*bEpNum*/); +void SetEPRxValid(BYTE /*bEpNum*/); +#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID)) +#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID)) +/*----------------------------------------------------------------------------*/ +/* GetTxStallStatus / GetRxStallStatus */ +BOOL GetTxStallStatus(BYTE /*bEpNum*/); +BOOL GetRxStallStatus(BYTE /*bEpNum*/); +#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \ + == EP_TX_STALL) +#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \ + == EP_RX_STALL) +/*----------------------------------------------------------------------------*/ +/* SetEP_KIND / ClearEP_KIND */ +void SetEP_KIND(BYTE /*bEpNum*/); +void ClearEP_KIND(BYTE /*bEpNum*/); +#define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ + (_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK)) +#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ + (_GetENDPOINT(bEpNum) & EPKIND_MASK))) +/*----------------------------------------------------------------------------*/ +/* Set_Status_Out / Clear_Status_Out */ +void Set_Status_Out(BYTE /*bEpNum*/); +void Clear_Status_Out(BYTE /*bEpNum*/); +#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum) +#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum) +/*----------------------------------------------------------------------------*/ +/* SetEPDoubleBuff / ClearEPDoubleBuff */ +void SetEPDoubleBuff(BYTE /*bEpNum*/); +void ClearEPDoubleBuff(BYTE /*bEpNum*/); +#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum) +#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum) +/*----------------------------------------------------------------------------*/ +/* ClearEP_CTR_RX / ClearEP_CTR_TX */ +void ClearEP_CTR_RX(BYTE /*bEpNum*/); +void ClearEP_CTR_TX(BYTE /*bEpNum*/); +#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\ + _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK)) +#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\ + _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK)) +/*----------------------------------------------------------------------------*/ +/* ToggleDTOG_RX / ToggleDTOG_TX */ +void ToggleDTOG_RX(BYTE /*bEpNum*/); +void ToggleDTOG_TX(BYTE /*bEpNum*/); +#define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \ + ((EP_DTOG_RX | _GetENDPOINT(bEpNum)) & EPREG_MASK))) +#define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \ + ((EP_DTOG_TX | _GetENDPOINT(bEpNum)) & EPREG_MASK))) +/*----------------------------------------------------------------------------*/ +/* ClearDTOG_RX / ClearDTOG_TX */ +void ClearDTOG_RX(BYTE /*bEpNum*/); +void ClearDTOG_TX(BYTE /*bEpNum*/); +#define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\ + _ToggleDTOG_RX(bEpNum) +#define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\ + _ToggleDTOG_TX(bEpNum) +/*----------------------------------------------------------------------------*/ +/* SetEPAddress */ +void SetEPAddress(BYTE /*bEpNum*/,BYTE /*bAddr*/); +#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\ + (_GetENDPOINT(bEpNum) & (EPREG_MASK | bAddr))) +/*----------------------------------------------------------------------------*/ +/* GetEPAddress */ +BYTE GetEPAddress(BYTE /*bEpNum*/); +#define _GetEPAddress(bEpNum) ((BYTE)(_GetENDPOINT(bEpNum) & EPADDR_FIELD)) +/*----------------------------------------------------------------------------*/ +/* SetEPTxAddr / SetEPRxAddr*/ +void SetEPTxAddr(BYTE /*bEpNum*/,WORD /*wAddr*/); +#define _SetEPTxAddr(bEpNum , wAddr) {\ + *_pEPBufAddr(bEpNum) &=0xFFFF0000; \ + *_pEPBufAddr(bEpNum) |=((wAddr)&0x0FFFC);\ + } +void SetEPRxAddr(BYTE /*bEpNum*/,WORD /*wAddr*/); +#define _SetEPRxAddr(bEpNum, wAddr) {\ + *_pEPBufAddr(bEpNum) &=0x0000FFFF;\ + *_pEPBufAddr(bEpNum) |=((wAddr<<16)&0xFFFC0000);\ +} +/*----------------------------------------------------------------------------*/ +/* GetEPTxAddr / GetEPRxAddr */ +WORD GetEPTxAddr(BYTE /*bEpNum*/); +#define _GetEPTxAddr(bEpNum) ((WORD)(*_pEPBufAddr(bEpNum) &0x0000FFFF)) +WORD GetEPRxAddr(BYTE /*bEpNum*/); +#define _GetEPRxAddr(bEpNum) ((WORD)((*_pEPBufAddr(bEpNum)&0xFFFF0000)>>16)) +/*----------------------------------------------------------------------------*/ +/* SetEPTxCount / SetEPRxCount */ +void SetEPTxCount(BYTE /*bEpNum*/,WORD /*wCount*/); +#define _SetEPTxCount(bEpNum,wCount) {\ + *_pEPBufCount(bEpNum) &=0xFFFFFC00;\ + *_pEPBufCount(bEpNum) |=wCount;\ +} +/*----------------------------------------------------------------------------*/ +void SetEPRxCount(BYTE /*bEpNum*/,WORD /*wCount*/); +#define _SetEPRxCount(bEpNum,wCount) {\ +DWORD BLsize=0;\ +DWORD Blocks;\ +if (wCount < 64) Blocks = wCount>>1;\ +else\ +{\ + BLsize = 0x80000000;\ + Blocks = wCount>>6;\ +}\ +*_pEPBufCount(bEpNum) &=~0x80000000;\ +*_pEPBufCount(bEpNum) |=BLsize;\ +*_pEPBufCount(bEpNum) &=0x83FFFFFF;\ +*_pEPBufCount(bEpNum) |=Blocks<<26;\ +*_pEPBufCount(bEpNum) &=0xFC00FFFF;\ +} + +/*----------------------------------------------------------------------------*/ +/* GetEPTxCount / GetEPRxCount */ +WORD GetEPTxCount(BYTE /*bEpNum*/); +#define _GetEPTxCount(bEpNum) (WORD)(*_pEPBufCount(bEpNum)&0x3FF) +WORD GetEPRxCount(BYTE /*bEpNum*/); +#define _GetEPRxCount(bEpNum) (WORD)((*_pEPBufCount(bEpNum)&0x3FF0000)>>16) +/*----------------------------------------------------------------------------*/ +/* SetEPDblBuf0Addr / SetEPDblBuf1Addr */ +void SetEPDblBuf0Addr(BYTE /*bEpNum*/,WORD /*wBuf0Addr*/); +void SetEPDblBuf1Addr(BYTE /*bEpNum*/,WORD /*wBuf1Addr*/); +#define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);} +#define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);} +/*----------------------------------------------------------------------------*/ +/* SetEPDblBuffAddr */ +void SetEPDblBuffAddr(BYTE /*bEpNum*/,WORD /*wBuf0Addr*/,WORD /*wBuf1Addr*/); +#define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \ + _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); \ + _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); \ +} /* _SetEPDblBuffAddr */ +/*----------------------------------------------------------------------------*/ +/* GetEPDblBuf0Addr / GetEPDblBuf1Addr */ +WORD GetEPDblBuf0Addr(BYTE /*bEpNum*/); +WORD GetEPDblBuf1Addr(BYTE /*bEpNum*/); +#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum)) +#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum)) +/*----------------------------------------------------------------------------*/ +/* SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count */ +void SetEPDblBuffCount(BYTE /*bEpNum*/, BYTE /*bDir*/, WORD /*wCount*/); +void SetEPDblBuf0Count(BYTE /*bEpNum*/, BYTE /*bDir*/, WORD /*wCount*/); +void SetEPDblBuf1Count(BYTE /*bEpNum*/, BYTE /*bDir*/, WORD /*wCount*/); + +/*----------------------------------------------------------------------------*/ +/* GetEPDblBuf0Count / GetEPDblBuf1Count */ +WORD GetEPDblBuf0Count(BYTE /*bEpNum*/); +WORD GetEPDblBuf1Count(BYTE /*bEpNum*/); +#define _GetEPDblBuf0Count(bEpNum) (GetEPTxCount(bEpNum)) +#define _GetEPDblBuf1Count(bEpNum) (GetEPRxCount(bEpNum)) +/*----------------------------------------------------------------------------*/ +/* FreeUserBuffer */ +void FreeUserBuffer(BYTE /*bEpNum*/,BYTE Dir); +/*----------------------------------------------------------------------------*/ +/* ToWord */ +WORD ToWord(BYTE,BYTE); +/*----------------------------------------------------------------------------*/ +/* ByteSwap */ +WORD ByteSwap(WORD); +/*----------------------------------------------------------------------------*/ + +/* DMA Functions */ +void SetDMABurstTxSize(BYTE /*DestBsize*/); +void SetDMABurstRxSize(BYTE /*SrcBsize*/); +void DMAUnlinkedModeTxConfig(BYTE /*bEpNum*/ ,BYTE /*index*/); +void DMAUnlinkedModeTxEnable(BYTE /*index*/); +void DMAUnlinkedModeTxDisable(BYTE /*index*/); +void DMAUnlinkedModeRxEnable(BYTE /*bEpNum*/); +void DMAUnlinkedModeRxDisable(BYTE /*bEpNum*/); +void DMALinkedModeRxConfig(BYTE /*bEpNum*/); +void DMALinkedModeTxConfig(BYTE /*bEpNum*/); +void DMALinkedModeRxEnable(void); +void DMALinkedModeTxEnable(void); +void DMALinkedModeRxDisable(void); +void DMALinkedModeTxDisable(void); +void DMASynchEnable(void); +void DMASynchDisable(void); +void SetDMALLITxLength(BYTE /*length*/); +void SetDMALLIRxLength(BYTE /*length*/ ); +void SetDMALLIRxPacketNum(BYTE /*PacketNum*/); +BYTE GetDMALLIRxPacketNum(void); diff --git a/uc_str912/prj_blinky_complex_startup/include/usb_type.h b/uc_str912/prj_blinky_complex_startup/include/usb_type.h new file mode 100644 index 0000000..42c7802 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/include/usb_type.h @@ -0,0 +1,31 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_type.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : types used in the usb library +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#ifndef __USB_TYPE_H +#define __USB_TYPE_H + +#ifndef NULL +#define NULL ((void *)0) +#endif + + +typedef unsigned int DWORD; +typedef unsigned char BOOL; +typedef unsigned char BYTE; +typedef unsigned short WORD; + +#endif /* __USB_TYPE_H */ diff --git a/uc_str912/prj_blinky_complex_startup/interrupt.c b/uc_str912/prj_blinky_complex_startup/interrupt.c new file mode 100644 index 0000000..2b6ccd7 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/interrupt.c @@ -0,0 +1,295 @@ +/******************************************************************** + * Project: STR9-comStick GNU (UART) + * File: interrupt.c + * + * System: ARM9TDMI 32 Bit (STR912FW44X) + * Compiler: GCC 4.0.3 + * + * Date: 2006-12-20 + * Author: Applications@Hitex.de + * + * Rights: Hitex Development Tools GmbH + * Greschbachstr. 12 + * D-76229 Karlsruhe + ******************************************************************** + * Description: + * +* This file is part of the GNU Example chain for STR9-comStick + * The code is bassed on usage of the STmicro library functions + * This is a small implementation of UART1 feature with command interface + * The application runs in ARM mode with high optimization level. + * + ******************************************************************** + * History: + * + * Revision 1.0 2006/12/20 Gn + * Initial revision + ******************************************************************** + * This is a preliminary version. + * + * WARRANTY: HITEX warrants that the media on which the SOFTWARE is + * furnished is free from defects in materials and workmanship under + * normal use and service for a period of ninety (90) days. HITEX entire + * liability and your exclusive remedy shall be the replacement of the + * SOFTWARE if the media is defective. This Warranty is void if failure + * of the media resulted from unauthorized modification, accident, abuse, + * or misapplication. + * + * DISCLAIMER: OTHER THAN THE ABOVE WARRANTY, THE SOFTWARE IS FURNISHED + * "AS IS" WITHOUT WARRANTY OF ANY KIND. HITEX DISCLAIMS ALL OTHER WARRANTIES, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * NEITHER HITEX NOR ITS AFFILIATES SHALL BE LIABLE FOR ANY DAMAGES ARISING + * OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE, INCLUDING DAMAGES FOR + * LOSS OF PROFITS, BUSINESS INTERRUPTION, OR ANY SPECIAL, INCIDENTAL, INDIRECT + * OR CONSEQUENTIAL DAMAGES EVEN IF HITEX HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGES. + ********************************************************************/ + +#define global extern /* to declare external variables and functions */ + +extern void USB_Istr(void); +extern void UART1_isr(void); + +/* switch to SYS mode and enabled interrupts */ +#define SWITCH_IRQ_TO_SYS asm(" msr CPSR_c,#0x1F \n stmfd sp!,{lr}" ) + +/* switch back to IRQ mode with IRQ disabled */ +#define SWITCH_SYS_TO_IRQ asm (" ldmfd sp!,{lr} \n msr CPSR_c,#0x12|0x80") + +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles preftetch abort exception. +*******************************************************************************/ +void Prefetch_Handler(void) +{ +} +/******************************************************************************* +* Function Name : WDG_IRQHandler +* Description : This function handles the WDG interrupt request +*******************************************************************************/ +void WDG_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : SW_IRQHandler +* Description : This function handles the SW interrupt request +*******************************************************************************/ +void SW_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : ARMRX_IRQHandler +* Description : This function handles the ARMRX interrupt request +*******************************************************************************/ +void ARMRX_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : ARMTX_IRQHandler +* Description : This function handles the ARMTX interrupt request +*******************************************************************************/ +void ARMTX_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : TIM0_IRQHandler +* Description : This function handles the TIM0 interrupt request +*******************************************************************************/ +void TIM0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : TIM1_IRQHandler +* Description : This function handles the TIM1 interrupt request +*******************************************************************************/ +void TIM1_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : TIM2_IRQHandler +* Description : This function handles the TIM2 interrupt request +*******************************************************************************/ +void TIM2_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : TIM3_IRQHandler +* Description : This function handles the TIM3 interrupt request +*******************************************************************************/ +void TIM3_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : USBHP_IRQHandler +* Description : This function handles the USBHP interrupt request +*******************************************************************************/ +void USBHP_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : USBLP_IRQHandler +* Description : This function handles the USBLP interrupt request +*******************************************************************************/ +void USBLP_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : SCU_IRQHandler +* Description : This function handles the SCU interrupt request +*******************************************************************************/ +void SCU_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : ENET_IRQHandler +* Description : This function handles the DENET interrupt request +*******************************************************************************/ +void ENET_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : DMA_IRQHandler +* Description : This function handles the DMA interrupt request +*******************************************************************************/ +void DMA_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : CAN_IRQHandler +* Description : This function handles the CAN interrupt request +*******************************************************************************/ +void CAN_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : MC_IRQHandler +* Description : This function handles the MC interrupt request +*******************************************************************************/ +void MC_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : ADC_IRQHandler +* Description : This function handles the ADC interrupt request +*******************************************************************************/ +void ADC_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : UART0_IRQHandler +* Description : This function handles the UART0 interrupt request +*******************************************************************************/ +void UART0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : UART1_IRQHandler -> moved to inthandler.s +* Description : This function handles the UART1 interrupt request +*******************************************************************************/ +void UART1_IRQHandler(void) +{ +/* SWITCH_SYS_TO_IRQ; + UART1_isr(); + SWITCH_IRQ_TO_SYS;*/ +} +/******************************************************************************* +* Function Name : UART2_IRQHandler +* Description : This function handles the UART2 interrupt request +*******************************************************************************/ +void UART2_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : I2C0_IRQHandler +* Description : This function handles the I2C0 interrupt request +*******************************************************************************/ +void I2C0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : I2C1_IRQHandler +* Description : This function handles the I2C1 interrupt request +*******************************************************************************/ +void I2C1_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : SSP0_IRQHandler +* Description : This function handles the SSP0 interrupt request +*******************************************************************************/ +void SSP0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : SSP1_IRQHandler +* Description : This function handles the SSP1 interrupt request +*******************************************************************************/ +void SSP1_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : LVD_IRQHandler +* Description : This function handles the LVD interrupt request +*******************************************************************************/ +void LVD_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles the RTC interrupt request +*******************************************************************************/ +void RTC_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : WIU_IRQHandler +* Description : This function handles the WIU interrupt request +*******************************************************************************/ +void WIU_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : EXTIT0_IRQHandler +* Description : This function handles the EXTIT0 interrupt request +*******************************************************************************/ +void EXTIT0_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : EXTIT1_IRQHandler +* Description : This function handles the EXTIT1 interrupt request +*******************************************************************************/ +void EXTIT1_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : EXTIT2_IRQHandler +* Description : This function handles the EXTIT2 interrupt request +*******************************************************************************/ +void EXTIT2_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : EXTIT3_IRQHandler +* Description : This function handles the EXTIT3 interrupt request +*******************************************************************************/ +void EXTIT3_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : USBWU_IRQHandler +* Description : This function handles the USBWU interrupt request +*******************************************************************************/ +void USBWU_IRQHandler(void) +{ +} +/******************************************************************************* +* Function Name : PFQBC_IRQHandler +* Description : This function handles the PFQBC interrupt request +*******************************************************************************/ +void PFQBC_IRQHandler(void) +{ +} + diff --git a/uc_str912/prj_blinky_complex_startup/inthandler.S b/uc_str912/prj_blinky_complex_startup/inthandler.S new file mode 100644 index 0000000..09fea2f --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/inthandler.S @@ -0,0 +1,94 @@ +# Hitex/We/26.04.2006 +# primary interrupt service + +# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F + + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + + .text +# generate arm instructions (.code32) + .arm + .extern UART1_isr + .global UART1_IRQHandler /*_uart1_srv*/ + .global _disableInterrupts + .global _enableInterrupts + + +# enable FIQ interrupts + + .func _enableInterrupts +_enableInterrupts: + stmfd sp!, {r1} + mrs r1, CPSR + bic r1, r1, #I_BIT + bic r1, r1, #F_BIT + msr CPSR_c, r1 + ldmfd sp!, {r1} + mov pc, r14 + .size __enableInterrupts, . - __enableInterrupts + .endfunc + + +#disable FIQ interrupts + + .func _disableInterrupts +_disableInterrupts: + stmfd sp!, {r1} + mrs r1, CPSR + orr r1, r1, #0x40 + msr CPSR_c, r1 + ldmfd sp!, {r1} + mov pc, r14 + .size __disableInterrupts, . - __disableInterrupts + .endfunc + + +################################################### +# +# primary interrupt services +# +################################################### +.macro SvCon +# Adjust and save LR_irq in IRQ stack + sub r14, r14, #4 + stmfd sp!, {r14} + +# Save SPSR and r0 in IRQ stack + mrs r14, SPSR + stmfd sp!, {r0, r1, r14} + +# Save used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, r14} +.endm +.macro RsCon +# Restore used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, r14} + +# Restore SPSR_irq and r0 from IRQ stack + ldmia sp!, {r0, r1, r14} + msr SPSR_cxsf, r14 +# Restore adjusted LR_irq from IRQ stack directly in the PC + ldmia sp!, {pc}^ +.endm + +#inthandler entries + .func UART1_IRQHandler /*_uart1_srv*/ +UART1_IRQHandler: /*_uart1_srv:*/ + SvCon +# enter ISR + bl UART1_isr /* branch to isr */ +# back from ISR + RsCon + .size __uart1_srv, . - __uart1_srv + .endfunc + +.end diff --git a/uc_str912/prj_blinky_complex_startup/load_segger.gdb b/uc_str912/prj_blinky_complex_startup/load_segger.gdb new file mode 100644 index 0000000..fe98dd4 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/load_segger.gdb @@ -0,0 +1,23 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:2331 + +monitor speed adaptive +monitor endian little + +monitor reset +monitor flash device = STR912FAW44 +monitor flash breakpoints = 1 +monitor flash download = 1 +monitor halt + + +pwd +load main.elf +file main.elf +step +break after_delay +continue diff --git a/uc_str912/prj_blinky_complex_startup/main.c b/uc_str912/prj_blinky_complex_startup/main.c new file mode 100644 index 0000000..067323d --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/main.c @@ -0,0 +1,173 @@ +/******************************************************************** + * Project: STR9-comStick GNU (UART on Interrupt) + * File: main.c + * + * System: ARM9TDMI 32 Bit (STR912FW44X) + * Compiler: GCC 4.0.3 + * + * Date: 2006-12-20 + * Author: Applications@Hitex.de + * + * Rights: Hitex Development Tools GmbH + * Greschbachstr. 12 + * D-76229 Karlsruhe + ******************************************************************** + * Description: + * + * This file is part of the GNU Example chain for STR9-comStick + * The code is bassed on usage of the STmicro library functions + * This is a small implementation of UART1 feature with command interface + * The application runs in ARM mode with high optimization level. + * + ******************************************************************** + * History: + * + * Revision 1.0 2006/12/20 Gn + * Initial revision + ******************************************************************** + * This is a preliminary version. + * + * WARRANTY: HITEX warrants that the media on which the SOFTWARE is + * furnished is free from defects in materials and workmanship under + * normal use and service for a period of ninety (90) days. HITEX entire + * liability and your exclusive remedy shall be the replacement of the + * SOFTWARE if the media is defective. This Warranty is void if failure + * of the media resulted from unauthorized modification, accident, abuse, + * or misapplication. + * + * DISCLAIMER: OTHER THAN THE ABOVE WARRANTY, THE SOFTWARE IS FURNISHED + * "AS IS" WITHOUT WARRANTY OF ANY KIND. HITEX DISCLAIMS ALL OTHER WARRANTIES, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * NEITHER HITEX NOR ITS AFFILIATES SHALL BE LIABLE FOR ANY DAMAGES ARISING + * OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE, INCLUDING DAMAGES FOR + * LOSS OF PROFITS, BUSINESS INTERRUPTION, OR ANY SPECIAL, INCIDENTAL, INDIRECT + * OR CONSEQUENTIAL DAMAGES EVEN IF HITEX HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGES. + ********************************************************************/ + +#include "defines.h" + +#define global extern /* to declare external variables and functions */ +#include "91x_lib.h" + +#include "main.h" + +extern void _enableInterrupts(void); + + + GPIO_InitTypeDef GPIO_InitStructure; + + +/* Private function prototypes -----------------------------------------------*/ + void SCU_Configuration(void); + void GPIO_Configuration(void); + void VIC_Configuration(void); + static void Delay(u32 nCount); + +int main (void) +{ + + /* Configure the system clocks */ + SCU_Configuration(); + /* Configure the GPIOs */ + GPIO_Configuration(); + /* VIC setup */ + VIC_Configuration(); + + + /* endless loop */ + while (1) + { + /* Turn ON leds connected to P8.0 pins */ + GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_SET); + GPIO_WriteBit(GPIO8, GPIO_Pin_1, Bit_SET); + GPIO_WriteBit(GPIO8, GPIO_Pin_2, Bit_SET); + GPIO_WriteBit(GPIO8, GPIO_Pin_3, Bit_SET); + + /* Insert delay */ + Delay(0x1FFFFF); + + /* Turn OFF leds connected to 88.0 pins */ + GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_RESET); + GPIO_WriteBit(GPIO8, GPIO_Pin_1, Bit_RESET); + GPIO_WriteBit(GPIO8, GPIO_Pin_2, Bit_RESET); + GPIO_WriteBit(GPIO8, GPIO_Pin_3, Bit_RESET); + + /* Insert delay */ + Delay(0x1FFFFF); + } +} + +void SCU_Configuration(void) +{ + +// FMI_BankRemapConfig(4, 2, 0x00000000, 0x80000); /* Set Flash banks size & address */ + FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE,\ + FMI_LVD_ENABLE, FMI_FREQ_HIGH); /* FMI Waite States */ + + SCU_MCLKSourceConfig(SCU_MCLK_OSC); + + SCU_PLLFactorsConfig(192,25,2); /* PLL = 96 MHz */ + SCU_PLLCmd(ENABLE); /* PLL Enabled */ + + SCU_RCLKDivisorConfig(SCU_RCLK_Div1); /* RCLK @96Mhz */ + SCU_HCLKDivisorConfig(SCU_HCLK_Div1); /* AHB @96Mhz */ + SCU_FMICLKDivisorConfig(SCU_FMICLK_Div1);/* FMI @96Mhz */ + SCU_PCLKDivisorConfig(SCU_PCLK_Div2); /* APB @48Mhz */ + SCU_MCLKSourceConfig(SCU_MCLK_PLL); /* MCLK @96Mhz */ + + /* Set the PCLK Clock to MCLK/2 */ + SCU_PCLKDivisorConfig(SCU_PCLK_Div2); + + /* Enable VIC clock */ + SCU_APBPeriphClockConfig(__VIC, ENABLE); + SCU_APBPeriphReset(__VIC, DISABLE); + + /* Enable the GPIO8 Clock */ + SCU_APBPeriphClockConfig(__GPIO8, ENABLE); + + /* Enable the clock for the GPIO3 */ + SCU_APBPeriphClockConfig(__GPIO3, ENABLE); + +} + +/* GPIO Configuration --------------------------------------------------------*/ +void GPIO_Configuration(void) +{ + GPIO_DeInit(GPIO8); + GPIO_DeInit(GPIO3); /* GPIO3 Deinitialization */ + /* LED */ + GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All; + GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; + GPIO_Init (GPIO8, &GPIO_InitStructure); + /* button */ + GPIO_InitStructure.GPIO_Direction = GPIO_PinInput; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; + GPIO_Init (GPIO3, &GPIO_InitStructure); + +} + +void VIC_Configuration(void) +{ + /* reset to default state */ + VIC_DeInit(); +} + +/******************************************************************************* +* Function Name : Delay +* Description : Inserts a delay time. +* Input : nCount: specifies the delay time length. +*******************************************************************************/ +static void Delay(u32 nCount) +{ + u32 j = 0; + + for(j = nCount; j > 0; j--) + asm("nop"); +} +/************************************** EOF *********************************/ + diff --git a/uc_str912/prj_blinky_complex_startup/main.h b/uc_str912/prj_blinky_complex_startup/main.h new file mode 100644 index 0000000..bf63b47 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/main.h @@ -0,0 +1,55 @@ +/******************************************************************** + * Project: STR9-comStick GNU (UART) + * File: main.h + * + * System: ARM9TDMI 32 Bit (STR912FW44X) + * Compiler: GCC 4.0.3 + * + * Date: 2006-12-20 + * Author: Applications@Hitex.de + * + * Rights: Hitex Development Tools GmbH + * Greschbachstr. 12 + * D-76229 Karlsruhe + ******************************************************************** + * Description: + * + * This file is part of the GNU Example chain for STR9-comStick + * The code is bassed on usage of the STmicro library functions + * This is a small implementation of UART1 feature with command interface + * The application runs in ARM mode with high optimization level. + * + ******************************************************************** + * History: + * + * Revision 1.0 2006/12/20 Gn + * Initial revision + ******************************************************************** + * This is a preliminary version. + * + * WARRANTY: HITEX warrants that the media on which the SOFTWARE is + * furnished is free from defects in materials and workmanship under + * normal use and service for a period of ninety (90) days. HITEX entire + * liability and your exclusive remedy shall be the replacement of the + * SOFTWARE if the media is defective. This Warranty is void if failure + * of the media resulted from unauthorized modification, accident, abuse, + * or misapplication. + * + * DISCLAIMER: OTHER THAN THE ABOVE WARRANTY, THE SOFTWARE IS FURNISHED + * "AS IS" WITHOUT WARRANTY OF ANY KIND. HITEX DISCLAIMS ALL OTHER WARRANTIES, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * NEITHER HITEX NOR ITS AFFILIATES SHALL BE LIABLE FOR ANY DAMAGES ARISING + * OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE, INCLUDING DAMAGES FOR + * LOSS OF PROFITS, BUSINESS INTERRUPTION, OR ANY SPECIAL, INCIDENTAL, INDIRECT + * OR CONSEQUENTIAL DAMAGES EVEN IF HITEX HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGES. + ********************************************************************/ + +#ifndef __MAIN_H__ +#define __MAIN_H__ + +#endif /* __MAIN_H__ */ + +/************************************** EOF *********************************/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_adc.c b/uc_str912/prj_blinky_complex_startup/src/91x_adc.c new file mode 100644 index 0000000..a36758b --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_adc.c @@ -0,0 +1,590 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_adc.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the ADC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_adc.h" +#include "91x_scu.h" +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ADC mask */ +#define ADC_FLAG_MASK 0x001F /* ADC Flag Mask */ +#define ADC_RESULT_MASK 0x03FF /* ADC Result Mask */ +#define ADC_SCAN_MODE_MASK 0x0020 /* ADC Sacn Mode Mask */ +#define ADC_STANDBY_MODE_MASK 0x0008 /* ADC Standby Mode Mask */ +#define ADC_CMD_MASK 0x0002 /* ADC Command Mask */ +#define ADC_CHANNEL_MASK 0xFE3F /* ADC Channel Select Mask */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ADC_DeInit +* Description : Deinitialize the ADC module registers to their default reset +* values +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DeInit(void) +{ + /* Reset the ADC registers values */ + SCU_APBPeriphReset(__ADC,ENABLE); + SCU_APBPeriphReset(__ADC,DISABLE); +} + +/******************************************************************************* +* Function Name : ADC_Init +* Description : Initializes ADC peripheral according to the specified +* parameters in the ADC_InitTypeDef structure. +* Input : ADC_InitStruct: pointer to a ADC_InitTypeDef structure that +* contains the configuration information for the specified +* ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Set the low threshold of the watchdog */ + ADC->LTR = ADC_InitStruct->ADC_WDG_Low_Threshold; + + /* Set the high threshold of the watchdog */ + ADC->HTR = ADC_InitStruct->ADC_WDG_High_Threshold; + + + /* Channel 0 conversion mode */ + ADC->CCR &= 0xFFFC; + ADC->CCR |= ADC_InitStruct->ADC_Channel_0_Mode; + + /* Channel 1 conversion mode */ + ADC->CCR &= 0xFFF3; + ADC->CCR |= ADC_InitStruct->ADC_Channel_1_Mode << 0x2; + + /* Channel 2 conversion mode */ + ADC->CCR &= 0xFFCF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_2_Mode << 0x4; + + /* Channel 3 conversion mode */ + ADC->CCR &= 0xFF3F; + ADC->CCR |= ADC_InitStruct->ADC_Channel_3_Mode << 0x6; + + /* Channel 4 conversion mode */ + ADC->CCR &= 0xFCFF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_4_Mode << 0x8; + + /* Channel 5 conversion mode */ + ADC->CCR &= 0xF3FF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_5_Mode << 0xA; + + /* Channel 6 conversion mode */ + ADC->CCR &= 0xCFFF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_6_Mode << 0xC; + + /* Channel 7 conversion mode */ + ADC->CCR &= 0x3FFF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_7_Mode << 0xE; + + /* Select the channel to be converted */ + ADC->CR &= ADC_CHANNEL_MASK; + ADC->CR |= ADC_InitStruct->ADC_Select_Channel << 0x6; + + /* Enable/disable the scan mode */ + if (ADC_InitStruct->ADC_Scan_Mode == ENABLE) + { + /* Enable the scan mode */ + ADC->CR |= ADC_SCAN_MODE_MASK; + } + else + { + /* Disable the scan mode */ + ADC->CR &= ~ADC_SCAN_MODE_MASK; + } + + /* Configure the conversion mode */ + if (ADC_InitStruct->ADC_Conversion_Mode == ADC_Continuous_Mode) + { + /* ADC continuous mode */ + ADC->CR |= ADC_Continuous_Mode; + } + else + { + /* ADC single mode */ + ADC->CR &= ADC_Single_Mode; + } +} + +/******************************************************************************* +* Function Name : ADC_StructInit +* Description : Fills each ADC_InitStruct member with its reset value. +* Input : ADC_InitStruct : pointer to a ADC_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + ADC_InitStruct->ADC_WDG_High_Threshold = 0x0000; + ADC_InitStruct->ADC_WDG_Low_Threshold = 0x0000; + ADC_InitStruct->ADC_Channel_0_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_1_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_2_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_3_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_4_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_5_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_6_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_7_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Select_Channel = ADC_Channel_0; + ADC_InitStruct->ADC_Scan_Mode = DISABLE; + ADC_InitStruct->ADC_Conversion_Mode = ADC_Single_Mode; +} + +/******************************************************************************* +* Function Name : ADC_PrescalerConfig +* Description : This routine is used to configure the ADC prescaler value. +* Input : ADC_Prescaler: specifies the prescaler value. This parameter +* can be a value from 0x0 to 0xFF. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_PrescalerConfig(u8 ADC_Prescaler) +{ + ADC->PRS &= 0xFF00; + ADC->PRS |= ADC_Prescaler; + +} +/******************************************************************************* +* Function Name : ADC_GetPrescalerValue +* Description : This routine is used to get the ADC prescaler value. +* Input : None +* Output : None +* Return : The prescaler value. +*******************************************************************************/ +u8 ADC_GetPrescalerValue(void) +{ + return ADC->PRS & 0x00FF; +} +/******************************************************************************* +* Function Name : ADC_GetFlagStatus +* Description : Checks whether the specified ADC flag is set or not. +* Input : ADC_Flag: flag to check. +* This parameter can be one of the following values: +* - ADC_FLAG_OV_CH_0: Conversion overflow status for +* channel 0. +* - ADC_FLAG_OV_CH_1: Conversion overflow status for +* channel 1. +* - ADC_FLAG_OV_CH_2: Conversion overflow status for +* channel 2. +* - ADC_FLAG_OV_CH_3: Conversion overflow status for +* channel 3. +* - ADC_FLAG_OV_CH_4: Conversion overflow status for +* channel 4. +* - ADC_FLAG_OV_CH_5: Conversion overflow status for +* channel 5. +* - ADC_FLAG_OV_CH_6: Conversion overflow status for +* channel 6. +* - ADC_FLAG_OV_CH_7: Conversion overflow status for +* channel 7. +* - ADC_FLAG_ECV: End of conversion status. +* - ADC_FLAG_AWD: Analog watchdog status. +* Output : None +* Return : The NewState of the ADC_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetFlagStatus(u16 ADC_Flag) +{ + u8 AdcReg = 0, FlagPos = 0; + + /* Get the ADC register index */ + AdcReg = ADC_Flag >> 5; + + /* Get the flag position */ + FlagPos = ADC_Flag & ADC_FLAG_MASK; + + if(AdcReg == 1) /* The flag to check is in CR register */ + { + if((ADC->CR & (1<DR0 & (1<DR1 & (1<DR2 & (1<DR3 & (1<DR4 & (1<DR5 & (1<DR6 & (1<DR7 & (1<CR |= (1<<(ADC_Flag & ADC_FLAG_MASK)); +} + +/******************************************************************************* +* Function Name : ADC_GetConversionValue +* Description : Read the result of conversion from the appropriate data +* register. +* Input : ADC_Channel: the correspondent channel of the ADC peripheral. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC channel 0. +* - ADC_Channel_1: ADC channel 1. +* - ADC_Channel_2: ADC channel 2. +* - ADC_Channel_3: ADC channel 3. +* - ADC_Channel_4: ADC channel 4. +* - ADC_Channel_5: ADC channel 5. +* - ADC_Channel_6: ADC channel 6. +* - ADC_Channel_7: ADC channel 7. +* Output : None +* Return : The result of the conversion for the specific channel. +*******************************************************************************/ +u16 ADC_GetConversionValue(u16 ADC_Channel) +{ + u16 ADC_Conversion_Value = 0; + + switch (ADC_Channel) + { + case (ADC_Channel_0): + /* Get the conversion value of the channel 0 */ + ADC_Conversion_Value = ADC->DR0 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_1): + /* Get the conversion value of the channel 1 */ + ADC_Conversion_Value = ADC->DR1 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_2): + /* Get the conversion value of the channel 2 */ + ADC_Conversion_Value = ADC->DR2 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_3): + /* Get the conversion value of the channel 3 */ + ADC_Conversion_Value = ADC->DR3 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_4): + /* Get the conversion value of the channel 4 */ + ADC_Conversion_Value = ADC->DR4 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_5): + /* Get the conversion value of the channel 5 */ + ADC_Conversion_Value = ADC->DR5 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_6): + /* Get the conversion value of the channel 6 */ + ADC_Conversion_Value = ADC->DR6 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_7): + /* Get the conversion value of the channel 7 */ + ADC_Conversion_Value = ADC->DR7 & ADC_RESULT_MASK; + break; + + default: + break; + } + + return(ADC_Conversion_Value); +} + +/******************************************************************************* +* Function Name : ADC_GetAnalogWatchdogResult +* Description : Return the result of the comparaison on the selected Analog +* Watchdog. +* Input : ADC_Channel: the correspondent channel of the ADC peripheral. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC channel 0. +* - ADC_Channel_1: ADC channel 1. +* - ADC_Channel_2: ADC channel 2. +* - ADC_Channel_3: ADC channel 3. +* - ADC_Channel_4: ADC channel 4. +* - ADC_Channel_5: ADC channel 5. +* - ADC_Channel_6: ADC channel 6. +* - ADC_Channel_7: ADC channel 7. +* Output : None +* Return : The state of the comparision (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetAnalogWatchdogResult(u16 ADC_Channel) +{ + if ((ADC->CRR & (1<CRR = 1<LTR; + break; + + case ADC_HighThreshold: + /* Get the high threshol of the watchdog */ + ADC_Threshold_Value = ADC->HTR; + break; + + default: + break; + } + + return(ADC_Threshold_Value); +} + +/******************************************************************************* +* Function Name : ADC_ITConfig +* Description : Enables or disables the specified ADC interrupts. +* Input : - ADC_IT: specifies the ADC interrupts sources to be enabled +* or disabled. +* This parameter can be one of the following values: +* - ADC_IT_EndOfConversion: End of conversion interrupt. +* - ADC_IT_AnalogWDG: Analog watchdog interrupt. +* - ADC_NewState: new state of the specified ADC interrupts. +* (ADC_Newstate can be ENABLE or DISABLE). +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ITConfig(u16 ADC_IT, FunctionalState ADC_NewState) +{ + if (ADC_NewState == ENABLE) + { + /* Enable the interrupt */ + ADC->CR |= ADC_IT; + } + else + { + /* Disable the interrupt */ + ADC->CR &= ~ADC_IT; + } +} + +/******************************************************************************* +* Function Name : ADC_StandbyModeCmd +* Description : Enable or disable the standby mode. +* Input : ADC_NewState: new state of the ADC standby mode. +* (ADC_Newstate can be ENABLE or DISABLE). +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StandbyModeCmd(FunctionalState ADC_NewState) +{ + if (ADC_NewState == ENABLE) + { + /* Enable the standby mode */ + ADC->CR |= ADC_STANDBY_MODE_MASK; + } + else + { + /* Disable the standby mode */ + ADC->CR &= ~ADC_STANDBY_MODE_MASK; + } +} + +/******************************************************************************* +* Function Name : ADC_Cmd +* Description : Power on or put in reset mode the ADC peripheral. +* Input : ADC_NewState: new state of the ADC peripheral. +* (ADC_Newstate can be ENABLE or DISABLE). +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Cmd(FunctionalState ADC_NewState) +{ + if (ADC_NewState == ENABLE) + { + /* Enable the ADC */ + ADC->CR |= ADC_CMD_MASK; + } + else + { + /* Disable the ADC */ + ADC->CR &= ~ADC_CMD_MASK; + } +} + +/******************************************************************************* +* Function Name : ADC_ConversionCmd +* Description : Start or stop the ADC conversion in the selected mode. +* Input : ADC_Conversion: the conversion command. +* This parameter can be one of the following values: +* - ADC_Conversion_Start: Start the conversion. +* - ADC_Conversion_Stop: Stop the Conversion. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ConversionCmd(u16 ADC_Conversion) +{ + if (ADC_Conversion == ADC_Conversion_Start) + { + /* Start the ADC conversion */ + ADC->CR |= ADC_Conversion_Start; + } + else + { + /* Stop the ADC conversion */ + ADC->CR &= ADC_Conversion_Stop; + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_ahbapb.c b/uc_str912/prj_blinky_complex_startup/src/91x_ahbapb.c new file mode 100644 index 0000000..41489ac --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_ahbapb.c @@ -0,0 +1,177 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the AHBAPB software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_ahbapb.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#define AHBAPB_SplitCounter_Mask 0xFFE0FFFF +#define AHBAPB_SetTimeOut_Mask 0xFFFFFFE0 +#define AHBAPB_Address_Mask 0xFEFFFFFF +#define AHBAPB_FLAG_RW_Mask 0x01000000 +/******************************************************************************* +* Function Name : AHBAPB_DeInit +* Description : Deinitializes the AHBAPBx peripheral registers to their default +* reset values. +* Input : AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx) +{ + AHBAPBx->BCR = 0x00000000; + AHBAPBx->BSR = 0x00000000; +} +/******************************************************************************* +* Function Name : AHBAPB_Init +* Description : Initializes the AHBAPBx peripheral according to the specified +* parameters in the AHBAPB_InitStruct . +* Input :- AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* - AHBAPB_InitStruct: pointer to a AHBAPB_InitTypeDef structure that +* contains the configuration information for the specified AHBAPB +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + + if(AHBAPB_InitStruct->AHBAPB_Split == AHBAPB_Split_Enable) + { + /* Set SPLITEN bit;*/ + AHBAPBx->BCR |= AHBAPB_Split_Enable; + /*Split_CNT bits[20:16]*/ + AHBAPBx->BCR &= AHBAPB_SplitCounter_Mask; + AHBAPBx->BCR |= (AHBAPB_InitStruct->AHBAPB_SplitCounter)<<16; + } + else + { + /*/ Clear SPLITEN bit;*/ + AHBAPBx->BCR &= AHBAPB_Split_Disable; + } + /*APB Time out*/ + if(AHBAPB_InitStruct->AHBAPB_Error == AHBAPB_Error_Enable) + { + /* Set ERREN bit*/ + AHBAPBx->BCR |= AHBAPB_Error_Enable; + /*Time ouit counter*/ + AHBAPBx->BCR &= AHBAPB_SetTimeOut_Mask; + AHBAPBx->BCR |= AHBAPB_InitStruct->AHBAPB_SetTimeOut; + } + else + { + /* Clear ERREN bit*/ + AHBAPBx->BCR &= AHBAPB_Error_Disable; + } +} + +/******************************************************************************* +* Function Name : AHBAPB_StructInit +* Description : Initialize the AHBAPB Init Structure parameters +* Input : AHBAPB_InitStruct : pointer to a AHBAPB_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + /* Reset AHBAPB init structure parameters values */ + AHBAPB_InitStruct->AHBAPB_Split = AHBAPB_Split_Enable; + AHBAPB_InitStruct->AHBAPB_SplitCounter = 0xFF; + AHBAPB_InitStruct->AHBAPB_Error = AHBAPB_Error_Enable; + AHBAPB_InitStruct->AHBAPB_SetTimeOut = 0xFF; + +} + +/******************************************************************************* +* Function Name : AHBAPB_GetFlagStatus +* Description : Checks whether the specified AHBAPB flag is set or not. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* - AHBAPB_FLAG_RW : Access type flag +* Output : None +* Return : The new state of AHBAPB_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + if(AHBAPB_FLAG == AHBAPB_FLAG_RW) + { + if ((AHBAPBx->PAER & AHBAPB_FLAG_RW_Mask) == RESET) + { + return RESET; + } + else + { + return SET; + } + } + else + { + if ((AHBAPBx->BSR & AHBAPB_FLAG) == RESET) + { + return RESET; + } + else + { + return SET; + } + } +} +/******************************************************************************* +* Function Name : AHBAPB_ClearFlag +* Description : Clears the AHBAPBx flags. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: flags to clear. This parameter one of the +* following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + /* Clear the flag */ + AHBAPBx->BSR &= AHBAPB_FLAG; +} +/******************************************************************************* +* Function Name : AHBAPB_GetPeriphAddrError +* Description : Gets the AHBAPB error address peripherals. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* Output : None +* Return : The Peropheral address error +*******************************************************************************/ +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx) +{ + u32 AHBAPB_Address = 0x00000000; + + /*Return Oeripheral address without RW bit*/ + AHBAPB_Address = (AHBAPBx->PAER)& AHBAPB_Address_Mask; + return (AHBAPB_Address); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_can.c b/uc_str912/prj_blinky_complex_startup/src/91x_can.c new file mode 100644 index 0000000..3a9ebce --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_can.c @@ -0,0 +1,769 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_can.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the CAN software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_can.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ +/* Description : Form the Mask and Arbitration registers value to filter */ +/* a range of identifiers or a fixed identifier, for standard*/ +/* and extended IDs */ +/*----------------------------------------------------------------------------*/ +#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) +#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) + +#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) +#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) + +#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) +#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) + +#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) +#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) + +#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) +#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) + +#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) +#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) +#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) +#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) + +/* macro to format the timing register value from the timing parameters*/ +#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) + +/* Private variables ---------------------------------------------------------*/ +/* array of pre-defined timing parameters for standard bitrates for AHB@48MHz */ +u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ + CAN_TIMING(13, 6, 4, 24), /* 0x5CD7 100 kbit/s 24 13 6 4 24 */ + CAN_TIMING(13, 6, 4, 19), /* 0xyyyy 125 kbit/s 20 13 6 4 20 */ + CAN_TIMING( 6, 3, 5, 19), /* 0xyyyy 250 kbit/s 10 6 3 5 19 */ + CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ + CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ +}; + +/* Private function prototypes -----------------------------------------------*/ +static u32 GetFreeIF(void); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_DeInit (void) +{ + /* Reset the CAN registers values*/ + + SCU_APBPeriphReset(__CAN,ENABLE); /*CAN peripheral is under Reset */ + SCU_APBPeriphReset(__CAN,DISABLE); /*CAN peripheral Reset off*/ + + +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +* contains the configuration information for the CAN peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); + CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); + CAN_LeaveInitMode(); + CAN_LeaveTestMode(); +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its reset value. +* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ +/* Reset CAN init structure parameters values */ + CAN_InitStruct->CAN_ConfigParameters = 0x0; + CAN_InitStruct->CAN_Bitrate = 0x2301; +} + +/******************************************************************************* +* Function Name : CAN_SetBitrate +* Description : Setups a standard CAN bitrate. +* Input : bitrate: specifies the bit rate. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetBitrate(u32 bitrate) +{ +// CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ + CAN->BTR = bitrate; /* write the predefined timing value */ + CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ +} + +/******************************************************************************* +* Function Name : CAN_SetTiming +* Description : Setups the CAN timing with specific parameters +* Input : - tseg1: specifies Time Segment before the sample point. +* This parameter must be a number between 1 and 16. +* - tseg2: Time Segment after the sample point. This parameter +* must be a number between 1 and 8. +* - sjw: Synchronisation Jump Width. This parameter must be +* a number between 1 and 4. +* - brp: Baud Rate Prescaler. This parameter must be a number +* between 1 and 1024. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) +{ + CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); + CAN->BRPR = ((brp-1) >> 6) & 0x0F; +} + +/******************************************************************************* +* Function Name : GetFreeIF +* Description : Searchs the first free message interface, starting from 0. +* Input : None +* Output : None +* Return : A free message interface number (0 or 1) if found, else 2 +*******************************************************************************/ +static u32 GetFreeIF(void) +{ + if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) + return 0; + else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) + return 1; + else + return 2; +} + +/******************************************************************************* +* Function Name : CAN_SetUnusedMsgObj +* Description : Configures the message object as unused +* Input : msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = 0; + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = 0; + + CAN->sMsgObj[msg_if].MCR = 0; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetTxMsgObj +* Description : Configures the message object as TX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].A1R = 0; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; + } + else + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetRxMsgObj +* Description : Configures the message object as RX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* - idLow: specifies the low part of the identifier range used +* for acceptance filtering. +* - idHigh: specifies the high part of the identifier range +* used for acceptance filtering. +* - singleOrFifoLast: specifies the end-of-buffer indicator. +* This parameter can be one of the following values: +* - TRUE: for a single receive object or a FIFO receive +* object that is the last one of the FIFO. +* - FALSE: for a FIFO receive object that is not the +* last one. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); + } + else + { + CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_InvalidateAllMsgObj +* Description : Configures all the message objects as unused. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_InvalidateAllMsgObj(void) +{ + u32 i=0; + for (i = 0; i < 32; i++) + CAN_SetUnusedMsgObj(i); +} + + +/******************************************************************************* +* Function Name : CAN_ReleaseMessage +* Description : Releases the message object +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_ReleaseMessage(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SendMessage +* Description : Start transmission of a message +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* : - pCanMsg: pointer to the message structure containing data +* to transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) +{ + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_TXOK; + + /* read the Arbitration and Message Control*/ + CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + /* update the contents needed for transmission*/ + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_ReceiveMessage +* Description : Gets the message, if received. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - release: specifies the message release indicator. +* This parameter can be one of the following values: +* - TRUE: the message object is released when getting +* the data. +* - FALSE: the message object is not released. +* - pCanMsg: pointer to the message structure where received +* data is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) +{ + if (!CAN_IsMessageWaiting(msgobj)) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + /* read the message contents*/ + CAN->sMsgObj[1].CMR = CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_CLRINTPND + | (release ? CAN_CMR_TXRQSTNEWDAT : 0) + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[1].CRR = 1 + msgobj; + + if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_WaitEndOfTx +* Description : Waits until current transmission is finished. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission ended +* - ERROR: Transmission did not occur yet +*******************************************************************************/ +ErrorStatus CAN_WaitEndOfTx(void) +{ + if ((CAN->SR & CAN_SR_TXOK) == 0) + { + return ERROR; + } + CAN->SR &= ~CAN_SR_TXOK; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicSendMessage +* Description : Starts transmission of a message in BASIC mode. This mode +* does not use the message RAM. +* Input : pCanMsg: Pointer to the message structure containing data to +* transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) +{ + /* clear NewDat bit in IF2 to detect next reception*/ + CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; + + CAN->SR &= ~CAN_SR_TXOK; + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + /* request transmission*/ + if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) + { + return ERROR; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicReceiveMessage +* Description : Gets the message in BASIC mode, if received. This mode does +* not use the message RAM. +* Input : pCanMsg: pointer to the message structure where message is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) +{ + if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + CAN->sMsgObj[1].CMR = CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_EnterInitMode +* Description : Switchs the CAN into initialization mode. This function must +* be used in conjunction with CAN_LeaveInitMode(). +* Input : InitMask: specifies the CAN configuration in normal mode. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterInitMode(u8 InitMask) +{ + CAN->CR = InitMask | CAN_CR_INIT; + CAN->SR = 0; /* reset the status*/ +} + +/******************************************************************************* +* Function Name : CAN_LeaveInitMode +* Description : Leaves the initialization mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterInitMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveInitMode(void) +{ + CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); +} + +/******************************************************************************* +* Function Name : CAN_EnterTestMode +* Description : Switchs the CAN into test mode. This function must be used in +* conjunction with CAN_LeaveTestMode(). +* Input : TestMask: specifies the configuration in test modes. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterTestMode(u8 TestMask) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR |= TestMask; +} + +/******************************************************************************* +* Function Name : CAN_LeaveTestMode +* Description : Leaves the current test mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterTestMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveTestMode(void) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); + CAN->CR &= ~CAN_CR_TEST; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseTxMessage +* Description : Releases the transmit message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseTxMessage(u32 msgobj) +{ + CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[0].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseRxMessage +* Description : Releases the receive message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseRxMessage(u32 msgobj) +{ + CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[1].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_IsMessageWaiting +* Description : Tests the waiting status of a received message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object has +* received a message waiting to be copied, else 0. +*******************************************************************************/ +u32 CAN_IsMessageWaiting(u32 msgobj) +{ + return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsTransmitRequested +* Description : Tests the request status of a transmitted message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message is requested +* to transmit, else 0. +*******************************************************************************/ +u32 CAN_IsTransmitRequested(u32 msgobj) +{ + return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsInterruptPending +* Description : Tests the interrupt status of a message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message has an +* interrupt pending, else 0. +*******************************************************************************/ +u32 CAN_IsInterruptPending(u32 msgobj) +{ + return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsObjectValid +* Description : Tests the validity of a message object (ready to use). +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object is +* valid, else 0. +*******************************************************************************/ +u32 CAN_IsObjectValid(u32 msgobj) +{ + return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_dma.c b/uc_str912/prj_blinky_complex_startup/src/91x_dma.c new file mode 100644 index 0000000..db6ad6e --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_dma.c @@ -0,0 +1,1125 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_dma.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the DMA software functions +* needed to access all DMA registers. +******************************************************************************** +* History:v 1.0 +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ + +# include"91x_dma.h" +# include"91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + + +/* DMA Masks "used" only in this module */ + +#define DMA_Width_DES_MASK 0xFF1FFFFF +#define DMA_Width_SRC_MASK 0xFFE3FFFF +#define DMA_Bst_DES_MASK 0xFFFC7FFF +#define DMA_Bst_SRC_MASK 0xFFFF8FFF +#define DMA_FlowCntrl_Mask 0xFFFFC7FF +#define DMA_TrsfSisze_Mask 0xFFFFF000 +#define SRC_Mask 0xFFFFFFE1 +#define DES_Mask 0xFFFFFC3F +#define DMA_TCIE 0x80000000 +#define DMA_ChannelDESInc 0x08000000 +#define DMA_ChannelSRCInc 0x04000000 +#define DMA_BufferChannel 0x20000000 +#define DMA_HaltChannel 0x00040000 +#define DMA_LockChannel 0x00010000 +#define DMA_CacheChannel 0x40000000 +#define DMA_ChannelActive 0x00020000 +#define DMA_Enable 0x00000001 +#define DMA_ChannelEnable 0x00000001 + + + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : DMA_ITMaskConfig +* Description : Enables or disables the specified DMA_Channelx Mask interrupt. +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -DMA_ITMask: specifies the DMA interrupt mask source to be enabled or disabled. +* This parameter can be: +* - DMA_ITMask_IE (Interrupt error mask). +* - DMA_ITMask_ITC (Terminal count interrupt mask). +* - DMA_ITMask_ALL ( All interrupts mask) +* +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask , FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Mask the Interrupt */ + { + DMA_Channelx-> CCNF |= DMA_ITMask ; + } + + else /* Disable the Interrupt Mask*/ + { + DMA_Channelx-> CCNF &= ~ DMA_ITMask ; + } +} + + + + + +/******************************************************************************* +* Function Name : DMA_ITConfig +* Description : Enables or disables the DMA_Channelx Terminal Count interrupt. +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enable the Terminal Count Interrupt */ + { + DMA_Channelx->CC |= DMA_TCIE ; + } + + else /* Disable the Terminal Count Interrupt */ + { + DMA_Channelx-> CC &= ~ DMA_TCIE ; + } +} + + +/******************************************************************************** +* Function Name : DMA_SyncConfig +* Description : Enables or disables synchronization logic for the corresponding DMA Request Signal. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SyncConfig(u16 SRCReq, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enable the synchronization logic for the corresponding DMA Request Signal */ + { + + DMA->SYNR &= ~ SRCReq ; + + } + + else /* Disable the synchronization logic for the corresponding DMA Request Signal. */ + { + DMA->SYNR |= SRCReq ; + + } +} + + +/******************************************************************************** +* Function Name : DMA_SetSReq +* Description : Set the DMA to generate a Single transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SetSReq(u16 SRCReq) + +{ /* Set the DMA to generate a Single transfer request for the corresponding DMA Request Source */ + DMA->SSRR |= SRCReq ; +} + + + + +/******************************************************************************** +* Function Name : DMA_SetLSReq +* Description : Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : None. +*******************************************************************************/ + +void DMA_SetLSReq(u16 SRCReq ) +{ /* Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source */ + DMA->SLSRR |= SRCReq ; +} + + +/******************************************************************************** +* Function Name : DMA_SetBReq +* Description : Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SetBReq(u16 SRCReq) + +{ /* Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source */ + DMA->SBRR |= SRCReq ; +} + + + +/******************************************************************************** +* Function Name : DMA_SetLBReq +* Description : Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SetLBReq(u16 SRCReq) + +{ /* Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source */ + DMA->SLBRR |= SRCReq ; +} + + +/******************************************************************************** +* Function Name : DMA_GetSReq +* Description : Check for a specific source if it request a Single transfer . +* Input : +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetSReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Single transfer . */ + if ( (DMA->SSRR & SRCReq )!= RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + + +/******************************************************************************** +* Function Name : DMA_GetLSReq +* Description : Check for a specific source if it request a Last Single transfer . +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetLSReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Last Single transfer . */ + if ( (DMA->SLSRR & SRCReq)!= RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + +/******************************************************************************** +* Function Name : DMA_GetBReq +* Description : Check for a specific source if it request a Burst transfer . +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetBReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Burst transfer . */ + if (( DMA->SBRR & SRCReq ) != RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + +/******************************************************************************** +* Function Name : DMA_GetLSReq +* Description : Check for a specific source if it request a Last Burst transfer . +* Input : +* Input : +* - SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetLBReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Last Burst transfer . */ + if ( ( DMA->SLBRR & SRCReq ) != RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + + + +/******************************************************************************* +* Function Name : DMA_ChannelHalt +* Description : Enables DMA requests or ignore extra source DMA requests for + the specified channel. +* Input : + -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. + -NewState: new state of the specified DMA_Channelx mask interrupt. + This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelHalt(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enables DMA requests */ + + { + DMA_Channelx->CCNF |= DMA_HaltChannel ; + } + + else /* Ignore extra source DMA request */ + { + DMA_Channelx->CCNF &= ~ DMA_HaltChannel ; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelLockTrsf +* Description : Enables or disables the Locked Transfers Feature for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Locked transfers enabled on channel x */ + + { + DMA_Channelx->CCNF |= DMA_LockChannel ; + } + + else /* Locked transfers disabled on channel xt */ + { + DMA_Channelx->CCNF &= ~ DMA_LockChannel; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelCache +* Description : Enables or disables the cacheability Feature for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelCache (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Cacheability Feature enabled on channelx */ + + { + DMA_Channelx->CC |= DMA_CacheChannel ; + } + + else /* Cacheability Feature disabled on channelx */ + { + DMA_Channelx->CC &= ~ DMA_CacheChannel ; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelBuffering +* Description : Enables or disables the Buffering Feature for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Cacheability Feature enabled on channel x */ + + { + DMA_Channelx->CC |= DMA_BufferChannel ; + } + + else /* Cacheability Feature disabled on channel xt */ + { + DMA_Channelx->CC &= ~ DMA_BufferChannel ; + } +} + +/******************************************************************************* +* Function Name : MA_ChannelProt0Mod +* Description : Sets The User or Privileged mode for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -Prot0Mode: Specifies the Privileged mode Or the User mode. +* This parameter can be: +* - DMA_PrevilegedMode +* - DMA_UserMode +* +* +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelProt0Mode (DMA_Channel_TypeDef * DMA_Channelx, u32 Prot0Mode) + +{ + if (Prot0Mode==DMA_PrevilegedMode) /* Privileged mode */ + { + DMA_Channelx->CC |= DMA_PrevilegedMode ; + } + + else /* User mode */ + { + DMA_Channelx->CC &= DMA_UserMode ; + } +} + + + + + +/******************************************************************************* +* Function Name : DMA_ChannelSRCIncConfig +* Description : Enables or disables the Source address incrementation after each transfer for +* the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* The Source address is incremented after each transfer */ + + { + DMA_Channelx->CC |= DMA_ChannelSRCInc ; + } + + else /* The Source address is not incremented after each Transfer */ + { + DMA_Channelx->CC &= ~ DMA_ChannelSRCInc ; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelDESIncConfig +* Description : Enables or disables the Destination address incrementation after each transfer for +* the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* The Destination address is incremented after each transfer */ + + { + DMA_Channelx->CC |= DMA_ChannelDESInc ; + } + + else /* The Destination address is not incremented after each Transfer */ + { + DMA_Channelx->CC &= ~ DMA_ChannelDESInc ; + } +} + + + +/******************************************************************************** +* Function Name : DMA_GetChannelStatus +* Description : Checks the status of DMA channelx ( Enabled or Disabled). +* - ChannelIndx:specifies the DMA Channel to be checked. +* This parameter can be: +* - Channel0 +* - Channel1 +* - Channel2 +* - Channel3 +* - Channel4 +* - Channel5 +* - Channel6 +* - Channel7 +* Output : None. +* +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ) + +{ + + if ( ( DMA->ENCSR & (1 << ChannelIndx )) != RESET ) + { + return SET; /* Channelx Enabled */ + } + + else + + { + + return RESET; /* Channelx Disabled */ + + } + +} + + + +/******************************************************************************** +* Function Name : DMA_GetITStatus +* Description : Checks the status of Terminal Count and Error interrupts request after and before Masking. +* Input : +* - ChannelIndx:specifies the DMA Channel to be checked. +* This parameter can be: +* - Channel0 +* - Channel1 +* - Channel2 +* - Channel3 +* - Channel4 +* - Channel5 +* - Channel6 +* - Channel7 +* +*. - DMA_ITReq: specifies the DMA interrupt request status to be checked. +* This parameter can be: +* +* - DMA_IS +* - DMA_TCS +* - DMA_ES +* - DMA_TCRS +* - DMA_ERS. +* +* Output : None. +* +* Return : SET or RESET. +*******************************************************************************/ + + +ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq) + +{ + u32 DMAReg = 0; + + switch(DMA_ITReq) + + { + + case (DMA_IS): /*The status of the interrupts after masking : logical or of all Interrupts after Masking*/ + DMAReg = DMA->ISR; + break; + + + + case (DMA_TCS): /* The status of the Terminal count request after masking */ + DMAReg = DMA->TCISR; + break; + + + case (DMA_ES): /* The status of the error request after masking */ + DMAReg = DMA->EISR; + break; + + + case (DMA_TCRS): /* Indicates if the DMA channel is requesting a transfer complete (terminal count Interrupt) prior to masking or Not. */ + DMAReg = DMA->TCRISR; + break; + + case (DMA_ERS): /* Indicates if the DMA channel is requesting an Error Interrupt prior to masking or Not. */ + DMAReg = DMA->ERISR; + break; + + + } + + if((DMAReg &(1 << ChannelIndx )) != RESET ) + + { + return SET; + } + + else + + { + + return RESET; + + + } + +} + + +/******************************************************************************** +* Function Name : DMA_ClearIT +* Description : Clears The Interrupt pending bits for termnal count or Error interrupts for a specified DMA Channel. +* - ChannelIndx:specifies the DMA Channel to be checked. +* This parameter can be: +* - Channel0 +* - Channel1 +* - Channel2 +* - Channel3 +* - Channel4 +* - Channel5 +* - Channel6 +* - Channel7 +* - DMA_ITClr : Specifies the DMA interrupt pending to be cleared. +*. This parameter can be: +* - DMA_TCC +* - DMA_EC. +* +* Output : None. + +* Return : SET or RESET. +*******************************************************************************/ + + +void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr) + +{ + + + switch(DMA_ITClr) + + { + + case (DMA_TCC): /* Clear The status of the Terminal count interrupt on the corresponding channel.*/ + DMA->TCICR |=(1 << ChannelIndx ); + break; + + + + case (DMA_EC): /* Clear The status of the error interrupt on the corresponding channel.*/ + DMA->EICR |=(1 << ChannelIndx ); + break; + + + + } + + + +} + + +/******************************************************************************* +* Function Name : DMA_Cmd(FunctionalState NewState) +* Description : Enables or disables the DMA peripheral. +* +* Input : +* -NewState: new state of the DMA. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_Cmd(FunctionalState NewState) + +{ + if (NewState==ENABLE) /* ENABLE the DMA peripheral */ + + { + DMA-> CNFR |= DMA_Enable ; + } + + else /* DISABLE the DMA peripheral */ + { + DMA-> CNFR &= ~ DMA_Enable ; + } +} + + + +/******************************************************************************* +* Function Name : DMA_ChannelCmd +* Description : Enables or disables the specified DMA_Channelx +* +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelCmd (DMA_Channel_TypeDef *DMA_Channelx,FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enable The Channelx */ + + { + DMA_Channelx->CCNF |= DMA_ChannelEnable ; + } + + else /* Disable The Channelx */ + { + DMA_Channelx-> CCNF &= ~ DMA_ChannelEnable ; + } +} + + + +/******************************************************************************** +* Function Name : DMA_GetChannelActiveStatus +* Description : Checks The DMA_Channelx FIFO if it has data or not. +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* +* +* Output : None. +* +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx ) + +{ + + if ( ( DMA_Channelx->CCNF & DMA_ChannelActive) != RESET ) + { + return SET; /* The DMA_Channelx FIFO has data */ + } + + else + + { + + return RESET; /* No data in the DMA_Channelx FIFO */ + + + } + +} + + +/******************************************************************************** +* Function Name : DMA_DeInit +* Description : Initializes the DMA peripheral registers to their default reset values. +* +* +* Input : None +* +* Output : None. +* +* Called Functions: +* +* - SCU_AHBPeriphReset: Function defined in the System clock Unit "scu.c". +* +* +* Return : None +*******************************************************************************/ + + +void DMA_DeInit(void) + +{ + + SCU_AHBPeriphReset(__DMA, ENABLE); /*DMA peripheral is under Reset " Reset on"*/ + SCU_AHBPeriphReset(__DMA, DISABLE); /*DMA peripheral Reset off*/ +} + + + +/******************************************************************************** +* Function Name : DMA_StructInit +* Description : Fills each DMA_InitStruct member with its reset value. +* Input : +* -DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized. +* +* Output : None. +* +* Return : None +*******************************************************************************/ + + +void DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct) + +{ + + /* Initialize The current source address */ + DMA_InitStruct-> DMA_Channel_SrcAdd =0x0000000; + + + /* Initialize The current Destination address */ + DMA_InitStruct->DMA_Channel_DesAdd=0x00000000; + + + + /* Initialize The Linked List Items */ + DMA_InitStruct->DMA_Channel_LLstItm=0x00000000 ; + + + + /* Initialize The Destination width */ + DMA_InitStruct->DMA_Channel_DesWidth= DMA_DesWidth_Byte; + + + + /* Initialize The source width */ + DMA_InitStruct->DMA_Channel_SrcWidth= DMA_SrcWidth_Byte; + + + /* Initialize The Burst Size for the Destination */ + DMA_InitStruct->DMA_Channel_DesBstSize= DMA_DesBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the Destination width */ + + + + /* Initialize The Burst Size for the Source*/ + DMA_InitStruct->DMA_Channel_SrcBstSize= DMA_SrcBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the source width */ + + /* Initialize The Flow control and transfer type for the DMA transfer */ + DMA_InitStruct->DMA_Channel_FlowCntrl=DMA_FlowCntrlt0_DMA; /* memory to memory transfer with DMA as flow controller */ + + + /* Initialize The Transfer Size */ + DMA_InitStruct->DMA_Channel_TrsfSize =0x00; + + + + /* Initialize the DMA source request peripheral :"This field is ignored if the source of the transfer is from memory" */ + DMA_InitStruct->DMA_Channel_Src =0x00; + + + + /* Initialize the DMA Destination request peripheral :"This field is ignored if the destination of the transfer is to memory.*/ + + DMA_InitStruct->DMA_Channel_Des=0x00; + + +} + + + + +/******************************************************************************** +* Function Name : DMA_Init +* Description : Initializes the DMA_Channelx according to the specified parameters +* in the DMA_InitStruct . +* +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -DMA_InitStruct: pointer to a DMA_InitTypeDef structure +* ( Structure Config to be load in DMA Registers). . +* +* Output : None. +* +* Return : None +*******************************************************************************/ + + +void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct) + +{ + + + + /* Select the DMA source peripheral request */ + DMA_Channelx->CCNF &= SRC_Mask; + DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Src; + + + /* Select the flow controller and the transfer type */ + DMA_Channelx->CCNF &= DMA_FlowCntrl_Mask; + DMA_Channelx->CCNF |=DMA_InitStruct->DMA_Channel_FlowCntrl; + + + /* Select the DMA Destination peripheral request*/ + DMA_Channelx->CCNF &= DES_Mask; + DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Des; + + /* Set the source address */ + DMA_Channelx->SRC = DMA_InitStruct-> DMA_Channel_SrcAdd ; + + + /* Set the destination address */ + + DMA_Channelx->DES = DMA_InitStruct->DMA_Channel_DesAdd ; + + + + /* Set the linked list Items address */ + DMA_Channelx->LLI = DMA_InitStruct->DMA_Channel_LLstItm ; + + + /* Set The Destination width */ + DMA_Channelx->CC &= DMA_Width_DES_MASK; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesWidth; + + + /* Set The Source width */ + DMA_Channelx->CC &= DMA_Width_SRC_MASK; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_SrcWidth; + + /* Set The Burst Size for the Destination */ + DMA_Channelx->CC &= DMA_Bst_DES_MASK; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesBstSize; + + /* Set The Burst Size for the Source */ + DMA_Channelx->CC &= DMA_Bst_SRC_MASK; + DMA_Channelx->CC |=DMA_InitStruct->DMA_Channel_SrcBstSize; + + + /* Initialize The Transfer Size for the Source */ + DMA_Channelx->CC &= DMA_TrsfSisze_Mask; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_TrsfSize; + + +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_emi.c b/uc_str912/prj_blinky_complex_startup/src/91x_emi.c new file mode 100644 index 0000000..deadae8 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_emi.c @@ -0,0 +1,167 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_emi.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the EMI software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_emi.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* These constant variables are used as masks to handle the EMI registers. */ + +#define EMI_PageModeRead_TL_Mask 0xFFFFF3FF +#define EMI_PageModeRead_Sel_Mask 0xFFFFFEFF +#define EMI_MemWidth_Mask 0xFFFFFFCF +#define EMI_WriteProtect_Mask 0xFFFFFEF7 + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : EMI_DeInit +* Description : Deinitializes the EMI peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ + +void EMI_DeInit(void) +{ + + SCU_AHBPeriphReset(__EMI, ENABLE); /* EMI peripheral under Reset */ + SCU_AHBPeriphReset(__EMI,DISABLE ); /* EMI not under Reset */ + +} + +/******************************************************************************* +* Function Name : EMI_StructInit +* Description : Fills the EMI_InitTypeDef structure member with its reset +* value. +* Input : EMI_InitStruct : pointer to a EMI_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ + +void EMI_StructInit( EMI_InitTypeDef *EMI_InitStruct) +{ + + /* Number of bus turnaround cycles added between read and write accesses.*/ + /*This member can be 0x01,0x02,0x03, ....0xF (Reset value:0xF "15 cycles"*/ + + EMI_InitStruct->EMI_Bank_IDCY =0xF; + + + /* Number of wait states for read accesses*/ + /*This member can be: 0x01,0x02,0x03, ....0x1F (Reset value:0x1F "31 cycles"*/ + + EMI_InitStruct->EMI_Bank_WSTRD =0x1F; + + + /* Number of wait states for write accesses*/ + /*This member can be: 0x01,0x02,0x03, ....0x1F (Reset value:0x1F "31 cycles"*/ + + EMI_InitStruct->EMI_Bank_WSTWR =0x1F; + + /*Output enable assertion delay from chip select assertion*/ + /*This member can be: 0x01,0x02,0x03, ....0xF (Reset value:0x01 "1 cycle"*/ + + EMI_InitStruct->EMI_Bank_WSTROEN =0x01; + + + /*Write enable assertion delay from chip select assertion*/ + /*This member can be: 0x01,0x02,0x03, ....0xF (Reset value:0x00 "0 cycle"*/ + + EMI_InitStruct->EMI_Bank_WSTWEN =0x00; + + + /*This member Controls the memory width*/ + /*This member can be :"EMI_Width_Byte" = 8 bits width or "EMI_Width_HalfWord" = 16 bits width*/ + + EMI_InitStruct->EMI_Bank_MemWidth = EMI_Width_Byte; + + + /*Write protection feature */ + /*This member can be :"EMI_Bank_NonWriteProtect" = No write protection or "EMI_Bank_WriteProtect" = bank is write protected*/ + + EMI_InitStruct-> EMI_Bank_WriteProtection= EMI_Bank_NonWriteProtect; + + + /* page transfer length for page mode read */ + /*This member can be :"EMI_4Data" = 4 transfers burst or "EMI_8Data" = 8 transfers burst*/ + + EMI_InitStruct->EMI_PageModeRead_TransferLength= EMI_4Data; + + /*Select or deselect the page mode read*/ + /*This member can be :"EMI_NormalMode" =Normal Mode or "EMI_PageModeRead" = Page Mode Read*/ + + EMI_InitStruct->EMI_PageModeRead_Selection = EMI_NormalMode; + + +} + +/******************************************************************************* +* Function Name : EMI_Init +* Description : Initializes EMI peripheral according to the specified +* parameters in the EMI_InitStruct. + +* Input : EMI_Bankx:where x can be 0,1,2 or 3 to select the EMI Bank. + EMI_InitStruct: pointer to a EMI_InitTypeDef structure + ( Structure Config to be loaded in EMI Registers). . + +* Output : None +* Return : None +*******************************************************************************/ + +void EMI_Init( EMI_Bank_TypeDef* EMI_Bankx, EMI_InitTypeDef* EMI_InitStruct) + +{ + + EMI_Bankx->ICR = EMI_InitStruct-> EMI_Bank_IDCY ; + + EMI_Bankx->RCR = EMI_InitStruct->EMI_Bank_WSTRD ; + + EMI_Bankx->WCR = EMI_InitStruct->EMI_Bank_WSTWR ; + + EMI_Bankx->OECR = EMI_InitStruct->EMI_Bank_WSTROEN; + + EMI_Bankx->WECR = EMI_InitStruct->EMI_Bank_WSTWEN ; + + EMI_Bankx->BCR &= EMI_MemWidth_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_Bank_MemWidth; + + EMI_Bankx->BCR &= EMI_WriteProtect_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_Bank_WriteProtection; + + EMI_Bankx->BCR &= EMI_PageModeRead_TL_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_PageModeRead_TransferLength; + + EMI_Bankx->BCR &= EMI_PageModeRead_Sel_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_PageModeRead_Selection; + + +} + + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_fmi.c b/uc_str912/prj_blinky_complex_startup/src/91x_fmi.c new file mode 100644 index 0000000..fb558ad --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_fmi.c @@ -0,0 +1,519 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the FMI software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_fmi.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define TIMEOUT 0xFFFFFF /* Timeout value */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/******************************************************************************* +* Function Name : FMI_BankRemapConfig +* Description : Configure the addresses and sizes of bank 0 and bank 1. +* Input1 : FMI_BootBankSize: specifies the boot bank size. +* This parameter can be one of the following values: +* - 0x0: 32KBytes. +* - 0x1: 64KBytes. +* - 0x2: 128KBytes. +* - 0x3: 256KBytes. +* - 0x4: 512KBytes. +* .... +* - 0xB: 64MBytes. +* Input2 : FMI_NonBootBankSize: specifies the non boot bank size. +* This parameter can be one of the following values: +* - 0x0: 8KBytes. +* - 0x1: 16KBytes. +* - 0x2: 32KBytes. +* - 0x3: 64KBytes. +* .... +* - 0xD: 64MBytes. +* Input3 : FMI_BootBankAddress: specifies the address of the boot bank. +* Input4 : FMI_NonBootBankAddress: specifies the address of the non +* boot bank. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress) +{ + FMI->BBSR = FMI_BootBankSize; + FMI->NBBSR = FMI_NonBootBankSize; + FMI->BBADR = (FMI_BootBankAddress >> 2); + FMI->NBBADR = (FMI_NonBootBankAddress >> 2); + FMI->CR |= 0x18; /* Enable bank 1 */ +} + +/******************************************************************************* +* Function Name : FMI_Config +* Description : Configure the FMI. +* Input1 : FMI_ReadWaitState: specifies the needed read wait states. +* This parameter can be one of the following values: +* - FMI_READ_WAIT_STATE_1: One read wait state. +* - FMI_READ_WAIT_STATE_2: Two read wait states. +* - FMI_READ_WAIT_STATE_3: Three read wait states. +* Input2 : FMI_WriteWaitState: specifies the needed write wait states. +* This parameter can be one of the following values: +* - FMI_WRITE_WAIT_STATE_1: One write wait state. +* - FMI_WRITE_WAIT_STATE_2: Two write wait states. +* Input3 : FMI_PWD: specifies the power down mode status. +* This parameter can be one of the following values: +* - FMI_PWD_ENABLE: Enable the PWD. +* - FMI_PWD_DISABLE: Disable the PWD. +* Input4 : FMI_LVDEN: specifies the low voltage detector status. +* This parameter can be one of the following values: +* - FMI_LVD_ENABLE: Enable the LVD. +* - FMI_LVD_DISABLE: Disable the LVD. +* Input5 : FMI_FreqRange: specifies the working frequency range. +* This parameter can be one of the following values: +* - FMI_FREQ_LOW: Low working frequency (up to 66MHz). +* - FMI_FREQ_HIGH: High working frequency (above 66MHz) . +* Output : None +* Return : None +*******************************************************************************/ +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange) +{ + /* Configure the write wait state value */ + if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1) + { + FMI->CR |= FMI_WRITE_WAIT_STATE_1; + } + else + { + FMI->CR &= FMI_WRITE_WAIT_STATE_0; + } + + /* Write a write flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x60; + + /* Configure the flash configuration register */ + *(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03; +} + +/******************************************************************************* +* Function Name : FMI_EraseSector +* Description : Erase the needed sector. +* Input : FMI_Sector: specifies the sector to be erased. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseSector(vu32 FMI_Sector) +{ + /* Write an erase set-up command to the sector */ + *(vu16 *)FMI_Sector = 0x20; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Sector = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_EraseBank +* Description : Erase the needed bank. +* Input : FMI_Bank: specifies the bank to be erased. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseBank(vu32 FMI_Bank) +{ + /* Write a bank erase set-up command to the bank */ + *(vu16 *)FMI_Bank = 0x80; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_WriteHalfWord +* Description : Write a halfword to the needed Flash memory address. +* Input 1 : FMI_Address: specifies the address offset where the data will +* be written. +* Input 2 : FMI_Data: the needed data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data) +{ + /* Write a program command to the sector to be written */ + *(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40; + + /* Write the halfword to the destination address */ + *(vu16 *)FMI_Address = FMI_Data; +} + +/******************************************************************************* +* Function Name : FMI_WriteOTPHalfWord +* Description : Write a halfword to the needed OTP sector address. +* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset +* where the data will be written. +* This parameter can be one of the following values: +* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0. +* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0. +* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1. +* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1. +* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2. +* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2. +* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3. +* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3. +* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4. +* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4. +* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5. +* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5. +* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6. +* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6. +* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7. +* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7. +* Input 2 : FMI_OTPData: The needed OTP data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData) +{ + /* Write a write OTP command to the needed address */ + *(vu16 *)(FMI_BANK_1) = 0xC0; + + /* Write the halfword to the destination address */ + *(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData; +} + +/******************************************************************************* +* Function Name : FMI_ReadWord +* Description : Read the correspondent data. +* Input : FMI_Address: specifies the needed address. +* Output : None +* Return : The data contained in the specified address. +*******************************************************************************/ +u32 FMI_ReadWord(u32 FMI_Address) +{ + return(*(u32*)FMI_Address); +} + +/******************************************************************************* +* Function Name : FMI_ReadOTPData +* Description : Read data from the OTP sector. +* Input : FMI_OTPAddress: specifies the address of the data to be read. +* This parameter can be one of the following values: +* - FMI_OTP_WORD_0: FMI bank 0 sector 0. +* - FMI_OTP_WORD_1: FMI bank 0 sector 1. +* - FMI_OTP_WORD_2: FMI bank 0 sector 2. +* - FMI_OTP_WORD_3: FMI bank 0 sector 3. +* - FMI_OTP_WORD_4: FMI bank 0 sector 4. +* - FMI_OTP_WORD_5: FMI bank 0 sector 5. +* - FMI_OTP_WORD_6: FMI bank 0 sector 6. +* - FMI_OTP_WORD_7: FMI bank 0 sector 7. +* Output : None +* Return : The needed OTP words. +*******************************************************************************/ +u32 FMI_ReadOTPData(u8 FMI_OTPAddress) +{ + u32 OTP_Data = 0x0; + /* write a read OTP sector command */ + *(vu16 *)(FMI_BANK_1) = 0x98; + + /* Read the correspondent data */ + OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress)); + + /* Write a read array command */ + *(vu16 *)(FMI_BANK_1) = 0xFF; + + return OTP_Data; +} + +/******************************************************************************* +* Function Name : FMI_GetFlagStatus +* Description : Check whether the specified FMI flag is set or not. +* Input1 : FMI_Flag: flag to check. +* This parameter can be one of the following values: +* - FMI_FLAG_SPS: Sector Protection Status Flag. +* - FMI_FLAG_PSS: Program Suspend Status Flag. +* - FMI_FLAG_PS: Program Status Flag. +* - FMI_FLAG_ES: Erase Status Flag. +* - FMI_FLAG_ESS: Erase Suspend Status Flag. +* - FMI_FLAG_PECS: FPEC Status Flag. +* Input2 : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank) +{ + u16 FMI_Status_Register = 0; + + /* Write a read status register command */ + *(vu16 *)FMI_Bank = 0x70; + + /* Wait until operation completion */ + while(!((*(vu16 *)FMI_Bank) & 0x80)); + + /* Read the status register */ + FMI_Status_Register = *(vu16 *)FMI_Bank; + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if((FMI_Status_Register & FMI_Flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_GetReadWaitStateValue +* Description : Get the current Read wait state value. +* Input : None +* Output : None +* Return : The current read wait states value. +*******************************************************************************/ +u16 FMI_GetReadWaitStateValue(void) +{ + u16 FMI_Configuration_Register = 0; + /* Write a read flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash configuration register */ + FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3; + + /* Return the wait states value */ + return FMI_Configuration_Register; +} + +/******************************************************************************* +* Function Name : FMI_GetWriteWaitStateValue +* Description : Get the current write wait state value. +* Input : None +* Output : None +* Return : The current write wait states value. +*******************************************************************************/ +u16 FMI_GetWriteWaitStateValue(void) +{ + return ((u16)((FMI->CR & 0x100) >> 8)); +} + +/******************************************************************************* +* Function Name : FMI_SuspendEnable +* Description : Suspend command enable. +* Input : FMI_Bank: specifies the bank to be suspended. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_SuspendEnable(vu32 FMI_Bank) +{ + /* Write a suspend command to the bank */ + *(vu16 *)FMI_Bank = 0xB0; +} + +/******************************************************************************* +* Function Name : FMI_ResumeEnable +* Description : Resume the suspended command. +* Input : FMI_Bank: specifies the suspended bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ResumeEnable(vu32 FMI_Bank) +{ + /* Write a resume command to the bank */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_ClearFlag +* Description : Clear the FMI Flags on the correspondent bank. +* Input : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ClearFlag(vu32 FMI_Bank) +{ + /* Write a clear status register command */ + *(vu16 *)FMI_Bank = 0x50; +} + +/******************************************************************************* +* Function Name : FMI_WriteProtectionCmd +* Description : Enable or disable the write protection for the needed sector. +* Input1 : FMI_Sector: specifies the sector to be protected or +* unprotected. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Input2 : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: Enable the protection. +* - DISABLE: Disable the protection. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState) +{ + if (FMI_NewState == ENABLE) + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0x01; + *(vu16*)FMI_Sector = 0xFF; + } + else /* DISABLE */ + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0xD0; + *(vu16*)FMI_Sector = 0xFF; + } +} + +/******************************************************************************* +* Function Name : FMI_GetWriteProtectionStatus +* Description : Get the write protection status for the needed sector. +* Input : FMI_Sector_Mask: specifies the needed sector mask. +* This parameter can be one of the following values: +* - FMI_B0S0_MASK: FMI bank 0 sector 0. +* - FMI_B0S1_MASK: FMI bank 0 sector 1. +* - FMI_B0S2_MASK: FMI bank 0 sector 2. +* - FMI_B0S3_MASK: FMI bank 0 sector 3. +* - FMI_B0S4_MASK: FMI bank 0 sector 4. +* - FMI_B0S5_MASK: FMI bank 0 sector 5. +* - FMI_B0S6_MASK: FMI bank 0 sector 6. +* - FMI_B0S7_MASK: FMI bank 0 sector 7. +* - FMI_B1S0_MASK: FMI bank 1 sector 0. +* - FMI_B1S1_MASK: FMI bank 1 sector 1. +* - FMI_B1S2_MASK: FMI bank 1 sector 2. +* - FMI_B1S3_MASK: FMI bank 1 sector 3. +* Output : None +* Return : The Protection Status of the needed sector. +* - RESET: The needed sector is not write protected. +* - SET : The needed sector is write protected. +*******************************************************************************/ +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask) +{ + u16 Protection_Level_1_Register = 0; + /* Write a read flash protection level 1 register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash protection level 1 register */ + Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + if (Protection_Level_1_Register &= FMI_Sector_Mask) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_WaitForLastOperation +* Description : Wait until the last operation (Write halfword, Write OTP +* halfword, Erase sector and Erase bank) completion. +* Input : FMI_Bank: specifies the bank where the operation is on going. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : The timeout status. +* This parameter can be one of the following values: +* - FMI_TIME_OUT_ERROR: Timeout error occurred. +* - FMI_NO_TIME_OUT_ERROR: No timeout error. +*******************************************************************************/ +u8 FMI_WaitForLastOperation(vu32 FMI_Bank) +{ + u32 Time_Out = 0; + + /* Write a read status register command */ + *(vu16 *)(FMI_Bank) = 0x70; + + /* Wait until operation compeletion */ + while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT )) + { + Time_Out ++; /* Time Out */ + } + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if (Time_Out == TIMEOUT) + { + return FMI_TIME_OUT_ERROR; + } + else + { + return FMI_NO_TIME_OUT_ERROR; + } +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_gpio.c b/uc_str912/prj_blinky_complex_startup/src/91x_gpio.c new file mode 100644 index 0000000..f2d0941 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_gpio.c @@ -0,0 +1,407 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the GPIO software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_gpio.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + + /* Reset the GPIO registers values */ + if(GPIOx == GPIO0) + { + SCU_APBPeriphReset(__GPIO0,ENABLE); + SCU_APBPeriphReset(__GPIO0,DISABLE); + SCU->GPIOTYPE[0x00] = 0x0000 ; + SCU->GPIOOUT[0x00] = 0x0000; + SCU->GPIOIN[0x00] = 0x0000; + } + + if(GPIOx == GPIO1) + { + SCU_APBPeriphReset(__GPIO1,ENABLE); + SCU_APBPeriphReset(__GPIO1,DISABLE); + SCU->GPIOTYPE[0x01] = 0x0000 ; + SCU->GPIOOUT[0x01] = 0x0000; + SCU->GPIOIN[0x01] = 0x0000; + } + + if(GPIOx == GPIO2) + { + SCU_APBPeriphReset(__GPIO2,ENABLE); + SCU_APBPeriphReset(__GPIO2,DISABLE); + SCU->GPIOTYPE[0x02] = 0x0000 ; + SCU->GPIOOUT[0x02] = 0x0000; + SCU->GPIOIN[0x02] = 0x0000; + } + + if(GPIOx == GPIO3) + { + SCU_APBPeriphReset(__GPIO3,ENABLE); + SCU_APBPeriphReset(__GPIO3,DISABLE); + SCU->GPIOTYPE[0x03] = 0x0000 ; + SCU->GPIOOUT[0x03] = 0x0000; + SCU->GPIOIN[0x03] = 0x0000; + } + + if(GPIOx == GPIO4) + { + SCU_APBPeriphReset(__GPIO4,ENABLE); + SCU_APBPeriphReset(__GPIO4,DISABLE); + SCU->GPIOTYPE[0x04] = 0x0000 ; + SCU->GPIOOUT[0x04] = 0x0000; + SCU->GPIOIN[0x04] = 0x0000; + SCU->GPIOANA = 0x00; + } + + if(GPIOx == GPIO5) + { + SCU_APBPeriphReset(__GPIO5,ENABLE); + SCU_APBPeriphReset(__GPIO5,DISABLE); + SCU->GPIOTYPE[0x05] = 0x0000 ; + SCU->GPIOOUT[0x05] = 0x0000; + SCU->GPIOIN[0x05] = 0x0000; + } + + if(GPIOx == GPIO6) + { + SCU_APBPeriphReset(__GPIO6,ENABLE); + SCU_APBPeriphReset(__GPIO6,DISABLE); + SCU->GPIOTYPE[0x06] = 0x0000 ; + SCU->GPIOOUT[0x06] = 0x0000; + SCU->GPIOIN[0x06] = 0x0000; + } + + if(GPIOx == GPIO7) + { + SCU_APBPeriphReset(__GPIO7,ENABLE); + SCU_APBPeriphReset(__GPIO7,DISABLE); + SCU->GPIOOUT[0x07] = 0xAAAA; + SCU->GPIOOUT[0x07] = 0x0000; + SCU->GPIOIN[0x07] = 0x0000; + } + + if(GPIOx == GPIO8) + { + SCU_APBPeriphReset(__GPIO8,ENABLE); + SCU_APBPeriphReset(__GPIO8,DISABLE); + SCU->GPIOEMI = 0x00; + } + + if(GPIOx == GPIO9) + { + SCU_APBPeriphReset(__GPIO9,ENABLE); + SCU_APBPeriphReset(__GPIO9,DISABLE); + SCU->GPIOEMI = 0x00; + } +} +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct . +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Select pin direction */ + u8 PinNumber = 0; + u8 Counter = 0; + u8 GPIO_Number = 0; + + GPIO_Number = GPIO_GetGPIONumber(GPIOx); + + + if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput) + { + GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin; + } + else + { + GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin; + } + + for (Counter = 0; Counter < 8;Counter++) + { + /*Search pin number*/ + PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <> Counter) == 1) + { + /*Output ALternate 0*/ + SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2)); + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1) + { + /*Output ALternate 1*/ + SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2) + { + /*Output ALternate 2*/ + SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3) + { + /*Output ALternate 3*/ + SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2); + } + + /*Type configuration: PushPull or Open Collector*/ + SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector) + { + /*Open Drain configuration*/ + SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter; + } + + /*IP Connected disable*/ + SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable) + { + /*IP Connected enable*/ + SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter; + } + } + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Initialize the GPIO Init Structure parameters +* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Direction = GPIO_PinInput; + GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull; + GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable; + GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1; +} + +/******************************************************************************* +* Function Name : GPIO_ReadBit +* Description : Reads the specified port pin +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* Output : None +* Return : The port pin value +*******************************************************************************/ +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin) +{ + if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET ) + { + return Bit_SET; + } + else + { + return Bit_RESET; + } +} + +/******************************************************************************* +* Function Name : GPIO_Read +* Description : Reads the specified GPIO data port +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO data port word value. +*******************************************************************************/ +u8 GPIO_Read(GPIO_TypeDef* GPIOx) +{ + return (GPIOx->DR[0x3FC]); +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* - BitVal: this parameter specifies the value to be written +* to the selected bit. +* BitVal must be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal) +{ + if(BitVal == Bit_SET) + { + GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin; + } + else + { + GPIOx->DR[GPIO_Pin <<2] = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes the passed value in the selected data GPIOx port +* register. +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - PortVal: the value to be written to the data port register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal) +{ + GPIOx->DR[0x3FC] = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_EMIConfig +* Description : Enables or disables GPIO 8 and 9 in EMI mode. +* Input : - NewState: new state of the EMI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EMIConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SCU->GPIOEMI = 0x01; + } + else + { + SCU->GPIOEMI = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_ANAPinConfig +* Description : Enables or disables pins from GPIO 4 in Analogue mode. +* Input :- GPIO_ANAChannel: selects the ADC channel pin. +* This parameter can be one of the following values: +* GPIO_ANAChannel0 +* GPIO_ANAChannel1 +* GPIO_ANAChannel2 +* GPIO_ANAChannel3 +* GPIO_ANAChannel4 +* GPIO_ANAChannel5 +* GPIO_ANAChannel6 +* GPIO_ANAChannel7 +* GPIO_ANAChannelALL +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState) +{ + + if(NewState == ENABLE) + { + if(GPIO_ANAChannel == GPIO_ANAChannelALL) + { + SCU->GPIOOUT[4] = 0x0000; + SCU->GPIOIN[4] = 0x00; + } + else + { + SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1)); + SCU->GPIOIN[4] &= ~GPIO_ANAChannel; + } + SCU->GPIOANA |= GPIO_ANAChannel; + + } + else + { + SCU->GPIOANA &= ~GPIO_ANAChannel; + } +} + +/******************************************************************************* +* Function Name : GPIO_GetGPIONumber +* Description : searche the GPIO number. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO number +*******************************************************************************/ +u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx) +{ + + if(GPIOx == GPIO1) + { + return 1; + } + if(GPIOx == GPIO2) + { + return 2; + } + if(GPIOx == GPIO3) + { + return 3; + } + if(GPIOx == GPIO4) + { + return 4; + } + if(GPIOx == GPIO5) + { + return 5; + } + if(GPIOx == GPIO6) + { + return 6; + } + if(GPIOx == GPIO7) + { + return 7; + } + if(GPIOx == GPIO8) + { + return 8; + } + if(GPIOx == GPIO9) + { + return 9; + } + return 0; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_i2c.c b/uc_str912/prj_blinky_complex_startup/src/91x_i2c.c new file mode 100644 index 0000000..9f15adb --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_i2c.c @@ -0,0 +1,616 @@ +/******************** (C) COPYRIGHT 2005 STMicroelectronics ******************** +* File Name : 91x_i2c.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the I2C software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_i2c.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* I2C IT enable */ +#define I2C_IT_Enable 0x01 +#define I2C_IT_Disable 0xFE + +/* I2C Peripheral Enable/Disable */ +#define I2C_PE_Set 0x20 +#define I2C_PE_Reset 0xDF + +/* Address direction bit */ +#define I2C_ADD0_Set 0x01 +#define I2C_ADD0_Reset 0xFE + +/* I2C START Enable/Disable */ +#define I2C_Start_Enable 0x08 +#define I2C_Start_Disable 0xF7 + +/* I2C STOP Enable/Disable */ +#define I2C_Stop_Enable 0x02 +#define I2C_Stop_Disable 0xFD + +/* I2C Masks */ +#define I2C_Frequency_Mask 0x1F +#define I2C_AddressHigh_Mask 0xF9 +#define I2C_OwnAddress_Mask 0x0300 +#define I2C_StandardMode_Mask 0x7f +#define I2C_FastMode_Mask 0x80 +#define I2C_Event_Mask 0x3FFF +#define I2C_HeaderSet_Mask 0xF1 +#define I2C_HeaderReset_Mask 0xFE + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : I2C_DeInit +* Description : Deinitializes the I2C peripheral registers to their default +* reset values. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + if (I2Cx == I2C0) + { + /* Reset the I2C0 registers values */ + SCU_APBPeriphReset(__I2C0, ENABLE); + SCU_APBPeriphReset(__I2C0, DISABLE); + } + if (I2Cx == I2C1) + { + /* Reset the I2C1 registers values */ + SCU_APBPeriphReset(__I2C1, ENABLE); + SCU_APBPeriphReset(__I2C1, DISABLE); + } +} + +/******************************************************************************* +* Function Name : I2C_Init +* Description : Initializes the I2C peripheral according to the specified +* parameters in the I2C_InitTypeDef structure. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* +* - I2C_InitStruct: pointer to an I2C_InitTypeDef structure that +* contains the configuration information for the specified I2C +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u16 wResult = 0x0F; + u32 dPCLK = 25000000; + + /* Get PCLK frequency value */ + dPCLK = SCU_GetPCLKFreqValue()*1000; + /* Disable I2C peripheral to set FR[2:0] bits */ + I2C_Cmd (I2Cx, DISABLE); + /* Clear frequency FR[2:0] bits */ + I2Cx->OAR2 &= I2C_Frequency_Mask; + /* Set frequency bits depending on PCLK value */ + if ((dPCLK <1667000) & (dPCLK > 10000000)) + I2Cx->OAR2 |= 0x20; + else if (dPCLK < 26670000) + I2Cx->OAR2 |= 0x40; + else if (dPCLK < 40000000) + I2Cx->OAR2 |= 0x60; + else if (dPCLK < 53330000) + I2Cx->OAR2 |= 0x80; + else if (dPCLK < 66000000) + I2Cx->OAR2 |= 0xA0; + else if (dPCLK < 80000000) + I2Cx->OAR2 |= 0xC0; + else if (dPCLK < 100000000) + I2Cx->OAR2 |= 0xE0; + I2C_Cmd (I2Cx, ENABLE); + + /* Configure general call */ + if (I2C_InitStruct->I2C_GeneralCall == I2C_GeneralCall_Enable) + { + /* Enable general call */ + I2Cx->CR |= I2C_GeneralCall_Enable; + } + else + { + /* Disable general call */ + I2Cx->CR &= I2C_GeneralCall_Disable; + } + /* Configure acknowledgement */ + if (I2C_InitStruct->I2C_Ack == I2C_Ack_Enable) + { + /* Enable acknowledgement */ + I2Cx->CR |= I2C_Ack_Enable; + } + else + { + /* Disable acknowledgement */ + I2Cx->CR &= I2C_Ack_Disable; + } + + /* Configure LSB own address */ + I2Cx->OAR1 = I2C_InitStruct->I2C_OwnAddress; + /* Clear MSB own address ADD[9:8] bits */ + I2Cx->OAR2 &= I2C_AddressHigh_Mask; + /* Set MSB own address value */ + I2Cx->OAR2 |= (I2C_InitStruct->I2C_OwnAddress & I2C_OwnAddress_Mask)>>7; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_CLKSpeed <= 100000) + { + /* Standard mode speed calculate */ + wResult = ((dPCLK/I2C_InitStruct->I2C_CLKSpeed)-7)/2; + /* Set speed value and clear FM/SM bit for standard mode in LSB clock divider */ + I2Cx->CCR = wResult & I2C_StandardMode_Mask; + } + /* Configure speed in fast mode */ + else if (I2C_InitStruct->I2C_CLKSpeed <= 400000) + { + /* Fast mode speed calculate */ + wResult = ((dPCLK/I2C_InitStruct->I2C_CLKSpeed)-9)/3; + /* Set speed value and set FM/SM bit for fast mode in LSB clock divider */ + I2Cx->CCR = wResult | I2C_FastMode_Mask; + } + /* Set speed in MSB clock divider */ + I2Cx->ECCR = wResult >>7; +} + +/******************************************************************************* +* Function Name : I2C_StructInit +* Description : Initialize the I2C Init Structure parameters +* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /* Initialize the I2C_CLKSpeed member */ + I2C_InitStruct->I2C_CLKSpeed = 5000; + + /* Initialize the I2C_OwnAddress member */ + I2C_InitStruct->I2C_OwnAddress = 0x0; + + /* Initialize the I2C_GeneralCall member */ + I2C_InitStruct->I2C_GeneralCall = I2C_GeneralCall_Disable; + + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; +} + +/******************************************************************************* +* Function Name : I2C_Cmd +* Description : Enables or disables the specified I2C peripheral. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - NewState: new state of the I2C peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C peripheral by setting twice the PE bit on the CR register */ + I2Cx->CR |= I2C_PE_Set; + I2Cx->CR |= I2C_PE_Set; + } + else + { + /* Disable the I2C peripheral */ + I2Cx->CR &= I2C_PE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTART +* Description : Generates I2C communication START condition. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* +* - NewState: new state of the Start condition. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateStart(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a START condition */ + I2Cx->CR |= I2C_Start_Enable; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR &= I2C_Start_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTOP +* Description : Generates I2C communication STOP condition. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* +* - NewState: new state of the Stop condition. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a SIOP condition */ + I2Cx->CR |= I2C_Stop_Enable; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR &= I2C_Stop_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_AcknowledgeConfig +* Description : Enables or disables I2C acknowledge feature. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - NewState: new state of the Acknowledgement. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR |= I2C_Ack_Enable; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR &= I2C_Ack_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_ITConfig +* Description : Enables or disables I2C interrupt feature. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - NewState: new state of the specified I2C interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_ITConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C interrupt */ + I2Cx->CR |= I2C_IT_Enable; + } + else + { + /* Disable the I2C interrupt */ + I2Cx->CR &= I2C_IT_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_ReadRegister +* Description : Reads any I2C register and returns its value. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_Register: the I2C register to be read. This parameter +* can be one of the following values: +* - I2C_CR: CR register. +* - I2C_SR1: SR1 register. +* - I2C_SR2: SR2 register. +* - I2C_CCR: CCR register. +* - I2C_OAR1: OAR1 register. +* - I2C_OAR2: OAR2 register. +* - I2C_DR: DR register. +* - I2C_ECCR: ECCR register. +* Output : None +* Return : The value of the register passed as parameter +*******************************************************************************/ +u8 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + /* Return the selected register value */ + if (I2Cx == I2C0) + { + return (*(u8 *)(I2C0_BASE + I2C_Register)); + } + if (I2Cx == I2C1) + { + return (*(u8 *)(I2C1_BASE + I2C_Register)); + } + return 0; +} + +/******************************************************************************* +* Function Name : I2C_GetFlagStatus +* Description : Checks whether the specified I2C flag is set or not. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_FLAG: flag to check. This parameter can be one of the +* following values: +* - I2C_FLAG_SB: Start bit flag +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Adress matched flag +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* Output : None +* Return : The NewState of the I2C_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u16 I2C_FLAG) +{ + u16 wFlag1=0, wFlag2=0, wTmp=0; + + wFlag1 = I2Cx->SR2; + wFlag1 = wFlag1<<8; + wFlag2 = I2Cx->CR & 0x04; + + /* Get all the I2C flags in a unique register*/ + wTmp = (((I2Cx->SR1 | (wFlag1)) & I2C_Event_Mask) | (wFlag2<<12)); + + /* Check the status of the specified I2C flag */ + if((wTmp & I2C_FLAG) != RESET) + { + /* Return SET if I2C_FLAG is set */ + return SET; + } + else + { + /* Return RESET if I2C_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : I2C_ClearFlag +* Description : Clears the I2C Flag passed as a parameter +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_FLAG: flag to check. This parameter can be one of the +* following values: +* - I2C_FLAG_SB: Start bit flag +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Adress matched flag +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* - parameter needed in the case that the flag to be cleared +* need a write in one register +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u16 I2C_FLAG, ...) +{ + u8 bTmp = (u8)*((u32 *) & I2C_FLAG + sizeof(I2C_FLAG)); + + /* flags that need a read of the SR2 register to be cleared */ + if ((I2C_FLAG==I2C_FLAG_ADD10) || (I2C_FLAG==I2C_FLAG_EVF) || (I2C_FLAG==I2C_FLAG_BERR) || (I2C_FLAG==I2C_FLAG_ARLO) | + (I2C_FLAG==I2C_FLAG_STOPF) ||(I2C_FLAG==I2C_FLAG_AF) || (I2C_FLAG==I2C_FLAG_ENDAD)) + { + /* Read the SR2 register */ + I2Cx->SR2; + + /* Two flags need a second step to be cleared */ + switch (I2C_FLAG) + { + case I2C_FLAG_ADD10: + /* Send the MSB 10bit address passed as second parameter */ + I2Cx->DR = bTmp; + break; + case I2C_FLAG_ENDAD: + /* Write to the I2C_CR register by setting PE bit */ + I2Cx->CR |= I2C_PE_Set; + break; + } + } + + /* flags that need a read of the SR1 register to be cleared */ + else if (I2C_FLAG==I2C_FLAG_SB || I2C_FLAG==I2C_FLAG_ADSL || I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* three flags need a second step to be cleared */ + if (I2C_FLAG == I2C_FLAG_SB) + { + /* Send the address byte passed as second parameter */ + I2Cx->DR = bTmp; + } + else if (I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* return the received byte in the variable passed as second parameter */ + bTmp=I2Cx->DR; + } + } + + /* flags that need to disable the I2C interface */ + else if ( I2C_FLAG==I2C_FLAG_M_SL || I2C_FLAG==I2C_FLAG_GCAL) + { + I2C_Cmd(I2Cx, DISABLE); + I2C_Cmd(I2Cx, ENABLE); + } +} + +/******************************************************************************* +* Function Name : I2C_Send7bitAddress +* Description : Transmits the address byte to select the slave device. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - Address: specifies the slave address which will be transmitted +* - Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. This parameter can be one of the +* following values +* - I2C_MODE_TRANSMITTER: Transmitter mode +* - I2C_MODE_RECEIVER: Receiver mode +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 Direction) +{ + /* Test on the direction to define the read/write bit */ + if (Direction == I2C_MODE_RECEIVER) + { + /* Set the address bit0 for read */ + Address |= I2C_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= I2C_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/******************************************************************************* +* Function Name : I2C_SendData +* Description : Send a data byte. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - bData : the byte to be sent +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, u8 bData) +{ + /* Write in the DR register the byte to be sent */ + I2Cx->DR = bData; +} + +/******************************************************************************* +* Function Name : I2C_ReceiveData +* Description : Read the received byte. +* Input : - I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* Output : None +* Return : The received byte +*******************************************************************************/ +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Return from the DR register the received byte */ + return I2Cx->DR; +} + +/******************************************************************************* +* Function Name : I2C_GetLastEvent +* Description : Get the Last happened I2C Event. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* Output : None +* Return : The Last happened Event. +*******************************************************************************/ +u16 I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + u16 wFlag1=0, wLastEvent=0; + wFlag1 = I2Cx->SR2; + wFlag1 = wFlag1<<8; + /* Get the last event value from I2C status register */ + wLastEvent = (((I2Cx->SR1 | (wFlag1)) & I2C_Event_Mask)); + /* Return the last event */ + return wLastEvent; +} + +/******************************************************************************* +* Function Name : I2C_CheckEvent +* Description : Checks whether the Last I2C Event is equal to the one passed +* as parameter. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_EVENT: the event to check. This parameter can be one of +* the following values: +* - I2C_EVENT_SLAVE_ADDRESS_MATCHED +* - I2C_EVENT_SLAVE_BYTE_RECEIVED +* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED +* - I2C_EVENT_MASTER_MODE_SELECT +* - I2C_EVENT_MASTER_MODE_SELECTED +* - I2C_EVENT_MASTER_BYTE_RECEIVED +* - I2C_EVENT_MASTER_BYTE_TRANSMITTED +* - I2C_EVENT_MASTER_MODE_ADDRESS10 +* - I2C_EVENT_SLAVE_STOP_DETECTED +* - I2C_EVENT_SLAVE_ACK_FAILURE +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Last event is equal to the I2C_Event +* - ERROR: Last event is different from the I2C_Event +*******************************************************************************/ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,u16 I2C_EVENT) +{ + u16 wLastEvent = I2C_GetLastEvent(I2Cx); + + /* Check whther the last event is equal to I2C_EVENT */ + if (wLastEvent == I2C_EVENT) + { + /* Return SUCCESS when last event is equal to I2C_EVENT */ + return SUCCESS; + } + else + { + /* Return ERROR when last event is different from I2C_EVENT */ + return ERROR; + } +} + +/******************* (C) COPYRIGHT 2005 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_lib.c b/uc_str912/prj_blinky_complex_startup/src/91x_lib.c new file mode 100644 index 0000000..c0eadbb --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_lib.c @@ -0,0 +1,281 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all peripherals pointers + : initialization. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#define EXT + +/* Standard include ----------------------------------------------------------*/ +#include "91x_map.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#ifdef DEBUG + +/******************************************************************************* +* Function Name : debug +* Description : this function initialize peripherals pointers +* Input : no one +* Output : no one +* Return : no one +*******************************************************************************/ +void debug(void) +{ + + +/************************* DMA *************************/ + +#ifdef _DMA + DMA = (DMA_TypeDef *)DMA_BASE; +#endif /* _DMA */ + +/************************* DMA *************************/ + + +#ifdef _DMA_Channel0 + DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE; +#endif /* _DMA_Channel0 */ + +#ifdef _DMA_Channel1 + DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE; +#endif /* _DMA_Channel1 */ + +#ifdef _DMA_Channel2 + DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE; +#endif /* _DMA_Channel2 */ + +#ifdef _DMA_Channel3 + DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE; +#endif /* _DMA_Channel3 */ + +#ifdef _DMA_Channel4 + DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE; +#endif /* _DMA_Channel4 */ + +#ifdef _DMA_Channel5 + DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE; +#endif /* _DMA_Channel5*/ + + +#ifdef _DMA_Channel6 + DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE; +#endif /* _DMA_Channel6 */ + +#ifdef _DMA_Channel7 + DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE; +#endif /* _DMA_Channel7 */ + + + + /************************* EMI *************************/ + +#ifdef _EMI_Bank0 + EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE; +#endif /* _EMI_Bank0 */ + +#ifdef _EMI_Bank1 + EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE; +#endif /* _EMI_Bank1 */ + +#ifdef _EMI_Bank2 + EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE; +#endif /* _EMI_Bank2 */ + +#ifdef _EMI_Bank3 + EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE; + #endif /* _EMI_Bank3 */ + + + +/************************* AHBAPB *************************/ + +#ifdef _AHBAPB0 + AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE; +#endif /* _AHBAPB0 */ + +#ifdef _AHBAPB1 + AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE; +#endif /*_AHBAPB1 */ + + + +/************************* FMI *************************/ + +#ifdef _FMI + FMI = (FMI_TypeDef *)FMI_BASE; +#endif /* _FMI */ + +/************************* VIC *************************/ + +#ifdef _VIC0 + VIC0 = (VIC_TypeDef *)VIC0_BASE; +#endif /* _VIC0 */ + +#ifdef _VIC1 + VIC1 = (VIC_TypeDef *)VIC1_BASE; +#endif /* _VIC1 */ + +/************************* WIU *************************/ + +#ifdef _WIU + WIU = (WIU_TypeDef *)WIU_BASE; +#endif /* _WIU */ + +/************************* TIM *************************/ + +#ifdef _TIM0 + TIM0 = (TIM_TypeDef *)TIM0_BASE; +#endif /* _TIM0 */ + +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *)TIM1_BASE; +#endif /* _TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *)TIM2_BASE; +#endif /* _TIM2 */ + +#ifdef _TIM3 + TIM3 = (TIM_TypeDef *)TIM3_BASE; +#endif /* _TIM3 */ + +/************************* GPIO ************************/ + +#ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; +#endif /* _GPIO0 */ + +#ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; +#endif /* _GPIO1 */ + +#ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; +#endif /* _GPIO2 */ + +#ifdef _GPIO3 + GPIO3 = (GPIO_TypeDef *)GPIO3_BASE; +#endif /* _GPIO3 */ + +#ifdef _GPIO4 + GPIO4 = (GPIO_TypeDef *)GPIO4_BASE; +#endif /* _GPIO4 */ + +#ifdef _GPIO5 + GPIO5 = (GPIO_TypeDef *)GPIO5_BASE; +#endif /* _GPIO5 */ + +#ifdef _GPIO6 + GPIO6 = (GPIO_TypeDef *)GPIO6_BASE; +#endif /* _GPIO6 */ + +#ifdef _GPIO7 + GPIO7 = (GPIO_TypeDef *)GPIO7_BASE; +#endif /* _GPIO7 */ + +#ifdef _GPIO8 + GPIO8 = (GPIO_TypeDef *)GPIO8_BASE; +#endif /* _GPIO8 */ + +#ifdef _GPIO9 + GPIO9 = (GPIO_TypeDef *)GPIO9_BASE; +#endif /* _GPIO9 */ + +/************************* RTC *************************/ + +#ifdef _RTC + RTC = (RTC_TypeDef *)RTC_BASE; +#endif /* _RTC */ + +/************************* PRCCU ***********************/ + +#ifdef _SCU + SCU = (SCU_TypeDef *)SCU_BASE; +#endif /* _PRCCU */ + +/************************** MC *************************/ + +#ifdef _MC + MC = (MC_TypeDef *)MC_BASE; +#endif /* _MC */ + +/************************* UART ************************/ + +#ifdef _UART0 + UART0 = (UART_TypeDef *)UART0_BASE; +#endif /* _UART0 */ + +#ifdef _UART1 + UART1 = (UART_TypeDef *)UART1_BASE; +#endif /* _UART1 */ + +#ifdef _UART2 + UART2 = (UART_TypeDef *)UART2_BASE; +#endif /* _UART2 */ + +/************************* SSP *************************/ + +#ifdef _SSP0 + SSP0 = (SSP_TypeDef *)SSP0_BASE; +#endif /* _SSP0 */ + +#ifdef _SSP1 + SSP1 = (SSP_TypeDef *)SSP1_BASE; +#endif /* _SSP1 */ + +/************************* CAN *************************/ + +#ifdef _CAN + CAN = (CAN_TypeDef *)CAN_BASE; +#endif /* _CAN */ + +/************************* ADC *************************/ + +#ifdef _ADC + ADC = (ADC_TypeDef *)ADC_BASE; +#endif /* _ADC */ + +/************************* WDG *************************/ + +#ifdef _WDG + WDG = (WDG_TypeDef *)WDG_BASE; +#endif /* _WDG */ + +/************************* I2C *************************/ + +#ifdef _I2C0 + I2C0 = (I2C_TypeDef *)I2C0_BASE; +#endif /* _I2C0 */ + +#ifdef _I2C1 + I2C1 = (I2C_TypeDef *)I2C1_BASE; +#endif /* _I2C1 */ +/********************** ENET **************************/ +#ifdef _ENET + ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE; + ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE; +#endif /* _ENET */ +} +#endif /* DEBUG */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_mc.c b/uc_str912/prj_blinky_complex_startup/src/91x_mc.c new file mode 100644 index 0000000..d3ca96a --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_mc.c @@ -0,0 +1,932 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_mc.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the MC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_mc.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +#define MC_ODCS_Set 0x0001 +#define MC_ODCS_Reset 0x00FE + +#define MC_CMS_Set 0x0004 +#define MC_CMS_Reset 0x00FB + +#define MC_CPC_Set 0x0008 +#define MC_CTC_Set 0x0010 + +#define MC_PCE_Set 0x0020 +#define MC_PCE_Reset 0xFFDF + +#define MC_TCE_Set 0x0040 +#define MC_TCE_Reset 0x00BF + +#define MC_DTE_Set 0x0080 +#define MC_DTE_Reset 0x007F + +#define MC_TCB_Set 0x0004 +#define MC_TCB_Reset 0x00FB + +#define MC_STC_Set 0x0008 + +#define MC_TES_Set 0x0010 +#define MC_TES_Reset 0x00EF + +#define MC_CCPT_Set 0x0020 +#define MC_CCPT_Reset 0x005F + +#define MC_DISEST_Set 0x0040 +#define MC_DISEST_Reset 0x003F + +#define MC_DTS_Set 0x0001 +#define MC_DTS_Reset 0x00FE + +#define MC_SDT_Set 0x0002 + +#define MC_C0SE_Set 0x0004 +#define MC_C0SE_Reset 0x00FB + +#define MC_CUSE_Set 0x0008 +#define MC_CUSE_Reset 0x00F7 + +#define MC_CVSE_Set 0x0010 +#define MC_CVSE_Reset 0x00EF + +#define MC_CWSE_Set 0x0020 +#define MC_CWSE_Reset 0x00D0 + +#define MC_RSE_Set 0x0040 +#define MC_RSE_Reset 0x00BF + +#define MC_GPI_Set 0x0080 +#define MC_GPI_Reset 0x007F + +#define MC_PUH_Set 0x0020 +#define MC_PUH_Reset 0x005F +#define MC_PUL_Set 0x0010 +#define MC_PUL_Reset 0x006F + +#define MC_PVH_Set 0x0008 +#define MC_PVH_Reset 0x0077 +#define MC_PVL_Set 0x0004 +#define MC_PVL_Reset 0x007B + +#define MC_PWH_Set 0x0002 +#define MC_PWH_Reset 0x007D +#define MC_PWL_Set 0x0001 +#define MC_PWL_Reset 0x007E + +#define MC_ODS_Set 0x0040 +#define MC_ODS_Reset 0xFF3F + +#define MC_ESC_Clear 0x4321 + +#define MC_PCR1_TIN_MASK 0xFFFC +#define MC_OPR_Mask 0x0040 +#define MC_UDCS_Mask 0x0002 +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/****************************************************************************** +* Function Name : MC_DeInit +* Description : Deinitializes MC peripheral registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_DeInit(void) +{ + /* MC peripheral is under Reset */ + SCU_APBPeriphReset(__MC, ENABLE); + + /* MC peripheral Reset off */ + SCU_APBPeriphReset(__MC, DISABLE); +} + +/******************************************************************************* +* Function Name : MC_Init +* Description : Initializes the MC peripheral according to the specified +* parameters in the MC_InitStruct . +* Input : IMC_InitStruct: pointer to a MC_InitTypeDef structure that +* contains the configuration information for the MC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void MC_Init(MC_InitTypeDef* MC_InitStruct) +{ + /* Select the operating Mode */ + if(MC_InitStruct->MC_OperatingMode == MC_SoftwareOperating_Mode) + { + /* Select the Data transfer Mode */ + MC->PCR2 |= MC_DTS_Set; + + /* Enable the registers Software Data Transfer */ + MC->PCR2 |= MC_C0SE_Set | MC_CUSE_Set | MC_CVSE_Set | MC_CWSE_Set + |MC_RSE_Set; + + } + else + { + /* Select the Data transfer Mode */ + MC->PCR2 &= MC_DTS_Reset; + + /* Disable the registers Software Data Transfer */ + MC->PCR2 &= MC_C0SE_Reset | MC_CUSE_Reset | MC_CVSE_Reset | MC_CWSE_Reset + |MC_RSE_Reset; + } + + /* Select the MC PWM counter Mode */ + if(MC_InitStruct->MC_PWMMode == MC_PWMZeroCentered_Mode) + { + MC->PCR0 |= MC_CMS_Set; + } + else + { + MC->PCR0 &= MC_CMS_Reset; + } + + /* Set the MC PWM counter Prescaler */ + MC->CPRS = MC_InitStruct->MC_Prescaler; + + /* Set the MC PWM Period */ + MC->CMP0 = MC_InitStruct->MC_Period; + + /* Set the MC PWM Repetition counter */ + MC->REP = MC_InitStruct->MC_RepetitionCounter; + + /* Set the Tacho Compare value */ + MC->TCMP = MC_InitStruct->MC_TachoPeriod; + + /* Set the Tacho Prescaler value */ + MC->TPRS = MC_InitStruct->MC_TachoPrescaler; + + /* Set the MC Tacho Input Polarity */ + MC->PCR1 = (MC->PCR1 & MC_PCR1_TIN_MASK) | MC_InitStruct->MC_TachoPolarity; + + /* Set the MC PWM Forced State */ + MC->OPR |= MC_ODS_Set; + MC->OPR = (MC->OPR & MC_OPR_Mask) | MC_InitStruct->MC_ForcedPWMState; + + /* Select the Tacho Mode */ + if(MC_InitStruct->MC_TachoMode == MC_TachoOneShot_Mode) + { + MC->PCR1 |= MC_TCB_Set; + } + else + { + MC->PCR1 &= MC_TCB_Reset; + } + + /* Select the Tacho Event Mode */ + if(MC_InitStruct->MC_TachoEvent_Mode == MC_TachoEvent_Software_Mode) + { + MC->PCR1 |= MC_TES_Set; + } + else + { + MC->PCR1 &= MC_TES_Reset; + } + + /* Enable or disable the emergency input */ + if(MC_InitStruct->MC_Emergency == MC_Emergency_Enable) + { + MC->PCR1 &= MC_DISEST_Reset; + } + else + { + MC->PCR1 |= MC_DISEST_Set; + } + +/* Select the complementary Mode */ + if(MC_InitStruct->MC_Complementary == MC_Complementary_Enable) + { + MC->DTG = MC_InitStruct->MC_DeadTime; + MC->PCR0 |= MC_ODCS_Set; + } + else + { + MC->PCR0 &= MC_ODCS_Reset; + } + + /* Tacho Mode selection */ + if(MC_InitStruct->MC_TachoMode == MC_TachoOneShot_Mode) + { + MC->PCR1 |= MC_TCB_Set; + } + else + { + MC->PCR1 &= MC_TCB_Reset; + } + + switch(MC_InitStruct->MC_Channel) + { + /* Channel U configuration */ + case MC_Channel_U: + { + MC->CMPU = MC_InitStruct->MC_PulseU; + + if(MC_InitStruct->MC_PolarityUL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUL_Set; + } + else + { + MC->PSR &= MC_PUL_Reset; + } + if(MC_InitStruct->MC_PolarityUH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUH_Set; + } + else + { + MC->PSR &= MC_PUH_Reset; + } + break; + } + + /* Channel V configuration */ + case MC_Channel_V: + { + MC->CMPV = MC_InitStruct->MC_PulseV; + + if(MC_InitStruct->MC_PolarityVL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVL_Set; + } + else + { + MC->PSR &= MC_PVL_Reset; + } + if(MC_InitStruct->MC_PolarityVH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVH_Set; + } + else + { + MC->PSR &= MC_PVH_Reset; + } + break; + } + + /* Channel W configuration */ + case MC_Channel_W: + { + MC->CMPW = MC_InitStruct->MC_PulseW; + + if(MC_InitStruct->MC_PolarityWL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWL_Set; + } + else + { + MC->PSR &= MC_PWL_Reset; + } + if(MC_InitStruct->MC_PolarityWH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWH_Set; + } + else + { + MC->PSR &= MC_PWH_Reset; + } + break; + } + /* All Channel Configuration */ + case MC_Channel_ALL: + { + MC->CMPU = MC_InitStruct->MC_PulseU; + MC->CMPV = MC_InitStruct->MC_PulseV; + MC->CMPW = MC_InitStruct->MC_PulseW; + + if(MC_InitStruct->MC_PolarityUL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUL_Set; + } + else + { + MC->PSR &= MC_PUL_Reset; + } + if(MC_InitStruct->MC_PolarityUH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUH_Set; + } + else + { + MC->PSR &= MC_PUH_Reset; + } + + if(MC_InitStruct->MC_PolarityVL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVL_Set; + } + else + { + MC->PSR &= MC_PVL_Reset; + } + if(MC_InitStruct->MC_PolarityVH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVH_Set; + } + else + { + MC->PSR &= MC_PVH_Reset; + } + + if(MC_InitStruct->MC_PolarityWL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWL_Set; + } + else + { + MC->PSR &= MC_PWL_Reset; + } + if(MC_InitStruct->MC_PolarityWH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWH_Set; + } + else + { + MC->PSR &= MC_PWH_Reset; + } + } + default: + break; + } +} + +/******************************************************************************* +* Function Name : MC_StructInit +* Description : Fills each MC_InitStruct member with its default value. +* Input : MC_InitStruct : pointer to a MC_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void MC_StructInit(MC_InitTypeDef* MC_InitStruct) +{ + MC_InitStruct->MC_OperatingMode = MC_HardwareOperating_Mode; + MC_InitStruct->MC_TachoMode = MC_TachoContinuous_Mode; + MC_InitStruct->MC_TachoEvent_Mode = MC_TachoEvent_Hardware_Mode; + MC_InitStruct->MC_Prescaler = 0x00; + MC_InitStruct->MC_TachoPrescaler = 0x0000; + MC_InitStruct->MC_PWMMode = MC_PWMClassical_Mode; + MC_InitStruct->MC_Complementary = MC_Complementary_Enable; + MC_InitStruct->MC_Emergency = MC_Emergency_Disable; + MC_InitStruct->MC_ForcedPWMState = 0x003F; + MC_InitStruct->MC_Period = 0x0000; + MC_InitStruct->MC_TachoPeriod = 0x00FF; + MC_InitStruct->MC_Channel = MC_Channel_ALL; + MC_InitStruct->MC_PulseU = 0x0000; + MC_InitStruct->MC_PulseV = 0x0000; + MC_InitStruct->MC_PulseW = 0x0000; + MC_InitStruct->MC_PolarityUL = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityUH = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityVL = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityVH = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityWL = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityWH = MC_Polarity_NonInverted; + MC_InitStruct->MC_TachoPolarity = MC_TachoEventEdge_RisingFalling; + MC_InitStruct->MC_DeadTime = 0x003F; + MC_InitStruct->MC_RepetitionCounter = 0x0000; +} + +/******************************************************************************* +* Function Name : MC_Cmd +* Description : Enables or disables the MC peripheral. +* Input : Newstate: new state of the MC peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the PWM counter */ + MC->PCR0 |= MC_PCE_Set; + + /* Enable the Tacho counter */ + MC->PCR0 |= MC_TCE_Set; + + /* Enable the Dead Time counter */ + MC->PCR0 |= MC_DTE_Set; + } + else + { + /* Disable the PWM counter */ + MC->PCR0 &= MC_PCE_Reset; + + /* Disable the Tacho counter */ + MC->PCR0 &= MC_TCE_Reset; + + /* Disable the Dead counter */ + MC->PCR0 &= MC_DTE_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_ClearPWMCounter +* Description : Clears the MC PWM counter. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearPWMCounter(void) +{ +/* Clear the PWM counter */ + MC->PCR0 |= MC_CPC_Set; +} + +/******************************************************************************* +* Function Name : MC_ClearTachoCounter +* Description : Clears the MC Tacho counter. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearTachoCounter(void) +{ +/* Clear the Tacho counter */ + MC->PCR0 |= MC_CTC_Set; +} + +/******************************************************************************* +* Function Name : MC_CtrlPWMOutputs +* Description : Enables or disables MC peripheral Main Outputs. +* Input : Newstate: new state of the MC peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_CtrlPWMOutputs(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + /* Enable the dead time generator data */ + MC->OPR &= MC_ODS_Reset; + } + else + { + /* Enable the default state data */ + MC->OPR |= MC_ODS_Set; + } +} + +/******************************************************************************* +* Function Name : MC_ITConfig +* Description : Enables or disables the MC interrupts. +* Input : - MC_IT: specifies the MC interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - MC_IT_CMPW: Compare W Interrupt. +* - MC_IT_CMPV: Compare V Interrupt. +* - MC_IT_CMPU: Compare U Interrupt. +* - MC_IT_ZPC: Zero of PWM counter Interrupt. +* - MC_IT_ADT: Automatic Data Transfer Interrupt. +* - MC_IT_OTC: Overflow of Tacho counter Interrupt. +* - MC_IT_CPT: Capture of Tacho counter Interrupt. +* - MC_IT_CM0: Compare 0 Interrupt. +* - Newstate: new state of IMC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ITConfig(u16 MC_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the specific interrupt source */ + MC->IMR |= MC_IT; + + /* Enable the global peripheral interrupt sources */ + MC->PCR2 |= MC_GPI_Set; + } + else + { + /* Disable the specific interrupt source */ + MC->IMR &= ~MC_IT; + + /* Disable the global peripheral interrupt sources */ + MC->PCR2 &= MC_GPI_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_SetPrescaler +* Description : Sets the MC prescaler value. +* Input : MC_Prescaler: MC prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPrescaler(u8 MC_Prescaler) +{ +/* Set the Prescaler Register value */ + MC->CPRS = MC_Prescaler; +} + +/******************************************************************************* +* Function Name : MC_SetPeriod +* Description : Sets the MC period value. +* Input : MC_Period: MC period new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPeriod(u16 MC_Period) +{ +/* Set the Period Register value */ + MC->CMP0 = MC_Period; +} + +/******************************************************************************* +* Function Name : MC_SetPulseU +* Description : Sets the MC pulse U value. +* Input : MC_PulseU: MC pulse U new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPulseU(u16 MC_PulseU) +{ +/* Set the Pulse U Register value */ + MC->CMPU = MC_PulseU; +} + +/******************************************************************************* +* Function Name : MC_SetPulseV +* Description : Sets the MC pulse V value. +* Input : MC_PulseV: MC pulse V new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPulseV(u16 MC_PulseV) +{ +/* Set the Pulse V Register value */ + MC->CMPV = MC_PulseV; +} + +/******************************************************************************* +* Function Name : MC_SetPulseW +* Description : Sets the MC pulse W value. +* Input : MC_PulseW: MC pulse W new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPulseW(u16 MC_PulseW) +{ +/* Set the Pulse W Register value */ + MC->CMPW = MC_PulseW; +} + +/******************************************************************************* +* Function Name : MC_PWMModeConfig +* Description : Selects the MC PWM counter Mode. +* Input : MC_PWMMode: MC PWM counter Mode. +* Output : None +* Return : None +*******************************************************************************/ +void MC_PWMModeConfig(u16 MC_PWMMode) +{ + /* Select the MC PWM counter Mode */ + if(MC_PWMMode == MC_PWMZeroCentered_Mode) + { + MC->PCR0 |= MC_CMS_Set; + } + else + { + MC->PCR0 &= MC_CMS_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_SetDeadTime +* Description : Sets the MC dead time value. +* Input : MC_DeadTime: MC dead time new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetDeadTime(u16 MC_DeadTime) +{ +/* Set the dead time Register value */ + MC->DTG = MC_DeadTime; +} + +/******************************************************************************* +* Function Name : MC_SetTachoCompare +* Description : Sets the MC Tacho Compare Register value. +* Input : MC_Compare: MC Tacho compare new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetTachoCompare(u8 MC_Compare) +{ + /* Sets the Tacho Compare Register value */ + MC->TCMP = MC_Compare; +} +/******************************************************************************* +* Function Name : MC_EmergencyCmd +* Description : Enables or disables the MC emergency feauture. +* Input : Newstate: new state of the MC peripheral Emergency. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_EmergencyCmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Reset the DISEST Bit in the PCR1 Register to enable the emergency stop input */ + MC->PCR1 &= MC_DISEST_Reset; + } + else + { + /* Set the DISEST Bit in the PCR1 Register to disable the emergency stop input */ + MC->PCR1 |= MC_DISEST_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_EmergencyClear +* Description : Clears the MC Emergency Register. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_EmergencyClear(void) +{ +/* Force PWM outputs in safe state (All OFF) */ + MC->OPR |= MC_ODS_Set; + +/* Clear EST bit */ + MC->ESC = MC_ESC_Clear; + +/* Re-enable protection */ + MC->ESC = 0; + +/* Enables the Outputs */ + MC->OPR &= MC_ODS_Reset; +} + +/******************************************************************************* +* Function Name : MC_GetPeriod +* Description : Gets the MC period value. +* Input : None +* Output : None +* Return : MC period value. +*******************************************************************************/ +u16 MC_GetPeriod(void) +{ +/* Return the PWM signal period value */ + return MC->CMP0; +} + +/******************************************************************************* +* Function Name : MC_GetPulseU +* Description : Gets the MC pulse U value. +* Input : None +* Output : None +* Return : MC pulse U value. +*******************************************************************************/ +u16 MC_GetPulseU(void) +{ +/* Return the PWM pulse U Register value */ + return MC->CMPU; +} + +/******************************************************************************* +* Function Name : MC_GetPulseV +* Description : Gets the MC pulse V value. +* Input : None +* Output : None +* Return : MC pulse V value. +*******************************************************************************/ +u16 MC_GetPulseV(void) +{ +/* Return the PWM pulse V Register value */ + return MC->CMPV; +} + +/******************************************************************************* +* Function Name : MC_GetPulseW +* Description : Gets the MC pulse W value. +* Input : None +* Output : None +* Return : MC pulse W value. +*******************************************************************************/ +u16 MC_GetPulseW(void) +{ +/* Return the PWM pulse W Register value */ + return MC->CMPW; +} + +/******************************************************************************* +* Function Name : MC_GetTachoCapture +* Description : Gets the MC Tacho period value. +* Input : None +* Output : None +* Return : MC Tacho capture value. +*******************************************************************************/ +u16 MC_GetTachoCapture(void) +{ +/* Return the Tacho Capture Register value */ + return MC->TCPT; +} + +/******************************************************************************* +* Function Name : MC_ClearOnTachoCapture +* Description : Enables or disables the the Clear on capture of tacho counter. +* Input : Newstate: new state of the CCPT bit. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearOnTachoCapture(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the Clear on capture of tacho counter */ + MC->PCR1 |= MC_CCPT_Set; + } + else + { + /* Disable the Clear on capture of tacho counter */ + MC->PCR1 &= MC_CCPT_Reset; + } +} +/******************************************************************************* +* Function Name : MC_ForceDataTransfer +* Description : Sets the MC Outputs default states. +* Input : MC_ForcedData: MC outputs new states. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ForceDataTransfer(u8 MC_ForcedData) +{ + /* Set the MC PWM Forced State */ + MC->OPR |= MC_ODS_Set; + MC->OPR = (MC->OPR & MC_OPR_Mask) | MC_ForcedData; +} + +/******************************************************************************* +* Function Name : MC_PreloadConfig +* Description : Enables the Software Data Transfer. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_SoftwarePreloadConfig(void) +{ + /* Set the SDT: Software Data Transfer bit */ + MC->PCR2 |= MC_SDT_Set; +} + +/******************************************************************************* +* Function Name : MC_SoftwareTachoCapture +* Description : Enables the Software Tacho Capture. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_SoftwareTachoCapture(void) +{ + /* Set the STC: Software Tacho Capture bit */ + MC->PCR1 |= MC_STC_Set; +} + +/******************************************************************************* +* Function Name : MC_GetCountingStatus +* Description : Checks whether the PWM Counter is counting Up or Down. +* Input : None +* Output : None +* Return : The new state of the PWM Counter(DOWN or UP). +*******************************************************************************/ +CountingStatus MC_GetCountingStatus(void) +{ + if((MC->PCR0 & MC_UDCS_Mask) != DOWN) + { + return UP; + } + else + { + return DOWN; + } +} + +/******************************************************************************* +* Function Name : MC_GetFlagStatus +* Description : Checks whether the specified MC flag is set or not. +* Input : MC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - MC_FLAG_CMPW: Compare W Flag. +* - MC_FLAG_CMPV: Compare V Flag. +* - MC_FLAG_CMPU: Compare U Flag. +* - MC_FLAG_ZPC: Zero of PWM counter Flag. +* - MC_FLAG_ADT: Automatic Data Transfer Flag. +* - MC_FLAG_OTC: Overflow of Tacho counter Flag. +* - MC_FLAG_CPT: Capture of Tacho counter Flag. +* - MC_FLAG_CM0: Compare 0 Flag. +* - MC_FLAG_EST: Emergency Stop Flag. +* Output : None +* Return : The new state of the MC_FLAG(SET or RESET). +*******************************************************************************/ +FlagStatus MC_GetFlagStatus(u16 MC_FLAG) +{ + if((MC->IPR & MC_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MC_ClearFlag +* Description : Clears the MC’s pending flags. +* Input : MC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - MC_FLAG_CMPW: Compare W Flag. +* - MC_FLAG_CMPV: Compare V Flag. +* - MC_FLAG_CMPU: Compare U Flag. +* - MC_FLAG_ZPC: Zero of PWM counter Flag. +* - MC_FLAG_ADT: Automatic Data Transfer Flag. +* - MC_FLAG_OTC: Overflow of Tacho counter Flag. +* - MC_FLAG_CPT: Capture of Tacho counter Flag. +* - MC_FLAG_CM0: Compare 0 Flag. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearFlag(u16 MC_FLAG) +{ +/* Clear the corresponding Flag */ + MC->IPR &= ~MC_FLAG; +} + +/******************************************************************************* +* Function Name : MC_GetITStatus +* Description : Checks whether the MC interrupt has occurred or not. +* Input : MC_IT: specifies the MC interrupt source to check. +* This parameter can be one of the following values: +* - MC_IT_CMPW: Compare W Interrupt. +* - MC_IT_CMPV: Compare V Interrupt. +* - MC_IT_CMPU: Compare U Interrupt. +* - MC_IT_ZPC: Zero of PWM counter Interrupt. +* - MC_IT_ADT: Automatic Data Transfer Interrupt. +* - MC_IT_OTC: Overflow of Tacho counter Interrupt. +* - MC_IT_CPT: Capture of Tacho counter Interrupt. +* - MC_IT_CM0: Compare 0 Interrupt. +* Output : None +* Return : The new state of the MC_IT(SET or RESET). +*******************************************************************************/ +ITStatus MC_GetITStatus(u16 MC_IT) +{ + if((MC->IPR & MC_IT) && (MC->IMR & MC_IT)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MC_ClearITPendingBit +* Description : Clears the IMC's interrupt pending bits. +* Input : MC_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - MC_IT_CMPW: Compare W Interrupt. +* - MC_IT_CMPV: Compare V Interrupt. +* - MC_IT_CMPU: Compare U Interrupt. +* - MC_IT_ZPC: Zero of PWM counter Interrupt. +* - MC_IT_ADT: Automatic Data Transfer Interrupt. +* - MC_IT_OTC: Overflow of Tacho counter Interrupt. +* - MC_IT_CPT: Capture of Tacho counter Interrupt. +* - MC_IT_CM0: Compare 0 Interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearITPendingBit(u16 MC_IT) +{ +/* Clear the corresponding interrupt pending bit */ + MC->IPR &= ~MC_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_rtc.c b/uc_str912/prj_blinky_complex_startup/src/91x_rtc.c new file mode 100644 index 0000000..27e5579 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_rtc.c @@ -0,0 +1,400 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_rtc.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the RTC library software functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_rtc.h" +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +u8 BYTEToBCD2(u8 value); +u16 WORDToBCD3(u16 value); +u8 BCD2ToBYTE(u8 value); +u16 BCD3ToBYTE(u16 value); +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : BYTEToBCD2 +* Description : Converts a 2 digit decimal to BCD format +* Input : None +* Output : None +* Return : Converted byte +*******************************************************************************/ +u8 BYTEToBCD2(u8 value) +{ + u8 bcdhigh = 0; + while (value >= 10) + { + bcdhigh++; + value -= 10; + } + return (bcdhigh << 4) | value; +} +/******************************************************************************* +* Function Name : WORDToBCD3 +* Description : Converts a 3 digit decimal to BCD format +* Input : None +* Output : None +* Return : Converted word +*******************************************************************************/ +u16 WORDToBCD3(u16 value) +{ + u16 bcdhigh = 0; + while (value >= 100) + { + bcdhigh++; + value -= 100; + } + bcdhigh <<= 4; + while (value >= 10) + { + bcdhigh++; + value -= 10; + } + return (bcdhigh << 4) | value; +} + +/******************************************************************************* +* Function Name : BCD3ToWORD +* Description : convert from 3 digit BCD to Binary +* Input : None +* Output : None +* Return : Converted word +*******************************************************************************/ +u16 BCD3ToWORD(u16 value) +{ + return (u16)((((value&0xF00)>>8)*100) + (((value&0x0F0)>>4)*10) + (value&0x0F)); +} + +/******************************************************************************* +* Function Name : BCD2ToBYTE +* Description : convert from 2 digit BCD to Binary +* Input : None +* Output : None +* Return : Converted word +*******************************************************************************/ +u8 BCD2ToBYTE(u8 value) +{ + u32 tmp; + tmp= ((value&0xF0)>>4)*10; + return (u8)(tmp+ (value&0x0F)); +} + +/******************************************************************************* +* Function Name : RTC_DeInit +* Description : Resets the RTC peripheral registers +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_DeInit(void) +{ + SCU_APBPeriphReset(__RTC,ENABLE); + SCU_APBPeriphReset(__RTC,DISABLE); +} + +/******************************************************************************* +* Function Name : RTC_SetDate +* Description : Sets the Date register +* Input : struct of type RTC_DATE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetDate(RTC_DATE Date) +{ + u32 tmp = 0; + + RTC->CR |=0x80; /*Enable write operation in DTR register*/ + RTC->DTR = 0; + tmp = BYTEToBCD2(Date.century); + RTC->DTR|=tmp<<24; + tmp = BYTEToBCD2(Date.year); + RTC->DTR|=tmp<<16; + tmp = BYTEToBCD2(Date.month); + RTC->DTR|=tmp<<8; + tmp = BYTEToBCD2(Date.weekday); + RTC->DTR|=tmp; + RTC->TR &=0xFFFFFF; + tmp = BYTEToBCD2(Date.day); + RTC->TR|=tmp<<24; + RTC->CR &=~0x80; /*Disable write operation in DTR register*/ +} +/******************************************************************************* +* Function Name : RTC_SetTime +* Description : Sets the Time register +* Input : struct of type RTC_TIME +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetTime(RTC_TIME Time) +{ + u32 tmp = 0; + + RTC->CR |=0x80; /*Enable write operation in TR register*/ + RTC->TR &= 0xFF000000; + tmp = BYTEToBCD2(Time.hours); + RTC->TR|=tmp<<16; + tmp = BYTEToBCD2(Time.minutes); + RTC->TR|=tmp<<8; + tmp = BYTEToBCD2(Time.seconds); + RTC->TR|=tmp; + RTC->MILR = 0; + RTC->MILR |= WORDToBCD3(Time.milliseconds); + RTC->CR &=~0x80; /*Disable write operation in TR register*/ +} +/******************************************************************************* +* Function Name : RTC_SetAlarm +* Description : Sets the Alarm register +* Input : Struct of type RTC_ALARM +* Output : Date +* Return : None +*******************************************************************************/ +void RTC_SetAlarm(RTC_ALARM Alarm) +{ + u32 tmp = 0; + + RTC->CR |=0x80; /*Enable write operation in ATR register*/ + RTC->ATR = 0; + tmp = BYTEToBCD2(Alarm.day); + RTC->ATR|=tmp<<24; + tmp = BYTEToBCD2(Alarm.hours); + RTC->ATR|=tmp<<16; + tmp = BYTEToBCD2(Alarm.minutes); + RTC->ATR|=tmp<<8; + tmp = BYTEToBCD2(Alarm.seconds); + RTC->ATR|=tmp; + RTC->CR &=~0x80; /*Disable write operation in ATR register*/ +} + +/******************************************************************************* +* Function Name : RTC_GetDate +* Description : Gets RTC date in BCD coded or BINARY code +* Input : -Format: BCD or BINARY +* -Date: pointer to structure of type RTC_DATE to be filled by function +* Output : None +* Return : None +*******************************************************************************/ +void RTC_GetDate(u8 Format, RTC_DATE * Date) +{ + Date->century = (u8)((RTC->DTR&0xFF000000)>>24); + Date->year = (u8)((RTC->DTR&0x00FF0000)>>16); + Date->month = (u8)((RTC->DTR&0x00001F00)>>8); + Date->day = (u8)((RTC->TR&0x3F000000)>>24); + Date->weekday = (u8)(RTC->DTR&0xF); + if (Format == BINARY) + { + Date->century = BCD2ToBYTE(Date->century); + Date->year = BCD2ToBYTE(Date->year); + Date->month = BCD2ToBYTE(Date->month); + Date->day = BCD2ToBYTE(Date->day); + Date->weekday = BCD2ToBYTE(Date->weekday); + } +} + +/******************************************************************************* +* Function Name : RTC_GetTime +* Description : Gets TIME in BCD coded or BINARY code +* Input : -Format: BCD or BINARY +* -Time : pointer to structure of type RTC_TIME to be filled by function +* Output : Time +* Return : None +*******************************************************************************/ +void RTC_GetTime(u8 Format, RTC_TIME * Time) +{ + + Time->hours = (u8)((RTC->TR&0x003F0000)>>16); + Time->minutes = (u8)((RTC->TR&0x00007F00)>>8); + Time->seconds = (u8)(RTC->TR&0x7F); + Time->milliseconds =(u16)(RTC->MILR&0xFFF); + if (Format == BINARY) + { + Time->hours = BCD2ToBYTE(Time->hours); + Time->minutes = BCD2ToBYTE(Time->minutes); + Time->seconds = BCD2ToBYTE(Time->seconds); + Time->seconds = BCD3ToWORD(Time->milliseconds); + } +} + + +/******************************************************************************* +* Function Name : RTC_GetAlarm +* Description : Gets the RTC Alarm in BCD or BINARY code +* Input : -Format: BCD or BINARY +* -Alarm : pointer to structure of type RTC_ALARM to be filled by function +* Output : Alarm +* Return : None +*******************************************************************************/ +void RTC_GetAlarm(u8 Format,RTC_ALARM * Alarm) +{ + Alarm->day = (u8)((RTC->ATR&0x3F000000)>>24); + Alarm->hours = (u8)((RTC->ATR&0x003F0000)>>16); + Alarm->minutes = (u8)((RTC->ATR&0x00007F00)>>8); + Alarm->seconds = (u8)((RTC->ATR)&0x7F); + if (Format == BINARY) + { + Alarm->day = BCD2ToBYTE(Alarm->day); + Alarm->hours = BCD2ToBYTE(Alarm->hours); + Alarm->minutes = BCD2ToBYTE(Alarm->minutes); + Alarm->seconds = BCD2ToBYTE(Alarm->seconds); + } +} + +/******************************************************************************* +* Function Name : RTC_TamperConfig +* Description : configures the Tamper mode and tamper polarity +* Input : -TamperMode: RTC_TamperMode_Edge or RTC_TamperMode_Level +* -TamperPol : RTC_TamperPol_Low or RTC_TamperMode_High +* Output : None +* Return : None +*******************************************************************************/ +void RTC_TamperConfig(u32 TamperMode, u32 TamperPol) +{ + RTC->CR&=RTC_TamperMode_Edge; + if (TamperMode!=RTC_TamperMode_Edge) + RTC->CR|=RTC_TamperMode_Level; + + RTC->CR&=RTC_TamperPol_Low; + if (TamperPol!=RTC_TamperPol_Low) + RTC->CR|=RTC_TamperPol_High; +} + +/******************************************************************************* +* Function Name : RTC_TamperCmd +* Description : Enable or Disable Tamper +* Input : NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_TamperCmd(FunctionalState NewState) +{ + RTC->CR&=0xFFFFFFFE; + if (NewState==ENABLE) + RTC->CR|=0x1; +} + +/******************************************************************************* +* Function Name : RTC_AlarmCmd +* Description : Enable or Disable Alarm +* Input : NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_AlarmCmd(FunctionalState NewState) +{ + RTC->CR&=~0x100000; + if (NewState==ENABLE) + RTC->CR|=0x100000; +} + +/******************************************************************************* +* Function Name : RTC_CalibClockCmd +* Description : Enable or Disable RTC Calibration Clock Output +* Input : NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_CalibClockCmd(FunctionalState NewState) +{ + RTC->CR&=~0x40; + if (NewState ==ENABLE) + RTC->CR|=0x40; +} + +/******************************************************************************* +* Function Name : SRAMBattPowerCmd +* Description : Enable or Disable SRAM backup Power by VBATT +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SRAMBattPowerCmd(FunctionalState NewState) +{ + RTC->CR&=~0x8; + if (NewState ==ENABLE) + RTC->CR|=0x8; +} + +/******************************************************************************* +* Function Name : RTC_PeridicIntConfig +* Description : Select a Periodic CLock +* Input : PeriodicClock +* Output : None +* Return : None +* Note : When PeriodicClock = RTC_Per_DISABLE the Periodic clock generation +* will be disabled. +*******************************************************************************/ +void RTC_PeriodicIntConfig(u32 PeriodicClock) +{ + RTC->CR &=~0xF0000; + RTC->CR|=PeriodicClock; +} + +/******************************************************************************* +* Function Name : RTC_ITConfig +* Description : Enable or Disable an interrupt +* Input : -RTC_IT : RTC interrupt +* -Newstate: Enable or Disable +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ITConfig(u32 RTC_IT, FunctionalState NewState) +{ + RTC->CR&=~RTC_IT; + if (NewState==ENABLE) + RTC->CR|=RTC_IT; +} + +/******************************************************************************* +* Function Name : RTC_GetFlagStatus +* Description : Gets a RTC flag status +* Input : RTC_FLAG +* Output : None +* Return : FlagStatus :SET or RESET +*******************************************************************************/ +FlagStatus RTC_GetFlagStatus(u32 RTC_FLAG) +{ + if (RTC->SR&RTC_FLAG) return SET; + else return RESET; +} + +/******************************************************************************* +* Function Name : RTC_ClearFlag +* Description : Clears a RTC flag +* Input : RTC_FLAG +* Output : None +* Return : None +* Note : Before clearing the RTC Periodic Flag you need to disable the +* Periodic interrupt generation, to do this use function +* RTC_PeriodicIntConfig(RTC_Per_DISABLE) +*******************************************************************************/ +void RTC_ClearFlag(u32 RTC_FLAG) +{ + vu32 tmp=0; + if (RTC_FLAG == RTC_FLAG_Per) tmp=RTC->SR; + else if (RTC_FLAG == RTC_FLAG_Alarm) RTC->CR&=~0x100000; + else if (RTC_FLAG == RTC_FLAG_Tamper) RTC->CR&=~0x1; +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_scu.c b/uc_str912/prj_blinky_complex_startup/src/91x_scu.c new file mode 100644 index 0000000..21116b2 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_scu.c @@ -0,0 +1,661 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SCU_PLLEN 0x80000 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SCU_MCLKSourceConfig +* Description : Configures the MCLK source clock +* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : this function returns ERROR if trying to select the PLL as +* clock source while the PLL is disabled or not locked. +*******************************************************************************/ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source) +{ + u32 CLKCNTR_Value; + + CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/ + CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/ + if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/ + { + /*check if PLL enabled & locked*/ + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + return ERROR; + } + else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/ + SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/ + return SUCCESS; +} + +/******************************************************************************* +* Function Name : SCU_PLLFactorsConfig +* Description : Sets the PLL factors +* Input : PLLN, PLLM and PLLP +* Output : None +* Return : ErrorStatus: ERROR or SUCCESS +* Notes : -The PLL factors must respect the PLL specification requirements +* -The function returns ERROR if trying to change PLL +* factors while PLL is selected as Main Clock source (MCLK) +* -This function disables the PLL, to enable the PLL use +* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors +******************************************************************************/ +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP) +{ + if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/ + { + SCU->PLLCONF =0; /*clear PLLCONF register*/ + SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/ + SCU->PLLCONF |=PLLM; /*update PLLM field*/ + SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/ + return SUCCESS; + } + return ERROR; +} + +/******************************************************************************* +* Function Name : SCU_PLLCmd +* Description : Enable or Disable the PLL +* Input : NewState = ENABLE or DISABLE +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : -The function returns ERROR if: +* *trying to disable the PLL while it is selected as the MCLK +* *trying to enable the PLL while it is already enabled and +* locked +*******************************************************************************/ +ErrorStatus SCU_PLLCmd(FunctionalState NewState) +{ + vu32 i; + if (NewState==ENABLE) + { + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + { + SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/ + SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/ + while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/ + return SUCCESS; + } + else return ERROR; + } + else /*NewState = DISABLE*/ + { + if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/ + { + for(i=10;i>0;i--); /*delay before PLL disabling*/ + SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/ + return SUCCESS; + } + else return ERROR; + } +} + +/******************************************************************************* +* Function Name : SCU_RCLKDivisorConfig +* Description : Sets the RCLK divisor value +* Input : RCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/ + if (RCLK_Divisor!=SCU_RCLK_Div1) + SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_HCLKDivisorConfig +* Description : Sets the HCLK divisor value +* Input : HCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/ + if (HCLK_Divisor!=SCU_HCLK_Div1) + SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_PCLKDivisorConfig +* Description : Sets the PCLK divisor value +* Input : PCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/ + if (PCLK_Divisor!=SCU_PCLK_Div1) + SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphClockConfig +* Description : Enable the clock for an APB peripheral +* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for APB peripheral*/ + SCU->PCGR1 |=APBPeriph; + else + SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphClockConfig +* Description : Enable the clock for an AHB peripheral +* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for AHB peripheral*/ + SCU->PCGRO |=AHBPeriph; + else + SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphReset +* Description : Assert or deassert Reset on APB peripheral +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) /*APB peripheral not held in Reset*/ + SCU->PRR1 |=APBPeriph; + else + SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphReset +* Description : Assert or deassert Reset on AHB peripheral +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) + SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/ + else + SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/ + else + SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/ + else + SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/ +} +/******************************************************************************* +* Function Name : SCU_BRCLKDivisorConfig +* Description : Sets the BRCLK divisor value +* Input : BRCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/ + if (BRCLK_Divisor!=SCU_BRCLK_Div1) + SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/ +} + +/******************************************************************************* +* Function Name : SCU_TIMCLKSourceConfig +* Description : Sets the TIMx clock source +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source) +{ + if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/ + { + SCU->CLKCNTR &=0xFFFFDFFF; + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x2000; + } + else + { + SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/ + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x4000; + } +} + +/******************************************************************************* +* Function Name : SCU_TIMPresConfig +* Description : Sets the TIMx Prescaler Value +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - Prescaler (16 bit value) +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler) +{ + if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/ + SCU->SCR1 = Prescaler&0xFFFF; + else + SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/ +} + +/******************************************************************************* +* Function Name : SCU_USBCLKConfig +* Description : Configures the clock source for the 48MHz USBCLK +* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_USBCLKConfig(u32 USBCLK_Source) +{ + SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/ + if (USBCLK_Source!=SCU_USBCLK_MCLK) + SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/ +} + +/******************************************************************************* +* Function Name : SCU_PHYCLKConfig +* Description : Enable or Disable PHY clock output +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PHYCLKConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/ + else + SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/ +} + +/******************************************************************************* +* Function Name : SCU_FMICLKDivisorConfig +* Description : Set the FMI clock divisor +* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor) +{ + SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/ + if (FMICLK_Divisor!=SCU_FMICLK_Div1) + SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIBCLKDivisorConfig +* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2 +* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK) +{ + SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */ + if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1) + SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIModeConfig +* Description : Configure the EMI as Multiplexed or Demultiplexed +* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIModeConfig(u32 SCU_EMIMODE) +{ + SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/ + if (SCU_EMIMODE!=SCU_EMI_MUX) + SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/ +} + +/******************************************************************************* +* Function Name : SCU_EMIALEConfig +* Description : Configure the ALE signal (length & polarity) +* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2 +* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL) +{ + /*Configure EMI ALE Length*/ + SCU->SCR0 &=SCU_EMIALE_LEN1; + if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1) + SCU->SCR0 |= SCU_EMIALE_LEN2; + + /*Configure EMI ALE POL*/ + SCU->SCR0 &=SCU_EMIALE_POLLow; + if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow) + SCU->SCR0 |= SCU_EMIALE_POLHigh; +} + +/******************************************************************************* +* Function Name : SCU_ITConfig +* Description : ENBALE or DISABLE an SCU interrupt +* Input : -SCU_IT: interrupt mask +* -NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->ITCMSK&=~SCU_IT; /*IT enable */ + else + SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/ +} + +/******************************************************************************* +* Function Name : SCU_GetFlagStatus +* Description : Returns flag status +* Input : SCU_Flag +* Output : NONE +* Return : SET or RESET +*******************************************************************************/ +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag) +{ + if (SCU->SYSSTATUS&SCU_Flag) + return SET; + else return RESET; +} + +/******************************************************************************* +* Function Name : SCU_ClearFlag +* Description : Clears a SYSTATUS Flag +* Input : SCU_Flag +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ClearFlag(u32 SCU_Flag) +{ + SCU->SYSSTATUS = SCU_Flag; +} +/******************************************************************************* +* Function Name : SCU_GetPLLfreqValue +* Description : Gets the current PLL frequency +* Input : None +* Output : None +* Return : PLL frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPLLFreqValue(void) +{ + u8 PLL_M; + u8 PLL_N; + u8 PLL_P; + + PLL_M = SCU->PLLCONF&0xFF; + PLL_N = (SCU->PLLCONF&0xFF00)>>8; + PLL_P = (SCU->PLLCONF&0x70000)>>16; + + if ((PLL_M>0)&&(PLL_N>0)) + return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal); + if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32); + else return (SCU_GetPLLFreqValue()); +} + +/******************************************************************************* +* Function Name : SCU_GetRCLKFreqValue +* Description : Gets the current RCLK frequency +* Input : None +* Output : None +* Return : RCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetRCLKFreqValue(void) +{ + u8 RCLK_Div; + RCLK_Div = (SCU->CLKCNTR&0x1C)>>2; + if (RCLK_Div==0x5) RCLK_Div=10; + return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetHCLKFreqValue +* Description : Gets the current PCLK frequency +* Input : None +* Output : None +* Return : HCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetHCLKFreqValue(void) +{ + u8 HCLK_Div; + HCLK_Div = (SCU->CLKCNTR&0x60)>>5; + return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetPCLKFreqValue +* Description : Gets the current HCLK frequency +* Input : None +* Output : None +* Return : PCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPCLKFreqValue(void) +{ + u8 PCLK_Div; + PCLK_Div = (SCU->CLKCNTR&0x180)>>7; + return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_WakeUpLineConfig +* Description : Configures an External interrupt as WakeUp line +* Input : EXTint : 0 -> 31 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_WakeUpLineConfig(u8 EXTint) +{ + if (EXTint < 8) + { + SCU->WKUPSEL&=~0x7; + SCU->WKUPSEL|=EXTint; + } + else if (EXTint<16) + { + SCU->WKUPSEL&=~0x38; + SCU->WKUPSEL|=(EXTint-8)<<3; + } + else if (EXTint<24) + { + SCU->WKUPSEL&=~0x1C0; + SCU->WKUPSEL|=(EXTint-16)<<6; + } + else + { + SCU->WKUPSEL&=~0xE00; + SCU->WKUPSEL|=(EXTint-24)<<9; + } +} + +/******************************************************************************* +* Function Name : SCU_SpecIntRunModeConfig +* Description : Enables or Disables the Special Run mode +* Input : newstate = ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_SpecIntRunModeConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + SCU->PWRMNG |=0x8; + else + SCU->PWRMNG &=~0x8; +} +/******************************************************************************* +* Function Name : SCU_EnterIdleMode +* Description : Enters in Idle mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterIdleMode(void) +{ + SCU->PWRMNG |=0x1; +} +/******************************************************************************* +* Function Name : SCU_EnterSleepMode +* Description : Enters in Sleep mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterSleepMode(void) +{ + SCU->PWRMNG |=0x2; +} + +/******************************************************************************* +* Function Name : SCU_UARTIrDAConfig +* Description : Enable or Disable the Irda mode for UARTx +* Input : - UARTx :x=0,1 or 2 +* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART +* Output : None +* Return : None +*******************************************************************************/ +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode) +{ + if (UART_IrDA_Mode == SCU_UARTMode_IrDA) + { + if (UARTx== UART0) SCU->SCR0 |=0x400; + else if (UARTx==UART1) SCU->SCR0 |=0x800; + else SCU->SCR0 |=0x1000; + } + else + { + if (UARTx== UART0) SCU->SCR0 &=~0x400; + else if (UARTx==UART1) SCU->SCR0 &=~0x800; + else SCU->SCR0 &=~0x1000; + } +} +/******************************************************************************* +* Function Name : SCU_PFQBCCmd +* Description : Enable or Disable PFQBC +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PFQBCCmd(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->SCR0 |=0x1; + else SCU->SCR0 &=~0x1; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_ssp.c b/uc_str912/prj_blinky_complex_startup/src/91x_ssp.c new file mode 100644 index 0000000..06bf30c --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_ssp.c @@ -0,0 +1,469 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ssp.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the SSP software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_ssp.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* SSP peripheral Enable */ +#define SSP_Enable 0x0002 +#define SSP_Disable 0xFFFD + +/* SSP Loop Back Mode Enable */ +#define SSP_LoopBackMode_Enable 0x0001 +#define SSP_LoopBackMode_Disable 0xFFFE + +/* SSP Flag Mask */ +#define SSP_Flag_Mask 0x001F + +/* SSP DMA transmit/ receive enable/disable Masks */ +#define SSP_DMA_TransmitEnable 0x0002 +#define SSP_DMA_TransmitDisable 0xFFFD +#define SSP_DMA_ReceiveEnable 0x0001 +#define SSP_DMA_ReceiveDisable 0xFFFE + +/* SSP Masks */ +#define SSP_FrameFormat_Mask 0xFFCF +#define SSP_DataSize_Mask 0xFFF0 +#define SSP_ClockRate_Mask 0x00FF +#define SSP_ClockPrescaler_Mask 0xFF00 + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SSP_DeInit +* Description : Deinitializes the SSPx peripheral registers to their default +* reset values. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DeInit(SSP_TypeDef* SSPx) +{ + if(SSPx == SSP0) + { + /* Reset the SSP0 registers values*/ + SCU_APBPeriphReset(__SSP0,ENABLE); + SCU_APBPeriphReset(__SSP0,DISABLE); + } + else if (SSPx == SSP1) + { + /* Reset the SSP1 registers values*/ + SCU_APBPeriphReset(__SSP1,ENABLE); + SCU_APBPeriphReset(__SSP1,DISABLE); + } +} + +/******************************************************************************* +* Function Name : SSP_Init +* Description : Initializes the SSPx peripheral according to the specified +* parameters in the SSP_InitTypeDef structure. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_InitStruct: pointer to a SSP_InitTypeDef structure that +* contains the configuration information for the specified SSP +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct) +{ + if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_Motorola) + { + /* Set the Motorola frame format */ + SSPx->CR0 &= SSP_FrameFormat_Motorola; + /* Configure the Clock polarity */ + if(SSP_InitStruct->SSP_CPOL == SSP_CPOL_High) + { + /* SCK is held high when no data is being transfered */ + SSPx->CR0 |= SSP_CPOL_High; + } + else + { + /* SCK is held low when no data is being transfered */ + SSPx->CR0 &= SSP_CPOL_Low; + } + /* Configure the Clock Phase */ + if(SSP_InitStruct->SSP_CPHA == SSP_CPHA_2Edge) + { + /* Data captured on second clock edge */ + SSPx->CR0 |= SSP_CPHA_2Edge; + } + else + { + /* Data captured on first clock edge */ + SSPx->CR0 &= SSP_CPHA_1Edge; + } + } + /* Configure the Frame format */ + else + { + /* Clear the FRF[1:0] bits */ + SSPx->CR0 &= SSP_FrameFormat_Mask; + /* Set the TI frame format */ + SSPx->CR0 |= SSP_InitStruct->SSP_FrameFormat; + } + /* Configure the Mode */ + if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave) + { + /* Set the slave mode */ + SSPx->CR1 |= SSP_Mode_Slave; + /* Configure the Slave output */ + if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable) + { + /* Slave output disabled */ + SSPx->CR1 |= SSP_SlaveOutput_Disable; + } + else + { + /* Slave output enabled */ + SSPx->CR1 &= SSP_SlaveOutput_Enable; + } + } + else + { + /* Set the master mode */ + SSPx->CR1 &= SSP_Mode_Master; + /* Clear clock rate SCR[7:0] bits */ + SSPx->CR0 &= SSP_ClockRate_Mask; + /* Set the serial clock rate */ + SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); + /* Clear clock prescaler CPSDVSR[7:0] bits */ + SSPx->PR &= SSP_ClockPrescaler_Mask; + /* Set the serial clock prescaler */ + SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; + } + + /* Clear data size DSS[3:0] bits */ + SSPx->CR0 &= SSP_DataSize_Mask; + /* Set the data size */ + SSPx->CR0 |= SSP_InitStruct->SSP_DataSize; +} +/******************************************************************************* +* Function Name : SSP_StructInit +* Description : Fills in a SSP_InitTypeDef structure with the reset value of +* each parameter. +* Input : SSP_InitStruct : pointer to a SSP_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct) +{ + /* Initialize the SSP_FrameFormat member */ + SSP_InitStruct->SSP_FrameFormat = SSP_FrameFormat_Motorola; + + /* Initialize the SSP_Mode member */ + SSP_InitStruct->SSP_Mode = SSP_Mode_Master; + + /* Initialize the SSP_CPOL member */ + SSP_InitStruct->SSP_CPOL = SSP_CPOL_Low; + + /* Initialize the SSP_CPHA member */ + SSP_InitStruct->SSP_CPHA = SSP_CPHA_1Edge; + + /* Initialize the SSP_DataSize member */ + SSP_InitStruct->SSP_DataSize = SSP_DataSize_8b; + + /* Initialize the SSP_SlaveOutput member */ + SSP_InitStruct->SSP_SlaveOutput = SSP_SlaveOutput_Enable; + + /* Initialize the SSP_ClockRate member */ + SSP_InitStruct->SSP_ClockRate = 0; + + /* Initialize the SSP_ClockPrescaler member */ + SSP_InitStruct->SSP_ClockPrescaler = 0; +} + +/******************************************************************************* +* Function Name : SSP_Cmd +* Description : Enables or disables the specified SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the SSPx peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the SSP peripheral */ + SSPx->CR1 |= SSP_Enable; + } + else + { + /* Disable the SSP peripheral */ + SSPx->CR1 &= SSP_Disable; + } +} + +/******************************************************************************* +* Function Name : SSP_ITConfig +* Description : Enables or disables the specified SSP interrupts. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the SSP interrupts sources to be enabled +* or disabled. This parameter can be any combination of the +* following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* - NewState: new state of the specified SSP interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected SSP interrupts */ + SSPx->IMSCR |= SSP_IT; + } + else + { + /* Disable the selected SSP interrupts */ + SSPx->IMSCR &= ~SSP_IT; + } +} + +/******************************************************************************* +* Function Name : SSP_DMACmd +* Description : Configures the SSP0 DMA interface. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_DMATransfert : specifies the DMA transfert to be +* enabled or disabled. This parameter can be one of the +* following values: +* - SSP_DMA_Transmit: transmit Fifo DMA transfert +* - SSP_DMA_Receive : receive Fifo DMA transfert +* - NewState: new state of the DMA transfert. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMACmd(SSP_TypeDef* SSPx, u16 SSP_DMATransfert, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + if(SSP_DMATransfert == SSP_DMA_Transmit) + { + /* Enable DMA for the transmit FIFO */ + SSPx->DMACR |= SSP_DMA_TransmitEnable; + } + else + { + /* Enable DMA for the receive FIFO */ + SSPx->DMACR |= SSP_DMA_ReceiveEnable; + } + } + else + { + if(SSP_DMATransfert == SSP_DMA_Transmit) + { + /* Disable DMA for the transmit FIFO */ + SSPx->DMACR &= SSP_DMA_TransmitDisable; + } + else + { + /* Disable DMA for the receive FIFO */ + SSPx->DMACR &= SSP_DMA_ReceiveDisable; + } + } +} + +/******************************************************************************* +* Function Name : SSP_SendData. +* Description : Transmits a Data through the SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - Data : Data to be transmitted. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data) +{ + /* Write in the DR register the data to be sent */ + SSPx->DR = Data; +} + +/******************************************************************************* +* Function Name : SSP_ReceiveData. +* Description : Returns the most recent received data by the SSP peripheral. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u16 SSP_ReceiveData(SSP_TypeDef* SSPx) +{ + /* Return the data in the DR register */ + return SSPx->DR; +} + +/******************************************************************************* +* Function Name : SSP_LoopBackMode +* Description : Enable or disable the Loop back mode for the selected SSPx peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the Loop Back mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void SSP_LoopBackMode(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable loop back mode */ + SSPx->CR1 |= SSP_LoopBackMode_Enable; + } + else + { + /* Disable loop back mode */ + SSPx->CR1 &= SSP_LoopBackMode_Disable; + } +} + + + +/******************************************************************************* +* Function Name : SSP_GetFlagStatus +* Description : Checks whether the specified SSP flag is set or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: flag to check. This parameter can be one of the +* following values: +* - SSP_FLAG_Busy: busy flag +* - SSP_FLAG_RxFifoFull: Receive FIFO full flag +* - SSP_FLAG_RxFifoNotEmpty: Receive FIFO not empty flag +* - SSP_FLAG_TxFifoNotFull: Transmit FIFO not full flag +* - SSP_FLAG_TxFifoEmpty: Transmit FIFO empty flag +* - SSP_FLAG_TxFifo: Transmit FIFO half empty or less flag +* - SSP_FLAG_RxFifo: Receive FIFO half full or less flag +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : The new state of SSP_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u32 SSPReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the SSP register index */ + SSPReg = SSP_FLAG >> 5; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Find the register of the flag to check */ + if(SSPReg == 1) + { + /* The flag to check is in SR register */ + StatusReg = SSPx->SR; + } + else if (SSPReg == 2) + { + /* The flag to check is in RISR register */ + StatusReg = SSPx->RISR; + } + + /* Check the status of the specified SSP flag */ + if((StatusReg & (1 << FlagPos)) != RESET) + { + /* Return SET if the SSP flag is set */ + return SET; + } + else + { + /* Return RESET if the SSP flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearFlag +* Description : Clears the SSPx flags. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: flags to clear. This parameter one of the +* following values: +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u8 FlagPos = 0; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Clear the selected SSP flag */ + SSPx->ICR = (1 << FlagPos); +} + +/******************************************************************************* +* Function Name : SSP_GetITStatus +* Description : Checks whether the specified SSP interrupt flag is set or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: interrupt flag to check. This parameter can be one +* of the following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : The new state of SSP_IT flag (SET or RESET). +*******************************************************************************/ +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Check the status of the specified interrupt flag */ + if((SSPx->MISR & SSP_IT) != RESET) + { + /* Return SET if the SSP interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if SSP interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearITPendingBit +* Description : Clears the pending interrupt flags. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: interrupts pending bits to clear. This parameter +* can be any combination of the following values: +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Clear the selected SSP interrupts pending bits */ + SSPx->ICR = SSP_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_tim.c b/uc_str912/prj_blinky_complex_startup/src/91x_tim.c new file mode 100644 index 0000000..7957168 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_tim.c @@ -0,0 +1,694 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_tim.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the TIM software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_tim.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* TIM Bits Masks */ + +#define TIM_PWM_MASK 0x0010 +#define TIM_OPM_MASK 0x0020 +#define TIM_OC1_ENABLE_MASK 0x0040 +#define TIM_OC1_DISABLE_MASK 0xFFBF +#define TIM_OC2_ENABLE_MASK 0x0080 +#define TIM_OC2_DISABLE_MASK 0xFF7F + +#define TIM_OLVL1_SET_MASK 0x0100 +#define TIM_OLVL1_RESET_MASK 0xFEFF + +#define TIM_OLVL2_SET_MASK 0x0200 +#define TIM_OLVL2_RESET_MASK 0xFDFF + +#define TIM_ENABLE_MASK 0x8000 +#define TIM_DISABLE_MASK 0x7FFF + +#define TIM_DMA_CLEAR_MASK 0xCFFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : TIM_DeInit +* Description : Initializes TIM peripheral control and registers to their +* : default reset values. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM0)||(TIMx == TIM1)) + { + SCU_APBPeriphReset(__TIM01, DISABLE); /* TIM0 & TIM1 Reset's off */ + } + else + { + SCU_APBPeriphReset(__TIM23, DISABLE); /* TIM2 & TIM3 Reset's off */ + } + + /* Set all the TIMx registers to thier default values */ + TIMx->OC1R = 0x8000; + TIMx->OC2R = 0x8000; + TIMx->CR1 = 0x0; + TIMx->CR2 = 0x1; + TIMx->CNTR = 0x1234; + TIMx->SR = 0x0; +} + +/******************************************************************************* +* Function Name : TIM_StructInit +* Description : Fills in a TIM_InitTypeDef structure with the reset value of +* each parameter. +* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct) +{ + TIM_InitStruct->TIM_Mode = 0x0000; + TIM_InitStruct->TIM_OC1_Modes = 0x0000; + TIM_InitStruct->TIM_OC2_Modes = 0x0000; + TIM_InitStruct->TIM_Clock_Source = 0x0000; + TIM_InitStruct->TIM_Clock_Edge = 0x0000; + TIM_InitStruct->TIM_OPM_INPUT_Edge = 0x0000; + TIM_InitStruct->TIM_ICAP1_Edge = 0x0000; + TIM_InitStruct->TIM_ICAP2_Edge = 0x0000; + TIM_InitStruct->TIM_Prescaler = 0x0000; + TIM_InitStruct->TIM_Pulse_Level_1 = 0x0000; + TIM_InitStruct->TIM_Pulse_Level_2 = 0x0000; + TIM_InitStruct->TIM_Period_Level = 0x0000; + TIM_InitStruct->TIM_Pulse_Length_1 = 0x0000; + TIM_InitStruct->TIM_Pulse_Length_2 = 0x0000; + TIM_InitStruct->TIM_Full_Period = 0x0000; +} + +/******************************************************************************* +* Function Name : TIM_Init +* Description : Initializes TIM peripheral according to the specified +* parameters in the TIM_InitTypeDef structure. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ + +void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct) +{ +/***************************** Clock configuration ****************************/ + + if (TIM_InitStruct->TIM_Clock_Source == TIM_CLK_APB) + { + /* APB clock */ + TIMx->CR1 &= TIM_CLK_APB; + } + else + { + /* External/SCU clock */ + TIMx->CR1 |= TIM_CLK_EXTERNAL; + if (TIM_InitStruct->TIM_Clock_Edge == TIM_CLK_EDGE_RISING) + { + /* Clock rising edge */ + TIMx->CR1 |= TIM_CLK_EDGE_RISING; + } + else + { + /* Clock falling edge */ + TIMx->CR1 &= TIM_CLK_EDGE_FALLING; + } + } + +/************************** Prescaler configuration ***************************/ + + TIMx->CR2 =( TIMx->CR2 & 0xFF00 )|TIM_InitStruct->TIM_Prescaler ; + +/********************************** TIM Modes *********************************/ + + switch ( TIM_InitStruct->TIM_Mode) + { +/******************************* PWM Input mode *******************************/ + + case TIM_PWMI: + + /* Set the PWMI Bit */ + TIMx->CR1 |= TIM_PWMI; + + /* Set the first edge Level */ + if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + /* Set the Second edge Level ( Opposite of the first level ) */ + if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + else + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + + break; + +/************************** Output compare channel 1 **************************/ + + case TIM_OCM_CHANNEL_1: + + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC1_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + } + + break; + +/************************** Output compare channel 2 **************************/ + + case TIM_OCM_CHANNEL_2: + + if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2; + + if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC2_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC2_ENABLE_MASK; + } + + break; + +/************************ Output compare channel 1 & 2 ************************/ + + case TIM_OCM_CHANNEL_12: + + TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2; + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC2_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC2_ENABLE_MASK; + } + + if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC1_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + } + + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + break; + +/********************************** PWM mode **********************************/ + + case TIM_PWM: + + /* Set the Level During the pulse */ + if ( TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + /* Set the Level after the pulse */ + if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + /* Set the OCAE */ + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + + /* Set the PWM Bit */ + TIMx->CR1 |= TIM_PWM_MASK; + + /* Set the Duty Cycle value */ + if ( TIM_InitStruct->TIM_Pulse_Length_1 < 5 ) + { + TIM_InitStruct->TIM_Pulse_Length_1 = 4; + } + + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1 - 4; + + /* Set the Full Period */ + TIMx->OC2R = TIM_InitStruct->TIM_Full_Period - 4; + + break; + +/******************************* One pulse mode *******************************/ + + case TIM_OPM: + + /* Set the Level During the pulse */ + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + + /* Set the Level after the pulse */ + if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + + /* Set the Activation Edge on the ICAP 1 */ + if (TIM_InitStruct->TIM_OPM_INPUT_Edge == TIM_OPM_EDGE_RISING) + { + TIMx->CR1 |= TIM_OPM_EDGE_RISING; + } + + /* Set the Output Compare Function */ + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + + /* Set the One pulse mode */ + TIMx->CR1 |= TIM_OPM_MASK; + + /* Set the Pulse length */ + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + break; + +/*************************** Input capture channel 1 **************************/ + + case TIM_ICAP_CHANNEL_1: + + if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + break; + +/*************************** Input capture channel 2 **************************/ + + case TIM_ICAP_CHANNEL_2: + + if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + + break; + +/************************* Input capture channel 1 & 2 ************************/ + + case TIM_ICAP_CHANNEL_12: + if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + + if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterCmd +* Description : Enables or disables TIMx Counter peripheral. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_operation: specifies the new state of the TIMx Counter. +* This parameter can be one of the following values: +* - TIM_START: Start the timer counter. +* - TIM_STOP : Stop the timer counter. +* - TIM_CLEAR: Clear the timer counter. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation) +{ + switch (TIM_operation) + { + case TIM_START: + TIMx->CR1 |= TIM_ENABLE_MASK; + break; + + case TIM_STOP: + TIMx->CR1 &= TIM_DISABLE_MASK; + break; + + case TIM_CLEAR: + TIMx->CNTR = 0x1234; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : This routine is used to configure the TIMx prescaler value +* (when using the APB clock). +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Prescaler: specifies the prescaler value. This parameter +* can be a value from 0x0 to 0xFF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler) +{ + TIMx->CR2 &= 0xFF00; + TIMx->CR2 |= TIM_Prescaler; + +} +/******************************************************************************* +* Function Name : TIM_GetPrescalerValue +* Description : This routine is used to get the TIMx prescaler value +* (when using the APB clock). +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The prescaler value. +*******************************************************************************/ +u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx) +{ + return TIMx->CR2 & 0x00FF; +} + +/******************************************************************************* +* Function Name : TIM_GetCounterValue +* Description : This routine is used to get the TIMx counter value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The counter value. +*******************************************************************************/ +u16 TIM_GetCounterValue(TIM_TypeDef *TIMx) +{ + return TIMx->CNTR; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP1Value +* Description : This routine is used to get the Input Capture 1 value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The Input Capture 1 value. +*******************************************************************************/ +u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx) +{ + return TIMx->IC1R; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP2Value +* Description : This routine is used to get the Input Capture 2 value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The Input Capture 2 value. +*******************************************************************************/ +u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx) +{ + return TIMx->IC2R; +} + +/******************************************************************************* +* Function Name : TIM_SetPulse +* Description : This routine is used to set the pulse value. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Channel: specifies the needed channel. +* This parameter can be one of the following values: +* - TIM_PWM_OC1_Channel: PWM/Output Compare 1 Channel +* - TIM_OC2_Channel : Output Compare 2 Channel +* Input3 : TIM_Pulse: specifies the new pulse value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse) +{ + if (TIM_Channel == TIM_PWM_OC1_Channel) + { + TIMx->OC1R = TIM_Pulse; + } + else + { + TIMx->OC2R = TIM_Pulse; + } +} +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIMx flag is set or not. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Flag: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture Channel 1 Flag +* - TIM_FLAG_IC2: Input Capture Channel 2 Flag +* - TIM_FLAG_TO : Timer Overflow Flag +* - TIM_FLAG_OC1: Output Compare Channel 1 Flag +* - TIM_FLAG_OC2: Output Compare Channel 2 Flag +* Output : None +* Return : The NewState of the TIM_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag) +{ + if((TIMx->SR & TIM_Flag) == RESET) + { + return RESET; + } + else + { + return SET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIM Flag passed as a parameter. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Flag: specifies the flag to clear. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture Channel 1 Flag +* - TIM_FLAG_IC2: Input Capture Channel 2 Flag +* - TIM_FLAG_TO : Timer Overflow Flag +* - TIM_FLAG_OC1: Output Compare Channel 1 Flag +* - TIM_FLAG_OC2: Output Compare Channel 2 Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag) +{ + /* Clear TIM_Flag */ + TIMx->SR &= ~TIM_Flag; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPulse +* Description : This routine is used to get the Pulse value in PWMI Mode. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The pulse value. +*******************************************************************************/ +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx) +{ + return TIMx->IC2R; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPeriod +* Description : This routine is used to get the Period value in PWMI Mode. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The period value. +*******************************************************************************/ +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx) +{ + return TIMx->IC1R; +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Configures the Timer interrupt source. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_IT: specifies the TIM interrupt source to be enabled. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt source. +* - TIM_IT_OC1: Output Compare 1 Interrupt source. +* - TIM_IT_TO : Timer Overflow Interrupt source. +* - TIM_IT_IC2: Input Capture 2 Interrupt source. +* - TIM_IT_OC2: Output Compare 2 Interrupt source. +* Input3 : TIM_Newstate: specifies the new state of the TIMx IT. +* This parameter can be one of the following values: +* - ENABLE : Enable the needed interrupt. +* - DISABLE: Disable the needed interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate) +{ + if(TIM_Newstate == ENABLE) + { + TIMx->CR2 = (TIMx->CR2 & 0x00FF) | TIM_IT; + } + else + { + TIMx->CR2 &= ~TIM_IT; + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the Timer DMA source. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_DMA_Souces: specifies the TIM DMA source to be selected. +* This parameter can be one of the following values: +* - TIM_DMA_IC1: Input Capture 1 DMA source. +* - TIM_DMA_OCA1 Output Compare 1 DMA source. +* - TIM_DMA_TO: Timer Overflow DMA source. +* - TIM_DMA_IC2: Input Capture 2 DMA source. +* - TIM_DMA_OC2: Output Compare 2 DMA source. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources) +{ + /* Reset the DMAS[1:0] bits */ + TIMx->CR1 &= TIM_DMA_CLEAR_MASK; + /* Set the DMAS[1:0] bits according to TIM_DMA_Sources parameter */ + TIMx->CR1 |= TIM_DMA_Sources; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables TIMx DMA peripheral. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Newstate: new state of the TIMx DMA peripheral +* This parameter can be one of the following values: +* - ENABLE : Enable the TIMx DMA. +* - DISABLE: Disable the TIMx DMA. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate) +{ + if (TIM_Newstate == ENABLE) + { + TIMx->CR2 |= TIM_DMA_ENABLE; + } + else + { + TIMx->CR2 &= TIM_DMA_DISABLE; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_uart.c b/uc_str912/prj_blinky_complex_startup/src/91x_uart.c new file mode 100644 index 0000000..c31803b --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_uart.c @@ -0,0 +1,658 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_uart.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the UART software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_uart.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* UART IrDA Mask */ +#define UART_IrDA_Disable_Mask 0xFFFD /* IrDA Disable Mask */ +#define UART_IrDA_Enable_Mask 0x0002 /* IrDA Enable Mask */ +#define IrDA_LowPower_Enable_Mask 0x0004 /*IrDA lower power mode enable*/ +#define IrDA_LowPower_Disable_Mask 0xFFFB /*IrDA lower power mode enable*/ + +/* UART Mask */ +#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ +#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ + +/* UART LoopBack */ +#define UART_LoopBack_Disable_Mask 0xFF7F /* LoopBack Disable Mask */ +#define UART_LoopBack_Enable_Mask 0x0080 /* LoopBack Enable Mask */ + +#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ +#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ +#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ +#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ +#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask*/ +#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ +#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ +#define UART_RTS_LowLevel_Mask 0x0800 /* RTS signal is low */ +#define UART_RTS_HighLevel_Mask 0xF7FF /* RTS signal is High */ +#define UART_DTR_LowLevel_Mask 0x0400 /* DTR signal is low */ +#define UART_DTR_HighLevel_Mask 0xFBFF /* DTR signal is High */ +#define UART_ClearFlag_Mask 0xAA /* Clear Flag Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + /******************************************************************************* +* Function Name : UART_DeInit +* Description : Deinitializes the UARTx peripheral registers +* to their default reset values. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DeInit(UART_TypeDef* UARTx) +{ + /* Reset the UARTx registers values */ + if(UARTx == UART0) + { + SCU_APBPeriphReset(__UART0,ENABLE); + SCU_APBPeriphReset(__UART0,DISABLE); + } + else if(UARTx == UART1) + { + SCU_APBPeriphReset(__UART1,ENABLE); + SCU_APBPeriphReset(__UART1,DISABLE); + } + else if(UARTx == UART2) + { + SCU_APBPeriphReset(__UART2,ENABLE); + SCU_APBPeriphReset(__UART2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : UART_Init +* Description : Initializes the UARTx peripheral according to the specified +* parameters in the UART_InitStruct . +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_InitStruct: pointer to a UART_InitTypeDef structure +* that contains the configuration information for the +* specified UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + + u64 UART_MainClock = 0; + u32 IntegerDivider = 0; + u32 FractionalDivider = 0; + + /* Clear the LCR[6:5] bits */ + UARTx->LCR &= UART_WordLength_Mask; + /* Set the LCR[6:5] bits according to UART_WordLength value */ + UARTx->LCR |= UART_InitStruct->UART_WordLength; + + /* Choose Stop Bits */ + if(UART_InitStruct->UART_StopBits == UART_StopBits_2) + { + /* 2 Stop Bit */ + UARTx->LCR |= UART_StopBits_2; + } + else + { + /* One Stop Bits */ + UARTx->LCR &= UART_StopBits_1; + } + + /* Configure the Parity */ + /* Clear the LCR[7]and LCR[2:1] bits */ + UARTx->LCR &= UART_Parity_Mask; + /* Set the LCR[7]and LCR[2:1] bits according to UART_Parity value */ + UARTx->LCR |= UART_InitStruct->UART_Parity; + + /* Configure the BaudRate */ + UART_MainClock = (SCU_GetMCLKFreqValue())*1000; + if((SCU->CLKCNTR & 0x200) != 0x200) + { + UART_MainClock = UART_MainClock/2; + } + /* Determine the integer part */ + IntegerDivider = ((100) * (UART_MainClock) / (16 * (UART_InitStruct->UART_BaudRate))); + UARTx->IBRD = IntegerDivider / 100; + + /* Determine the fractional part */ + FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); + UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); + + /* Choose the Hardware Flow Control */ + /* Clear the CR[15:14] bits */ + UARTx->CR &= UART_HardwareFlowControl_Mask; + /* Set the CR[15:14] bits according to UART_HardwareFlowControl value */ + UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; + + /* Configure the UART mode */ + /* Clear the CR[9:8] bits */ + UARTx->CR &= UART_Mode_Mask; + /* Set the CR[9:8] bits according to UART_Mode value */ + UARTx->CR |= UART_InitStruct->UART_Mode; + + /* Enable or disable the FIFOs */ + /* Set the FIFOs Levels */ + if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) + { + /* Enable the FIFOs */ + UARTx->LCR |= UART_FIFO_Enable; + + /* Clear TXIFLSEL and RXIFLSEL bits */ + UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; + + /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ + UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); + + /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ + UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; + } + else + { + /* Disable the FIFOs */ + UARTx->LCR &= UART_FIFO_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_StructInit +* Description : Fills each UART_InitStruct member with its reset value. +* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* Reset the UART_InitStruct members */ + UART_InitStruct->UART_WordLength = UART_WordLength_8D; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_Odd ; + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; + UART_InitStruct->UART_FIFO = UART_FIFO_Enable; + UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; + UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; +} + +/******************************************************************************* +* Function Name : UART_Cmd +* Description : Enables or disables the specified UART peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected UART by setting the UARTEN bit in the CR register */ + UARTx->CR |= UART_Enable_Mask; + } + else + { + /* Disable the selected UART by clearing the UARTEN bit in the CR register */ + UARTx->CR &= UART_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_ITConfig +* Description : Enables or disables the specified UART interrupts. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_IT: specifies the UART interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enables the selected interrupts */ + UARTx->IMSC |= UART_IT; + } + else + { + /* Disables the selected interrupts */ + UARTx->IMSC &= ~UART_IT; + } +} + +/******************************************************************************* +* Function Name : UART_DMAConfig +* Description : Configures the UARTx’s DMA interface. +* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral +* - UART_DMAOnError: specifies the DMA on error request. +* This parameter can be: +* - UART_DMAOnError_Enable: DMA receive request enabled +* when the UART error interrupt is asserted. +* - UART_DMAOnError_Disable: DMA receive request disabled +* when the UART error interrupt is asserted. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError) +{ + if(UART_DMAOnError == UART_DMAOnError_Enable) + { + UARTx->DMACR &= UART_DMAOnError_Enable; + } + else + { + UARTx->DMACR |= UART_DMAOnError_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_DMACmd +* Description : Enables or disables the UARTx’s DMA interface. +* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral +* - UART_DMAReq: enables or disables the request of DMA from UART. +* This parameter can be: +* - UART_DMAReq_Tx: Transmit DMA Enable +* - UART_DMAReq_Rx: Receive DMA Enable +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState) +{ + if(UART_DMAReq == UART_DMAReq_Tx) + { + if(NewState == ENABLE) + { + UARTx->DMACR |= UART_DMAReq_Tx; + } + else + { + UARTx->DMACR &= ~UART_DMAReq_Tx; + } + } + + if(UART_DMAReq == UART_DMAReq_Rx) + { + if(NewState == ENABLE) + { + UARTx->DMACR |= UART_DMAReq_Rx; + } + else + { + UARTx->DMACR &= ~UART_DMAReq_Rx; + } + } +} + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : Enables or disables the LoopBack mode. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the LoopBack mode of the specified UART */ + UARTx->CR |= UART_LoopBack_Enable_Mask; + } + else + { + /* Disable the LoopBack mode of the specified UART */ + UARTx->CR &= UART_LoopBack_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_GetFlagStatus +* Description : Checks whether the specified UART flag is set or not. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* - UART_FLAG_RI: RI flag +* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag +* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag +* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag +* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag +* - UART_FLAG_Busy: UART Busy flag +* - UART_FLAG_CTS: CTS flag +* - UART_FLAG_DCD: DCD flag +* - UART_FLAG_DSR: DSR flag +* - UART_RawIT_OverrunError: Overrun Error interrupt flag +* - UART_RawIT_BreakError: Break Error interrupt flag +* - UART_RawIT_ParityError: Parity Error interrupt flag +* - UART_RawIT_FrameError: Frame Error interrupt flag +* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag +* - UART_RawIT_Transmit: Transmit interrupt flag +* - UART_RawIT_Receive: Receive interrupt flag +* - UART_RawIT_DSR: DSR interrupt flag +* - UART_RawIT_DCD: DCD interrupt flag +* - UART_RawIT_CTS: CTS interrupt flag +* - UART_RawIT_RI: RI interrupt flag +* Output : None +* Return : The new state of UART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + + u32 UARTReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the UART register index */ + UARTReg = UART_FLAG >> 5; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + if(UARTReg == 1) /* The flag to check is in RSR register */ + { + StatusReg = UARTx->RSECR; + } + else if (UARTReg == 2) /* The flag to check is in FR register */ + { + StatusReg = UARTx->FR; + } + else if(UARTReg == 3) /* The flag to check is in RIS register */ + { + StatusReg = UARTx->RIS; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearFlag +* Description : Clears the UARTx’s flags(Frame, Parity, Break, Overrun error). +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearFlag(UART_TypeDef* UARTx) +{ + /* Clear the flag */ + UARTx->RSECR = UART_ClearFlag_Mask; +} + +/******************************************************************************* +* Function Name : UART_GetITStatus +* Description : Checks whether the specified UART interrupt has occured or not. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to be checked. +* This parameter can be one of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* Output : None +* Return : The new state of UART_IT (SET or RESET). +*******************************************************************************/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) +{ + if((UARTx->MIS & UART_IT) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearITPendingBit +* Description : Clears the UARTx’s interrupt pending bits. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to clear. +* More than one interrupt can be cleared using the “|” operator. +* This parameter can be: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) +{ + /* Clear the specified interrupt */ + UARTx->ICR &= UART_IT; +} + +/******************************************************************************* +* Function Name : UART_IrDALowPowerConfig +* Description : Sets the IrDA low power mode +* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. +* - NewState: new state of the UARTIrDA peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState) +{ + UART_TypeDef* UARTx = UART0; + + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + + if (NewState == ENABLE) + { + UARTx->CR |= IrDA_LowPower_Enable_Mask; + } + else + { + UARTx->CR &= IrDA_LowPower_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_IrDASetCounter +* Description : Sets the IrDA counter divisor value. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. +* - IrDA_Counter: IrDA counter divisor new value n low power mode(Hz). +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter) +{ + UART_TypeDef* UARTx = UART0; + u32 APBClock; + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + /* Get the APB frequency */ + APBClock = (SCU_GetPCLKFreqValue())*1000; + /* Determine the Counter Divisor part */ + UARTx->ILPR = (((APBClock*10) / ( IrDA_Counter)) + 5 )/10; + } + +/******************************************************************************* +* Function Name : UART_IrDACmd +* Description : Enables or disables the UARTx’s IrDA interface. +* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDACmd(u8 IrDAx, FunctionalState NewState) +{ + UART_TypeDef* UARTx = UART0; + + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + if(NewState == ENABLE) + { + /* Enable the IrDA mode of the specified UART */ + UARTx->CR |= UART_IrDA_Enable_Mask; + } + else + { + /* Disable the IrDA mode of the specified UART */ + UARTx->CR &= UART_IrDA_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_SendData +* Description : Transmits signle Byte of data through the UARTx peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - Data: the byte to transmit +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendData(UART_TypeDef* UARTx, u8 Data) +{ + /* Transmit one byte */ + UARTx->DR = Data; +} + +/******************************************************************************* +* Function Name : UART_ReceiveData +* Description : Returns the most recent received Byte by the UARTx peripheral. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : The received data +*******************************************************************************/ +u8 UART_ReceiveData(UART_TypeDef* UARTx) +{ + /* Receive one byte */ + return ((u8)UARTx->DR); +} + +/******************************************************************************* +* Function Name : UART_SendBreak +* Description : Transmits break characters. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendBreak(UART_TypeDef* UARTx) +{ + /* Send break characters */ + UARTx->LCR |= UART_BreakChar_Mask; +} + +/******************************************************************************* +* Function Name : UART_RTSConfig +* Description : Sets or Resets the RTS signal +* Input : - LevelState: new state of the RTS signal for UART0 only. +* This parameter can be: LowLevel or HighLevel +* Output : None +* Return : None +*******************************************************************************/ +void UART_RTSConfig(UART_LevelTypeDef LevelState) +{ + if(LevelState == LowLevel) + { + UART0->CR |= UART_RTS_LowLevel_Mask; + } + else + { + UART0->CR &= UART_RTS_HighLevel_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_DTRConfig +* Description : Sets or Resets the DTR signal for UART0 only +* Input : - LevelState: new state of the DTR signal. +* This parameter can be: LowLevel or HighLevel +* Output : None +* Return : None +*******************************************************************************/ +void UART_DTRConfig(UART_LevelTypeDef LevelState) +{ + if(LevelState == LowLevel) + { + UART0->CR |= UART_DTR_LowLevel_Mask; + } + else + { + UART0->CR &= UART_DTR_HighLevel_Mask; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_vic.c b/uc_str912/prj_blinky_complex_startup/src/91x_vic.c new file mode 100644 index 0000000..fecb890 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_vic.c @@ -0,0 +1,830 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_vic.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the VIC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_vic.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define VIC_REGISTER_NUMBER 16 +#define VIC_PROTECTION_ENABLE_MASK 0x1 +#define VIC_PROTECTION_DISABLE_MASK 0xFFFFFFFE +#define VIC_VECTOR_ENABLE_MASK 0x20 +#define VIC_IT_SOURCE_MASK 0xFFFFFFE0 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode); +static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ + void (*VIC_VectAddress)(void)); +static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority); +static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority); + +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : VIC_DeInit +* Description : Deinitialize the VIC module registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void VIC_DeInit(void) +{ + SCU_AHBPeriphReset(__VIC, ENABLE); /* VIC peripheral is under Reset */ + SCU_AHBPeriphReset(__VIC, DISABLE); /* VIC peripheral Reset off */ +} + +/******************************************************************************* +* Function Name : VIC_GetIRQStatus +* Description : Get the status of interrupts after IRQ masking. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the IRQ interrupt after masking (SET or RESET). +*******************************************************************************/ +FlagStatus VIC_GetIRQStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->ISR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->ISR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_GetFIQStatus +* Description : Get the status of interrupts after FIQ masking +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the FIQ interrupt after masking (SET or RESET) +*******************************************************************************/ +FlagStatus VIC_GetFIQStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->RINTSR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->RINTSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_GetSourceITStatus +* Description : Get the status of the source interrupts before masking. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the source interrupt before masking +*******************************************************************************/ +FlagStatus VIC_GetSourceITStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->FSR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->FSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_ITModeConfig +* Description : Select the type of interrupt (IRQ or FIQ) +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_LineMode :specifies the type of interrupt of the source +* line. This parameter can be one of the following values: +* - VIC_IRQ: the correspondent line is configured as IRQ. +* - VIC_FIQ: the correspondent line is configured as FIQ. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode) +{ + u32 VIC_Mask = 1; + + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + { + if (VIC_LineMode == VIC_IRQ) + VIC0->INTSR &= ~(VIC_Mask << VIC_Source); + else /* VIC_LineMode == VIC_FIQ */ + VIC0->INTSR |= (VIC_Mask << VIC_Source); + } + else /* VIC1 */ + { + if (VIC_LineMode == VIC_IRQ) + VIC1->INTSR &= ~(VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + else /* VIC_LineMode == VIC_FIQ */ + VIC1->INTSR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_ITCmd +* Description : Enable or disable the interrupt request lines. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : FMI_NewState: specifies the line status. +* This parameter can be one of the following values: +* - ENABLE: The line is enabled. +* - DISABLE: The line is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState) +{ + u32 VIC_Mask = 1; + + if (VIC_NewState == ENABLE) + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->INTER |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->INTER |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } + else /* VIC_NewState == DISABLE */ + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->INTECR |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->INTECR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_SWITCmd +* Description : Generate a software interrupt for the specific source +* interrupt. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : FMI_NewState: specifies the software interrupt status. +* This parameter can be one of the following values: +* - ENABLE: The software interrupt is enabled. +* - DISABLE: The software interrupt is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState) +{ + u32 VIC_Mask = 1; + + if (VIC_NewState == ENABLE) + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->SWINTR |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->SWINTR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } + else /* VIC_NewState == DISABLE */ + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->SWINTCR = (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->SWINTCR = (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_ProtectionCmd +* Description : Enable or Disable the register access protection. +* Input : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: The protection is enabled. +* - DISABLE: The protection is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_ProtectionCmd(FunctionalState VIC_NewState) +{ + if (VIC_NewState == ENABLE) + { + VIC0->PER |= VIC_PROTECTION_ENABLE_MASK; + VIC1->PER |= VIC_PROTECTION_ENABLE_MASK; + } + else + { + VIC0->PER &= VIC_PROTECTION_DISABLE_MASK; + VIC1->PER &= VIC_PROTECTION_DISABLE_MASK; + } +} + +/******************************************************************************* +* Function Name : VIC_GetCurrentISRAdd +* Description : Get the address of the current active ISR. +* Input : VICx: specifies the VIC peripheral +* This parameter can be one of the following values: +* - VIC0: To select VIC0. +* - VIC1: To select VIC1. +* Output : None +* Return : The Address of the active ISR. +*******************************************************************************/ +u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx) +{ + return VICx->VAR; +} + +/******************************************************************************* +* Function Name : VIC_ISRVectAddConfig +* Description : Configuration of the ISR vector address. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Input3 : void (*VIC_VectAddress)(void): specifies the ISR vector +* address pointer. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ + void (*VIC_VectAddress)(void)) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->VAiR[VIC_Priority] = (u32)VIC_VectAddress; + else /* VIC1 */ + VIC1->VAiR[VIC_Priority] = (u32)VIC_VectAddress; +} + +/******************************************************************************* +* Function Name : VIC_GetISRVectAdd +* Description : Get the ISR vector address of the correspondent line. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The correspondent ISR vector address. +*******************************************************************************/ +u32 VIC_GetISRVectAdd(u16 VIC_Source) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + return VIC0->VAiR[VIC_Source]; + else /* VIC1 */ + return VIC1->VAiR[VIC_Source - VIC_REGISTER_NUMBER]; +} + +/******************************************************************************* +* Function Name : VIC_VectEnableConfig +* Description : Enable the vector interrupt. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; + else /* VIC1 */ + VIC1->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; +} + +/******************************************************************************* +* Function Name : VIC_ITSourceConfig +* Description : Select the interrupt source. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + { + VIC0->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; + VIC0->VCiR[VIC_Priority] |= VIC_Source; + } + else /* VIC1 */ + { + VIC1->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; + VIC1->VCiR[VIC_Priority] |= VIC_Source - VIC_REGISTER_NUMBER; + } +} + +/******************************************************************************* +* Function Name : VIC_Config +* Description : Configure the ISR, the line, the mode and the priority for +* each interrupt source line. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_LineMode :specifies the type of interrupt of the source +* line. This parameter can be one of the following values: +* - VIC_IRQ: the correspondent line is configured as IRQ. +* - VIC_FIQ: the correspondent line is configured as FIQ. +* Input3 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority) +{ + switch (VIC_Source) + { + case 0: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WDG_IRQHandler); + break; + + case 1: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SW_IRQHandler); + break; + + case 2: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMRX_IRQHandler); + break; + + case 3: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMTX_IRQHandler); + break; + + case 4: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM0_IRQHandler); + break; + + case 5: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM1_IRQHandler); + break; + + case 6: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM2_IRQHandler); + break; + + case 7: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM3_IRQHandler); + break; + + case 8: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBHP_IRQHandler); + break; + + case 9: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBLP_IRQHandler); + break; + + case 10: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SCU_IRQHandler); + break; + + case 11: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ENET_IRQHandler); + break; + + case 12: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, DMA_IRQHandler); + break; + + case 13: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, CAN_IRQHandler); + break; + + case 14: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, MC_IRQHandler); + break; + + case 15: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ADC_IRQHandler); + break; + + case 16: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART0_IRQHandler); + break; + + case 17: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART1_IRQHandler); + break; + + case 18: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART2_IRQHandler); + break; + + case 19: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C0_IRQHandler); + break; + + case 20: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C1_IRQHandler); + break; + + case 21: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP0_IRQHandler); + break; + + case 22: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP1_IRQHandler); + break; + + case 23: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, LVD_IRQHandler); + break; + + case 24: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, RTC_IRQHandler); + break; + + case 25: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WIU_IRQHandler); + break; + + case 26: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT0_IRQHandler); + break; + + case 27: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT1_IRQHandler); + break; + + case 28: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT2_IRQHandler); + break; + + case 29: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT3_IRQHandler); + break; + + case 30: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBWU_IRQHandler); + break; + + case 31: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, PFQBC_IRQHandler); + break; + + default: break; + } + VIC_ITModeConfig(VIC_Source, VIC_LineMode); + VIC_VectEnableConfig(VIC_Source, VIC_Priority); + VIC_ITSourceConfig(VIC_Source, VIC_Priority); +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_wdg.c b/uc_str912/prj_blinky_complex_startup/src/91x_wdg.c new file mode 100644 index 0000000..f933635 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_wdg.c @@ -0,0 +1,277 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wdg.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the WDG software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_wdg.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + + +/* WDG End of Count interrupt Flag */ +#define WDG_FLAG_EC 0x0001 + + +/* WDG End of Count interrupt request */ +#define WDG_IT_EC 0x0001 + + + +/* WDG Start/Stop counter */ +#define WDG_Counter_Start 0x0002 +#define WDG_Counter_Stop 0xFFFD + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : WDG_DeInit +* Description : Deinitializes the WDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_DeInit(void) +{ + + SCU_APBPeriphReset(__WDG, ENABLE); /*WDG peripheral under Reset */ + SCU_APBPeriphReset(__WDG, DISABLE); /*WDG peripheral Reset off*/ + +} + +/******************************************************************************* +* Function Name : WDG_StructInit +* Description : Fills the WDG_InitTypeDef structure member with its reset +* value. +* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) +{ + /* Select the Watchdog running mode*/ + WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; + + /* Select the source clock */ + WDG_InitStruct-> WDG_ClockSource = WDG_ClockSource_Apb; + + /* Initialize Prescaler */ + WDG_InitStruct->WDG_Prescaler =0xFF; + + /* Initialize Preload */ + WDG_InitStruct->WDG_Preload =0xFFFF; + + +} + +/******************************************************************************* +* Function Name : WDG_Init +* Description : Initializes WDG peripheral according to the specified +* parameters in the WDG_InitStruct. +* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that +* contains the configuration information for the WDG peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) +{ + + + if(WDG_InitStruct->WDG_ClockSource == WDG_ClockSource_Apb) + { + /* Select The APB clock as clock source */ + WDG->CR &= WDG_ClockSource_Apb; + } + + else + { + /* Select the RTC clock as source */ + WDG->CR |= WDG_ClockSource_Rtc ; + } + + + /* Configure WDG Prescaler register value */ + WDG->PR = WDG_InitStruct->WDG_Prescaler; + + /* Configure WDG Pre-load register value */ + WDG->VR = WDG_InitStruct->WDG_Preload ; + + + if(WDG_InitStruct->WDG_Mode == WDG_Mode_Timer) + { + /* Select Timer mode */ + WDG->CR &= WDG_Mode_Timer; + } + else + { + /* Select WDG mode */ + WDG->CR |= WDG_Mode_Wdg ; + } + + +} + +/******************************************************************************* +* Function Name : WDG_Cmd +* Description : Enables or disables the WDG peripheral. +* Input : NewState: new state of the WDG peripheral (Newstate can be +* ENABLE or DISABLE) +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Cmd(FunctionalState NewState ) +{ + if((WDG->CR & WDG_Mode_Wdg) == 0) + { + /* Timer mode */ + if(NewState == ENABLE) + { + /* Start timer by setting SC bit in Control register */ + WDG->CR |= WDG_Counter_Start; + } + else + { + /* Stop timer by clearning SC bit in Control register */ + WDG->CR &= WDG_Counter_Stop; + } + } + else + { + /* Watchdog mode */ + if(NewState == ENABLE) + { + WDG->KR = WDG_KeyValue1; + WDG->KR = WDG_KeyValue2; + } + } +} + +/******************************************************************************* +* Function Name : WDG_ITConfig +* Description : Enables or disables the WDG End of Count(EC) interrupt. +* Input : Newstate: new state of the End of Count(EC) WDG interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ITConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the End of Count interrupt */ + WDG->MR |= WDG_IT_EC; + } + else + { + /* Disable the End of Count interrupt */ + WDG->MR &= ~WDG_IT_EC; + } +} + +/******************************************************************************* +* Function Name : WDG_GetCounter +* Description : Gets the WDG’s current counter value. +* Input : None +* Output : None +* Return : The WDG current counter value +*******************************************************************************/ +u16 WDG_GetCounter(void) +{ + return WDG->CNT; +} + + + + +/******************************************************************************* +* Function Name : WDG_GetITStatus +* Description : Checks whether the WDG End of Count(EC) interrupt is occured or not. +* Input : None +* Output : None +* Return : The new state of WDG_IT (SET or RESET). +*******************************************************************************/ +ITStatus WDG_GetITStatus(void) +{ + if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearITPendingBit +* Description : Clears the WDG's End of Count(EC) interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearITPendingBit(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_IT_EC; + +} + +/******************************************************************************* +* Function Name : WDG_ClearFlag +* Description : Clears the WDG's End of Count(EC) Flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearFlag(void) +{ + /* Clear the EC Flag */ + + WDG->SR &= ~WDG_FLAG_EC; + +} + + +/******************************************************************************* +* Function Name : WDG_GetFlagStatus +* Description : Checks whether the WDG End of Count(EC) flag is set or not. +* Input : None +* Output : None +* Return : The new state of the WDG_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus WDG_GetFlagStatus(void) +{ + if((WDG->SR & WDG_FLAG_EC) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/91x_wiu.c b/uc_str912/prj_blinky_complex_startup/src/91x_wiu.c new file mode 100644 index 0000000..3154a3c --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/91x_wiu.c @@ -0,0 +1,190 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wiu.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the WIU software functions. +********************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +/* Standard include ----------------------------------------------------------*/ +#include "91x_wiu.h" +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/****************************************************************************** +* Function Name : WIU_Init +* Description : Initializes the WIU unit according to the specified parameters +* in the WIU_InitTypeDef structure. +* Input : WIU_InitStruct: pointer to a WIU_InitTypeDef structure that +* contains the configuration information for the WIU peripheral. +* Output : None +* Return : None +******************************************************************************/ +void WIU_Init(WIU_InitTypeDef* WIU_InitStruct) +{ + /* select the Wake-up line to be used */ + WIU->MR |= WIU_InitStruct->WIU_Line; + + /* configure the triggering edge */ + if(WIU_InitStruct->WIU_TriggerEdge == WIU_RisingEdge) + { + /* trigger on rising edge */ + WIU->TR |= WIU_InitStruct->WIU_Line; + } + else + { + /* trigger on falling edge */ + WIU->TR &= ~WIU_InitStruct->WIU_Line; + } + + if(WIU_InitStruct->WIU_Mode == WIU_Mode_SWInterrupt) + { + /* enable interrupt mode */ + WIU->CTRL |= WIU_Mode_Interrupt; + + /* set the corresponding WUINT bit*/ + WIU->INTR |= WIU_InitStruct->WIU_Line; + } + else + { + /* configure the WIU mode */ + WIU->CTRL |= WIU_InitStruct->WIU_Mode; + } +} + +/****************************************************************************** +* Function Name : WIU_DeInit +* Description : Deinitializes the WIU registers to their default reset values. +* Input : None +* Output : None +* Return : None +******************************************************************************/ +void WIU_DeInit(void) +{ + /* initialize the WIU registers to their reset value */ + SCU_APBPeriphReset(__WIU, ENABLE); + SCU_APBPeriphReset(__WIU, DISABLE); +} + +/****************************************************************************** +* Function Name : WIU_StructInit +* Description : Fills in a WIU_InitTypeDef structure with the reset value of +* each parameter. +* Input : WIU_InitStruct : pointer to a WIU_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +******************************************************************************/ +void WIU_StructInit(WIU_InitTypeDef* WIU_InitStruct) +{ + /* initialize the WIU_InitStruct fields to their reset values */ + WIU_InitStruct->WIU_Mode = 0x0 ; + WIU_InitStruct->WIU_Line = 0x0 ; + WIU_InitStruct->WIU_TriggerEdge = WIU_FallingEdge ; +} + + +/******************************************************************************* +* Function Name : WIU_GenerateSWInterrupt +* Description : Generates a Software interrupt. +* Input : - WIU_Line: specifies the WIU lines to be enabled or +* disabled. This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : None +*******************************************************************************/ +void WIU_GenerateSWInterrupt(u32 WIU_Line) +{ + WIU->INTR |= WIU_Line; +} + +/******************************************************************************* +* Function Name : WIU_GetFlagStatus +* Description : Checks whether the specified WIU line flag is set or not. +* Input : - WIU_Line: specifies the WIU lines flag to check. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : The new state of WIU_Line (SET or RESET). +*******************************************************************************/ +FlagStatus WIU_GetFlagStatus(u32 WIU_Line) +{ + if((WIU->PR & WIU_Line) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WIU_ClearFlag +* Description : Clears the WIU’s line pending flags. +* Input : - WIU_Line: specifies the WIU lines flags to clear. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : None +*******************************************************************************/ +void WIU_ClearFlag(u32 WIU_Line) +{ + WIU->PR = WIU_Line; +} + +/******************************************************************************* +* Function Name : WIU_GetITStatus +* Description : Checks whether the specified WIU line is asserted or not. +* Input : - WIU_Line: specifies the WIU lines to check. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : The new state of WIU_Line (SET or RESET). +*******************************************************************************/ +ITStatus WIU_GetITStatus(u32 WIU_Line) +{ + if(((WIU->PR & WIU_Line) != RESET)&& ((WIU->MR & WIU_Line) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WIU_ClearITPendingBit +* Description : Clears the WIU’s line pending bits. +* Input : - WIU_Line: specifies the WIU lines to clear. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : None +*******************************************************************************/ +void WIU_ClearITPendingBit(u32 WIU_Line) +{ + WIU->PR = WIU_Line; +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_complex_startup/src/usb_core.c b/uc_str912/prj_blinky_complex_startup/src/usb_core.c new file mode 100644 index 0000000..aacc3d4 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/usb_core.c @@ -0,0 +1,860 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_core.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : USB protocol state machine functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#include "USB_lib.h" + +#define ValBit(VAR,Place) (VAR & (1<Current_Configuration); + return (BYTE *)&pInformation->Current_Configuration; +} /* Standard_GetConfiguration */ + +/******************************************************************************* +* Function Name : Standard_SetConfiguration +* Description : This routine is called to set the configuration value +* Input : None +* Output : None +* Return : Return USB_SUCCESS, if the request is performed +* Return UNSUPPORT, if the request is invalid +*******************************************************************************/ +RESULT Standard_SetConfiguration(void) +{ + if (pInformation->USBwValue0 <= Device_Table.Total_Configuration + && pInformation->USBwValue1==0 && pInformation->USBwIndex==0) + { + pInformation->Current_Configuration = pInformation->USBwValue0; + return USB_SUCCESS; + } + else + return UNSUPPORT; +} /* Standard_SetConfiguration */ + +/******************************************************************************* +* Function Name : Standard_GetInterface +* Description : Return the Alternate Setting of the current interface +* Input : Length +* Output : None +* Return : Return a pointer on Current_AlternateSetting value +* if length is not 0 +*******************************************************************************/ +BYTE *Standard_GetInterface(WORD Length) +{ + if (Length == 0) + return (BYTE *)sizeof(pInformation->Current_AlternateSetting); + return (BYTE *)&pInformation->Current_AlternateSetting; +} /* Standard_GetInterface */ + +/******************************************************************************* +* Function Name : Standard_SetInterface +* Description : This routine is called to set the interface alternate settings +* Input : None +* Output : None +* Return : USB_SCCESS or UNSUPPORT +*******************************************************************************/ +RESULT Standard_SetInterface(void) +{ + DEVICE_INFO *pInfo = pInformation; + DEVICE_PROP *pProp = pProperty; + RESULT Re; + + /*test if the specified Interface and Alternate Setting + are supported by the application Firmware*/ + Re = (*pProp->Class_Get_Interface_Setting)(pInfo->USBwIndex0,pInfo->USBwValue0); + if(pInfo->Current_Configuration==0 ) + return UNSUPPORT; + else + { + if (Re!= USB_SUCCESS || pInfo->USBwIndex1!=0 || pInfo->USBwValue1!=0) + return UNSUPPORT; + else if ( Re == USB_SUCCESS) + { + pInfo->Current_Interface = pInfo->USBwIndex0; + pInfo->Current_AlternateSetting = pInfo->USBwValue0; + return USB_SUCCESS; + } + else return UNSUPPORT; + } +} /* Standard_SetInterface */ + + +/******************************************************************************* +* Function Name : Standard_GetStatus +* Description : GetStatus request processing (device, interface or endpoint) +* Input : None +* Output : None +* Return : pointer on StatusInfo +*******************************************************************************/ + +BYTE *Standard_GetStatus(WORD Length) +{ + DEVICE_INFO *pInfo = pInformation; + if (Length == 0) + return (BYTE *)2; + StatusInfo.w = 0; + /* Reset Status Information */ + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + /*Get Device Status */ + BYTE Feature = pInfo->Current_Feature; + if (ValBit(Feature, 5)) + SetBit(StatusInfo0, 1); /* Remote Wakeup enabled */ + if (ValBit(Feature, 7)) + ClrBit(StatusInfo0, 0); /* Bus-powered */ + else if (ValBit(Feature, 6)) + SetBit(StatusInfo0, 0); /* Self-powered */ + } + else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))/*Interface Status*/ + return (BYTE *)&StatusInfo; + else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { + /*Get EndPoint Status*/ + BYTE Related_Endpoint; + BYTE wIndex0 = pInfo->USBwIndex0; + Related_Endpoint = (wIndex0 & 0x0f); + if (ValBit(wIndex0, 7)) + { + /* IN endpoint */ + if (_GetTxStallStatus( Related_Endpoint )) + SetBit(StatusInfo0, 0); /* IN Endpoint stalled */ + } + else + { + /* OUT endpoint */ + if (_GetRxStallStatus( Related_Endpoint )) + SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */ + } + } + else + return NULL; + return (BYTE *)&StatusInfo; +} /* Standard_GetStatus */ + + +/******************************************************************************* +* Function Name : Standard_ClearFeature +* Description : Clear (or disable) a specific feature (device or endpoint) +* Input : None +* Output : None +* Return : USB_SUCCESS or UNSUPPORT +*******************************************************************************/ +RESULT Standard_ClearFeature(void) +{ + DEVICE_INFO *pInfo = pInformation; + BYTE Type_Rec = Type_Recipient; + WORD Status; + if ( Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT) ) + { + if (pInfo->USBwValue != DEVICE_REMOTE_WAKEUP) + return UNSUPPORT; + /*Device Clear Feature*/ + ClrBit(pInfo->Current_Feature, 5); + return USB_SUCCESS; + } + else if ( Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT) ) + { + /*EndPoint Clear Feature*/ + DEVICE* pDev; + BYTE Related_Endpoint; + BYTE wIndex0; + BYTE rEP; + if (pInfo->USBwValue != ENDPOINT_STALL || pInfo->USBwIndex1!=0) + return UNSUPPORT; + pDev = &Device_Table; + wIndex0 = pInfo->USBwIndex0; + rEP = wIndex0 & ~0x80; + Related_Endpoint = ENDP0 + rEP; + if (ValBit(pInfo->USBwIndex0, 7)) + Status =_GetEPTxStatus(Related_Endpoint); + /*get Status of endpoint & stall the request if the related_ENdpoint is Disabled*/ + else Status =_GetEPRxStatus(Related_Endpoint); + if (rEP >= pDev->Total_Endpoint || Status==0 || pInfo->Current_Configuration==0) + return UNSUPPORT; + if (wIndex0 & 0x80) + { + /* IN endpoint */ + if (_GetTxStallStatus(Related_Endpoint )) + _SetEPTxStatus(Related_Endpoint, EP_TX_NAK); + } + else + { + /* OUT endpoint */ + if (_GetRxStallStatus(Related_Endpoint)) + { + if (Related_Endpoint == ENDP0) + { + /* After clear the STALL, enable the default endpoint receiver */ + _SetEPRxStatus(Related_Endpoint, EP_RX_VALID); + } + else + _SetEPRxStatus(Related_Endpoint, EP_RX_NAK); + } + } + return USB_SUCCESS; + } + return UNSUPPORT; +} /* Standard_ClearFeature */ + + +/******************************************************************************* +* Function Name : Standard_SetEndPointFeature +* Description : Sets endpoint feature +* Input : None +* Output : None +* Return : USB_SUCCESS or UNSUPPORT +*******************************************************************************/ +RESULT Standard_SetEndPointFeature(void) +{ + DEVICE_INFO *pInfo = pInformation; + BYTE wIndex0; + BYTE Related_Endpoint; + BYTE rEP; + WORD Status; + wIndex0 = pInfo->USBwIndex0; + rEP = wIndex0 & ~0x80; + Related_Endpoint = ENDP0 + rEP; + if (ValBit(pInfo->USBwIndex0, 7)) + Status =_GetEPTxStatus(Related_Endpoint);// get Status of endpoint & stall the request if + //the related_ENdpoint is Disable + else Status =_GetEPRxStatus(Related_Endpoint); + if (Related_Endpoint >= Device_Table.Total_Endpoint || pInfo->USBwValue !=0 || Status==0 || + pInfo->Current_Configuration==0 /*&& Related_Endpoint!=ENDP0)*/) + return UNSUPPORT; + else + { + if (wIndex0 & 0x80) + { + /* IN endpoint */ + _SetEPTxStatus(Related_Endpoint, EP_TX_STALL); + } + else + { + /* OUT endpoint */ + _SetEPRxStatus(Related_Endpoint, EP_RX_STALL); + } + } + return USB_SUCCESS; +} /*Standard_SetEndPointFeature */ + + +/******************************************************************************* +* Function Name : Standard_SetDeviceFeature +* Description : Set or enable a specific feature of Device +* Input : None +* Output : None +* Return : USB_SUCCESS +*******************************************************************************/ +RESULT Standard_SetDeviceFeature(void) +{ + SetBit(pInformation->Current_Feature, 5); + return USB_SUCCESS; + +} /*Standard_SetDeviceFeature */ + +/******************************************************************************* +* Function Name : Standard_GetStringDescriptor +* Description : GetStringDescriptor +* Input : +* Output : None +* Return : Pointer +*******************************************************************************/ + +BYTE *Standard_GetStringDescriptor(WORD Length, ONE_DESCRIPTOR *pDesc) +{ + int len, offset, wOffset; + wOffset = pInformation->Ctrl_Info.Usb_wOffset; + if (Length == 0) + { + offset = 0; + do + { + len = (int)*(pDesc->Descriptor + offset); + if (wOffset >= 0 && wOffset < len) + { + len -= wOffset; + if (len > 0) + return (BYTE*)len; + break; + } + wOffset -= len; + offset += len; + } + while (offset < pDesc->Descriptor_Size); + return 0; + } + return pDesc->Descriptor + wOffset; +}/* Standard_GetStringDescriptor */ + +/******************************************************************************* +* Function Name : Standard_GetDescriptorData +* Description : GetDescriptorData +* Input : +* Output : None +* Return : Return pointer on string descriptor if length is not 0 +* Return string descriptor length if length is 0 +*******************************************************************************/ + +BYTE *Standard_GetDescriptorData(WORD Length, ONE_DESCRIPTOR *pDesc) +{ + int len, wOffset; + wOffset = pInformation->Ctrl_Info.Usb_wOffset; + if (Length == 0) + { + len = pDesc->Descriptor_Size - wOffset; + if (len <= 0) + return 0; + return (BYTE *)len; + } + return pDesc->Descriptor + wOffset; +} /* Standard_GetDescriptorData */ + +/******************************************************************************* +* Function Name : DataStageOut +* Description : Data OUT stage of a control transfer +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DataStageOut() +{ + ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info; + WORD save_rLength; + save_rLength = pEPinfo->Usb_rLength; + if (pEPinfo->CopyData && save_rLength) + { + BYTE *Buffer; + WORD Length; + WORD wBuffer; + WORD *Source; + Length = pEPinfo->PacketSize; + if (Length > save_rLength) + Length = save_rLength; + Buffer = (*pEPinfo->CopyData)(Length); + pEPinfo->Usb_rLength -= Length; + pEPinfo->Usb_rOffset += Length; + Source = (WORD*)(PMAAddr + GetEPRxAddr(ENDP0)); + while (Length) + { + wBuffer = *Source; + Source++; + *Buffer = wBuffer&0x00FF; + *(Buffer+1) = ((wBuffer&0xFF00)>>8); + Buffer++; + Buffer++; + Length--; + if(Length == 0) break; /* odd counter */ + Length--; + } + } + if(pEPinfo->Usb_rLength !=0) + { + vSetEPRxStatus(EP_RX_VALID);/* reenable for next data reception */ + SetEPTxCount(ENDP0, 0); + vSetEPTxStatus(EP_TX_VALID);/* Expect the host to abort the data OUT stage */ + } + /* Set the next State*/ + if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize) + pInformation->ControlState = OUT_DATA; + else + { + if (pEPinfo->Usb_rLength >0) + pInformation->ControlState = LAST_OUT_DATA; + else if (pEPinfo->Usb_rLength == 0) + { + pInformation->ControlState = WAIT_STATUS_IN; + USB_StatusIn(); + } + } +} /* DataStageOut */ + +/******************************************************************************* +* Function Name : DataStageIn +* Description : Data IN stage of a Control Transfer +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DataStageIn(void) +{ + ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info; + WORD save_wLength = pEPinfo->Usb_wLength; + BYTE ControlState; + BYTE *DataBuffer; + WORD Length; + DWORD tmp; + int i; + DWORD *pTxBuff; + + + + if (save_wLength == 0) + { + /* no more data to send so STALL the TX Status*/ + ControlState = WAIT_STATUS_OUT; + vSetEPTxStatus(EP_TX_STALL); + goto Expect_Status_Out; + } + Length = pEPinfo->PacketSize; + ControlState = (save_wLength < Length) ? LAST_IN_DATA : IN_DATA; + + /* Same as UsbWrite */ + if (Length > save_wLength) + Length = save_wLength; + DataBuffer = (*pEPinfo->CopyData)(Length); + /* transfer data from buffer to PMA */ + pTxBuff = (DWORD *)(PMAAddr + GetEPTxAddr(ENDP0)); + for(i=0;i < Length;) + { + tmp = *DataBuffer; + tmp|=*(DataBuffer+1)<<8; + tmp|=*(DataBuffer+2)<<16; + tmp|=*(DataBuffer+3)<<24; + DataBuffer = DataBuffer+4; + i=i+4; + *pTxBuff=tmp; + pTxBuff++; + } + SetEPTxCount(ENDP0, Length); + pEPinfo->Usb_wLength -= Length; + pEPinfo->Usb_wOffset += Length; + vSetEPTxStatus(EP_TX_VALID); + USB_StatusOut();/* Expect the host to abort the data IN stage */ + +Expect_Status_Out: pInformation->ControlState = ControlState; + +}/* DataStageIn */ + +/******************************************************************************* +* Function Name : NoData_Setup0 +* Description : Proceed the processing of setup request without data stage +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NoData_Setup0() +{ + DEVICE_INFO *pInfo = pInformation; + RESULT Result; + BYTE RequestNo = pInformation->USBbRequest; + BYTE ControlState; + + /*Standard Device Requests*/ + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + /*SET_CONFIGURATION*/ + if (RequestNo == SET_CONFIGURATION) + Result = Standard_SetConfiguration(); + + /*SET ADDRESS*/ + else if (RequestNo == SET_ADDRESS) + { + if(pInfo->USBwValue0 > 127 || pInfo->USBwValue1!=0 + ||pInfo->USBwIndex!=0 || pInfo->Current_Configuration!=0) + { + ControlState = STALLED; + goto exit_NoData_Setup0; + } + else Result = USB_SUCCESS; + } + + /*SET FEATURE*/ + else if (RequestNo == SET_FEATURE) + { + if (pInfo->USBwValue0==DEVICE_REMOTE_WAKEUP && pInfo->USBwIndex==0 + && ValBit(pInfo->Current_Feature,5)) + Result = Standard_SetDeviceFeature(); + else + Result = UNSUPPORT; + } + + /*Clear FEATURE */ + else if (RequestNo == CLEAR_FEATURE) + { + if (pInfo->USBwValue0==DEVICE_REMOTE_WAKEUP && pInfo->USBwIndex==0 + &&ValBit(pInfo->Current_Feature,5)) + Result = Standard_ClearFeature(); + else + Result = UNSUPPORT; + } + } + + /*Standard Interface Requests*/ + else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) + { + /*SET INTERFACE*/ + if (RequestNo == SET_INTERFACE) + Result = Standard_SetInterface(); + } + + /*Standard EndPoint Requests*/ + else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { + /*CLEAR FEATURE for EndPoint*/ + if (RequestNo == CLEAR_FEATURE) + Result = Standard_ClearFeature(); + + /*SET FEATURE for EndPoint*/ + else if (RequestNo == SET_FEATURE) + { + Result = Standard_SetEndPointFeature(); + } + } + + else Result = UNSUPPORT; + if (Result != USB_SUCCESS) + { + /*Check and Process possible Class_NoData_Setup Requests*/ + Result = (*pProperty->Class_NoData_Setup)(RequestNo); + if (Result == NOT_READY) + { + ControlState = PAUSE; + goto exit_NoData_Setup0; + } + } + if (Result != USB_SUCCESS) + { + ControlState = STALLED; + goto exit_NoData_Setup0; + } + ControlState = WAIT_STATUS_IN; /* After no data stage SETUP */ + USB_StatusIn(); + +exit_NoData_Setup0: + pInfo->ControlState = ControlState; + return; +} /* NoData_Setup0 */ + +/******************************************************************************* +* Function Name : Data_Setup0 +* Description : Processing Setup Requests with data stage +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Data_Setup0() +{ + DEVICE_INFO *pInfo = pInformation; + DEVICE_PROP *pProp = pProperty; + BYTE *(*CopyRoutine)(WORD); + RESULT Result; + BYTE Request_No = pInfo->USBbRequest; + BYTE *pbLen; + BYTE Related_Endpoint,Reserved; + WORD wOffset,wLen,Status; + + CopyRoutine = NULL; + wOffset = 0; + + /*GET_DESCRIPTOR*/ + if (Request_No == GET_DESCRIPTOR) + { + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)) + { + BYTE wValue1 = pInfo->USBwValue1; + if (wValue1 == DEVICE_DESCRIPTOR) + CopyRoutine = pProp->GetDeviceDescriptor; + else if (wValue1 == CONFIG_DESCRIPTOR) + CopyRoutine = pProp->GetConfigDescriptor; + else if (wValue1 == STRING_DESCRIPTOR) + { + wOffset = pInfo->USBwValue0; + CopyRoutine = pProp->GetStringDescriptor; + } + } + } + + /*GET STATUS*/ + else if (Request_No == GET_STATUS && pInfo->USBwValue==0 + && pInfo->USBwLength == 0x0002 && pInfo->USBwIndex1==0) + { + /* GET STATUS for Device*/ + if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT) && pInfo->USBwIndex==0) + { + CopyRoutine = Standard_GetStatus; + } + + /* GET STATUS for Interface*/ + else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT)) + { + if ((*pProp->Class_Get_Interface_Setting)(pInfo->USBwIndex0,0)==USB_SUCCESS + && pInfo->Current_Configuration!=0) + CopyRoutine = Standard_GetStatus; + } + + /* GET STATUS for EndPoint*/ + else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT)) + { + Related_Endpoint = (pInfo->USBwIndex0 & 0x0f); + Reserved= pInfo->USBwIndex0 & 0x70; + if (ValBit(pInfo->USBwIndex0, 7)) + Status =_GetEPTxStatus(Related_Endpoint); + else Status =_GetEPRxStatus(Related_Endpoint); + if(Related_Endpoint < Device_Table.Total_Endpoint && Reserved==0 && Status != 0) + CopyRoutine = Standard_GetStatus; + } + } + + /*GET CONFIGURATION*/ + else if (Request_No == GET_CONFIGURATION) + { + if ( Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT) ) + CopyRoutine = Standard_GetConfiguration; + } + + /*GET INTERFACE*/ + else if (Request_No == GET_INTERFACE) + { + if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT) + && pInfo->Current_Configuration!=0 && pInfo->USBwValue==0 + && pInfo->USBwIndex1==0 && pInfo->USBwLength == 0x0001 + && (*pProperty->Class_Get_Interface_Setting)(pInfo->USBwIndex0,0)==USB_SUCCESS) + CopyRoutine = Standard_GetInterface; + } + + if (CopyRoutine) + { + pInfo->Ctrl_Info.Usb_wOffset = wOffset; + pInfo->Ctrl_Info.CopyData = CopyRoutine; + pbLen = (*CopyRoutine)(0); + wLen = (WORD)((DWORD)pbLen); + pInfo->Ctrl_Info.Usb_wLength = wLen; + Result = USB_SUCCESS; + } + else + { + /*check and process possible Class_Data_Setup request*/ + Result = (*pProp->Class_Data_Setup)(pInfo->USBbRequest); + if(Result == NOT_READY) + { + pInfo->ControlState = PAUSE; + return; + } + } + if (pInfo->Ctrl_Info.Usb_wLength == 255) + { + /* Data is not ready, wait it */ + pInfo->ControlState = PAUSE; + return; + } + if (Result == UNSUPPORT || pInfo->Ctrl_Info.Usb_wLength == 0) + { + /* Unsupported request */ + pInfo->ControlState = STALLED; + return; + } + if (ValBit(pInfo->USBbmRequestType, 7)) + { + /* Device ==> Host */ + WORD wLength = pInfo->USBwLength; + /* Restrict the data length to be the one host asks */ + if (pInfo->Ctrl_Info.Usb_wLength > wLength) + pInfo->Ctrl_Info.Usb_wLength = wLength; + pInfo->Ctrl_Info.PacketSize = pProp->MaxPacketSize; + DataStageIn(); + } + else + { + pInfo->ControlState = OUT_DATA; + vSetEPRxStatus(EP_RX_VALID);/* enable for next data reception */ + } + return; +} /* Data_Setup0 */ + +/******************************************************************************* +* Function Name : Setup0_Process +* Description : Setup Token processing (entry point) +* Input : None +* Output : None +* Return : (see Post0_Process) +*******************************************************************************/ +BYTE Setup0_Process() +{ + DEVICE_INFO *pInfo = pInformation; + WORD* pBuf; + + pBuf= (WORD *)(GetEPRxAddr(ENDP0)+PMAAddr); + if (pInfo->ControlState != PAUSE) + { + pInfo->USBbmRequestType = (*pBuf)&0xFF; /* bmRequestType */ + pInfo->USBbRequest = ((*pBuf)&0xFF00)>>8; /* bRequest */ + pInfo->USBwValue = ByteSwap(*(pBuf+1)); /* wValue */ + pInfo->USBwIndex = ByteSwap(*(pBuf+2)); /* wIndex */ + pInfo->USBwLength = *(pBuf+3); /* wLength */ + } + pInfo->ControlState = SETTING_UP; + if (pInfo->USBwLength == 0) + { + /* Setup with no data stage */ + NoData_Setup0(); + } + else + { + /* Setup with data stage */ + Data_Setup0(); + } + return Post0_Process(); +} /* Setup0_Process */ + +/******************************************************************************* +* Function Name : In0_Process +* Description : Process the IN tocken on control endpoint +* Input : None +* Output : None +* Return : (see Post0_Process) +*******************************************************************************/ +BYTE In0_Process() +{ + DEVICE_INFO *pInfo = pInformation; + BYTE ControlState = pInfo->ControlState; + if (ControlState == IN_DATA || ControlState == LAST_IN_DATA) + { + DataStageIn(); + ControlState = pInfo->ControlState; + } + else if (ControlState == WAIT_STATUS_IN) + { + if (pInfo->USBbRequest == SET_ADDRESS && + Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT) ) + { + SetDeviceAddress(pInfo->USBwValue0); + } + (*pProperty->Process_Status_IN)(); + ControlState = STALLED; + } + else + ControlState = STALLED; + pInfo->ControlState = ControlState; + return Post0_Process(); +} /* In0_Process */ + +/******************************************************************************* +* Function Name : Out0_Process +* Description : Process the OUT token on control endpoint +* Input : None +* Output : None +* Return : (see Post0_Process) +*******************************************************************************/ +BYTE Out0_Process() +{ + DEVICE_INFO *pInfo = pInformation; + BYTE ControlState = pInfo->ControlState; + if(ControlState == OUT_DATA || ControlState == LAST_OUT_DATA) + DataStageOut(); + else if (ControlState == WAIT_STATUS_OUT) + { + (*pProperty->Process_Status_OUT)(); + ControlState = STALLED; + } + else if (ControlState == IN_DATA || ControlState == LAST_IN_DATA) + { + /* host aborts the transfer before finish */ + ControlState = STALLED; + } + /* Unexpect state, STALL the endpoint */ + else + { + ControlState = STALLED; + } + pInfo->ControlState = ControlState; + return Post0_Process(); +} /* Out0_Process */ + +/******************************************************************************* +* Function Name : Post0_Process +* Description : Stalls ENDPOINT0 if ControlState = STALLED +* Input : None +* Output : None +* Return : 0: if ControlState is not " PAUSE " +* 1: if ControlState is "PAUSE" +*******************************************************************************/ +BYTE Post0_Process() +{ + _SetEPRxCount(ENDP0, STD_MAXPACKETSIZE); + if (pInformation->ControlState == STALLED) + { + vSetEPRxStatus(EP_RX_STALL); + vSetEPTxStatus(EP_TX_STALL); + } + return (pInformation->ControlState == PAUSE); +} /* Post0_Process */ + + +/******************************************************************************* +* Function Name : SetDeviceAddress +* Description : Set Device Address +* Input : Val: Device Address +* Output : None +* Return : None +*******************************************************************************/ +void SetDeviceAddress(BYTE Val) +{ + int i; + DEVICE *pDevice = &Device_Table; + /* BYTE EP0 = pDevice->EP0; */ + int nEP = pDevice->Total_Endpoint; + /* set address in every used endpoint */ + for(i=0;iControlState = 2; + pProperty = &Device_Property; + /* Initialize devices one by one */ + pProperty->Init(); + +} /* USB_Init() */ + +/*==========================================================================*/ diff --git a/uc_str912/prj_blinky_complex_startup/src/usb_int.c b/uc_str912/prj_blinky_complex_startup/src/usb_int.c new file mode 100644 index 0000000..28c956b --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/usb_int.c @@ -0,0 +1,95 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_int.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Endpoint CTR interrupt service routine +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#include "USB_lib.h" +extern void (*pEpInt[9])(void); + +void CTR_ISR() +{ + WORD wEPVal; + /* stay in loop while pending ints */ + while(((wIstr = _GetISTR()) & ISTR_CTR)!= 0) + { + _SetISTR((WORD)CLR_CTR); /* clear CTR flag */ + /* extract highest priority endpoint number */ + EPindex = (BYTE)(wIstr & ISTR_EP_ID); + if(EPindex == 0) /* Decode and service control endpoint interrupt */ + { + /* save RX & TX status */ + /* and set both to NAK */ + SaveRState = _GetEPRxStatus(ENDP0); + SaveTState = _GetEPTxStatus(ENDP0); + _SetEPRxStatus(ENDP0, EP_RX_NAK); + _SetEPTxStatus(ENDP0, EP_TX_NAK); + if((wIstr & ISTR_DIR) == 0) + { + /* DIR = 0 => IN int */ + _ClearEP_CTR_TX(ENDP0); + In0_Process(); + /* check if SETUP arrived during IN processing */ + wEPVal = _GetENDPOINT(ENDP0); + if((wEPVal & (EP_CTR_RX|EP_SETUP)) != 0) + { + _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */ + Setup0_Process(); + } + } + else + { + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + wEPVal = _GetENDPOINT(ENDP0); + if((wEPVal & EP_CTR_TX) != 0) + { + _ClearEP_CTR_TX(ENDP0); + In0_Process(); + } + if((wEPVal &EP_SETUP) != 0) + { + _ClearEP_CTR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */ + Setup0_Process(); + } + else if((wEPVal & EP_CTR_RX) != 0) + { + _ClearEP_CTR_RX(ENDP0); + Out0_Process(); + } + } + /* before terminate set Tx & Rx status */ + _SetEPRxStatus(ENDP0, SaveRState); + _SetEPTxStatus(ENDP0, SaveTState); + } + else /* Decode and service non control endpoints interrupt */ + { + /* process related endpoint register */ + wEPVal = _GetENDPOINT(EPindex); + if((wEPVal & EP_CTR_RX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_RX(EPindex); + } + if((wEPVal & EP_CTR_TX) != 0) + { + /* clear int flag */ + _ClearEP_CTR_TX(EPindex); + } + /* call service function */ + (*pEpInt[EPindex-1])(); + } + } +} /* CTR_ISR */ + diff --git a/uc_str912/prj_blinky_complex_startup/src/usb_mem.c b/uc_str912/prj_blinky_complex_startup/src/usb_mem.c new file mode 100644 index 0000000..5bb2bda --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/usb_mem.c @@ -0,0 +1,85 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_mem.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : utility functions for memory transfers +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#include "usb_lib.h" +#include "usb_mem.h" + +/******************************************************************************* +* Function Name : UserToPMABufferCopy +* Description : Copy a buffer from user memory to packet memory area +* Input : - pbUsrBuf = pointer to user memory area +* - wPMABufAddr = address into PMA +* - wNBytes = number of bytes to be copied +* Output : None +* Return value : None +*******************************************************************************/ +void UserToPMABufferCopy(BYTE *pbUsrBuf,WORD wPMABufAddr, WORD wNBytes) +{ + DWORD *pdwVal; + + DWORD wTra, i; + union + { + BYTE *bTra; + DWORD *wTra; + }pBuf; + int wNTrasf=wNBytes; + + pdwVal= (DWORD *)(PMAAddr+(DWORD)((wPMABufAddr))); + pBuf.wTra = &wTra; + for(i=0;i < wNTrasf;) + { + *(pBuf.bTra ) = *pbUsrBuf++; + i++; + *(pBuf.bTra+1) = *pbUsrBuf++; + i++; + *(pBuf.bTra+2) = *pbUsrBuf++; + i++; + *(pBuf.bTra+3) = *pbUsrBuf++; + i++; + *pdwVal = wTra; + pdwVal++; + } +} /* UserToPMABufferCopy */ + +/******************************************************************************* +* Function Name : PMAToUserBufferCopy +* Description : Copy a buffer from packet memory area to user memory +* Input : - pbUsrBuf = pointer to user memory area +* - wPMABufAddr = address into PMA +* - wNBytes = number of bytes to be copied +* Output : None +* Return value : None +*******************************************************************************/ +void PMAToUserBufferCopy(BYTE *pbUsrBuf,WORD wPMABufAddr, WORD wNBytes) +{ + BYTE *pbVal; + WORD wNTrasf=wNBytes; + if((wNBytes) == 0) return; + pbVal = (BYTE *)(PMAAddr + wPMABufAddr); + while(1) + { + *pbUsrBuf++ = *pbVal++; + if((--wNTrasf) == 0) return; + *pbUsrBuf++ = *pbVal++; + if((--wNTrasf) == 0) return; + }/* while */ +} /* PMAToUserBufferCopy */ + + + diff --git a/uc_str912/prj_blinky_complex_startup/src/usb_regs.c b/uc_str912/prj_blinky_complex_startup/src/usb_regs.c new file mode 100644 index 0000000..0555753 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/src/usb_regs.c @@ -0,0 +1,1000 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : usb_regs.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Interface functions to USB cell registers +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#include "USB_lib.h" + +/******************************************************************************* +* Function Name : SetCNTR +* Description : Sets the CNTR (Control Register) +* Input : wRegValue = register value +* Output : None +* Return : None +*******************************************************************************/ +void SetCNTR(WORD wRegValue) +{ + _SetCNTR(wRegValue); +} + +/******************************************************************************* +* Function Name : GetCNTR +* Description : Gets the CNTR +* Input : None +* Output : None +* Return : CNTR value +*******************************************************************************/ +WORD GetCNTR(void) +{ + return(_GetCNTR()); +} + +/******************************************************************************* +* Function Name : SetISTR +* Description : Sets the ISTR +* Input : wRegValue = register value +* Output : None +* Return : None +*******************************************************************************/ +void SetISTR(WORD wRegValue) +{ + _SetISTR(wRegValue); +} + +/******************************************************************************* +* Function Name : GetISTR +* Description : Gets the ISTR (Interrupt Status Register) +* Input : None +* Output : None +* Return : ISTR register value +*******************************************************************************/ +WORD GetISTR(void) +{ + return(_GetISTR()); +} + +/******************************************************************************* +* Function Name : GetFNR +* Description : Gets the FNR (Frame Number Register) +* Input : None +* Output : None +* Return : FNR regiter value +*******************************************************************************/ +WORD GetFNR(void) +{ + return(_GetFNR()); +} + +/******************************************************************************* +* Function Name : SetDADDR +* Description : Sets the DADDR (Device Address Register) +* Input : wRegValue = register value +* Output : None +* Return : None +*******************************************************************************/ +void SetDADDR(WORD wRegValue) +{ + _SetDADDR(wRegValue); +} + +/******************************************************************************* +* Function Name : GetDADDR +* Description : Gets the DADDR (Device Address Register) +* Input : None +* Output : None +* Return : DADDR register value +*******************************************************************************/ +WORD GetDADDR(void) +{ + return(_GetDADDR()); +} + +/******************************************************************************* +* Function Name : SetBTABLE +* Description : Sets the BTABLE (Buffer Table Register) +* Input : BTABLE value +* Output : None +* Return : None +*******************************************************************************/ +void SetBTABLE(WORD wRegValue) +{ + _SetBTABLE(wRegValue); +} + +/******************************************************************************* +* Function Name : GetBTABLE +* Description : Gets the BTABLE (Buffer Table Register) +* Input : None +* Output : None +* Return : BTABLE value +*******************************************************************************/ +WORD GetBTABLE(void) +{ + return(_GetBTABLE()); +} + +/******************************************************************************* +* Function Name : SetENDPOINT +* Description : Sets the Endpoint Register +* Input : bEpNum = endpoint Number[0:9], wRegValue= register value +* Output : None +* Return : None +*******************************************************************************/ +void SetENDPOINT(BYTE bEpNum, WORD wRegValue) +{ + _SetENDPOINT(bEpNum,wRegValue); +} + +/******************************************************************************* +* Function Name : GetENDPOINT +* Description : Gets the Endpoint Register value +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : Endpoint register value +*******************************************************************************/ +WORD GetENDPOINT(BYTE bEpNum) +{ + return(_GetENDPOINT(bEpNum)); +} + +/******************************************************************************* +* Function Name : SetEPtype +* Description : Sets the Endpoint Type +* Input : - bEpNum = endpoint number[0:9] +* - wType = endpint type: EP_BULK,EP_CONTROL,EP_ISOCHRONOUS +* EP_INTERRUPT +* Output : None +* Return : None +*******************************************************************************/ +void SetEPType(BYTE bEpNum, WORD wType) +{ + _SetEPType(bEpNum, wType); +} + +/******************************************************************************* +* Function Name : GetEPtype +* Description : Gets the Endpoint type +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : Endpoint type: EP_BULK,EP_CONTROL,EP_ISOCHRONOUS +* EP_INTERRUPT +*******************************************************************************/ +WORD GetEPType(BYTE bEpNum) +{ + return(_GetEPType(bEpNum)); +} + +/******************************************************************************* +* Function Name : SetEPTxStatus +* Description : Sets the endpoint Tx status +* Input : - bEpNum = endpoint number[0:9] +* - wState = Tx status: EP_TX_DIS,EP_TX_STALL,EP_TX_NAK,EP_TX_VALID +* Output : None +* Return : None +*******************************************************************************/ +void SetEPTxStatus(BYTE bEpNum, WORD wState) +{ + _SetEPTxStatus(bEpNum,wState); +} + +/******************************************************************************* +* Function Name : SetEPRxStatus +* Description : Sets the endpoint Rx status +* Input : - bEpNum = endpoint number[0:9] +* - wState = Rx status: EP_RX_DIS,EP_RX_STALL,EP_RX_NAK,EP_RX_VALID +* Output : None +* Return : None +*******************************************************************************/ +void SetEPRxStatus(BYTE bEpNum, WORD wState) +{ + _SetEPRxStatus(bEpNum,wState); +} + +/******************************************************************************* +* Function Name : GetEPTxStatus +* Description : Gets the endpoint Tx Status +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : Enpointx Tx Status: EP_TX_DIS,EP_TX_STALL,EP_TX_NAK,EP_TX_VALID +*******************************************************************************/ +WORD GetEPTxStatus(BYTE bEpNum) +{ + return(_GetEPTxStatus(bEpNum)); +} + +/******************************************************************************* +* Function Name : GetEPRxStatus +* Description : Gets the endpoint Rx Status +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : Enpointx Rx Status: EP_RX_DIS,EP_RX_STALL,EP_RX_NAK,EP_RX_VALID +*******************************************************************************/ +WORD GetEPRxStatus(BYTE bEpNum) +{ + return(_GetEPRxStatus(bEpNum)); +} + +/******************************************************************************* +* Function Name : SetEPTxValid +* Description : Sets the Endpoint Tx Status as valid +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void SetEPTxValid(BYTE bEpNum) +{ + _SetEPTxStatus(bEpNum, EP_TX_VALID); +} + +/******************************************************************************* +* Function Name : SetEPRxStatus +* Description : Sets the Endpoint Rx Status as valid +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void SetEPRxValid(BYTE bEpNum) +{ + _SetEPRxStatus(bEpNum, EP_RX_VALID); +} + +/******************************************************************************* +* Function Name : SetEP_KIND +* Description : Sets the Endpoint EP_KIND bit +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void SetEP_KIND(BYTE bEpNum) +{ + _SetEP_KIND(bEpNum); +} + +/******************************************************************************* +* Function Name : ClearEP_KIND +* Description : Clears the Endpoint EP_KIND bit +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void ClearEP_KIND(BYTE bEpNum) +{ + _ClearEP_KIND(bEpNum); +} + +/******************************************************************************* +* Function Name : Clear_Status_Out +* Description : Clears the Status_Out bit (= EP_KIND bit) +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void Clear_Status_Out(BYTE bEpNum) +{ + _ClearEP_KIND(bEpNum); +} + +/******************************************************************************* +* Function Name : Set_Status_Out +* Description : Sets the Status_Out bit (=EP_KIND bit) +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void Set_Status_Out(BYTE bEpNum) +{ + _SetEP_KIND(bEpNum); +} + +/******************************************************************************* +* Function Name : SetEPDoubleBuff +* Description : Sets the DBL_BUF bit (=EP_KIND bit) +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void SetEPDoubleBuff(BYTE bEpNum) +{ + _SetEP_KIND(bEpNum); +} + +/******************************************************************************* +* Function Name : ClearEPDoubleBuff +* Description : Clears the DBL_BUF bit (=EP_KIND bit) +* Input : bEpNum = endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void ClearEPDoubleBuff(BYTE bEpNum) +{ + _ClearEP_KIND(bEpNum); +} + +/******************************************************************************* +* Function Name : GetTxStallStatus +* Description : checks if endpoint Tx status== STALL +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : TRUE or FALSE +*******************************************************************************/ +BOOL GetTxStallStatus(BYTE bEpNum) +{ + return(_GetTxStallStatus(bEpNum)); +} + +/******************************************************************************* +* Function Name : GetRxStallStatus +* Description : checks if endpoint Rx status ==STALL +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : TRUE or FALSE +*******************************************************************************/ +BOOL GetRxStallStatus(BYTE bEpNum) +{ + return(_GetRxStallStatus(bEpNum)); +} + +/******************************************************************************* +* Function Name : ClearEP_CTR_RX +* Description : Clears the CTR_RX flag in endpoint +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void ClearEP_CTR_RX(BYTE bEpNum) +{ + _ClearEP_CTR_RX(bEpNum); +} + +/******************************************************************************* +* Function Name : ClearEP_CTR_Tx +* Description : Clears the CTR_Tx flag +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void ClearEP_CTR_TX(BYTE bEpNum) +{ + _ClearEP_CTR_TX(bEpNum); +} + +/******************************************************************************* +* Function Name : ToggleDTOG_RX +* Description : Toggles the DTOG_RX bit +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void ToggleDTOG_RX(BYTE bEpNum) +{ + _ToggleDTOG_RX(bEpNum); +} + +/******************************************************************************* +* Function Name : ToggleDTOG_TX +* Description : Toggles the DTOG_Tx bit +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void ToggleDTOG_TX(BYTE bEpNum) +{ + _ToggleDTOG_TX(bEpNum); +} + +/******************************************************************************* +* Function Name : ClearDTOG_RX +* Description : Clears the DTOG_RX bit +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void ClearDTOG_RX(BYTE bEpNum) +{ + _ClearDTOG_RX(bEpNum); +} + +/******************************************************************************* +* Function Name : ClearDTOG_TX +* Description : Clears the DTOG_TX bit +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void ClearDTOG_TX(BYTE bEpNum) +{ + _ClearDTOG_TX(bEpNum); +} + +/******************************************************************************* +* Function Name : SetEPAddress +* Description : Sets the Endpoint Address +* Input : -bEpNum: endpoint number[0:9] +* -bAddr : Address value +* Output : None +* Return : None +*******************************************************************************/ +void SetEPAddress(BYTE bEpNum,BYTE bAddr) +{ + _SetEPAddress(bEpNum,bAddr); +} + +/******************************************************************************* +* Function Name : GetEPAddress +* Description : Gets the Endpoint Address +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : Endpoint address value +*******************************************************************************/ +BYTE GetEPAddress(BYTE bEpNum) +{ + return(_GetEPAddress(bEpNum)); +} + +/******************************************************************************* +* Function Name : SetEPTxAddr +* Description : Sets the Endpoint Tx buffer Addr offset in the PMA +* Input : - bEpNum: endpoint number[0:9] +* - wAddr : Tx buffer address offset value in the PMA +* Output : None +* Return : None +*******************************************************************************/ +void SetEPTxAddr(BYTE bEpNum, WORD wAddr) +{ + _SetEPTxAddr(bEpNum,wAddr); +} + +/******************************************************************************* +* Function Name : SetEPRxAddr +* Description : Sets the Endpoint Rx buffer Addr in the Packet Memory Area PMA +* Input : - bEpNum: endpoint number[0:9] +* - wAddr : Rx buffer address offset value in the PMA +* Output : None +* Return : None +*******************************************************************************/ +void SetEPRxAddr(BYTE bEpNum, WORD wAddr) +{ + _SetEPRxAddr(bEpNum,wAddr); +} + +/******************************************************************************* +* Function Name : GetEPTxAddr +* Description : Gets the Endpoint Tx buffer address offset in PMA +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : Endpoint Tx buffer Address offset in PMA +*******************************************************************************/ +WORD GetEPTxAddr(BYTE bEpNum) +{ + return (_GetEPTxAddr(bEpNum)); +} + +/******************************************************************************* +* Function Name : GetEPRxAddr +* Description : Gets the Endpoint Rx buffer address offset in the PMA +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : Endpoint Rx buffer Address offset in PMA +*******************************************************************************/ +WORD GetEPRxAddr(BYTE bEpNum) +{ + return(_GetEPRxAddr(bEpNum)); +} + +/******************************************************************************* +* Function Name : SetEPTxCount +* Description : Sets the Endpoint Tx buffer size +* Input : - bEpNum: endpoint number[0:9] +* - wCount: size (in bytes) of the Tx buffer in the PMA +* Output : None +* Return : None +*******************************************************************************/ +void SetEPTxCount(BYTE bEpNum, WORD wCount) +{ + _SetEPTxCount(bEpNum,wCount); +} + +/******************************************************************************* +* Function Name : SetEPRxCount +* Description : Sets the Endpoint Rx buffer size +* Input : - bEpNum: endpoint number[0:9] +* - wCount : size (in bytes) of the Rx buffer in the PMA +* Output : None +* Return : None +*******************************************************************************/ +void SetEPRxCount(BYTE bEpNum, WORD wCount) +{ + _SetEPRxCount(bEpNum,wCount); +} +/******************************************************************************* +* Function Name : GetEPTxCount +* Description : Gets the Endpoint count value +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : Endpoint TxCount value +*******************************************************************************/ + +WORD GetEPTxCount(BYTE bEpNum) +{ + return(_GetEPTxCount(bEpNum)); +} + +/******************************************************************************* +* Function Name : GetEPRxCount +* Description : Gets the Endpoint Count register value +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : Endpoint Rx Count value +*******************************************************************************/ +WORD GetEPRxCount(BYTE bEpNum) +{ + return(_GetEPRxCount(bEpNum)); +} + +/******************************************************************************* +* Function Name : SetEPDblBuffAddr +* Description : Set double buffer buffer0, buffer1 addresses in the PMA +* Input : - bEpNum: endpoint number[0:9] +* - wBuf0Addr : buffer0 Address offset in PMA +* - wBuf1Addr : buffer1 Address offset in PMA +* Output : None +* Return : None +*******************************************************************************/ +void SetEPDblBuffAddr(BYTE bEpNum, WORD wBuf0Addr, WORD wBuf1Addr) +{ + _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr); +} + +/******************************************************************************* +* Function Name : SetEPDBlBuf0Addr +* Description : Set buffer0 address in PMA +* Input : -bEpNum: endpoint number[0:9] +* -wBuf0Addr: buffer0 Address offset in PMA +* Output : None +* Return : None +*******************************************************************************/ +void SetEPDblBuf0Addr(BYTE bEpNum,WORD wBuf0Addr) +{ + _SetEPDblBuf0Addr(bEpNum, wBuf0Addr); +} +/******************************************************************************* +* Function Name : SetEPDBlBuf1Addr +* Description : Set buffer1 address in PMA +* Input : -bEpNum: endpoint number[0:9] +* -wBuf1Addr: buffer1 Address offset in PMA +* Output : None +* Return : None +*******************************************************************************/ +void SetEPDblBuf1Addr(BYTE bEpNum,WORD wBuf1Addr) +{ + _SetEPDblBuf1Addr(bEpNum, wBuf1Addr); +} + +/******************************************************************************* +* Function Name : GetEPDblBuf0Addr +* Description : Gets buffer0 address +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : Buffer 0 Address offset in PMA +*******************************************************************************/ +WORD GetEPDblBuf0Addr(BYTE bEpNum) +{ + return(_GetEPDblBuf0Addr(bEpNum)); +} + +/******************************************************************************* +* Function Name : GetEPDblbuf1Addr +* Description : Gets buffer1 address +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : Buffer 1 Address offset in PMA +*******************************************************************************/ +WORD GetEPDblBuf1Addr(BYTE bEpNum) +{ + return(_GetEPDblBuf1Addr(bEpNum)); +} +/******************************************************************************* +* Function Name : SetEPDblBuf1Count +* Description : Set buffer1 size +* Input : - bEpNum: endpoint number[0:9] +* - bDir: buffer direction : EP_DBUF_OUT or EP_DBUF_IN +* - wCount: bytes count value +* Output : None +* Return : None +*******************************************************************************/ +void SetEPDblBuf1Count(BYTE bEpNum, BYTE bDir,WORD wCount) +{ + if(bDir == EP_DBUF_IN) + /* IN double buffered endpoint */ + { + *_pEPBufCount(bEpNum)&= 0x000FFFF; + *_pEPBufCount(bEpNum)|=(wCount<<16); + } + else if(bDir == EP_DBUF_OUT) + /* OUT double buffered endpoint */ + _SetEPRxCount(bEpNum, wCount); +} + + +/******************************************************************************* +* Function Name : SetEPDblBuf0Count +* Description : Set buffer0 size +* Input : - bEpNum: endpoint number[0:9] +* - bDir: buffer direction : EP_DBUF_OUT or EP_DBUF_IN +* - wCount: bytes count value +* Output : None +* Return : None +*******************************************************************************/ +void SetEPDblBuf0Count(BYTE bEpNum, BYTE bDir,WORD wCount) +{ +DWORD BLsize=0; +DWORD Blocks; +if(bDir == EP_DBUF_IN) +/* IN double bufferd endpoint */ +SetEPTxCount(bEpNum,wCount); +else if(bDir == EP_DBUF_OUT) { +/* OUT double bufferd endpoint */ + + if (wCount < 64) Blocks = wCount>>1; + else + { + BLsize = 0x8000; + Blocks = wCount>>6; + } + *_pEPBufCount(bEpNum) &=~0x8000; + *_pEPBufCount(bEpNum) |=BLsize; + *_pEPBufCount(bEpNum) &=~0x7C00; + *_pEPBufCount(bEpNum) |=Blocks<<10; + *_pEPBufCount(bEpNum) &=0xFFFFFC00; + } +} + +/******************************************************************************* +* Function Name : SetEPDblBuffCount +* Description : Set buffer0 or 1 size +* Input : - bEpNum: endpoint number[0:9] + - bDir: buffer direction : EP_DBUF_OUT, EP_DBUF_IN + - wCount: bytes count value +* Output : None +* Return : None +*******************************************************************************/ +void SetEPDblBuffCount(BYTE bEpNum, BYTE bDir, WORD wCount) +{ + SetEPDblBuf0Count(bEpNum, bDir,wCount); + SetEPDblBuf1Count(bEpNum, bDir,wCount); +} + +/******************************************************************************* +* Function Name : GetEPDblBuf0Count +* Description : Get buffer0 bytes count +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : buffer0 bytes count +*******************************************************************************/ +WORD GetEPDblBuf0Count(BYTE bEpNum) +{ + return(_GetEPDblBuf0Count(bEpNum)); +} + +/******************************************************************************* +* Function Name : GetEPDBuf1Count +* Description : Get buffer1 bytes count +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : buffer1 bytes count +*******************************************************************************/ +WORD GetEPDblBuf1Count(BYTE bEpNum) +{ + return(_GetEPDblBuf1Count(bEpNum)); +} + +/******************************************************************************* +* Function Name : Free User buffer +* Description : Toggles the SW_Buf bit +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void FreeUserBuffer(BYTE bEpNum, BYTE bDir) +{ + if(bDir== EP_DBUF_OUT) + { /* OUT double buffered endpoint */ + _ToggleDTOG_TX(bEpNum); + } + else if(bDir == EP_DBUF_IN) + { /* IN double buffered endpoint */ + _ToggleDTOG_RX(bEpNum); + } +} + +/******************************************************************************* +* Function Name : ToWord +* Description : Puts 2 bytes into a single word +* Input : -bh : MSB byte + -bl : LSB byte +* Output : None +* Return : Word +*******************************************************************************/ +WORD ToWord(BYTE bh, BYTE bl) +{ + WORD wRet; + wRet = (WORD)bl | ((WORD)bh << 8); + return(wRet); +} + +/******************************************************************************* +* Function Name : ByteSwap +* Description : Swaps two bytes in a word +* Input : wSwW: word +* Output : None +* Return : Word swapped +*******************************************************************************/ +WORD ByteSwap(WORD wSwW) +{ + BYTE bTemp; + WORD wRet; + bTemp = (BYTE)(wSwW & 0xff); + wRet = (wSwW >> 8) | ((WORD)bTemp << 8); + return(wRet); +} + + +/* DMA Functions */ + +/******************************************************************************* +* Function Name : SetDMAburstTxSize +* Description : Configure the Burst Size for a Tx Endpoint +* Input : DestBsize: Destination Burst Size +* Output : None +* Return : None +*******************************************************************************/ +void SetDMABurstTxSize(BYTE DestBsize) +{ + *DMABSIZE &=~0xEF; + *DMABSIZE = (DestBsize<<4); +} + +/******************************************************************************* +* Function Name : SetDMABurstRxSize +* Description : Configure the Burst Size for a Rx Endpoint +* Input : SrcBsize: Source Burst +* Output : None +* Return : None +*******************************************************************************/ +void SetDMABurstRxSize(BYTE SrcBsize) +{ + *DMABSIZE &=~0x7; + *DMABSIZE = SrcBsize; +} + +/******************************************************************************* +* Function Name : DMAUnlinkedModeTxConfig +* Description : Configure a Tx Endpoint to trigger TX Unlinked DMA request +* Note : Up to three endpoints could be configured to trigger DMA + request, an index[0:2] must be associated to an endpoint +* Input : -bEpNum: endpoint number[0:9] +* -index: 0,1 or 2 +* Output : None +* Return : None +*******************************************************************************/ +void DMAUnlinkedModeTxConfig(BYTE bEpNum ,BYTE index) +{ + *DMACR2 &=~(0x0F<<(4*index)); + *DMACR2 |=bEpNum<<(4*index); +} + +/******************************************************************************* +* Function Name : DMAUnlinkedModeTxEnable +* Description : Enable a Tx endpoint to trigger Tx DMA request +* Input : -index :0,1 or 2 = index associated to endpoint in function +* "DMAUnlinkedModeTxConfig" +* Output : None +* Return : None +*******************************************************************************/ +void DMAUnlinkedModeTxEnable(BYTE index) +{ + *DMACR3 &=~0x01; /*DMA Tx linked mode disabled*/ + *DMACR2 &=~0x3000; + *DMACR2 |=(index+1)<<12; +} + +/******************************************************************************* +* Function Name : DMAUnlinkedModeTxDisable +* Description : Enable a Tx endpoint to trigger Tx DMA request +* Input : index :0,1 or 2 = index associated to endpoint in function +* "DMAUnlinkedModeTxConfig" +* Output : None +* Return : None +*******************************************************************************/ +void DMAUnlinkedModeTxDisable(BYTE index) +{ + *DMACR2 &=~0x3000; +} + +/******************************************************************************* +* Function Name : DMAUnlinkedModeRxEnable +* Description : Enable a Rx Endpoint to trigger Rx DMA +* Input : bEpNum: endpoint number[0:9] +* Output : None +* Return : None +*******************************************************************************/ +void DMAUnlinkedModeRxEnable(BYTE bEpNum) +{ + *DMACR3 &=~0x80; /*DMA Rx linked mode disabled*/ + *DMACR1 |=(0x1<>8); +} diff --git a/uc_str912/prj_blinky_complex_startup/startup912.S b/uc_str912/prj_blinky_complex_startup/startup912.S new file mode 100644 index 0000000..84cf524 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/startup912.S @@ -0,0 +1,405 @@ +#************************************************************************* +# *** STR912 Startup Code For GNU Tools (executed after Reset) *** +# +# (C) Hitex (UK) Ltd. 2006 +# +# Disclaimer: Whilst every effort has been made to ensure the correctness +# of this code, Hitex (UK) Ltd. cannot be held responsible for the consequences +# of its use. Users should therefore verify its operation before including it +# in any program. +#************************************************************************* +# +# +# --------------------------------------------- +# Include startup macros +# --------------------------------------------- + +//#include "stacks.h" + + .include "startup_generic.s" + +# +# +# System Memory definitions +# +# Internal RAM definitions + .equ RAM_Size, 0x00018000 /* 96K */ + .equ RAM_Base, 0x04000000 + +#************************************************************************* +# Control Startup Code Operation +#************************************************************************* +.equ SRAM_SETUP , 1 /* Enable setup of SRAM */ +.equ FMI_SETUP , 1 /* Enable FMI Setup */ +.equ CLOCK_SETUP , 0 /* Enable clock setup */ +.equ ETM_SETUP , 0 /* Enable ETM setup */ + +#************************************************************************* +# Hardware Definitions +#************************************************************************* + +# Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses) +.equ FMI_BASE , 0x54000000 /* FMI Base Address (non-buffered) */ +.equ FMI_BBSR_OFS , 0x00 /* Boot Bank Size Register */ +.equ FMI_NBBSR_OFS , 0x04 /* Non-boot Bank Size Register */ +.equ FMI_BBADR_OFS , 0x0C /* Boot Bank Base Address Register #!!! Documentation page 30,*/ +.equ FMI_NBBADR_OFS , 0x10 /* Non-boot Bank Base Address Register #!!! adresseses do not correspond*/ +.equ FMI_CR_OFS , 0x18 /* Control Register */ +.equ FMI_SR_OFS , 0x1C /* Status Register */ + + +.equ FMI_CR_Val , 0x00000018 /* NBBEN = 1, BBEN = 1 */ +.equ FMI_BBSR_Val , 0x00000004 +.equ FMI_BBADR_Val , 0x00000000 +.equ FMI_NBBSR_Val , 0x00000002 +.equ FMI_NBBADR_Val , 0x00080000 +#.equ FLASH_CFG_Val , 0x00001010 /* WSTATES = 3, buscfg = 1 */ +.equ FLASH_CFG_Val , 0x00000000 /* WSTATES = 0, buscfg = 0 */ +.equ FMI_SR_Val , 0x0000000B /* Clear status errors RM0006 1.10.6 */ + + +# System Control Unit (SCU) definitions +.equ SCU_BASE , 0x5C002000 /* SCU Base Address (non-buffered) */ +.equ SCU_CLKCNTR_OFS , 0x00 /* Clock Control register Offset */ +.equ SCU_PLLCONF_OFS , 0x04 /* PLL Configuration register Offset */ +.equ SCU_SYSTAT_OFS , 0x08 /* SCU status register offset */ +.equ SCU_PWRMNG , 0x0C /* Power Management register */ +.equ SCU_PCGR0_OFS , 0x14 /* Peripheral Clock Gating Register 0 Offset */ +.equ SCU_PCGR1_OFS , 0x18 /* Peripheral Clock Gating Register 1 Offset */ +.equ SCU_PRR0_OFS , 0x1C /* Peripheral reset register 0 */ +.equ SCU_PRR1_OFS , 0x1C /* Peripheral reset register 1 */ +.equ SCU_SCR0_OFS , 0x34 /* System Configuration Register 0 Offset */ + + +.equ SCU_CLKCNTR_Val , 0x00030000 /* Use PLL, external memory ratio/2 */ +.equ SCU_PLLCONF_Val , 0x000AC019 +.equ SCU_PCGR0_Val , 0x0000001B /* Setup SRAM, Prefetch Queue/Branch cache, FMI */ +.equ SCU_PCGR1_Val , 0x00C40000 /* Setup GPIO8, 9 & 4 */ +.equ SCU_PRR0_Val , 0x00001013 /* reset VIC, EMI, DMA, USB, MAC */ +.equ SCU_SCR0_Val , 0x00000196 /* Disable Prefetch Queue and Branch cache, SRAM = 96kb */ +.equ SCU_SYSSTAT_LOCK , 0x01 /* Check for PLL locked */ + +# APB Bridge 1 & 2 definitions (Peripherals) +.equ APB0_BUF_BASE , 0x48001802 /* APB Bridge 0 Buffered Base Address */ +.equ APB0_NBUF_BASE , 0x58000000 /* APB Bridge 0 Non-buffered Base Address */ +.equ APB1_BUF_BASE , 0x4C000000 /* APB Bridge 1 Buffered Base Address */ +.equ APB1_NBUF_BASE , 0x5C000000 /* APB Bridge 1 Non-buffered Base Address */ + +# ETM Definitions +.equ IOPORT2_ETM_ENABLE_BASE , 0x5C00204C +.equ IOPORT6_ETM_ENABLE_BASE , 0x5C00205C + +.equ IOPORT2_ETM_ENABLE_VAL , 0x0000FFFF +.equ IOPORT6_ETM_ENABLE_VAL , 0x0000FFFF + +#************************************************************************* +# Stack definitions +#************************************************************************* + + .equ UND_Stack_Size, 8 + .equ SVC_Stack_Size, 256 + .equ ABT_Stack_Size, 8 + .equ FIQ_Stack_Size, 32 + .equ IRQ_Stack_Size, 512 + .equ Top_Stack, RAM_Base + RAM_Size + +# NOTE: Startup Code must be linked first at Address at which it expects to run. + +#************************************************************************* +# STARTUP EXECUTABLE CODE +#************************************************************************* + + .text + .arm + .extern main + .global _startup + +_startup: + +#************************************************************************* +# Exception Vectors +#************************************************************************* +Vectors: + LDR PC, Reset_Addr /* 0x0000 */ + LDR PC, Undef_Addr /* 0x0004 */ + LDR PC, SWI_Addr /* 0x0008 */ + LDR PC, PAbt_Addr /* 0x000C */ + LDR PC, DAbt_Addr /* 0x0010 */ + NOP /* 0x0014 Reserved Vector */ + LDR PC, [PC, #-0xFF0] /* 0x0018 wraps around address space to 0xFFFFFF030. Vector from VicVECAddr */ + LDR PC, FIQ_Addr /* 0x001C FIQ has no VIC vector slot! */ + +#************************************************************************* +# Interrupt Vectors +#************************************************************************* + +Reset_Addr: .word Hard_Reset /* CPU reset vector and entry point */ +Undef_Addr: .word Undefined_Handler +SWI_Addr: .word SWI_Handler +PAbt_Addr: .word PAbt_Handler +DAbt_Addr: .word DAbt_Handler + .word 0 /* Reserved Address */ +IRQ_Addr: .word IRQ_Handler /* Does not get used due to "LDR PC, [PC, #-0xFF0]" above */ +FIQ_Addr: .word FIQ_Handler + +# Dummy Interrupt Vector Table (real service routines in INTERRUPT.C) + +Undefined_Handler: B Undefined_Handler +SWI_Handler: B SWI_Handler +PAbt_Handler: B PAbt_Handler +DAbt_Handler: B DAbt_Handler +IRQ_Handler: B IRQ_Handler /* should never get here as IRQ is via VIC slot... */ +FIQ_Handler: B FIQ_Handler + + +#************************************************************************* +# Reset Handler Entry Point +#************************************************************************* +Hard_Reset: + + StartupDelay 900000 + +after_delay: + # enable buffered mode + MRC P15, 0, R0, C1, C0, 0 + ORR R0, R0, #0x8 + MCR P15, 0, R0, C1, C0, 0 + + # workaround for flash write/read + # set bit 17 (data TCM order) + # and bit 18 (instruction TCM order) + MOV R0, #0x60000 + MCR P15, 0x1, R0, C15, C1, 0 + + + # clear enables of the VIC1_INTENCR + LDR R0, =0xfc000014 + LDR R1, =0xffffffff + STR R1, [R0, #0] + + # clear enables of the VIC0_INTENCR + LDR R0, =0xfffff014 + LDR R1, =0xffffffff + STR R1, [R0, #0] + +#************************************************************************* +# Setup SRAM Size + + .IF SRAM_SETUP == 1 + + LDR R0, =SCU_BASE + LDR R1, =SCU_SCR0_Val + STR R1, [R0, #SCU_SCR0_OFS] + + .ENDIF + +#************************************************************************* +# Setup Flash Memory Interface (FMI) + + .IF FMI_SETUP == 1 + + LDR R0, =FMI_BASE + LDR R1, =(FMI_BBADR_Val >> 2) + STR R1, [R0, #FMI_BBADR_OFS] + LDR R1, =FMI_BBSR_Val + STR R1, [R0, #FMI_BBSR_OFS] + LDR R1, =(FMI_NBBADR_Val >> 2) + STR R1, [R0, #FMI_NBBADR_OFS] + LDR R1, =FMI_NBBSR_Val + STR R1, [R0, #FMI_NBBSR_OFS] + + LDR R2, =FMI_CR_Val + STR R2, [R0, #FMI_CR_OFS] + LDR R2, =FMI_SR_Val + STR R2, [R0, #FMI_SR_OFS] + +# # Write "Write flash configuration" command (60h) +# MOV R0, R1, LSL #2 +# MOV R1, #0x60 +# STRH R1, [R0, #0] + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + # Write "Write flash configuration confirm" command (03h) +# LDR R2, =(FLASH_CFG_Val >> 2) +# ADD R0, R0, R2 +# MOV R1, #0x03 +# STRH R1, [R0, #0] + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + .ENDIF + +#************************************************************************* +# Setup Clock PLL + + .IF CLOCK_SETUP == 1 + + LDR R0, =SCU_BASE + LDR R1, =0x00020002 + STR R1, [R0, #SCU_CLKCNTR_OFS] /* Select OSC as clock src */ + + NOP /* Wait for oscillator stabilisation */ + NOP /* Must be more than 10 oscillator periods */ + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + LDR R1, =0x00000000 + STR R1, [R0, #SCU_PWRMNG] /* power management */ + + LDR R1, =0x0003C019 /* Disable PLL */ + STR R1, [R0, #SCU_PLLCONF_OFS] + LDR R1, =SCU_PLLCONF_Val + STR R1, [R0, #SCU_PLLCONF_OFS] /* Set new PLL values */ + + .IF (SCU_PLLCONF_Val & 0x8000) /* See if PLL is being used */ + + LDR R1, =SCU_SYSSTAT_LOCK +PLL_LOCK_LOOP: + LDR R2,[R0, #SCU_SYSTAT_OFS] /* Wait for PLL lock */ + ANDS R2, R2, R1 + BEQ PLL_LOCK_LOOP + + .ENDIF + + LDR R1, =SCU_PLLCONF_Val + STR R1, [R0, #SCU_PLLCONF_OFS] + LDR R1, =SCU_CLKCNTR_Val + STR R1, [R0, #SCU_CLKCNTR_OFS] + + LDR R1, =SCU_PCGR0_Val /* Enable clock gating */ + STR R1, [R0, #SCU_PCGR0_OFS] + LDR R1, =SCU_PRR0_Val + STR R1, [R0, #SCU_PRR0_OFS] + +# LDR R1, =SCU_PCGR1_Val +# STR R1, [R0, #SCU_PCGR1_OFS] + .ENDIF + + +#************************************************************************* +# Embedded Trace Module Setup +#************************************************************************* + + .IF ETM_SETUP == 1 + +# Configure IOPORT2 for ETM operation + LDR R0, =IOPORT2_ETM_ENABLE_BASE + LDR R1, =IOPORT2_ETM_ENABLE_VAL + STR R1, [R0, #0] + +# Configure IOPORT6 for ETM operation + LDR R0, =IOPORT6_ETM_ENABLE_BASE + LDR R1, =IOPORT6_ETM_ENABLE_VAL + STR R1, [R0, #0] + + .ENDIF + + +#************************************************************************* +# Compiler Runtime Environment Setup +#************************************************************************* +# Note: R13 = SP + +# Setup Stack for each mode + LDR R0, =Top_Stack + +# Set up Fast Interrupt Mode and set FIQ Mode Stack + MSR CPSR_c, #Mode_FIQ|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #FIQ_Stack_Size + +# Set up Interrupt Mode and set IRQ Mode Stack + msr CPSR_c, #Mode_IRQ|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #IRQ_Stack_Size + +# Set up Abort Mode and set Abort Mode Stack + msr CPSR_c, #Mode_ABT|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #ABT_Stack_Size + +# Set up Undefined Instruction Mode and set Undef Mode Stack + msr CPSR_c, #Mode_UND|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #UND_Stack_Size + +# Set up Supervisor Mode and set Supervisor Mode Stack + msr CPSR_c, #Mode_SVC|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #SVC_Stack_Size + +# Set up User Mode and set User Mode Stack + msr CPSR_c, #Mode_USR /* Leave interrupts enabled in user mode */ + mov r13, r0 /* Note: interrupts will not happen until VIC is enabled */ + +# Setup a default Stack Limit (when compiled with "-mapcs-stack-check") +# SUB SL, SP, #1<<10 /* 1kB */ + +# Initialise current CPU status to prevent unwanted interrupts +# msr CPSR_c, #0x000000D3 + +#************************************************************************* +# Initialise RAM For Compiler Variables +#************************************************************************* + + copy_section2 data, _efixed, _srelocate, _erelocate + +#************************************************************************* +# Clear .bss section +#************************************************************************* + + clear_section bss, _szero, _ezero + +#************************************************************************* +# Enter the C code +#************************************************************************* +# Jump to main() + +# variant for "long jump" +# ldr r0, =main +# mov lr, pc +# bx r0 + +# variant for "short jump" + B main + +# secure loop +forever: + B forever + +#************************************************************************* +# END +#************************************************************************* + .end diff --git a/uc_str912/prj_blinky_complex_startup/startup912.S_old b/uc_str912/prj_blinky_complex_startup/startup912.S_old new file mode 100644 index 0000000..91d7f88 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/startup912.S_old @@ -0,0 +1,361 @@ +#************************************************************************* +# *** STR912 Startup Code For GNU Tools (executed after Reset) *** +# +# (C) Hitex (UK) Ltd. 2006 +# +# Disclaimer: Whilst every effort has been made to ensure the correctness +# of this code, Hitex (UK) Ltd. cannot be held responsible for the consequences +# of its use. Users should therefore verify its operation before including it +# in any program. +#************************************************************************* +# +# +# --------------------------------------------- +# Include startup macros +# --------------------------------------------- + + .include "./startup_generic.S" + +# reference to external interrupt handlers +# + +# .extern SWI_Handler +# .extern PAbt_Handler +# .extern DAbt_Handler +# .extern Undefined_Handler +# .extern FIQ_Handler + +# +# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs +# + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F +# + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ +# +# +# System Memory definitions +# +# Internal RAM definitions + .equ RAM_Size, 0x00018000 /* 96K */ + .equ RAM_Base, 0x04000000 + +#************************************************************************* +# Control Startup Code Operation +#************************************************************************* +.equ SRAM_SETUP , 0 /* Enable setup of SRAM */ +.equ FMI_SETUP , 0 /* Enable FMI Setup */ +.equ CLOCK_SETUP , 1 /* Enable clock setup */ +.equ ETM_SETUP , 0 /* Enable ETM setup */ + +#************************************************************************* +# Hardware Definitions +#************************************************************************* + +# Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses) +.equ FMI_BASE , 0x54000000 /* FMI Base Address (non-buffered) */ +.equ FMI_BBSR_OFS , 0x00 /* Boot Bank Size Register */ +.equ FMI_NBBSR_OFS , 0x04 /* Non-boot Bank Size Register */ +.equ FMI_BBADR_OFS , 0x0C /* Boot Bank Base Address Register #!!! Documentation page 30,*/ +.equ FMI_NBBADR_OFS , 0x10 /* Non-boot Bank Base Address Register #!!! adresseses do not correspond*/ +.equ FMI_CR_OFS , 0x18 /* Control Register */ +.equ FMI_SR_OFS , 0x1C /* Status Register */ + + +.equ FMI_CR_Val , 0x00000018 +.equ FMI_BBSR_Val , 0x00000004 +.equ FMI_BBADR_Val , 0x00000000 +.equ FMI_NBBSR_Val , 0x00000002 +.equ FMI_NBBADR_Val , 0x00080000 +.equ FLASH_CFG_Val , 0x00001010 +.equ FMI_SR_Val , 0x00000003 /* Clear status errors (register not in STR912 manual! */ + + +# System Control Unit (SCU) definitions +.equ SCU_BASE , 0x5C002000 /* SCU Base Address (non-buffered) */ +.equ SCU_CLKCNTR_OFS , 0x00 /* Clock Control register Offset */ +.equ SCU_PLLCONF_OFS , 0x04 /* PLL Configuration register Offset */ +.equ SCU_SYSTAT_OFS , 0x08 /* SCU status register offset */ +.equ SCU_PCGR0_OFS , 0x14 /* Peripheral Clock Gating Register 0 Offset */ +.equ SCU_PCGR1_OFS , 0x18 /* Peripheral Clock Gating Register 1 Offset */ +.equ SCU_SCR0_OFS , 0x34 /* System Configuration Register 0 Offset */ + + +.equ SCU_CLKCNTR_Val , 0x00030000 /* Use PLL, external memory ratio/2 */ +.equ SCU_PLLCONF_Val , 0x000AC019 +.equ SCU_PCGR0_Val , 0x000000DB /* Setup ext mem clock, EMI, SRAM, Prefetch Queue/Branch cache, FMI */ +.equ SCU_PCGR1_Val , 0x00C40000 /* Setup GPIO8, 9 & 4 */ +.equ SCU_SCR0_Val , 0x00000196 /* Disable Prefetch Queue and Branch cache, SRAM = 96kb */ +.equ SCU_SYSSTAT_LOCK , 0x01 /* Check for PLL locked */ + +# APB Bridge 1 & 2 definitions (Peripherals) +.equ APB0_BUF_BASE , 0x48001802 /* APB Bridge 0 Buffered Base Address */ +.equ APB0_NBUF_BASE , 0x58000000 /* APB Bridge 0 Non-buffered Base Address */ +.equ APB1_BUF_BASE , 0x4C000000 /* APB Bridge 1 Buffered Base Address */ +.equ APB1_NBUF_BASE , 0x5C000000 /* APB Bridge 1 Non-buffered Base Address */ + +# ETM Definitions +.equ IOPORT2_ETM_ENABLE_BASE , 0x5C00204C +.equ IOPORT6_ETM_ENABLE_BASE , 0x5C00205C + +.equ IOPORT2_ETM_ENABLE_VAL , 0x0000FFFF +.equ IOPORT6_ETM_ENABLE_VAL , 0x0000FFFF + +#************************************************************************* +# Stack definitions +#************************************************************************* + + .equ UND_Stack_Size, 8 + .equ SVC_Stack_Size, 256 + .equ ABT_Stack_Size, 8 + .equ FIQ_Stack_Size, 32 + .equ IRQ_Stack_Size, 512 + .equ USR_Stack_Size, 512 + .equ Top_Stack, RAM_Base + RAM_Size + +# NOTE: Startup Code must be linked first at Address at which it expects to run. + +#************************************************************************* +# STARTUP EXECUTABLE CODE +#************************************************************************* + + .text + .arm + .extern main + .global _startup + +_startup: + +#************************************************************************* +# Exception Vectors +#************************************************************************* +Vectors: + LDR PC, Reset_Addr /* 0x0000 */ + LDR PC, Undef_Addr /* 0x0004 */ + LDR PC, SWI_Addr /* 0x0008 */ + LDR PC, PAbt_Addr /* 0x000C */ + LDR PC, DAbt_Addr /* 0x0010 */ + NOP /* 0x0014 Reserved Vector */ + LDR PC, [PC, #-0xFF0] /* 0x0018 wraps around address space to 0xFFFFFF030. Vector from VicVECAddr */ + LDR PC, FIQ_Addr /* 0x001C FIQ has no VIC vector slot! */ + +#************************************************************************* +# Interrupt Vectors +#************************************************************************* + +Reset_Addr: .word Hard_Reset /* CPU reset vector and entry point */ +Undef_Addr: .word Undefined_Handler +SWI_Addr: .word SWI_Handler +PAbt_Addr: .word PAbt_Handler +DAbt_Addr: .word DAbt_Handler + .word 0 /* Reserved Address */ +IRQ_Addr: .word IRQ_Handler /* Does not get used due to "LDR PC, [PC, #-0xFF0]" above */ +FIQ_Addr: .word FIQ_Handler + +# Dummy Interrupt Vector Table (real service routines in INTERRUPT.C) + +Undefined_Handler: B Undefined_Handler +SWI_Handler: B SWI_Handler +PAbt_Handler: B PAbt_Handler +DAbt_Handler: B DAbt_Handler +IRQ_Handler: B IRQ_Handler /* should never get here as IRQ is via VIC slot... */ +FIQ_Handler: B FIQ_Handler + + +#************************************************************************* +# Reset Handler Entry Point +#************************************************************************* +Hard_Reset: + StartupDelay 500000 + +#************************************************************************* +# Setup SRAM Size + + .IF SRAM_SETUP == 1 + + LDR R0, =SCU_BASE + LDR R1, =SCU_SCR0_Val + STR R1, [R0, #SCU_SCR0_OFS] + + .ENDIF + +#************************************************************************* +# Setup Flash Memory Interface (FMI) + + .IF FMI_SETUP == 1 + + LDR R0, =FMI_BASE + LDR R1, =FMI_BBSR_Val + STR R1, [R0, #FMI_BBSR_OFS] + LDR R1, =FMI_NBBSR_Val + STR R1, [R0, #FMI_NBBSR_OFS] + LDR R1, =(FMI_BBADR_Val >> 2) + STR R1, [R0, #FMI_BBADR_OFS] + LDR R1, =(FMI_NBBADR_Val >> 2) + STR R1, [R0, #FMI_NBBADR_OFS] + LDR R2, =FMI_CR_Val + STR R2, [R0, #FMI_CR_OFS] + + LDR R2, =FMI_SR_Val + STR R2, [R0, #FMI_SR_OFS] + + # Write "Write flash configuration" command (60h) + MOV R0, R1, LSL #2 + MOV R1, #0x60 + STRH R1, [R0, #0] + + # Write "Write flash configuration confirm" command (03h) + LDR R2, =(FLASH_CFG_Val >> 2) + ADD R0, R0, R2 + MOV R1, #0x03 + STRH R1, [R0, #0] + + .ENDIF + +#************************************************************************* +# Setup Clock PLL + + .IF CLOCK_SETUP == 1 + + LDR R0, =SCU_BASE + LDR R1, =0x00020002 + STR R1, [R0, #SCU_CLKCNTR_OFS] /* Select OSC as clock src */ + + NOP /* Wait for oscillator stabilisation */ + NOP /* Must be more than 10 oscillator periods */ + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + LDR R1, =0x0003C019 /* Disable PLL */ + STR R1, [R0, #SCU_PLLCONF_OFS] + LDR R1, =SCU_PLLCONF_Val + STR R1, [R0, #SCU_PLLCONF_OFS] /* Set new PLL values */ + + .IF (SCU_PLLCONF_Val & 0x8000) /* See if PLL is being used */ + + LDR R1, =SCU_SYSSTAT_LOCK +PLL_LOCK_LOOP: + LDR R2,[R0, #SCU_SYSTAT_OFS] /* Wait for PLL lock */ + ANDS R2, R2, R1 + BEQ PLL_LOCK_LOOP + + .ENDIF + + LDR R1, =SCU_PLLCONF_Val + STR R1, [R0, #SCU_PLLCONF_OFS] + LDR R1, =SCU_CLKCNTR_Val + STR R1, [R0, #SCU_CLKCNTR_OFS] + + LDR R1, =SCU_PCGR0_Val /* Enable clock gating */ + STR R1, [R0, #SCU_PCGR0_OFS] + LDR R1, =SCU_PCGR1_Val + STR R1, [R0, #SCU_PCGR1_OFS] + .ENDIF + + +#************************************************************************* +# Embedded Trace Module Setup +#************************************************************************* + + .IF ETM_SETUP == 1 + +# Configure IOPORT2 for ETM operation + LDR R0, =IOPORT2_ETM_ENABLE_BASE + LDR R1, =IOPORT2_ETM_ENABLE_VAL + STR R1, [R0, #0] + +# Configure IOPORT6 for ETM operation + LDR R0, =IOPORT6_ETM_ENABLE_BASE + LDR R1, =IOPORT6_ETM_ENABLE_VAL + STR R1, [R0, #0] + + .ENDIF + + +#************************************************************************* +# Compiler Runtime Environment Setup +#************************************************************************* +# Note: R13 = SP + +# Setup Stack for each mode + LDR R0, =Top_Stack + +# Set up Fast Interrupt Mode and set FIQ Mode Stack + MSR CPSR_c, #Mode_FIQ|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #FIQ_Stack_Size + +# Set up Interrupt Mode and set IRQ Mode Stack + msr CPSR_c, #Mode_IRQ|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #IRQ_Stack_Size + +# Set up Abort Mode and set Abort Mode Stack + msr CPSR_c, #Mode_ABT|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #ABT_Stack_Size + +# Set up Undefined Instruction Mode and set Undef Mode Stack + msr CPSR_c, #Mode_UND|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #UND_Stack_Size + +# Set up Supervisor Mode and set Supervisor Mode Stack + msr CPSR_c, #Mode_SVC|I_BIT|F_BIT + mov r13, r0 + sub r0, r0, #SVC_Stack_Size + +# Set up User Mode and set User Mode Stack + msr CPSR_c, #Mode_USR /* Leave interrupts enabled in user mode */ + mov r13, r0 /* Note: interrupts will not happen until VIC is enabled */ + +# Setup a default Stack Limit (when compiled with "-mapcs-stack-check") + SUB SL, SP, #1<<10 /* 1kB */ + +# Initialise current CPU status to prevent unwanted interrupts +# msr CPSR_c,#0xD3 + +#************************************************************************* +# Initialise RAM For Compiler Variables +#************************************************************************* + + copy_section2 data, _etext, __data_start__, _edata + +#************************************************************************* +# Clear .bss section +#************************************************************************* + + clear_section bss, __bss_start__, __bss_end__ + clear_section bss2, __bss2_start__, __bss2_end__ + +#************************************************************************* +# Enter the C code +#************************************************************************* +# Jump to main() + + B main + + .size _startup, . - _startup + +#************************************************************************* +# END +#************************************************************************* + .end diff --git a/uc_str912/prj_blinky_complex_startup/startup_generic.S b/uc_str912/prj_blinky_complex_startup/startup_generic.S new file mode 100644 index 0000000..711a5d0 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/startup_generic.S @@ -0,0 +1,162 @@ +#***************************************************************************** +#* +#* Project: Generic include file for ARM startup +#* Filename: startup.inc +#* Date: 11.05.2004 +#* Rights: Hitex Development Tools GmbH +#* Greschbachstr. 12 +#* 76229 Karlsruhe +#* +#**************************************************************************** + +# *** Startup Code (executed after Reset) *** + + +# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F + + .equ T_BIT, 0x20 /* when T bit is set, thumb mode active */ + .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ + .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ + +# --------------------------------------------- +# macro definition for stack memory reservation +# --------------------------------------------- +# use this macro to setup the stack + .macro setup_stack label1, size, mode_bits + + .lcomm __range_\label1, (\size - 1) * 4 + .global \label1 + .lcomm \label1, 4 + + ldr r0, adr_\label1 + msr CPSR_c, \mode_bits + mov r13, r0 + + .endm + +# use this macro to define the label for the setup_stack mcaro! + .macro stack_adr label1 +adr_\label1: + .word \label1 + .endm +# --------------------------------------------- +# copy section +# use this macro to copy a section +# parameters: +# - individual name, used to create labels +# - source pointer +# - destination pointer +# - source pointer + length > end address of source +# --------------------------------------------- + .macro copy_section sec_name, source, destination, source_end + + ldr R1, =\source + ldr R2, =\destination + ldr R3, =\source_end +_cplp_\sec_name: + cmp R1, R3 + ldrlo R0, [R1], #4 + strlo R0, [R2], #4 + blo _cplp_\sec_name + + .endm + +# --------------------------------------------- +# copy section 2 +# use this macro to copy a section +# parameters: +# - individual name, used to create labels +# - source pointer +# - destination pointer +# - destination pointer + length > end address of destination +# --------------------------------------------- + .macro copy_section2 sec_name, source, destination, destination_end + + ldr R1, =\source + ldr R2, =\destination + ldr R3, =\destination_end +_cplp_\sec_name: + cmp R2, R3 + ldrlo R0, [R1], #4 + strlo R0, [R2], #4 + blo _cplp_\sec_name + + .endm + +# --------------------------------------------- +# clear section +# use this macro to clear bss sections +# --------------------------------------------- + .macro clear_section sec_name, source, source_end + + mov R0, #0 + ldr R1, =\source + ldr R2, =\source_end +_cllp_\sec_name: + cmp R1, R2 + strlo R0, [R1], #4 + blo _cllp_\sec_name + .endm + +# --------------------------------------------- +# examples how to use the macros +# --------------------------------------------- +# Setup stacks for the operating modes +# --------------------------------------------- + +# setup_stack UND_Stack, UND_Stack_Size, #Mode_UND|I_BIT|F_BIT +# setup_stack SVC_Stack, SVC_Stack_Size, #Mode_SVC|I_BIT|F_BIT +# setup_stack ABT_Stack, ABT_Stack_Size, #Mode_ABT|I_BIT|F_BIT +# setup_stack FIQ_Stack, FIQ_Stack_Size, #Mode_FIQ|I_BIT|F_BIT +# setup_stack IRQ_Stack, IRQ_Stack_Size, #Mode_IRQ|I_BIT|F_BIT +# setup_stack USR_Stack, USR_Stack_Size, #Mode_USR + +# --------------------------------------------- +# copy sections +# --------------------------------------------- + +# copy code into internal ram +# copy_section code, __code_start__, RAM_Base_Boot, __code_end__ + +# Relocate .data section (Copy from ROM to RAM) +# copy_section data, __data_start__, __data_start__+RAM_Base_Boot, __data_end__ + +# --------------------------------------------- +# Clear .bss section +# --------------------------------------------- + +# Clear .bss section (Zero init) +# clear_section bss, __bss_start__, __bss_end__ + +# --------------------------------------------- +# startup delay +# use this macro if you are working with an debugger +# the startup delay avoid problems while +# the application start before the debug interface +# becomes controled by the debugger +# --------------------------------------------- + +# a goodf choice for the delay value is +# cpu clock / 100 with ATMEL controllers +# cpu clock / 40 with Philips controllers + + .macro StartupDelay delay_value + + ldr R1, =\delay_value + ldr R2, =0 +__StartDelay: + sub R1, R1, #1 + cmp R1, R2 + bhi __StartDelay + + .endm + +# --------------------------------------------- diff --git a/uc_str912/prj_blinky_complex_startup/syscalls.c b/uc_str912/prj_blinky_complex_startup/syscalls.c new file mode 100644 index 0000000..ce25753 --- /dev/null +++ b/uc_str912/prj_blinky_complex_startup/syscalls.c @@ -0,0 +1,180 @@ +/**************************************************************************** +* Copyright (c) 2009 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +* 28.03.09 mifi First Version, based on the original syscall.c from +* newlib version 1.17.0 +****************************************************************************/ + +#include +#include +#include +#include +#include + +/***************************************************************************/ + +int _read_r (struct _reent *r, int file, char * ptr, int len) +{ + r = r; + file = file; + ptr = ptr; + len = len; + + errno = EINVAL; + return -1; +} + +/***************************************************************************/ + +int _lseek_r (struct _reent *r, int file, int ptr, int dir) +{ + r = r; + file = file; + ptr = ptr; + dir = dir; + + return 0; +} + +/***************************************************************************/ + +int _write_r (struct _reent *r, int file, char * ptr, int len) +{ + r = r; + file = file; + ptr = ptr; + +#if 0 + int index; + + /* For example, output string by UART */ + for(index=0; index stack_ptr) + { + /* Some of the libstdc++-v3 tests rely upon detecting + out of memory errors, so do not abort here. */ +#if 0 + extern void abort (void); + + _write (1, "_sbrk: Heap and stack collision\n", 32); + + abort (); +#else + errno = ENOMEM; + return (caddr_t) -1; +#endif + } + + heap_end += incr; + + return (caddr_t) prev_heap_end; +} + +/***************************************************************************/ + +int _fstat_r (struct _reent *r, int file, struct stat * st) +{ + r = r; + file = file; + + memset (st, 0, sizeof (* st)); + st->st_mode = S_IFCHR; + return 0; +} + +/***************************************************************************/ + +int _isatty_r(struct _reent *r, int fd) +{ + r = r; + fd = fd; + + return 1; +} + + + +void _exit() +{ + while(1); +} + + +int _getpid() +{ + return 0; +} + +int _kill(int pid, int sig) +{ + return 0; +} + +/*** EOF ***/ + + diff --git a/uc_str912/prj_blinky_simple_startup/Makefile b/uc_str912/prj_blinky_simple_startup/Makefile new file mode 100644 index 0000000..171319e --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/Makefile @@ -0,0 +1,495 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# WinARM template makefile +# by Giacomo Fazio and Antonio Nasca, Catania, Italy +# +# +# +# based on the WinARM template makefile written by Martin Thomas +# Released to the Public Domain +# Please read the make user manual! +# +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make program = Download the hex file to the device +# +# (TODO: make filename.s = Just compile filename.c into the assembler code only) +# +# To rebuild project do "make clean" then "make all". +# Toolchain prefix (i.e arm-elf -> arm-elf-gcc.exe) +#TCHAIN = arm-elf +TCHAIN = arm-none-eabi + +#USE_THUMB_MODE = YES +USE_THUMB_MODE = NO + +# MCU name and submodel +MCU = arm966e-s +SUBMDL = STR91x + +## Create ROM-Image +RUN_MODE=ROM_RUN +## Create RAM-Image +#RUN_MODE=RAM_RUN + +## not supported in this example: +## Exception-Vector placement only supported for "ROM_RUN" +## (placement settings ignored when using "RAM_RUN") +## - Exception vectors in ROM: +#VECTOR_LOCATION=VECTORS_IN_ROM +## - Exception vectors in RAM: +#VECTOR_LOCATION=VECTORS_IN_RAM + + +# Target file name (without extension). +TARGET = main + +# List C source files here. (C dependencies are automatically generated.) +# use file-extension c for "c-only"-files +SRC = src/$(TARGET).c + +# List C source files here which must be compiled in ARM-Mode. +# use file-extension c for "c-only"-files +SRCARM = src/vectors.c +# thumb is possible too for vectors.c - keep ARM, TODO: profile + +# List C++ source files here. +# use file-extension cpp for C++-files (use extension .cpp) +CPPSRC = + +# List C++ source files here which must be compiled in ARM-Mode. +# use file-extension cpp for C++-files (use extension .cpp) +#CPPSRCARM = $(TARGET).cpp +CPPSRCARM = + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +# List Assembler source files here which must be assembled in ARM-Mode.. +ASRCARM = src/vector.S src/startup.S + +# Path to Linker-Scripts +LINKERSCRIPTPATH = . + +## Output format. (can be ihex or binary or both) +## (binary i.e. for openocd and SAM-BA, hex i.e. for lpc21isp and uVision) +#FORMAT = ihex +#FORMAT = binary +FORMAT = both + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +#OPT = s +OPT = 0 + +## Using the Atmel AT91_lib produces warning with +## the default warning-levels. +## yes - disable these warnings; no - keep default settings +#AT91LIBNOWARN = yes +AT91LIBNOWARN = no + +# Debugging format. +# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2. +# AVR (extended) COFF requires stabs, plus an avr-objcopy run. +#DEBUG = stabs +DEBUG = dwarf-2 + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +EXTRAINCDIRS = ./include ./str91x_lib/include + +# List any extra directories to look for library files here. +# Each directory must be seperated by a space. +#EXTRA_LIBDIRS = ../arm7_efsl_0_2_4 +EXTRA_LIBDIRS = ./str91x_lib + + +# Compiler flag to set the C Standard level. +# c89 - "ANSI" C +# gnu89 - c89 plus GCC extensions +# c99 - ISO C99 standard (not yet fully implemented) +# gnu99 - c99 plus GCC extensions +CSTANDARD = -std=gnu99 + +# Place -D or -U options for C here +CDEFS = -D$(RUN_MODE) + +# Place -I options here +CINCS = + +# Place -D or -U options for ASM here +ADEFS = -D$(RUN_MODE) + +ifdef VECTOR_LOCATION +CDEFS += -D$(VECTOR_LOCATION) +ADEFS += -D$(VECTOR_LOCATION) +endif + +CDEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__ +ADEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__ + +# Compiler flags. + +ifeq ($(USE_THUMB_MODE),YES) +THUMB = -mthumb +THUMB_IW = -mthumb-interwork +else +THUMB = +THUMB_IW = +endif + +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +# +# Flags for C and C++ (arm-elf-gcc/arm-elf-g++) +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) $(CINCS) +CFLAGS += -O$(OPT) +CFLAGS += -Wall -Wcast-align -Wimplicit +CFLAGS += -Wpointer-arith -Wswitch +CFLAGS += -ffunction-sections -fdata-sections +CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused +CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +# flags only for C +CONLYFLAGS += -Wnested-externs +CONLYFLAGS += $(CSTANDARD) + +ifneq ($(AT91LIBNOWARN),yes) +#AT91-lib warnings with: +CFLAGS += -Wcast-qual +CONLYFLAGS += -Wmissing-prototypes +CONLYFLAGS += -Wstrict-prototypes +CONLYFLAGS += -Wmissing-declarations +endif + +# flags only for C++ (arm-elf-g++) +# CPPFLAGS = -fno-rtti -fno-exceptions +CPPFLAGS = + +# Assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlns: create listing +# -g$(DEBUG): have the assembler create line number information +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG) + + +#Additional libraries. + +# Extra libraries +# Each library-name must be seperated by a space. +# To add libxyz.a, libabc.a and libefsl.a: +# EXTRA_LIBS = xyz abc efsl +#EXTRA_LIBS = efsl +EXTRA_LIBS = STR91x_lib + +#Support for newlibc-lpc (file: libnewlibc-lpc.a) +#NEWLIBLPC = -lnewlib-lpc + +MATH_LIB = -lm + +# CPLUSPLUS_LIB = -lstdc++ + + +# Linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref,--gc-sections,--no-warn-mismatch +LDFLAGS += -lc +LDFLAGS += $(NEWLIBLPC) $(MATH_LIB) +LDFLAGS += -lc -lgcc +LDFLAGS += $(CPLUSPLUS_LIB) +LDFLAGS += $(patsubst %,-L%,$(EXTRA_LIBDIRS)) +LDFLAGS += $(patsubst %,-l%,$(EXTRA_LIBS)) + +# Set Linker-Script Depending On Selected Memory and Controller +ifeq ($(RUN_MODE),RAM_RUN) +LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-RAM.ld +else +LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-ROM.ld +endif + + +# Define directories, if needed. +## DIRARM = c:/WinARM/ +## DIRARMBIN = $(DIRAVR)/bin/ +## DIRAVRUTILS = $(DIRAVR)/utils/bin/ + +# Define programs and commands. +SHELL = sh +CC = $(TCHAIN)-gcc +CPP = $(TCHAIN)-g++ +AR = $(TCHAIN)-ar +OBJCOPY = $(TCHAIN)-objcopy +OBJDUMP = $(TCHAIN)-objdump +SIZE = $(TCHAIN)-size +NM = $(TCHAIN)-nm +REMOVE = rm -f +REMOVEDIR = rm -f -r +COPY = cp + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = "-------- begin (mode: $(RUN_MODE)) --------" +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_FLASH = Creating load file for Flash: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_ARM = "Compiling C (ARM-only):" +MSG_COMPILINGCPP = Compiling C++: +MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):" +MSG_ASSEMBLING = Assembling: +MSG_ASSEMBLING_ARM = "Assembling (ARM-only):" +MSG_CLEANING = Cleaning project: +MSG_FORMATERROR = Can not handle output-format +MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now. + +# Define all object files. +COBJ = $(SRC:.c=.o) +AOBJ = $(ASRC:.S=.o) +COBJARM = $(SRCARM:.c=.o) +AOBJARM = $(ASRCARM:.S=.o) +CPPOBJ = $(CPPSRC:.cpp=.o) +CPPOBJARM = $(CPPSRCARM:.cpp=.o) + +# Define all listing files. +LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst) +LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst) + +# Compiler flags to generate dependency files. +### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d +GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS) + + +# Default target. +all: begin gccversion sizebefore build sizeafter finished end + +ifeq ($(FORMAT),ihex) +build: elf hex lss sym +hex: $(TARGET).hex +IMGEXT=hex +else +ifeq ($(FORMAT),binary) +build: elf bin lss sym +bin: $(TARGET).bin +IMGEXT=bin +else +ifeq ($(FORMAT),both) +build: elf hex bin lss sym +hex: $(TARGET).hex +bin: $(TARGET).bin +else +$(error "$(MSG_FORMATERROR) $(FORMAT)") +endif +endif +endif + +elf: $(TARGET).elf +lss: $(TARGET).lss +sym: $(TARGET).sym + +# Eye candy. +begin: + @echo + @echo $(MSG_BEGIN) + +finished: + @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf +sizebefore: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + + +# Display compiler version information. +gccversion : + @$(CC) --version + +# FLASH Programming with OPENOCD + +# specify the directory where openocd executable resides (openocd-ftd2xx.exe or openocd-pp.exe) +# Note: you may have to adjust this if a newer version of YAGARTO has been downloaded +OPENOCD_DIR = 'c:\Programmi\openocd\bin\' + +# specify OpenOCD executable (pp is for the wiggler, ftd2xx is for the USB debugger) +OPENOCD = $(OPENOCD_DIR)openocd-pp.exe +#OPENOCD = $(OPENOCD_DIR)openocd-ftd2xx.exe + +# specify OpenOCD configuration file (pick the one for your device) +#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_signalyzer-flash-program.cfg +#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_jtagkey-flash-program.cfg +#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_armusbocd-flash-program.cfg +OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_pp-flash-program.cfg + +program: + @echo + @echo "Flash Programming with OpenOCD..." + $(OPENOCD) -f $(OPENOCD_CFG) + @echo + @echo + @echo "Flash Programming Finished." + + +# Create final output file (.hex) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O ihex $< $@ + +# Create final output file (.bin) from ELF output file. +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary $< $@ + + +# Create extended listing file from ELF output file. +# testing: option -C +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S -C $< > $@ + + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) +%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) +# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) + +# Compile: create object files from C source files. ARM/Thumb +$(COBJ) : %.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C source files. ARM-only +$(COBJARM) : %.o : %.c + @echo + @echo $(MSG_COMPILING_ARM) $< + $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM/Thumb +$(CPPOBJ) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP) $< + $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM-only +$(CPPOBJARM) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP_ARM) $< + $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. ARM/Thumb +## does not work - TODO - hints welcome +##$(COBJ) : %.s : %.c +## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM/Thumb +$(AOBJ) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM-only +$(AOBJARM) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING_ARM) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list finished end + + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).a90 + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lnk + $(REMOVE) $(TARGET).lss + $(REMOVE) $(COBJ) + $(REMOVE) $(CPPOBJ) + $(REMOVE) $(AOBJ) + $(REMOVE) $(COBJARM) + $(REMOVE) $(CPPOBJARM) + $(REMOVE) $(AOBJARM) + $(REMOVE) $(LST) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRCARM:.c=.s) + $(REMOVE) $(SRCARM:.c=.d) + $(REMOVE) $(CPPSRC:.cpp=.s) + $(REMOVE) $(CPPSRC:.cpp=.d) + $(REMOVE) $(CPPSRCARM:.cpp=.s) + $(REMOVE) $(CPPSRCARM:.cpp=.d) + $(REMOVEDIR) .dep | exit 0 + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin lss sym clean clean_list program + diff --git a/uc_str912/prj_blinky_simple_startup/STR91x-RAM.ld b/uc_str912/prj_blinky_simple_startup/STR91x-RAM.ld new file mode 100644 index 0000000..aced384 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/STR91x-RAM.ld @@ -0,0 +1,218 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 256; + _STACKSIZE_SVC = 0; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t .glue_7) + KEEP(*(.fini)) + *(.gcc_except_table) + } >DATA =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >DATA + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >DATA + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >DATA + . = ALIGN(4); + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } >DATA + . = ALIGN(4); + + __data_start = .; + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/prj_blinky_simple_startup/STR91x-ROM.ld b/uc_str912/prj_blinky_simple_startup/STR91x-ROM.ld new file mode 100644 index 0000000..ed2979b --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/STR91x-ROM.ld @@ -0,0 +1,221 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 256; + _STACKSIZE_SVC = 0; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t .glue_7) + KEEP(*(.fini)) + *(.gcc_except_table) + } >CODE =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >CODE + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >CODE + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >CODE + . = ALIGN(4); + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + __data_start = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + . = ALIGN(4); + *(.fastrun .fastrun.*) + } >DATA + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/prj_blinky_simple_startup/include/vectors.h b/uc_str912/prj_blinky_simple_startup/include/vectors.h new file mode 100644 index 0000000..d48e61f --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/include/vectors.h @@ -0,0 +1,67 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +#ifndef _VECTOR_H +#define _VECTOR_H + +#ifdef __cplusplus +extern "C" { +#endif + +void Undefined_Handler(void); +void FIQ_Handler(void); +void SWI_Handler(void); +void Prefetch_Handler(void); +void Abort_Handler(void); +void WDG_IRQHandler(void); +void SW_IRQHandler(void); +void ARMRX_IRQHandler(void); +void ARMTX_IRQHandler(void); +void TIM0_IRQHandler(void); +void TIM1_IRQHandler(void); +void TIM2_IRQHandler(void); +void TIM3_IRQHandler(void); +void USBHP_IRQHandler(void); +void USBLP_IRQHandler(void); +void SCU_IRQHandler(void); +void ENET_IRQHandler(void); +void DMA_IRQHandler(void); +void CAN_IRQHandler(void); +void MC_IRQHandler(void); +void ADC_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void I2C0_IRQHandler(void); +void I2C1_IRQHandler(void); +void SSP0_IRQHandler(void); +void SSP1_IRQHandler(void); +void LVD_IRQHandler(void); +void RTC_IRQHandler(void); +void WIU_IRQHandler(void); +void EXTIT0_IRQHandler(void); +void EXTIT1_IRQHandler(void); +void EXTIT2_IRQHandler(void); +void EXTIT3_IRQHandler(void); +void USBWU_IRQHandler(void); +void PFQBC_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif //_VECTOR_H diff --git a/uc_str912/prj_blinky_simple_startup/load_segger.gdb b/uc_str912/prj_blinky_simple_startup/load_segger.gdb new file mode 100644 index 0000000..95d2621 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/load_segger.gdb @@ -0,0 +1,20 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:2331 + +monitor speed adaptive +monitor endian little + +monitor reset +monitor flash device = STR912FAW44 +monitor flash breakpoints = 1 +monitor flash download = 1 +monitor halt + + +pwd +load main.elf +file main.elf diff --git a/uc_str912/prj_blinky_simple_startup/src/main.c b/uc_str912/prj_blinky_simple_startup/src/main.c new file mode 100644 index 0000000..61ab08c --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/src/main.c @@ -0,0 +1,102 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : main.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Main program body +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_lib.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + GPIO_InitTypeDef GPIO_InitStructure; + +/* Private function prototypes -----------------------------------------------*/ + void SCU_Configuration(void); + static void Delay(u32 nCount); + +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : main +* Description : Main program +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +int main() +{ + /* Configure the system clocks */ + SCU_Configuration(); + +/* GPIO Configuration --------------------------------------------------------*/ + GPIO_DeInit(GPIO8); + GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_4 | GPIO_Pin_6; + GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ; + GPIO_Init (GPIO8, &GPIO_InitStructure); + + while(1) + { + /* Turn OFF leds connected to P9.0, P9.1, P9.2 and P9.3 pins */ + GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_SET); + Delay(0x7FFFF); + GPIO_WriteBit(GPIO8, GPIO_Pin_2, Bit_SET); + Delay(0x7FFFF); + GPIO_WriteBit(GPIO8, GPIO_Pin_4, Bit_SET); + Delay(0x7FFFF); + GPIO_WriteBit(GPIO8, GPIO_Pin_6, Bit_SET); + Delay(0x7FFFF); + /* Turn ON leds connected to P9.0, P9.1, P9.2 and P9.3 pins */ + GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_RESET); + Delay(0x7FFFF); + GPIO_WriteBit(GPIO8, GPIO_Pin_2, Bit_RESET); + Delay(0x7FFFF); + GPIO_WriteBit(GPIO8, GPIO_Pin_4, Bit_RESET); + Delay(0x7FFFF); + GPIO_WriteBit(GPIO8, GPIO_Pin_6, Bit_RESET); + Delay(0x7FFFF); + } +} + +/******************************************************************************* +* Function Name : SCU_Configuration +* Description : Configures the system clocks. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_Configuration(void) +{ + /* Enable the __GPIO9 */ + SCU_APBPeriphClockConfig(__GPIO8 ,ENABLE); +} + +/******************************************************************************* +* Function Name : Delay +* Description : Inserts a delay time. +* Input : nCount: specifies the delay time length. +* Output : None +* Return : None +*******************************************************************************/ +static void Delay(u32 nCount) +{ + u32 j = 0; + + for(j = nCount; j != 0; j--); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_simple_startup/src/startup.s b/uc_str912/prj_blinky_simple_startup/src/startup.s new file mode 100644 index 0000000..cef54d8 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/src/startup.s @@ -0,0 +1,233 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/**** Startup Code (executed after Reset) ****/ + +/* Frequency values kHz */ +/* set to suit target hardware */ + + .equ FOSC, 25000 + +/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */ + + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + .equ SRAM32, 0x00 + .equ SRAM64, 0x08 + .equ SRAM96, 0x10 + +/* --- System memory locations */ + + .equ SCRO_AHB_UMB, 0x5C002034 /* System configuration register 0 (unbuffered) */ + + .equ FMI_BASE_UMB, 0x54000000 /* Flash FMI base address (unbuffered) */ + .equ BBSR_off_addr, 0x00 + .equ NBBSR_off_addr, 0x04 + .equ BBADR_off_addr, 0x0C + .equ NBBADR_off_addr, 0x10 + .equ CR_off_addr, 0x18 + +.ifndef LIBUFF + .equ LIBUFF, 0 +.endif + +/* Startup Code must be linked first at Address at which it expects to run. */ + + .text + .arm + .section .init, "ax" + + .global _start + .global _Main_Crystal + +/* After remap this will be our reset handler */ + +_start: + LDR pc, =NextInst +NextInst: + + NOP /* Wait for OSC stabilization */ + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +/* Enable buffered mode */ + +.if LIBUFF + MRC p15, 0, r0, c1, c0, 0 /* Read CP15 register 1 into r0 */ + ORR r0, r0, #0x8 /* Enable Write Buffer on AHB */ + MCR p15, 0, r0, c1, c0, 0 /* Write CP15 register 1 */ +.endif + +/* Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, */ +/* when the bank 0 is the boot bank, then enable the Bank 1. */ + + LDR r0, =FMI_BASE_UMB + LDR r1, =0x4 /* configure 512KB Boot bank 0 */ + STR r1, [r0, #BBSR_off_addr] + + LDR r1, =0x2 /* configure 32KB Non Boot bank 1 */ + STR r1, [r0, #NBBSR_off_addr] + + LDR r1, =(0x00000000 >> 2) /* Boot Bank Base Address */ + STR r1, [r0, #BBADR_off_addr] + + LDR r1, =(0x00080000 >> 2) /* Non Boot Bank Base Address */ + STR r1, [r0, #NBBADR_off_addr] + + LDR r1, =0x18 /* Flash Banks 0 1 enabled */ + STR r1, [r0, #CR_off_addr] + +/* Enable 96K RAM */ + + LDR r0, =SCRO_AHB_UMB +# LDR r1, =0x0196 /* prefetch disabled, default enabled */ + LDR r1, =0x0187|SRAM96 + STR r1, [r0] + +/* Set bits 17-18 (Instruction/Data TCM order) of the */ +/* Core Configuration Control Register */ + + MOV r0, #0x60000 + MCR p15, 0x1, r0, c15, c1, 0 + +/* Setup Stack for each mode */ + +/* Enter Abort Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_ABT|I_Bit|F_Bit + LDR sp, =__stack_abt_end__ + +/* Enter Undefined Instruction Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_UND|I_Bit|F_Bit + LDR sp, =__stack_und_end__ + +/* Enter Supervisor Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SVC|I_Bit|F_Bit + LDR sp, =__stack_svc_end__ + +/* Enter FIQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_FIQ|I_Bit|F_Bit + LDR sp, =__stack_fiq_end__ + +/* Enter IRQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit + LDR sp, =__stack_irq_end__ + +/* Enter System/User Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SYS + LDR sp, =__stack_end__ + +/* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */ + + LDR sl, =__bss_end__ + +/* Relocate .data section (Copy from ROM to RAM) */ + + LDR r1, =_etext + LDR r2, =__data_start + LDR r3, =_edata +LoopRel: + CMP r2, r3 + LDRLO r0, [r1], #4 + STRLO r0, [r2], #4 + BLO LoopRel + +/* Clear .bss section (Zero init) */ + + MOV r0, #0 + LDR r1, =__bss_start__ + LDR r2, =__bss_end__ +LoopZI: + CMP r1, r2 + STRLO r0, [r1], #4 + BLO LoopZI + +/* Call C++ constructors */ + + LDR r0, =__ctors_start__ + LDR r1, =__ctors_end__ +ctor_loop: + CMP r0, r1 + BEQ ctor_end + LDR r2, [r0], #4 + STMFD sp!, {r0-r1} + BLX r2 + LDMFD sp!, {r0-r1} + B ctor_loop +ctor_end: + +/* Need to set up standard file handles */ +/* Only used under simulator, normally overide syscall.c */ + +# BL initialise_monitor_handles + +/* if we use debug version of str9lib this will call the init function */ + + BL libdebug +libdebug: + +/* Enter the C code, use B instruction so as to never return */ +/* use BL main if you want to use c++ destructors below */ + + B main + +/* Call destructors */ + +# LDR r0, =__dtors_start__ +# LDR r1, =__dtors_end__ +#dtor_loop: +# CMP r0, r1 +# BEQ dtor_end +# LDR r2, [r0], #4 +# STMFD sp!, {r0-r1} +# BLX r2 +# LDMFD sp!, {r0-r1} +# B dtor_loop +#dtor_end: + +/* Return from main, loop forever. */ + +#exit_loop: +# B exit_loop + +/* Fosc values, used by libstr9 */ + +_Main_Crystal: .long FOSC + + .weak libdebug + + .end diff --git a/uc_str912/prj_blinky_simple_startup/src/vector.s b/uc_str912/prj_blinky_simple_startup/src/vector.s new file mode 100644 index 0000000..7708f54 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/src/vector.s @@ -0,0 +1,202 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + + .equ VectorAddress, 0xFFFFF030 /* VIC Vector address register address. */ + .equ VectorAddressDaisy, 0xFC000030 /* Daisy VIC Vector address register */ + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */ + + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + .text + .arm + .section .vectors, "ax" + + .global Reset_Vec + +/* Note: LDR PC instructions are used here, though branch (B) instructions */ +/* could also be used, unless the ROM is at an address >32MB. */ + +/******************************************************************************* + Exception vectors +*******************************************************************************/ + +Reset_Vec: LDR pc, Reset_Addr /* Reset Handler */ +Undef_Vec: LDR pc, Undefined_Addr +SWI_Vec: LDR pc, SWI_Addr +PAbt_Vec: LDR pc, Prefetch_Addr +DAbt_Vec: LDR pc, Abort_Addr + NOP /* Reserved vector */ +IRQ_Vec: LDR pc, IRQ_Addr +FIQ_Vec: LDR pc, FIQ_Addr + +/******************************************************************************* + Exception handlers address table +*******************************************************************************/ + +Reset_Addr: .word _start +Undefined_Addr: .word UndefinedHandler +SWI_Addr: .word SWIHandler +Prefetch_Addr: .word PrefetchHandler +Abort_Addr: .word AbortHandler + .word 0 /* reserved */ +IRQ_Addr: .word IRQHandler +FIQ_Addr: .word FIQHandler + +/******************************************************************************* + Exception Handlers +*******************************************************************************/ + +/******************************************************************************* +* Macro Name : SaveContext +* Description : This macro used to save the context before entering + an exception handler. +* Input : The range of registers to store. +* Output : none +*******************************************************************************/ + +.macro SaveContext reg1 reg2 + STMFD sp!,{\reg1-\reg2,lr} /* Save The workspace plus the current return */ + /* address lr_ mode into the stack */ + MRS r1, spsr /* Save the spsr_mode into r1 */ + STMFD sp!, {r1} /* Save spsr */ +.endm + +/******************************************************************************* +* Macro Name : RestoreContext +* Description : This macro used to restore the context to return from + an exception handler and continue the program execution. +* Input : The range of registers to restore. +* Output : none +*******************************************************************************/ + +.macro RestoreContext reg1 reg2 + LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */ + MSR spsr_cxsf, r1 /* Restore spsr_mode */ + LDMFD sp!, {\reg1-\reg2,pc}^ /* Return to the instruction following */ + /* the exception interrupt */ +.endm + +/******************************************************************************* +* Function Name : IRQHandler +* Description : This function called when IRQ exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +IRQHandler: + SUB lr, lr, #4 /* Update the link register */ + SaveContext r0, r12 /* Save the workspace plus the current */ + /* return address lr_irq and spsr_irq */ + LDR r0, =VectorAddress + LDR r0, [r0] /* Read the routine address */ + LDR r1, =VectorAddressDaisy + LDR r1, [r1] + /* Padding between the acknowledge and re-enable of interrupts */ + /* For more details, please refer to the following URL */ + /* http://www.arm.com/support/faqip/3682.html */ + NOP + NOP + MSR cpsr_c, #Mode_SYS /* Switch to SYS mode and enable IRQ */ + STMFD sp!, {lr} /* Save the link register. */ + LDR lr, =ReturnAddress /* Read the return address. */ + MOV pc, r0 /* Branch to the IRQ handler. */ +ReturnAddress: + LDMFD sp!, {lr} /* Restore the link register. */ + MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit /* Switch to IRQ mode and disable IRQ */ + LDR r0, =VectorAddress /* Write to the VectorAddress to clear the */ + STR r0, [r0] /* respective interrupt in the internal interrupt */ + LDR r1, =VectorAddressDaisy /* Write to the VectorAddressDaisy to clear the */ + STR r1, [r1] /* respective interrupt in the internal interrupt */ + RestoreContext r0, r12 /* Restore the context and return to the program execution. */ + +/******************************************************************************* +* Function Name : SWIHandler +* Description : This function called when SWI instruction executed. +* Input : none +* Output : none +*******************************************************************************/ + +SWIHandler: + SaveContext r0, r12 /* r0 holds swi number */ + MOV r1, sp /* load regs */ + BL SWI_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : UndefinedHandler +* Description : This function called when undefined instruction + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +UndefinedHandler: + SaveContext r0, r12 + BL Undefined_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : PrefetchAbortHandler +* Description : This function called when Prefetch Abort + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +PrefetchHandler: + SUB lr, lr, #4 /* Update the link register. */ + SaveContext r0, r12 + BL Prefetch_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : DataAbortHandler +* Description : This function is called when Data Abort + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +AbortHandler: + SUB lr, lr, #8 /* Update the link register. */ + SaveContext r0, r12 + BL Abort_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : FIQHandler +* Description : This function is called when FIQ + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +FIQHandler: + SUB lr, lr, #4 /* Update the link register. */ + SaveContext r0, r7 + BL FIQ_Handler + RestoreContext r0, r7 + + .end diff --git a/uc_str912/prj_blinky_simple_startup/src/vectors.c b/uc_str912/prj_blinky_simple_startup/src/vectors.c new file mode 100644 index 0000000..4022391 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/src/vectors.c @@ -0,0 +1,462 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +#include "vectors.h" + +/******************************************************************************* +* Function Name : Undefined_Handler +* Description : This function Undefined instruction exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Undefined_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SWI_Handler +* Description : This function handles SW exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SWI_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles preftetch abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Prefetch_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : Abort_Handler +* Description : This function handles data abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Abort_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : FIQ_Handler +* Description : This function handles FIQ exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FIQ_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : WDG_IRQHandler +* Description : This function handles the WDG interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SW_IRQHandler +* Description : This function handles the SW interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SW_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ARMRX_IRQHandler +* Description : This function handles the ARMRX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMRX_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ARMTX_IRQHandler +* Description : This function handles the ARMTX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMTX_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM0_IRQHandler +* Description : This function handles the TIM0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM1_IRQHandler +* Description : This function handles the TIM1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM2_IRQHandler +* Description : This function handles the TIM2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM3_IRQHandler +* Description : This function handles the TIM3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM3_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBHP_IRQHandler +* Description : This function handles the USBHP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBHP_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBLP_IRQHandler +* Description : This function handles the USBLP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBLP_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SCU_IRQHandler +* Description : This function handles the SCU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ENET_IRQHandler +* Description : This function handles the ENET interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ENET_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : DMA_IRQHandler +* Description : This function handles the DMA interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : CAN_IRQHandler +* Description : This function handles the CAN interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : MC_IRQHandler +* Description : This function handles the MC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ADC_IRQHandler +* Description : This function handles the ADC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART0_IRQHandler +* Description : This function handles the UART0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART1_IRQHandler +* Description : This function handles the UART1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART2_IRQHandler +* Description : This function handles the UART2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : I2C0_IRQHandler +* Description : This function handles the I2C0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : I2C1_IRQHandler +* Description : This function handles the I2C1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SSP0_IRQHandler +* Description : This function handles the SSP0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SSP1_IRQHandler +* Description : This function handles the SSP1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : LVD_IRQHandler +* Description : This function handles the LVD interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LVD_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles the RTC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : WIU_IRQHandler +* Description : This function handles the WIU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WIU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT0_IRQHandler +* Description : This function handles the EXTIT0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT1_IRQHandler +* Description : This function handles the EXTIT1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT2_IRQHandler +* Description : This function handles the EXTIT2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT3_IRQHandler +* Description : This function handles the EXTIT3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT3_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBWU_IRQHandler +* Description : This function handles the USBWU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBWU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : PFQBC_IRQHandler +* Description : This function handles the PFQBC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PFQBC_IRQHandler(void) +{ + while(1); +} diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/Makefile b/uc_str912/prj_blinky_simple_startup/str91x_lib/Makefile new file mode 100644 index 0000000..e65be4d --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/Makefile @@ -0,0 +1,38 @@ +# efsl library Makefile for STR910 by Giacomo Fazio and Antonio Nasca +# (based on efsl library makefile for AT91SAM7S by Martin Thomas) + + +MCU = arm9e +#THUMB = -mthumb -mthumb-interwork +THUMB = + +LIBNAME = libSTR91x_lib.a + +COPT= -mcpu=$(MCU) $(THUMB) -gdwarf-2 -Wall -Os +INCLUDEDIRS=-Iinclude +CFLAGS=$(COPT) $(INCLUDEDIRS) +# gcc4 unused code-removal: +CFLAGS += -ffunction-sections -fdata-sections + +CC=arm-elf-gcc +AR=arm-elf-ar +OBJCOPY=arm-elf-objcopy + +OBJ=src/91x_adc.o src/91x_ahbapb.o src/91x_can.o src/91x_dma.o +OBJ+=src/91x_emi.o src/91x_fmi.o src/91x_gpio.o src/91x_i2c.o src/91x_lib.o src/91x_mc.o +OBJ+=src/91x_rtc.o src/91x_scu.o src/91x_ssp.o src/91x_tim.o +OBJ+=src/91x_wdg.o src/91x_wiu.o src/91x_uart.o src/91x_vic.o + + +all: lib + +libandclean: lib srcclean + +lib: $(OBJ) + $(AR) rcs $(LIBNAME) $(OBJ) + +srcclean : + rm -f $(OBJ) + +clean : + rm -f $(OBJ) $(LIBNAME) diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_adc.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_adc.h new file mode 100644 index 0000000..25a396d --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_adc.h @@ -0,0 +1,124 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_adc.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* ADC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef __91x_ADC_H +#define __91x_ADC_H + +/* Includes ------------------------------------------------------------------*/ + +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* ADC Init structure define */ +typedef struct +{ + u16 ADC_WDG_High_Threshold; + u16 ADC_WDG_Low_Threshold; + u16 ADC_Channel_0_Mode; + u16 ADC_Channel_1_Mode; + u16 ADC_Channel_2_Mode; + u16 ADC_Channel_3_Mode; + u16 ADC_Channel_4_Mode; + u16 ADC_Channel_5_Mode; + u16 ADC_Channel_6_Mode; + u16 ADC_Channel_7_Mode; + u16 ADC_Select_Channel; + FunctionalState ADC_Scan_Mode; + u16 ADC_Conversion_Mode; +}ADC_InitTypeDef; + +/* ADC watchdog thresholds */ +typedef enum +{ + ADC_HighThreshold, + ADC_LowThreshold +}ADC_ThresholdType; + +/* Exported constants --------------------------------------------------------*/ + +/* ADC channels */ +#define ADC_Channel_0 0x00 /* Channel 0 */ +#define ADC_Channel_1 0x01 /* Channel 1 */ +#define ADC_Channel_2 0x02 /* Channel 2 */ +#define ADC_Channel_3 0x03 /* Channel 3 */ +#define ADC_Channel_4 0x04 /* Channel 4 */ +#define ADC_Channel_5 0x05 /* Channel 5 */ +#define ADC_Channel_6 0x06 /* Channel 6 */ +#define ADC_Channel_7 0x07 /* Channel 7 */ + +/* ADC modes */ +#define ADC_Continuous_Mode 0x0010 /* Continuous mode conversion */ +#define ADC_Single_Mode 0xFFEF /* Single mode conversion */ + +/* ADC Flags */ +#define ADC_FLAG_ECV 0x002F /* End of Conversion Flag */ +#define ADC_FLAG_AWD 0x002E /* Analog WatchDog Flag */ + +#define ADC_FLAG_OV_CH_0 0x00CF /* Overflow Flag for channel 0 */ +#define ADC_FLAG_OV_CH_1 0x00EF /* Overflow Flag for channel 1 */ +#define ADC_FLAG_OV_CH_2 0x010F /* Overflow Flag for channel 2 */ +#define ADC_FLAG_OV_CH_3 0x012F /* Overflow Flag for channel 3 */ +#define ADC_FLAG_OV_CH_4 0x014F /* Overflow Flag for channel 4 */ +#define ADC_FLAG_OV_CH_5 0x016F /* Overflow Flag for channel 5 */ +#define ADC_FLAG_OV_CH_6 0x018F /* Overflow Flag for channel 6 */ +#define ADC_FLAG_OV_CH_7 0x01AF /* Overflow Flag for channel 7 */ + +/* ADC conversion modes */ +#define ADC_NoThreshold_Conversion 0x0003 /* Conversion w/o thresholds */ +#define ADC_LowThreshold_Conversion 0x0002 /* Low threshold conversion */ +#define ADC_HighThreshold_Conversion 0x0001 /* High threshold conversion */ +#define ADC_No_Conversion 0x0000 /* No ADC conversion */ + +/* ADC interrupts */ +#define ADC_IT_ECV 0x0400 /* End of Conversion Interrupt */ +#define ADC_IT_AWD 0x0200 /* Analog Watchdog Interrupt */ + +/* ADC Start/Stop conversion */ +#define ADC_Conversion_Start 0x0001 /* ADC start conversion */ +#define ADC_Conversion_Stop 0xFFFE /* ADC stop conversion */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void ADC_DeInit(void); +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_PrescalerConfig(u8 ADC_Prescaler); +u8 ADC_GetPrescalerValue(void); +FlagStatus ADC_GetFlagStatus(u16 ADC_Flag); +void ADC_ClearFlag(u16 ADC_Flag); +u16 ADC_GetConversionValue(u16 ADC_Channel); +FlagStatus ADC_GetAnalogWatchdogResult(u16 ADC_Channel); +void ADC_ClearAnalogWatchdogResult(u16 ADC_Channel); +u16 ADC_GetWatchdogThreshold(ADC_ThresholdType ADC_Threshold); +void ADC_ITConfig(u16 ADC_IT, FunctionalState ADC_NewState); +void ADC_StandbyModeCmd(FunctionalState ADC_NewState); +void ADC_Cmd(FunctionalState ADC_NewState); +void ADC_ConversionCmd(u16 ADC_Conversion); + +#endif /* __91x_ADC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_ahbapb.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_ahbapb.h new file mode 100644 index 0000000..1828d48 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_ahbapb.h @@ -0,0 +1,60 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* AHBAPB software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _91x_AHBAPB_H +#define _91x_AHBAPB_H + +#include "91x_map.h" + +#define AHBAPB_Split_Enable 0x01000000 +#define AHBAPB_Split_Disable 0xFEFFFFFF +#define AHBAPB_Error_Enable 0x0000100 +#define AHBAPB_Error_Disable 0xFFFFEFF + +/*FLAG*/ +#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/ +#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */ +#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */ +#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/ + +/* Includes ------------------------------------------------------------------*/ + + +/* AHBAPB Init structure definition */ +typedef struct +{ + u32 AHBAPB_SetTimeOut; + u32 AHBAPB_Error; + u32 AHBAPB_Split; + u8 AHBAPB_SplitCounter; +}AHBAPB_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx); +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct); +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct); +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx); + + +#endif /* _91x_AHBAPB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_can.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_can.h new file mode 100644 index 0000000..b3d0653 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_can.h @@ -0,0 +1,165 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_can.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* CAN bus software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_CAN_H +#define __91x_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* CAN Init structure define */ +typedef struct +{ + u8 CAN_ConfigParameters; + u32 CAN_Bitrate; +}CAN_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Standard bitrates available*/ +enum +{ + CAN_BITRATE_100K, + CAN_BITRATE_125K, + CAN_BITRATE_250K, + CAN_BITRATE_500K, + CAN_BITRATE_1M +}; + +/* Control register*/ +#define CAN_CR_TEST 0x0080 +#define CAN_CR_CCE 0x0040 +#define CAN_CR_DAR 0x0020 +#define CAN_CR_EIE 0x0008 +#define CAN_CR_SIE 0x0004 +#define CAN_CR_IE 0x0002 +#define CAN_CR_INIT 0x0001 + +/* Status register */ +#define CAN_SR_BOFF 0x0080 +#define CAN_SR_EWARN 0x0040 +#define CAN_SR_EPASS 0x0020 +#define CAN_SR_RXOK 0x0010 +#define CAN_SR_TXOK 0x0008 +#define CAN_SR_LEC 0x0007 + +/* Test register*/ +#define CAN_TESTR_RX 0x0080 +#define CAN_TESTR_TX1 0x0040 +#define CAN_TESTR_TX0 0x0020 +#define CAN_TESTR_LBACK 0x0010 +#define CAN_TESTR_SILENT 0x0008 +#define CAN_TESTR_BASIC 0x0004 + +/* IFn / Command Request register*/ +#define CAN_CRR_BUSY 0x8000 + +/* IFn / Command Mask register*/ +#define CAN_CMR_WRRD 0x0080 +#define CAN_CMR_MASK 0x0040 +#define CAN_CMR_ARB 0x0020 +#define CAN_CMR_CONTROL 0x0010 +#define CAN_CMR_CLRINTPND 0x0008 +#define CAN_CMR_TXRQSTNEWDAT 0x0004 +#define CAN_CMR_DATAA 0x0002 +#define CAN_CMR_DATAB 0x0001 + +/* IFn / Mask 2 register*/ +#define CAN_M2R_MXTD 0x8000 +#define CAN_M2R_MDIR 0x4000 + +/* IFn / Arbitration 2 register*/ +#define CAN_A2R_MSGVAL 0x8000 +#define CAN_A2R_XTD 0x4000 +#define CAN_A2R_DIR 0x2000 + +/* IFn / Message Control register*/ +#define CAN_MCR_NEWDAT 0x8000 +#define CAN_MCR_MSGLST 0x4000 +#define CAN_MCR_INTPND 0x2000 +#define CAN_MCR_UMASK 0x1000 +#define CAN_MCR_TXIE 0x0800 +#define CAN_MCR_RXIE 0x0400 +#define CAN_MCR_RMTEN 0x0200 +#define CAN_MCR_TXRQST 0x0100 +#define CAN_MCR_EOB 0x0080 + + +/* Wake-up modes*/ +enum +{ + CAN_WAKEUP_ON_EXT, + CAN_WAKEUP_ON_CAN +}; + + +/* CAN message structure*/ +typedef struct +{ + u32 IdType; + u32 Id; + u8 Dlc; + u8 Data[8]; +} canmsg; + +/* Message ID types*/ +enum +{ + CAN_STD_ID, + CAN_EXT_ID +}; + +/* Message ID limits*/ + +#define CAN_LAST_STD_ID ((1<<11) - 1) +#define CAN_LAST_EXT_ID ((1L<<29) - 1) + +/* Exported functions ------------------------------------------------------- */ + +void CAN_Init (CAN_InitTypeDef *CAN_InitStruct); +void CAN_DeInit (void); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SetBitrate(u32 bitrate); +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj); +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType); +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); +void CAN_InvalidateAllMsgObj(void); +ErrorStatus CAN_ReleaseMessage(u32 msgobj); +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); +ErrorStatus CAN_WaitEndOfTx(void); +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg); +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg); +void CAN_EnterTestMode(u8 TestMask); +void CAN_EnterInitMode(u8 InitMask); +void CAN_LeaveInitMode(void); +void CAN_LeaveTestMode(void); +void CAN_ReleaseTxMessage(u32 msgobj); +void CAN_ReleaseRxMessage(u32 msgobj); +u32 CAN_IsMessageWaiting(u32 msgobj); +u32 CAN_IsTransmitRequested(u32 msgobj); +u32 CAN_IsInterruptPending(u32 msgobj); +u32 CAN_IsObjectValid(u32 msgobj); + +#endif /* __91x_CAN_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_conf.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_conf.h new file mode 100644 index 0000000..a39d57e --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_conf.h @@ -0,0 +1,117 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_conf.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Library configuration. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +#ifndef __91x_CONF_H +#define __91x_CONF_H + +/* To work in buffered mode just decomment the following line */ + +//#define LIBUFF + +/* Comment the line below to put the library in release mode */ +//#define LIBDEBUG + +#define inline static __inline + +/************************* AHBAPB *************************/ +#define _AHBAPB +#define _AHBAPB0 +#define _AHBAPB1 +/************************* VIC *************************/ +#define _VIC +#define _VIC0 +#define _VIC1 +/************************* DMA *************************/ +#define _DMA +#define _DMA_Channel0 +#define _DMA_Channel1 +#define _DMA_Channel2 +#define _DMA_Channel3 +#define _DMA_Channel4 +#define _DMA_Channel5 +#define _DMA_Channel6 +#define _DMA_Channel7 + +/************************* EMI *************************/ +#define _EMI +#define _EMI_Bank0 +#define _EMI_Bank1 +#define _EMI_Bank2 +#define _EMI_Bank3 +/************************* FMI *************************/ +#define _FMI +/************************* WIU *************************/ +#define _WIU +/************************* TIM *************************/ +#define _TIM +#define _TIM0 +#define _TIM1 +#define _TIM2 +#define _TIM3 +/************************* GPIO ************************/ +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 +#define _GPIO3 +#define _GPIO4 +#define _GPIO5 +#define _GPIO6 +#define _GPIO7 +#define _GPIO8 +#define _GPIO9 +/************************* RTC *************************/ +#define _RTC +/************************* SCU *************************/ +#define _SCU +/************************* MC **************************/ +#define _MC +/************************* UART ************************/ +#define _UART +#define _UART0 +#define _UART1 +#define _UART2 +/************************* SSP *************************/ +#define _SSP +#define _SSP0 +#define _SSP1 +/************************* CAN *************************/ +#define _CAN +/************************* ADC *************************/ +#define _ADC +/************************* WDG *************************/ +#define _WDG +/************************* I2C *************************/ +#define _I2C +#define _I2C0 +#define _I2C1 +/************************ ENET *************************/ +#define _ENET + +/*---------------------------- _Main_Crystal frequency value (KHz)------------*/ + +//#ifndef _Main_Crystal +//#define _Main_Crystal 25000 +//#endif +/*------------------------------------------------------------------------------*/ + + +#endif /* __91x_CONF_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_dma.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_dma.h new file mode 100644 index 0000000..6a383aa --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_dma.h @@ -0,0 +1,247 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : template.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : provide a short description of the source file indicating +* its purpose. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_DMA_H +#define __91x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include"91x_map.h" + + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/ + + u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/ + + u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */ + + u32 DMA_Channel_DesWidth; /* Destination transfer width. */ + + u32 DMA_Channel_SrcWidth; /* Source transfer width. */ + + u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/ + + u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */ + + u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/ + + u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */ + + u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */ + + u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */ + +} DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + /* Interrupts masks */ + +#define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */ +#define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/ +#define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/ + + /* Sources Request (used as masks) */ + +#define DMA_USB_RX_Mask 0x0001 +#define DMA_USB_TX_Mask 0x0002 +#define DMA_TIM0_Mask 0x0004 +#define DMA_TIM1_Mask 0x0008 +#define DMA_UART0_RX_Mask 0x0010 +#define DMA_UART0_TX_Mask 0x0020 +#define DMA_UART1_RX_Mask 0x0040 +#define DMA_UART1_TX_Mask 0x0080 +#define DMA_External_Req0_Mask 0x0100 +#define DMA_External_Req1_Mask 0x0200 +#define DMA_I2C0_Mask 0x0400 +#define DMA_I2C1_Mask 0x0800 +#define DMA_SSP0_RX_Mask 0x1000 +#define DMA_SSP0_TX_Mask 0x2000 +#define DMA_SSP1_RX_Mask 0x4000 +#define DMA_SSP1_TX_Mask 0x8000 + + +/* Previleged Mode and user mode */ + +#define DMA_PrevilegedMode 0x10000000 +#define DMA_UserMode 0xEFFFFFFF + + +/* Error and Terminal Count interrupts Status, after and before"raw" masking */ +#define DMA_IS 0x01 +#define DMA_TCS 0x02 +#define DMA_ES 0x03 +#define DMA_TCRS 0x04 +#define DMA_ERS 0x05 + + +/* interrupt clear: Terminal Count flag Clear and Error flag clear*/ + +#define DMA_TCC 0x01 +#define DMA_EC 0x02 + +/* channel index "0...7"*/ + +#define Channel0 0 +#define Channel1 1 +#define Channel2 2 +#define Channel3 3 +#define Channel4 4 +#define Channel5 5 +#define Channel6 6 +#define Channel7 7 + + + +/* Destination request selection: selects the DMA Destination request peripheral */ + +#define DMA_DES_USB_RX 0x00 +#define DMA_DES_USB_TX 0x40 +#define DMA_DES_TIM1 0x80 +#define DMA_DES_TIM2 0xC0 +#define DMA_DES_UART0_RX 0x100 +#define DMA_DES_UART0_TX 0x140 +#define DMA_DES_UART1_RX 0x180 +#define DMA_DES_UART1_TX 0x1C0 +#define DMA_DES_External_Req0 0x200 +#define DMA_DES_External_Req1 0x240 +#define DMA_DES_I2C0 0x280 +#define DMA_DES_I2C1 0x2C0 +#define DMA_DES_SSP0_RX 0x300 +#define DMA_DES_SSP0_TX 0x340 +#define DMA_DES_SSP1_RX 0x380 +#define DMA_DES_SSP1_TX 0x3C0 + + + + +/* Source request selection: selects the DMA Source request peripheral */ + +#define DMA_SRC_USB_RX 0x00 +#define DMA_SRC_USB_TX 0x02 +#define DMA_SRC_TIM1 0x04 +#define DMA_SRC_TIM2 0x06 +#define DMA_SRC_UART0_RX 0x08 +#define DMA_SRC_UART0_TX 0x0A +#define DMA_SRC_UART1_RX 0x0C +#define DMA_SRC_UART1_TX 0x0E +#define DMA_SRC_External_Req0 0x10 +#define DMA_SRC_External_Req1 0x12 +#define DMA_SRC_I2C0 0x14 +#define DMA_SRC_I2C1 0x16 +#define DMA_SRC_SSP0_RX 0x18 +#define DMA_SRC_SSP0_TX 0x1A +#define DMA_SRC_SSP1_RX 0x1C +#define DMA_SRC_SSP1_TX 0x1E + + + + + +#define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */ +#define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */ +#define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */ +#define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */ +#define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */ +#define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */ +#define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */ +#define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */ + + + + +#define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */ +#define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */ +#define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */ +#define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */ +#define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */ +#define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */ +#define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */ +#define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */ + + + + +#define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */ +#define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */ +#define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */ +#define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */ +#define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */ +#define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */ +#define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */ +#define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */ + + + + + +#define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */ +#define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */ +#define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */ + + + + +#define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */ +#define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */ +#define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */ + + + + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void DMA_DeInit(void); +void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(FunctionalState NewState); +void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); +FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ); +ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq); +void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr); +void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState); +FlagStatus DMA_GetSReq(u16 DMA_SrcReq); +FlagStatus DMA_GetLSReq(u16 DMA_SrcReq); +FlagStatus DMA_GetBReq(u16 DMA_SrcReq); +FlagStatus DMA_GetLBReq(u16 DMA_SrcReq); +FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx); +void DMA_SetSReq(u16 DMA_SrcReq); +void DMA_SetLSReq(u16 DMA_SrcReq); +void DMA_SetBReq(u16 DMA_SrcReq); +void DMA_SetLBReq(u16 DMA_SrcReq); +void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode); +void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); +void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); + +#endif /* __91x_DMA_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_emi.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_emi.h new file mode 100644 index 0000000..4633020 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_emi.h @@ -0,0 +1,83 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_emi.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* EMI software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_EMI_H +#define __91x_EMI_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ + typedef struct + { + u32 EMI_Bank_IDCY; + + u32 EMI_Bank_WSTRD; + + u32 EMI_Bank_WSTWR; + + u32 EMI_Bank_WSTROEN; + + u32 EMI_Bank_WSTWEN; + + u32 EMI_Bank_MemWidth ; + + u32 EMI_Bank_WriteProtection; + + u32 EMI_PageModeRead_TransferLength; + + u32 EMI_PageModeRead_Selection; + + } EMI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + +/* page transfer length for page mode read */ +#define EMI_4Data 0x00000000 /*4 transfers burst*/ +#define EMI_8Data 0x00000400 /*8 transfers burst*/ + + +/*Select or deselect the page mode read*/ +#define EMI_NormalMode 0x00000000 /*Normal Mode*/ +#define EMI_PageModeRead 0x00000100 /*Page Mode Read*/ + + +/*memory width*/ +#define EMI_Width_Byte 0x00000000 /*8 bits width*/ +#define EMI_Width_HalfWord 0x00000010 /*16 bits width*/ + +/*Write protection feature */ +#define EMI_Bank_NonWriteProtect 0x00000000 /*No write protection*/ +#define EMI_Bank_WriteProtect 0x00000008 /*bank is write protected*/ + + +/* Exported macro ------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ + +void EMI_DeInit(void); +void EMI_Init( EMI_Bank_TypeDef* EMI_Bankx, EMI_InitTypeDef* EMI_InitStruct); +void EMI_StructInit(EMI_InitTypeDef* EMI_InitStruct); + +#endif /* __EMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_fmi.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_fmi.h new file mode 100644 index 0000000..06e8115 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_fmi.h @@ -0,0 +1,184 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* FMI software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef __91x_FMI_H +#define __91x_FMI_H + +/* ========================================================================== */ +/* When bank 1 is remapped at address 0x0, decomment the following line */ +/* ========================================================================== */ + +//#define Remap_Bank_1 + + +/* Includes ------------------------------------------------------------------*/ + +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* FMI banks */ + +#ifdef Remap_Bank_1 + +#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */ + +#else /* Remap Bank 0 */ + +#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */ + +#endif + +/* FMI sectors */ + +#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */ +#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */ +#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */ +#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */ +#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */ +#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */ +#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */ +#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */ + +#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */ +#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */ +#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */ +#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */ + +/* FMI Flags */ + +#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */ +#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */ +#define FMI_FLAG_PS 0x10 /* Program Status Flag */ +#define FMI_FLAG_ES 0x20 /* Erase Status Flag */ +#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */ +#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */ + +/* FMI read wait states */ + +#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */ +#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */ +#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */ + +/* FMI write wait states */ + +#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */ +#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */ + +/* FMI power down configuration */ + +#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */ +#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */ + +/* FMI low voltage detector */ + +#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */ +#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */ + +/* FMI frequency range */ + +#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */ +#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */ + /* Above 66 MHz*/ +/* FMI OTP word addresses */ + +#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */ +#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */ +#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */ +#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */ +#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */ +#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */ +#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */ +#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */ + +/* FMI OTP halfword addresses */ + +#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */ +#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */ +#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */ +#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */ +#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */ +#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */ +#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */ +#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */ +#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */ +#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */ +#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */ +#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */ +#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */ +#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */ +#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */ +#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */ + +/* FMI sectors Masks */ + +#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */ +#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */ +#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */ +#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */ +#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */ +#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */ +#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */ +#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */ + +#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */ +#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */ +#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */ +#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */ + +/* Timeout error */ + +#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */ +#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress); +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange); +void FMI_EraseSector(vu32 FMI_Sector); +void FMI_EraseBank(vu32 FMI_Bank); +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data); +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData); +u32 FMI_ReadWord(u32 FMI_Address); +u32 FMI_ReadOTPData(u8 FMI_OTPAddress); +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank); +u16 FMI_GetReadWaitStateValue(void); +u16 FMI_GetWriteWaitStateValue(void); +void FMI_SuspendEnable(vu32 FMI_Bank); +void FMI_ResumeEnable(vu32 FMI_Bank); +void FMI_ClearFlag(vu32 FMI_Bank); +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState); +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection); +u8 FMI_WaitForLastOperation(vu32 FMI_Bank); + +#endif /* __91x_FMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_gpio.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_gpio.h new file mode 100644 index 0000000..f4e5658 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_gpio.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef _91x_GPIO_H +#define _91x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* GPIO Init structure definition */ +typedef struct +{ + u8 GPIO_Pin; + u8 GPIO_Direction; + u8 GPIO_Type; + u8 GPIO_IPConnected; + u16 GPIO_Alternate; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + + +/* Exported constants --------------------------------------------------------*/ +#define GPIO_Pin_None 0x00 +#define GPIO_Pin_0 0x01 +#define GPIO_Pin_1 0x02 +#define GPIO_Pin_2 0x04 +#define GPIO_Pin_3 0x08 +#define GPIO_Pin_4 0x10 +#define GPIO_Pin_5 0x20 +#define GPIO_Pin_6 0x40 +#define GPIO_Pin_7 0x80 +#define GPIO_Pin_All 0xFF + +#define GPIO_PinInput 0x00 +#define GPIO_PinOutput 0x01 + +#define GPIO_Type_PushPull 0x00 +#define GPIO_Type_OpenCollector 0x01 + +#define GPIO_IPConnected_Disable 0x00 +#define GPIO_IPConnected_Enable 0x01 + +#define GPIO_InputAlt1 0x00 +#define GPIO_OutputAlt1 0x01 +#define GPIO_OutputAlt2 0x02 +#define GPIO_OutputAlt3 0x03 + +#define GPIO_ANAChannel0 0x01 +#define GPIO_ANAChannel1 0x02 +#define GPIO_ANAChannel2 0x04 +#define GPIO_ANAChannel3 0x08 +#define GPIO_ANAChannel4 0x10 +#define GPIO_ANAChannel5 0x20 +#define GPIO_ANAChannel6 0x40 +#define GPIO_ANAChannel7 0x80 +#define GPIO_ANAChannelALL 0xFF + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin); +u8 GPIO_Read(GPIO_TypeDef* GPIOx); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal); +void GPIO_EMIConfig(FunctionalState NewState); +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState); + +#endif /* _91x_GPIO_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_i2c.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_i2c.h new file mode 100644 index 0000000..f4d0c66 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_i2c.h @@ -0,0 +1,112 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_i2c.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* I2C software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_I2C_H +#define __91x_I2C_H + +/* Includes ----------------------------------------------------------------- */ +#include "91x_map.h" + +/* Exported types ----------------------------------------------------------- */ +/* I2C Init structure definition */ +typedef struct +{ + u32 I2C_CLKSpeed; + u16 I2C_OwnAddress; + u8 I2C_GeneralCall; + u8 I2C_Ack; +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +#define I2C_GeneralCall_Enable 0x10 +#define I2C_GeneralCall_Disable 0xEF +/* Acknowledgement */ +#define I2C_Ack_Enable 0x04 +#define I2C_Ack_Disable 0xFB + +/* I2C Flags */ +#define I2C_FLAG_SB 0x0001 +#define I2C_FLAG_M_SL 0x0002 +#define I2C_FLAG_ADSL 0x0004 +#define I2C_FLAG_BTF 0x0008 +#define I2C_FLAG_BUSY 0x0010 +#define I2C_FLAG_TRA 0x0020 +#define I2C_FLAG_ADD10 0x0040 +#define I2C_FLAG_EVF 0x0080 +#define I2C_FLAG_GCAL 0x0100 +#define I2C_FLAG_BERR 0x0200 +#define I2C_FLAG_ARLO 0x0400 +#define I2C_FLAG_STOPF 0x0800 +#define I2C_FLAG_AF 0x1000 +#define I2C_FLAG_ENDAD 0x2000 +#define I2C_FLAG_ACK 0x4000 + +/* I2C Events */ +#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_ADSL) +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF ) +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB ) +#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD ) +#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF ) +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 ) +#define I2C_EVENT_SLAVE_STOP_DETECTED I2C_FLAG_STOPF +#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF) + +#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR +#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO +#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL) + +/* Master/Receiver Mode */ +#define I2C_MODE_TRANSMITTER 0x00 +#define I2C_MODE_RECEIVER 0x01 + +/* I2C Registers offset */ +#define I2C_CR 0x00 +#define I2C_SR1 0x04 +#define I2C_SR2 0x08 +#define I2C_CCR 0x0C +#define I2C_OAR1 0x10 +#define I2C_OAR2 0x14 +#define I2C_DR 0x18 +#define I2C_ECCR 0x1C + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateStart(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 Direction); +u8 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u16 I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u16 I2C_FLAG, ...); +void I2C_SendData(I2C_TypeDef* I2Cx, u8 bData); +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx); +u16 I2C_GetLastEvent(I2C_TypeDef* I2Cx); +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,u16 I2C_Event); + +#endif /* __91x_I2C_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_it.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_it.h new file mode 100644 index 0000000..a8e35fc --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_it.h @@ -0,0 +1,73 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_it.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains the headers of the interrupt +* handlers'routines +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef _91x_IT_H +#define _91x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void Undefined_Handler (void); +void SWI_Handler (void); +void Prefetch_Handler (void); +void Abort_Handler (void); +void FIQ_Handler (void); +void WDG_IRQHandler (void); +void SW_IRQHandler (void); +void ARMRX_IRQHandler (void); +void ARMTX_IRQHandler (void); +void TIM0_IRQHandler (void); +void TIM1_IRQHandler (void); +void TIM2_IRQHandler (void); +void TIM3_IRQHandler (void); +void USBHP_IRQHandler (void); +void USBLP_IRQHandler (void); +void SCU_IRQHandler (void); +void ENET_IRQHandler (void); +void DMA_IRQHandler (void); +void CAN_IRQHandler (void); +void MC_IRQHandler (void); +void ADC_IRQHandler (void); +void UART0_IRQHandler (void); +void UART1_IRQHandler (void); +void UART2_IRQHandler (void); +void I2C0_IRQHandler (void); +void I2C1_IRQHandler (void); +void SSP0_IRQHandler (void); +void SSP1_IRQHandler (void); +void LVD_IRQHandler (void); +void RTC_IRQHandler (void); +void WIU_IRQHandler (void); +void EXTIT0_IRQHandler (void); +void EXTIT1_IRQHandler (void); +void EXTIT2_IRQHandler (void); +void EXTIT3_IRQHandler (void); +void USBWU_IRQHandler (void); +void PFQBC_IRQHandler (void); + +#endif /* _91x_IT_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_lib.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_lib.h new file mode 100644 index 0000000..3df7ced --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_lib.h @@ -0,0 +1,113 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Used to include the peripherals header file in the +* user application. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __91x_LIB_H +#define __91x_LIB_H + +#include "91x_map.h" +#include "91x_conf.h" + +#ifdef _AHBAPB + #include "91x_ahbapb.h" +#endif /* _AHBAPB */ + +#ifdef _EMI + #include "91x_emi.h" +#endif /* _EMI */ + +#ifdef _DMA + #include "91x_dma.h" +#endif /* _DMA */ + +#ifdef _FMI + #include "91x_fmi.h" +#endif /* _FMI */ + +#ifdef _VIC + #include "91x_vic.h" +#endif /* _VIC */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif /* _WIU */ + +#ifdef _TIM + #include "91x_tim.h" +#endif /* _TIM */ + +#ifdef _GPIO + #include "91x_gpio.h" +#endif /* _GPIO */ + +#ifdef _RTC + #include "91x_rtc.h" +#endif /* _RTC */ + +#ifdef _SCU + #include "91x_scu.h" +#endif /* _SCU */ + +#ifdef _UART + #include "91x_uart.h" +#endif /* _UART */ + +#ifdef _SSP + #include "91x_ssp.h" +#endif /* _SSP */ + +#ifdef _CAN + #include "91x_can.h" +#endif /* _CAN */ + +#ifdef _ADC + #include "91x_adc.h" +#endif /* _ADC */ + +#ifdef _WDG + #include "91x_wdg.h" +#endif /* _WDG */ + +#ifdef _I2C + #include "91x_i2c.h" +#endif /* _I2C */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif + +#ifdef _MC + #include "91x_mc.h" +#endif + +#ifdef _ENET +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + void libdebug( void ); + + +#endif /* __91x_LIB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_map.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_map.h new file mode 100644 index 0000000..5fe67cf --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_map.h @@ -0,0 +1,878 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_map.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Peripherals registers definition and memory mapping. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_MAP_H +#define __91x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_conf.h" +#include "91x_type.h" + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------------------ FMI -----------------------------------*/ + +typedef struct +{ + vu32 BBSR; /* Boot Bank Size Register */ + vu32 NBBSR; /* Non-Boot Bank Size Register */ + vu32 EMPTY1; + vu32 BBADR; /* Boot Bank Base Address Register */ + vu32 NBBADR; /* Non-Boot Bank Base Address Register */ + vu32 EMPTY2; + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */ +} FMI_TypeDef; + +/*---------------------- Analog to Digital Convertor ------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 CCR; /* Channel Configuration Register */ + vu16 EMPTY2; + vu16 HTR; /* Higher Threshold Register */ + vu16 EMPTY3; + vu16 LTR; /* Lower Threshold Register */ + vu16 EMPTY4; + vu16 CRR; /* Compare Result Register */ + vu16 EMPTY5; + vu16 DR0; /* Data Register for Channel 0 */ + vu16 EMPTY6; + vu16 DR1; /* Data Register for Channel 1 */ + vu16 EMPTY7; + vu16 DR2; /* Data Register for Channel 2 */ + vu16 EMPTY8; + vu16 DR3; /* Data Register for Channel 3 */ + vu16 EMPTY9; + vu16 DR4; /* Data Register for Channel 4 */ + vu16 EMPTY10; + vu16 DR5; /* Data Register for Channel 5 */ + vu16 EMPTY11; + vu16 DR6; /* Data Register for Channel 6 */ + vu16 EMPTY12; + vu16 DR7; /* Data Register for Channel 7 */ + vu16 EMPTY13; + vu16 PRS; /* Prescaler Value Register */ + vu16 EMPTY14; +} ADC_TypeDef; + +/*--------------------- AHB APB BRIDGE registers strcture --------------------*/ + +typedef struct +{ + vu32 BSR; /* Bridge Status Register */ + vu32 BCR; /* Bridge Configuration Register */ + vu32 PAER; /* Peripheral Address Error register */ +} AHBAPB_TypeDef; + +/*--------------- Controller Area Network Interface Register -----------------*/ + +typedef struct +{ + vu16 CRR; /* IFn Command request Register */ + vu16 EMPTY1; + vu16 CMR; /* IFn Command Mask Register */ + vu16 EMPTY2; + vu16 M1R; /* IFn Message Mask 1 Register */ + vu16 EMPTY3; + vu16 M2R; /* IFn Message Mask 2 Register */ + vu16 EMPTY4; + vu16 A1R; /* IFn Message Arbitration 1 Register */ + vu16 EMPTY5; + vu16 A2R; /* IFn Message Arbitration 2 Register */ + vu16 EMPTY6; + vu16 MCR; /* IFn Message Control Register */ + vu16 EMPTY7; + vu16 DA1R; /* IFn DATA A 1 Register */ + vu16 EMPTY8; + vu16 DA2R; /* IFn DATA A 2 Register */ + vu16 EMPTY9; + vu16 DB1R; /* IFn DATA B 1 Register */ + vu16 EMPTY10; + vu16 DB2R; /* IFn DATA B 2 Register */ + vu16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 SR; /* Status Register */ + vu16 EMPTY2; + vu16 ERR; /* Error counter Register */ + vu16 EMPTY3; + vu16 BTR; /* Bit Timing Register */ + vu16 EMPTY4; + vu16 IDR; /* Interrupt Identifier Register */ + vu16 EMPTY5; + vu16 TESTR; /* Test Register */ + vu16 EMPTY6; + vu16 BRPR; /* BRP Extension Register */ + vu16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + vu16 EMPTY8[16]; + vu16 TXR1R; /* Transmission request 1 Register */ + vu16 EMPTY9; + vu16 TXR2R; /* Transmission Request 2 Register */ + vu16 EMPTY10[13]; + vu16 ND1R; /* New Data 1 Register */ + vu16 EMPTY11; + vu16 ND2R; /* New Data 2 Register */ + vu16 EMPTY12[13]; + vu16 IP1R; /* Interrupt Pending 1 Register */ + vu16 EMPTY13; + vu16 IP2R; /* Interrupt Pending 2 Register */ + vu16 EMPTY14[13]; + vu16 MV1R; /* Message Valid 1 Register */ + vu16 EMPTY15; + vu16 MV2R; /* Message VAlid 2 Register */ + vu16 EMPTY16; +} CAN_TypeDef; + +/*----------------------- System Control Unit---------------------------------*/ + +typedef struct +{ + vu32 CLKCNTR; /* Clock Control Register */ + vu32 PLLCONF; /* PLL Configuration Register */ + vu32 SYSSTATUS; /* System Status Register */ + vu32 PWRMNG; /* Power Management Register */ + vu32 ITCMSK; /* Interrupt Mask Register */ + vu32 PCGRO; /* Peripheral Clock Gating Register 0 */ + vu32 PCGR1; /* Peripheral Clock Gating Register 1 */ + vu32 PRR0; /* Peripheral Reset Register 0 */ + vu32 PRR1; /* Peripheral Reset Register 1 */ + vu32 MGR0; /* Idle Mode Mask Gating Register 0 */ + vu32 MGR1; /* Idle Mode Mask Gating Register 1 */ + vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */ + vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */ + vu32 SCR0; /* System Configuration Register 0 */ + vu32 SCR1; /* System Configuration Register 1 */ + vu32 SCR2; /* System Configuration Register 2 */ + u32 EMPTY1; + vu32 GPIOOUT[8]; /* GPIO Output Registers */ + vu32 GPIOIN[8]; /* GPIO Input Registers */ + vu32 GPIOTYPE[10]; /* GPIO Type Registers */ + vu32 GPIOEMI; /* GPIO EMI Selector Register */ + vu32 WKUPSEL; /* Wake-Up Selection Register */ + u32 EMPTY2[2]; + vu32 GPIOANA; /* GPIO Analag mode Register */ +} SCU_TypeDef; + +/*------------------------- DMA Channelx Registers ---------------------------*/ + +typedef struct +{ + vu32 SRC; /* Channelx Source Address Register */ + vu32 DES; /* Channelx Destination Address Register */ + vu32 LLI; /* Channelx Lincked List Item Register */ + vu32 CC; /* Channelx Contol Register */ + vu32 CCNF; /* Channelx Configuration Register */ +} DMA_Channel_TypeDef; + +/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */ + +/*----------------------------- DMA Controller -------------------------------*/ + +typedef struct +{ + vu32 ISR; /* Interrupt Status Register */ + vu32 TCISR; /* Terminal Count Interrupt Status Register */ + vu32 TCICR; /* Terminal CountInterrupt Clear Register */ + vu32 EISR; /* Error Interrupt Status Register */ + vu32 EICR; /* Error Interrupt Clear Register */ + vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */ + vu32 ERISR; /* Raw Error Interrupt Status Register */ + vu32 ENCSR; /* Enabled Channel Status Register */ + vu32 SBRR; /* Software Burst Request Register */ + vu32 SSRR; /* Software Single Request Register */ + vu32 SLBRR; /* Software Last Burst Request Register */ + vu32 SLSRR; /* Software Last Single Request Register */ + vu32 CNFR; /* Configuration Register */ + vu32 SYNR; /* Syncronization Register */ +} DMA_TypeDef; + +/*--------------------------------- TIM Timer --------------------------------*/ + +typedef struct +{ + vu16 IC1R; /* Input Capture 1 Register */ + vu16 EMPTY1; + vu16 IC2R; /* Input Capture 2 Register */ + vu16 EMPTY2; + vu16 OC1R; /* Output Compare 1 Register */ + vu16 EMPTY3; + vu16 OC2R; /* Output Compare 2 Register */ + vu16 EMPTY4; + vu16 CNTR; /* Counter Register */ + vu16 EMPTY5; + vu16 CR1; /* Control Register 1 */ + vu16 EMPTY6; + vu16 CR2; /* Control Register 2 */ + vu16 EMPTY7; + vu16 SR; /* Status Register */ + vu16 EMPTY8; +} TIM_TypeDef; + +/*---------------------------- EMI Bankx Registers ---------------------------*/ + +typedef struct +{ + vu32 ICR; /* Bankx Idle Cycle Control Register */ + vu32 RCR; /* Bankx Read Wait State Control Register */ + vu32 WCR; /* Bankx Write Wait State Control Register */ + vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */ + vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */ + vu32 BCR; /* Bankx Control Register */ + } EMI_Bank_TypeDef; + +/*---------------------------- Ethernet Controller ---------------------------*/ + +/* MAC Registers */ +typedef struct +{ + vu32 MCR; /* ENET Control Register */ + vu32 MAH; /* ENET Address High Register */ + vu32 MAL; /* ENET Address Low Register */ + vu32 MCHA; /* Multicast Address High Register */ + vu32 MCLA; /* Multicast Address Low Register */ + vu32 MIIA; /* MII Address Register */ + vu32 MIID; /* MII Data Register */ + vu32 MCF; /* ENET Control Frame Register */ + vu32 VL1; /* VLAN1 Register */ + vu32 VL2; /* VLAN2 register */ + vu32 MTS; /* ENET Transmission Status Register */ + vu32 MRS; /* ENET Reception Status Register */ +} ENET_MAC_TypeDef; + +/* DMA Registers */ +typedef struct +{ + vu32 SCR; /* DMA Status and Control Register */ + vu32 IER; /* DMA Interrupt Sources Enable Register */ + vu32 ISR; /* DMA Interrupt Status Register */ + vu32 CCR; /* Clock Control Relation : HCLK, PCLK and + ENET_CLK phase relations */ + vu32 RXSTR; /* Rx DMA start Register */ + vu32 RXCR; /* Rx DMA Control Register */ + vu32 RXSAR; /* Rx DMA Base Address Register */ + vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */ + vu32 RXCAR; /* Rx DMA Current Address Register */ + vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */ + vu32 RXTOR; /* Rx DMA FIFO Time Out Register */ + vu32 RXSR; /* Rx DMA FIFO Status Register */ + vu32 TXSTR; /* Tx DMA start Register */ + vu32 TXCR; /* Tx DMA Control Register */ + vu32 TXSAR; /* Tx DMA Base Address Register */ + vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */ + vu32 TXCAR; /* Tx DMA Current Address Register */ + vu32 TXTCR; /* Tx DMA Current Transfer Count Register */ + vu32 TXTOR; /* Tx DMA FIFO Time Out Register */ + vu32 TXSR; /* Tx DMA FIFO Status Register */ +} ENET_DMA_TypeDef; + +/*------------------------------------- GPIO ---------------------------------*/ + +typedef struct +{ + vu8 DR[1021]; /* Data Register */ + vu32 DDR; /* Data Direction Register */ +} GPIO_TypeDef; + +/*-------------------------------- I2C interface -----------------------------*/ + +typedef struct +{ + vu8 CR; /* Control Register */ + vu8 EMPTY1[3]; + vu8 SR1; /* Status Register 1 */ + vu8 EMPTY2[3]; + vu8 SR2; /* Status Register 2 */ + vu8 EMPTY3[3]; + vu8 CCR; /* Clock Control Register */ + vu8 EMPTY4[3]; + vu8 OAR1; /* Own Address Register 1 */ + vu8 EMPTY5[3]; + vu8 OAR2; /* Own Address Register 2 */ + vu8 EMPTY6[3]; + vu8 DR; /* Data Register */ + vu8 EMPTY7[3]; + vu8 ECCR; /* Extended Clock Control Register */ + vu8 EMPTY8[3]; +} I2C_TypeDef; + +/*------------------------------------- VIC ----------------------------------*/ + +typedef struct +{ + vu32 ISR; /* IRQ Status Register */ + vu32 FSR; /* FIQ Status Register */ + vu32 RINTSR; /* Raw Interrupt Status Register */ + vu32 INTSR; /* Interrupt Select Register */ + vu32 INTER; /* Interrupt Enable Register */ + vu32 INTECR; /* Interrupt Enable Clear Register */ + vu32 SWINTR; /* Software Interrupt Register */ + vu32 SWINTCR; /* Software Interrupt clear Register */ + vu32 PER; /* Protection Enable Register */ + vu32 EMPTY1[3]; + vu32 VAR; /* Vector Address Register */ + vu32 DVAR; /* Default Vector Address Register */ + vu32 EMPTY2[50]; + vu32 VAiR[16]; /* Vector Address 0-15 Register */ + vu32 EMPTY3[48]; + vu32 VCiR[16]; /* Vector Control 0-15 Register */ +} VIC_TypeDef; + +/*-------------------------------- Motor Control -----------------------------*/ + +typedef struct +{ + vu16 TCPT; /* Tacho Capture Register */ + vu16 EMPTY1; + vu16 TCMP; /* Tacho Compare Register */ + vu16 EMPTY2; + vu16 IPR; /* Input Pending Register */ + vu16 EMPTY3; + vu16 TPRS; /* Tacho Prescaler Register */ + vu16 EMPTY4; + vu16 CPRS; /* PWM Counter Prescaler Register */ + vu16 EMPTY5; + vu16 REP; /* Repetition Counter Register */ + vu16 EMPTY6; + vu16 CMPW; /* Compare Phase W Preload Register */ + vu16 EMPTY7; + vu16 CMPV; /* Compare Phase V Preload Register */ + vu16 EMPTY8; + vu16 CMPU; /* Compare Phase U Preload Register */ + vu16 EMPTY9; + vu16 CMP0; /* Compare 0 Preload Register */ + vu16 EMPTY10; + vu16 PCR0; /* Peripheral Control Register 0 */ + vu16 EMPTY11; + vu16 PCR1; /* Peripheral Control Register 1 */ + vu16 EMPTY12; + vu16 PCR2; /* Peripheral Control Register 2 */ + vu16 EMPTY13; + vu16 PSR; /* Polarity Selection Register */ + vu16 EMPTY14; + vu16 OPR; /* Output Peripheral Register */ + vu16 EMPTY15; + vu16 IMR; /* Interrupt Mask Register */ + vu16 EMPTY16; + vu16 DTG; /* Dead Time Generator Register */ + vu16 EMPTY17; + vu16 ESC; /* Emergency Stop Clear Register */ + vu16 EMPTY18; +}MC_TypeDef; + +/*------------------------------------- RTC ----------------------------------*/ + +typedef struct +{ + vu32 TR; /* Time Register */ + vu32 DTR; /* Date Register */ + vu32 ATR; /* Alarm time Register */ + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 MILR; /* Millisec Register */ +}RTC_TypeDef; + +/*------------------------------------- SSP ----------------------------------*/ + +typedef struct +{ + vu16 CR0; /* Control Register 1 */ + vu16 EMPTY1; + vu16 CR1; /* Control Register 2 */ + vu16 EMPTY2; + vu16 DR; /* Data Register */ + vu16 EMPTY3; + vu16 SR; /* Status Register */ + vu16 EMPTY4; + vu16 PR; /* Clock Prescale Register */ + vu16 EMPTY5; + vu16 IMSCR; /* Interrupt Mask Set or Clear Register */ + vu16 EMPTY6; + vu16 RISR; /* Raw Interrupt Status Register */ + vu16 EMPTY7; + vu16 MISR; /* Masked Interrupt Status Register */ + vu16 EMPTY8; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY9; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY10; +}SSP_TypeDef; + +/*------------------------------------ UART ----------------------------------*/ + +typedef struct +{ + vu16 DR; /* Data Register */ + vu16 EMPTY1; + vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */ + vu16 EMPTY2[9]; + vu16 FR; /* Flag Register */ + vu16 EMPTY3[3]; + vu16 ILPR; /* IrDA Low-Power counter Register */ + vu16 EMPTY4; + vu16 IBRD; /* Integer Baud Rate Divisor Register */ + vu16 EMPTY5; + vu16 FBRD; /* Fractional Baud Rate Divisor Register */ + vu16 EMPTY6; + vu16 LCR; /* Line Control Register, High byte */ + vu16 EMPTY7; + vu16 CR; /* Control Register */ + vu16 EMPTY8; + vu16 IFLS; /* Interrupt FIFO Level Select Register */ + vu16 EMPTY9; + vu16 IMSC; /* Interrupt Mask Set/Clear Register */ + vu16 EMPTY10; + vu16 RIS; /* Raw Interrupt Status Register */ + vu16 EMPTY11; + vu16 MIS; /* Masked Interrupt Status Register */ + vu16 EMPTY12; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY13; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY14; +}UART_TypeDef; + +/*------------------------------- Wake-up System -----------------------------*/ + +typedef struct +{ + vu32 CTRL; /* Control Register */ + vu32 MR; /* Mask Register */ + vu32 TR; /* Trigger Register */ + vu32 PR; /* Pending Register */ + vu32 INTR; /* Software Interrupt Register */ +} WIU_TypeDef; + +/*------------------------------- WatchDog Timer -----------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 PR; /* Presclar Register */ + vu16 EMPTY2; + vu16 VR; /* Pre-load Value Register */ + vu16 EMPTY3; + vu16 CNT; /* Counter Register */ + vu16 EMPTY4; + vu16 SR; /* Status Register */ + vu16 EMPTY5; + vu16 MR; /* Mask Register */ + vu16 EMPTY6; + vu16 KR; /* Key Register */ + vu16 EMPTY7; +} WDG_TypeDef; + +/******************************************************************************* +* Memory Mapping of STR91x * +*******************************************************************************/ + +#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */ +#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */ + +#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */ +#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */ + +#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */ +#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */ + +#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */ +#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */ + +#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */ +#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */ + +#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */ +#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */ + +#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */ +#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */ + +#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */ +#define AHB_FMI_B (0x44000000) /* FMI buffered Space */ + +/******************************************************************************* +* Addresses related to the VICs' peripherals * +*******************************************************************************/ + +#define VIC0_BASE (AHB_VIC0_U) +#define VIC1_BASE (AHB_VIC1_U) + +/******************************************************************************* +* Addresses related to the EMI banks * +*******************************************************************************/ + +#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */ +#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */ +#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */ +#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */ + +/******************************************************************************* +* Addresses related to the DMA peripheral * +*******************************************************************************/ + +#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */ +#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */ +#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */ +#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */ +#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */ +#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */ +#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */ +#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */ + +/******************************************************************************* +* Addresses related to the APB0 sub-system * +*******************************************************************************/ + +#define APB_WIU_OFST (0x00001000) /* Offset of WIU */ +#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */ +#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */ +#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */ +#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */ +#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */ +#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */ +#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */ +#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */ +#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */ +#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */ +#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */ +#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */ +#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */ +#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */ + +/******************************************************************************* +* Addresses related to the APB1 sub-system * +*******************************************************************************/ + +#define APB_RTC_OFST (0x00001000) /* Offset of RTC */ +#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */ +#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */ +#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */ +#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */ +#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */ +#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */ +#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */ +#define APB_CAN_OFST (0x00009000) /* Offset of CAN */ +#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */ +#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */ +#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */ +#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */ + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Unbuffered Mode ------------------------------*/ +/*----------------------------------------------------------------------------*/ + +#ifndef LIBUFF + +/******************************************************************************* +* AHBAPB peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_U) +#define AHBAPB1_BASE (AHB_APB_BRDG1_U) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_U) +#define ENET_DMA_BASE (AHB_ENET_DMA_U) + +/******************************************************************************* +* DMA peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_U) + +/******************************************************************************* +* EMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_U) + +/******************************************************************************* +* FMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_U) + + +#else /* LIBUFF */ + +/*----------------------------------------------------------------------------*/ +/*------------------------------ Buffered Mode -------------------------------*/ +/*----------------------------------------------------------------------------*/ + +/******************************************************************************* +* AHBAPB peripheral Buffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_B) +#define AHBAPB1_BASE (AHB_APB_BRDG1_B) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_B) +#define ENET_DMA_BASE (AHB_ENET_DMA_B) + +/******************************************************************************* +* DMA peripheral Buffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_B) + +/******************************************************************************* +* EMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_B) + +/******************************************************************************* +* FMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_B) + +#endif /* LIBUFF */ + +/******************************************************************************* +* DMA channels Base Address * +*******************************************************************************/ +#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST) +#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST) +#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST) +#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST) +#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST) +#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST) +#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST) +#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST) + +/******************************************************************************* +* EMI Banks peripheral Base Address * +*******************************************************************************/ + +#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST) +#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST) +#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST) +#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST) + +/******************************************************************************* +* APB0 Peripherals' Base addresses * +*******************************************************************************/ + +#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST) +#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST) +#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST) +#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST) +#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST) +#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST) +#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST) +#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST) +#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST) +#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST) +#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST) +#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST) +#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST) +#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST) +#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST) + +/******************************************************************************* +* APB1 Peripherals' Base addresses * +*******************************************************************************/ + +#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST) +#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST) +#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST) +#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST) +#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST) +#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST) +#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST) +#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST) +#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST) +#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST) +#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST) +#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST) +#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST) + +/******************************************************************************* +* IPs' declaration * +*******************************************************************************/ + +/*------------------------------ Non Debug Mode ------------------------------*/ + +#ifndef LIBDEBUG + +/*********************************** AHBAPB ***********************************/ + +#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE) +#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE) + +/************************************* EMI ************************************/ + +#define EMI ((EMI_TypeDef *)EMI_BASE) + +/************************************* DMA ************************************/ + +#define DMA ((DMA_TypeDef *)DMA_BASE) +#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) +#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) +#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) +#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) +#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) +#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE) +#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE) +#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE) + +/************************************* EMI ************************************/ + +#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE) +#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE) +#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE) +#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE) + +/************************************* ENET_MAC ************************************/ + +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) + +/************************************* ENET_DMA ************************************/ + +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +/************************************* FMI ************************************/ + +#define FMI ((FMI_TypeDef *)FMI_BASE) + +/************************************* VIC ************************************/ + +#define VIC0 ((VIC_TypeDef *)VIC0_BASE) +#define VIC1 ((VIC_TypeDef *)VIC1_BASE) + +/******************************************************************************* +* APB0 Peripherals' * +*******************************************************************************/ +#define WIU ((WIU_TypeDef *)WIU_BASE) +#define TIM0 ((TIM_TypeDef *)TIM0_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) +#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) +#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) +#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE) +#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE) +#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE) +#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE) +#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE) +#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE) +#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE) +/******************************************************************************* +* APB1 Peripherals' * +*******************************************************************************/ +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define SCU ((SCU_TypeDef *)SCU_BASE) +#define MC ((MC_TypeDef *)MC_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define SSP0 ((SSP_TypeDef *)SSP0_BASE) +#define SSP1 ((SSP_TypeDef *)SSP1_BASE) +#define CAN ((CAN_TypeDef *)CAN_BASE) +#define ADC ((ADC_TypeDef *)ADC_BASE) +#define WDG ((WDG_TypeDef *)WDG_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +#else /* LIBDEBUG */ + +/*-------------------------------- Debug Mode --------------------------------*/ + +EXT AHBAPB_TypeDef *AHBAPB0; +EXT AHBAPB_TypeDef *AHBAPB1; +EXT DMA_TypeDef *DMA; +EXT DMA_Channel_TypeDef *DMA_Channel0; +EXT DMA_Channel_TypeDef *DMA_Channel1; +EXT DMA_Channel_TypeDef *DMA_Channel2; +EXT DMA_Channel_TypeDef *DMA_Channel3; +EXT DMA_Channel_TypeDef *DMA_Channel4; +EXT DMA_Channel_TypeDef *DMA_Channel5; +EXT DMA_Channel_TypeDef *DMA_Channel6; +EXT DMA_Channel_TypeDef *DMA_Channel7; +EXT EMI_Bank_TypeDef *EMI_Bank0; +EXT EMI_Bank_TypeDef *EMI_Bank1; +EXT EMI_Bank_TypeDef *EMI_Bank2; +EXT EMI_Bank_TypeDef *EMI_Bank3; +EXT FMI_TypeDef *FMI; +EXT VIC_TypeDef *VIC0; +EXT VIC_TypeDef *VIC1; +EXT WIU_TypeDef *WIU; +EXT TIM_TypeDef *TIM0; +EXT TIM_TypeDef *TIM1; +EXT TIM_TypeDef *TIM2; +EXT TIM_TypeDef *TIM3; +EXT GPIO_TypeDef *GPIO0; +EXT GPIO_TypeDef *GPIO1; +EXT GPIO_TypeDef *GPIO2; +EXT GPIO_TypeDef *GPIO3; +EXT GPIO_TypeDef *GPIO4; +EXT GPIO_TypeDef *GPIO5; +EXT GPIO_TypeDef *GPIO6; +EXT GPIO_TypeDef *GPIO7; +EXT GPIO_TypeDef *GPIO8; +EXT GPIO_TypeDef *GPIO9; +EXT RTC_TypeDef *RTC; +EXT SCU_TypeDef *SCU; +EXT MC_TypeDef *MC; +EXT UART_TypeDef *UART0; +EXT UART_TypeDef *UART1; +EXT UART_TypeDef *UART2; +EXT SSP_TypeDef *SSP0; +EXT SSP_TypeDef *SSP1; +EXT CAN_TypeDef *CAN; +EXT ADC_TypeDef *ADC; +EXT WDG_TypeDef *WDG; +EXT I2C_TypeDef *I2C0; +EXT I2C_TypeDef *I2C1; +EXT ENET_MAC_TypeDef *ENET_MAC; +EXT ENET_DMA_TypeDef *ENET_DMA; + + +#endif /* LIBDEBUG */ + +#endif /* __91x_MAP_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_mc.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_mc.h new file mode 100644 index 0000000..b33b7c3 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_mc.h @@ -0,0 +1,144 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_mc.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* MC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_MC_H +#define __91x_MC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u16 MC_OperatingMode; + u16 MC_TachoMode; + u16 MC_TachoEvent_Mode; + u8 MC_Prescaler; + u8 MC_ForcedPWMState; + u16 MC_TachoPrescaler; + u16 MC_PWMMode; + u16 MC_Complementary; + u16 MC_Emergency; + u16 MC_Period; + u16 MC_TachoPeriod; + u16 MC_Channel; + u16 MC_PulseU; + u16 MC_PulseV; + u16 MC_PulseW; + u16 MC_PolarityUL; + u16 MC_PolarityUH; + u16 MC_PolarityVL; + u16 MC_PolarityVH; + u16 MC_PolarityWL; + u16 MC_PolarityWH; + u16 MC_TachoPolarity; + u16 MC_DeadTime; + u8 MC_RepetitionCounter; +} MC_InitTypeDef; + +typedef enum { DOWN = 0, UP = !DOWN} CountingStatus; + +/* Exported constants --------------------------------------------------------*/ +#define MC_Complementary_Enable 0x0001 +#define MC_Complementary_Disable 0x0002 + +#define MC_HardwareOperating_Mode 0x0001 +#define MC_SoftwareOperating_Mode 0x0002 + +#define MC_PWMClassical_Mode 0x0001 +#define MC_PWMZeroCentered_Mode 0x0002 + +#define MC_Emergency_Enable 0x0001 +#define MC_Emergency_Disable 0x0002 + +#define MC_Polarity_Inverted 0x0001 +#define MC_Polarity_NonInverted 0x0002 + +#define MC_TachoOneShot_Mode 0x0001 +#define MC_TachoContinuous_Mode 0x0002 + +#define MC_TachoEventEdge_None 0x0000 +#define MC_TachoEventEdge_Falling 0x0001 +#define MC_TachoEventEdge_Rising 0x0002 +#define MC_TachoEventEdge_RisingFalling 0x0003 + +#define MC_Channel_U 0x0001 +#define MC_Channel_V 0x0002 +#define MC_Channel_W 0x0003 +#define MC_Channel_ALL 0x0004 + + +#define MC_TachoEvent_Hardware_Mode 0x0001 +#define MC_TachoEvent_Software_Mode 0x0002 + +#define MC_IT_CMPW 0x0001 +#define MC_IT_CMPV 0x0002 +#define MC_IT_CMPU 0x0004 +#define MC_IT_ZPC 0x0008 +#define MC_IT_ADT 0x0010 +#define MC_IT_OTC 0x0020 +#define MC_IT_CPT 0x0040 +#define MC_IT_CM0 0x0080 + +#define MC_FLAG_CMPW 0x0001 +#define MC_FLAG_CMPV 0x0002 +#define MC_FLAG_CMPU 0x0004 +#define MC_FLAG_ZPC 0x0008 +#define MC_FLAG_ADT 0x0010 +#define MC_FLAG_OTC 0x0020 +#define MC_FLAG_CPT 0x0040 +#define MC_FLAG_CM0 0x0080 +#define MC_FLAG_EST 0x0100 +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void MC_Init(MC_InitTypeDef* MC_InitStruct); +void MC_DeInit(void); +void MC_StructInit(MC_InitTypeDef* MC_InitStruct); +void MC_Cmd(FunctionalState NewState); +void MC_CtrlPWMOutputs(FunctionalState Newstate); +void MC_ITConfig(u16 MC_IT, FunctionalState NewState); +void MC_SetPrescaler(u8 Prescaler); +void MC_SetPeriod(u16 MC_Period); +void MC_SetPulseU(u16 MC_PulseU); +void MC_SetPulseV(u16 MC_PulseV); +void MC_SetPulseW(u16 MC_PulseW); +void MC_SetTachoCompare(u8 MC_Compare); +void MC_PWMModeConfig(u16 MC_PWMMode); +void MC_SetDeadTime(u16 MC_DeadTime); +void MC_EmergencyCmd(FunctionalState NewState); +void MC_EmergencyClear(void); +u16 MC_GetPeriod(void); +u16 MC_GetPulseU(void); +u16 MC_GetPulseV(void); +u16 MC_GetPulseW(void); +u16 MC_GetTachoCapture(void); +void MC_ClearOnTachoCapture(FunctionalState NewState); +void MC_ForceDataTransfer(u8 MC_ForcedData); +void MC_SoftwarePreloadConfig(void); +void MC_SoftwareTachoCapture(void); +CountingStatus MC_GetCountingStatus(void); +FlagStatus MC_GetFlagStatus(u16 MC_FLAG); +void MC_ClearFlag(u16 MC_FLAG); +ITStatus MC_GetITStatus(u16 MC_IT); +void MC_ClearITPendingBit(u16 MC_IT); + +#endif /* __91x_MC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_rtc.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_rtc.h new file mode 100644 index 0000000..25a2805 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_rtc.h @@ -0,0 +1,109 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_rtc.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the RTC library software functions +* prototypes & definitions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_RTC_H +#define __91x_RTC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Private typedef -----------------------------------------------------------*/ +typedef struct +{ + u8 century; + u8 year; + u8 month; + u8 day; + u8 weekday; +}RTC_DATE; + +typedef struct +{ + u8 hours; + u8 minutes; + u8 seconds; + u16 milliseconds; +}RTC_TIME; + +typedef struct +{ + u8 day; + u8 hours; + u8 minutes; + u8 seconds; +}RTC_ALARM; + +/* Exported constants --------------------------------------------------------*/ + +#define BINARY 0 +#define BCD 1 + +/*TamperMode*/ +#define RTC_TamperMode_Edge 0xFFFFFFEF +#define RTC_TamperMode_Level 0x10 + +/*TamperPol*/ +#define RTC_TamperPol_High 0x4 +#define RTC_TamperPol_Low 0xFFFFFFFB + +/*PeriodicClock*/ +#define RTC_Per_2Hz 0x10000 +#define RTC_Per_16Hz 0x20000 +#define RTC_Per_128Hz 0x40000 +#define RTC_Per_1024Hz 0x80000 +#define RTC_Per_DISABLE 0x0 + +/*RTC_IT*/ +#define RTC_IT_Per 0x200000 +#define RTC_IT_Alarm 0x800000 +#define RTC_IT_Tamper 0x400000 + +/*RTC_FLAG*/ +#define RTC_FLAG_Per 0x80000000 +#define RTC_FLAG_Alarm 0x40000000 +#define RTC_FLAG_Tamper 0x10000000 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RTC_DeInit(void); +void RTC_SetDate(RTC_DATE Date); +void RTC_SetTime(RTC_TIME Time); +void RTC_SetAlarm(RTC_ALARM Alarm); +void RTC_GetDate(u8 Format, RTC_DATE * Date); +void RTC_GetTime(u8 Format, RTC_TIME * Time); +void RTC_GetAlarm(u8 Format, RTC_ALARM * Alarm); +void RTC_TamperConfig(u32 TamperMode, u32 TamperPol); +void RTC_TamperCmd(FunctionalState NewState); +void RTC_AlarmCmd(FunctionalState NewState); +void RTC_CalibClockCmd(FunctionalState NewState); +void RTC_SRAMBattPowerCmd(FunctionalState NewState); +void RTC_PeriodicIntConfig(u32 PeriodicClock); +void RTC_ITConfig(u32 RTC_IT, FunctionalState NewState); +FlagStatus RTC_GetFlagStatus(u32 RTC_FLAG); +void RTC_ClearFlag(u32 RTC_FLAG); +#endif /*__91x_RTC_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + + + diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_scu.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_scu.h new file mode 100644 index 0000000..22d9260 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_scu.h @@ -0,0 +1,198 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +* prototypes & definitions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_SCU_H +#define __91x_SCU_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported constants --------------------------------------------------------*/ + +/*MCLK_Source*/ +#define SCU_MCLK_PLL 0x0 +#define SCU_MCLK_RTC 0x1 +#define SCU_MCLK_OSC 0x2 + +/*RCLK_Divisor*/ +#define SCU_RCLK_Div1 0xFFFFFFE3 +#define SCU_RCLK_Div2 0x4 +#define SCU_RCLK_Div4 0x8 +#define SCU_RCLK_Div8 0xC +#define SCU_RCLK_Div16 0x10 +#define SCU_RCLK_Div1024 0x14 + +/*HCLK_Divisor*/ +#define SCU_HCLK_Div1 0xFFFFFF9F +#define SCU_HCLK_Div2 0x20 +#define SCU_HCLK_Div4 0x40 + +/*PCLK_Divisor*/ +#define SCU_PCLK_Div1 0xFFFFFE7F +#define SCU_PCLK_Div2 0x80 +#define SCU_PCLK_Div4 0x100 +#define SCU_PCLK_Div8 0x180 + +/*FMICLK_Divisor*/ +#define SCU_FMICLK_Div1 0xFFFEFFFF +#define SCU_FMICLK_Div2 0x10000 + +/*BRCLK_Divisor*/ +#define SCU_BRCLK_Div1 0xFFFFFDFF +#define SCU_BRCLK_Div2 0x200 + +/*TIMCLK_Source*/ +#define SCU_TIMCLK_EXT 0x1 +#define SCU_TIMCLK_INT 0x0 + +/*TIMx*/ +#define SCU_TIM01 0x0 +#define SCU_TIM23 0x1 + + +/*USBCLK_Source*/ +#define SCU_USBCLK_MCLK 0xFFFFF3FF +#define SCU_USBCLK_MCLK2 0x400 +#define SCU_USBCLK_EXT 0x800 + +/*SCU_EMIBCLK*/ +#define SCU_EMIBCLK_Div1 0xFFF9FFFF +#define SCU_EMIBCLK_Div2 0x20000 + +/*SCU_EMIMODE*/ +#define SCU_EMI_MUX 0xFFFFFFBF +#define SCU_EMI_DEMUX 0x40 + +/*SCU_EMIALE_LEN*/ +#define SCU_EMIALE_LEN1 0xFFFFFEFF +#define SCU_EMIALE_LEN2 0x100 + +/*SCU_EMIALE_POL*/ +#define SCU_EMIALE_POLLow 0xFFFFFF7F +#define SCU_EMIALE_POLHigh 0x80 + +/*UART_IrDA_Mode*/ +#define SCU_UARTMode_IrDA 0x1 +#define SCU_UARTMode_UART 0x0 + +/*APBPeriph*/ +#define __TIM01 0x1 +#define __TIM23 0x2 +#define __MC 0x4 +#define __UART0 0x8 +#define __UART1 0x10 +#define __UART2 0x20 +#define __I2C0 0x40 +#define __I2C1 0x80 +#define __SSP0 0x100 +#define __SSP1 0x200 +#define __CAN 0x400 +#define __ADC 0x800 +#define __WDG 0x1000 +#define __WIU 0x2000 +#define __GPIO0 0x4000 +#define __GPIO1 0x8000 +#define __GPIO2 0x10000 +#define __GPIO3 0x20000 +#define __GPIO4 0x40000 +#define __GPIO5 0x80000 +#define __GPIO6 0x100000 +#define __GPIO7 0x200000 +#define __GPIO8 0x400000 +#define __GPIO9 0x800000 +#define __RTC 0x1000000 + +/*AHBPeriph*/ +#define __FMI 0x1 +#define __FPQBC 0x2 +#define __SRAM 0x8 +#define __SRAM_ARBITER 0x10 +#define __VIC 0x20 +#define __EMI 0x40 +#define __EMI_MEM_CLK 0x80 +#define __DMA 0x100 +#define __USB 0x200 +#define __USB48M 0x400 +#define __ENET 0x800 +#define __PFQBC_AHB 0x1000 + +/*SCU_IT*/ +#define SCU_IT_LVD_RST 0x10 +#define SCU_IT_SRAM_ERROR 0x8 +#define SCU_IT_ACK_PFQBC 0x4 +#define SCU_IT_LOCK_LOST 0x2 +#define SCU_IT_LOCK 0x1 + +/*SCU_FLAG*/ +#define SCU_FLAG_SRAM_ERROR 0x20 +#define SCU_FLAG_ACK_PFQBC 0x10 +#define SCU_FLAG_LVD_RESET 0x8 +#define SCU_FLAG_WDG_RST 0x4 +#define SCU_FLAG_LOCK_LOST 0x2 +#define SCU_FLAG_LOCK 0x1 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source); +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP); +ErrorStatus SCU_PLLCmd(FunctionalState NewState); +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor); +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor); +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor); +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor); +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source); +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler); +void SCU_USBCLKConfig(u32 USBCLK_Source); +void SCU_PHYCLKConfig(FunctionalState NewState); +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor); +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK); +void SCU_EMIModeConfig(u32 SCU_EMIMODE); +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL); +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState); +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag); +void SCU_ClearFlag(u32 SCU_Flag); +u32 SCU_GetPLLFreqValue(void); +u32 SCU_GetMCLKFreqValue(void); +u32 SCU_GetRCLKFreqValue(void); +u32 SCU_GetHCLKFreqValue(void); +u32 SCU_GetPCLKFreqValue(void); +void SCU_WakeUpLineConfig(u8 EXTint); +void SCU_SpecIntRunModeConfig(FunctionalState NewState); +void SCU_EnterIdleMode(void); +void SCU_EnterSleepMode(void); +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode); +void SCU_PFQBCCmd(FunctionalState NewState); + +extern const u32 _Main_Crystal; + +#endif /*__91x_SCU_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_ssp.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_ssp.h new file mode 100644 index 0000000..e356d4f --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_ssp.h @@ -0,0 +1,119 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ssp.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* SSP software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_SSP_H +#define __91x_SSP_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* SSP Init structure definition */ +typedef struct +{ + u16 SSP_FrameFormat ; + u16 SSP_Mode ; + u16 SSP_CPOL ; + u16 SSP_CPHA ; + u16 SSP_DataSize ; + u16 SSP_SlaveOutput ; + u8 SSP_ClockRate ; + u8 SSP_ClockPrescaler ; +}SSP_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SSP Frame Format Select */ +#define SSP_FrameFormat_TI 0x0010 +#define SSP_FrameFormat_Motorola 0xFFCF +#define SSP_FrameFormat_Microwire 0x0020 + +/* SSP Master/Slave Select */ +#define SSP_Mode_Master 0xFFFB +#define SSP_Mode_Slave 0x0004 + +/* SSP Clock Polarity */ +#define SSP_CPOL_Low 0xFFBF +#define SSP_CPOL_High 0x0040 + +/* SSP Clock Phase */ +#define SSP_CPHA_1Edge 0xFF7F +#define SSP_CPHA_2Edge 0x0080 + +/* SSP Data Size */ +#define SSP_DataSize_16b 0x000F +#define SSP_DataSize_15b 0x000E +#define SSP_DataSize_14b 0x000D +#define SSP_DataSize_13b 0x000C +#define SSP_DataSize_12b 0x000B +#define SSP_DataSize_11b 0x000A +#define SSP_DataSize_10b 0x0009 +#define SSP_DataSize_9b 0x0008 +#define SSP_DataSize_8b 0x0007 +#define SSP_DataSize_7b 0x0006 +#define SSP_DataSize_6b 0x0005 +#define SSP_DataSize_5b 0x0004 +#define SSP_DataSize_4b 0x0003 + +/* SSP Slave output config */ +#define SSP_SlaveOutput_Enable 0xFFF7 +#define SSP_SlaveOutput_Disable 0x0008 + +/* SSP Interrupts */ +#define SSP_IT_TxFifo 0x0008 +#define SSP_IT_RxFifo 0x0004 +#define SSP_IT_RxTimeOut 0x0002 +#define SSP_IT_RxOverrun 0x0001 + +/* SSP Flags */ +#define SSP_FLAG_Busy 0x0024 +#define SSP_FLAG_RxFifoFull 0x0023 +#define SSP_FLAG_RxFifoNotEmpty 0x0022 +#define SSP_FLAG_TxFifoNotFull 0x0021 +#define SSP_FLAG_TxFifoEmpty 0x0020 +#define SSP_FLAG_TxFifo 0x0043 +#define SSP_FLAG_RxFifo 0x0042 +#define SSP_FLAG_RxTimeOut 0x0041 +#define SSP_FLAG_RxOverrun 0x0040 + +/* SSP DMA Requests */ +#define SSP_DMA_Transmit 0x0002 +#define SSP_DMA_Receive 0x0001 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void SSP_DeInit(SSP_TypeDef* SSPx); +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct); +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct); +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState); +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState); +void SSP_DMACmd(SSP_TypeDef* SSPx, u16 SSP_DMATransfert, FunctionalState NewState); +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data); +u16 SSP_ReceiveData(SSP_TypeDef* SSPx); +void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState); +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG); +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG); +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT); +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT); + +#endif /* __91x_SSP_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_tim.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_tim.h new file mode 100644 index 0000000..b587c27 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_tim.h @@ -0,0 +1,155 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_tim.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* TIM software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_TIM_H +#define __91x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" +#include "91x_scu.h" + +/* Exported types ----------------------------------------------------------- */ + +/* TIM Init structure define */ +typedef struct +{ + u16 TIM_Mode; /* Timer mode */ + u16 TIM_OC1_Modes; /* Output Compare 1 Mode: Timing or Wave */ + u16 TIM_OC2_Modes; /* Output Compare 2 Mode: Timing or Wave */ + u16 TIM_Clock_Source; /* Timer Clock source APB/SCU/EXTERNAL */ + u16 TIM_Clock_Edge; /* Timer Clock Edge: Rising or Falling Edge */ + u16 TIM_OPM_INPUT_Edge; /* Timer Input Capture 1 Edge used in OPM Mode */ + u16 TIM_ICAP1_Edge; /* Timer Input Capture 1 Edge used in ICAP1 Mode */ + u16 TIM_ICAP2_Edge; /* Timer Input Capture 2 Edge used in ICAP2 Mode */ + u8 TIM_Prescaler; /* Timer Prescaler factor */ + u16 TIM_Pulse_Level_1; /* Level applied on the Output Compare Pin 1 */ + u16 TIM_Pulse_Level_2; /* Level applied on the Output Compare Pin 2 */ + u16 TIM_Period_Level; /* Level applied during the Period of a PWM Mode */ + u16 TIM_Pulse_Length_1; /* Pulse 1 Length used in Output Compare 1 Mode */ + u16 TIM_Pulse_Length_2; /* Pulse 2 Length used in Output Compare 2 Mode */ + u16 TIM_Full_Period; /* Period Length used in PWM Mode */ +} TIM_InitTypeDef; + +typedef enum +{ + TIM_START, + TIM_STOP, + TIM_CLEAR +} TIM_CounterOperations; + +/* Exported constants --------------------------------------------------------*/ + +/* TIM MODE */ +#define TIM_PWMI 0x4000 /* PWM INPUT Mode */ +#define TIM_OCM_CHANNEL_1 0x0040 /* OUTPUT COMPARE CHANNEL 1 Mode */ +#define TIM_OCM_CHANNEL_2 0x0080 /* OUTPUT COMPARE CHANNEL 2 Mode */ +#define TIM_OCM_CHANNEL_12 0x00C0 /* OUTPUT COMPARE CHANNEL 1 & 2 Mode */ +#define TIM_PWM 0x0010 /* PWM Mode */ +#define TIM_OPM 0x0020 /* ONE PULSE Mode */ +#define TIM_ICAP_CHANNEL_1 0x0400 /* INPUT CAPTURE 1 Mode */ +#define TIM_ICAP_CHANNEL_2 0x0500 /* INPUT CAPTURE 2 Mode */ +#define TIM_ICAP_CHANNEL_12 0x0600 /* INPUT CAPTURE 1 & 2 Mode */ + +/* TIM OUTPUT COMPARE MODE */ +#define TIM_WAVE 0x0001 +#define TIM_TIMING 0x0002 + +/* TIM CLOCK SOURCE */ +#define TIM_CLK_APB 0xFFFE +#define TIM_CLK_EXTERNAL 0x0001 +#define TIM_CLK_SCU 0x0001 + +/* TIM CLOCK EDGE */ +#define TIM_CLK_EDGE_FALLING 0xFFFD +#define TIM_CLK_EDGE_RISING 0x0002 + +/* TIM OPM INPUT EDGE */ +#define TIM_OPM_EDGE_FALLING 0xFFFB +#define TIM_OPM_EDGE_RISING 0x0004 + +/* TIM ICAPA INPUT EDGE */ +#define TIM_ICAP1_EDGE_FALLING 0xFFFB +#define TIM_ICAP1_EDGE_RISING 0x0004 + +/* TIM ICAPB INPUT EDGE */ +#define TIM_ICAP2_EDGE_FALLING 0xFFF7 +#define TIM_ICAP2_EDGE_RISING 0x0008 + +/* TIM OUTPUT LEVEL */ +#define TIM_HIGH 0x0200 +#define TIM_LOW 0x0300 + +/* TIM OUTPUT EDGE */ +#define TIM_OUTPUT_EDGE_RISING 0x8000 +#define TIM_OUTPUT_EDGE_FALLING 0x0800 + +/* TIM channels */ +#define TIM_PWM_OC1_Channel 0x1 /* PWM/Output Compare 1 Channel */ +#define TIM_OC2_Channel 0x2 /* Output Compare 2 Channel */ + +/* TIM DMA SOURCE */ +#define TIM_DMA_IC1 0x0000 /* Input Capture Channel 1 DMA Source */ +#define TIM_DMA_OC1 0x1000 /* OUTPUT Compare Channel 1 DMA Source */ +#define TIM_DMA_IC2 0x2000 /* Input Capture Channel 2 DMA Source */ +#define TIM_DMA_OC2 0x3000 /* OUTPUT Compare Channel 2 DMA Source */ + +/* TIM DMA ENABLE or DISABLE */ +#define TIM_DMA_ENABLE 0x0400 /* DMA Enable */ +#define TIM_DMA_DISABLE 0xFBFF /* DMA Disable */ + +/* TIM Interruption Sources*/ +#define TIM_IT_IC1 0x8000 /* Input Capture Channel 1 Interrupt Source */ +#define TIM_IT_OC1 0x4000 /* Output Compare Channel 1 Interrupt Source */ +#define TIM_IT_TO 0x2000 /* Timer OverFlow Interrupt Source */ +#define TIM_IT_IC2 0x1000 /* Input Capture Channel 2 Interrupt Source */ +#define TIM_IT_OC2 0x0800 /* Output Compare Channel 2 Interrupt Source */ + +/* TIM Flags */ +#define TIM_FLAG_IC1 0x8000 /* Input Capture Channel 1 Flag */ +#define TIM_FLAG_OC1 0x4000 /* Output Compare Channel 1 Flag */ +#define TIM_FLAG_TO 0x2000 /* Timer OverFlow Flag */ +#define TIM_FLAG_IC2 0x1000 /* Input Capture Channel 2 Flag */ +#define TIM_FLAG_OC2 0x0800 /* Output Compare Channel 2 Flag */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct); +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); +void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler); +u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx); +u16 TIM_GetCounterValue(TIM_TypeDef *TIMx); +u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx); +u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx); +void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag); +void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag); +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate); +void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources); +void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate); + +#endif /* __91x_TIM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_type.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_type.h new file mode 100644 index 0000000..916d81c --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_type.h @@ -0,0 +1,50 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_type.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : It contains common types and constants used in all the +* peripherals' drivers. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +#ifndef __91x_type_H +#define __91x_type_H + + typedef long long u64; + typedef unsigned long u32; + typedef unsigned short u16; + typedef unsigned char u8; + + typedef signed long s32; + typedef signed short s16; + typedef signed char s8; + + typedef volatile unsigned long vu32; + typedef volatile unsigned short vu16; + typedef volatile unsigned char vu8; + + typedef volatile signed long vs32; + typedef volatile signed short vs16; + typedef volatile signed char vs8; + +typedef enum { FALSE = 0, TRUE = !FALSE } bool; + +typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; + +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#endif /* __91x_type_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_uart.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_uart.h new file mode 100644 index 0000000..b979438 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_uart.h @@ -0,0 +1,174 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_uart.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* UART software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_UART_H +#define __91x_UART_H + +/* Includes ------------------------------------------------------------------*/ +#include <91x_map.h> + +/* Exported types ------------------------------------------------------------*/ +/* UART FIFO Level enumeration */ +typedef enum +{ + UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ + UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ + UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ + UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ +}UART_FIFOLevel; + +/* UART Init Structure definition */ +typedef struct +{ + u16 UART_WordLength; + u16 UART_StopBits; + u16 UART_Parity; + u32 UART_BaudRate; + u16 UART_HardwareFlowControl; + u16 UART_Mode; + u16 UART_FIFO; + UART_FIFOLevel UART_TxFIFOLevel; + UART_FIFOLevel UART_RxFIFOLevel; +}UART_InitTypeDef; + + +/* UART RTS enumeration */ +typedef enum +{ + LowLevel = 0, + HighLevel +}UART_LevelTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* UART Data Length */ +#define UART_WordLength_5D 0x0000 /* 5 bits Data */ +#define UART_WordLength_6D 0x0020 /* 6 bits Data */ +#define UART_WordLength_7D 0x0040 /* 7 bits Data */ +#define UART_WordLength_8D 0x0060 /* 8 bits Data */ + +/* UART Stop Bits */ +#define UART_StopBits_1 0xFFF7 /* Disable two stop bit is transmitted + at the end of frame */ +#define UART_StopBits_2 0x0008 /* Enable Two stop bits are transmitted + at the end of frame */ +/* UART Parity */ +#define UART_Parity_No 0x0000 /* Parity Disable */ +#define UART_Parity_Even 0x0006 /* Even Parity */ +#define UART_Parity_Odd 0x0002 /* Odd Parity */ +#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ +#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ + +/* UART Hardware Flow Control */ +#define UART_HardwareFlowControl_None 0x0000 /* HFC Disable */ +#define UART_HardwareFlowControl_RTS 0x4000 /* RTS Enable */ +#define UART_HardwareFlowControl_CTS 0x8000 /* CTS Enable */ +#define UART_HardwareFlowControl_RTS_CTS 0xC000 /* CTS and RTS Enable */ + +/* UART Mode */ +#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ +#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ +#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ + +/* UART FIFO */ +#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ +#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ + +/* UART Interrupt definition */ +#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt mask */ +#define UART_IT_BreakError 0x0200 /* Break Error interrupt mask */ +#define UART_IT_ParityError 0x0100 /* Parity Error interrupt mask */ +#define UART_IT_FrameError 0x0080 /* Frame Error interrupt mask */ +#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt mask */ +#define UART_IT_Transmit 0x0020 /* Transmit interrupt mask */ +#define UART_IT_Receive 0x0010 /* Receive interrupt mask */ +#define UART_IT_DSR 0x0008 /* DSR interrupt mask */ +#define UART_IT_DCD 0x0004 /* DCD interrupt mask */ +#define UART_IT_CTS 0x0002 /* CTS interrupt mask */ +#define UART_IT_RI 0x0001 /* RI interrupt mask */ + +/* UART DMA On Error */ +#define UART_DMAOnError_Enable 0xFFFB /* DMA receive request enabled + when the UART error interrupt + is asserted. */ +#define UART_DMAOnError_Disable 0x0004 /* DMA receive request disabled + when the UART error interrupt + is asserted. */ +/* UART DMA Request */ +#define UART_DMAReq_Tx 0x02 /* Transmit DMA Enable */ +#define UART_DMAReq_Rx 0x01 /* Receive DMA Enable */ + +/* UART FLAG */ +#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ +#define UART_FLAG_Break 0x22 /* break error flag */ +#define UART_FLAG_ParityError 0x21 /* parity error flag */ +#define UART_FLAG_FrameError 0x20 /* frame error flag */ +#define UART_FLAG_RI 0x48 /* RI flag */ +#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ +#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ +#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ +#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ +#define UART_FLAG_Busy 0x43 /* UART Busy flag */ +#define UART_FLAG_DCD 0x42 /* DCD flag */ +#define UART_FLAG_DSR 0x41 /* DSR flag */ +#define UART_FLAG_CTS 0x40 /* CTS flag */ +#define UART_RawIT_OverrunError 0x6A /* Overrun Error Raw IT flag */ +#define UART_RawIT_BreakError 0x69 /* Break Error Raw IT flag */ +#define UART_RawIT_ParityError 0x68 /* Parity Error Raw IT flag */ +#define UART_RawIT_FrameError 0x67 /* Frame Error Raw IT flag */ +#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Raw IT flag */ +#define UART_RawIT_Transmit 0x65 /* Transmit Raw IT flag */ +#define UART_RawIT_Receive 0x64 /* Receive Raw IT flag */ +#define UART_RawIT_DSR 0x63 /* DSR Raw IT flag */ +#define UART_RawIT_DCD 0x62 /* DCD Raw IT flag */ +#define UART_RawIT_CTS 0x61 /* CTS Raw IT flag */ +#define UART_RawIT_RI 0x60 /* RI Raw IT flag */ + +/*IrDAx select*/ +#define IrDA0 0x01 /*IrDA0 select*/ +#define IrDA1 0x02 /*IrDA0 select*/ +#define IrDA2 0x03 /*IrDA0 select*/ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void UART_DeInit(UART_TypeDef* UARTx); +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); +void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError); +void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState); +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); +void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState); +void UART_IrDACmd(u8 IrDAx, FunctionalState NewState); +void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter); +void UART_SendData(UART_TypeDef* UARTx, u8 Data); +u8 UART_ReceiveData(UART_TypeDef* UARTx); +void UART_SendBreak(UART_TypeDef* UARTx); +void UART_DTRConfig(UART_LevelTypeDef LevelState); +void UART_RTSConfig(UART_LevelTypeDef LevelState); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); + +#endif /* __91x_UART_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_vic.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_vic.h new file mode 100644 index 0000000..127716a --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_vic.h @@ -0,0 +1,94 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_vic.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* VIC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_VIC_H +#define __91x_VIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" +#include "91x_it.h" + +/* Exported types ------------------------------------------------------------*/ +/* Type of interrupt */ +typedef enum +{ + VIC_IRQ, + VIC_FIQ +} VIC_ITLineMode; + +/* Exported constants --------------------------------------------------------*/ + +/* VIC sources*/ + +#define WDG_ITLine 0 +#define SW_ITLine 1 +#define ARMRX_ITLine 2 +#define ARMTX_ITLine 3 +#define TIM0_ITLine 4 +#define TIM1_ITLine 5 +#define TIM2_ITLine 6 +#define TIM3_ITLine 7 +#define USBHP_ITLine 8 +#define USBLP_ITLine 9 +#define SCU_ITLine 10 +#define ENET_ITLine 11 +#define DMA_ITLine 12 +#define CAN_ITLine 13 +#define MC_ITLine 14 +#define ADC_ITLine 15 +#define UART0_ITLine 16 +#define UART1_ITLine 17 +#define UART2_ITLine 18 +#define I2C0_ITLine 19 +#define I2C1_ITLine 20 +#define SSP0_ITLine 21 +#define SSP1_ITLine 22 +#define LVD_ITLine 23 +#define RTC_ITLine 24 +#define WIU_ITLine 25 +#define EXTIT0_ITLine 26 +#define EXTIT1_ITLine 27 +#define EXTIT2_ITLine 28 +#define EXTIT3_ITLine 29 +#define USBWU_ITLine 30 +#define PFQBC_ITLine 31 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void VIC_DeInit(void); +FlagStatus VIC_GetIRQStatus(u16 VIC_Source); +FlagStatus VIC_GetFIQStatus(u16 VIC_Source); +FlagStatus VIC_GetSourceITStatus(u16 VIC_Source); +void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState); +void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState); +void VIC_ProtectionCmd(FunctionalState VIC_NewState); +u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx); +u32 VIC_GetISRVectAdd(u16 VIC_Source); +void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority); + +#endif /* __91x_VIC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_wdg.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_wdg.h new file mode 100644 index 0000000..fc70547 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_wdg.h @@ -0,0 +1,82 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wdg.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* WDG software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_WDG_H +#define __91x_WDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ +u16 WDG_Mode; +u16 WDG_ClockSource; +u16 WDG_Prescaler; +u16 WDG_Preload; + +} WDG_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/* WDG_Mode */ +#define WDG_Mode_Wdg 0x0001 /*WDG configured to run in watchdog mode.*/ +#define WDG_Mode_Timer 0xFFFE /*WDG configured to be in Free-running Timer mode.*/ + + +/* WDG_ClockSource */ +#define WDG_ClockSource_Rtc 0x0004 /* External clock ( 32 khz RTC clock ) will be used as counting clock.*/ +#define WDG_ClockSource_Apb 0xFFFB /*The APB clock signal will be used as counting clock.*/ + +/* WDG_Prescaler */ +/*This member must be a number between 0x00 and 0xFF. +Specifies the Prescaler value to divide the clock source. +The clock of the Watchdog Timer Counter is divided by " WDG_Prescaler + 1".*/ + + + +/* WDG_Preload */ +/*This member must be a number between 0x0000 and 0xFFFF. +This value is loaded in the WDG Counter when it starts counting.*/ + + +/* WDG Sequence */ +#define WDG_KeyValue1 0xA55A +#define WDG_KeyValue2 0x5AA5 + +/* Exported macro ------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ + +void WDG_DeInit(void); +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); +void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); +void WDG_Cmd(FunctionalState NewState); +void WDG_ITConfig(FunctionalState NewState); +u16 WDG_GetCounter(void); +FlagStatus WDG_GetFlagStatus(void); +void WDG_ClearFlag(void); +ITStatus WDG_GetITStatus(void); +void WDG_ClearITPendingBit(void); + +#endif /* __WDG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_wiu.h b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_wiu.h new file mode 100644 index 0000000..8b0349c --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/include/91x_wiu.h @@ -0,0 +1,99 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wiu.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* WIU software library. +********************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_WIU_H +#define __91x_WIU_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* WIU Init structure type define */ +typedef struct +{ + u8 WIU_Mode ; + u8 WIU_TriggerEdge; + u32 WIU_Line ; +}WIU_InitTypeDef ; + +/* Exported constants --------------------------------------------------------*/ +/* Wake-up line triggering edge */ +#define WIU_FallingEdge 0x00 +#define WIU_RisingEdge 0x01 + +/* Wake-up unit modes */ +#define WIU_Mode_WakeUp 0x01 +#define WIU_Mode_Interrupt 0x02 +#define WIU_Mode_WakeUpInterrupt 0x03 +#define WIU_Mode_SWInterrupt 0x04 + +/* Wake-up lines*/ +#define WIU_Line0 0x0001 +#define WIU_Line1 (WIU_Line0<<1) +#define WIU_Line2 (WIU_Line1<<1) +#define WIU_Line3 (WIU_Line2<<1) +#define WIU_Line4 (WIU_Line3<<1) +#define WIU_Line5 (WIU_Line4<<1) +#define WIU_Line6 (WIU_Line5<<1) +#define WIU_Line7 (WIU_Line6<<1) +#define WIU_Line8 (WIU_Line7<<1) +#define WIU_Line9 (WIU_Line8<<1) +#define WIU_Line10 (WIU_Line9<<1) +#define WIU_Line11 (WIU_Line10<<1) +#define WIU_Line12 (WIU_Line11<<1) +#define WIU_Line13 (WIU_Line12<<1) +#define WIU_Line14 (WIU_Line13<<1) +#define WIU_Line15 (WIU_Line14<<1) +#define WIU_Line16 (WIU_Line15<<1) +#define WIU_Line17 (WIU_Line16<<1) +#define WIU_Line18 (WIU_Line17<<1) +#define WIU_Line19 (WIU_Line18<<1) +#define WIU_Line20 (WIU_Line19<<1) +#define WIU_Line21 (WIU_Line20<<1) +#define WIU_Line22 (WIU_Line21<<1) +#define WIU_Line23 (WIU_Line22<<1) +#define WIU_Line24 (WIU_Line23<<1) +#define WIU_Line25 (WIU_Line24<<1) +#define WIU_Line26 (WIU_Line25<<1) +#define WIU_Line27 (WIU_Line26<<1) +#define WIU_Line28 (WIU_Line27<<1) +#define WIU_Line29 (WIU_Line28<<1) +#define WIU_Line30 (WIU_Line29<<1) +#define WIU_Line31 (WIU_Line30<<1) + +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void WIU_DeInit(void); +void WIU_StructInit(WIU_InitTypeDef* WIU_InitStruct); +void WIU_Init(WIU_InitTypeDef* WIU_InitStruct); +void WIU_GenerateSWInterrupt(u32 WIU_Line); +FlagStatus WIU_GetFlagStatus(u32 WIU_Line); +void WIU_ClearFlag(u32 WIU_Line); +ITStatus WIU_GetITStatus(u32 WIU_Line); +void WIU_ClearITPendingBit(u32 WIU_Line); + +#endif /* __91x_WIU_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_adc.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_adc.c new file mode 100644 index 0000000..a6a07d3 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_adc.c @@ -0,0 +1,590 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_adc.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the ADC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_adc.h" +#include "91x_scu.h" +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ADC mask */ +#define ADC_FLAG_MASK 0x001F /* ADC Flag Mask */ +#define ADC_RESULT_MASK 0x03FF /* ADC Result Mask */ +#define ADC_SCAN_MODE_MASK 0x0020 /* ADC Sacn Mode Mask */ +#define ADC_STANDBY_MODE_MASK 0x0008 /* ADC Standby Mode Mask */ +#define ADC_CMD_MASK 0x0002 /* ADC Command Mask */ +#define ADC_CHANNEL_MASK 0xFE3F /* ADC Channel Select Mask */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ADC_DeInit +* Description : Deinitialize the ADC module registers to their default reset +* values +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DeInit(void) +{ + /* Reset the ADC registers values */ + SCU_APBPeriphReset(__ADC,ENABLE); + SCU_APBPeriphReset(__ADC,DISABLE); +} + +/******************************************************************************* +* Function Name : ADC_Init +* Description : Initializes ADC peripheral according to the specified +* parameters in the ADC_InitTypeDef structure. +* Input : ADC_InitStruct: pointer to a ADC_InitTypeDef structure that +* contains the configuration information for the specified +* ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Set the low threshold of the watchdog */ + ADC->LTR = ADC_InitStruct->ADC_WDG_Low_Threshold; + + /* Set the high threshold of the watchdog */ + ADC->HTR = ADC_InitStruct->ADC_WDG_High_Threshold; + + + /* Channel 0 conversion mode */ + ADC->CCR &= 0xFFFC; + ADC->CCR |= ADC_InitStruct->ADC_Channel_0_Mode; + + /* Channel 1 conversion mode */ + ADC->CCR &= 0xFFF3; + ADC->CCR |= ADC_InitStruct->ADC_Channel_1_Mode << 0x2; + + /* Channel 2 conversion mode */ + ADC->CCR &= 0xFFCF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_2_Mode << 0x4; + + /* Channel 3 conversion mode */ + ADC->CCR &= 0xFF3F; + ADC->CCR |= ADC_InitStruct->ADC_Channel_3_Mode << 0x6; + + /* Channel 4 conversion mode */ + ADC->CCR &= 0xFCFF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_4_Mode << 0x8; + + /* Channel 5 conversion mode */ + ADC->CCR &= 0xF3FF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_5_Mode << 0xA; + + /* Channel 6 conversion mode */ + ADC->CCR &= 0xCFFF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_6_Mode << 0xC; + + /* Channel 7 conversion mode */ + ADC->CCR &= 0x3FFF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_7_Mode << 0xE; + + /* Select the channel to be converted */ + ADC->CR &= ADC_CHANNEL_MASK; + ADC->CR |= ADC_InitStruct->ADC_Select_Channel << 0x6; + + /* Enable/disable the scan mode */ + if (ADC_InitStruct->ADC_Scan_Mode == ENABLE) + { + /* Enable the scan mode */ + ADC->CR |= ADC_SCAN_MODE_MASK; + } + else + { + /* Disable the scan mode */ + ADC->CR &= ~ADC_SCAN_MODE_MASK; + } + + /* Configure the conversion mode */ + if (ADC_InitStruct->ADC_Conversion_Mode == ADC_Continuous_Mode) + { + /* ADC continuous mode */ + ADC->CR |= ADC_Continuous_Mode; + } + else + { + /* ADC single mode */ + ADC->CR &= ADC_Single_Mode; + } +} + +/******************************************************************************* +* Function Name : ADC_StructInit +* Description : Fills each ADC_InitStruct member with its reset value. +* Input : ADC_InitStruct : pointer to a ADC_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + ADC_InitStruct->ADC_WDG_High_Threshold = 0x0000; + ADC_InitStruct->ADC_WDG_Low_Threshold = 0x0000; + ADC_InitStruct->ADC_Channel_0_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_1_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_2_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_3_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_4_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_5_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_6_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_7_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Select_Channel = ADC_Channel_0; + ADC_InitStruct->ADC_Scan_Mode = DISABLE; + ADC_InitStruct->ADC_Conversion_Mode = ADC_Single_Mode; +} + +/******************************************************************************* +* Function Name : ADC_PrescalerConfig +* Description : This routine is used to configure the ADC prescaler value. +* Input : ADC_Prescaler: specifies the prescaler value. This parameter +* can be a value from 0x0 to 0xFF. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_PrescalerConfig(u8 ADC_Prescaler) +{ + ADC->PRS &= 0xFF00; + ADC->PRS |= ADC_Prescaler; + +} +/******************************************************************************* +* Function Name : ADC_GetPrescalerValue +* Description : This routine is used to get the ADC prescaler value. +* Input : None +* Output : None +* Return : The prescaler value. +*******************************************************************************/ +u8 ADC_GetPrescalerValue(void) +{ + return ADC->PRS & 0x00FF; +} +/******************************************************************************* +* Function Name : ADC_GetFlagStatus +* Description : Checks whether the specified ADC flag is set or not. +* Input : ADC_Flag: flag to check. +* This parameter can be one of the following values: +* - ADC_FLAG_OV_CH_0: Conversion overflow status for +* channel 0. +* - ADC_FLAG_OV_CH_1: Conversion overflow status for +* channel 1. +* - ADC_FLAG_OV_CH_2: Conversion overflow status for +* channel 2. +* - ADC_FLAG_OV_CH_3: Conversion overflow status for +* channel 3. +* - ADC_FLAG_OV_CH_4: Conversion overflow status for +* channel 4. +* - ADC_FLAG_OV_CH_5: Conversion overflow status for +* channel 5. +* - ADC_FLAG_OV_CH_6: Conversion overflow status for +* channel 6. +* - ADC_FLAG_OV_CH_7: Conversion overflow status for +* channel 7. +* - ADC_FLAG_ECV: End of conversion status. +* - ADC_FLAG_AWD: Analog watchdog status. +* Output : None +* Return : The NewState of the ADC_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetFlagStatus(u16 ADC_Flag) +{ + u8 AdcReg = 0, FlagPos = 0; + + /* Get the ADC register index */ + AdcReg = ADC_Flag >> 5; + + /* Get the flag position */ + FlagPos = ADC_Flag & ADC_FLAG_MASK; + + if(AdcReg == 1) /* The flag to check is in CR register */ + { + if((ADC->CR & (1<DR0 & (1<DR1 & (1<DR2 & (1<DR3 & (1<DR4 & (1<DR5 & (1<DR6 & (1<DR7 & (1<CR |= (1<<(ADC_Flag & ADC_FLAG_MASK)); +} + +/******************************************************************************* +* Function Name : ADC_GetConversionValue +* Description : Read the result of conversion from the appropriate data +* register. +* Input : ADC_Channel: the correspondent channel of the ADC peripheral. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC channel 0. +* - ADC_Channel_1: ADC channel 1. +* - ADC_Channel_2: ADC channel 2. +* - ADC_Channel_3: ADC channel 3. +* - ADC_Channel_4: ADC channel 4. +* - ADC_Channel_5: ADC channel 5. +* - ADC_Channel_6: ADC channel 6. +* - ADC_Channel_7: ADC channel 7. +* Output : None +* Return : The result of the conversion for the specific channel. +*******************************************************************************/ +u16 ADC_GetConversionValue(u16 ADC_Channel) +{ + u16 ADC_Conversion_Value = 0; + + switch (ADC_Channel) + { + case (ADC_Channel_0): + /* Get the conversion value of the channel 0 */ + ADC_Conversion_Value = ADC->DR0 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_1): + /* Get the conversion value of the channel 1 */ + ADC_Conversion_Value = ADC->DR1 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_2): + /* Get the conversion value of the channel 2 */ + ADC_Conversion_Value = ADC->DR2 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_3): + /* Get the conversion value of the channel 3 */ + ADC_Conversion_Value = ADC->DR3 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_4): + /* Get the conversion value of the channel 4 */ + ADC_Conversion_Value = ADC->DR4 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_5): + /* Get the conversion value of the channel 5 */ + ADC_Conversion_Value = ADC->DR5 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_6): + /* Get the conversion value of the channel 6 */ + ADC_Conversion_Value = ADC->DR6 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_7): + /* Get the conversion value of the channel 7 */ + ADC_Conversion_Value = ADC->DR7 & ADC_RESULT_MASK; + break; + + default: + break; + } + + return(ADC_Conversion_Value); +} + +/******************************************************************************* +* Function Name : ADC_GetAnalogWatchdogResult +* Description : Return the result of the comparaison on the selected Analog +* Watchdog. +* Input : ADC_Channel: the correspondent channel of the ADC peripheral. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC channel 0. +* - ADC_Channel_1: ADC channel 1. +* - ADC_Channel_2: ADC channel 2. +* - ADC_Channel_3: ADC channel 3. +* - ADC_Channel_4: ADC channel 4. +* - ADC_Channel_5: ADC channel 5. +* - ADC_Channel_6: ADC channel 6. +* - ADC_Channel_7: ADC channel 7. +* Output : None +* Return : The state of the comparision (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetAnalogWatchdogResult(u16 ADC_Channel) +{ + if (ADC->CRR & (1<CRR = 1<LTR; + break; + + case ADC_HighThreshold: + /* Get the high threshol of the watchdog */ + ADC_Threshold_Value = ADC->HTR; + break; + + default: + break; + } + + return(ADC_Threshold_Value); +} + +/******************************************************************************* +* Function Name : ADC_ITConfig +* Description : Enables or disables the specified ADC interrupts. +* Input : - ADC_IT: specifies the ADC interrupts sources to be enabled +* or disabled. +* This parameter can be one of the following values: +* - ADC_IT_EndOfConversion: End of conversion interrupt. +* - ADC_IT_AnalogWDG: Analog watchdog interrupt. +* - ADC_NewState: new state of the specified ADC interrupts. +* (ADC_Newstate can be ENABLE or DISABLE). +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ITConfig(u16 ADC_IT, FunctionalState ADC_NewState) +{ + if (ADC_NewState == ENABLE) + { + /* Enable the interrupt */ + ADC->CR |= ADC_IT; + } + else + { + /* Disable the interrupt */ + ADC->CR &= ~ADC_IT; + } +} + +/******************************************************************************* +* Function Name : ADC_StandbyModeCmd +* Description : Enable or disable the standby mode. +* Input : ADC_NewState: new state of the ADC standby mode. +* (ADC_Newstate can be ENABLE or DISABLE). +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StandbyModeCmd(FunctionalState ADC_NewState) +{ + if (ADC_NewState == ENABLE) + { + /* Enable the standby mode */ + ADC->CR |= ADC_STANDBY_MODE_MASK; + } + else + { + /* Disable the standby mode */ + ADC->CR &= ~ADC_STANDBY_MODE_MASK; + } +} + +/******************************************************************************* +* Function Name : ADC_Cmd +* Description : Power on or put in reset mode the ADC peripheral. +* Input : ADC_NewState: new state of the ADC peripheral. +* (ADC_Newstate can be ENABLE or DISABLE). +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Cmd(FunctionalState ADC_NewState) +{ + if (ADC_NewState == ENABLE) + { + /* Enable the ADC */ + ADC->CR |= ADC_CMD_MASK; + } + else + { + /* Disable the ADC */ + ADC->CR &= ~ADC_CMD_MASK; + } +} + +/******************************************************************************* +* Function Name : ADC_ConversionCmd +* Description : Start or stop the ADC conversion in the selected mode. +* Input : ADC_Conversion: the conversion command. +* This parameter can be one of the following values: +* - ADC_Conversion_Start: Start the conversion. +* - ADC_Conversion_Stop: Stop the Conversion. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ConversionCmd(u16 ADC_Conversion) +{ + if (ADC_Conversion == ADC_Conversion_Start) + { + /* Start the ADC conversion */ + ADC->CR |= ADC_Conversion_Start; + } + else + { + /* Stop the ADC conversion */ + ADC->CR &= ADC_Conversion_Stop; + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_ahbapb.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_ahbapb.c new file mode 100644 index 0000000..41489ac --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_ahbapb.c @@ -0,0 +1,177 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the AHBAPB software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_ahbapb.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#define AHBAPB_SplitCounter_Mask 0xFFE0FFFF +#define AHBAPB_SetTimeOut_Mask 0xFFFFFFE0 +#define AHBAPB_Address_Mask 0xFEFFFFFF +#define AHBAPB_FLAG_RW_Mask 0x01000000 +/******************************************************************************* +* Function Name : AHBAPB_DeInit +* Description : Deinitializes the AHBAPBx peripheral registers to their default +* reset values. +* Input : AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx) +{ + AHBAPBx->BCR = 0x00000000; + AHBAPBx->BSR = 0x00000000; +} +/******************************************************************************* +* Function Name : AHBAPB_Init +* Description : Initializes the AHBAPBx peripheral according to the specified +* parameters in the AHBAPB_InitStruct . +* Input :- AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* - AHBAPB_InitStruct: pointer to a AHBAPB_InitTypeDef structure that +* contains the configuration information for the specified AHBAPB +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + + if(AHBAPB_InitStruct->AHBAPB_Split == AHBAPB_Split_Enable) + { + /* Set SPLITEN bit;*/ + AHBAPBx->BCR |= AHBAPB_Split_Enable; + /*Split_CNT bits[20:16]*/ + AHBAPBx->BCR &= AHBAPB_SplitCounter_Mask; + AHBAPBx->BCR |= (AHBAPB_InitStruct->AHBAPB_SplitCounter)<<16; + } + else + { + /*/ Clear SPLITEN bit;*/ + AHBAPBx->BCR &= AHBAPB_Split_Disable; + } + /*APB Time out*/ + if(AHBAPB_InitStruct->AHBAPB_Error == AHBAPB_Error_Enable) + { + /* Set ERREN bit*/ + AHBAPBx->BCR |= AHBAPB_Error_Enable; + /*Time ouit counter*/ + AHBAPBx->BCR &= AHBAPB_SetTimeOut_Mask; + AHBAPBx->BCR |= AHBAPB_InitStruct->AHBAPB_SetTimeOut; + } + else + { + /* Clear ERREN bit*/ + AHBAPBx->BCR &= AHBAPB_Error_Disable; + } +} + +/******************************************************************************* +* Function Name : AHBAPB_StructInit +* Description : Initialize the AHBAPB Init Structure parameters +* Input : AHBAPB_InitStruct : pointer to a AHBAPB_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + /* Reset AHBAPB init structure parameters values */ + AHBAPB_InitStruct->AHBAPB_Split = AHBAPB_Split_Enable; + AHBAPB_InitStruct->AHBAPB_SplitCounter = 0xFF; + AHBAPB_InitStruct->AHBAPB_Error = AHBAPB_Error_Enable; + AHBAPB_InitStruct->AHBAPB_SetTimeOut = 0xFF; + +} + +/******************************************************************************* +* Function Name : AHBAPB_GetFlagStatus +* Description : Checks whether the specified AHBAPB flag is set or not. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* - AHBAPB_FLAG_RW : Access type flag +* Output : None +* Return : The new state of AHBAPB_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + if(AHBAPB_FLAG == AHBAPB_FLAG_RW) + { + if ((AHBAPBx->PAER & AHBAPB_FLAG_RW_Mask) == RESET) + { + return RESET; + } + else + { + return SET; + } + } + else + { + if ((AHBAPBx->BSR & AHBAPB_FLAG) == RESET) + { + return RESET; + } + else + { + return SET; + } + } +} +/******************************************************************************* +* Function Name : AHBAPB_ClearFlag +* Description : Clears the AHBAPBx flags. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: flags to clear. This parameter one of the +* following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + /* Clear the flag */ + AHBAPBx->BSR &= AHBAPB_FLAG; +} +/******************************************************************************* +* Function Name : AHBAPB_GetPeriphAddrError +* Description : Gets the AHBAPB error address peripherals. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* Output : None +* Return : The Peropheral address error +*******************************************************************************/ +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx) +{ + u32 AHBAPB_Address = 0x00000000; + + /*Return Oeripheral address without RW bit*/ + AHBAPB_Address = (AHBAPBx->PAER)& AHBAPB_Address_Mask; + return (AHBAPB_Address); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_can.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_can.c new file mode 100644 index 0000000..e560d03 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_can.c @@ -0,0 +1,768 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_can.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the CAN software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_can.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ +/* Description : Form the Mask and Arbitration registers value to filter */ +/* a range of identifiers or a fixed identifier, for standard*/ +/* and extended IDs */ +/*----------------------------------------------------------------------------*/ +#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) +#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) + +#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) +#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) + +#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) +#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) + +#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) +#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) + +#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) +#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) + +#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) +#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) +#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) +#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) + +/* macro to format the timing register value from the timing parameters*/ +#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) + +/* Private variables ---------------------------------------------------------*/ +/* array of pre-defined timing parameters for standard bitrates*/ +u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ + CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ + CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ + CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ + CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ + CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ +}; + +/* Private function prototypes -----------------------------------------------*/ +static u32 GetFreeIF(void); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_DeInit (void) +{ + /* Reset the CAN registers values*/ + + SCU_APBPeriphReset(__CAN,ENABLE); /*CAN peripheral is under Reset */ + SCU_APBPeriphReset(__CAN,DISABLE); /*CAN peripheral Reset off*/ + + +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +* contains the configuration information for the CAN peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); + CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); + CAN_LeaveInitMode(); + CAN_LeaveTestMode(); +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its reset value. +* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ +/* Reset CAN init structure parameters values */ + CAN_InitStruct->CAN_ConfigParameters = 0x0; + CAN_InitStruct->CAN_Bitrate = 0x2301; +} + +/******************************************************************************* +* Function Name : CAN_SetBitrate +* Description : Setups a standard CAN bitrate. +* Input : bitrate: specifies the bit rate. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetBitrate(u32 bitrate) +{ + CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ + CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ +} + +/******************************************************************************* +* Function Name : CAN_SetTiming +* Description : Setups the CAN timing with specific parameters +* Input : - tseg1: specifies Time Segment before the sample point. +* This parameter must be a number between 1 and 16. +* - tseg2: Time Segment after the sample point. This parameter +* must be a number between 1 and 8. +* - sjw: Synchronisation Jump Width. This parameter must be +* a number between 1 and 4. +* - brp: Baud Rate Prescaler. This parameter must be a number +* between 1 and 1024. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) +{ + CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); + CAN->BRPR = ((brp-1) >> 6) & 0x0F; +} + +/******************************************************************************* +* Function Name : GetFreeIF +* Description : Searchs the first free message interface, starting from 0. +* Input : None +* Output : None +* Return : A free message interface number (0 or 1) if found, else 2 +*******************************************************************************/ +static u32 GetFreeIF(void) +{ + if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) + return 0; + else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) + return 1; + else + return 2; +} + +/******************************************************************************* +* Function Name : CAN_SetUnusedMsgObj +* Description : Configures the message object as unused +* Input : msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = 0; + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = 0; + + CAN->sMsgObj[msg_if].MCR = 0; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetTxMsgObj +* Description : Configures the message object as TX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].A1R = 0; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; + } + else + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetRxMsgObj +* Description : Configures the message object as RX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* - idLow: specifies the low part of the identifier range used +* for acceptance filtering. +* - idHigh: specifies the high part of the identifier range +* used for acceptance filtering. +* - singleOrFifoLast: specifies the end-of-buffer indicator. +* This parameter can be one of the following values: +* - TRUE: for a single receive object or a FIFO receive +* object that is the last one of the FIFO. +* - FALSE: for a FIFO receive object that is not the +* last one. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); + } + else + { + CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_InvalidateAllMsgObj +* Description : Configures all the message objects as unused. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_InvalidateAllMsgObj(void) +{ + u32 i=0; + for (i = 0; i < 32; i++) + CAN_SetUnusedMsgObj(i); +} + + +/******************************************************************************* +* Function Name : CAN_ReleaseMessage +* Description : Releases the message object +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_ReleaseMessage(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SendMessage +* Description : Start transmission of a message +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* : - pCanMsg: pointer to the message structure containing data +* to transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) +{ + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_TXOK; + + /* read the Arbitration and Message Control*/ + CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + /* update the contents needed for transmission*/ + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_ReceiveMessage +* Description : Gets the message, if received. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - release: specifies the message release indicator. +* This parameter can be one of the following values: +* - TRUE: the message object is released when getting +* the data. +* - FALSE: the message object is not released. +* - pCanMsg: pointer to the message structure where received +* data is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) +{ + if (!CAN_IsMessageWaiting(msgobj)) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + /* read the message contents*/ + CAN->sMsgObj[1].CMR = CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_CLRINTPND + | (release ? CAN_CMR_TXRQSTNEWDAT : 0) + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[1].CRR = 1 + msgobj; + + if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_WaitEndOfTx +* Description : Waits until current transmission is finished. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission ended +* - ERROR: Transmission did not occur yet +*******************************************************************************/ +ErrorStatus CAN_WaitEndOfTx(void) +{ + if ((CAN->SR & CAN_SR_TXOK) == 0) + { + return ERROR; + } + CAN->SR &= ~CAN_SR_TXOK; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicSendMessage +* Description : Starts transmission of a message in BASIC mode. This mode +* does not use the message RAM. +* Input : pCanMsg: Pointer to the message structure containing data to +* transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) +{ + /* clear NewDat bit in IF2 to detect next reception*/ + CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; + + CAN->SR &= ~CAN_SR_TXOK; + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + /* request transmission*/ + if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) + { + return ERROR; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicReceiveMessage +* Description : Gets the message in BASIC mode, if received. This mode does +* not use the message RAM. +* Input : pCanMsg: pointer to the message structure where message is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) +{ + if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + CAN->sMsgObj[1].CMR = CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_EnterInitMode +* Description : Switchs the CAN into initialization mode. This function must +* be used in conjunction with CAN_LeaveInitMode(). +* Input : InitMask: specifies the CAN configuration in normal mode. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterInitMode(u8 InitMask) +{ + CAN->CR = InitMask | CAN_CR_INIT; + CAN->SR = 0; /* reset the status*/ +} + +/******************************************************************************* +* Function Name : CAN_LeaveInitMode +* Description : Leaves the initialization mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterInitMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveInitMode(void) +{ + CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); +} + +/******************************************************************************* +* Function Name : CAN_EnterTestMode +* Description : Switchs the CAN into test mode. This function must be used in +* conjunction with CAN_LeaveTestMode(). +* Input : TestMask: specifies the configuration in test modes. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterTestMode(u8 TestMask) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR |= TestMask; +} + +/******************************************************************************* +* Function Name : CAN_LeaveTestMode +* Description : Leaves the current test mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterTestMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveTestMode(void) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); + CAN->CR &= ~CAN_CR_TEST; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseTxMessage +* Description : Releases the transmit message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseTxMessage(u32 msgobj) +{ + CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[0].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseRxMessage +* Description : Releases the receive message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseRxMessage(u32 msgobj) +{ + CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[1].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_IsMessageWaiting +* Description : Tests the waiting status of a received message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object has +* received a message waiting to be copied, else 0. +*******************************************************************************/ +u32 CAN_IsMessageWaiting(u32 msgobj) +{ + return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsTransmitRequested +* Description : Tests the request status of a transmitted message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message is requested +* to transmit, else 0. +*******************************************************************************/ +u32 CAN_IsTransmitRequested(u32 msgobj) +{ + return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsInterruptPending +* Description : Tests the interrupt status of a message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message has an +* interrupt pending, else 0. +*******************************************************************************/ +u32 CAN_IsInterruptPending(u32 msgobj) +{ + return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsObjectValid +* Description : Tests the validity of a message object (ready to use). +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object is +* valid, else 0. +*******************************************************************************/ +u32 CAN_IsObjectValid(u32 msgobj) +{ + return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_dma.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_dma.c new file mode 100644 index 0000000..db6ad6e --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_dma.c @@ -0,0 +1,1125 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_dma.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the DMA software functions +* needed to access all DMA registers. +******************************************************************************** +* History:v 1.0 +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ + +# include"91x_dma.h" +# include"91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + + +/* DMA Masks "used" only in this module */ + +#define DMA_Width_DES_MASK 0xFF1FFFFF +#define DMA_Width_SRC_MASK 0xFFE3FFFF +#define DMA_Bst_DES_MASK 0xFFFC7FFF +#define DMA_Bst_SRC_MASK 0xFFFF8FFF +#define DMA_FlowCntrl_Mask 0xFFFFC7FF +#define DMA_TrsfSisze_Mask 0xFFFFF000 +#define SRC_Mask 0xFFFFFFE1 +#define DES_Mask 0xFFFFFC3F +#define DMA_TCIE 0x80000000 +#define DMA_ChannelDESInc 0x08000000 +#define DMA_ChannelSRCInc 0x04000000 +#define DMA_BufferChannel 0x20000000 +#define DMA_HaltChannel 0x00040000 +#define DMA_LockChannel 0x00010000 +#define DMA_CacheChannel 0x40000000 +#define DMA_ChannelActive 0x00020000 +#define DMA_Enable 0x00000001 +#define DMA_ChannelEnable 0x00000001 + + + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : DMA_ITMaskConfig +* Description : Enables or disables the specified DMA_Channelx Mask interrupt. +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -DMA_ITMask: specifies the DMA interrupt mask source to be enabled or disabled. +* This parameter can be: +* - DMA_ITMask_IE (Interrupt error mask). +* - DMA_ITMask_ITC (Terminal count interrupt mask). +* - DMA_ITMask_ALL ( All interrupts mask) +* +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask , FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Mask the Interrupt */ + { + DMA_Channelx-> CCNF |= DMA_ITMask ; + } + + else /* Disable the Interrupt Mask*/ + { + DMA_Channelx-> CCNF &= ~ DMA_ITMask ; + } +} + + + + + +/******************************************************************************* +* Function Name : DMA_ITConfig +* Description : Enables or disables the DMA_Channelx Terminal Count interrupt. +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enable the Terminal Count Interrupt */ + { + DMA_Channelx->CC |= DMA_TCIE ; + } + + else /* Disable the Terminal Count Interrupt */ + { + DMA_Channelx-> CC &= ~ DMA_TCIE ; + } +} + + +/******************************************************************************** +* Function Name : DMA_SyncConfig +* Description : Enables or disables synchronization logic for the corresponding DMA Request Signal. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SyncConfig(u16 SRCReq, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enable the synchronization logic for the corresponding DMA Request Signal */ + { + + DMA->SYNR &= ~ SRCReq ; + + } + + else /* Disable the synchronization logic for the corresponding DMA Request Signal. */ + { + DMA->SYNR |= SRCReq ; + + } +} + + +/******************************************************************************** +* Function Name : DMA_SetSReq +* Description : Set the DMA to generate a Single transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SetSReq(u16 SRCReq) + +{ /* Set the DMA to generate a Single transfer request for the corresponding DMA Request Source */ + DMA->SSRR |= SRCReq ; +} + + + + +/******************************************************************************** +* Function Name : DMA_SetLSReq +* Description : Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : None. +*******************************************************************************/ + +void DMA_SetLSReq(u16 SRCReq ) +{ /* Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source */ + DMA->SLSRR |= SRCReq ; +} + + +/******************************************************************************** +* Function Name : DMA_SetBReq +* Description : Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SetBReq(u16 SRCReq) + +{ /* Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source */ + DMA->SBRR |= SRCReq ; +} + + + +/******************************************************************************** +* Function Name : DMA_SetLBReq +* Description : Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SetLBReq(u16 SRCReq) + +{ /* Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source */ + DMA->SLBRR |= SRCReq ; +} + + +/******************************************************************************** +* Function Name : DMA_GetSReq +* Description : Check for a specific source if it request a Single transfer . +* Input : +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetSReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Single transfer . */ + if ( (DMA->SSRR & SRCReq )!= RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + + +/******************************************************************************** +* Function Name : DMA_GetLSReq +* Description : Check for a specific source if it request a Last Single transfer . +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetLSReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Last Single transfer . */ + if ( (DMA->SLSRR & SRCReq)!= RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + +/******************************************************************************** +* Function Name : DMA_GetBReq +* Description : Check for a specific source if it request a Burst transfer . +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetBReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Burst transfer . */ + if (( DMA->SBRR & SRCReq ) != RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + +/******************************************************************************** +* Function Name : DMA_GetLSReq +* Description : Check for a specific source if it request a Last Burst transfer . +* Input : +* Input : +* - SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetLBReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Last Burst transfer . */ + if ( ( DMA->SLBRR & SRCReq ) != RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + + + +/******************************************************************************* +* Function Name : DMA_ChannelHalt +* Description : Enables DMA requests or ignore extra source DMA requests for + the specified channel. +* Input : + -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. + -NewState: new state of the specified DMA_Channelx mask interrupt. + This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelHalt(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enables DMA requests */ + + { + DMA_Channelx->CCNF |= DMA_HaltChannel ; + } + + else /* Ignore extra source DMA request */ + { + DMA_Channelx->CCNF &= ~ DMA_HaltChannel ; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelLockTrsf +* Description : Enables or disables the Locked Transfers Feature for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Locked transfers enabled on channel x */ + + { + DMA_Channelx->CCNF |= DMA_LockChannel ; + } + + else /* Locked transfers disabled on channel xt */ + { + DMA_Channelx->CCNF &= ~ DMA_LockChannel; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelCache +* Description : Enables or disables the cacheability Feature for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelCache (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Cacheability Feature enabled on channelx */ + + { + DMA_Channelx->CC |= DMA_CacheChannel ; + } + + else /* Cacheability Feature disabled on channelx */ + { + DMA_Channelx->CC &= ~ DMA_CacheChannel ; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelBuffering +* Description : Enables or disables the Buffering Feature for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Cacheability Feature enabled on channel x */ + + { + DMA_Channelx->CC |= DMA_BufferChannel ; + } + + else /* Cacheability Feature disabled on channel xt */ + { + DMA_Channelx->CC &= ~ DMA_BufferChannel ; + } +} + +/******************************************************************************* +* Function Name : MA_ChannelProt0Mod +* Description : Sets The User or Privileged mode for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -Prot0Mode: Specifies the Privileged mode Or the User mode. +* This parameter can be: +* - DMA_PrevilegedMode +* - DMA_UserMode +* +* +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelProt0Mode (DMA_Channel_TypeDef * DMA_Channelx, u32 Prot0Mode) + +{ + if (Prot0Mode==DMA_PrevilegedMode) /* Privileged mode */ + { + DMA_Channelx->CC |= DMA_PrevilegedMode ; + } + + else /* User mode */ + { + DMA_Channelx->CC &= DMA_UserMode ; + } +} + + + + + +/******************************************************************************* +* Function Name : DMA_ChannelSRCIncConfig +* Description : Enables or disables the Source address incrementation after each transfer for +* the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* The Source address is incremented after each transfer */ + + { + DMA_Channelx->CC |= DMA_ChannelSRCInc ; + } + + else /* The Source address is not incremented after each Transfer */ + { + DMA_Channelx->CC &= ~ DMA_ChannelSRCInc ; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelDESIncConfig +* Description : Enables or disables the Destination address incrementation after each transfer for +* the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* The Destination address is incremented after each transfer */ + + { + DMA_Channelx->CC |= DMA_ChannelDESInc ; + } + + else /* The Destination address is not incremented after each Transfer */ + { + DMA_Channelx->CC &= ~ DMA_ChannelDESInc ; + } +} + + + +/******************************************************************************** +* Function Name : DMA_GetChannelStatus +* Description : Checks the status of DMA channelx ( Enabled or Disabled). +* - ChannelIndx:specifies the DMA Channel to be checked. +* This parameter can be: +* - Channel0 +* - Channel1 +* - Channel2 +* - Channel3 +* - Channel4 +* - Channel5 +* - Channel6 +* - Channel7 +* Output : None. +* +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ) + +{ + + if ( ( DMA->ENCSR & (1 << ChannelIndx )) != RESET ) + { + return SET; /* Channelx Enabled */ + } + + else + + { + + return RESET; /* Channelx Disabled */ + + } + +} + + + +/******************************************************************************** +* Function Name : DMA_GetITStatus +* Description : Checks the status of Terminal Count and Error interrupts request after and before Masking. +* Input : +* - ChannelIndx:specifies the DMA Channel to be checked. +* This parameter can be: +* - Channel0 +* - Channel1 +* - Channel2 +* - Channel3 +* - Channel4 +* - Channel5 +* - Channel6 +* - Channel7 +* +*. - DMA_ITReq: specifies the DMA interrupt request status to be checked. +* This parameter can be: +* +* - DMA_IS +* - DMA_TCS +* - DMA_ES +* - DMA_TCRS +* - DMA_ERS. +* +* Output : None. +* +* Return : SET or RESET. +*******************************************************************************/ + + +ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq) + +{ + u32 DMAReg = 0; + + switch(DMA_ITReq) + + { + + case (DMA_IS): /*The status of the interrupts after masking : logical or of all Interrupts after Masking*/ + DMAReg = DMA->ISR; + break; + + + + case (DMA_TCS): /* The status of the Terminal count request after masking */ + DMAReg = DMA->TCISR; + break; + + + case (DMA_ES): /* The status of the error request after masking */ + DMAReg = DMA->EISR; + break; + + + case (DMA_TCRS): /* Indicates if the DMA channel is requesting a transfer complete (terminal count Interrupt) prior to masking or Not. */ + DMAReg = DMA->TCRISR; + break; + + case (DMA_ERS): /* Indicates if the DMA channel is requesting an Error Interrupt prior to masking or Not. */ + DMAReg = DMA->ERISR; + break; + + + } + + if((DMAReg &(1 << ChannelIndx )) != RESET ) + + { + return SET; + } + + else + + { + + return RESET; + + + } + +} + + +/******************************************************************************** +* Function Name : DMA_ClearIT +* Description : Clears The Interrupt pending bits for termnal count or Error interrupts for a specified DMA Channel. +* - ChannelIndx:specifies the DMA Channel to be checked. +* This parameter can be: +* - Channel0 +* - Channel1 +* - Channel2 +* - Channel3 +* - Channel4 +* - Channel5 +* - Channel6 +* - Channel7 +* - DMA_ITClr : Specifies the DMA interrupt pending to be cleared. +*. This parameter can be: +* - DMA_TCC +* - DMA_EC. +* +* Output : None. + +* Return : SET or RESET. +*******************************************************************************/ + + +void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr) + +{ + + + switch(DMA_ITClr) + + { + + case (DMA_TCC): /* Clear The status of the Terminal count interrupt on the corresponding channel.*/ + DMA->TCICR |=(1 << ChannelIndx ); + break; + + + + case (DMA_EC): /* Clear The status of the error interrupt on the corresponding channel.*/ + DMA->EICR |=(1 << ChannelIndx ); + break; + + + + } + + + +} + + +/******************************************************************************* +* Function Name : DMA_Cmd(FunctionalState NewState) +* Description : Enables or disables the DMA peripheral. +* +* Input : +* -NewState: new state of the DMA. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_Cmd(FunctionalState NewState) + +{ + if (NewState==ENABLE) /* ENABLE the DMA peripheral */ + + { + DMA-> CNFR |= DMA_Enable ; + } + + else /* DISABLE the DMA peripheral */ + { + DMA-> CNFR &= ~ DMA_Enable ; + } +} + + + +/******************************************************************************* +* Function Name : DMA_ChannelCmd +* Description : Enables or disables the specified DMA_Channelx +* +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelCmd (DMA_Channel_TypeDef *DMA_Channelx,FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enable The Channelx */ + + { + DMA_Channelx->CCNF |= DMA_ChannelEnable ; + } + + else /* Disable The Channelx */ + { + DMA_Channelx-> CCNF &= ~ DMA_ChannelEnable ; + } +} + + + +/******************************************************************************** +* Function Name : DMA_GetChannelActiveStatus +* Description : Checks The DMA_Channelx FIFO if it has data or not. +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* +* +* Output : None. +* +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx ) + +{ + + if ( ( DMA_Channelx->CCNF & DMA_ChannelActive) != RESET ) + { + return SET; /* The DMA_Channelx FIFO has data */ + } + + else + + { + + return RESET; /* No data in the DMA_Channelx FIFO */ + + + } + +} + + +/******************************************************************************** +* Function Name : DMA_DeInit +* Description : Initializes the DMA peripheral registers to their default reset values. +* +* +* Input : None +* +* Output : None. +* +* Called Functions: +* +* - SCU_AHBPeriphReset: Function defined in the System clock Unit "scu.c". +* +* +* Return : None +*******************************************************************************/ + + +void DMA_DeInit(void) + +{ + + SCU_AHBPeriphReset(__DMA, ENABLE); /*DMA peripheral is under Reset " Reset on"*/ + SCU_AHBPeriphReset(__DMA, DISABLE); /*DMA peripheral Reset off*/ +} + + + +/******************************************************************************** +* Function Name : DMA_StructInit +* Description : Fills each DMA_InitStruct member with its reset value. +* Input : +* -DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized. +* +* Output : None. +* +* Return : None +*******************************************************************************/ + + +void DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct) + +{ + + /* Initialize The current source address */ + DMA_InitStruct-> DMA_Channel_SrcAdd =0x0000000; + + + /* Initialize The current Destination address */ + DMA_InitStruct->DMA_Channel_DesAdd=0x00000000; + + + + /* Initialize The Linked List Items */ + DMA_InitStruct->DMA_Channel_LLstItm=0x00000000 ; + + + + /* Initialize The Destination width */ + DMA_InitStruct->DMA_Channel_DesWidth= DMA_DesWidth_Byte; + + + + /* Initialize The source width */ + DMA_InitStruct->DMA_Channel_SrcWidth= DMA_SrcWidth_Byte; + + + /* Initialize The Burst Size for the Destination */ + DMA_InitStruct->DMA_Channel_DesBstSize= DMA_DesBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the Destination width */ + + + + /* Initialize The Burst Size for the Source*/ + DMA_InitStruct->DMA_Channel_SrcBstSize= DMA_SrcBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the source width */ + + /* Initialize The Flow control and transfer type for the DMA transfer */ + DMA_InitStruct->DMA_Channel_FlowCntrl=DMA_FlowCntrlt0_DMA; /* memory to memory transfer with DMA as flow controller */ + + + /* Initialize The Transfer Size */ + DMA_InitStruct->DMA_Channel_TrsfSize =0x00; + + + + /* Initialize the DMA source request peripheral :"This field is ignored if the source of the transfer is from memory" */ + DMA_InitStruct->DMA_Channel_Src =0x00; + + + + /* Initialize the DMA Destination request peripheral :"This field is ignored if the destination of the transfer is to memory.*/ + + DMA_InitStruct->DMA_Channel_Des=0x00; + + +} + + + + +/******************************************************************************** +* Function Name : DMA_Init +* Description : Initializes the DMA_Channelx according to the specified parameters +* in the DMA_InitStruct . +* +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -DMA_InitStruct: pointer to a DMA_InitTypeDef structure +* ( Structure Config to be load in DMA Registers). . +* +* Output : None. +* +* Return : None +*******************************************************************************/ + + +void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct) + +{ + + + + /* Select the DMA source peripheral request */ + DMA_Channelx->CCNF &= SRC_Mask; + DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Src; + + + /* Select the flow controller and the transfer type */ + DMA_Channelx->CCNF &= DMA_FlowCntrl_Mask; + DMA_Channelx->CCNF |=DMA_InitStruct->DMA_Channel_FlowCntrl; + + + /* Select the DMA Destination peripheral request*/ + DMA_Channelx->CCNF &= DES_Mask; + DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Des; + + /* Set the source address */ + DMA_Channelx->SRC = DMA_InitStruct-> DMA_Channel_SrcAdd ; + + + /* Set the destination address */ + + DMA_Channelx->DES = DMA_InitStruct->DMA_Channel_DesAdd ; + + + + /* Set the linked list Items address */ + DMA_Channelx->LLI = DMA_InitStruct->DMA_Channel_LLstItm ; + + + /* Set The Destination width */ + DMA_Channelx->CC &= DMA_Width_DES_MASK; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesWidth; + + + /* Set The Source width */ + DMA_Channelx->CC &= DMA_Width_SRC_MASK; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_SrcWidth; + + /* Set The Burst Size for the Destination */ + DMA_Channelx->CC &= DMA_Bst_DES_MASK; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesBstSize; + + /* Set The Burst Size for the Source */ + DMA_Channelx->CC &= DMA_Bst_SRC_MASK; + DMA_Channelx->CC |=DMA_InitStruct->DMA_Channel_SrcBstSize; + + + /* Initialize The Transfer Size for the Source */ + DMA_Channelx->CC &= DMA_TrsfSisze_Mask; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_TrsfSize; + + +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_emi.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_emi.c new file mode 100644 index 0000000..deadae8 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_emi.c @@ -0,0 +1,167 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_emi.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the EMI software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_emi.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* These constant variables are used as masks to handle the EMI registers. */ + +#define EMI_PageModeRead_TL_Mask 0xFFFFF3FF +#define EMI_PageModeRead_Sel_Mask 0xFFFFFEFF +#define EMI_MemWidth_Mask 0xFFFFFFCF +#define EMI_WriteProtect_Mask 0xFFFFFEF7 + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : EMI_DeInit +* Description : Deinitializes the EMI peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ + +void EMI_DeInit(void) +{ + + SCU_AHBPeriphReset(__EMI, ENABLE); /* EMI peripheral under Reset */ + SCU_AHBPeriphReset(__EMI,DISABLE ); /* EMI not under Reset */ + +} + +/******************************************************************************* +* Function Name : EMI_StructInit +* Description : Fills the EMI_InitTypeDef structure member with its reset +* value. +* Input : EMI_InitStruct : pointer to a EMI_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ + +void EMI_StructInit( EMI_InitTypeDef *EMI_InitStruct) +{ + + /* Number of bus turnaround cycles added between read and write accesses.*/ + /*This member can be 0x01,0x02,0x03, ....0xF (Reset value:0xF "15 cycles"*/ + + EMI_InitStruct->EMI_Bank_IDCY =0xF; + + + /* Number of wait states for read accesses*/ + /*This member can be: 0x01,0x02,0x03, ....0x1F (Reset value:0x1F "31 cycles"*/ + + EMI_InitStruct->EMI_Bank_WSTRD =0x1F; + + + /* Number of wait states for write accesses*/ + /*This member can be: 0x01,0x02,0x03, ....0x1F (Reset value:0x1F "31 cycles"*/ + + EMI_InitStruct->EMI_Bank_WSTWR =0x1F; + + /*Output enable assertion delay from chip select assertion*/ + /*This member can be: 0x01,0x02,0x03, ....0xF (Reset value:0x01 "1 cycle"*/ + + EMI_InitStruct->EMI_Bank_WSTROEN =0x01; + + + /*Write enable assertion delay from chip select assertion*/ + /*This member can be: 0x01,0x02,0x03, ....0xF (Reset value:0x00 "0 cycle"*/ + + EMI_InitStruct->EMI_Bank_WSTWEN =0x00; + + + /*This member Controls the memory width*/ + /*This member can be :"EMI_Width_Byte" = 8 bits width or "EMI_Width_HalfWord" = 16 bits width*/ + + EMI_InitStruct->EMI_Bank_MemWidth = EMI_Width_Byte; + + + /*Write protection feature */ + /*This member can be :"EMI_Bank_NonWriteProtect" = No write protection or "EMI_Bank_WriteProtect" = bank is write protected*/ + + EMI_InitStruct-> EMI_Bank_WriteProtection= EMI_Bank_NonWriteProtect; + + + /* page transfer length for page mode read */ + /*This member can be :"EMI_4Data" = 4 transfers burst or "EMI_8Data" = 8 transfers burst*/ + + EMI_InitStruct->EMI_PageModeRead_TransferLength= EMI_4Data; + + /*Select or deselect the page mode read*/ + /*This member can be :"EMI_NormalMode" =Normal Mode or "EMI_PageModeRead" = Page Mode Read*/ + + EMI_InitStruct->EMI_PageModeRead_Selection = EMI_NormalMode; + + +} + +/******************************************************************************* +* Function Name : EMI_Init +* Description : Initializes EMI peripheral according to the specified +* parameters in the EMI_InitStruct. + +* Input : EMI_Bankx:where x can be 0,1,2 or 3 to select the EMI Bank. + EMI_InitStruct: pointer to a EMI_InitTypeDef structure + ( Structure Config to be loaded in EMI Registers). . + +* Output : None +* Return : None +*******************************************************************************/ + +void EMI_Init( EMI_Bank_TypeDef* EMI_Bankx, EMI_InitTypeDef* EMI_InitStruct) + +{ + + EMI_Bankx->ICR = EMI_InitStruct-> EMI_Bank_IDCY ; + + EMI_Bankx->RCR = EMI_InitStruct->EMI_Bank_WSTRD ; + + EMI_Bankx->WCR = EMI_InitStruct->EMI_Bank_WSTWR ; + + EMI_Bankx->OECR = EMI_InitStruct->EMI_Bank_WSTROEN; + + EMI_Bankx->WECR = EMI_InitStruct->EMI_Bank_WSTWEN ; + + EMI_Bankx->BCR &= EMI_MemWidth_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_Bank_MemWidth; + + EMI_Bankx->BCR &= EMI_WriteProtect_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_Bank_WriteProtection; + + EMI_Bankx->BCR &= EMI_PageModeRead_TL_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_PageModeRead_TransferLength; + + EMI_Bankx->BCR &= EMI_PageModeRead_Sel_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_PageModeRead_Selection; + + +} + + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_fmi.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_fmi.c new file mode 100644 index 0000000..fb558ad --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_fmi.c @@ -0,0 +1,519 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the FMI software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_fmi.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define TIMEOUT 0xFFFFFF /* Timeout value */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/******************************************************************************* +* Function Name : FMI_BankRemapConfig +* Description : Configure the addresses and sizes of bank 0 and bank 1. +* Input1 : FMI_BootBankSize: specifies the boot bank size. +* This parameter can be one of the following values: +* - 0x0: 32KBytes. +* - 0x1: 64KBytes. +* - 0x2: 128KBytes. +* - 0x3: 256KBytes. +* - 0x4: 512KBytes. +* .... +* - 0xB: 64MBytes. +* Input2 : FMI_NonBootBankSize: specifies the non boot bank size. +* This parameter can be one of the following values: +* - 0x0: 8KBytes. +* - 0x1: 16KBytes. +* - 0x2: 32KBytes. +* - 0x3: 64KBytes. +* .... +* - 0xD: 64MBytes. +* Input3 : FMI_BootBankAddress: specifies the address of the boot bank. +* Input4 : FMI_NonBootBankAddress: specifies the address of the non +* boot bank. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress) +{ + FMI->BBSR = FMI_BootBankSize; + FMI->NBBSR = FMI_NonBootBankSize; + FMI->BBADR = (FMI_BootBankAddress >> 2); + FMI->NBBADR = (FMI_NonBootBankAddress >> 2); + FMI->CR |= 0x18; /* Enable bank 1 */ +} + +/******************************************************************************* +* Function Name : FMI_Config +* Description : Configure the FMI. +* Input1 : FMI_ReadWaitState: specifies the needed read wait states. +* This parameter can be one of the following values: +* - FMI_READ_WAIT_STATE_1: One read wait state. +* - FMI_READ_WAIT_STATE_2: Two read wait states. +* - FMI_READ_WAIT_STATE_3: Three read wait states. +* Input2 : FMI_WriteWaitState: specifies the needed write wait states. +* This parameter can be one of the following values: +* - FMI_WRITE_WAIT_STATE_1: One write wait state. +* - FMI_WRITE_WAIT_STATE_2: Two write wait states. +* Input3 : FMI_PWD: specifies the power down mode status. +* This parameter can be one of the following values: +* - FMI_PWD_ENABLE: Enable the PWD. +* - FMI_PWD_DISABLE: Disable the PWD. +* Input4 : FMI_LVDEN: specifies the low voltage detector status. +* This parameter can be one of the following values: +* - FMI_LVD_ENABLE: Enable the LVD. +* - FMI_LVD_DISABLE: Disable the LVD. +* Input5 : FMI_FreqRange: specifies the working frequency range. +* This parameter can be one of the following values: +* - FMI_FREQ_LOW: Low working frequency (up to 66MHz). +* - FMI_FREQ_HIGH: High working frequency (above 66MHz) . +* Output : None +* Return : None +*******************************************************************************/ +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange) +{ + /* Configure the write wait state value */ + if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1) + { + FMI->CR |= FMI_WRITE_WAIT_STATE_1; + } + else + { + FMI->CR &= FMI_WRITE_WAIT_STATE_0; + } + + /* Write a write flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x60; + + /* Configure the flash configuration register */ + *(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03; +} + +/******************************************************************************* +* Function Name : FMI_EraseSector +* Description : Erase the needed sector. +* Input : FMI_Sector: specifies the sector to be erased. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseSector(vu32 FMI_Sector) +{ + /* Write an erase set-up command to the sector */ + *(vu16 *)FMI_Sector = 0x20; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Sector = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_EraseBank +* Description : Erase the needed bank. +* Input : FMI_Bank: specifies the bank to be erased. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseBank(vu32 FMI_Bank) +{ + /* Write a bank erase set-up command to the bank */ + *(vu16 *)FMI_Bank = 0x80; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_WriteHalfWord +* Description : Write a halfword to the needed Flash memory address. +* Input 1 : FMI_Address: specifies the address offset where the data will +* be written. +* Input 2 : FMI_Data: the needed data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data) +{ + /* Write a program command to the sector to be written */ + *(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40; + + /* Write the halfword to the destination address */ + *(vu16 *)FMI_Address = FMI_Data; +} + +/******************************************************************************* +* Function Name : FMI_WriteOTPHalfWord +* Description : Write a halfword to the needed OTP sector address. +* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset +* where the data will be written. +* This parameter can be one of the following values: +* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0. +* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0. +* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1. +* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1. +* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2. +* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2. +* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3. +* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3. +* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4. +* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4. +* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5. +* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5. +* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6. +* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6. +* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7. +* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7. +* Input 2 : FMI_OTPData: The needed OTP data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData) +{ + /* Write a write OTP command to the needed address */ + *(vu16 *)(FMI_BANK_1) = 0xC0; + + /* Write the halfword to the destination address */ + *(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData; +} + +/******************************************************************************* +* Function Name : FMI_ReadWord +* Description : Read the correspondent data. +* Input : FMI_Address: specifies the needed address. +* Output : None +* Return : The data contained in the specified address. +*******************************************************************************/ +u32 FMI_ReadWord(u32 FMI_Address) +{ + return(*(u32*)FMI_Address); +} + +/******************************************************************************* +* Function Name : FMI_ReadOTPData +* Description : Read data from the OTP sector. +* Input : FMI_OTPAddress: specifies the address of the data to be read. +* This parameter can be one of the following values: +* - FMI_OTP_WORD_0: FMI bank 0 sector 0. +* - FMI_OTP_WORD_1: FMI bank 0 sector 1. +* - FMI_OTP_WORD_2: FMI bank 0 sector 2. +* - FMI_OTP_WORD_3: FMI bank 0 sector 3. +* - FMI_OTP_WORD_4: FMI bank 0 sector 4. +* - FMI_OTP_WORD_5: FMI bank 0 sector 5. +* - FMI_OTP_WORD_6: FMI bank 0 sector 6. +* - FMI_OTP_WORD_7: FMI bank 0 sector 7. +* Output : None +* Return : The needed OTP words. +*******************************************************************************/ +u32 FMI_ReadOTPData(u8 FMI_OTPAddress) +{ + u32 OTP_Data = 0x0; + /* write a read OTP sector command */ + *(vu16 *)(FMI_BANK_1) = 0x98; + + /* Read the correspondent data */ + OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress)); + + /* Write a read array command */ + *(vu16 *)(FMI_BANK_1) = 0xFF; + + return OTP_Data; +} + +/******************************************************************************* +* Function Name : FMI_GetFlagStatus +* Description : Check whether the specified FMI flag is set or not. +* Input1 : FMI_Flag: flag to check. +* This parameter can be one of the following values: +* - FMI_FLAG_SPS: Sector Protection Status Flag. +* - FMI_FLAG_PSS: Program Suspend Status Flag. +* - FMI_FLAG_PS: Program Status Flag. +* - FMI_FLAG_ES: Erase Status Flag. +* - FMI_FLAG_ESS: Erase Suspend Status Flag. +* - FMI_FLAG_PECS: FPEC Status Flag. +* Input2 : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank) +{ + u16 FMI_Status_Register = 0; + + /* Write a read status register command */ + *(vu16 *)FMI_Bank = 0x70; + + /* Wait until operation completion */ + while(!((*(vu16 *)FMI_Bank) & 0x80)); + + /* Read the status register */ + FMI_Status_Register = *(vu16 *)FMI_Bank; + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if((FMI_Status_Register & FMI_Flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_GetReadWaitStateValue +* Description : Get the current Read wait state value. +* Input : None +* Output : None +* Return : The current read wait states value. +*******************************************************************************/ +u16 FMI_GetReadWaitStateValue(void) +{ + u16 FMI_Configuration_Register = 0; + /* Write a read flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash configuration register */ + FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3; + + /* Return the wait states value */ + return FMI_Configuration_Register; +} + +/******************************************************************************* +* Function Name : FMI_GetWriteWaitStateValue +* Description : Get the current write wait state value. +* Input : None +* Output : None +* Return : The current write wait states value. +*******************************************************************************/ +u16 FMI_GetWriteWaitStateValue(void) +{ + return ((u16)((FMI->CR & 0x100) >> 8)); +} + +/******************************************************************************* +* Function Name : FMI_SuspendEnable +* Description : Suspend command enable. +* Input : FMI_Bank: specifies the bank to be suspended. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_SuspendEnable(vu32 FMI_Bank) +{ + /* Write a suspend command to the bank */ + *(vu16 *)FMI_Bank = 0xB0; +} + +/******************************************************************************* +* Function Name : FMI_ResumeEnable +* Description : Resume the suspended command. +* Input : FMI_Bank: specifies the suspended bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ResumeEnable(vu32 FMI_Bank) +{ + /* Write a resume command to the bank */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_ClearFlag +* Description : Clear the FMI Flags on the correspondent bank. +* Input : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ClearFlag(vu32 FMI_Bank) +{ + /* Write a clear status register command */ + *(vu16 *)FMI_Bank = 0x50; +} + +/******************************************************************************* +* Function Name : FMI_WriteProtectionCmd +* Description : Enable or disable the write protection for the needed sector. +* Input1 : FMI_Sector: specifies the sector to be protected or +* unprotected. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Input2 : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: Enable the protection. +* - DISABLE: Disable the protection. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState) +{ + if (FMI_NewState == ENABLE) + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0x01; + *(vu16*)FMI_Sector = 0xFF; + } + else /* DISABLE */ + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0xD0; + *(vu16*)FMI_Sector = 0xFF; + } +} + +/******************************************************************************* +* Function Name : FMI_GetWriteProtectionStatus +* Description : Get the write protection status for the needed sector. +* Input : FMI_Sector_Mask: specifies the needed sector mask. +* This parameter can be one of the following values: +* - FMI_B0S0_MASK: FMI bank 0 sector 0. +* - FMI_B0S1_MASK: FMI bank 0 sector 1. +* - FMI_B0S2_MASK: FMI bank 0 sector 2. +* - FMI_B0S3_MASK: FMI bank 0 sector 3. +* - FMI_B0S4_MASK: FMI bank 0 sector 4. +* - FMI_B0S5_MASK: FMI bank 0 sector 5. +* - FMI_B0S6_MASK: FMI bank 0 sector 6. +* - FMI_B0S7_MASK: FMI bank 0 sector 7. +* - FMI_B1S0_MASK: FMI bank 1 sector 0. +* - FMI_B1S1_MASK: FMI bank 1 sector 1. +* - FMI_B1S2_MASK: FMI bank 1 sector 2. +* - FMI_B1S3_MASK: FMI bank 1 sector 3. +* Output : None +* Return : The Protection Status of the needed sector. +* - RESET: The needed sector is not write protected. +* - SET : The needed sector is write protected. +*******************************************************************************/ +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask) +{ + u16 Protection_Level_1_Register = 0; + /* Write a read flash protection level 1 register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash protection level 1 register */ + Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + if (Protection_Level_1_Register &= FMI_Sector_Mask) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_WaitForLastOperation +* Description : Wait until the last operation (Write halfword, Write OTP +* halfword, Erase sector and Erase bank) completion. +* Input : FMI_Bank: specifies the bank where the operation is on going. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : The timeout status. +* This parameter can be one of the following values: +* - FMI_TIME_OUT_ERROR: Timeout error occurred. +* - FMI_NO_TIME_OUT_ERROR: No timeout error. +*******************************************************************************/ +u8 FMI_WaitForLastOperation(vu32 FMI_Bank) +{ + u32 Time_Out = 0; + + /* Write a read status register command */ + *(vu16 *)(FMI_Bank) = 0x70; + + /* Wait until operation compeletion */ + while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT )) + { + Time_Out ++; /* Time Out */ + } + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if (Time_Out == TIMEOUT) + { + return FMI_TIME_OUT_ERROR; + } + else + { + return FMI_NO_TIME_OUT_ERROR; + } +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_gpio.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_gpio.c new file mode 100644 index 0000000..f2d0941 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_gpio.c @@ -0,0 +1,407 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the GPIO software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_gpio.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + + /* Reset the GPIO registers values */ + if(GPIOx == GPIO0) + { + SCU_APBPeriphReset(__GPIO0,ENABLE); + SCU_APBPeriphReset(__GPIO0,DISABLE); + SCU->GPIOTYPE[0x00] = 0x0000 ; + SCU->GPIOOUT[0x00] = 0x0000; + SCU->GPIOIN[0x00] = 0x0000; + } + + if(GPIOx == GPIO1) + { + SCU_APBPeriphReset(__GPIO1,ENABLE); + SCU_APBPeriphReset(__GPIO1,DISABLE); + SCU->GPIOTYPE[0x01] = 0x0000 ; + SCU->GPIOOUT[0x01] = 0x0000; + SCU->GPIOIN[0x01] = 0x0000; + } + + if(GPIOx == GPIO2) + { + SCU_APBPeriphReset(__GPIO2,ENABLE); + SCU_APBPeriphReset(__GPIO2,DISABLE); + SCU->GPIOTYPE[0x02] = 0x0000 ; + SCU->GPIOOUT[0x02] = 0x0000; + SCU->GPIOIN[0x02] = 0x0000; + } + + if(GPIOx == GPIO3) + { + SCU_APBPeriphReset(__GPIO3,ENABLE); + SCU_APBPeriphReset(__GPIO3,DISABLE); + SCU->GPIOTYPE[0x03] = 0x0000 ; + SCU->GPIOOUT[0x03] = 0x0000; + SCU->GPIOIN[0x03] = 0x0000; + } + + if(GPIOx == GPIO4) + { + SCU_APBPeriphReset(__GPIO4,ENABLE); + SCU_APBPeriphReset(__GPIO4,DISABLE); + SCU->GPIOTYPE[0x04] = 0x0000 ; + SCU->GPIOOUT[0x04] = 0x0000; + SCU->GPIOIN[0x04] = 0x0000; + SCU->GPIOANA = 0x00; + } + + if(GPIOx == GPIO5) + { + SCU_APBPeriphReset(__GPIO5,ENABLE); + SCU_APBPeriphReset(__GPIO5,DISABLE); + SCU->GPIOTYPE[0x05] = 0x0000 ; + SCU->GPIOOUT[0x05] = 0x0000; + SCU->GPIOIN[0x05] = 0x0000; + } + + if(GPIOx == GPIO6) + { + SCU_APBPeriphReset(__GPIO6,ENABLE); + SCU_APBPeriphReset(__GPIO6,DISABLE); + SCU->GPIOTYPE[0x06] = 0x0000 ; + SCU->GPIOOUT[0x06] = 0x0000; + SCU->GPIOIN[0x06] = 0x0000; + } + + if(GPIOx == GPIO7) + { + SCU_APBPeriphReset(__GPIO7,ENABLE); + SCU_APBPeriphReset(__GPIO7,DISABLE); + SCU->GPIOOUT[0x07] = 0xAAAA; + SCU->GPIOOUT[0x07] = 0x0000; + SCU->GPIOIN[0x07] = 0x0000; + } + + if(GPIOx == GPIO8) + { + SCU_APBPeriphReset(__GPIO8,ENABLE); + SCU_APBPeriphReset(__GPIO8,DISABLE); + SCU->GPIOEMI = 0x00; + } + + if(GPIOx == GPIO9) + { + SCU_APBPeriphReset(__GPIO9,ENABLE); + SCU_APBPeriphReset(__GPIO9,DISABLE); + SCU->GPIOEMI = 0x00; + } +} +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct . +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Select pin direction */ + u8 PinNumber = 0; + u8 Counter = 0; + u8 GPIO_Number = 0; + + GPIO_Number = GPIO_GetGPIONumber(GPIOx); + + + if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput) + { + GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin; + } + else + { + GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin; + } + + for (Counter = 0; Counter < 8;Counter++) + { + /*Search pin number*/ + PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <> Counter) == 1) + { + /*Output ALternate 0*/ + SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2)); + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1) + { + /*Output ALternate 1*/ + SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2) + { + /*Output ALternate 2*/ + SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3) + { + /*Output ALternate 3*/ + SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2); + } + + /*Type configuration: PushPull or Open Collector*/ + SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector) + { + /*Open Drain configuration*/ + SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter; + } + + /*IP Connected disable*/ + SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable) + { + /*IP Connected enable*/ + SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter; + } + } + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Initialize the GPIO Init Structure parameters +* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Direction = GPIO_PinInput; + GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull; + GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable; + GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1; +} + +/******************************************************************************* +* Function Name : GPIO_ReadBit +* Description : Reads the specified port pin +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* Output : None +* Return : The port pin value +*******************************************************************************/ +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin) +{ + if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET ) + { + return Bit_SET; + } + else + { + return Bit_RESET; + } +} + +/******************************************************************************* +* Function Name : GPIO_Read +* Description : Reads the specified GPIO data port +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO data port word value. +*******************************************************************************/ +u8 GPIO_Read(GPIO_TypeDef* GPIOx) +{ + return (GPIOx->DR[0x3FC]); +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* - BitVal: this parameter specifies the value to be written +* to the selected bit. +* BitVal must be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal) +{ + if(BitVal == Bit_SET) + { + GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin; + } + else + { + GPIOx->DR[GPIO_Pin <<2] = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes the passed value in the selected data GPIOx port +* register. +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - PortVal: the value to be written to the data port register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal) +{ + GPIOx->DR[0x3FC] = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_EMIConfig +* Description : Enables or disables GPIO 8 and 9 in EMI mode. +* Input : - NewState: new state of the EMI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EMIConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SCU->GPIOEMI = 0x01; + } + else + { + SCU->GPIOEMI = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_ANAPinConfig +* Description : Enables or disables pins from GPIO 4 in Analogue mode. +* Input :- GPIO_ANAChannel: selects the ADC channel pin. +* This parameter can be one of the following values: +* GPIO_ANAChannel0 +* GPIO_ANAChannel1 +* GPIO_ANAChannel2 +* GPIO_ANAChannel3 +* GPIO_ANAChannel4 +* GPIO_ANAChannel5 +* GPIO_ANAChannel6 +* GPIO_ANAChannel7 +* GPIO_ANAChannelALL +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState) +{ + + if(NewState == ENABLE) + { + if(GPIO_ANAChannel == GPIO_ANAChannelALL) + { + SCU->GPIOOUT[4] = 0x0000; + SCU->GPIOIN[4] = 0x00; + } + else + { + SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1)); + SCU->GPIOIN[4] &= ~GPIO_ANAChannel; + } + SCU->GPIOANA |= GPIO_ANAChannel; + + } + else + { + SCU->GPIOANA &= ~GPIO_ANAChannel; + } +} + +/******************************************************************************* +* Function Name : GPIO_GetGPIONumber +* Description : searche the GPIO number. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO number +*******************************************************************************/ +u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx) +{ + + if(GPIOx == GPIO1) + { + return 1; + } + if(GPIOx == GPIO2) + { + return 2; + } + if(GPIOx == GPIO3) + { + return 3; + } + if(GPIOx == GPIO4) + { + return 4; + } + if(GPIOx == GPIO5) + { + return 5; + } + if(GPIOx == GPIO6) + { + return 6; + } + if(GPIOx == GPIO7) + { + return 7; + } + if(GPIOx == GPIO8) + { + return 8; + } + if(GPIOx == GPIO9) + { + return 9; + } + return 0; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_i2c.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_i2c.c new file mode 100644 index 0000000..9f15adb --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_i2c.c @@ -0,0 +1,616 @@ +/******************** (C) COPYRIGHT 2005 STMicroelectronics ******************** +* File Name : 91x_i2c.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the I2C software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_i2c.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* I2C IT enable */ +#define I2C_IT_Enable 0x01 +#define I2C_IT_Disable 0xFE + +/* I2C Peripheral Enable/Disable */ +#define I2C_PE_Set 0x20 +#define I2C_PE_Reset 0xDF + +/* Address direction bit */ +#define I2C_ADD0_Set 0x01 +#define I2C_ADD0_Reset 0xFE + +/* I2C START Enable/Disable */ +#define I2C_Start_Enable 0x08 +#define I2C_Start_Disable 0xF7 + +/* I2C STOP Enable/Disable */ +#define I2C_Stop_Enable 0x02 +#define I2C_Stop_Disable 0xFD + +/* I2C Masks */ +#define I2C_Frequency_Mask 0x1F +#define I2C_AddressHigh_Mask 0xF9 +#define I2C_OwnAddress_Mask 0x0300 +#define I2C_StandardMode_Mask 0x7f +#define I2C_FastMode_Mask 0x80 +#define I2C_Event_Mask 0x3FFF +#define I2C_HeaderSet_Mask 0xF1 +#define I2C_HeaderReset_Mask 0xFE + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : I2C_DeInit +* Description : Deinitializes the I2C peripheral registers to their default +* reset values. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + if (I2Cx == I2C0) + { + /* Reset the I2C0 registers values */ + SCU_APBPeriphReset(__I2C0, ENABLE); + SCU_APBPeriphReset(__I2C0, DISABLE); + } + if (I2Cx == I2C1) + { + /* Reset the I2C1 registers values */ + SCU_APBPeriphReset(__I2C1, ENABLE); + SCU_APBPeriphReset(__I2C1, DISABLE); + } +} + +/******************************************************************************* +* Function Name : I2C_Init +* Description : Initializes the I2C peripheral according to the specified +* parameters in the I2C_InitTypeDef structure. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* +* - I2C_InitStruct: pointer to an I2C_InitTypeDef structure that +* contains the configuration information for the specified I2C +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u16 wResult = 0x0F; + u32 dPCLK = 25000000; + + /* Get PCLK frequency value */ + dPCLK = SCU_GetPCLKFreqValue()*1000; + /* Disable I2C peripheral to set FR[2:0] bits */ + I2C_Cmd (I2Cx, DISABLE); + /* Clear frequency FR[2:0] bits */ + I2Cx->OAR2 &= I2C_Frequency_Mask; + /* Set frequency bits depending on PCLK value */ + if ((dPCLK <1667000) & (dPCLK > 10000000)) + I2Cx->OAR2 |= 0x20; + else if (dPCLK < 26670000) + I2Cx->OAR2 |= 0x40; + else if (dPCLK < 40000000) + I2Cx->OAR2 |= 0x60; + else if (dPCLK < 53330000) + I2Cx->OAR2 |= 0x80; + else if (dPCLK < 66000000) + I2Cx->OAR2 |= 0xA0; + else if (dPCLK < 80000000) + I2Cx->OAR2 |= 0xC0; + else if (dPCLK < 100000000) + I2Cx->OAR2 |= 0xE0; + I2C_Cmd (I2Cx, ENABLE); + + /* Configure general call */ + if (I2C_InitStruct->I2C_GeneralCall == I2C_GeneralCall_Enable) + { + /* Enable general call */ + I2Cx->CR |= I2C_GeneralCall_Enable; + } + else + { + /* Disable general call */ + I2Cx->CR &= I2C_GeneralCall_Disable; + } + /* Configure acknowledgement */ + if (I2C_InitStruct->I2C_Ack == I2C_Ack_Enable) + { + /* Enable acknowledgement */ + I2Cx->CR |= I2C_Ack_Enable; + } + else + { + /* Disable acknowledgement */ + I2Cx->CR &= I2C_Ack_Disable; + } + + /* Configure LSB own address */ + I2Cx->OAR1 = I2C_InitStruct->I2C_OwnAddress; + /* Clear MSB own address ADD[9:8] bits */ + I2Cx->OAR2 &= I2C_AddressHigh_Mask; + /* Set MSB own address value */ + I2Cx->OAR2 |= (I2C_InitStruct->I2C_OwnAddress & I2C_OwnAddress_Mask)>>7; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_CLKSpeed <= 100000) + { + /* Standard mode speed calculate */ + wResult = ((dPCLK/I2C_InitStruct->I2C_CLKSpeed)-7)/2; + /* Set speed value and clear FM/SM bit for standard mode in LSB clock divider */ + I2Cx->CCR = wResult & I2C_StandardMode_Mask; + } + /* Configure speed in fast mode */ + else if (I2C_InitStruct->I2C_CLKSpeed <= 400000) + { + /* Fast mode speed calculate */ + wResult = ((dPCLK/I2C_InitStruct->I2C_CLKSpeed)-9)/3; + /* Set speed value and set FM/SM bit for fast mode in LSB clock divider */ + I2Cx->CCR = wResult | I2C_FastMode_Mask; + } + /* Set speed in MSB clock divider */ + I2Cx->ECCR = wResult >>7; +} + +/******************************************************************************* +* Function Name : I2C_StructInit +* Description : Initialize the I2C Init Structure parameters +* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /* Initialize the I2C_CLKSpeed member */ + I2C_InitStruct->I2C_CLKSpeed = 5000; + + /* Initialize the I2C_OwnAddress member */ + I2C_InitStruct->I2C_OwnAddress = 0x0; + + /* Initialize the I2C_GeneralCall member */ + I2C_InitStruct->I2C_GeneralCall = I2C_GeneralCall_Disable; + + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; +} + +/******************************************************************************* +* Function Name : I2C_Cmd +* Description : Enables or disables the specified I2C peripheral. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - NewState: new state of the I2C peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C peripheral by setting twice the PE bit on the CR register */ + I2Cx->CR |= I2C_PE_Set; + I2Cx->CR |= I2C_PE_Set; + } + else + { + /* Disable the I2C peripheral */ + I2Cx->CR &= I2C_PE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTART +* Description : Generates I2C communication START condition. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* +* - NewState: new state of the Start condition. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateStart(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a START condition */ + I2Cx->CR |= I2C_Start_Enable; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR &= I2C_Start_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTOP +* Description : Generates I2C communication STOP condition. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* +* - NewState: new state of the Stop condition. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a SIOP condition */ + I2Cx->CR |= I2C_Stop_Enable; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR &= I2C_Stop_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_AcknowledgeConfig +* Description : Enables or disables I2C acknowledge feature. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - NewState: new state of the Acknowledgement. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR |= I2C_Ack_Enable; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR &= I2C_Ack_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_ITConfig +* Description : Enables or disables I2C interrupt feature. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - NewState: new state of the specified I2C interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_ITConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C interrupt */ + I2Cx->CR |= I2C_IT_Enable; + } + else + { + /* Disable the I2C interrupt */ + I2Cx->CR &= I2C_IT_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_ReadRegister +* Description : Reads any I2C register and returns its value. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_Register: the I2C register to be read. This parameter +* can be one of the following values: +* - I2C_CR: CR register. +* - I2C_SR1: SR1 register. +* - I2C_SR2: SR2 register. +* - I2C_CCR: CCR register. +* - I2C_OAR1: OAR1 register. +* - I2C_OAR2: OAR2 register. +* - I2C_DR: DR register. +* - I2C_ECCR: ECCR register. +* Output : None +* Return : The value of the register passed as parameter +*******************************************************************************/ +u8 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + /* Return the selected register value */ + if (I2Cx == I2C0) + { + return (*(u8 *)(I2C0_BASE + I2C_Register)); + } + if (I2Cx == I2C1) + { + return (*(u8 *)(I2C1_BASE + I2C_Register)); + } + return 0; +} + +/******************************************************************************* +* Function Name : I2C_GetFlagStatus +* Description : Checks whether the specified I2C flag is set or not. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_FLAG: flag to check. This parameter can be one of the +* following values: +* - I2C_FLAG_SB: Start bit flag +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Adress matched flag +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* Output : None +* Return : The NewState of the I2C_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u16 I2C_FLAG) +{ + u16 wFlag1=0, wFlag2=0, wTmp=0; + + wFlag1 = I2Cx->SR2; + wFlag1 = wFlag1<<8; + wFlag2 = I2Cx->CR & 0x04; + + /* Get all the I2C flags in a unique register*/ + wTmp = (((I2Cx->SR1 | (wFlag1)) & I2C_Event_Mask) | (wFlag2<<12)); + + /* Check the status of the specified I2C flag */ + if((wTmp & I2C_FLAG) != RESET) + { + /* Return SET if I2C_FLAG is set */ + return SET; + } + else + { + /* Return RESET if I2C_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : I2C_ClearFlag +* Description : Clears the I2C Flag passed as a parameter +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_FLAG: flag to check. This parameter can be one of the +* following values: +* - I2C_FLAG_SB: Start bit flag +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Adress matched flag +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* - parameter needed in the case that the flag to be cleared +* need a write in one register +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u16 I2C_FLAG, ...) +{ + u8 bTmp = (u8)*((u32 *) & I2C_FLAG + sizeof(I2C_FLAG)); + + /* flags that need a read of the SR2 register to be cleared */ + if ((I2C_FLAG==I2C_FLAG_ADD10) || (I2C_FLAG==I2C_FLAG_EVF) || (I2C_FLAG==I2C_FLAG_BERR) || (I2C_FLAG==I2C_FLAG_ARLO) | + (I2C_FLAG==I2C_FLAG_STOPF) ||(I2C_FLAG==I2C_FLAG_AF) || (I2C_FLAG==I2C_FLAG_ENDAD)) + { + /* Read the SR2 register */ + I2Cx->SR2; + + /* Two flags need a second step to be cleared */ + switch (I2C_FLAG) + { + case I2C_FLAG_ADD10: + /* Send the MSB 10bit address passed as second parameter */ + I2Cx->DR = bTmp; + break; + case I2C_FLAG_ENDAD: + /* Write to the I2C_CR register by setting PE bit */ + I2Cx->CR |= I2C_PE_Set; + break; + } + } + + /* flags that need a read of the SR1 register to be cleared */ + else if (I2C_FLAG==I2C_FLAG_SB || I2C_FLAG==I2C_FLAG_ADSL || I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* three flags need a second step to be cleared */ + if (I2C_FLAG == I2C_FLAG_SB) + { + /* Send the address byte passed as second parameter */ + I2Cx->DR = bTmp; + } + else if (I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* return the received byte in the variable passed as second parameter */ + bTmp=I2Cx->DR; + } + } + + /* flags that need to disable the I2C interface */ + else if ( I2C_FLAG==I2C_FLAG_M_SL || I2C_FLAG==I2C_FLAG_GCAL) + { + I2C_Cmd(I2Cx, DISABLE); + I2C_Cmd(I2Cx, ENABLE); + } +} + +/******************************************************************************* +* Function Name : I2C_Send7bitAddress +* Description : Transmits the address byte to select the slave device. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - Address: specifies the slave address which will be transmitted +* - Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. This parameter can be one of the +* following values +* - I2C_MODE_TRANSMITTER: Transmitter mode +* - I2C_MODE_RECEIVER: Receiver mode +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 Direction) +{ + /* Test on the direction to define the read/write bit */ + if (Direction == I2C_MODE_RECEIVER) + { + /* Set the address bit0 for read */ + Address |= I2C_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= I2C_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/******************************************************************************* +* Function Name : I2C_SendData +* Description : Send a data byte. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - bData : the byte to be sent +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, u8 bData) +{ + /* Write in the DR register the byte to be sent */ + I2Cx->DR = bData; +} + +/******************************************************************************* +* Function Name : I2C_ReceiveData +* Description : Read the received byte. +* Input : - I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* Output : None +* Return : The received byte +*******************************************************************************/ +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Return from the DR register the received byte */ + return I2Cx->DR; +} + +/******************************************************************************* +* Function Name : I2C_GetLastEvent +* Description : Get the Last happened I2C Event. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* Output : None +* Return : The Last happened Event. +*******************************************************************************/ +u16 I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + u16 wFlag1=0, wLastEvent=0; + wFlag1 = I2Cx->SR2; + wFlag1 = wFlag1<<8; + /* Get the last event value from I2C status register */ + wLastEvent = (((I2Cx->SR1 | (wFlag1)) & I2C_Event_Mask)); + /* Return the last event */ + return wLastEvent; +} + +/******************************************************************************* +* Function Name : I2C_CheckEvent +* Description : Checks whether the Last I2C Event is equal to the one passed +* as parameter. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_EVENT: the event to check. This parameter can be one of +* the following values: +* - I2C_EVENT_SLAVE_ADDRESS_MATCHED +* - I2C_EVENT_SLAVE_BYTE_RECEIVED +* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED +* - I2C_EVENT_MASTER_MODE_SELECT +* - I2C_EVENT_MASTER_MODE_SELECTED +* - I2C_EVENT_MASTER_BYTE_RECEIVED +* - I2C_EVENT_MASTER_BYTE_TRANSMITTED +* - I2C_EVENT_MASTER_MODE_ADDRESS10 +* - I2C_EVENT_SLAVE_STOP_DETECTED +* - I2C_EVENT_SLAVE_ACK_FAILURE +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Last event is equal to the I2C_Event +* - ERROR: Last event is different from the I2C_Event +*******************************************************************************/ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,u16 I2C_EVENT) +{ + u16 wLastEvent = I2C_GetLastEvent(I2Cx); + + /* Check whther the last event is equal to I2C_EVENT */ + if (wLastEvent == I2C_EVENT) + { + /* Return SUCCESS when last event is equal to I2C_EVENT */ + return SUCCESS; + } + else + { + /* Return ERROR when last event is different from I2C_EVENT */ + return ERROR; + } +} + +/******************* (C) COPYRIGHT 2005 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_lib.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_lib.c new file mode 100644 index 0000000..3fab413 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_lib.c @@ -0,0 +1,281 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all peripherals pointers + : initialization. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#define EXT + +/* Standard include ----------------------------------------------------------*/ +#include "91x_map.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#ifdef LIBDEBUG + +/******************************************************************************* +* Function Name : debug +* Description : this function initialize peripherals pointers +* Input : no one +* Output : no one +* Return : no one +*******************************************************************************/ +void libdebug(void) +{ + + +/************************* DMA *************************/ + +#ifdef _DMA + DMA = (DMA_TypeDef *)DMA_BASE; +#endif /* _DMA */ + +/************************* DMA *************************/ + + +#ifdef _DMA_Channel0 + DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE; +#endif /* _DMA_Channel0 */ + +#ifdef _DMA_Channel1 + DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE; +#endif /* _DMA_Channel1 */ + +#ifdef _DMA_Channel2 + DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE; +#endif /* _DMA_Channel2 */ + +#ifdef _DMA_Channel3 + DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE; +#endif /* _DMA_Channel3 */ + +#ifdef _DMA_Channel4 + DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE; +#endif /* _DMA_Channel4 */ + +#ifdef _DMA_Channel5 + DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE; +#endif /* _DMA_Channel5*/ + + +#ifdef _DMA_Channel6 + DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE; +#endif /* _DMA_Channel6 */ + +#ifdef _DMA_Channel7 + DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE; +#endif /* _DMA_Channel7 */ + + + + /************************* EMI *************************/ + +#ifdef _EMI_Bank0 + EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE; +#endif /* _EMI_Bank0 */ + +#ifdef _EMI_Bank1 + EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE; +#endif /* _EMI_Bank1 */ + +#ifdef _EMI_Bank2 + EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE; +#endif /* _EMI_Bank2 */ + +#ifdef _EMI_Bank3 + EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE; + #endif /* _EMI_Bank3 */ + + + +/************************* AHBAPB *************************/ + +#ifdef _AHBAPB0 + AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE; +#endif /* _AHBAPB0 */ + +#ifdef _AHBAPB1 + AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE; +#endif /*_AHBAPB1 */ + + + +/************************* FMI *************************/ + +#ifdef _FMI + FMI = (FMI_TypeDef *)FMI_BASE; +#endif /* _FMI */ + +/************************* VIC *************************/ + +#ifdef _VIC0 + VIC0 = (VIC_TypeDef *)VIC0_BASE; +#endif /* _VIC0 */ + +#ifdef _VIC1 + VIC1 = (VIC_TypeDef *)VIC1_BASE; +#endif /* _VIC1 */ + +/************************* WIU *************************/ + +#ifdef _WIU + WIU = (WIU_TypeDef *)WIU_BASE; +#endif /* _WIU */ + +/************************* TIM *************************/ + +#ifdef _TIM0 + TIM0 = (TIM_TypeDef *)TIM0_BASE; +#endif /* _TIM0 */ + +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *)TIM1_BASE; +#endif /* _TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *)TIM2_BASE; +#endif /* _TIM2 */ + +#ifdef _TIM3 + TIM3 = (TIM_TypeDef *)TIM3_BASE; +#endif /* _TIM3 */ + +/************************* GPIO ************************/ + +#ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; +#endif /* _GPIO0 */ + +#ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; +#endif /* _GPIO1 */ + +#ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; +#endif /* _GPIO2 */ + +#ifdef _GPIO3 + GPIO3 = (GPIO_TypeDef *)GPIO3_BASE; +#endif /* _GPIO3 */ + +#ifdef _GPIO4 + GPIO4 = (GPIO_TypeDef *)GPIO4_BASE; +#endif /* _GPIO4 */ + +#ifdef _GPIO5 + GPIO5 = (GPIO_TypeDef *)GPIO5_BASE; +#endif /* _GPIO5 */ + +#ifdef _GPIO6 + GPIO6 = (GPIO_TypeDef *)GPIO6_BASE; +#endif /* _GPIO6 */ + +#ifdef _GPIO7 + GPIO7 = (GPIO_TypeDef *)GPIO7_BASE; +#endif /* _GPIO7 */ + +#ifdef _GPIO8 + GPIO8 = (GPIO_TypeDef *)GPIO8_BASE; +#endif /* _GPIO8 */ + +#ifdef _GPIO9 + GPIO9 = (GPIO_TypeDef *)GPIO9_BASE; +#endif /* _GPIO9 */ + +/************************* RTC *************************/ + +#ifdef _RTC + RTC = (RTC_TypeDef *)RTC_BASE; +#endif /* _RTC */ + +/************************* PRCCU ***********************/ + +#ifdef _SCU + SCU = (SCU_TypeDef *)SCU_BASE; +#endif /* _PRCCU */ + +/************************** MC *************************/ + +#ifdef _MC + MC = (MC_TypeDef *)MC_BASE; +#endif /* _MC */ + +/************************* UART ************************/ + +#ifdef _UART0 + UART0 = (UART_TypeDef *)UART0_BASE; +#endif /* _UART0 */ + +#ifdef _UART1 + UART1 = (UART_TypeDef *)UART1_BASE; +#endif /* _UART1 */ + +#ifdef _UART2 + UART2 = (UART_TypeDef *)UART2_BASE; +#endif /* _UART2 */ + +/************************* SSP *************************/ + +#ifdef _SSP0 + SSP0 = (SSP_TypeDef *)SSP0_BASE; +#endif /* _SSP0 */ + +#ifdef _SSP1 + SSP1 = (SSP_TypeDef *)SSP1_BASE; +#endif /* _SSP1 */ + +/************************* CAN *************************/ + +#ifdef _CAN + CAN = (CAN_TypeDef *)CAN_BASE; +#endif /* _CAN */ + +/************************* ADC *************************/ + +#ifdef _ADC + ADC = (ADC_TypeDef *)ADC_BASE; +#endif /* _ADC */ + +/************************* WDG *************************/ + +#ifdef _WDG + WDG = (WDG_TypeDef *)WDG_BASE; +#endif /* _WDG */ + +/************************* I2C *************************/ + +#ifdef _I2C0 + I2C0 = (I2C_TypeDef *)I2C0_BASE; +#endif /* _I2C0 */ + +#ifdef _I2C1 + I2C1 = (I2C_TypeDef *)I2C1_BASE; +#endif /* _I2C1 */ +/********************** ENET **************************/ +#ifdef _ENET + ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE; + ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE; +#endif /* _ENET */ +} +#endif /* LIBDEBUG */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_mc.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_mc.c new file mode 100644 index 0000000..d3ca96a --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_mc.c @@ -0,0 +1,932 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_mc.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the MC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_mc.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +#define MC_ODCS_Set 0x0001 +#define MC_ODCS_Reset 0x00FE + +#define MC_CMS_Set 0x0004 +#define MC_CMS_Reset 0x00FB + +#define MC_CPC_Set 0x0008 +#define MC_CTC_Set 0x0010 + +#define MC_PCE_Set 0x0020 +#define MC_PCE_Reset 0xFFDF + +#define MC_TCE_Set 0x0040 +#define MC_TCE_Reset 0x00BF + +#define MC_DTE_Set 0x0080 +#define MC_DTE_Reset 0x007F + +#define MC_TCB_Set 0x0004 +#define MC_TCB_Reset 0x00FB + +#define MC_STC_Set 0x0008 + +#define MC_TES_Set 0x0010 +#define MC_TES_Reset 0x00EF + +#define MC_CCPT_Set 0x0020 +#define MC_CCPT_Reset 0x005F + +#define MC_DISEST_Set 0x0040 +#define MC_DISEST_Reset 0x003F + +#define MC_DTS_Set 0x0001 +#define MC_DTS_Reset 0x00FE + +#define MC_SDT_Set 0x0002 + +#define MC_C0SE_Set 0x0004 +#define MC_C0SE_Reset 0x00FB + +#define MC_CUSE_Set 0x0008 +#define MC_CUSE_Reset 0x00F7 + +#define MC_CVSE_Set 0x0010 +#define MC_CVSE_Reset 0x00EF + +#define MC_CWSE_Set 0x0020 +#define MC_CWSE_Reset 0x00D0 + +#define MC_RSE_Set 0x0040 +#define MC_RSE_Reset 0x00BF + +#define MC_GPI_Set 0x0080 +#define MC_GPI_Reset 0x007F + +#define MC_PUH_Set 0x0020 +#define MC_PUH_Reset 0x005F +#define MC_PUL_Set 0x0010 +#define MC_PUL_Reset 0x006F + +#define MC_PVH_Set 0x0008 +#define MC_PVH_Reset 0x0077 +#define MC_PVL_Set 0x0004 +#define MC_PVL_Reset 0x007B + +#define MC_PWH_Set 0x0002 +#define MC_PWH_Reset 0x007D +#define MC_PWL_Set 0x0001 +#define MC_PWL_Reset 0x007E + +#define MC_ODS_Set 0x0040 +#define MC_ODS_Reset 0xFF3F + +#define MC_ESC_Clear 0x4321 + +#define MC_PCR1_TIN_MASK 0xFFFC +#define MC_OPR_Mask 0x0040 +#define MC_UDCS_Mask 0x0002 +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/****************************************************************************** +* Function Name : MC_DeInit +* Description : Deinitializes MC peripheral registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_DeInit(void) +{ + /* MC peripheral is under Reset */ + SCU_APBPeriphReset(__MC, ENABLE); + + /* MC peripheral Reset off */ + SCU_APBPeriphReset(__MC, DISABLE); +} + +/******************************************************************************* +* Function Name : MC_Init +* Description : Initializes the MC peripheral according to the specified +* parameters in the MC_InitStruct . +* Input : IMC_InitStruct: pointer to a MC_InitTypeDef structure that +* contains the configuration information for the MC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void MC_Init(MC_InitTypeDef* MC_InitStruct) +{ + /* Select the operating Mode */ + if(MC_InitStruct->MC_OperatingMode == MC_SoftwareOperating_Mode) + { + /* Select the Data transfer Mode */ + MC->PCR2 |= MC_DTS_Set; + + /* Enable the registers Software Data Transfer */ + MC->PCR2 |= MC_C0SE_Set | MC_CUSE_Set | MC_CVSE_Set | MC_CWSE_Set + |MC_RSE_Set; + + } + else + { + /* Select the Data transfer Mode */ + MC->PCR2 &= MC_DTS_Reset; + + /* Disable the registers Software Data Transfer */ + MC->PCR2 &= MC_C0SE_Reset | MC_CUSE_Reset | MC_CVSE_Reset | MC_CWSE_Reset + |MC_RSE_Reset; + } + + /* Select the MC PWM counter Mode */ + if(MC_InitStruct->MC_PWMMode == MC_PWMZeroCentered_Mode) + { + MC->PCR0 |= MC_CMS_Set; + } + else + { + MC->PCR0 &= MC_CMS_Reset; + } + + /* Set the MC PWM counter Prescaler */ + MC->CPRS = MC_InitStruct->MC_Prescaler; + + /* Set the MC PWM Period */ + MC->CMP0 = MC_InitStruct->MC_Period; + + /* Set the MC PWM Repetition counter */ + MC->REP = MC_InitStruct->MC_RepetitionCounter; + + /* Set the Tacho Compare value */ + MC->TCMP = MC_InitStruct->MC_TachoPeriod; + + /* Set the Tacho Prescaler value */ + MC->TPRS = MC_InitStruct->MC_TachoPrescaler; + + /* Set the MC Tacho Input Polarity */ + MC->PCR1 = (MC->PCR1 & MC_PCR1_TIN_MASK) | MC_InitStruct->MC_TachoPolarity; + + /* Set the MC PWM Forced State */ + MC->OPR |= MC_ODS_Set; + MC->OPR = (MC->OPR & MC_OPR_Mask) | MC_InitStruct->MC_ForcedPWMState; + + /* Select the Tacho Mode */ + if(MC_InitStruct->MC_TachoMode == MC_TachoOneShot_Mode) + { + MC->PCR1 |= MC_TCB_Set; + } + else + { + MC->PCR1 &= MC_TCB_Reset; + } + + /* Select the Tacho Event Mode */ + if(MC_InitStruct->MC_TachoEvent_Mode == MC_TachoEvent_Software_Mode) + { + MC->PCR1 |= MC_TES_Set; + } + else + { + MC->PCR1 &= MC_TES_Reset; + } + + /* Enable or disable the emergency input */ + if(MC_InitStruct->MC_Emergency == MC_Emergency_Enable) + { + MC->PCR1 &= MC_DISEST_Reset; + } + else + { + MC->PCR1 |= MC_DISEST_Set; + } + +/* Select the complementary Mode */ + if(MC_InitStruct->MC_Complementary == MC_Complementary_Enable) + { + MC->DTG = MC_InitStruct->MC_DeadTime; + MC->PCR0 |= MC_ODCS_Set; + } + else + { + MC->PCR0 &= MC_ODCS_Reset; + } + + /* Tacho Mode selection */ + if(MC_InitStruct->MC_TachoMode == MC_TachoOneShot_Mode) + { + MC->PCR1 |= MC_TCB_Set; + } + else + { + MC->PCR1 &= MC_TCB_Reset; + } + + switch(MC_InitStruct->MC_Channel) + { + /* Channel U configuration */ + case MC_Channel_U: + { + MC->CMPU = MC_InitStruct->MC_PulseU; + + if(MC_InitStruct->MC_PolarityUL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUL_Set; + } + else + { + MC->PSR &= MC_PUL_Reset; + } + if(MC_InitStruct->MC_PolarityUH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUH_Set; + } + else + { + MC->PSR &= MC_PUH_Reset; + } + break; + } + + /* Channel V configuration */ + case MC_Channel_V: + { + MC->CMPV = MC_InitStruct->MC_PulseV; + + if(MC_InitStruct->MC_PolarityVL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVL_Set; + } + else + { + MC->PSR &= MC_PVL_Reset; + } + if(MC_InitStruct->MC_PolarityVH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVH_Set; + } + else + { + MC->PSR &= MC_PVH_Reset; + } + break; + } + + /* Channel W configuration */ + case MC_Channel_W: + { + MC->CMPW = MC_InitStruct->MC_PulseW; + + if(MC_InitStruct->MC_PolarityWL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWL_Set; + } + else + { + MC->PSR &= MC_PWL_Reset; + } + if(MC_InitStruct->MC_PolarityWH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWH_Set; + } + else + { + MC->PSR &= MC_PWH_Reset; + } + break; + } + /* All Channel Configuration */ + case MC_Channel_ALL: + { + MC->CMPU = MC_InitStruct->MC_PulseU; + MC->CMPV = MC_InitStruct->MC_PulseV; + MC->CMPW = MC_InitStruct->MC_PulseW; + + if(MC_InitStruct->MC_PolarityUL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUL_Set; + } + else + { + MC->PSR &= MC_PUL_Reset; + } + if(MC_InitStruct->MC_PolarityUH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUH_Set; + } + else + { + MC->PSR &= MC_PUH_Reset; + } + + if(MC_InitStruct->MC_PolarityVL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVL_Set; + } + else + { + MC->PSR &= MC_PVL_Reset; + } + if(MC_InitStruct->MC_PolarityVH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVH_Set; + } + else + { + MC->PSR &= MC_PVH_Reset; + } + + if(MC_InitStruct->MC_PolarityWL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWL_Set; + } + else + { + MC->PSR &= MC_PWL_Reset; + } + if(MC_InitStruct->MC_PolarityWH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWH_Set; + } + else + { + MC->PSR &= MC_PWH_Reset; + } + } + default: + break; + } +} + +/******************************************************************************* +* Function Name : MC_StructInit +* Description : Fills each MC_InitStruct member with its default value. +* Input : MC_InitStruct : pointer to a MC_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void MC_StructInit(MC_InitTypeDef* MC_InitStruct) +{ + MC_InitStruct->MC_OperatingMode = MC_HardwareOperating_Mode; + MC_InitStruct->MC_TachoMode = MC_TachoContinuous_Mode; + MC_InitStruct->MC_TachoEvent_Mode = MC_TachoEvent_Hardware_Mode; + MC_InitStruct->MC_Prescaler = 0x00; + MC_InitStruct->MC_TachoPrescaler = 0x0000; + MC_InitStruct->MC_PWMMode = MC_PWMClassical_Mode; + MC_InitStruct->MC_Complementary = MC_Complementary_Enable; + MC_InitStruct->MC_Emergency = MC_Emergency_Disable; + MC_InitStruct->MC_ForcedPWMState = 0x003F; + MC_InitStruct->MC_Period = 0x0000; + MC_InitStruct->MC_TachoPeriod = 0x00FF; + MC_InitStruct->MC_Channel = MC_Channel_ALL; + MC_InitStruct->MC_PulseU = 0x0000; + MC_InitStruct->MC_PulseV = 0x0000; + MC_InitStruct->MC_PulseW = 0x0000; + MC_InitStruct->MC_PolarityUL = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityUH = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityVL = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityVH = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityWL = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityWH = MC_Polarity_NonInverted; + MC_InitStruct->MC_TachoPolarity = MC_TachoEventEdge_RisingFalling; + MC_InitStruct->MC_DeadTime = 0x003F; + MC_InitStruct->MC_RepetitionCounter = 0x0000; +} + +/******************************************************************************* +* Function Name : MC_Cmd +* Description : Enables or disables the MC peripheral. +* Input : Newstate: new state of the MC peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the PWM counter */ + MC->PCR0 |= MC_PCE_Set; + + /* Enable the Tacho counter */ + MC->PCR0 |= MC_TCE_Set; + + /* Enable the Dead Time counter */ + MC->PCR0 |= MC_DTE_Set; + } + else + { + /* Disable the PWM counter */ + MC->PCR0 &= MC_PCE_Reset; + + /* Disable the Tacho counter */ + MC->PCR0 &= MC_TCE_Reset; + + /* Disable the Dead counter */ + MC->PCR0 &= MC_DTE_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_ClearPWMCounter +* Description : Clears the MC PWM counter. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearPWMCounter(void) +{ +/* Clear the PWM counter */ + MC->PCR0 |= MC_CPC_Set; +} + +/******************************************************************************* +* Function Name : MC_ClearTachoCounter +* Description : Clears the MC Tacho counter. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearTachoCounter(void) +{ +/* Clear the Tacho counter */ + MC->PCR0 |= MC_CTC_Set; +} + +/******************************************************************************* +* Function Name : MC_CtrlPWMOutputs +* Description : Enables or disables MC peripheral Main Outputs. +* Input : Newstate: new state of the MC peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_CtrlPWMOutputs(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + /* Enable the dead time generator data */ + MC->OPR &= MC_ODS_Reset; + } + else + { + /* Enable the default state data */ + MC->OPR |= MC_ODS_Set; + } +} + +/******************************************************************************* +* Function Name : MC_ITConfig +* Description : Enables or disables the MC interrupts. +* Input : - MC_IT: specifies the MC interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - MC_IT_CMPW: Compare W Interrupt. +* - MC_IT_CMPV: Compare V Interrupt. +* - MC_IT_CMPU: Compare U Interrupt. +* - MC_IT_ZPC: Zero of PWM counter Interrupt. +* - MC_IT_ADT: Automatic Data Transfer Interrupt. +* - MC_IT_OTC: Overflow of Tacho counter Interrupt. +* - MC_IT_CPT: Capture of Tacho counter Interrupt. +* - MC_IT_CM0: Compare 0 Interrupt. +* - Newstate: new state of IMC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ITConfig(u16 MC_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the specific interrupt source */ + MC->IMR |= MC_IT; + + /* Enable the global peripheral interrupt sources */ + MC->PCR2 |= MC_GPI_Set; + } + else + { + /* Disable the specific interrupt source */ + MC->IMR &= ~MC_IT; + + /* Disable the global peripheral interrupt sources */ + MC->PCR2 &= MC_GPI_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_SetPrescaler +* Description : Sets the MC prescaler value. +* Input : MC_Prescaler: MC prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPrescaler(u8 MC_Prescaler) +{ +/* Set the Prescaler Register value */ + MC->CPRS = MC_Prescaler; +} + +/******************************************************************************* +* Function Name : MC_SetPeriod +* Description : Sets the MC period value. +* Input : MC_Period: MC period new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPeriod(u16 MC_Period) +{ +/* Set the Period Register value */ + MC->CMP0 = MC_Period; +} + +/******************************************************************************* +* Function Name : MC_SetPulseU +* Description : Sets the MC pulse U value. +* Input : MC_PulseU: MC pulse U new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPulseU(u16 MC_PulseU) +{ +/* Set the Pulse U Register value */ + MC->CMPU = MC_PulseU; +} + +/******************************************************************************* +* Function Name : MC_SetPulseV +* Description : Sets the MC pulse V value. +* Input : MC_PulseV: MC pulse V new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPulseV(u16 MC_PulseV) +{ +/* Set the Pulse V Register value */ + MC->CMPV = MC_PulseV; +} + +/******************************************************************************* +* Function Name : MC_SetPulseW +* Description : Sets the MC pulse W value. +* Input : MC_PulseW: MC pulse W new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPulseW(u16 MC_PulseW) +{ +/* Set the Pulse W Register value */ + MC->CMPW = MC_PulseW; +} + +/******************************************************************************* +* Function Name : MC_PWMModeConfig +* Description : Selects the MC PWM counter Mode. +* Input : MC_PWMMode: MC PWM counter Mode. +* Output : None +* Return : None +*******************************************************************************/ +void MC_PWMModeConfig(u16 MC_PWMMode) +{ + /* Select the MC PWM counter Mode */ + if(MC_PWMMode == MC_PWMZeroCentered_Mode) + { + MC->PCR0 |= MC_CMS_Set; + } + else + { + MC->PCR0 &= MC_CMS_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_SetDeadTime +* Description : Sets the MC dead time value. +* Input : MC_DeadTime: MC dead time new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetDeadTime(u16 MC_DeadTime) +{ +/* Set the dead time Register value */ + MC->DTG = MC_DeadTime; +} + +/******************************************************************************* +* Function Name : MC_SetTachoCompare +* Description : Sets the MC Tacho Compare Register value. +* Input : MC_Compare: MC Tacho compare new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetTachoCompare(u8 MC_Compare) +{ + /* Sets the Tacho Compare Register value */ + MC->TCMP = MC_Compare; +} +/******************************************************************************* +* Function Name : MC_EmergencyCmd +* Description : Enables or disables the MC emergency feauture. +* Input : Newstate: new state of the MC peripheral Emergency. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_EmergencyCmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Reset the DISEST Bit in the PCR1 Register to enable the emergency stop input */ + MC->PCR1 &= MC_DISEST_Reset; + } + else + { + /* Set the DISEST Bit in the PCR1 Register to disable the emergency stop input */ + MC->PCR1 |= MC_DISEST_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_EmergencyClear +* Description : Clears the MC Emergency Register. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_EmergencyClear(void) +{ +/* Force PWM outputs in safe state (All OFF) */ + MC->OPR |= MC_ODS_Set; + +/* Clear EST bit */ + MC->ESC = MC_ESC_Clear; + +/* Re-enable protection */ + MC->ESC = 0; + +/* Enables the Outputs */ + MC->OPR &= MC_ODS_Reset; +} + +/******************************************************************************* +* Function Name : MC_GetPeriod +* Description : Gets the MC period value. +* Input : None +* Output : None +* Return : MC period value. +*******************************************************************************/ +u16 MC_GetPeriod(void) +{ +/* Return the PWM signal period value */ + return MC->CMP0; +} + +/******************************************************************************* +* Function Name : MC_GetPulseU +* Description : Gets the MC pulse U value. +* Input : None +* Output : None +* Return : MC pulse U value. +*******************************************************************************/ +u16 MC_GetPulseU(void) +{ +/* Return the PWM pulse U Register value */ + return MC->CMPU; +} + +/******************************************************************************* +* Function Name : MC_GetPulseV +* Description : Gets the MC pulse V value. +* Input : None +* Output : None +* Return : MC pulse V value. +*******************************************************************************/ +u16 MC_GetPulseV(void) +{ +/* Return the PWM pulse V Register value */ + return MC->CMPV; +} + +/******************************************************************************* +* Function Name : MC_GetPulseW +* Description : Gets the MC pulse W value. +* Input : None +* Output : None +* Return : MC pulse W value. +*******************************************************************************/ +u16 MC_GetPulseW(void) +{ +/* Return the PWM pulse W Register value */ + return MC->CMPW; +} + +/******************************************************************************* +* Function Name : MC_GetTachoCapture +* Description : Gets the MC Tacho period value. +* Input : None +* Output : None +* Return : MC Tacho capture value. +*******************************************************************************/ +u16 MC_GetTachoCapture(void) +{ +/* Return the Tacho Capture Register value */ + return MC->TCPT; +} + +/******************************************************************************* +* Function Name : MC_ClearOnTachoCapture +* Description : Enables or disables the the Clear on capture of tacho counter. +* Input : Newstate: new state of the CCPT bit. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearOnTachoCapture(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the Clear on capture of tacho counter */ + MC->PCR1 |= MC_CCPT_Set; + } + else + { + /* Disable the Clear on capture of tacho counter */ + MC->PCR1 &= MC_CCPT_Reset; + } +} +/******************************************************************************* +* Function Name : MC_ForceDataTransfer +* Description : Sets the MC Outputs default states. +* Input : MC_ForcedData: MC outputs new states. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ForceDataTransfer(u8 MC_ForcedData) +{ + /* Set the MC PWM Forced State */ + MC->OPR |= MC_ODS_Set; + MC->OPR = (MC->OPR & MC_OPR_Mask) | MC_ForcedData; +} + +/******************************************************************************* +* Function Name : MC_PreloadConfig +* Description : Enables the Software Data Transfer. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_SoftwarePreloadConfig(void) +{ + /* Set the SDT: Software Data Transfer bit */ + MC->PCR2 |= MC_SDT_Set; +} + +/******************************************************************************* +* Function Name : MC_SoftwareTachoCapture +* Description : Enables the Software Tacho Capture. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_SoftwareTachoCapture(void) +{ + /* Set the STC: Software Tacho Capture bit */ + MC->PCR1 |= MC_STC_Set; +} + +/******************************************************************************* +* Function Name : MC_GetCountingStatus +* Description : Checks whether the PWM Counter is counting Up or Down. +* Input : None +* Output : None +* Return : The new state of the PWM Counter(DOWN or UP). +*******************************************************************************/ +CountingStatus MC_GetCountingStatus(void) +{ + if((MC->PCR0 & MC_UDCS_Mask) != DOWN) + { + return UP; + } + else + { + return DOWN; + } +} + +/******************************************************************************* +* Function Name : MC_GetFlagStatus +* Description : Checks whether the specified MC flag is set or not. +* Input : MC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - MC_FLAG_CMPW: Compare W Flag. +* - MC_FLAG_CMPV: Compare V Flag. +* - MC_FLAG_CMPU: Compare U Flag. +* - MC_FLAG_ZPC: Zero of PWM counter Flag. +* - MC_FLAG_ADT: Automatic Data Transfer Flag. +* - MC_FLAG_OTC: Overflow of Tacho counter Flag. +* - MC_FLAG_CPT: Capture of Tacho counter Flag. +* - MC_FLAG_CM0: Compare 0 Flag. +* - MC_FLAG_EST: Emergency Stop Flag. +* Output : None +* Return : The new state of the MC_FLAG(SET or RESET). +*******************************************************************************/ +FlagStatus MC_GetFlagStatus(u16 MC_FLAG) +{ + if((MC->IPR & MC_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MC_ClearFlag +* Description : Clears the MC’s pending flags. +* Input : MC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - MC_FLAG_CMPW: Compare W Flag. +* - MC_FLAG_CMPV: Compare V Flag. +* - MC_FLAG_CMPU: Compare U Flag. +* - MC_FLAG_ZPC: Zero of PWM counter Flag. +* - MC_FLAG_ADT: Automatic Data Transfer Flag. +* - MC_FLAG_OTC: Overflow of Tacho counter Flag. +* - MC_FLAG_CPT: Capture of Tacho counter Flag. +* - MC_FLAG_CM0: Compare 0 Flag. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearFlag(u16 MC_FLAG) +{ +/* Clear the corresponding Flag */ + MC->IPR &= ~MC_FLAG; +} + +/******************************************************************************* +* Function Name : MC_GetITStatus +* Description : Checks whether the MC interrupt has occurred or not. +* Input : MC_IT: specifies the MC interrupt source to check. +* This parameter can be one of the following values: +* - MC_IT_CMPW: Compare W Interrupt. +* - MC_IT_CMPV: Compare V Interrupt. +* - MC_IT_CMPU: Compare U Interrupt. +* - MC_IT_ZPC: Zero of PWM counter Interrupt. +* - MC_IT_ADT: Automatic Data Transfer Interrupt. +* - MC_IT_OTC: Overflow of Tacho counter Interrupt. +* - MC_IT_CPT: Capture of Tacho counter Interrupt. +* - MC_IT_CM0: Compare 0 Interrupt. +* Output : None +* Return : The new state of the MC_IT(SET or RESET). +*******************************************************************************/ +ITStatus MC_GetITStatus(u16 MC_IT) +{ + if((MC->IPR & MC_IT) && (MC->IMR & MC_IT)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MC_ClearITPendingBit +* Description : Clears the IMC's interrupt pending bits. +* Input : MC_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - MC_IT_CMPW: Compare W Interrupt. +* - MC_IT_CMPV: Compare V Interrupt. +* - MC_IT_CMPU: Compare U Interrupt. +* - MC_IT_ZPC: Zero of PWM counter Interrupt. +* - MC_IT_ADT: Automatic Data Transfer Interrupt. +* - MC_IT_OTC: Overflow of Tacho counter Interrupt. +* - MC_IT_CPT: Capture of Tacho counter Interrupt. +* - MC_IT_CM0: Compare 0 Interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearITPendingBit(u16 MC_IT) +{ +/* Clear the corresponding interrupt pending bit */ + MC->IPR &= ~MC_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_rtc.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_rtc.c new file mode 100644 index 0000000..2d0751b --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_rtc.c @@ -0,0 +1,400 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_rtc.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the RTC library software functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_rtc.h" +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +u8 BYTEToBCD2(u8 value); +u16 WORDToBCD3(u16 value); +u8 BCD2ToBYTE(u8 value); +u16 BCD3ToBYTE(u16 value); +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : BYTEToBCD2 +* Description : Converts a 2 digit decimal to BCD format +* Input : None +* Output : None +* Return : Converted byte +*******************************************************************************/ +u8 BYTEToBCD2(u8 value) +{ + u8 bcdhigh = 0; + while (value >= 10) + { + bcdhigh++; + value -= 10; + } + return (bcdhigh << 4) | value; +} +/******************************************************************************* +* Function Name : WORDToBCD3 +* Description : Converts a 3 digit decimal to BCD format +* Input : None +* Output : None +* Return : Converted word +*******************************************************************************/ +u16 WORDToBCD3(u16 value) +{ + u16 bcdhigh = 0; + while (value >= 100) + { + bcdhigh++; + value -= 100; + } + bcdhigh <<= 4; + while (value >= 10) + { + bcdhigh++; + value -= 10; + } + return (bcdhigh << 4) | value; +} + +/******************************************************************************* +* Function Name : BCD3ToWORD +* Description : convert from 3 digit BCD to Binary +* Input : None +* Output : None +* Return : Converted word +*******************************************************************************/ +u16 BCD3ToWORD(u16 value) +{ + return (u16)((((value&0xF00)>>8)*100) + (((value&0x0F0)>>4)*10) + (value&0x0F)); +} + +/******************************************************************************* +* Function Name : BCD2ToBYTE +* Description : convert from 2 digit BCD to Binary +* Input : None +* Output : None +* Return : Converted word +*******************************************************************************/ +u8 BCD2ToBYTE(u8 value) +{ + u32 tmp; + tmp= ((value&0xF0)>>4)*10; + return (u8)(tmp+ (value&0x0F)); +} + +/******************************************************************************* +* Function Name : RTC_DeInit +* Description : Resets the RTC peripheral registers +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_DeInit(void) +{ + SCU_APBPeriphReset(__RTC,ENABLE); + SCU_APBPeriphReset(__RTC,DISABLE); +} + +/******************************************************************************* +* Function Name : RTC_SetDate +* Description : Sets the Date register +* Input : struct of type RTC_DATE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetDate(RTC_DATE Date) +{ + u32 tmp = 0; + + RTC->CR |=0x80; /*Enable write operation in DTR register*/ + RTC->DTR = 0; + tmp = BYTEToBCD2(Date.century); + RTC->DTR|=tmp<<24; + tmp = BYTEToBCD2(Date.year); + RTC->DTR|=tmp<<16; + tmp = BYTEToBCD2(Date.month); + RTC->DTR|=tmp<<8; + tmp = BYTEToBCD2(Date.weekday); + RTC->DTR|=tmp; + RTC->TR &=0xFFFFFF; + tmp = BYTEToBCD2(Date.day); + RTC->TR|=tmp<<24; + RTC->CR &=~0x80; /*Disable write operation in DTR register*/ +} +/******************************************************************************* +* Function Name : RTC_SetTime +* Description : Sets the Time register +* Input : struct of type RTC_TIME +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetTime(RTC_TIME Time) +{ + u32 tmp = 0; + + RTC->CR |=0x80; /*Enable write operation in TR register*/ + RTC->TR &= 0xFF000000; + tmp = BYTEToBCD2(Time.hours); + RTC->TR|=tmp<<16; + tmp = BYTEToBCD2(Time.minutes); + RTC->TR|=tmp<<8; + tmp = BYTEToBCD2(Time.seconds); + RTC->TR|=tmp; + RTC->MILR = 0; + RTC->MILR |= WORDToBCD3(Time.milliseconds); + RTC->CR &=~0x80; /*Disable write operation in TR register*/ +} +/******************************************************************************* +* Function Name : RTC_SetAlarm +* Description : Sets the Alarm register +* Input : Struct of type RTC_ALARM +* Output : Date +* Return : None +*******************************************************************************/ +void RTC_SetAlarm(RTC_ALARM Alarm) +{ + u32 tmp = 0; + + RTC->CR |=0x80; /*Enable write operation in ATR register*/ + RTC->ATR = 0; + tmp = BYTEToBCD2(Alarm.day); + RTC->ATR|=tmp<<24; + tmp = BYTEToBCD2(Alarm.hours); + RTC->ATR|=tmp<<16; + tmp = BYTEToBCD2(Alarm.minutes); + RTC->ATR|=tmp<<8; + tmp = BYTEToBCD2(Alarm.seconds); + RTC->ATR|=tmp; + RTC->CR &=~0x80; /*Disable write operation in ATR register*/ +} + +/******************************************************************************* +* Function Name : RTC_GetDate +* Description : Gets RTC date in BCD coded or BINARY code +* Input : -Format: BCD or BINARY +* -Date: pointer to structure of type RTC_DATE to be filled by function +* Output : None +* Return : None +*******************************************************************************/ +void RTC_GetDate(u8 Format, RTC_DATE * Date) +{ + Date->century = (u8)((RTC->DTR&0xFF000000)>>24); + Date->year = (u8)((RTC->DTR&0x00FF0000)>>16); + Date->month = (u8)((RTC->DTR&0x00001F00)>>8); + Date->day = (u8)((RTC->TR&0x3F000000)>>24); + Date->weekday = (u8)(RTC->DTR&0xF); + if (Format == BINARY) + { + Date->century = BCD2ToBYTE(Date->century); + Date->year = BCD2ToBYTE(Date->year); + Date->month = BCD2ToBYTE(Date->month); + Date->day = BCD2ToBYTE(Date->day); + Date->weekday = BCD2ToBYTE(Date->weekday); + } +} + +/******************************************************************************* +* Function Name : RTC_GetTime +* Description : Gets TIME in BCD coded or BINARY code +* Input : -Format: BCD or BINARY +* -Time : pointer to structure of type RTC_TIME to be filled by function +* Output : Time +* Return : None +*******************************************************************************/ +void RTC_GetTime(u8 Format, RTC_TIME * Time) +{ + + Time->hours = (u8)((RTC->TR&0x003F0000)>>16); + Time->minutes = (u8)((RTC->TR&0x00007F00)>>8); + Time->seconds = (u8)(RTC->TR&0x7F); + Time->milliseconds =(u16)(RTC->MILR&0xFFF); + if (Format == BINARY) + { + Time->hours = BCD2ToBYTE(Time->hours); + Time->minutes = BCD2ToBYTE(Time->minutes); + Time->seconds = BCD2ToBYTE(Time->seconds); + Time->milliseconds = BCD3ToWORD(Time->milliseconds); + } +} + + +/******************************************************************************* +* Function Name : RTC_GetAlarm +* Description : Gets the RTC Alarm in BCD or BINARY code +* Input : -Format: BCD or BINARY +* -Alarm : pointer to structure of type RTC_ALARM to be filled by function +* Output : Alarm +* Return : None +*******************************************************************************/ +void RTC_GetAlarm(u8 Format,RTC_ALARM * Alarm) +{ + Alarm->day = (u8)((RTC->ATR&0x3F000000)>>24); + Alarm->hours = (u8)((RTC->ATR&0x003F0000)>>16); + Alarm->minutes = (u8)((RTC->ATR&0x00007F00)>>8); + Alarm->seconds = (u8)((RTC->ATR)&0x7F); + if (Format == BINARY) + { + Alarm->day = BCD2ToBYTE(Alarm->day); + Alarm->hours = BCD2ToBYTE(Alarm->hours); + Alarm->minutes = BCD2ToBYTE(Alarm->minutes); + Alarm->seconds = BCD2ToBYTE(Alarm->seconds); + } +} + +/******************************************************************************* +* Function Name : RTC_TamperConfig +* Description : configures the Tamper mode and tamper polarity +* Input : -TamperMode: RTC_TamperMode_Edge or RTC_TamperMode_Level +* -TamperPol : RTC_TamperPol_Low or RTC_TamperMode_High +* Output : None +* Return : None +*******************************************************************************/ +void RTC_TamperConfig(u32 TamperMode, u32 TamperPol) +{ + RTC->CR&=RTC_TamperMode_Edge; + if (TamperMode!=RTC_TamperMode_Edge) + RTC->CR|=RTC_TamperMode_Level; + + RTC->CR&=RTC_TamperPol_Low; + if (TamperPol!=RTC_TamperPol_Low) + RTC->CR|=RTC_TamperPol_High; +} + +/******************************************************************************* +* Function Name : RTC_TamperCmd +* Description : Enable or Disable Tamper +* Input : NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_TamperCmd(FunctionalState NewState) +{ + RTC->CR&=0xFFFFFFFE; + if (NewState==ENABLE) + RTC->CR|=0x1; +} + +/******************************************************************************* +* Function Name : RTC_AlarmCmd +* Description : Enable or Disable Alarm +* Input : NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_AlarmCmd(FunctionalState NewState) +{ + RTC->CR&=~0x100000; + if (NewState==ENABLE) + RTC->CR|=0x100000; +} + +/******************************************************************************* +* Function Name : RTC_CalibClockCmd +* Description : Enable or Disable RTC Calibration Clock Output +* Input : NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_CalibClockCmd(FunctionalState NewState) +{ + RTC->CR&=~0x40; + if (NewState ==ENABLE) + RTC->CR|=0x40; +} + +/******************************************************************************* +* Function Name : SRAMBattPowerCmd +* Description : Enable or Disable SRAM backup Power by VBATT +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SRAMBattPowerCmd(FunctionalState NewState) +{ + RTC->CR&=~0x8; + if (NewState ==ENABLE) + RTC->CR|=0x8; +} + +/******************************************************************************* +* Function Name : RTC_PeridicIntConfig +* Description : Select a Periodic CLock +* Input : PeriodicClock +* Output : None +* Return : None +* Note : When PeriodicClock = RTC_Per_DISABLE the Periodic clock generation +* will be disabled. +*******************************************************************************/ +void RTC_PeriodicIntConfig(u32 PeriodicClock) +{ + RTC->CR &=~0xF0000; + RTC->CR|=PeriodicClock; +} + +/******************************************************************************* +* Function Name : RTC_ITConfig +* Description : Enable or Disable an interrupt +* Input : -RTC_IT : RTC interrupt +* -Newstate: Enable or Disable +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ITConfig(u32 RTC_IT, FunctionalState NewState) +{ + RTC->CR&=~RTC_IT; + if (NewState==ENABLE) + RTC->CR|=RTC_IT; +} + +/******************************************************************************* +* Function Name : RTC_GetFlagStatus +* Description : Gets a RTC flag status +* Input : RTC_FLAG +* Output : None +* Return : FlagStatus :SET or RESET +*******************************************************************************/ +FlagStatus RTC_GetFlagStatus(u32 RTC_FLAG) +{ + if (RTC->SR&RTC_FLAG) return SET; + else return RESET; +} + +/******************************************************************************* +* Function Name : RTC_ClearFlag +* Description : Clears a RTC flag +* Input : RTC_FLAG +* Output : None +* Return : None +* Note : Before clearing the RTC Periodic Flag you need to disable the +* Periodic interrupt generation, to do this use function +* RTC_PeriodicIntConfig(RTC_Per_DISABLE) +*******************************************************************************/ +void RTC_ClearFlag(u32 RTC_FLAG) +{ + vu32 tmp=0; + if (RTC_FLAG == RTC_FLAG_Per) tmp=RTC->SR; + else if (RTC_FLAG == RTC_FLAG_Alarm) RTC->CR&=~0x100000; + else if (RTC_FLAG == RTC_FLAG_Tamper) RTC->CR&=~0x1; +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_scu.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_scu.c new file mode 100644 index 0000000..21116b2 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_scu.c @@ -0,0 +1,661 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SCU_PLLEN 0x80000 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SCU_MCLKSourceConfig +* Description : Configures the MCLK source clock +* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : this function returns ERROR if trying to select the PLL as +* clock source while the PLL is disabled or not locked. +*******************************************************************************/ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source) +{ + u32 CLKCNTR_Value; + + CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/ + CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/ + if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/ + { + /*check if PLL enabled & locked*/ + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + return ERROR; + } + else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/ + SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/ + return SUCCESS; +} + +/******************************************************************************* +* Function Name : SCU_PLLFactorsConfig +* Description : Sets the PLL factors +* Input : PLLN, PLLM and PLLP +* Output : None +* Return : ErrorStatus: ERROR or SUCCESS +* Notes : -The PLL factors must respect the PLL specification requirements +* -The function returns ERROR if trying to change PLL +* factors while PLL is selected as Main Clock source (MCLK) +* -This function disables the PLL, to enable the PLL use +* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors +******************************************************************************/ +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP) +{ + if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/ + { + SCU->PLLCONF =0; /*clear PLLCONF register*/ + SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/ + SCU->PLLCONF |=PLLM; /*update PLLM field*/ + SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/ + return SUCCESS; + } + return ERROR; +} + +/******************************************************************************* +* Function Name : SCU_PLLCmd +* Description : Enable or Disable the PLL +* Input : NewState = ENABLE or DISABLE +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : -The function returns ERROR if: +* *trying to disable the PLL while it is selected as the MCLK +* *trying to enable the PLL while it is already enabled and +* locked +*******************************************************************************/ +ErrorStatus SCU_PLLCmd(FunctionalState NewState) +{ + vu32 i; + if (NewState==ENABLE) + { + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + { + SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/ + SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/ + while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/ + return SUCCESS; + } + else return ERROR; + } + else /*NewState = DISABLE*/ + { + if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/ + { + for(i=10;i>0;i--); /*delay before PLL disabling*/ + SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/ + return SUCCESS; + } + else return ERROR; + } +} + +/******************************************************************************* +* Function Name : SCU_RCLKDivisorConfig +* Description : Sets the RCLK divisor value +* Input : RCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/ + if (RCLK_Divisor!=SCU_RCLK_Div1) + SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_HCLKDivisorConfig +* Description : Sets the HCLK divisor value +* Input : HCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/ + if (HCLK_Divisor!=SCU_HCLK_Div1) + SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_PCLKDivisorConfig +* Description : Sets the PCLK divisor value +* Input : PCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/ + if (PCLK_Divisor!=SCU_PCLK_Div1) + SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphClockConfig +* Description : Enable the clock for an APB peripheral +* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for APB peripheral*/ + SCU->PCGR1 |=APBPeriph; + else + SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphClockConfig +* Description : Enable the clock for an AHB peripheral +* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for AHB peripheral*/ + SCU->PCGRO |=AHBPeriph; + else + SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphReset +* Description : Assert or deassert Reset on APB peripheral +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) /*APB peripheral not held in Reset*/ + SCU->PRR1 |=APBPeriph; + else + SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphReset +* Description : Assert or deassert Reset on AHB peripheral +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) + SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/ + else + SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/ + else + SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/ + else + SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/ +} +/******************************************************************************* +* Function Name : SCU_BRCLKDivisorConfig +* Description : Sets the BRCLK divisor value +* Input : BRCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/ + if (BRCLK_Divisor!=SCU_BRCLK_Div1) + SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/ +} + +/******************************************************************************* +* Function Name : SCU_TIMCLKSourceConfig +* Description : Sets the TIMx clock source +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source) +{ + if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/ + { + SCU->CLKCNTR &=0xFFFFDFFF; + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x2000; + } + else + { + SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/ + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x4000; + } +} + +/******************************************************************************* +* Function Name : SCU_TIMPresConfig +* Description : Sets the TIMx Prescaler Value +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - Prescaler (16 bit value) +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler) +{ + if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/ + SCU->SCR1 = Prescaler&0xFFFF; + else + SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/ +} + +/******************************************************************************* +* Function Name : SCU_USBCLKConfig +* Description : Configures the clock source for the 48MHz USBCLK +* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_USBCLKConfig(u32 USBCLK_Source) +{ + SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/ + if (USBCLK_Source!=SCU_USBCLK_MCLK) + SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/ +} + +/******************************************************************************* +* Function Name : SCU_PHYCLKConfig +* Description : Enable or Disable PHY clock output +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PHYCLKConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/ + else + SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/ +} + +/******************************************************************************* +* Function Name : SCU_FMICLKDivisorConfig +* Description : Set the FMI clock divisor +* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor) +{ + SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/ + if (FMICLK_Divisor!=SCU_FMICLK_Div1) + SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIBCLKDivisorConfig +* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2 +* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK) +{ + SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */ + if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1) + SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIModeConfig +* Description : Configure the EMI as Multiplexed or Demultiplexed +* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIModeConfig(u32 SCU_EMIMODE) +{ + SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/ + if (SCU_EMIMODE!=SCU_EMI_MUX) + SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/ +} + +/******************************************************************************* +* Function Name : SCU_EMIALEConfig +* Description : Configure the ALE signal (length & polarity) +* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2 +* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL) +{ + /*Configure EMI ALE Length*/ + SCU->SCR0 &=SCU_EMIALE_LEN1; + if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1) + SCU->SCR0 |= SCU_EMIALE_LEN2; + + /*Configure EMI ALE POL*/ + SCU->SCR0 &=SCU_EMIALE_POLLow; + if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow) + SCU->SCR0 |= SCU_EMIALE_POLHigh; +} + +/******************************************************************************* +* Function Name : SCU_ITConfig +* Description : ENBALE or DISABLE an SCU interrupt +* Input : -SCU_IT: interrupt mask +* -NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->ITCMSK&=~SCU_IT; /*IT enable */ + else + SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/ +} + +/******************************************************************************* +* Function Name : SCU_GetFlagStatus +* Description : Returns flag status +* Input : SCU_Flag +* Output : NONE +* Return : SET or RESET +*******************************************************************************/ +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag) +{ + if (SCU->SYSSTATUS&SCU_Flag) + return SET; + else return RESET; +} + +/******************************************************************************* +* Function Name : SCU_ClearFlag +* Description : Clears a SYSTATUS Flag +* Input : SCU_Flag +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ClearFlag(u32 SCU_Flag) +{ + SCU->SYSSTATUS = SCU_Flag; +} +/******************************************************************************* +* Function Name : SCU_GetPLLfreqValue +* Description : Gets the current PLL frequency +* Input : None +* Output : None +* Return : PLL frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPLLFreqValue(void) +{ + u8 PLL_M; + u8 PLL_N; + u8 PLL_P; + + PLL_M = SCU->PLLCONF&0xFF; + PLL_N = (SCU->PLLCONF&0xFF00)>>8; + PLL_P = (SCU->PLLCONF&0x70000)>>16; + + if ((PLL_M>0)&&(PLL_N>0)) + return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal); + if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32); + else return (SCU_GetPLLFreqValue()); +} + +/******************************************************************************* +* Function Name : SCU_GetRCLKFreqValue +* Description : Gets the current RCLK frequency +* Input : None +* Output : None +* Return : RCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetRCLKFreqValue(void) +{ + u8 RCLK_Div; + RCLK_Div = (SCU->CLKCNTR&0x1C)>>2; + if (RCLK_Div==0x5) RCLK_Div=10; + return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetHCLKFreqValue +* Description : Gets the current PCLK frequency +* Input : None +* Output : None +* Return : HCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetHCLKFreqValue(void) +{ + u8 HCLK_Div; + HCLK_Div = (SCU->CLKCNTR&0x60)>>5; + return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetPCLKFreqValue +* Description : Gets the current HCLK frequency +* Input : None +* Output : None +* Return : PCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPCLKFreqValue(void) +{ + u8 PCLK_Div; + PCLK_Div = (SCU->CLKCNTR&0x180)>>7; + return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_WakeUpLineConfig +* Description : Configures an External interrupt as WakeUp line +* Input : EXTint : 0 -> 31 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_WakeUpLineConfig(u8 EXTint) +{ + if (EXTint < 8) + { + SCU->WKUPSEL&=~0x7; + SCU->WKUPSEL|=EXTint; + } + else if (EXTint<16) + { + SCU->WKUPSEL&=~0x38; + SCU->WKUPSEL|=(EXTint-8)<<3; + } + else if (EXTint<24) + { + SCU->WKUPSEL&=~0x1C0; + SCU->WKUPSEL|=(EXTint-16)<<6; + } + else + { + SCU->WKUPSEL&=~0xE00; + SCU->WKUPSEL|=(EXTint-24)<<9; + } +} + +/******************************************************************************* +* Function Name : SCU_SpecIntRunModeConfig +* Description : Enables or Disables the Special Run mode +* Input : newstate = ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_SpecIntRunModeConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + SCU->PWRMNG |=0x8; + else + SCU->PWRMNG &=~0x8; +} +/******************************************************************************* +* Function Name : SCU_EnterIdleMode +* Description : Enters in Idle mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterIdleMode(void) +{ + SCU->PWRMNG |=0x1; +} +/******************************************************************************* +* Function Name : SCU_EnterSleepMode +* Description : Enters in Sleep mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterSleepMode(void) +{ + SCU->PWRMNG |=0x2; +} + +/******************************************************************************* +* Function Name : SCU_UARTIrDAConfig +* Description : Enable or Disable the Irda mode for UARTx +* Input : - UARTx :x=0,1 or 2 +* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART +* Output : None +* Return : None +*******************************************************************************/ +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode) +{ + if (UART_IrDA_Mode == SCU_UARTMode_IrDA) + { + if (UARTx== UART0) SCU->SCR0 |=0x400; + else if (UARTx==UART1) SCU->SCR0 |=0x800; + else SCU->SCR0 |=0x1000; + } + else + { + if (UARTx== UART0) SCU->SCR0 &=~0x400; + else if (UARTx==UART1) SCU->SCR0 &=~0x800; + else SCU->SCR0 &=~0x1000; + } +} +/******************************************************************************* +* Function Name : SCU_PFQBCCmd +* Description : Enable or Disable PFQBC +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PFQBCCmd(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->SCR0 |=0x1; + else SCU->SCR0 &=~0x1; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_ssp.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_ssp.c new file mode 100644 index 0000000..06bf30c --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_ssp.c @@ -0,0 +1,469 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ssp.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the SSP software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_ssp.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* SSP peripheral Enable */ +#define SSP_Enable 0x0002 +#define SSP_Disable 0xFFFD + +/* SSP Loop Back Mode Enable */ +#define SSP_LoopBackMode_Enable 0x0001 +#define SSP_LoopBackMode_Disable 0xFFFE + +/* SSP Flag Mask */ +#define SSP_Flag_Mask 0x001F + +/* SSP DMA transmit/ receive enable/disable Masks */ +#define SSP_DMA_TransmitEnable 0x0002 +#define SSP_DMA_TransmitDisable 0xFFFD +#define SSP_DMA_ReceiveEnable 0x0001 +#define SSP_DMA_ReceiveDisable 0xFFFE + +/* SSP Masks */ +#define SSP_FrameFormat_Mask 0xFFCF +#define SSP_DataSize_Mask 0xFFF0 +#define SSP_ClockRate_Mask 0x00FF +#define SSP_ClockPrescaler_Mask 0xFF00 + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SSP_DeInit +* Description : Deinitializes the SSPx peripheral registers to their default +* reset values. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DeInit(SSP_TypeDef* SSPx) +{ + if(SSPx == SSP0) + { + /* Reset the SSP0 registers values*/ + SCU_APBPeriphReset(__SSP0,ENABLE); + SCU_APBPeriphReset(__SSP0,DISABLE); + } + else if (SSPx == SSP1) + { + /* Reset the SSP1 registers values*/ + SCU_APBPeriphReset(__SSP1,ENABLE); + SCU_APBPeriphReset(__SSP1,DISABLE); + } +} + +/******************************************************************************* +* Function Name : SSP_Init +* Description : Initializes the SSPx peripheral according to the specified +* parameters in the SSP_InitTypeDef structure. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_InitStruct: pointer to a SSP_InitTypeDef structure that +* contains the configuration information for the specified SSP +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct) +{ + if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_Motorola) + { + /* Set the Motorola frame format */ + SSPx->CR0 &= SSP_FrameFormat_Motorola; + /* Configure the Clock polarity */ + if(SSP_InitStruct->SSP_CPOL == SSP_CPOL_High) + { + /* SCK is held high when no data is being transfered */ + SSPx->CR0 |= SSP_CPOL_High; + } + else + { + /* SCK is held low when no data is being transfered */ + SSPx->CR0 &= SSP_CPOL_Low; + } + /* Configure the Clock Phase */ + if(SSP_InitStruct->SSP_CPHA == SSP_CPHA_2Edge) + { + /* Data captured on second clock edge */ + SSPx->CR0 |= SSP_CPHA_2Edge; + } + else + { + /* Data captured on first clock edge */ + SSPx->CR0 &= SSP_CPHA_1Edge; + } + } + /* Configure the Frame format */ + else + { + /* Clear the FRF[1:0] bits */ + SSPx->CR0 &= SSP_FrameFormat_Mask; + /* Set the TI frame format */ + SSPx->CR0 |= SSP_InitStruct->SSP_FrameFormat; + } + /* Configure the Mode */ + if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave) + { + /* Set the slave mode */ + SSPx->CR1 |= SSP_Mode_Slave; + /* Configure the Slave output */ + if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable) + { + /* Slave output disabled */ + SSPx->CR1 |= SSP_SlaveOutput_Disable; + } + else + { + /* Slave output enabled */ + SSPx->CR1 &= SSP_SlaveOutput_Enable; + } + } + else + { + /* Set the master mode */ + SSPx->CR1 &= SSP_Mode_Master; + /* Clear clock rate SCR[7:0] bits */ + SSPx->CR0 &= SSP_ClockRate_Mask; + /* Set the serial clock rate */ + SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); + /* Clear clock prescaler CPSDVSR[7:0] bits */ + SSPx->PR &= SSP_ClockPrescaler_Mask; + /* Set the serial clock prescaler */ + SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; + } + + /* Clear data size DSS[3:0] bits */ + SSPx->CR0 &= SSP_DataSize_Mask; + /* Set the data size */ + SSPx->CR0 |= SSP_InitStruct->SSP_DataSize; +} +/******************************************************************************* +* Function Name : SSP_StructInit +* Description : Fills in a SSP_InitTypeDef structure with the reset value of +* each parameter. +* Input : SSP_InitStruct : pointer to a SSP_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct) +{ + /* Initialize the SSP_FrameFormat member */ + SSP_InitStruct->SSP_FrameFormat = SSP_FrameFormat_Motorola; + + /* Initialize the SSP_Mode member */ + SSP_InitStruct->SSP_Mode = SSP_Mode_Master; + + /* Initialize the SSP_CPOL member */ + SSP_InitStruct->SSP_CPOL = SSP_CPOL_Low; + + /* Initialize the SSP_CPHA member */ + SSP_InitStruct->SSP_CPHA = SSP_CPHA_1Edge; + + /* Initialize the SSP_DataSize member */ + SSP_InitStruct->SSP_DataSize = SSP_DataSize_8b; + + /* Initialize the SSP_SlaveOutput member */ + SSP_InitStruct->SSP_SlaveOutput = SSP_SlaveOutput_Enable; + + /* Initialize the SSP_ClockRate member */ + SSP_InitStruct->SSP_ClockRate = 0; + + /* Initialize the SSP_ClockPrescaler member */ + SSP_InitStruct->SSP_ClockPrescaler = 0; +} + +/******************************************************************************* +* Function Name : SSP_Cmd +* Description : Enables or disables the specified SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the SSPx peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the SSP peripheral */ + SSPx->CR1 |= SSP_Enable; + } + else + { + /* Disable the SSP peripheral */ + SSPx->CR1 &= SSP_Disable; + } +} + +/******************************************************************************* +* Function Name : SSP_ITConfig +* Description : Enables or disables the specified SSP interrupts. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the SSP interrupts sources to be enabled +* or disabled. This parameter can be any combination of the +* following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* - NewState: new state of the specified SSP interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected SSP interrupts */ + SSPx->IMSCR |= SSP_IT; + } + else + { + /* Disable the selected SSP interrupts */ + SSPx->IMSCR &= ~SSP_IT; + } +} + +/******************************************************************************* +* Function Name : SSP_DMACmd +* Description : Configures the SSP0 DMA interface. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_DMATransfert : specifies the DMA transfert to be +* enabled or disabled. This parameter can be one of the +* following values: +* - SSP_DMA_Transmit: transmit Fifo DMA transfert +* - SSP_DMA_Receive : receive Fifo DMA transfert +* - NewState: new state of the DMA transfert. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMACmd(SSP_TypeDef* SSPx, u16 SSP_DMATransfert, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + if(SSP_DMATransfert == SSP_DMA_Transmit) + { + /* Enable DMA for the transmit FIFO */ + SSPx->DMACR |= SSP_DMA_TransmitEnable; + } + else + { + /* Enable DMA for the receive FIFO */ + SSPx->DMACR |= SSP_DMA_ReceiveEnable; + } + } + else + { + if(SSP_DMATransfert == SSP_DMA_Transmit) + { + /* Disable DMA for the transmit FIFO */ + SSPx->DMACR &= SSP_DMA_TransmitDisable; + } + else + { + /* Disable DMA for the receive FIFO */ + SSPx->DMACR &= SSP_DMA_ReceiveDisable; + } + } +} + +/******************************************************************************* +* Function Name : SSP_SendData. +* Description : Transmits a Data through the SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - Data : Data to be transmitted. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data) +{ + /* Write in the DR register the data to be sent */ + SSPx->DR = Data; +} + +/******************************************************************************* +* Function Name : SSP_ReceiveData. +* Description : Returns the most recent received data by the SSP peripheral. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u16 SSP_ReceiveData(SSP_TypeDef* SSPx) +{ + /* Return the data in the DR register */ + return SSPx->DR; +} + +/******************************************************************************* +* Function Name : SSP_LoopBackMode +* Description : Enable or disable the Loop back mode for the selected SSPx peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the Loop Back mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void SSP_LoopBackMode(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable loop back mode */ + SSPx->CR1 |= SSP_LoopBackMode_Enable; + } + else + { + /* Disable loop back mode */ + SSPx->CR1 &= SSP_LoopBackMode_Disable; + } +} + + + +/******************************************************************************* +* Function Name : SSP_GetFlagStatus +* Description : Checks whether the specified SSP flag is set or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: flag to check. This parameter can be one of the +* following values: +* - SSP_FLAG_Busy: busy flag +* - SSP_FLAG_RxFifoFull: Receive FIFO full flag +* - SSP_FLAG_RxFifoNotEmpty: Receive FIFO not empty flag +* - SSP_FLAG_TxFifoNotFull: Transmit FIFO not full flag +* - SSP_FLAG_TxFifoEmpty: Transmit FIFO empty flag +* - SSP_FLAG_TxFifo: Transmit FIFO half empty or less flag +* - SSP_FLAG_RxFifo: Receive FIFO half full or less flag +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : The new state of SSP_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u32 SSPReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the SSP register index */ + SSPReg = SSP_FLAG >> 5; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Find the register of the flag to check */ + if(SSPReg == 1) + { + /* The flag to check is in SR register */ + StatusReg = SSPx->SR; + } + else if (SSPReg == 2) + { + /* The flag to check is in RISR register */ + StatusReg = SSPx->RISR; + } + + /* Check the status of the specified SSP flag */ + if((StatusReg & (1 << FlagPos)) != RESET) + { + /* Return SET if the SSP flag is set */ + return SET; + } + else + { + /* Return RESET if the SSP flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearFlag +* Description : Clears the SSPx flags. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: flags to clear. This parameter one of the +* following values: +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u8 FlagPos = 0; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Clear the selected SSP flag */ + SSPx->ICR = (1 << FlagPos); +} + +/******************************************************************************* +* Function Name : SSP_GetITStatus +* Description : Checks whether the specified SSP interrupt flag is set or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: interrupt flag to check. This parameter can be one +* of the following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : The new state of SSP_IT flag (SET or RESET). +*******************************************************************************/ +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Check the status of the specified interrupt flag */ + if((SSPx->MISR & SSP_IT) != RESET) + { + /* Return SET if the SSP interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if SSP interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearITPendingBit +* Description : Clears the pending interrupt flags. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: interrupts pending bits to clear. This parameter +* can be any combination of the following values: +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Clear the selected SSP interrupts pending bits */ + SSPx->ICR = SSP_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_tim.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_tim.c new file mode 100644 index 0000000..7957168 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_tim.c @@ -0,0 +1,694 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_tim.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the TIM software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_tim.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* TIM Bits Masks */ + +#define TIM_PWM_MASK 0x0010 +#define TIM_OPM_MASK 0x0020 +#define TIM_OC1_ENABLE_MASK 0x0040 +#define TIM_OC1_DISABLE_MASK 0xFFBF +#define TIM_OC2_ENABLE_MASK 0x0080 +#define TIM_OC2_DISABLE_MASK 0xFF7F + +#define TIM_OLVL1_SET_MASK 0x0100 +#define TIM_OLVL1_RESET_MASK 0xFEFF + +#define TIM_OLVL2_SET_MASK 0x0200 +#define TIM_OLVL2_RESET_MASK 0xFDFF + +#define TIM_ENABLE_MASK 0x8000 +#define TIM_DISABLE_MASK 0x7FFF + +#define TIM_DMA_CLEAR_MASK 0xCFFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : TIM_DeInit +* Description : Initializes TIM peripheral control and registers to their +* : default reset values. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM0)||(TIMx == TIM1)) + { + SCU_APBPeriphReset(__TIM01, DISABLE); /* TIM0 & TIM1 Reset's off */ + } + else + { + SCU_APBPeriphReset(__TIM23, DISABLE); /* TIM2 & TIM3 Reset's off */ + } + + /* Set all the TIMx registers to thier default values */ + TIMx->OC1R = 0x8000; + TIMx->OC2R = 0x8000; + TIMx->CR1 = 0x0; + TIMx->CR2 = 0x1; + TIMx->CNTR = 0x1234; + TIMx->SR = 0x0; +} + +/******************************************************************************* +* Function Name : TIM_StructInit +* Description : Fills in a TIM_InitTypeDef structure with the reset value of +* each parameter. +* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct) +{ + TIM_InitStruct->TIM_Mode = 0x0000; + TIM_InitStruct->TIM_OC1_Modes = 0x0000; + TIM_InitStruct->TIM_OC2_Modes = 0x0000; + TIM_InitStruct->TIM_Clock_Source = 0x0000; + TIM_InitStruct->TIM_Clock_Edge = 0x0000; + TIM_InitStruct->TIM_OPM_INPUT_Edge = 0x0000; + TIM_InitStruct->TIM_ICAP1_Edge = 0x0000; + TIM_InitStruct->TIM_ICAP2_Edge = 0x0000; + TIM_InitStruct->TIM_Prescaler = 0x0000; + TIM_InitStruct->TIM_Pulse_Level_1 = 0x0000; + TIM_InitStruct->TIM_Pulse_Level_2 = 0x0000; + TIM_InitStruct->TIM_Period_Level = 0x0000; + TIM_InitStruct->TIM_Pulse_Length_1 = 0x0000; + TIM_InitStruct->TIM_Pulse_Length_2 = 0x0000; + TIM_InitStruct->TIM_Full_Period = 0x0000; +} + +/******************************************************************************* +* Function Name : TIM_Init +* Description : Initializes TIM peripheral according to the specified +* parameters in the TIM_InitTypeDef structure. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ + +void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct) +{ +/***************************** Clock configuration ****************************/ + + if (TIM_InitStruct->TIM_Clock_Source == TIM_CLK_APB) + { + /* APB clock */ + TIMx->CR1 &= TIM_CLK_APB; + } + else + { + /* External/SCU clock */ + TIMx->CR1 |= TIM_CLK_EXTERNAL; + if (TIM_InitStruct->TIM_Clock_Edge == TIM_CLK_EDGE_RISING) + { + /* Clock rising edge */ + TIMx->CR1 |= TIM_CLK_EDGE_RISING; + } + else + { + /* Clock falling edge */ + TIMx->CR1 &= TIM_CLK_EDGE_FALLING; + } + } + +/************************** Prescaler configuration ***************************/ + + TIMx->CR2 =( TIMx->CR2 & 0xFF00 )|TIM_InitStruct->TIM_Prescaler ; + +/********************************** TIM Modes *********************************/ + + switch ( TIM_InitStruct->TIM_Mode) + { +/******************************* PWM Input mode *******************************/ + + case TIM_PWMI: + + /* Set the PWMI Bit */ + TIMx->CR1 |= TIM_PWMI; + + /* Set the first edge Level */ + if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + /* Set the Second edge Level ( Opposite of the first level ) */ + if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + else + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + + break; + +/************************** Output compare channel 1 **************************/ + + case TIM_OCM_CHANNEL_1: + + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC1_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + } + + break; + +/************************** Output compare channel 2 **************************/ + + case TIM_OCM_CHANNEL_2: + + if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2; + + if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC2_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC2_ENABLE_MASK; + } + + break; + +/************************ Output compare channel 1 & 2 ************************/ + + case TIM_OCM_CHANNEL_12: + + TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2; + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC2_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC2_ENABLE_MASK; + } + + if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC1_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + } + + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + break; + +/********************************** PWM mode **********************************/ + + case TIM_PWM: + + /* Set the Level During the pulse */ + if ( TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + /* Set the Level after the pulse */ + if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + /* Set the OCAE */ + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + + /* Set the PWM Bit */ + TIMx->CR1 |= TIM_PWM_MASK; + + /* Set the Duty Cycle value */ + if ( TIM_InitStruct->TIM_Pulse_Length_1 < 5 ) + { + TIM_InitStruct->TIM_Pulse_Length_1 = 4; + } + + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1 - 4; + + /* Set the Full Period */ + TIMx->OC2R = TIM_InitStruct->TIM_Full_Period - 4; + + break; + +/******************************* One pulse mode *******************************/ + + case TIM_OPM: + + /* Set the Level During the pulse */ + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + + /* Set the Level after the pulse */ + if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + + /* Set the Activation Edge on the ICAP 1 */ + if (TIM_InitStruct->TIM_OPM_INPUT_Edge == TIM_OPM_EDGE_RISING) + { + TIMx->CR1 |= TIM_OPM_EDGE_RISING; + } + + /* Set the Output Compare Function */ + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + + /* Set the One pulse mode */ + TIMx->CR1 |= TIM_OPM_MASK; + + /* Set the Pulse length */ + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + break; + +/*************************** Input capture channel 1 **************************/ + + case TIM_ICAP_CHANNEL_1: + + if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + break; + +/*************************** Input capture channel 2 **************************/ + + case TIM_ICAP_CHANNEL_2: + + if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + + break; + +/************************* Input capture channel 1 & 2 ************************/ + + case TIM_ICAP_CHANNEL_12: + if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + + if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterCmd +* Description : Enables or disables TIMx Counter peripheral. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_operation: specifies the new state of the TIMx Counter. +* This parameter can be one of the following values: +* - TIM_START: Start the timer counter. +* - TIM_STOP : Stop the timer counter. +* - TIM_CLEAR: Clear the timer counter. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation) +{ + switch (TIM_operation) + { + case TIM_START: + TIMx->CR1 |= TIM_ENABLE_MASK; + break; + + case TIM_STOP: + TIMx->CR1 &= TIM_DISABLE_MASK; + break; + + case TIM_CLEAR: + TIMx->CNTR = 0x1234; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : This routine is used to configure the TIMx prescaler value +* (when using the APB clock). +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Prescaler: specifies the prescaler value. This parameter +* can be a value from 0x0 to 0xFF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler) +{ + TIMx->CR2 &= 0xFF00; + TIMx->CR2 |= TIM_Prescaler; + +} +/******************************************************************************* +* Function Name : TIM_GetPrescalerValue +* Description : This routine is used to get the TIMx prescaler value +* (when using the APB clock). +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The prescaler value. +*******************************************************************************/ +u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx) +{ + return TIMx->CR2 & 0x00FF; +} + +/******************************************************************************* +* Function Name : TIM_GetCounterValue +* Description : This routine is used to get the TIMx counter value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The counter value. +*******************************************************************************/ +u16 TIM_GetCounterValue(TIM_TypeDef *TIMx) +{ + return TIMx->CNTR; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP1Value +* Description : This routine is used to get the Input Capture 1 value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The Input Capture 1 value. +*******************************************************************************/ +u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx) +{ + return TIMx->IC1R; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP2Value +* Description : This routine is used to get the Input Capture 2 value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The Input Capture 2 value. +*******************************************************************************/ +u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx) +{ + return TIMx->IC2R; +} + +/******************************************************************************* +* Function Name : TIM_SetPulse +* Description : This routine is used to set the pulse value. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Channel: specifies the needed channel. +* This parameter can be one of the following values: +* - TIM_PWM_OC1_Channel: PWM/Output Compare 1 Channel +* - TIM_OC2_Channel : Output Compare 2 Channel +* Input3 : TIM_Pulse: specifies the new pulse value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse) +{ + if (TIM_Channel == TIM_PWM_OC1_Channel) + { + TIMx->OC1R = TIM_Pulse; + } + else + { + TIMx->OC2R = TIM_Pulse; + } +} +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIMx flag is set or not. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Flag: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture Channel 1 Flag +* - TIM_FLAG_IC2: Input Capture Channel 2 Flag +* - TIM_FLAG_TO : Timer Overflow Flag +* - TIM_FLAG_OC1: Output Compare Channel 1 Flag +* - TIM_FLAG_OC2: Output Compare Channel 2 Flag +* Output : None +* Return : The NewState of the TIM_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag) +{ + if((TIMx->SR & TIM_Flag) == RESET) + { + return RESET; + } + else + { + return SET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIM Flag passed as a parameter. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Flag: specifies the flag to clear. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture Channel 1 Flag +* - TIM_FLAG_IC2: Input Capture Channel 2 Flag +* - TIM_FLAG_TO : Timer Overflow Flag +* - TIM_FLAG_OC1: Output Compare Channel 1 Flag +* - TIM_FLAG_OC2: Output Compare Channel 2 Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag) +{ + /* Clear TIM_Flag */ + TIMx->SR &= ~TIM_Flag; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPulse +* Description : This routine is used to get the Pulse value in PWMI Mode. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The pulse value. +*******************************************************************************/ +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx) +{ + return TIMx->IC2R; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPeriod +* Description : This routine is used to get the Period value in PWMI Mode. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The period value. +*******************************************************************************/ +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx) +{ + return TIMx->IC1R; +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Configures the Timer interrupt source. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_IT: specifies the TIM interrupt source to be enabled. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt source. +* - TIM_IT_OC1: Output Compare 1 Interrupt source. +* - TIM_IT_TO : Timer Overflow Interrupt source. +* - TIM_IT_IC2: Input Capture 2 Interrupt source. +* - TIM_IT_OC2: Output Compare 2 Interrupt source. +* Input3 : TIM_Newstate: specifies the new state of the TIMx IT. +* This parameter can be one of the following values: +* - ENABLE : Enable the needed interrupt. +* - DISABLE: Disable the needed interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate) +{ + if(TIM_Newstate == ENABLE) + { + TIMx->CR2 = (TIMx->CR2 & 0x00FF) | TIM_IT; + } + else + { + TIMx->CR2 &= ~TIM_IT; + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the Timer DMA source. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_DMA_Souces: specifies the TIM DMA source to be selected. +* This parameter can be one of the following values: +* - TIM_DMA_IC1: Input Capture 1 DMA source. +* - TIM_DMA_OCA1 Output Compare 1 DMA source. +* - TIM_DMA_TO: Timer Overflow DMA source. +* - TIM_DMA_IC2: Input Capture 2 DMA source. +* - TIM_DMA_OC2: Output Compare 2 DMA source. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources) +{ + /* Reset the DMAS[1:0] bits */ + TIMx->CR1 &= TIM_DMA_CLEAR_MASK; + /* Set the DMAS[1:0] bits according to TIM_DMA_Sources parameter */ + TIMx->CR1 |= TIM_DMA_Sources; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables TIMx DMA peripheral. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Newstate: new state of the TIMx DMA peripheral +* This parameter can be one of the following values: +* - ENABLE : Enable the TIMx DMA. +* - DISABLE: Disable the TIMx DMA. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate) +{ + if (TIM_Newstate == ENABLE) + { + TIMx->CR2 |= TIM_DMA_ENABLE; + } + else + { + TIMx->CR2 &= TIM_DMA_DISABLE; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_uart.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_uart.c new file mode 100644 index 0000000..3c87216 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_uart.c @@ -0,0 +1,658 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_uart.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the UART software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_uart.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* UART IrDA Mask */ +#define UART_IrDA_Disable_Mask 0xFFFD /* IrDA Disable Mask */ +#define UART_IrDA_Enable_Mask 0x0002 /* IrDA Enable Mask */ +#define IrDA_LowPower_Enable_Mask 0x0004 /*IrDA lower power mode enable*/ +#define IrDA_LowPower_Disable_Mask 0xFFFB /*IrDA lower power mode enable*/ + +/* UART Mask */ +#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ +#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ + +/* UART LoopBack */ +#define UART_LoopBack_Disable_Mask 0xFF7F /* LoopBack Disable Mask */ +#define UART_LoopBack_Enable_Mask 0x0080 /* LoopBack Enable Mask */ + +#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ +#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ +#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ +#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ +#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask*/ +#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ +#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ +#define UART_RTS_LowLevel_Mask 0x0800 /* RTS signal is low */ +#define UART_RTS_HighLevel_Mask 0xF7FF /* RTS signal is High */ +#define UART_DTR_LowLevel_Mask 0x0400 /* DTR signal is low */ +#define UART_DTR_HighLevel_Mask 0xFBFF /* DTR signal is High */ +#define UART_ClearFlag_Mask 0xAA /* Clear Flag Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + /******************************************************************************* +* Function Name : UART_DeInit +* Description : Deinitializes the UARTx peripheral registers +* to their default reset values. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DeInit(UART_TypeDef* UARTx) +{ + /* Reset the UARTx registers values */ + if(UARTx == UART0) + { + SCU_APBPeriphReset(__UART0,ENABLE); + SCU_APBPeriphReset(__UART0,DISABLE); + } + else if(UARTx == UART1) + { + SCU_APBPeriphReset(__UART1,ENABLE); + SCU_APBPeriphReset(__UART1,DISABLE); + } + else if(UARTx == UART2) + { + SCU_APBPeriphReset(__UART2,ENABLE); + SCU_APBPeriphReset(__UART2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : UART_Init +* Description : Initializes the UARTx peripheral according to the specified +* parameters in the UART_InitStruct . +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_InitStruct: pointer to a UART_InitTypeDef structure +* that contains the configuration information for the +* specified UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + + u64 UART_MainClock = 0; + u32 IntegerDivider = 0; + u32 FractionalDivider = 0; + + /* Clear the LCR[6:5] bits */ + UARTx->LCR &= UART_WordLength_Mask; + /* Set the LCR[6:5] bits according to UART_WordLength value */ + UARTx->LCR |= UART_InitStruct->UART_WordLength; + + /* Choose Stop Bits */ + if(UART_InitStruct->UART_StopBits == UART_StopBits_2) + { + /* 2 Stop Bit */ + UARTx->LCR |= UART_StopBits_2; + } + else + { + /* One Stop Bits */ + UARTx->LCR &= UART_StopBits_1; + } + + /* Configure the Parity */ + /* Clear the LCR[7]and LCR[2:1] bits */ + UARTx->LCR &= UART_Parity_Mask; + /* Set the LCR[7]and LCR[2:1] bits according to UART_Parity value */ + UARTx->LCR |= UART_InitStruct->UART_Parity; + + /* Configure the BaudRate */ + UART_MainClock = (SCU_GetMCLKFreqValue())*1000; + if((SCU->CLKCNTR & 0x200) != 0x200) + { + UART_MainClock = UART_MainClock/2; + } + /* Determine the integer part */ + IntegerDivider = ((100) * (UART_MainClock) / (16 * (UART_InitStruct->UART_BaudRate))); + UARTx->IBRD = IntegerDivider / 100; + + /* Determine the fractional part */ + FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); + UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); + + /* Choose the Hardware Flow Control */ + /* Clear the CR[15:14] bits */ + UARTx->CR &= UART_HardwareFlowControl_Mask; + /* Set the CR[15:14] bits according to UART_HardwareFlowControl value */ + UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; + + /* Configure the UART mode */ + /* Clear the CR[9:8] bits */ + UARTx->CR &= UART_Mode_Mask; + /* Set the CR[9:8] bits according to UART_Mode value */ + UARTx->CR |= UART_InitStruct->UART_Mode; + + /* Enable or disable the FIFOs */ + /* Set the FIFOs Levels */ + if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) + { + /* Enable the FIFOs */ + UARTx->LCR |= UART_FIFO_Enable; + + /* Clear TXIFLSEL and RXIFLSEL bits */ + UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; + + /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ + UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); + + /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ + UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; + } + else + { + /* Disable the FIFOs */ + UARTx->LCR &= UART_FIFO_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_StructInit +* Description : Fills each UART_InitStruct member with its reset value. +* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* Reset the UART_InitStruct members */ + UART_InitStruct->UART_WordLength = UART_WordLength_8D; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_Odd ; + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; + UART_InitStruct->UART_FIFO = UART_FIFO_Enable; + UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; + UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; +} + +/******************************************************************************* +* Function Name : UART_Cmd +* Description : Enables or disables the specified UART peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected UART by setting the UARTEN bit in the CR register */ + UARTx->CR |= UART_Enable_Mask; + } + else + { + /* Disable the selected UART by clearing the UARTEN bit in the CR register */ + UARTx->CR &= UART_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_ITConfig +* Description : Enables or disables the specified UART interrupts. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_IT: specifies the UART interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enables the selected interrupts */ + UARTx->IMSC |= UART_IT; + } + else + { + /* Disables the selected interrupts */ + UARTx->IMSC &= ~UART_IT; + } +} + +/******************************************************************************* +* Function Name : UART_DMAConfig +* Description : Configures the UARTx’s DMA interface. +* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral +* - UART_DMAOnError: specifies the DMA on error request. +* This parameter can be: +* - UART_DMAOnError_Enable: DMA receive request enabled +* when the UART error interrupt is asserted. +* - UART_DMAOnError_Disable: DMA receive request disabled +* when the UART error interrupt is asserted. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError) +{ + if(UART_DMAOnError == UART_DMAOnError_Enable) + { + UARTx->DMACR &= UART_DMAOnError_Enable; + } + else + { + UARTx->DMACR |= UART_DMAOnError_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_DMACmd +* Description : Enables or disables the UARTx’s DMA interface. +* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral +* - UART_DMAReq: enables or disables the request of DMA from UART. +* This parameter can be: +* - UART_DMAReq_Tx: Transmit DMA Enable +* - UART_DMAReq_Rx: Receive DMA Enable +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState) +{ + if(UART_DMAReq == UART_DMAReq_Tx) + { + if(NewState == ENABLE) + { + UARTx->DMACR |= UART_DMAReq_Tx; + } + else + { + UARTx->DMACR &= ~UART_DMAReq_Tx; + } + } + + if(UART_DMAReq == UART_DMAReq_Rx) + { + if(NewState == ENABLE) + { + UARTx->DMACR |= UART_DMAReq_Rx; + } + else + { + UARTx->DMACR &= ~UART_DMAReq_Rx; + } + } +} + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : Enables or disables the LoopBack mode. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the LoopBack mode of the specified UART */ + UARTx->CR |= UART_LoopBack_Enable_Mask; + } + else + { + /* Disable the LoopBack mode of the specified UART */ + UARTx->CR &= UART_LoopBack_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_GetFlagStatus +* Description : Checks whether the specified UART flag is set or not. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* - UART_FLAG_RI: RI flag +* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag +* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag +* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag +* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag +* - UART_FLAG_Busy: UART Busy flag +* - UART_FLAG_CTS: CTS flag +* - UART_FLAG_DCD: DCD flag +* - UART_FLAG_DSR: DSR flag +* - UART_RawIT_OverrunError: Overrun Error interrupt flag +* - UART_RawIT_BreakError: Break Error interrupt flag +* - UART_RawIT_ParityError: Parity Error interrupt flag +* - UART_RawIT_FrameError: Frame Error interrupt flag +* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag +* - UART_RawIT_Transmit: Transmit interrupt flag +* - UART_RawIT_Receive: Receive interrupt flag +* - UART_RawIT_DSR: DSR interrupt flag +* - UART_RawIT_DCD: DCD interrupt flag +* - UART_RawIT_CTS: CTS interrupt flag +* - UART_RawIT_RI: RI interrupt flag +* Output : None +* Return : The new state of UART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + + u32 UARTReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the UART register index */ + UARTReg = UART_FLAG >> 5; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + if(UARTReg == 1) /* The flag to check is in RSR register */ + { + StatusReg = UARTx->RSECR; + } + else if (UARTReg == 2) /* The flag to check is in FR register */ + { + StatusReg = UARTx->FR; + } + else if(UARTReg == 3) /* The flag to check is in RIS register */ + { + StatusReg = UARTx->RIS; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearFlag +* Description : Clears the UARTx’s flags(Frame, Parity, Break, Overrun error). +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearFlag(UART_TypeDef* UARTx) +{ + /* Clear the flag */ + UARTx->RSECR = UART_ClearFlag_Mask; +} + +/******************************************************************************* +* Function Name : UART_GetITStatus +* Description : Checks whether the specified UART interrupt has occured or not. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to be checked. +* This parameter can be one of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* Output : None +* Return : The new state of UART_IT (SET or RESET). +*******************************************************************************/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) +{ + if((UARTx->MIS & UART_IT) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearITPendingBit +* Description : Clears the UARTx’s interrupt pending bits. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to clear. +* More than one interrupt can be cleared using the “|” operator. +* This parameter can be: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) +{ + /* Clear the specified interrupt */ + UARTx->ICR = UART_IT; +} + +/******************************************************************************* +* Function Name : UART_IrDALowPowerConfig +* Description : Sets the IrDA low power mode +* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. +* - NewState: new state of the UARTIrDA peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState) +{ + UART_TypeDef* UARTx; + + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + + if (NewState == ENABLE) + { + UARTx->CR |= IrDA_LowPower_Enable_Mask; + } + else + { + UARTx->CR &= IrDA_LowPower_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_IrDASetCounter +* Description : Sets the IrDA counter divisor value. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. +* - IrDA_Counter: IrDA counter divisor new value n low power mode(Hz). +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter) +{ + UART_TypeDef* UARTx; + u32 APBClock; + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + /* Get the APB frequency */ + APBClock = (SCU_GetPCLKFreqValue())*1000; + /* Determine the Counter Divisor part */ + UARTx->ILPR = (((APBClock*10) / ( IrDA_Counter)) + 5 )/10; + } + +/******************************************************************************* +* Function Name : UART_IrDACmd +* Description : Enables or disables the UARTx’s IrDA interface. +* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDACmd(u8 IrDAx, FunctionalState NewState) +{ + UART_TypeDef* UARTx; + + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + if(NewState == ENABLE) + { + /* Enable the IrDA mode of the specified UART */ + UARTx->CR |= UART_IrDA_Enable_Mask; + } + else + { + /* Disable the IrDA mode of the specified UART */ + UARTx->CR &= UART_IrDA_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_SendData +* Description : Transmits signle Byte of data through the UARTx peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - Data: the byte to transmit +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendData(UART_TypeDef* UARTx, u8 Data) +{ + /* Transmit one byte */ + UARTx->DR = Data; +} + +/******************************************************************************* +* Function Name : UART_ReceiveData +* Description : Returns the most recent received Byte by the UARTx peripheral. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : The received data +*******************************************************************************/ +u8 UART_ReceiveData(UART_TypeDef* UARTx) +{ + /* Receive one byte */ + return ((u8)UARTx->DR); +} + +/******************************************************************************* +* Function Name : UART_SendBreak +* Description : Transmits break characters. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendBreak(UART_TypeDef* UARTx) +{ + /* Send break characters */ + UARTx->LCR |= UART_BreakChar_Mask; +} + +/******************************************************************************* +* Function Name : UART_RTSConfig +* Description : Sets or Resets the RTS signal +* Input : - LevelState: new state of the RTS signal for UART0 only. +* This parameter can be: LowLevel or HighLevel +* Output : None +* Return : None +*******************************************************************************/ +void UART_RTSConfig(UART_LevelTypeDef LevelState) +{ + if(LevelState == LowLevel) + { + UART0->CR |= UART_RTS_LowLevel_Mask; + } + else + { + UART0->CR &= UART_RTS_HighLevel_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_DTRConfig +* Description : Sets or Resets the DTR signal for UART0 only +* Input : - LevelState: new state of the DTR signal. +* This parameter can be: LowLevel or HighLevel +* Output : None +* Return : None +*******************************************************************************/ +void UART_DTRConfig(UART_LevelTypeDef LevelState) +{ + if(LevelState == LowLevel) + { + UART0->CR |= UART_DTR_LowLevel_Mask; + } + else + { + UART0->CR &= UART_DTR_HighLevel_Mask; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_vic.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_vic.c new file mode 100644 index 0000000..fecb890 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_vic.c @@ -0,0 +1,830 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_vic.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the VIC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_vic.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define VIC_REGISTER_NUMBER 16 +#define VIC_PROTECTION_ENABLE_MASK 0x1 +#define VIC_PROTECTION_DISABLE_MASK 0xFFFFFFFE +#define VIC_VECTOR_ENABLE_MASK 0x20 +#define VIC_IT_SOURCE_MASK 0xFFFFFFE0 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode); +static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ + void (*VIC_VectAddress)(void)); +static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority); +static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority); + +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : VIC_DeInit +* Description : Deinitialize the VIC module registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void VIC_DeInit(void) +{ + SCU_AHBPeriphReset(__VIC, ENABLE); /* VIC peripheral is under Reset */ + SCU_AHBPeriphReset(__VIC, DISABLE); /* VIC peripheral Reset off */ +} + +/******************************************************************************* +* Function Name : VIC_GetIRQStatus +* Description : Get the status of interrupts after IRQ masking. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the IRQ interrupt after masking (SET or RESET). +*******************************************************************************/ +FlagStatus VIC_GetIRQStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->ISR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->ISR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_GetFIQStatus +* Description : Get the status of interrupts after FIQ masking +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the FIQ interrupt after masking (SET or RESET) +*******************************************************************************/ +FlagStatus VIC_GetFIQStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->RINTSR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->RINTSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_GetSourceITStatus +* Description : Get the status of the source interrupts before masking. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the source interrupt before masking +*******************************************************************************/ +FlagStatus VIC_GetSourceITStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->FSR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->FSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_ITModeConfig +* Description : Select the type of interrupt (IRQ or FIQ) +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_LineMode :specifies the type of interrupt of the source +* line. This parameter can be one of the following values: +* - VIC_IRQ: the correspondent line is configured as IRQ. +* - VIC_FIQ: the correspondent line is configured as FIQ. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode) +{ + u32 VIC_Mask = 1; + + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + { + if (VIC_LineMode == VIC_IRQ) + VIC0->INTSR &= ~(VIC_Mask << VIC_Source); + else /* VIC_LineMode == VIC_FIQ */ + VIC0->INTSR |= (VIC_Mask << VIC_Source); + } + else /* VIC1 */ + { + if (VIC_LineMode == VIC_IRQ) + VIC1->INTSR &= ~(VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + else /* VIC_LineMode == VIC_FIQ */ + VIC1->INTSR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_ITCmd +* Description : Enable or disable the interrupt request lines. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : FMI_NewState: specifies the line status. +* This parameter can be one of the following values: +* - ENABLE: The line is enabled. +* - DISABLE: The line is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState) +{ + u32 VIC_Mask = 1; + + if (VIC_NewState == ENABLE) + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->INTER |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->INTER |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } + else /* VIC_NewState == DISABLE */ + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->INTECR |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->INTECR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_SWITCmd +* Description : Generate a software interrupt for the specific source +* interrupt. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : FMI_NewState: specifies the software interrupt status. +* This parameter can be one of the following values: +* - ENABLE: The software interrupt is enabled. +* - DISABLE: The software interrupt is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState) +{ + u32 VIC_Mask = 1; + + if (VIC_NewState == ENABLE) + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->SWINTR |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->SWINTR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } + else /* VIC_NewState == DISABLE */ + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->SWINTCR = (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->SWINTCR = (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_ProtectionCmd +* Description : Enable or Disable the register access protection. +* Input : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: The protection is enabled. +* - DISABLE: The protection is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_ProtectionCmd(FunctionalState VIC_NewState) +{ + if (VIC_NewState == ENABLE) + { + VIC0->PER |= VIC_PROTECTION_ENABLE_MASK; + VIC1->PER |= VIC_PROTECTION_ENABLE_MASK; + } + else + { + VIC0->PER &= VIC_PROTECTION_DISABLE_MASK; + VIC1->PER &= VIC_PROTECTION_DISABLE_MASK; + } +} + +/******************************************************************************* +* Function Name : VIC_GetCurrentISRAdd +* Description : Get the address of the current active ISR. +* Input : VICx: specifies the VIC peripheral +* This parameter can be one of the following values: +* - VIC0: To select VIC0. +* - VIC1: To select VIC1. +* Output : None +* Return : The Address of the active ISR. +*******************************************************************************/ +u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx) +{ + return VICx->VAR; +} + +/******************************************************************************* +* Function Name : VIC_ISRVectAddConfig +* Description : Configuration of the ISR vector address. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Input3 : void (*VIC_VectAddress)(void): specifies the ISR vector +* address pointer. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ + void (*VIC_VectAddress)(void)) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->VAiR[VIC_Priority] = (u32)VIC_VectAddress; + else /* VIC1 */ + VIC1->VAiR[VIC_Priority] = (u32)VIC_VectAddress; +} + +/******************************************************************************* +* Function Name : VIC_GetISRVectAdd +* Description : Get the ISR vector address of the correspondent line. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The correspondent ISR vector address. +*******************************************************************************/ +u32 VIC_GetISRVectAdd(u16 VIC_Source) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + return VIC0->VAiR[VIC_Source]; + else /* VIC1 */ + return VIC1->VAiR[VIC_Source - VIC_REGISTER_NUMBER]; +} + +/******************************************************************************* +* Function Name : VIC_VectEnableConfig +* Description : Enable the vector interrupt. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; + else /* VIC1 */ + VIC1->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; +} + +/******************************************************************************* +* Function Name : VIC_ITSourceConfig +* Description : Select the interrupt source. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + { + VIC0->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; + VIC0->VCiR[VIC_Priority] |= VIC_Source; + } + else /* VIC1 */ + { + VIC1->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; + VIC1->VCiR[VIC_Priority] |= VIC_Source - VIC_REGISTER_NUMBER; + } +} + +/******************************************************************************* +* Function Name : VIC_Config +* Description : Configure the ISR, the line, the mode and the priority for +* each interrupt source line. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_LineMode :specifies the type of interrupt of the source +* line. This parameter can be one of the following values: +* - VIC_IRQ: the correspondent line is configured as IRQ. +* - VIC_FIQ: the correspondent line is configured as FIQ. +* Input3 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority) +{ + switch (VIC_Source) + { + case 0: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WDG_IRQHandler); + break; + + case 1: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SW_IRQHandler); + break; + + case 2: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMRX_IRQHandler); + break; + + case 3: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMTX_IRQHandler); + break; + + case 4: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM0_IRQHandler); + break; + + case 5: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM1_IRQHandler); + break; + + case 6: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM2_IRQHandler); + break; + + case 7: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM3_IRQHandler); + break; + + case 8: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBHP_IRQHandler); + break; + + case 9: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBLP_IRQHandler); + break; + + case 10: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SCU_IRQHandler); + break; + + case 11: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ENET_IRQHandler); + break; + + case 12: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, DMA_IRQHandler); + break; + + case 13: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, CAN_IRQHandler); + break; + + case 14: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, MC_IRQHandler); + break; + + case 15: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ADC_IRQHandler); + break; + + case 16: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART0_IRQHandler); + break; + + case 17: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART1_IRQHandler); + break; + + case 18: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART2_IRQHandler); + break; + + case 19: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C0_IRQHandler); + break; + + case 20: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C1_IRQHandler); + break; + + case 21: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP0_IRQHandler); + break; + + case 22: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP1_IRQHandler); + break; + + case 23: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, LVD_IRQHandler); + break; + + case 24: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, RTC_IRQHandler); + break; + + case 25: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WIU_IRQHandler); + break; + + case 26: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT0_IRQHandler); + break; + + case 27: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT1_IRQHandler); + break; + + case 28: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT2_IRQHandler); + break; + + case 29: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT3_IRQHandler); + break; + + case 30: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBWU_IRQHandler); + break; + + case 31: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, PFQBC_IRQHandler); + break; + + default: break; + } + VIC_ITModeConfig(VIC_Source, VIC_LineMode); + VIC_VectEnableConfig(VIC_Source, VIC_Priority); + VIC_ITSourceConfig(VIC_Source, VIC_Priority); +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_wdg.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_wdg.c new file mode 100644 index 0000000..f933635 --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_wdg.c @@ -0,0 +1,277 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wdg.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the WDG software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_wdg.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + + +/* WDG End of Count interrupt Flag */ +#define WDG_FLAG_EC 0x0001 + + +/* WDG End of Count interrupt request */ +#define WDG_IT_EC 0x0001 + + + +/* WDG Start/Stop counter */ +#define WDG_Counter_Start 0x0002 +#define WDG_Counter_Stop 0xFFFD + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : WDG_DeInit +* Description : Deinitializes the WDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_DeInit(void) +{ + + SCU_APBPeriphReset(__WDG, ENABLE); /*WDG peripheral under Reset */ + SCU_APBPeriphReset(__WDG, DISABLE); /*WDG peripheral Reset off*/ + +} + +/******************************************************************************* +* Function Name : WDG_StructInit +* Description : Fills the WDG_InitTypeDef structure member with its reset +* value. +* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) +{ + /* Select the Watchdog running mode*/ + WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; + + /* Select the source clock */ + WDG_InitStruct-> WDG_ClockSource = WDG_ClockSource_Apb; + + /* Initialize Prescaler */ + WDG_InitStruct->WDG_Prescaler =0xFF; + + /* Initialize Preload */ + WDG_InitStruct->WDG_Preload =0xFFFF; + + +} + +/******************************************************************************* +* Function Name : WDG_Init +* Description : Initializes WDG peripheral according to the specified +* parameters in the WDG_InitStruct. +* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that +* contains the configuration information for the WDG peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) +{ + + + if(WDG_InitStruct->WDG_ClockSource == WDG_ClockSource_Apb) + { + /* Select The APB clock as clock source */ + WDG->CR &= WDG_ClockSource_Apb; + } + + else + { + /* Select the RTC clock as source */ + WDG->CR |= WDG_ClockSource_Rtc ; + } + + + /* Configure WDG Prescaler register value */ + WDG->PR = WDG_InitStruct->WDG_Prescaler; + + /* Configure WDG Pre-load register value */ + WDG->VR = WDG_InitStruct->WDG_Preload ; + + + if(WDG_InitStruct->WDG_Mode == WDG_Mode_Timer) + { + /* Select Timer mode */ + WDG->CR &= WDG_Mode_Timer; + } + else + { + /* Select WDG mode */ + WDG->CR |= WDG_Mode_Wdg ; + } + + +} + +/******************************************************************************* +* Function Name : WDG_Cmd +* Description : Enables or disables the WDG peripheral. +* Input : NewState: new state of the WDG peripheral (Newstate can be +* ENABLE or DISABLE) +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Cmd(FunctionalState NewState ) +{ + if((WDG->CR & WDG_Mode_Wdg) == 0) + { + /* Timer mode */ + if(NewState == ENABLE) + { + /* Start timer by setting SC bit in Control register */ + WDG->CR |= WDG_Counter_Start; + } + else + { + /* Stop timer by clearning SC bit in Control register */ + WDG->CR &= WDG_Counter_Stop; + } + } + else + { + /* Watchdog mode */ + if(NewState == ENABLE) + { + WDG->KR = WDG_KeyValue1; + WDG->KR = WDG_KeyValue2; + } + } +} + +/******************************************************************************* +* Function Name : WDG_ITConfig +* Description : Enables or disables the WDG End of Count(EC) interrupt. +* Input : Newstate: new state of the End of Count(EC) WDG interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ITConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the End of Count interrupt */ + WDG->MR |= WDG_IT_EC; + } + else + { + /* Disable the End of Count interrupt */ + WDG->MR &= ~WDG_IT_EC; + } +} + +/******************************************************************************* +* Function Name : WDG_GetCounter +* Description : Gets the WDG’s current counter value. +* Input : None +* Output : None +* Return : The WDG current counter value +*******************************************************************************/ +u16 WDG_GetCounter(void) +{ + return WDG->CNT; +} + + + + +/******************************************************************************* +* Function Name : WDG_GetITStatus +* Description : Checks whether the WDG End of Count(EC) interrupt is occured or not. +* Input : None +* Output : None +* Return : The new state of WDG_IT (SET or RESET). +*******************************************************************************/ +ITStatus WDG_GetITStatus(void) +{ + if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearITPendingBit +* Description : Clears the WDG's End of Count(EC) interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearITPendingBit(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_IT_EC; + +} + +/******************************************************************************* +* Function Name : WDG_ClearFlag +* Description : Clears the WDG's End of Count(EC) Flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearFlag(void) +{ + /* Clear the EC Flag */ + + WDG->SR &= ~WDG_FLAG_EC; + +} + + +/******************************************************************************* +* Function Name : WDG_GetFlagStatus +* Description : Checks whether the WDG End of Count(EC) flag is set or not. +* Input : None +* Output : None +* Return : The new state of the WDG_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus WDG_GetFlagStatus(void) +{ + if((WDG->SR & WDG_FLAG_EC) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_wiu.c b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_wiu.c new file mode 100644 index 0000000..3154a3c --- /dev/null +++ b/uc_str912/prj_blinky_simple_startup/str91x_lib/src/91x_wiu.c @@ -0,0 +1,190 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wiu.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the WIU software functions. +********************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +/* Standard include ----------------------------------------------------------*/ +#include "91x_wiu.h" +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/****************************************************************************** +* Function Name : WIU_Init +* Description : Initializes the WIU unit according to the specified parameters +* in the WIU_InitTypeDef structure. +* Input : WIU_InitStruct: pointer to a WIU_InitTypeDef structure that +* contains the configuration information for the WIU peripheral. +* Output : None +* Return : None +******************************************************************************/ +void WIU_Init(WIU_InitTypeDef* WIU_InitStruct) +{ + /* select the Wake-up line to be used */ + WIU->MR |= WIU_InitStruct->WIU_Line; + + /* configure the triggering edge */ + if(WIU_InitStruct->WIU_TriggerEdge == WIU_RisingEdge) + { + /* trigger on rising edge */ + WIU->TR |= WIU_InitStruct->WIU_Line; + } + else + { + /* trigger on falling edge */ + WIU->TR &= ~WIU_InitStruct->WIU_Line; + } + + if(WIU_InitStruct->WIU_Mode == WIU_Mode_SWInterrupt) + { + /* enable interrupt mode */ + WIU->CTRL |= WIU_Mode_Interrupt; + + /* set the corresponding WUINT bit*/ + WIU->INTR |= WIU_InitStruct->WIU_Line; + } + else + { + /* configure the WIU mode */ + WIU->CTRL |= WIU_InitStruct->WIU_Mode; + } +} + +/****************************************************************************** +* Function Name : WIU_DeInit +* Description : Deinitializes the WIU registers to their default reset values. +* Input : None +* Output : None +* Return : None +******************************************************************************/ +void WIU_DeInit(void) +{ + /* initialize the WIU registers to their reset value */ + SCU_APBPeriphReset(__WIU, ENABLE); + SCU_APBPeriphReset(__WIU, DISABLE); +} + +/****************************************************************************** +* Function Name : WIU_StructInit +* Description : Fills in a WIU_InitTypeDef structure with the reset value of +* each parameter. +* Input : WIU_InitStruct : pointer to a WIU_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +******************************************************************************/ +void WIU_StructInit(WIU_InitTypeDef* WIU_InitStruct) +{ + /* initialize the WIU_InitStruct fields to their reset values */ + WIU_InitStruct->WIU_Mode = 0x0 ; + WIU_InitStruct->WIU_Line = 0x0 ; + WIU_InitStruct->WIU_TriggerEdge = WIU_FallingEdge ; +} + + +/******************************************************************************* +* Function Name : WIU_GenerateSWInterrupt +* Description : Generates a Software interrupt. +* Input : - WIU_Line: specifies the WIU lines to be enabled or +* disabled. This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : None +*******************************************************************************/ +void WIU_GenerateSWInterrupt(u32 WIU_Line) +{ + WIU->INTR |= WIU_Line; +} + +/******************************************************************************* +* Function Name : WIU_GetFlagStatus +* Description : Checks whether the specified WIU line flag is set or not. +* Input : - WIU_Line: specifies the WIU lines flag to check. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : The new state of WIU_Line (SET or RESET). +*******************************************************************************/ +FlagStatus WIU_GetFlagStatus(u32 WIU_Line) +{ + if((WIU->PR & WIU_Line) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WIU_ClearFlag +* Description : Clears the WIU’s line pending flags. +* Input : - WIU_Line: specifies the WIU lines flags to clear. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : None +*******************************************************************************/ +void WIU_ClearFlag(u32 WIU_Line) +{ + WIU->PR = WIU_Line; +} + +/******************************************************************************* +* Function Name : WIU_GetITStatus +* Description : Checks whether the specified WIU line is asserted or not. +* Input : - WIU_Line: specifies the WIU lines to check. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : The new state of WIU_Line (SET or RESET). +*******************************************************************************/ +ITStatus WIU_GetITStatus(u32 WIU_Line) +{ + if(((WIU->PR & WIU_Line) != RESET)&& ((WIU->MR & WIU_Line) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WIU_ClearITPendingBit +* Description : Clears the WIU’s line pending bits. +* Input : - WIU_Line: specifies the WIU lines to clear. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : None +*******************************************************************************/ +void WIU_ClearITPendingBit(u32 WIU_Line) +{ + WIU->PR = WIU_Line; +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_main_add/Makefile b/uc_str912/prj_main_add/Makefile new file mode 100644 index 0000000..96db3a9 --- /dev/null +++ b/uc_str912/prj_main_add/Makefile @@ -0,0 +1,146 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +BIN = $(CP) -O ihex + +MCU = arm9e + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = test + +# Define linker script file here +LDSCRIPT_RAM = ./prj/str912_ram.ld +LDSCRIPT_ROM = ./prj/str912_rom.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List C source files here +SRC = ./src/main.c + +# List ASM source files here +ASRC = ./src/startup.s + +# List all user directories here +UINCDIR = ./inc + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -O0 + +# +# End of user defines +############################################################################################## + + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +LDFLAGS_RAM = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT_RAM) -Wl,-Map=$(PROJECT)_ram.map,--cref,--no-warn-mismatch $(LIBDIR) +LDFLAGS_ROM = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT_ROM) -Wl,-Map=$(PROJECT)_rom.map,--cref,--no-warn-mismatch $(LIBDIR) + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: RAM ROM + +RAM: $(OBJS) $(PROJECT)_ram.elf $(PROJECT)_ram.hex + +ROM: $(OBJS) $(PROJECT)_rom.elf $(PROJECT)_rom.hex + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%ram.elf: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS_RAM) $(LIBS) -o $@ + +%rom.elf: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS_ROM) $(LIBS) -o $@ + +%hex: %elf + $(BIN) $< $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT)_ram.elf + -rm -f $(PROJECT)_ram.map + -rm -f $(PROJECT)_ram.hex + -rm -f $(PROJECT)_rom.elf + -rm -f $(PROJECT)_rom.map + -rm -f $(PROJECT)_rom.hex + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/uc_str912/prj_main_add/dram.bat b/uc_str912/prj_main_add/dram.bat new file mode 100644 index 0000000..9f6bae9 --- /dev/null +++ b/uc_str912/prj_main_add/dram.bat @@ -0,0 +1 @@ +arm-elf-insight -x .\prj\str912_ram.gdb test_ram.elf \ No newline at end of file diff --git a/uc_str912/prj_main_add/inc/typedefs.h b/uc_str912/prj_main_add/inc/typedefs.h new file mode 100644 index 0000000..a7201fd --- /dev/null +++ b/uc_str912/prj_main_add/inc/typedefs.h @@ -0,0 +1,50 @@ +/**************************************************************************** +* Copyright (c) 2006 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +* 30.03.06 mifi First Version for Insight tutorial +****************************************************************************/ +#ifndef __TYPEDEFS_H__ +#define __TYPEDEFS_H__ + +/* + * Some types to use Windows like source + */ +typedef char CHAR; /* 8-bit signed data */ +typedef unsigned char BYTE; /* 8-bit unsigned data */ +typedef unsigned short WORD; /* 16-bit unsigned data */ +typedef long LONG; /* 32-bit signed data */ +typedef unsigned long ULONG; /* 32-bit unsigned data */ +typedef unsigned long DWORD; /* 32-bit unsigned data */ + + +#endif /* !__TYPEDEFS_H__ */ +/*** EOF ***/ diff --git a/uc_str912/prj_main_add/prj/eclipse_ram.gdb b/uc_str912/prj_main_add/prj/eclipse_ram.gdb new file mode 100644 index 0000000..0c72df4 --- /dev/null +++ b/uc_str912/prj_main_add/prj/eclipse_ram.gdb @@ -0,0 +1,24 @@ +target remote localhost:3333 +monitor reset +monitor sleep 500 +monitor poll +monitor soft_reset_halt +monitor arm7_9 sw_bkpts enable + +# Set SRAM size to 96 KB +monitor mww 0x5C002034 0x0197 +monitor mdw 0x5C002034 + +# Set Flash, Bank0 size to 512 KB +monitor mww 0x54000000 0xf + +# needed for gdb 6.8 and higher +set mem inaccessible-by-default off + +load +break main +continue + + + + diff --git a/uc_str912/prj_main_add/prj/eclipse_rom.gdb b/uc_str912/prj_main_add/prj/eclipse_rom.gdb new file mode 100644 index 0000000..3baf4fe --- /dev/null +++ b/uc_str912/prj_main_add/prj/eclipse_rom.gdb @@ -0,0 +1,24 @@ +target remote localhost:3333 +monitor reset +monitor sleep 500 +monitor poll +monitor soft_reset_halt +monitor arm7_9 force_hw_bkpts enable + +# Set SRAM size to 96 KB +monitor mww 0x5C002034 0x0197 +monitor mdw 0x5C002034 + +# Set Flash, Bank0 size to 512 KB +monitor mww 0x54000000 0xf + +# needed for gdb 6.8 and higher +set mem inaccessible-by-default off + +load +break main +continue + + + + diff --git a/uc_str912/prj_main_add/prj/jtagkey.cfg b/uc_str912/prj_main_add/prj/jtagkey.cfg new file mode 100644 index 0000000..4a25c96 --- /dev/null +++ b/uc_str912/prj_main_add/prj/jtagkey.cfg @@ -0,0 +1,59 @@ +# daemon configuration +telnet_port 4444 +gdb_port 3333 + +# tell gdb our flash memory map +# and enable flash programming +gdb_memory_map enable +gdb_flash_program enable + +# +# interface, if you want to use an other interface +# you must replace this section here +# +#################### interface start #################### + +interface ft2232 +ft2232_device_desc "Amontec JTAGkey A" +ft2232_layout jtagkey +ft2232_vid_pid 0x0403 0xcff8 + +##################### interface end ##################### + +# jtag speed +# start slow, speed up after reset +jtag_khz 16 2000 + +#delays on reset lines +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 8 0x1 0x1 0xfe +jtag_device 4 0x1 0xf 0xe +jtag_device 5 0x1 0x1 0x1e + +#target configuration +daemon_startup reset + +#target +#target arm7tdmi +target arm966e little reset_halt 1 arm966e +run_and_halt_time 0 30 + +target_script 0 reset ./prj/str912_reset.script + +target_script 0 gdb_program_config ./prj/str912_program.script + +working_area 0 0x50000000 16384 nobackup + +#flash bank str9x 0 0 +flash bank str9x 0x00000000 0x00080000 0 0 0 +flash bank str9x 0x00080000 0x00008000 0 0 0 + +# For more information about the configuration files, take a +# look at the "Open On-Chip Debugger (openocd)" documentation. diff --git a/uc_str912/prj_main_add/prj/str912_program.script b/uc_str912/prj_main_add/prj/str912_program.script new file mode 100644 index 0000000..9f88149 --- /dev/null +++ b/uc_str912/prj_main_add/prj/str912_program.script @@ -0,0 +1,2 @@ +str9x flash_config 0 4 2 0 0x80000 +flash protect 0 0 7 off diff --git a/uc_str912/prj_main_add/prj/str912_ram.gdb b/uc_str912/prj_main_add/prj/str912_ram.gdb new file mode 100644 index 0000000..892f14b --- /dev/null +++ b/uc_str912/prj_main_add/prj/str912_ram.gdb @@ -0,0 +1,22 @@ +target remote localhost:3333 +monitor reset +monitor sleep 500 +monitor poll +monitor soft_reset_halt +monitor arm7_9 sw_bkpts enable + +# Set SRAM size to 96 KB +monitor mww 0x5C002034 0x0197 +monitor mdw 0x5C002034 + +# needed for gdb 6.8 and higher +set mem inaccessible-by-default off + +load +break main +continue + + + + + diff --git a/uc_str912/prj_main_add/prj/str912_ram.ld b/uc_str912/prj_main_add/prj/str912_ram.ld new file mode 100644 index 0000000..0974b39 --- /dev/null +++ b/uc_str912/prj_main_add/prj/str912_ram.ld @@ -0,0 +1,218 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 0; + _STACKSIZE_SVC = 1024; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t .glue_7) + KEEP(*(.fini)) + *(.gcc_except_table) + } >DATA =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >DATA + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >DATA + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >DATA + . = ALIGN(4); + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } >DATA + . = ALIGN(4); + + __data_start = .; + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/prj_main_add/prj/str912_reset.script b/uc_str912/prj_main_add/prj/str912_reset.script new file mode 100644 index 0000000..8c222a8 --- /dev/null +++ b/uc_str912/prj_main_add/prj/str912_reset.script @@ -0,0 +1,2 @@ +# -- Enable 96K RAM */ +mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled diff --git a/uc_str912/prj_main_add/prj/str912_rom.gdb b/uc_str912/prj_main_add/prj/str912_rom.gdb new file mode 100644 index 0000000..4b2649c --- /dev/null +++ b/uc_str912/prj_main_add/prj/str912_rom.gdb @@ -0,0 +1,22 @@ +target remote localhost:3333 +monitor reset +monitor sleep 500 +monitor poll +monitor soft_reset_halt +monitor arm7_9 force_hw_bkpts enable + +# Set SRAM size to 96 KB +monitor mww 0x5C002034 0x0197 +monitor mdw 0x5C002034 + +# needed for gdb 6.8 and higher +set mem inaccessible-by-default off + +load +break main +continue + + + + + diff --git a/uc_str912/prj_main_add/prj/str912_rom.ld b/uc_str912/prj_main_add/prj/str912_rom.ld new file mode 100644 index 0000000..8cbb7f7 --- /dev/null +++ b/uc_str912/prj_main_add/prj/str912_rom.ld @@ -0,0 +1,249 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 0; + _STACKSIZE_SVC = 1024; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + CREATE_OBJECT_SYMBOLS + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + KEEP(*(.fini)) + *(.gcc_except_table) + } >CODE =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >CODE + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >CODE + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >CODE + . = ALIGN(4); + + .init_array : + { + *(.init) + *(.fini) + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >CODE + + . = ALIGN(4); + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >CODE + __exidx_end = .; + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + __data_start = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + . = ALIGN(4); + *(.fastrun .fastrun.*) + } >DATA + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/prj_main_add/segger.gdb b/uc_str912/prj_main_add/segger.gdb new file mode 100644 index 0000000..31f9031 --- /dev/null +++ b/uc_str912/prj_main_add/segger.gdb @@ -0,0 +1,17 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:2331 + +monitor speed adaptive +monitor endian little + +monitor reset +monitor flash device = STR912FAW44 +monitor flash breakpoints = 1 +monitor flash download = 1 +monitor halt + +pwd diff --git a/uc_str912/prj_main_add/src/main.c b/uc_str912/prj_main_add/src/main.c new file mode 100644 index 0000000..b846536 --- /dev/null +++ b/uc_str912/prj_main_add/src/main.c @@ -0,0 +1,91 @@ +/**************************************************************************** +* Copyright (c) 2006 by Michael Fischer. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the author nor the names of its contributors may +* be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +* SUCH DAMAGE. +* +**************************************************************************** +* History: +* +* 30.03.06 mifi First Version for Insight tutorial +* 26.01.08 mifi Added variable "d" to test const variable. +****************************************************************************/ +#define __MAIN_C__ + +/* + * I use the include only, to show + * how to setup a include dir in the makefile + */ +#include "typedefs.h" + +/*=========================================================================*/ +/* DEFINE: All Structures and Common Constants */ +/*=========================================================================*/ + +/*=========================================================================*/ +/* DEFINE: Prototypes */ +/*=========================================================================*/ + +/*=========================================================================*/ +/* DEFINE: Definition of all local Data */ +/*=========================================================================*/ +static const DWORD d = 7; + +/*=========================================================================*/ +/* DEFINE: Definition of all local Procedures */ +/*=========================================================================*/ + +/*=========================================================================*/ +/* DEFINE: All code exported */ +/*=========================================================================*/ +/***************************************************************************/ +/* main */ +/***************************************************************************/ +int main (void) +{ + DWORD a = 1; + DWORD b = 2; + DWORD c = 0; + + a = a + d; + + while (1) + { + a++; + b++; + c = a + b; + } + + /* + * This return here make no sense. + * But to prevent the compiler warning: + * "return type of 'main' is not 'int' + * we use an int as return :-) + */ + return(0); +} + +/*** EOF ***/ diff --git a/uc_str912/prj_main_add/src/startup.s b/uc_str912/prj_main_add/src/startup.s new file mode 100644 index 0000000..cdf2c44 --- /dev/null +++ b/uc_str912/prj_main_add/src/startup.s @@ -0,0 +1,222 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +* mifi, 22.01.2008, small changes by the init of the C++ eabi constructors. +* Here I have replaced the eabi init by the normal init. +* Thanks to Spen for the startup code. +***********************************************************************************/ + +/**** Startup Code (executed after Reset) ****/ + +/* Frequency values kHz */ +/* set to suit target hardware */ + + .equ FOSC, 25000 + +/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */ + + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + .equ SRAM32, 0x00 + .equ SRAM64, 0x08 + .equ SRAM96, 0x10 + +/* --- System memory locations */ + + .equ SCRO_AHB_UMB, 0x5C002034 /* System configuration register 0 (unbuffered) */ + + .equ FMI_BASE_UMB, 0x54000000 /* Flash FMI base address (unbuffered) */ + .equ BBSR_off_addr, 0x00 + .equ NBBSR_off_addr, 0x04 + .equ BBADR_off_addr, 0x0C + .equ NBBADR_off_addr, 0x10 + .equ CR_off_addr, 0x18 + +.ifndef LIBUFF + .equ LIBUFF, 0 +.endif + +/* Startup Code must be linked first at Address at which it expects to run. */ + + .text + .arm + .section .init, "ax" + + .global _start + .global _Main_Crystal + +/* After remap this will be our reset handler */ + +_start: + LDR pc, =NextInst +NextInst: + + NOP /* Wait for OSC stabilization */ + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +/* Enable buffered mode */ + +.if LIBUFF + MRC p15, 0, r0, c1, c0, 0 /* Read CP15 register 1 into r0 */ + ORR r0, r0, #0x8 /* Enable Write Buffer on AHB */ + MCR p15, 0, r0, c1, c0, 0 /* Write CP15 register 1 */ +.endif + +/* Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, */ +/* when the bank 0 is the boot bank, then enable the Bank 1. */ + + LDR r0, =FMI_BASE_UMB + LDR r1, =0x4 /* configure 512KB Boot bank 0 */ + STR r1, [r0, #BBSR_off_addr] + + LDR r1, =0x2 /* configure 32KB Non Boot bank 1 */ + STR r1, [r0, #NBBSR_off_addr] + + LDR r1, =(0x00000000 >> 2) /* Boot Bank Base Address */ + STR r1, [r0, #BBADR_off_addr] + + LDR r1, =(0x00080000 >> 2) /* Non Boot Bank Base Address */ + STR r1, [r0, #NBBADR_off_addr] + + LDR r1, =0x18 /* Flash Banks 0 1 enabled */ + STR r1, [r0, #CR_off_addr] + +/* Enable 96K RAM */ + + LDR r0, =SCRO_AHB_UMB +# LDR r1, =0x0196 /* prefetch disabled, default enabled */ + LDR r1, =0x0187|SRAM96 + STR r1, [r0] + +/* Set bits 17-18 (Instruction/Data TCM order) of the */ +/* Core Configuration Control Register */ + + MOV r0, #0x60000 + MCR p15, 0x1, r0, c15, c1, 0 + +/* Setup Stack for each mode */ + +/* Enter Abort Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_ABT|I_Bit|F_Bit + LDR sp, =__stack_abt_end__ + +/* Enter Undefined Instruction Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_UND|I_Bit|F_Bit + LDR sp, =__stack_und_end__ + +/* Enter Supervisor Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SVC|I_Bit|F_Bit + LDR sp, =__stack_svc_end__ + +/* Enter FIQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_FIQ|I_Bit|F_Bit + LDR sp, =__stack_fiq_end__ + +/* Enter IRQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit + LDR sp, =__stack_irq_end__ + +/* Enter System/User Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SYS + LDR sp, =__stack_end__ + +/* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */ + + LDR sl, =__bss_end__ + +/* Relocate .data section (Copy from ROM to RAM) */ + + LDR r1, =_etext + LDR r2, =__data_start + LDR r3, =_edata +LoopRel: + CMP r2, r3 + LDRLO r0, [r1], #4 + STRLO r0, [r2], #4 + BLO LoopRel + +/* Clear .bss section (Zero init) */ + + MOV r0, #0 + LDR r1, =__bss_start__ + LDR r2, =__bss_end__ +LoopZI: + CMP r1, r2 + STRLO r0, [r1], #4 + BLO LoopZI + +/* Call C++ constructors */ + + LDR r0, =__ctors_start__ + LDR r1, =__ctors_end__ +ctor_loop: + CMP r0, r1 + BEQ ctor_end + LDR r2, [r0], #4 + STMFD sp!, {r0-r1} + BLX r2 + LDMFD sp!, {r0-r1} + B ctor_loop +ctor_end: + +/* Need to set up standard file handles */ +/* Only used under simulator, normally overide syscall.c */ + +# BL initialise_monitor_handles + +/* if we use debug version of str9lib this will call the init function */ + + BL libdebug +libdebug: + +/* Enter the C code, use B instruction so as to never return */ +/* use BL main if you want to use c++ destructors below */ + + B main + +/* Return from main, loop forever. */ + +#exit_loop: +# B exit_loop + +/* Fosc values, used by libstr9 */ + +_Main_Crystal: .long FOSC + + .weak libdebug + + .end diff --git a/uc_str912/prj_template91x/Makefile b/uc_str912/prj_template91x/Makefile new file mode 100644 index 0000000..7dad7f7 --- /dev/null +++ b/uc_str912/prj_template91x/Makefile @@ -0,0 +1,495 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# WinARM template makefile +# by Giacomo Fazio and Antonio Nasca, Catania, Italy +# +# +# +# based on the WinARM template makefile written by Martin Thomas +# Released to the Public Domain +# Please read the make user manual! +# +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make program = Download the hex file to the device +# +# (TODO: make filename.s = Just compile filename.c into the assembler code only) +# +# To rebuild project do "make clean" then "make all". +# Toolchain prefix (i.e arm-elf -> arm-elf-gcc.exe) +#TCHAIN = arm-elf +TCHAIN = arm-none-eabi + +#USE_THUMB_MODE = YES +USE_THUMB_MODE = NO + +# MCU name and submodel +MCU = arm966e-s +SUBMDL = STR91x + +## Create ROM-Image +RUN_MODE=ROM_RUN +## Create RAM-Image +#RUN_MODE=RAM_RUN + +## not supported in this example: +## Exception-Vector placement only supported for "ROM_RUN" +## (placement settings ignored when using "RAM_RUN") +## - Exception vectors in ROM: +#VECTOR_LOCATION=VECTORS_IN_ROM +## - Exception vectors in RAM: +#VECTOR_LOCATION=VECTORS_IN_RAM + + +# Target file name (without extension). +TARGET = main + +# List C source files here. (C dependencies are automatically generated.) +# use file-extension c for "c-only"-files +SRC = src/$(TARGET).c + +# List C source files here which must be compiled in ARM-Mode. +# use file-extension c for "c-only"-files +SRCARM = src/vectors.c +# thumb is possible too for vectors.c - keep ARM, TODO: profile + +# List C++ source files here. +# use file-extension cpp for C++-files (use extension .cpp) +CPPSRC = + +# List C++ source files here which must be compiled in ARM-Mode. +# use file-extension cpp for C++-files (use extension .cpp) +#CPPSRCARM = $(TARGET).cpp +CPPSRCARM = + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +# List Assembler source files here which must be assembled in ARM-Mode.. +ASRCARM = src/vector.S src/startup.S + +# Path to Linker-Scripts +LINKERSCRIPTPATH = . + +## Output format. (can be ihex or binary or both) +## (binary i.e. for openocd and SAM-BA, hex i.e. for lpc21isp and uVision) +#FORMAT = ihex +#FORMAT = binary +FORMAT = both + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +#OPT = s +OPT = 0 + +## Using the Atmel AT91_lib produces warning with +## the default warning-levels. +## yes - disable these warnings; no - keep default settings +#AT91LIBNOWARN = yes +AT91LIBNOWARN = no + +# Debugging format. +# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2. +# AVR (extended) COFF requires stabs, plus an avr-objcopy run. +#DEBUG = stabs +DEBUG = dwarf-2 + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +EXTRAINCDIRS = ./include ./str91x_lib/include + +# List any extra directories to look for library files here. +# Each directory must be seperated by a space. +#EXTRA_LIBDIRS = ../arm7_efsl_0_2_4 +EXTRA_LIBDIRS = ./str91x_lib + + +# Compiler flag to set the C Standard level. +# c89 - "ANSI" C +# gnu89 - c89 plus GCC extensions +# c99 - ISO C99 standard (not yet fully implemented) +# gnu99 - c99 plus GCC extensions +CSTANDARD = -std=gnu99 + +# Place -D or -U options for C here +CDEFS = -D$(RUN_MODE) + +# Place -I options here +CINCS = + +# Place -D or -U options for ASM here +ADEFS = -D$(RUN_MODE) + +ifdef VECTOR_LOCATION +CDEFS += -D$(VECTOR_LOCATION) +ADEFS += -D$(VECTOR_LOCATION) +endif + +CDEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__ +ADEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__ + +# Compiler flags. + +ifeq ($(USE_THUMB_MODE),YES) +THUMB = -mthumb +THUMB_IW = -mthumb-interwork +else +THUMB = +THUMB_IW = +endif + +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +# +# Flags for C and C++ (arm-elf-gcc/arm-elf-g++) +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) $(CINCS) +CFLAGS += -O$(OPT) +CFLAGS += -Wall -Wcast-align -Wimplicit +CFLAGS += -Wpointer-arith -Wswitch +CFLAGS += -ffunction-sections -fdata-sections +CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused +CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +# flags only for C +CONLYFLAGS += -Wnested-externs +CONLYFLAGS += $(CSTANDARD) + +ifneq ($(AT91LIBNOWARN),yes) +#AT91-lib warnings with: +CFLAGS += -Wcast-qual +CONLYFLAGS += -Wmissing-prototypes +CONLYFLAGS += -Wstrict-prototypes +CONLYFLAGS += -Wmissing-declarations +endif + +# flags only for C++ (arm-elf-g++) +# CPPFLAGS = -fno-rtti -fno-exceptions +CPPFLAGS = + +# Assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlns: create listing +# -g$(DEBUG): have the assembler create line number information +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst), -g$(DEBUG) + + +#Additional libraries. + +# Extra libraries +# Each library-name must be seperated by a space. +# To add libxyz.a, libabc.a and libefsl.a: +# EXTRA_LIBS = xyz abc efsl +#EXTRA_LIBS = efsl +EXTRA_LIBS = STR91x_lib + +#Support for newlibc-lpc (file: libnewlibc-lpc.a) +#NEWLIBLPC = -lnewlib-lpc + +MATH_LIB = -lm + +# CPLUSPLUS_LIB = -lstdc++ + + +# Linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref,--gc-sections,--no-warn-mismatch +LDFLAGS += -lc +LDFLAGS += $(NEWLIBLPC) $(MATH_LIB) +LDFLAGS += -lc -lgcc +LDFLAGS += $(CPLUSPLUS_LIB) +LDFLAGS += $(patsubst %,-L%,$(EXTRA_LIBDIRS)) +LDFLAGS += $(patsubst %,-l%,$(EXTRA_LIBS)) + +# Set Linker-Script Depending On Selected Memory and Controller +ifeq ($(RUN_MODE),RAM_RUN) +LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-RAM.ld +else +LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-ROM.ld +endif + + +# Define directories, if needed. +## DIRARM = c:/WinARM/ +## DIRARMBIN = $(DIRAVR)/bin/ +## DIRAVRUTILS = $(DIRAVR)/utils/bin/ + +# Define programs and commands. +SHELL = sh +CC = $(TCHAIN)-gcc +CPP = $(TCHAIN)-g++ +AR = $(TCHAIN)-ar +OBJCOPY = $(TCHAIN)-objcopy +OBJDUMP = $(TCHAIN)-objdump +SIZE = $(TCHAIN)-size +NM = $(TCHAIN)-nm +REMOVE = rm -f +REMOVEDIR = rm -f -r +COPY = cp + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = "-------- begin (mode: $(RUN_MODE)) --------" +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_FLASH = Creating load file for Flash: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_ARM = "Compiling C (ARM-only):" +MSG_COMPILINGCPP = Compiling C++: +MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):" +MSG_ASSEMBLING = Assembling: +MSG_ASSEMBLING_ARM = "Assembling (ARM-only):" +MSG_CLEANING = Cleaning project: +MSG_FORMATERROR = Can not handle output-format +MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now. + +# Define all object files. +COBJ = $(SRC:.c=.o) +AOBJ = $(ASRC:.S=.o) +COBJARM = $(SRCARM:.c=.o) +AOBJARM = $(ASRCARM:.S=.o) +CPPOBJ = $(CPPSRC:.cpp=.o) +CPPOBJARM = $(CPPSRCARM:.cpp=.o) + +# Define all listing files. +LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst) +LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst) + +# Compiler flags to generate dependency files. +### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d +GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mcpu=$(MCU) -msoft-float $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mcpu=$(MCU) -msoft-float $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS) + + +# Default target. +all: begin gccversion sizebefore build sizeafter finished end + +ifeq ($(FORMAT),ihex) +build: elf hex lss sym +hex: $(TARGET).hex +IMGEXT=hex +else +ifeq ($(FORMAT),binary) +build: elf bin lss sym +bin: $(TARGET).bin +IMGEXT=bin +else +ifeq ($(FORMAT),both) +build: elf hex bin lss sym +hex: $(TARGET).hex +bin: $(TARGET).bin +else +$(error "$(MSG_FORMATERROR) $(FORMAT)") +endif +endif +endif + +elf: $(TARGET).elf +lss: $(TARGET).lss +sym: $(TARGET).sym + +# Eye candy. +begin: + @echo + @echo $(MSG_BEGIN) + +finished: + @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf +sizebefore: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + + +# Display compiler version information. +gccversion : + @$(CC) --version + +# FLASH Programming with OPENOCD + +# specify the directory where openocd executable resides (openocd-ftd2xx.exe or openocd-pp.exe) +# Note: you may have to adjust this if a newer version of YAGARTO has been downloaded +OPENOCD_DIR = '/usr/local/bin/' + +# specify OpenOCD executable (pp is for the wiggler, ftd2xx is for the USB debugger) +OPENOCD = $(OPENOCD_DIR)openocd +#OPENOCD = $(OPENOCD_DIR)openocd-ftd2xx.exe + +# specify OpenOCD configuration file (pick the one for your device) +#OPENOCD_CFG = /home/l3golas/openocd-configs/str91x-configs/str91x_signalyzer-flash-program.cfg +#OPENOCD_CFG = /home/l3golas/openocd-configs/str91x-configs/str91x_jtagkey-flash-program.cfg +#OPENOCD_CFG = /home/l3golas/openocd-configs/str91x-configs/str91x_armusbocd-flash-program.cfg +OPENOCD_CFG = /home/l3golas/openocd-configs/str91x-configs/str91x_pp-flash-program.cfg + +program: + @echo + @echo "Flash Programming with OpenOCD..." + $(OPENOCD) -f $(OPENOCD_CFG) + @echo + @echo + @echo "Flash Programming Finished." + + +# Create final output file (.hex) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O ihex $< $@ + +# Create final output file (.bin) from ELF output file. +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary $< $@ + + +# Create extended listing file from ELF output file. +# testing: option -C +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S -C $< > $@ + + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) +%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) +# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) + +# Compile: create object files from C source files. ARM/Thumb +$(COBJ) : %.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C source files. ARM-only +$(COBJARM) : %.o : %.c + @echo + @echo $(MSG_COMPILING_ARM) $< + $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM/Thumb +$(CPPOBJ) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP) $< + $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM-only +$(CPPOBJARM) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP_ARM) $< + $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. ARM/Thumb +## does not work - TODO - hints welcome +##$(COBJ) : %.s : %.c +## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM/Thumb +$(AOBJ) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM-only +$(AOBJARM) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING_ARM) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list finished end + + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).a90 + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lnk + $(REMOVE) $(TARGET).lss + $(REMOVE) $(COBJ) + $(REMOVE) $(CPPOBJ) + $(REMOVE) $(AOBJ) + $(REMOVE) $(COBJARM) + $(REMOVE) $(CPPOBJARM) + $(REMOVE) $(AOBJARM) + $(REMOVE) $(LST) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRCARM:.c=.s) + $(REMOVE) $(SRCARM:.c=.d) + $(REMOVE) $(CPPSRC:.cpp=.s) + $(REMOVE) $(CPPSRC:.cpp=.d) + $(REMOVE) $(CPPSRCARM:.cpp=.s) + $(REMOVE) $(CPPSRCARM:.cpp=.d) + $(REMOVEDIR) .dep | exit 0 + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin lss sym clean clean_list program + diff --git a/uc_str912/prj_template91x/STR91x-RAM.ld b/uc_str912/prj_template91x/STR91x-RAM.ld new file mode 100644 index 0000000..aced384 --- /dev/null +++ b/uc_str912/prj_template91x/STR91x-RAM.ld @@ -0,0 +1,218 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 256; + _STACKSIZE_SVC = 0; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t .glue_7) + KEEP(*(.fini)) + *(.gcc_except_table) + } >DATA =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >DATA + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >DATA + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >DATA + . = ALIGN(4); + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } >DATA + . = ALIGN(4); + + __data_start = .; + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/prj_template91x/STR91x-ROM.ld b/uc_str912/prj_template91x/STR91x-ROM.ld new file mode 100644 index 0000000..ed2979b --- /dev/null +++ b/uc_str912/prj_template91x/STR91x-ROM.ld @@ -0,0 +1,221 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 256; + _STACKSIZE_SVC = 0; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t .glue_7) + KEEP(*(.fini)) + *(.gcc_except_table) + } >CODE =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >CODE + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >CODE + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >CODE + . = ALIGN(4); + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + __data_start = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + . = ALIGN(4); + *(.fastrun .fastrun.*) + } >DATA + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/prj_template91x/include/vectors.h b/uc_str912/prj_template91x/include/vectors.h new file mode 100644 index 0000000..d48e61f --- /dev/null +++ b/uc_str912/prj_template91x/include/vectors.h @@ -0,0 +1,67 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +#ifndef _VECTOR_H +#define _VECTOR_H + +#ifdef __cplusplus +extern "C" { +#endif + +void Undefined_Handler(void); +void FIQ_Handler(void); +void SWI_Handler(void); +void Prefetch_Handler(void); +void Abort_Handler(void); +void WDG_IRQHandler(void); +void SW_IRQHandler(void); +void ARMRX_IRQHandler(void); +void ARMTX_IRQHandler(void); +void TIM0_IRQHandler(void); +void TIM1_IRQHandler(void); +void TIM2_IRQHandler(void); +void TIM3_IRQHandler(void); +void USBHP_IRQHandler(void); +void USBLP_IRQHandler(void); +void SCU_IRQHandler(void); +void ENET_IRQHandler(void); +void DMA_IRQHandler(void); +void CAN_IRQHandler(void); +void MC_IRQHandler(void); +void ADC_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void I2C0_IRQHandler(void); +void I2C1_IRQHandler(void); +void SSP0_IRQHandler(void); +void SSP1_IRQHandler(void); +void LVD_IRQHandler(void); +void RTC_IRQHandler(void); +void WIU_IRQHandler(void); +void EXTIT0_IRQHandler(void); +void EXTIT1_IRQHandler(void); +void EXTIT2_IRQHandler(void); +void EXTIT3_IRQHandler(void); +void USBWU_IRQHandler(void); +void PFQBC_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif //_VECTOR_H diff --git a/uc_str912/prj_template91x/load_segger.gdb b/uc_str912/prj_template91x/load_segger.gdb new file mode 100644 index 0000000..fe98dd4 --- /dev/null +++ b/uc_str912/prj_template91x/load_segger.gdb @@ -0,0 +1,23 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:2331 + +monitor speed adaptive +monitor endian little + +monitor reset +monitor flash device = STR912FAW44 +monitor flash breakpoints = 1 +monitor flash download = 1 +monitor halt + + +pwd +load main.elf +file main.elf +step +break after_delay +continue diff --git a/uc_str912/prj_template91x/src/main.c b/uc_str912/prj_template91x/src/main.c new file mode 100644 index 0000000..62d3c59 --- /dev/null +++ b/uc_str912/prj_template91x/src/main.c @@ -0,0 +1,43 @@ +/******************** (C) COPYRIGHT 2005 STMicroelectronics ******************** +* File Name : main.c +* Author : MCD Application Team +* Date First Issued : 09/27/2005 : V1.0 +* Description : Main program body +********************************************************************************** +* History: +* 09/27/2005 : V1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +/* Standard include ------------------------------------------------------------*/ +#include "91x_lib.h" + +/* Include of other module interface headers -----------------------------------*/ +/* Local includes --------------------------------------------------------------*/ +/* Private typedef -------------------------------------------------------------*/ +/* Private define --------------------------------------------------------------*/ +/* Private macro ---------------------------------------------------------------*/ +/* Private variables -----------------------------------------------------------*/ + + +/*---------------------------------main---------------------------------------*/ + +void main() +{ + #ifdef LIBDEBUG + libdebug(); + #endif + int a=4; + int b=5; + int c; + c=a+b; +} + + +/******************* (C) COPYRIGHT 2005 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/src/startup.S b/uc_str912/prj_template91x/src/startup.S new file mode 100755 index 0000000..cef54d8 --- /dev/null +++ b/uc_str912/prj_template91x/src/startup.S @@ -0,0 +1,233 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/**** Startup Code (executed after Reset) ****/ + +/* Frequency values kHz */ +/* set to suit target hardware */ + + .equ FOSC, 25000 + +/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */ + + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + .equ SRAM32, 0x00 + .equ SRAM64, 0x08 + .equ SRAM96, 0x10 + +/* --- System memory locations */ + + .equ SCRO_AHB_UMB, 0x5C002034 /* System configuration register 0 (unbuffered) */ + + .equ FMI_BASE_UMB, 0x54000000 /* Flash FMI base address (unbuffered) */ + .equ BBSR_off_addr, 0x00 + .equ NBBSR_off_addr, 0x04 + .equ BBADR_off_addr, 0x0C + .equ NBBADR_off_addr, 0x10 + .equ CR_off_addr, 0x18 + +.ifndef LIBUFF + .equ LIBUFF, 0 +.endif + +/* Startup Code must be linked first at Address at which it expects to run. */ + + .text + .arm + .section .init, "ax" + + .global _start + .global _Main_Crystal + +/* After remap this will be our reset handler */ + +_start: + LDR pc, =NextInst +NextInst: + + NOP /* Wait for OSC stabilization */ + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + +/* Enable buffered mode */ + +.if LIBUFF + MRC p15, 0, r0, c1, c0, 0 /* Read CP15 register 1 into r0 */ + ORR r0, r0, #0x8 /* Enable Write Buffer on AHB */ + MCR p15, 0, r0, c1, c0, 0 /* Write CP15 register 1 */ +.endif + +/* Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, */ +/* when the bank 0 is the boot bank, then enable the Bank 1. */ + + LDR r0, =FMI_BASE_UMB + LDR r1, =0x4 /* configure 512KB Boot bank 0 */ + STR r1, [r0, #BBSR_off_addr] + + LDR r1, =0x2 /* configure 32KB Non Boot bank 1 */ + STR r1, [r0, #NBBSR_off_addr] + + LDR r1, =(0x00000000 >> 2) /* Boot Bank Base Address */ + STR r1, [r0, #BBADR_off_addr] + + LDR r1, =(0x00080000 >> 2) /* Non Boot Bank Base Address */ + STR r1, [r0, #NBBADR_off_addr] + + LDR r1, =0x18 /* Flash Banks 0 1 enabled */ + STR r1, [r0, #CR_off_addr] + +/* Enable 96K RAM */ + + LDR r0, =SCRO_AHB_UMB +# LDR r1, =0x0196 /* prefetch disabled, default enabled */ + LDR r1, =0x0187|SRAM96 + STR r1, [r0] + +/* Set bits 17-18 (Instruction/Data TCM order) of the */ +/* Core Configuration Control Register */ + + MOV r0, #0x60000 + MCR p15, 0x1, r0, c15, c1, 0 + +/* Setup Stack for each mode */ + +/* Enter Abort Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_ABT|I_Bit|F_Bit + LDR sp, =__stack_abt_end__ + +/* Enter Undefined Instruction Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_UND|I_Bit|F_Bit + LDR sp, =__stack_und_end__ + +/* Enter Supervisor Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SVC|I_Bit|F_Bit + LDR sp, =__stack_svc_end__ + +/* Enter FIQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_FIQ|I_Bit|F_Bit + LDR sp, =__stack_fiq_end__ + +/* Enter IRQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit + LDR sp, =__stack_irq_end__ + +/* Enter System/User Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SYS + LDR sp, =__stack_end__ + +/* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */ + + LDR sl, =__bss_end__ + +/* Relocate .data section (Copy from ROM to RAM) */ + + LDR r1, =_etext + LDR r2, =__data_start + LDR r3, =_edata +LoopRel: + CMP r2, r3 + LDRLO r0, [r1], #4 + STRLO r0, [r2], #4 + BLO LoopRel + +/* Clear .bss section (Zero init) */ + + MOV r0, #0 + LDR r1, =__bss_start__ + LDR r2, =__bss_end__ +LoopZI: + CMP r1, r2 + STRLO r0, [r1], #4 + BLO LoopZI + +/* Call C++ constructors */ + + LDR r0, =__ctors_start__ + LDR r1, =__ctors_end__ +ctor_loop: + CMP r0, r1 + BEQ ctor_end + LDR r2, [r0], #4 + STMFD sp!, {r0-r1} + BLX r2 + LDMFD sp!, {r0-r1} + B ctor_loop +ctor_end: + +/* Need to set up standard file handles */ +/* Only used under simulator, normally overide syscall.c */ + +# BL initialise_monitor_handles + +/* if we use debug version of str9lib this will call the init function */ + + BL libdebug +libdebug: + +/* Enter the C code, use B instruction so as to never return */ +/* use BL main if you want to use c++ destructors below */ + + B main + +/* Call destructors */ + +# LDR r0, =__dtors_start__ +# LDR r1, =__dtors_end__ +#dtor_loop: +# CMP r0, r1 +# BEQ dtor_end +# LDR r2, [r0], #4 +# STMFD sp!, {r0-r1} +# BLX r2 +# LDMFD sp!, {r0-r1} +# B dtor_loop +#dtor_end: + +/* Return from main, loop forever. */ + +#exit_loop: +# B exit_loop + +/* Fosc values, used by libstr9 */ + +_Main_Crystal: .long FOSC + + .weak libdebug + + .end diff --git a/uc_str912/prj_template91x/src/vector.S b/uc_str912/prj_template91x/src/vector.S new file mode 100755 index 0000000..7708f54 --- /dev/null +++ b/uc_str912/prj_template91x/src/vector.S @@ -0,0 +1,202 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + + .equ VectorAddress, 0xFFFFF030 /* VIC Vector address register address. */ + .equ VectorAddressDaisy, 0xFC000030 /* Daisy VIC Vector address register */ + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */ + + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + .text + .arm + .section .vectors, "ax" + + .global Reset_Vec + +/* Note: LDR PC instructions are used here, though branch (B) instructions */ +/* could also be used, unless the ROM is at an address >32MB. */ + +/******************************************************************************* + Exception vectors +*******************************************************************************/ + +Reset_Vec: LDR pc, Reset_Addr /* Reset Handler */ +Undef_Vec: LDR pc, Undefined_Addr +SWI_Vec: LDR pc, SWI_Addr +PAbt_Vec: LDR pc, Prefetch_Addr +DAbt_Vec: LDR pc, Abort_Addr + NOP /* Reserved vector */ +IRQ_Vec: LDR pc, IRQ_Addr +FIQ_Vec: LDR pc, FIQ_Addr + +/******************************************************************************* + Exception handlers address table +*******************************************************************************/ + +Reset_Addr: .word _start +Undefined_Addr: .word UndefinedHandler +SWI_Addr: .word SWIHandler +Prefetch_Addr: .word PrefetchHandler +Abort_Addr: .word AbortHandler + .word 0 /* reserved */ +IRQ_Addr: .word IRQHandler +FIQ_Addr: .word FIQHandler + +/******************************************************************************* + Exception Handlers +*******************************************************************************/ + +/******************************************************************************* +* Macro Name : SaveContext +* Description : This macro used to save the context before entering + an exception handler. +* Input : The range of registers to store. +* Output : none +*******************************************************************************/ + +.macro SaveContext reg1 reg2 + STMFD sp!,{\reg1-\reg2,lr} /* Save The workspace plus the current return */ + /* address lr_ mode into the stack */ + MRS r1, spsr /* Save the spsr_mode into r1 */ + STMFD sp!, {r1} /* Save spsr */ +.endm + +/******************************************************************************* +* Macro Name : RestoreContext +* Description : This macro used to restore the context to return from + an exception handler and continue the program execution. +* Input : The range of registers to restore. +* Output : none +*******************************************************************************/ + +.macro RestoreContext reg1 reg2 + LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */ + MSR spsr_cxsf, r1 /* Restore spsr_mode */ + LDMFD sp!, {\reg1-\reg2,pc}^ /* Return to the instruction following */ + /* the exception interrupt */ +.endm + +/******************************************************************************* +* Function Name : IRQHandler +* Description : This function called when IRQ exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +IRQHandler: + SUB lr, lr, #4 /* Update the link register */ + SaveContext r0, r12 /* Save the workspace plus the current */ + /* return address lr_irq and spsr_irq */ + LDR r0, =VectorAddress + LDR r0, [r0] /* Read the routine address */ + LDR r1, =VectorAddressDaisy + LDR r1, [r1] + /* Padding between the acknowledge and re-enable of interrupts */ + /* For more details, please refer to the following URL */ + /* http://www.arm.com/support/faqip/3682.html */ + NOP + NOP + MSR cpsr_c, #Mode_SYS /* Switch to SYS mode and enable IRQ */ + STMFD sp!, {lr} /* Save the link register. */ + LDR lr, =ReturnAddress /* Read the return address. */ + MOV pc, r0 /* Branch to the IRQ handler. */ +ReturnAddress: + LDMFD sp!, {lr} /* Restore the link register. */ + MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit /* Switch to IRQ mode and disable IRQ */ + LDR r0, =VectorAddress /* Write to the VectorAddress to clear the */ + STR r0, [r0] /* respective interrupt in the internal interrupt */ + LDR r1, =VectorAddressDaisy /* Write to the VectorAddressDaisy to clear the */ + STR r1, [r1] /* respective interrupt in the internal interrupt */ + RestoreContext r0, r12 /* Restore the context and return to the program execution. */ + +/******************************************************************************* +* Function Name : SWIHandler +* Description : This function called when SWI instruction executed. +* Input : none +* Output : none +*******************************************************************************/ + +SWIHandler: + SaveContext r0, r12 /* r0 holds swi number */ + MOV r1, sp /* load regs */ + BL SWI_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : UndefinedHandler +* Description : This function called when undefined instruction + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +UndefinedHandler: + SaveContext r0, r12 + BL Undefined_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : PrefetchAbortHandler +* Description : This function called when Prefetch Abort + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +PrefetchHandler: + SUB lr, lr, #4 /* Update the link register. */ + SaveContext r0, r12 + BL Prefetch_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : DataAbortHandler +* Description : This function is called when Data Abort + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +AbortHandler: + SUB lr, lr, #8 /* Update the link register. */ + SaveContext r0, r12 + BL Abort_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : FIQHandler +* Description : This function is called when FIQ + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +FIQHandler: + SUB lr, lr, #4 /* Update the link register. */ + SaveContext r0, r7 + BL FIQ_Handler + RestoreContext r0, r7 + + .end diff --git a/uc_str912/prj_template91x/src/vectors.c b/uc_str912/prj_template91x/src/vectors.c new file mode 100644 index 0000000..4022391 --- /dev/null +++ b/uc_str912/prj_template91x/src/vectors.c @@ -0,0 +1,462 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +#include "vectors.h" + +/******************************************************************************* +* Function Name : Undefined_Handler +* Description : This function Undefined instruction exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Undefined_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SWI_Handler +* Description : This function handles SW exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SWI_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles preftetch abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Prefetch_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : Abort_Handler +* Description : This function handles data abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Abort_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : FIQ_Handler +* Description : This function handles FIQ exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FIQ_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : WDG_IRQHandler +* Description : This function handles the WDG interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SW_IRQHandler +* Description : This function handles the SW interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SW_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ARMRX_IRQHandler +* Description : This function handles the ARMRX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMRX_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ARMTX_IRQHandler +* Description : This function handles the ARMTX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMTX_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM0_IRQHandler +* Description : This function handles the TIM0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM1_IRQHandler +* Description : This function handles the TIM1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM2_IRQHandler +* Description : This function handles the TIM2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM3_IRQHandler +* Description : This function handles the TIM3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM3_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBHP_IRQHandler +* Description : This function handles the USBHP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBHP_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBLP_IRQHandler +* Description : This function handles the USBLP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBLP_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SCU_IRQHandler +* Description : This function handles the SCU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ENET_IRQHandler +* Description : This function handles the ENET interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ENET_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : DMA_IRQHandler +* Description : This function handles the DMA interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : CAN_IRQHandler +* Description : This function handles the CAN interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : MC_IRQHandler +* Description : This function handles the MC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ADC_IRQHandler +* Description : This function handles the ADC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART0_IRQHandler +* Description : This function handles the UART0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART1_IRQHandler +* Description : This function handles the UART1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART2_IRQHandler +* Description : This function handles the UART2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : I2C0_IRQHandler +* Description : This function handles the I2C0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : I2C1_IRQHandler +* Description : This function handles the I2C1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SSP0_IRQHandler +* Description : This function handles the SSP0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SSP1_IRQHandler +* Description : This function handles the SSP1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : LVD_IRQHandler +* Description : This function handles the LVD interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LVD_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles the RTC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : WIU_IRQHandler +* Description : This function handles the WIU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WIU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT0_IRQHandler +* Description : This function handles the EXTIT0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT1_IRQHandler +* Description : This function handles the EXTIT1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT2_IRQHandler +* Description : This function handles the EXTIT2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT3_IRQHandler +* Description : This function handles the EXTIT3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT3_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBWU_IRQHandler +* Description : This function handles the USBWU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBWU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : PFQBC_IRQHandler +* Description : This function handles the PFQBC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PFQBC_IRQHandler(void) +{ + while(1); +} diff --git a/uc_str912/prj_template91x/str91x_lib/Makefile b/uc_str912/prj_template91x/str91x_lib/Makefile new file mode 100644 index 0000000..e65be4d --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/Makefile @@ -0,0 +1,38 @@ +# efsl library Makefile for STR910 by Giacomo Fazio and Antonio Nasca +# (based on efsl library makefile for AT91SAM7S by Martin Thomas) + + +MCU = arm9e +#THUMB = -mthumb -mthumb-interwork +THUMB = + +LIBNAME = libSTR91x_lib.a + +COPT= -mcpu=$(MCU) $(THUMB) -gdwarf-2 -Wall -Os +INCLUDEDIRS=-Iinclude +CFLAGS=$(COPT) $(INCLUDEDIRS) +# gcc4 unused code-removal: +CFLAGS += -ffunction-sections -fdata-sections + +CC=arm-elf-gcc +AR=arm-elf-ar +OBJCOPY=arm-elf-objcopy + +OBJ=src/91x_adc.o src/91x_ahbapb.o src/91x_can.o src/91x_dma.o +OBJ+=src/91x_emi.o src/91x_fmi.o src/91x_gpio.o src/91x_i2c.o src/91x_lib.o src/91x_mc.o +OBJ+=src/91x_rtc.o src/91x_scu.o src/91x_ssp.o src/91x_tim.o +OBJ+=src/91x_wdg.o src/91x_wiu.o src/91x_uart.o src/91x_vic.o + + +all: lib + +libandclean: lib srcclean + +lib: $(OBJ) + $(AR) rcs $(LIBNAME) $(OBJ) + +srcclean : + rm -f $(OBJ) + +clean : + rm -f $(OBJ) $(LIBNAME) diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_adc.h b/uc_str912/prj_template91x/str91x_lib/include/91x_adc.h new file mode 100644 index 0000000..25a396d --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_adc.h @@ -0,0 +1,124 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_adc.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* ADC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef __91x_ADC_H +#define __91x_ADC_H + +/* Includes ------------------------------------------------------------------*/ + +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* ADC Init structure define */ +typedef struct +{ + u16 ADC_WDG_High_Threshold; + u16 ADC_WDG_Low_Threshold; + u16 ADC_Channel_0_Mode; + u16 ADC_Channel_1_Mode; + u16 ADC_Channel_2_Mode; + u16 ADC_Channel_3_Mode; + u16 ADC_Channel_4_Mode; + u16 ADC_Channel_5_Mode; + u16 ADC_Channel_6_Mode; + u16 ADC_Channel_7_Mode; + u16 ADC_Select_Channel; + FunctionalState ADC_Scan_Mode; + u16 ADC_Conversion_Mode; +}ADC_InitTypeDef; + +/* ADC watchdog thresholds */ +typedef enum +{ + ADC_HighThreshold, + ADC_LowThreshold +}ADC_ThresholdType; + +/* Exported constants --------------------------------------------------------*/ + +/* ADC channels */ +#define ADC_Channel_0 0x00 /* Channel 0 */ +#define ADC_Channel_1 0x01 /* Channel 1 */ +#define ADC_Channel_2 0x02 /* Channel 2 */ +#define ADC_Channel_3 0x03 /* Channel 3 */ +#define ADC_Channel_4 0x04 /* Channel 4 */ +#define ADC_Channel_5 0x05 /* Channel 5 */ +#define ADC_Channel_6 0x06 /* Channel 6 */ +#define ADC_Channel_7 0x07 /* Channel 7 */ + +/* ADC modes */ +#define ADC_Continuous_Mode 0x0010 /* Continuous mode conversion */ +#define ADC_Single_Mode 0xFFEF /* Single mode conversion */ + +/* ADC Flags */ +#define ADC_FLAG_ECV 0x002F /* End of Conversion Flag */ +#define ADC_FLAG_AWD 0x002E /* Analog WatchDog Flag */ + +#define ADC_FLAG_OV_CH_0 0x00CF /* Overflow Flag for channel 0 */ +#define ADC_FLAG_OV_CH_1 0x00EF /* Overflow Flag for channel 1 */ +#define ADC_FLAG_OV_CH_2 0x010F /* Overflow Flag for channel 2 */ +#define ADC_FLAG_OV_CH_3 0x012F /* Overflow Flag for channel 3 */ +#define ADC_FLAG_OV_CH_4 0x014F /* Overflow Flag for channel 4 */ +#define ADC_FLAG_OV_CH_5 0x016F /* Overflow Flag for channel 5 */ +#define ADC_FLAG_OV_CH_6 0x018F /* Overflow Flag for channel 6 */ +#define ADC_FLAG_OV_CH_7 0x01AF /* Overflow Flag for channel 7 */ + +/* ADC conversion modes */ +#define ADC_NoThreshold_Conversion 0x0003 /* Conversion w/o thresholds */ +#define ADC_LowThreshold_Conversion 0x0002 /* Low threshold conversion */ +#define ADC_HighThreshold_Conversion 0x0001 /* High threshold conversion */ +#define ADC_No_Conversion 0x0000 /* No ADC conversion */ + +/* ADC interrupts */ +#define ADC_IT_ECV 0x0400 /* End of Conversion Interrupt */ +#define ADC_IT_AWD 0x0200 /* Analog Watchdog Interrupt */ + +/* ADC Start/Stop conversion */ +#define ADC_Conversion_Start 0x0001 /* ADC start conversion */ +#define ADC_Conversion_Stop 0xFFFE /* ADC stop conversion */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void ADC_DeInit(void); +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_PrescalerConfig(u8 ADC_Prescaler); +u8 ADC_GetPrescalerValue(void); +FlagStatus ADC_GetFlagStatus(u16 ADC_Flag); +void ADC_ClearFlag(u16 ADC_Flag); +u16 ADC_GetConversionValue(u16 ADC_Channel); +FlagStatus ADC_GetAnalogWatchdogResult(u16 ADC_Channel); +void ADC_ClearAnalogWatchdogResult(u16 ADC_Channel); +u16 ADC_GetWatchdogThreshold(ADC_ThresholdType ADC_Threshold); +void ADC_ITConfig(u16 ADC_IT, FunctionalState ADC_NewState); +void ADC_StandbyModeCmd(FunctionalState ADC_NewState); +void ADC_Cmd(FunctionalState ADC_NewState); +void ADC_ConversionCmd(u16 ADC_Conversion); + +#endif /* __91x_ADC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_ahbapb.h b/uc_str912/prj_template91x/str91x_lib/include/91x_ahbapb.h new file mode 100644 index 0000000..1828d48 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_ahbapb.h @@ -0,0 +1,60 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* AHBAPB software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _91x_AHBAPB_H +#define _91x_AHBAPB_H + +#include "91x_map.h" + +#define AHBAPB_Split_Enable 0x01000000 +#define AHBAPB_Split_Disable 0xFEFFFFFF +#define AHBAPB_Error_Enable 0x0000100 +#define AHBAPB_Error_Disable 0xFFFFEFF + +/*FLAG*/ +#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/ +#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */ +#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */ +#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/ + +/* Includes ------------------------------------------------------------------*/ + + +/* AHBAPB Init structure definition */ +typedef struct +{ + u32 AHBAPB_SetTimeOut; + u32 AHBAPB_Error; + u32 AHBAPB_Split; + u8 AHBAPB_SplitCounter; +}AHBAPB_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx); +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct); +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct); +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx); + + +#endif /* _91x_AHBAPB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_can.h b/uc_str912/prj_template91x/str91x_lib/include/91x_can.h new file mode 100644 index 0000000..b3d0653 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_can.h @@ -0,0 +1,165 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_can.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* CAN bus software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_CAN_H +#define __91x_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ + +/* CAN Init structure define */ +typedef struct +{ + u8 CAN_ConfigParameters; + u32 CAN_Bitrate; +}CAN_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* Standard bitrates available*/ +enum +{ + CAN_BITRATE_100K, + CAN_BITRATE_125K, + CAN_BITRATE_250K, + CAN_BITRATE_500K, + CAN_BITRATE_1M +}; + +/* Control register*/ +#define CAN_CR_TEST 0x0080 +#define CAN_CR_CCE 0x0040 +#define CAN_CR_DAR 0x0020 +#define CAN_CR_EIE 0x0008 +#define CAN_CR_SIE 0x0004 +#define CAN_CR_IE 0x0002 +#define CAN_CR_INIT 0x0001 + +/* Status register */ +#define CAN_SR_BOFF 0x0080 +#define CAN_SR_EWARN 0x0040 +#define CAN_SR_EPASS 0x0020 +#define CAN_SR_RXOK 0x0010 +#define CAN_SR_TXOK 0x0008 +#define CAN_SR_LEC 0x0007 + +/* Test register*/ +#define CAN_TESTR_RX 0x0080 +#define CAN_TESTR_TX1 0x0040 +#define CAN_TESTR_TX0 0x0020 +#define CAN_TESTR_LBACK 0x0010 +#define CAN_TESTR_SILENT 0x0008 +#define CAN_TESTR_BASIC 0x0004 + +/* IFn / Command Request register*/ +#define CAN_CRR_BUSY 0x8000 + +/* IFn / Command Mask register*/ +#define CAN_CMR_WRRD 0x0080 +#define CAN_CMR_MASK 0x0040 +#define CAN_CMR_ARB 0x0020 +#define CAN_CMR_CONTROL 0x0010 +#define CAN_CMR_CLRINTPND 0x0008 +#define CAN_CMR_TXRQSTNEWDAT 0x0004 +#define CAN_CMR_DATAA 0x0002 +#define CAN_CMR_DATAB 0x0001 + +/* IFn / Mask 2 register*/ +#define CAN_M2R_MXTD 0x8000 +#define CAN_M2R_MDIR 0x4000 + +/* IFn / Arbitration 2 register*/ +#define CAN_A2R_MSGVAL 0x8000 +#define CAN_A2R_XTD 0x4000 +#define CAN_A2R_DIR 0x2000 + +/* IFn / Message Control register*/ +#define CAN_MCR_NEWDAT 0x8000 +#define CAN_MCR_MSGLST 0x4000 +#define CAN_MCR_INTPND 0x2000 +#define CAN_MCR_UMASK 0x1000 +#define CAN_MCR_TXIE 0x0800 +#define CAN_MCR_RXIE 0x0400 +#define CAN_MCR_RMTEN 0x0200 +#define CAN_MCR_TXRQST 0x0100 +#define CAN_MCR_EOB 0x0080 + + +/* Wake-up modes*/ +enum +{ + CAN_WAKEUP_ON_EXT, + CAN_WAKEUP_ON_CAN +}; + + +/* CAN message structure*/ +typedef struct +{ + u32 IdType; + u32 Id; + u8 Dlc; + u8 Data[8]; +} canmsg; + +/* Message ID types*/ +enum +{ + CAN_STD_ID, + CAN_EXT_ID +}; + +/* Message ID limits*/ + +#define CAN_LAST_STD_ID ((1<<11) - 1) +#define CAN_LAST_EXT_ID ((1L<<29) - 1) + +/* Exported functions ------------------------------------------------------- */ + +void CAN_Init (CAN_InitTypeDef *CAN_InitStruct); +void CAN_DeInit (void); +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct); +void CAN_SetBitrate(u32 bitrate); +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj); +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType); +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); +void CAN_InvalidateAllMsgObj(void); +ErrorStatus CAN_ReleaseMessage(u32 msgobj); +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); +ErrorStatus CAN_WaitEndOfTx(void); +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg); +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg); +void CAN_EnterTestMode(u8 TestMask); +void CAN_EnterInitMode(u8 InitMask); +void CAN_LeaveInitMode(void); +void CAN_LeaveTestMode(void); +void CAN_ReleaseTxMessage(u32 msgobj); +void CAN_ReleaseRxMessage(u32 msgobj); +u32 CAN_IsMessageWaiting(u32 msgobj); +u32 CAN_IsTransmitRequested(u32 msgobj); +u32 CAN_IsInterruptPending(u32 msgobj); +u32 CAN_IsObjectValid(u32 msgobj); + +#endif /* __91x_CAN_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_conf.h b/uc_str912/prj_template91x/str91x_lib/include/91x_conf.h new file mode 100644 index 0000000..a39d57e --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_conf.h @@ -0,0 +1,117 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_conf.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Library configuration. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +#ifndef __91x_CONF_H +#define __91x_CONF_H + +/* To work in buffered mode just decomment the following line */ + +//#define LIBUFF + +/* Comment the line below to put the library in release mode */ +//#define LIBDEBUG + +#define inline static __inline + +/************************* AHBAPB *************************/ +#define _AHBAPB +#define _AHBAPB0 +#define _AHBAPB1 +/************************* VIC *************************/ +#define _VIC +#define _VIC0 +#define _VIC1 +/************************* DMA *************************/ +#define _DMA +#define _DMA_Channel0 +#define _DMA_Channel1 +#define _DMA_Channel2 +#define _DMA_Channel3 +#define _DMA_Channel4 +#define _DMA_Channel5 +#define _DMA_Channel6 +#define _DMA_Channel7 + +/************************* EMI *************************/ +#define _EMI +#define _EMI_Bank0 +#define _EMI_Bank1 +#define _EMI_Bank2 +#define _EMI_Bank3 +/************************* FMI *************************/ +#define _FMI +/************************* WIU *************************/ +#define _WIU +/************************* TIM *************************/ +#define _TIM +#define _TIM0 +#define _TIM1 +#define _TIM2 +#define _TIM3 +/************************* GPIO ************************/ +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 +#define _GPIO3 +#define _GPIO4 +#define _GPIO5 +#define _GPIO6 +#define _GPIO7 +#define _GPIO8 +#define _GPIO9 +/************************* RTC *************************/ +#define _RTC +/************************* SCU *************************/ +#define _SCU +/************************* MC **************************/ +#define _MC +/************************* UART ************************/ +#define _UART +#define _UART0 +#define _UART1 +#define _UART2 +/************************* SSP *************************/ +#define _SSP +#define _SSP0 +#define _SSP1 +/************************* CAN *************************/ +#define _CAN +/************************* ADC *************************/ +#define _ADC +/************************* WDG *************************/ +#define _WDG +/************************* I2C *************************/ +#define _I2C +#define _I2C0 +#define _I2C1 +/************************ ENET *************************/ +#define _ENET + +/*---------------------------- _Main_Crystal frequency value (KHz)------------*/ + +//#ifndef _Main_Crystal +//#define _Main_Crystal 25000 +//#endif +/*------------------------------------------------------------------------------*/ + + +#endif /* __91x_CONF_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_dma.h b/uc_str912/prj_template91x/str91x_lib/include/91x_dma.h new file mode 100644 index 0000000..6a383aa --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_dma.h @@ -0,0 +1,247 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : template.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : provide a short description of the source file indicating +* its purpose. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_DMA_H +#define __91x_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include"91x_map.h" + + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/ + + u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/ + + u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */ + + u32 DMA_Channel_DesWidth; /* Destination transfer width. */ + + u32 DMA_Channel_SrcWidth; /* Source transfer width. */ + + u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/ + + u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */ + + u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/ + + u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */ + + u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */ + + u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */ + +} DMA_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + /* Interrupts masks */ + +#define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */ +#define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/ +#define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/ + + /* Sources Request (used as masks) */ + +#define DMA_USB_RX_Mask 0x0001 +#define DMA_USB_TX_Mask 0x0002 +#define DMA_TIM0_Mask 0x0004 +#define DMA_TIM1_Mask 0x0008 +#define DMA_UART0_RX_Mask 0x0010 +#define DMA_UART0_TX_Mask 0x0020 +#define DMA_UART1_RX_Mask 0x0040 +#define DMA_UART1_TX_Mask 0x0080 +#define DMA_External_Req0_Mask 0x0100 +#define DMA_External_Req1_Mask 0x0200 +#define DMA_I2C0_Mask 0x0400 +#define DMA_I2C1_Mask 0x0800 +#define DMA_SSP0_RX_Mask 0x1000 +#define DMA_SSP0_TX_Mask 0x2000 +#define DMA_SSP1_RX_Mask 0x4000 +#define DMA_SSP1_TX_Mask 0x8000 + + +/* Previleged Mode and user mode */ + +#define DMA_PrevilegedMode 0x10000000 +#define DMA_UserMode 0xEFFFFFFF + + +/* Error and Terminal Count interrupts Status, after and before"raw" masking */ +#define DMA_IS 0x01 +#define DMA_TCS 0x02 +#define DMA_ES 0x03 +#define DMA_TCRS 0x04 +#define DMA_ERS 0x05 + + +/* interrupt clear: Terminal Count flag Clear and Error flag clear*/ + +#define DMA_TCC 0x01 +#define DMA_EC 0x02 + +/* channel index "0...7"*/ + +#define Channel0 0 +#define Channel1 1 +#define Channel2 2 +#define Channel3 3 +#define Channel4 4 +#define Channel5 5 +#define Channel6 6 +#define Channel7 7 + + + +/* Destination request selection: selects the DMA Destination request peripheral */ + +#define DMA_DES_USB_RX 0x00 +#define DMA_DES_USB_TX 0x40 +#define DMA_DES_TIM1 0x80 +#define DMA_DES_TIM2 0xC0 +#define DMA_DES_UART0_RX 0x100 +#define DMA_DES_UART0_TX 0x140 +#define DMA_DES_UART1_RX 0x180 +#define DMA_DES_UART1_TX 0x1C0 +#define DMA_DES_External_Req0 0x200 +#define DMA_DES_External_Req1 0x240 +#define DMA_DES_I2C0 0x280 +#define DMA_DES_I2C1 0x2C0 +#define DMA_DES_SSP0_RX 0x300 +#define DMA_DES_SSP0_TX 0x340 +#define DMA_DES_SSP1_RX 0x380 +#define DMA_DES_SSP1_TX 0x3C0 + + + + +/* Source request selection: selects the DMA Source request peripheral */ + +#define DMA_SRC_USB_RX 0x00 +#define DMA_SRC_USB_TX 0x02 +#define DMA_SRC_TIM1 0x04 +#define DMA_SRC_TIM2 0x06 +#define DMA_SRC_UART0_RX 0x08 +#define DMA_SRC_UART0_TX 0x0A +#define DMA_SRC_UART1_RX 0x0C +#define DMA_SRC_UART1_TX 0x0E +#define DMA_SRC_External_Req0 0x10 +#define DMA_SRC_External_Req1 0x12 +#define DMA_SRC_I2C0 0x14 +#define DMA_SRC_I2C1 0x16 +#define DMA_SRC_SSP0_RX 0x18 +#define DMA_SRC_SSP0_TX 0x1A +#define DMA_SRC_SSP1_RX 0x1C +#define DMA_SRC_SSP1_TX 0x1E + + + + + +#define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */ +#define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */ +#define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */ +#define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */ +#define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */ +#define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */ +#define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */ +#define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */ + + + + +#define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */ +#define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */ +#define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */ +#define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */ +#define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */ +#define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */ +#define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */ +#define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */ + + + + +#define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */ +#define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */ +#define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */ +#define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */ +#define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */ +#define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */ +#define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */ +#define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */ + + + + + +#define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */ +#define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */ +#define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */ + + + + +#define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */ +#define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */ +#define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */ + + + + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void DMA_DeInit(void); +void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(FunctionalState NewState); +void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); +FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ); +ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq); +void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr); +void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState); +FlagStatus DMA_GetSReq(u16 DMA_SrcReq); +FlagStatus DMA_GetLSReq(u16 DMA_SrcReq); +FlagStatus DMA_GetBReq(u16 DMA_SrcReq); +FlagStatus DMA_GetLBReq(u16 DMA_SrcReq); +FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx); +void DMA_SetSReq(u16 DMA_SrcReq); +void DMA_SetLSReq(u16 DMA_SrcReq); +void DMA_SetBReq(u16 DMA_SrcReq); +void DMA_SetLBReq(u16 DMA_SrcReq); +void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); +void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode); +void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); +void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); + +#endif /* __91x_DMA_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_emi.h b/uc_str912/prj_template91x/str91x_lib/include/91x_emi.h new file mode 100644 index 0000000..4633020 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_emi.h @@ -0,0 +1,83 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_emi.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* EMI software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_EMI_H +#define __91x_EMI_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ + typedef struct + { + u32 EMI_Bank_IDCY; + + u32 EMI_Bank_WSTRD; + + u32 EMI_Bank_WSTWR; + + u32 EMI_Bank_WSTROEN; + + u32 EMI_Bank_WSTWEN; + + u32 EMI_Bank_MemWidth ; + + u32 EMI_Bank_WriteProtection; + + u32 EMI_PageModeRead_TransferLength; + + u32 EMI_PageModeRead_Selection; + + } EMI_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + + +/* page transfer length for page mode read */ +#define EMI_4Data 0x00000000 /*4 transfers burst*/ +#define EMI_8Data 0x00000400 /*8 transfers burst*/ + + +/*Select or deselect the page mode read*/ +#define EMI_NormalMode 0x00000000 /*Normal Mode*/ +#define EMI_PageModeRead 0x00000100 /*Page Mode Read*/ + + +/*memory width*/ +#define EMI_Width_Byte 0x00000000 /*8 bits width*/ +#define EMI_Width_HalfWord 0x00000010 /*16 bits width*/ + +/*Write protection feature */ +#define EMI_Bank_NonWriteProtect 0x00000000 /*No write protection*/ +#define EMI_Bank_WriteProtect 0x00000008 /*bank is write protected*/ + + +/* Exported macro ------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ + +void EMI_DeInit(void); +void EMI_Init( EMI_Bank_TypeDef* EMI_Bankx, EMI_InitTypeDef* EMI_InitStruct); +void EMI_StructInit(EMI_InitTypeDef* EMI_InitStruct); + +#endif /* __EMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_fmi.h b/uc_str912/prj_template91x/str91x_lib/include/91x_fmi.h new file mode 100644 index 0000000..06e8115 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_fmi.h @@ -0,0 +1,184 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* FMI software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef __91x_FMI_H +#define __91x_FMI_H + +/* ========================================================================== */ +/* When bank 1 is remapped at address 0x0, decomment the following line */ +/* ========================================================================== */ + +//#define Remap_Bank_1 + + +/* Includes ------------------------------------------------------------------*/ + +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* FMI banks */ + +#ifdef Remap_Bank_1 + +#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */ + +#else /* Remap Bank 0 */ + +#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */ + +#endif + +/* FMI sectors */ + +#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */ +#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */ +#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */ +#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */ +#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */ +#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */ +#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */ +#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */ + +#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */ +#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */ +#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */ +#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */ + +/* FMI Flags */ + +#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */ +#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */ +#define FMI_FLAG_PS 0x10 /* Program Status Flag */ +#define FMI_FLAG_ES 0x20 /* Erase Status Flag */ +#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */ +#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */ + +/* FMI read wait states */ + +#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */ +#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */ +#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */ + +/* FMI write wait states */ + +#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */ +#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */ + +/* FMI power down configuration */ + +#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */ +#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */ + +/* FMI low voltage detector */ + +#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */ +#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */ + +/* FMI frequency range */ + +#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */ +#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */ + /* Above 66 MHz*/ +/* FMI OTP word addresses */ + +#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */ +#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */ +#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */ +#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */ +#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */ +#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */ +#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */ +#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */ + +/* FMI OTP halfword addresses */ + +#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */ +#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */ +#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */ +#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */ +#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */ +#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */ +#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */ +#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */ +#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */ +#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */ +#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */ +#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */ +#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */ +#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */ +#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */ +#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */ + +/* FMI sectors Masks */ + +#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */ +#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */ +#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */ +#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */ +#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */ +#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */ +#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */ +#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */ + +#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */ +#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */ +#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */ +#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */ + +/* Timeout error */ + +#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */ +#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress); +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange); +void FMI_EraseSector(vu32 FMI_Sector); +void FMI_EraseBank(vu32 FMI_Bank); +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data); +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData); +u32 FMI_ReadWord(u32 FMI_Address); +u32 FMI_ReadOTPData(u8 FMI_OTPAddress); +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank); +u16 FMI_GetReadWaitStateValue(void); +u16 FMI_GetWriteWaitStateValue(void); +void FMI_SuspendEnable(vu32 FMI_Bank); +void FMI_ResumeEnable(vu32 FMI_Bank); +void FMI_ClearFlag(vu32 FMI_Bank); +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState); +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection); +u8 FMI_WaitForLastOperation(vu32 FMI_Bank); + +#endif /* __91x_FMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_gpio.h b/uc_str912/prj_template91x/str91x_lib/include/91x_gpio.h new file mode 100644 index 0000000..f4e5658 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_gpio.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef _91x_GPIO_H +#define _91x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* GPIO Init structure definition */ +typedef struct +{ + u8 GPIO_Pin; + u8 GPIO_Direction; + u8 GPIO_Type; + u8 GPIO_IPConnected; + u16 GPIO_Alternate; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + + +/* Exported constants --------------------------------------------------------*/ +#define GPIO_Pin_None 0x00 +#define GPIO_Pin_0 0x01 +#define GPIO_Pin_1 0x02 +#define GPIO_Pin_2 0x04 +#define GPIO_Pin_3 0x08 +#define GPIO_Pin_4 0x10 +#define GPIO_Pin_5 0x20 +#define GPIO_Pin_6 0x40 +#define GPIO_Pin_7 0x80 +#define GPIO_Pin_All 0xFF + +#define GPIO_PinInput 0x00 +#define GPIO_PinOutput 0x01 + +#define GPIO_Type_PushPull 0x00 +#define GPIO_Type_OpenCollector 0x01 + +#define GPIO_IPConnected_Disable 0x00 +#define GPIO_IPConnected_Enable 0x01 + +#define GPIO_InputAlt1 0x00 +#define GPIO_OutputAlt1 0x01 +#define GPIO_OutputAlt2 0x02 +#define GPIO_OutputAlt3 0x03 + +#define GPIO_ANAChannel0 0x01 +#define GPIO_ANAChannel1 0x02 +#define GPIO_ANAChannel2 0x04 +#define GPIO_ANAChannel3 0x08 +#define GPIO_ANAChannel4 0x10 +#define GPIO_ANAChannel5 0x20 +#define GPIO_ANAChannel6 0x40 +#define GPIO_ANAChannel7 0x80 +#define GPIO_ANAChannelALL 0xFF + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin); +u8 GPIO_Read(GPIO_TypeDef* GPIOx); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal); +void GPIO_EMIConfig(FunctionalState NewState); +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState); + +#endif /* _91x_GPIO_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_i2c.h b/uc_str912/prj_template91x/str91x_lib/include/91x_i2c.h new file mode 100644 index 0000000..f4d0c66 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_i2c.h @@ -0,0 +1,112 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_i2c.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* I2C software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_I2C_H +#define __91x_I2C_H + +/* Includes ----------------------------------------------------------------- */ +#include "91x_map.h" + +/* Exported types ----------------------------------------------------------- */ +/* I2C Init structure definition */ +typedef struct +{ + u32 I2C_CLKSpeed; + u16 I2C_OwnAddress; + u8 I2C_GeneralCall; + u8 I2C_Ack; +}I2C_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +#define I2C_GeneralCall_Enable 0x10 +#define I2C_GeneralCall_Disable 0xEF +/* Acknowledgement */ +#define I2C_Ack_Enable 0x04 +#define I2C_Ack_Disable 0xFB + +/* I2C Flags */ +#define I2C_FLAG_SB 0x0001 +#define I2C_FLAG_M_SL 0x0002 +#define I2C_FLAG_ADSL 0x0004 +#define I2C_FLAG_BTF 0x0008 +#define I2C_FLAG_BUSY 0x0010 +#define I2C_FLAG_TRA 0x0020 +#define I2C_FLAG_ADD10 0x0040 +#define I2C_FLAG_EVF 0x0080 +#define I2C_FLAG_GCAL 0x0100 +#define I2C_FLAG_BERR 0x0200 +#define I2C_FLAG_ARLO 0x0400 +#define I2C_FLAG_STOPF 0x0800 +#define I2C_FLAG_AF 0x1000 +#define I2C_FLAG_ENDAD 0x2000 +#define I2C_FLAG_ACK 0x4000 + +/* I2C Events */ +#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_ADSL) +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF ) +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB ) +#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD ) +#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF ) +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA ) +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 ) +#define I2C_EVENT_SLAVE_STOP_DETECTED I2C_FLAG_STOPF +#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF) + +#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR +#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO +#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL) + +/* Master/Receiver Mode */ +#define I2C_MODE_TRANSMITTER 0x00 +#define I2C_MODE_RECEIVER 0x01 + +/* I2C Registers offset */ +#define I2C_CR 0x00 +#define I2C_SR1 0x04 +#define I2C_SR2 0x08 +#define I2C_CCR 0x0C +#define I2C_OAR1 0x10 +#define I2C_OAR2 0x14 +#define I2C_DR 0x18 +#define I2C_ECCR 0x1C + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateStart(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 Direction); +u8 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u16 I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u16 I2C_FLAG, ...); +void I2C_SendData(I2C_TypeDef* I2Cx, u8 bData); +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx); +u16 I2C_GetLastEvent(I2C_TypeDef* I2Cx); +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,u16 I2C_Event); + +#endif /* __91x_I2C_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_it.h b/uc_str912/prj_template91x/str91x_lib/include/91x_it.h new file mode 100644 index 0000000..a8e35fc --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_it.h @@ -0,0 +1,73 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_it.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains the headers of the interrupt +* handlers'routines +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef _91x_IT_H +#define _91x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_lib.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void Undefined_Handler (void); +void SWI_Handler (void); +void Prefetch_Handler (void); +void Abort_Handler (void); +void FIQ_Handler (void); +void WDG_IRQHandler (void); +void SW_IRQHandler (void); +void ARMRX_IRQHandler (void); +void ARMTX_IRQHandler (void); +void TIM0_IRQHandler (void); +void TIM1_IRQHandler (void); +void TIM2_IRQHandler (void); +void TIM3_IRQHandler (void); +void USBHP_IRQHandler (void); +void USBLP_IRQHandler (void); +void SCU_IRQHandler (void); +void ENET_IRQHandler (void); +void DMA_IRQHandler (void); +void CAN_IRQHandler (void); +void MC_IRQHandler (void); +void ADC_IRQHandler (void); +void UART0_IRQHandler (void); +void UART1_IRQHandler (void); +void UART2_IRQHandler (void); +void I2C0_IRQHandler (void); +void I2C1_IRQHandler (void); +void SSP0_IRQHandler (void); +void SSP1_IRQHandler (void); +void LVD_IRQHandler (void); +void RTC_IRQHandler (void); +void WIU_IRQHandler (void); +void EXTIT0_IRQHandler (void); +void EXTIT1_IRQHandler (void); +void EXTIT2_IRQHandler (void); +void EXTIT3_IRQHandler (void); +void USBWU_IRQHandler (void); +void PFQBC_IRQHandler (void); + +#endif /* _91x_IT_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_lib.h b/uc_str912/prj_template91x/str91x_lib/include/91x_lib.h new file mode 100644 index 0000000..3df7ced --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_lib.h @@ -0,0 +1,113 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Used to include the peripherals header file in the +* user application. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __91x_LIB_H +#define __91x_LIB_H + +#include "91x_map.h" +#include "91x_conf.h" + +#ifdef _AHBAPB + #include "91x_ahbapb.h" +#endif /* _AHBAPB */ + +#ifdef _EMI + #include "91x_emi.h" +#endif /* _EMI */ + +#ifdef _DMA + #include "91x_dma.h" +#endif /* _DMA */ + +#ifdef _FMI + #include "91x_fmi.h" +#endif /* _FMI */ + +#ifdef _VIC + #include "91x_vic.h" +#endif /* _VIC */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif /* _WIU */ + +#ifdef _TIM + #include "91x_tim.h" +#endif /* _TIM */ + +#ifdef _GPIO + #include "91x_gpio.h" +#endif /* _GPIO */ + +#ifdef _RTC + #include "91x_rtc.h" +#endif /* _RTC */ + +#ifdef _SCU + #include "91x_scu.h" +#endif /* _SCU */ + +#ifdef _UART + #include "91x_uart.h" +#endif /* _UART */ + +#ifdef _SSP + #include "91x_ssp.h" +#endif /* _SSP */ + +#ifdef _CAN + #include "91x_can.h" +#endif /* _CAN */ + +#ifdef _ADC + #include "91x_adc.h" +#endif /* _ADC */ + +#ifdef _WDG + #include "91x_wdg.h" +#endif /* _WDG */ + +#ifdef _I2C + #include "91x_i2c.h" +#endif /* _I2C */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif + +#ifdef _MC + #include "91x_mc.h" +#endif + +#ifdef _ENET +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + void libdebug( void ); + + +#endif /* __91x_LIB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_map.h b/uc_str912/prj_template91x/str91x_lib/include/91x_map.h new file mode 100644 index 0000000..5fe67cf --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_map.h @@ -0,0 +1,878 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_map.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Peripherals registers definition and memory mapping. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_MAP_H +#define __91x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_conf.h" +#include "91x_type.h" + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------------------ FMI -----------------------------------*/ + +typedef struct +{ + vu32 BBSR; /* Boot Bank Size Register */ + vu32 NBBSR; /* Non-Boot Bank Size Register */ + vu32 EMPTY1; + vu32 BBADR; /* Boot Bank Base Address Register */ + vu32 NBBADR; /* Non-Boot Bank Base Address Register */ + vu32 EMPTY2; + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */ +} FMI_TypeDef; + +/*---------------------- Analog to Digital Convertor ------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 CCR; /* Channel Configuration Register */ + vu16 EMPTY2; + vu16 HTR; /* Higher Threshold Register */ + vu16 EMPTY3; + vu16 LTR; /* Lower Threshold Register */ + vu16 EMPTY4; + vu16 CRR; /* Compare Result Register */ + vu16 EMPTY5; + vu16 DR0; /* Data Register for Channel 0 */ + vu16 EMPTY6; + vu16 DR1; /* Data Register for Channel 1 */ + vu16 EMPTY7; + vu16 DR2; /* Data Register for Channel 2 */ + vu16 EMPTY8; + vu16 DR3; /* Data Register for Channel 3 */ + vu16 EMPTY9; + vu16 DR4; /* Data Register for Channel 4 */ + vu16 EMPTY10; + vu16 DR5; /* Data Register for Channel 5 */ + vu16 EMPTY11; + vu16 DR6; /* Data Register for Channel 6 */ + vu16 EMPTY12; + vu16 DR7; /* Data Register for Channel 7 */ + vu16 EMPTY13; + vu16 PRS; /* Prescaler Value Register */ + vu16 EMPTY14; +} ADC_TypeDef; + +/*--------------------- AHB APB BRIDGE registers strcture --------------------*/ + +typedef struct +{ + vu32 BSR; /* Bridge Status Register */ + vu32 BCR; /* Bridge Configuration Register */ + vu32 PAER; /* Peripheral Address Error register */ +} AHBAPB_TypeDef; + +/*--------------- Controller Area Network Interface Register -----------------*/ + +typedef struct +{ + vu16 CRR; /* IFn Command request Register */ + vu16 EMPTY1; + vu16 CMR; /* IFn Command Mask Register */ + vu16 EMPTY2; + vu16 M1R; /* IFn Message Mask 1 Register */ + vu16 EMPTY3; + vu16 M2R; /* IFn Message Mask 2 Register */ + vu16 EMPTY4; + vu16 A1R; /* IFn Message Arbitration 1 Register */ + vu16 EMPTY5; + vu16 A2R; /* IFn Message Arbitration 2 Register */ + vu16 EMPTY6; + vu16 MCR; /* IFn Message Control Register */ + vu16 EMPTY7; + vu16 DA1R; /* IFn DATA A 1 Register */ + vu16 EMPTY8; + vu16 DA2R; /* IFn DATA A 2 Register */ + vu16 EMPTY9; + vu16 DB1R; /* IFn DATA B 1 Register */ + vu16 EMPTY10; + vu16 DB2R; /* IFn DATA B 2 Register */ + vu16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 SR; /* Status Register */ + vu16 EMPTY2; + vu16 ERR; /* Error counter Register */ + vu16 EMPTY3; + vu16 BTR; /* Bit Timing Register */ + vu16 EMPTY4; + vu16 IDR; /* Interrupt Identifier Register */ + vu16 EMPTY5; + vu16 TESTR; /* Test Register */ + vu16 EMPTY6; + vu16 BRPR; /* BRP Extension Register */ + vu16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + vu16 EMPTY8[16]; + vu16 TXR1R; /* Transmission request 1 Register */ + vu16 EMPTY9; + vu16 TXR2R; /* Transmission Request 2 Register */ + vu16 EMPTY10[13]; + vu16 ND1R; /* New Data 1 Register */ + vu16 EMPTY11; + vu16 ND2R; /* New Data 2 Register */ + vu16 EMPTY12[13]; + vu16 IP1R; /* Interrupt Pending 1 Register */ + vu16 EMPTY13; + vu16 IP2R; /* Interrupt Pending 2 Register */ + vu16 EMPTY14[13]; + vu16 MV1R; /* Message Valid 1 Register */ + vu16 EMPTY15; + vu16 MV2R; /* Message VAlid 2 Register */ + vu16 EMPTY16; +} CAN_TypeDef; + +/*----------------------- System Control Unit---------------------------------*/ + +typedef struct +{ + vu32 CLKCNTR; /* Clock Control Register */ + vu32 PLLCONF; /* PLL Configuration Register */ + vu32 SYSSTATUS; /* System Status Register */ + vu32 PWRMNG; /* Power Management Register */ + vu32 ITCMSK; /* Interrupt Mask Register */ + vu32 PCGRO; /* Peripheral Clock Gating Register 0 */ + vu32 PCGR1; /* Peripheral Clock Gating Register 1 */ + vu32 PRR0; /* Peripheral Reset Register 0 */ + vu32 PRR1; /* Peripheral Reset Register 1 */ + vu32 MGR0; /* Idle Mode Mask Gating Register 0 */ + vu32 MGR1; /* Idle Mode Mask Gating Register 1 */ + vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */ + vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */ + vu32 SCR0; /* System Configuration Register 0 */ + vu32 SCR1; /* System Configuration Register 1 */ + vu32 SCR2; /* System Configuration Register 2 */ + u32 EMPTY1; + vu32 GPIOOUT[8]; /* GPIO Output Registers */ + vu32 GPIOIN[8]; /* GPIO Input Registers */ + vu32 GPIOTYPE[10]; /* GPIO Type Registers */ + vu32 GPIOEMI; /* GPIO EMI Selector Register */ + vu32 WKUPSEL; /* Wake-Up Selection Register */ + u32 EMPTY2[2]; + vu32 GPIOANA; /* GPIO Analag mode Register */ +} SCU_TypeDef; + +/*------------------------- DMA Channelx Registers ---------------------------*/ + +typedef struct +{ + vu32 SRC; /* Channelx Source Address Register */ + vu32 DES; /* Channelx Destination Address Register */ + vu32 LLI; /* Channelx Lincked List Item Register */ + vu32 CC; /* Channelx Contol Register */ + vu32 CCNF; /* Channelx Configuration Register */ +} DMA_Channel_TypeDef; + +/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */ + +/*----------------------------- DMA Controller -------------------------------*/ + +typedef struct +{ + vu32 ISR; /* Interrupt Status Register */ + vu32 TCISR; /* Terminal Count Interrupt Status Register */ + vu32 TCICR; /* Terminal CountInterrupt Clear Register */ + vu32 EISR; /* Error Interrupt Status Register */ + vu32 EICR; /* Error Interrupt Clear Register */ + vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */ + vu32 ERISR; /* Raw Error Interrupt Status Register */ + vu32 ENCSR; /* Enabled Channel Status Register */ + vu32 SBRR; /* Software Burst Request Register */ + vu32 SSRR; /* Software Single Request Register */ + vu32 SLBRR; /* Software Last Burst Request Register */ + vu32 SLSRR; /* Software Last Single Request Register */ + vu32 CNFR; /* Configuration Register */ + vu32 SYNR; /* Syncronization Register */ +} DMA_TypeDef; + +/*--------------------------------- TIM Timer --------------------------------*/ + +typedef struct +{ + vu16 IC1R; /* Input Capture 1 Register */ + vu16 EMPTY1; + vu16 IC2R; /* Input Capture 2 Register */ + vu16 EMPTY2; + vu16 OC1R; /* Output Compare 1 Register */ + vu16 EMPTY3; + vu16 OC2R; /* Output Compare 2 Register */ + vu16 EMPTY4; + vu16 CNTR; /* Counter Register */ + vu16 EMPTY5; + vu16 CR1; /* Control Register 1 */ + vu16 EMPTY6; + vu16 CR2; /* Control Register 2 */ + vu16 EMPTY7; + vu16 SR; /* Status Register */ + vu16 EMPTY8; +} TIM_TypeDef; + +/*---------------------------- EMI Bankx Registers ---------------------------*/ + +typedef struct +{ + vu32 ICR; /* Bankx Idle Cycle Control Register */ + vu32 RCR; /* Bankx Read Wait State Control Register */ + vu32 WCR; /* Bankx Write Wait State Control Register */ + vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */ + vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */ + vu32 BCR; /* Bankx Control Register */ + } EMI_Bank_TypeDef; + +/*---------------------------- Ethernet Controller ---------------------------*/ + +/* MAC Registers */ +typedef struct +{ + vu32 MCR; /* ENET Control Register */ + vu32 MAH; /* ENET Address High Register */ + vu32 MAL; /* ENET Address Low Register */ + vu32 MCHA; /* Multicast Address High Register */ + vu32 MCLA; /* Multicast Address Low Register */ + vu32 MIIA; /* MII Address Register */ + vu32 MIID; /* MII Data Register */ + vu32 MCF; /* ENET Control Frame Register */ + vu32 VL1; /* VLAN1 Register */ + vu32 VL2; /* VLAN2 register */ + vu32 MTS; /* ENET Transmission Status Register */ + vu32 MRS; /* ENET Reception Status Register */ +} ENET_MAC_TypeDef; + +/* DMA Registers */ +typedef struct +{ + vu32 SCR; /* DMA Status and Control Register */ + vu32 IER; /* DMA Interrupt Sources Enable Register */ + vu32 ISR; /* DMA Interrupt Status Register */ + vu32 CCR; /* Clock Control Relation : HCLK, PCLK and + ENET_CLK phase relations */ + vu32 RXSTR; /* Rx DMA start Register */ + vu32 RXCR; /* Rx DMA Control Register */ + vu32 RXSAR; /* Rx DMA Base Address Register */ + vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */ + vu32 RXCAR; /* Rx DMA Current Address Register */ + vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */ + vu32 RXTOR; /* Rx DMA FIFO Time Out Register */ + vu32 RXSR; /* Rx DMA FIFO Status Register */ + vu32 TXSTR; /* Tx DMA start Register */ + vu32 TXCR; /* Tx DMA Control Register */ + vu32 TXSAR; /* Tx DMA Base Address Register */ + vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */ + vu32 TXCAR; /* Tx DMA Current Address Register */ + vu32 TXTCR; /* Tx DMA Current Transfer Count Register */ + vu32 TXTOR; /* Tx DMA FIFO Time Out Register */ + vu32 TXSR; /* Tx DMA FIFO Status Register */ +} ENET_DMA_TypeDef; + +/*------------------------------------- GPIO ---------------------------------*/ + +typedef struct +{ + vu8 DR[1021]; /* Data Register */ + vu32 DDR; /* Data Direction Register */ +} GPIO_TypeDef; + +/*-------------------------------- I2C interface -----------------------------*/ + +typedef struct +{ + vu8 CR; /* Control Register */ + vu8 EMPTY1[3]; + vu8 SR1; /* Status Register 1 */ + vu8 EMPTY2[3]; + vu8 SR2; /* Status Register 2 */ + vu8 EMPTY3[3]; + vu8 CCR; /* Clock Control Register */ + vu8 EMPTY4[3]; + vu8 OAR1; /* Own Address Register 1 */ + vu8 EMPTY5[3]; + vu8 OAR2; /* Own Address Register 2 */ + vu8 EMPTY6[3]; + vu8 DR; /* Data Register */ + vu8 EMPTY7[3]; + vu8 ECCR; /* Extended Clock Control Register */ + vu8 EMPTY8[3]; +} I2C_TypeDef; + +/*------------------------------------- VIC ----------------------------------*/ + +typedef struct +{ + vu32 ISR; /* IRQ Status Register */ + vu32 FSR; /* FIQ Status Register */ + vu32 RINTSR; /* Raw Interrupt Status Register */ + vu32 INTSR; /* Interrupt Select Register */ + vu32 INTER; /* Interrupt Enable Register */ + vu32 INTECR; /* Interrupt Enable Clear Register */ + vu32 SWINTR; /* Software Interrupt Register */ + vu32 SWINTCR; /* Software Interrupt clear Register */ + vu32 PER; /* Protection Enable Register */ + vu32 EMPTY1[3]; + vu32 VAR; /* Vector Address Register */ + vu32 DVAR; /* Default Vector Address Register */ + vu32 EMPTY2[50]; + vu32 VAiR[16]; /* Vector Address 0-15 Register */ + vu32 EMPTY3[48]; + vu32 VCiR[16]; /* Vector Control 0-15 Register */ +} VIC_TypeDef; + +/*-------------------------------- Motor Control -----------------------------*/ + +typedef struct +{ + vu16 TCPT; /* Tacho Capture Register */ + vu16 EMPTY1; + vu16 TCMP; /* Tacho Compare Register */ + vu16 EMPTY2; + vu16 IPR; /* Input Pending Register */ + vu16 EMPTY3; + vu16 TPRS; /* Tacho Prescaler Register */ + vu16 EMPTY4; + vu16 CPRS; /* PWM Counter Prescaler Register */ + vu16 EMPTY5; + vu16 REP; /* Repetition Counter Register */ + vu16 EMPTY6; + vu16 CMPW; /* Compare Phase W Preload Register */ + vu16 EMPTY7; + vu16 CMPV; /* Compare Phase V Preload Register */ + vu16 EMPTY8; + vu16 CMPU; /* Compare Phase U Preload Register */ + vu16 EMPTY9; + vu16 CMP0; /* Compare 0 Preload Register */ + vu16 EMPTY10; + vu16 PCR0; /* Peripheral Control Register 0 */ + vu16 EMPTY11; + vu16 PCR1; /* Peripheral Control Register 1 */ + vu16 EMPTY12; + vu16 PCR2; /* Peripheral Control Register 2 */ + vu16 EMPTY13; + vu16 PSR; /* Polarity Selection Register */ + vu16 EMPTY14; + vu16 OPR; /* Output Peripheral Register */ + vu16 EMPTY15; + vu16 IMR; /* Interrupt Mask Register */ + vu16 EMPTY16; + vu16 DTG; /* Dead Time Generator Register */ + vu16 EMPTY17; + vu16 ESC; /* Emergency Stop Clear Register */ + vu16 EMPTY18; +}MC_TypeDef; + +/*------------------------------------- RTC ----------------------------------*/ + +typedef struct +{ + vu32 TR; /* Time Register */ + vu32 DTR; /* Date Register */ + vu32 ATR; /* Alarm time Register */ + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 MILR; /* Millisec Register */ +}RTC_TypeDef; + +/*------------------------------------- SSP ----------------------------------*/ + +typedef struct +{ + vu16 CR0; /* Control Register 1 */ + vu16 EMPTY1; + vu16 CR1; /* Control Register 2 */ + vu16 EMPTY2; + vu16 DR; /* Data Register */ + vu16 EMPTY3; + vu16 SR; /* Status Register */ + vu16 EMPTY4; + vu16 PR; /* Clock Prescale Register */ + vu16 EMPTY5; + vu16 IMSCR; /* Interrupt Mask Set or Clear Register */ + vu16 EMPTY6; + vu16 RISR; /* Raw Interrupt Status Register */ + vu16 EMPTY7; + vu16 MISR; /* Masked Interrupt Status Register */ + vu16 EMPTY8; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY9; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY10; +}SSP_TypeDef; + +/*------------------------------------ UART ----------------------------------*/ + +typedef struct +{ + vu16 DR; /* Data Register */ + vu16 EMPTY1; + vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */ + vu16 EMPTY2[9]; + vu16 FR; /* Flag Register */ + vu16 EMPTY3[3]; + vu16 ILPR; /* IrDA Low-Power counter Register */ + vu16 EMPTY4; + vu16 IBRD; /* Integer Baud Rate Divisor Register */ + vu16 EMPTY5; + vu16 FBRD; /* Fractional Baud Rate Divisor Register */ + vu16 EMPTY6; + vu16 LCR; /* Line Control Register, High byte */ + vu16 EMPTY7; + vu16 CR; /* Control Register */ + vu16 EMPTY8; + vu16 IFLS; /* Interrupt FIFO Level Select Register */ + vu16 EMPTY9; + vu16 IMSC; /* Interrupt Mask Set/Clear Register */ + vu16 EMPTY10; + vu16 RIS; /* Raw Interrupt Status Register */ + vu16 EMPTY11; + vu16 MIS; /* Masked Interrupt Status Register */ + vu16 EMPTY12; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY13; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY14; +}UART_TypeDef; + +/*------------------------------- Wake-up System -----------------------------*/ + +typedef struct +{ + vu32 CTRL; /* Control Register */ + vu32 MR; /* Mask Register */ + vu32 TR; /* Trigger Register */ + vu32 PR; /* Pending Register */ + vu32 INTR; /* Software Interrupt Register */ +} WIU_TypeDef; + +/*------------------------------- WatchDog Timer -----------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 PR; /* Presclar Register */ + vu16 EMPTY2; + vu16 VR; /* Pre-load Value Register */ + vu16 EMPTY3; + vu16 CNT; /* Counter Register */ + vu16 EMPTY4; + vu16 SR; /* Status Register */ + vu16 EMPTY5; + vu16 MR; /* Mask Register */ + vu16 EMPTY6; + vu16 KR; /* Key Register */ + vu16 EMPTY7; +} WDG_TypeDef; + +/******************************************************************************* +* Memory Mapping of STR91x * +*******************************************************************************/ + +#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */ +#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */ + +#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */ +#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */ + +#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */ +#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */ + +#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */ +#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */ + +#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */ +#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */ + +#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */ +#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */ + +#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */ +#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */ + +#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */ +#define AHB_FMI_B (0x44000000) /* FMI buffered Space */ + +/******************************************************************************* +* Addresses related to the VICs' peripherals * +*******************************************************************************/ + +#define VIC0_BASE (AHB_VIC0_U) +#define VIC1_BASE (AHB_VIC1_U) + +/******************************************************************************* +* Addresses related to the EMI banks * +*******************************************************************************/ + +#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */ +#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */ +#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */ +#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */ + +/******************************************************************************* +* Addresses related to the DMA peripheral * +*******************************************************************************/ + +#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */ +#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */ +#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */ +#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */ +#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */ +#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */ +#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */ +#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */ + +/******************************************************************************* +* Addresses related to the APB0 sub-system * +*******************************************************************************/ + +#define APB_WIU_OFST (0x00001000) /* Offset of WIU */ +#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */ +#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */ +#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */ +#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */ +#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */ +#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */ +#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */ +#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */ +#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */ +#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */ +#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */ +#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */ +#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */ +#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */ + +/******************************************************************************* +* Addresses related to the APB1 sub-system * +*******************************************************************************/ + +#define APB_RTC_OFST (0x00001000) /* Offset of RTC */ +#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */ +#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */ +#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */ +#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */ +#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */ +#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */ +#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */ +#define APB_CAN_OFST (0x00009000) /* Offset of CAN */ +#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */ +#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */ +#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */ +#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */ + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Unbuffered Mode ------------------------------*/ +/*----------------------------------------------------------------------------*/ + +#ifndef LIBUFF + +/******************************************************************************* +* AHBAPB peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_U) +#define AHBAPB1_BASE (AHB_APB_BRDG1_U) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_U) +#define ENET_DMA_BASE (AHB_ENET_DMA_U) + +/******************************************************************************* +* DMA peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_U) + +/******************************************************************************* +* EMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_U) + +/******************************************************************************* +* FMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_U) + + +#else /* LIBUFF */ + +/*----------------------------------------------------------------------------*/ +/*------------------------------ Buffered Mode -------------------------------*/ +/*----------------------------------------------------------------------------*/ + +/******************************************************************************* +* AHBAPB peripheral Buffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_B) +#define AHBAPB1_BASE (AHB_APB_BRDG1_B) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_B) +#define ENET_DMA_BASE (AHB_ENET_DMA_B) + +/******************************************************************************* +* DMA peripheral Buffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_B) + +/******************************************************************************* +* EMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_B) + +/******************************************************************************* +* FMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_B) + +#endif /* LIBUFF */ + +/******************************************************************************* +* DMA channels Base Address * +*******************************************************************************/ +#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST) +#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST) +#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST) +#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST) +#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST) +#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST) +#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST) +#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST) + +/******************************************************************************* +* EMI Banks peripheral Base Address * +*******************************************************************************/ + +#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST) +#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST) +#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST) +#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST) + +/******************************************************************************* +* APB0 Peripherals' Base addresses * +*******************************************************************************/ + +#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST) +#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST) +#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST) +#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST) +#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST) +#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST) +#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST) +#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST) +#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST) +#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST) +#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST) +#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST) +#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST) +#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST) +#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST) + +/******************************************************************************* +* APB1 Peripherals' Base addresses * +*******************************************************************************/ + +#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST) +#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST) +#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST) +#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST) +#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST) +#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST) +#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST) +#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST) +#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST) +#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST) +#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST) +#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST) +#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST) + +/******************************************************************************* +* IPs' declaration * +*******************************************************************************/ + +/*------------------------------ Non Debug Mode ------------------------------*/ + +#ifndef LIBDEBUG + +/*********************************** AHBAPB ***********************************/ + +#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE) +#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE) + +/************************************* EMI ************************************/ + +#define EMI ((EMI_TypeDef *)EMI_BASE) + +/************************************* DMA ************************************/ + +#define DMA ((DMA_TypeDef *)DMA_BASE) +#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) +#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) +#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) +#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) +#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) +#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE) +#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE) +#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE) + +/************************************* EMI ************************************/ + +#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE) +#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE) +#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE) +#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE) + +/************************************* ENET_MAC ************************************/ + +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) + +/************************************* ENET_DMA ************************************/ + +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +/************************************* FMI ************************************/ + +#define FMI ((FMI_TypeDef *)FMI_BASE) + +/************************************* VIC ************************************/ + +#define VIC0 ((VIC_TypeDef *)VIC0_BASE) +#define VIC1 ((VIC_TypeDef *)VIC1_BASE) + +/******************************************************************************* +* APB0 Peripherals' * +*******************************************************************************/ +#define WIU ((WIU_TypeDef *)WIU_BASE) +#define TIM0 ((TIM_TypeDef *)TIM0_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) +#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) +#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) +#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE) +#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE) +#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE) +#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE) +#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE) +#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE) +#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE) +/******************************************************************************* +* APB1 Peripherals' * +*******************************************************************************/ +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define SCU ((SCU_TypeDef *)SCU_BASE) +#define MC ((MC_TypeDef *)MC_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define SSP0 ((SSP_TypeDef *)SSP0_BASE) +#define SSP1 ((SSP_TypeDef *)SSP1_BASE) +#define CAN ((CAN_TypeDef *)CAN_BASE) +#define ADC ((ADC_TypeDef *)ADC_BASE) +#define WDG ((WDG_TypeDef *)WDG_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +#else /* LIBDEBUG */ + +/*-------------------------------- Debug Mode --------------------------------*/ + +EXT AHBAPB_TypeDef *AHBAPB0; +EXT AHBAPB_TypeDef *AHBAPB1; +EXT DMA_TypeDef *DMA; +EXT DMA_Channel_TypeDef *DMA_Channel0; +EXT DMA_Channel_TypeDef *DMA_Channel1; +EXT DMA_Channel_TypeDef *DMA_Channel2; +EXT DMA_Channel_TypeDef *DMA_Channel3; +EXT DMA_Channel_TypeDef *DMA_Channel4; +EXT DMA_Channel_TypeDef *DMA_Channel5; +EXT DMA_Channel_TypeDef *DMA_Channel6; +EXT DMA_Channel_TypeDef *DMA_Channel7; +EXT EMI_Bank_TypeDef *EMI_Bank0; +EXT EMI_Bank_TypeDef *EMI_Bank1; +EXT EMI_Bank_TypeDef *EMI_Bank2; +EXT EMI_Bank_TypeDef *EMI_Bank3; +EXT FMI_TypeDef *FMI; +EXT VIC_TypeDef *VIC0; +EXT VIC_TypeDef *VIC1; +EXT WIU_TypeDef *WIU; +EXT TIM_TypeDef *TIM0; +EXT TIM_TypeDef *TIM1; +EXT TIM_TypeDef *TIM2; +EXT TIM_TypeDef *TIM3; +EXT GPIO_TypeDef *GPIO0; +EXT GPIO_TypeDef *GPIO1; +EXT GPIO_TypeDef *GPIO2; +EXT GPIO_TypeDef *GPIO3; +EXT GPIO_TypeDef *GPIO4; +EXT GPIO_TypeDef *GPIO5; +EXT GPIO_TypeDef *GPIO6; +EXT GPIO_TypeDef *GPIO7; +EXT GPIO_TypeDef *GPIO8; +EXT GPIO_TypeDef *GPIO9; +EXT RTC_TypeDef *RTC; +EXT SCU_TypeDef *SCU; +EXT MC_TypeDef *MC; +EXT UART_TypeDef *UART0; +EXT UART_TypeDef *UART1; +EXT UART_TypeDef *UART2; +EXT SSP_TypeDef *SSP0; +EXT SSP_TypeDef *SSP1; +EXT CAN_TypeDef *CAN; +EXT ADC_TypeDef *ADC; +EXT WDG_TypeDef *WDG; +EXT I2C_TypeDef *I2C0; +EXT I2C_TypeDef *I2C1; +EXT ENET_MAC_TypeDef *ENET_MAC; +EXT ENET_DMA_TypeDef *ENET_DMA; + + +#endif /* LIBDEBUG */ + +#endif /* __91x_MAP_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_mc.h b/uc_str912/prj_template91x/str91x_lib/include/91x_mc.h new file mode 100644 index 0000000..b33b7c3 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_mc.h @@ -0,0 +1,144 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_mc.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* MC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_MC_H +#define __91x_MC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u16 MC_OperatingMode; + u16 MC_TachoMode; + u16 MC_TachoEvent_Mode; + u8 MC_Prescaler; + u8 MC_ForcedPWMState; + u16 MC_TachoPrescaler; + u16 MC_PWMMode; + u16 MC_Complementary; + u16 MC_Emergency; + u16 MC_Period; + u16 MC_TachoPeriod; + u16 MC_Channel; + u16 MC_PulseU; + u16 MC_PulseV; + u16 MC_PulseW; + u16 MC_PolarityUL; + u16 MC_PolarityUH; + u16 MC_PolarityVL; + u16 MC_PolarityVH; + u16 MC_PolarityWL; + u16 MC_PolarityWH; + u16 MC_TachoPolarity; + u16 MC_DeadTime; + u8 MC_RepetitionCounter; +} MC_InitTypeDef; + +typedef enum { DOWN = 0, UP = !DOWN} CountingStatus; + +/* Exported constants --------------------------------------------------------*/ +#define MC_Complementary_Enable 0x0001 +#define MC_Complementary_Disable 0x0002 + +#define MC_HardwareOperating_Mode 0x0001 +#define MC_SoftwareOperating_Mode 0x0002 + +#define MC_PWMClassical_Mode 0x0001 +#define MC_PWMZeroCentered_Mode 0x0002 + +#define MC_Emergency_Enable 0x0001 +#define MC_Emergency_Disable 0x0002 + +#define MC_Polarity_Inverted 0x0001 +#define MC_Polarity_NonInverted 0x0002 + +#define MC_TachoOneShot_Mode 0x0001 +#define MC_TachoContinuous_Mode 0x0002 + +#define MC_TachoEventEdge_None 0x0000 +#define MC_TachoEventEdge_Falling 0x0001 +#define MC_TachoEventEdge_Rising 0x0002 +#define MC_TachoEventEdge_RisingFalling 0x0003 + +#define MC_Channel_U 0x0001 +#define MC_Channel_V 0x0002 +#define MC_Channel_W 0x0003 +#define MC_Channel_ALL 0x0004 + + +#define MC_TachoEvent_Hardware_Mode 0x0001 +#define MC_TachoEvent_Software_Mode 0x0002 + +#define MC_IT_CMPW 0x0001 +#define MC_IT_CMPV 0x0002 +#define MC_IT_CMPU 0x0004 +#define MC_IT_ZPC 0x0008 +#define MC_IT_ADT 0x0010 +#define MC_IT_OTC 0x0020 +#define MC_IT_CPT 0x0040 +#define MC_IT_CM0 0x0080 + +#define MC_FLAG_CMPW 0x0001 +#define MC_FLAG_CMPV 0x0002 +#define MC_FLAG_CMPU 0x0004 +#define MC_FLAG_ZPC 0x0008 +#define MC_FLAG_ADT 0x0010 +#define MC_FLAG_OTC 0x0020 +#define MC_FLAG_CPT 0x0040 +#define MC_FLAG_CM0 0x0080 +#define MC_FLAG_EST 0x0100 +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void MC_Init(MC_InitTypeDef* MC_InitStruct); +void MC_DeInit(void); +void MC_StructInit(MC_InitTypeDef* MC_InitStruct); +void MC_Cmd(FunctionalState NewState); +void MC_CtrlPWMOutputs(FunctionalState Newstate); +void MC_ITConfig(u16 MC_IT, FunctionalState NewState); +void MC_SetPrescaler(u8 Prescaler); +void MC_SetPeriod(u16 MC_Period); +void MC_SetPulseU(u16 MC_PulseU); +void MC_SetPulseV(u16 MC_PulseV); +void MC_SetPulseW(u16 MC_PulseW); +void MC_SetTachoCompare(u8 MC_Compare); +void MC_PWMModeConfig(u16 MC_PWMMode); +void MC_SetDeadTime(u16 MC_DeadTime); +void MC_EmergencyCmd(FunctionalState NewState); +void MC_EmergencyClear(void); +u16 MC_GetPeriod(void); +u16 MC_GetPulseU(void); +u16 MC_GetPulseV(void); +u16 MC_GetPulseW(void); +u16 MC_GetTachoCapture(void); +void MC_ClearOnTachoCapture(FunctionalState NewState); +void MC_ForceDataTransfer(u8 MC_ForcedData); +void MC_SoftwarePreloadConfig(void); +void MC_SoftwareTachoCapture(void); +CountingStatus MC_GetCountingStatus(void); +FlagStatus MC_GetFlagStatus(u16 MC_FLAG); +void MC_ClearFlag(u16 MC_FLAG); +ITStatus MC_GetITStatus(u16 MC_IT); +void MC_ClearITPendingBit(u16 MC_IT); + +#endif /* __91x_MC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_rtc.h b/uc_str912/prj_template91x/str91x_lib/include/91x_rtc.h new file mode 100644 index 0000000..25a2805 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_rtc.h @@ -0,0 +1,109 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_rtc.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the RTC library software functions +* prototypes & definitions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_RTC_H +#define __91x_RTC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Private typedef -----------------------------------------------------------*/ +typedef struct +{ + u8 century; + u8 year; + u8 month; + u8 day; + u8 weekday; +}RTC_DATE; + +typedef struct +{ + u8 hours; + u8 minutes; + u8 seconds; + u16 milliseconds; +}RTC_TIME; + +typedef struct +{ + u8 day; + u8 hours; + u8 minutes; + u8 seconds; +}RTC_ALARM; + +/* Exported constants --------------------------------------------------------*/ + +#define BINARY 0 +#define BCD 1 + +/*TamperMode*/ +#define RTC_TamperMode_Edge 0xFFFFFFEF +#define RTC_TamperMode_Level 0x10 + +/*TamperPol*/ +#define RTC_TamperPol_High 0x4 +#define RTC_TamperPol_Low 0xFFFFFFFB + +/*PeriodicClock*/ +#define RTC_Per_2Hz 0x10000 +#define RTC_Per_16Hz 0x20000 +#define RTC_Per_128Hz 0x40000 +#define RTC_Per_1024Hz 0x80000 +#define RTC_Per_DISABLE 0x0 + +/*RTC_IT*/ +#define RTC_IT_Per 0x200000 +#define RTC_IT_Alarm 0x800000 +#define RTC_IT_Tamper 0x400000 + +/*RTC_FLAG*/ +#define RTC_FLAG_Per 0x80000000 +#define RTC_FLAG_Alarm 0x40000000 +#define RTC_FLAG_Tamper 0x10000000 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RTC_DeInit(void); +void RTC_SetDate(RTC_DATE Date); +void RTC_SetTime(RTC_TIME Time); +void RTC_SetAlarm(RTC_ALARM Alarm); +void RTC_GetDate(u8 Format, RTC_DATE * Date); +void RTC_GetTime(u8 Format, RTC_TIME * Time); +void RTC_GetAlarm(u8 Format, RTC_ALARM * Alarm); +void RTC_TamperConfig(u32 TamperMode, u32 TamperPol); +void RTC_TamperCmd(FunctionalState NewState); +void RTC_AlarmCmd(FunctionalState NewState); +void RTC_CalibClockCmd(FunctionalState NewState); +void RTC_SRAMBattPowerCmd(FunctionalState NewState); +void RTC_PeriodicIntConfig(u32 PeriodicClock); +void RTC_ITConfig(u32 RTC_IT, FunctionalState NewState); +FlagStatus RTC_GetFlagStatus(u32 RTC_FLAG); +void RTC_ClearFlag(u32 RTC_FLAG); +#endif /*__91x_RTC_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + + + diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_scu.h b/uc_str912/prj_template91x/str91x_lib/include/91x_scu.h new file mode 100644 index 0000000..22d9260 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_scu.h @@ -0,0 +1,198 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +* prototypes & definitions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_SCU_H +#define __91x_SCU_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported constants --------------------------------------------------------*/ + +/*MCLK_Source*/ +#define SCU_MCLK_PLL 0x0 +#define SCU_MCLK_RTC 0x1 +#define SCU_MCLK_OSC 0x2 + +/*RCLK_Divisor*/ +#define SCU_RCLK_Div1 0xFFFFFFE3 +#define SCU_RCLK_Div2 0x4 +#define SCU_RCLK_Div4 0x8 +#define SCU_RCLK_Div8 0xC +#define SCU_RCLK_Div16 0x10 +#define SCU_RCLK_Div1024 0x14 + +/*HCLK_Divisor*/ +#define SCU_HCLK_Div1 0xFFFFFF9F +#define SCU_HCLK_Div2 0x20 +#define SCU_HCLK_Div4 0x40 + +/*PCLK_Divisor*/ +#define SCU_PCLK_Div1 0xFFFFFE7F +#define SCU_PCLK_Div2 0x80 +#define SCU_PCLK_Div4 0x100 +#define SCU_PCLK_Div8 0x180 + +/*FMICLK_Divisor*/ +#define SCU_FMICLK_Div1 0xFFFEFFFF +#define SCU_FMICLK_Div2 0x10000 + +/*BRCLK_Divisor*/ +#define SCU_BRCLK_Div1 0xFFFFFDFF +#define SCU_BRCLK_Div2 0x200 + +/*TIMCLK_Source*/ +#define SCU_TIMCLK_EXT 0x1 +#define SCU_TIMCLK_INT 0x0 + +/*TIMx*/ +#define SCU_TIM01 0x0 +#define SCU_TIM23 0x1 + + +/*USBCLK_Source*/ +#define SCU_USBCLK_MCLK 0xFFFFF3FF +#define SCU_USBCLK_MCLK2 0x400 +#define SCU_USBCLK_EXT 0x800 + +/*SCU_EMIBCLK*/ +#define SCU_EMIBCLK_Div1 0xFFF9FFFF +#define SCU_EMIBCLK_Div2 0x20000 + +/*SCU_EMIMODE*/ +#define SCU_EMI_MUX 0xFFFFFFBF +#define SCU_EMI_DEMUX 0x40 + +/*SCU_EMIALE_LEN*/ +#define SCU_EMIALE_LEN1 0xFFFFFEFF +#define SCU_EMIALE_LEN2 0x100 + +/*SCU_EMIALE_POL*/ +#define SCU_EMIALE_POLLow 0xFFFFFF7F +#define SCU_EMIALE_POLHigh 0x80 + +/*UART_IrDA_Mode*/ +#define SCU_UARTMode_IrDA 0x1 +#define SCU_UARTMode_UART 0x0 + +/*APBPeriph*/ +#define __TIM01 0x1 +#define __TIM23 0x2 +#define __MC 0x4 +#define __UART0 0x8 +#define __UART1 0x10 +#define __UART2 0x20 +#define __I2C0 0x40 +#define __I2C1 0x80 +#define __SSP0 0x100 +#define __SSP1 0x200 +#define __CAN 0x400 +#define __ADC 0x800 +#define __WDG 0x1000 +#define __WIU 0x2000 +#define __GPIO0 0x4000 +#define __GPIO1 0x8000 +#define __GPIO2 0x10000 +#define __GPIO3 0x20000 +#define __GPIO4 0x40000 +#define __GPIO5 0x80000 +#define __GPIO6 0x100000 +#define __GPIO7 0x200000 +#define __GPIO8 0x400000 +#define __GPIO9 0x800000 +#define __RTC 0x1000000 + +/*AHBPeriph*/ +#define __FMI 0x1 +#define __FPQBC 0x2 +#define __SRAM 0x8 +#define __SRAM_ARBITER 0x10 +#define __VIC 0x20 +#define __EMI 0x40 +#define __EMI_MEM_CLK 0x80 +#define __DMA 0x100 +#define __USB 0x200 +#define __USB48M 0x400 +#define __ENET 0x800 +#define __PFQBC_AHB 0x1000 + +/*SCU_IT*/ +#define SCU_IT_LVD_RST 0x10 +#define SCU_IT_SRAM_ERROR 0x8 +#define SCU_IT_ACK_PFQBC 0x4 +#define SCU_IT_LOCK_LOST 0x2 +#define SCU_IT_LOCK 0x1 + +/*SCU_FLAG*/ +#define SCU_FLAG_SRAM_ERROR 0x20 +#define SCU_FLAG_ACK_PFQBC 0x10 +#define SCU_FLAG_LVD_RESET 0x8 +#define SCU_FLAG_WDG_RST 0x4 +#define SCU_FLAG_LOCK_LOST 0x2 +#define SCU_FLAG_LOCK 0x1 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source); +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP); +ErrorStatus SCU_PLLCmd(FunctionalState NewState); +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor); +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor); +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor); +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor); +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source); +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler); +void SCU_USBCLKConfig(u32 USBCLK_Source); +void SCU_PHYCLKConfig(FunctionalState NewState); +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor); +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK); +void SCU_EMIModeConfig(u32 SCU_EMIMODE); +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL); +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState); +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag); +void SCU_ClearFlag(u32 SCU_Flag); +u32 SCU_GetPLLFreqValue(void); +u32 SCU_GetMCLKFreqValue(void); +u32 SCU_GetRCLKFreqValue(void); +u32 SCU_GetHCLKFreqValue(void); +u32 SCU_GetPCLKFreqValue(void); +void SCU_WakeUpLineConfig(u8 EXTint); +void SCU_SpecIntRunModeConfig(FunctionalState NewState); +void SCU_EnterIdleMode(void); +void SCU_EnterSleepMode(void); +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode); +void SCU_PFQBCCmd(FunctionalState NewState); + +extern const u32 _Main_Crystal; + +#endif /*__91x_SCU_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_ssp.h b/uc_str912/prj_template91x/str91x_lib/include/91x_ssp.h new file mode 100644 index 0000000..e356d4f --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_ssp.h @@ -0,0 +1,119 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ssp.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* SSP software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_SSP_H +#define __91x_SSP_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* SSP Init structure definition */ +typedef struct +{ + u16 SSP_FrameFormat ; + u16 SSP_Mode ; + u16 SSP_CPOL ; + u16 SSP_CPHA ; + u16 SSP_DataSize ; + u16 SSP_SlaveOutput ; + u8 SSP_ClockRate ; + u8 SSP_ClockPrescaler ; +}SSP_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* SSP Frame Format Select */ +#define SSP_FrameFormat_TI 0x0010 +#define SSP_FrameFormat_Motorola 0xFFCF +#define SSP_FrameFormat_Microwire 0x0020 + +/* SSP Master/Slave Select */ +#define SSP_Mode_Master 0xFFFB +#define SSP_Mode_Slave 0x0004 + +/* SSP Clock Polarity */ +#define SSP_CPOL_Low 0xFFBF +#define SSP_CPOL_High 0x0040 + +/* SSP Clock Phase */ +#define SSP_CPHA_1Edge 0xFF7F +#define SSP_CPHA_2Edge 0x0080 + +/* SSP Data Size */ +#define SSP_DataSize_16b 0x000F +#define SSP_DataSize_15b 0x000E +#define SSP_DataSize_14b 0x000D +#define SSP_DataSize_13b 0x000C +#define SSP_DataSize_12b 0x000B +#define SSP_DataSize_11b 0x000A +#define SSP_DataSize_10b 0x0009 +#define SSP_DataSize_9b 0x0008 +#define SSP_DataSize_8b 0x0007 +#define SSP_DataSize_7b 0x0006 +#define SSP_DataSize_6b 0x0005 +#define SSP_DataSize_5b 0x0004 +#define SSP_DataSize_4b 0x0003 + +/* SSP Slave output config */ +#define SSP_SlaveOutput_Enable 0xFFF7 +#define SSP_SlaveOutput_Disable 0x0008 + +/* SSP Interrupts */ +#define SSP_IT_TxFifo 0x0008 +#define SSP_IT_RxFifo 0x0004 +#define SSP_IT_RxTimeOut 0x0002 +#define SSP_IT_RxOverrun 0x0001 + +/* SSP Flags */ +#define SSP_FLAG_Busy 0x0024 +#define SSP_FLAG_RxFifoFull 0x0023 +#define SSP_FLAG_RxFifoNotEmpty 0x0022 +#define SSP_FLAG_TxFifoNotFull 0x0021 +#define SSP_FLAG_TxFifoEmpty 0x0020 +#define SSP_FLAG_TxFifo 0x0043 +#define SSP_FLAG_RxFifo 0x0042 +#define SSP_FLAG_RxTimeOut 0x0041 +#define SSP_FLAG_RxOverrun 0x0040 + +/* SSP DMA Requests */ +#define SSP_DMA_Transmit 0x0002 +#define SSP_DMA_Receive 0x0001 + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void SSP_DeInit(SSP_TypeDef* SSPx); +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct); +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct); +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState); +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState); +void SSP_DMACmd(SSP_TypeDef* SSPx, u16 SSP_DMATransfert, FunctionalState NewState); +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data); +u16 SSP_ReceiveData(SSP_TypeDef* SSPx); +void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState); +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG); +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG); +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT); +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT); + +#endif /* __91x_SSP_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_tim.h b/uc_str912/prj_template91x/str91x_lib/include/91x_tim.h new file mode 100644 index 0000000..b587c27 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_tim.h @@ -0,0 +1,155 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_tim.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* TIM software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_TIM_H +#define __91x_TIM_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" +#include "91x_scu.h" + +/* Exported types ----------------------------------------------------------- */ + +/* TIM Init structure define */ +typedef struct +{ + u16 TIM_Mode; /* Timer mode */ + u16 TIM_OC1_Modes; /* Output Compare 1 Mode: Timing or Wave */ + u16 TIM_OC2_Modes; /* Output Compare 2 Mode: Timing or Wave */ + u16 TIM_Clock_Source; /* Timer Clock source APB/SCU/EXTERNAL */ + u16 TIM_Clock_Edge; /* Timer Clock Edge: Rising or Falling Edge */ + u16 TIM_OPM_INPUT_Edge; /* Timer Input Capture 1 Edge used in OPM Mode */ + u16 TIM_ICAP1_Edge; /* Timer Input Capture 1 Edge used in ICAP1 Mode */ + u16 TIM_ICAP2_Edge; /* Timer Input Capture 2 Edge used in ICAP2 Mode */ + u8 TIM_Prescaler; /* Timer Prescaler factor */ + u16 TIM_Pulse_Level_1; /* Level applied on the Output Compare Pin 1 */ + u16 TIM_Pulse_Level_2; /* Level applied on the Output Compare Pin 2 */ + u16 TIM_Period_Level; /* Level applied during the Period of a PWM Mode */ + u16 TIM_Pulse_Length_1; /* Pulse 1 Length used in Output Compare 1 Mode */ + u16 TIM_Pulse_Length_2; /* Pulse 2 Length used in Output Compare 2 Mode */ + u16 TIM_Full_Period; /* Period Length used in PWM Mode */ +} TIM_InitTypeDef; + +typedef enum +{ + TIM_START, + TIM_STOP, + TIM_CLEAR +} TIM_CounterOperations; + +/* Exported constants --------------------------------------------------------*/ + +/* TIM MODE */ +#define TIM_PWMI 0x4000 /* PWM INPUT Mode */ +#define TIM_OCM_CHANNEL_1 0x0040 /* OUTPUT COMPARE CHANNEL 1 Mode */ +#define TIM_OCM_CHANNEL_2 0x0080 /* OUTPUT COMPARE CHANNEL 2 Mode */ +#define TIM_OCM_CHANNEL_12 0x00C0 /* OUTPUT COMPARE CHANNEL 1 & 2 Mode */ +#define TIM_PWM 0x0010 /* PWM Mode */ +#define TIM_OPM 0x0020 /* ONE PULSE Mode */ +#define TIM_ICAP_CHANNEL_1 0x0400 /* INPUT CAPTURE 1 Mode */ +#define TIM_ICAP_CHANNEL_2 0x0500 /* INPUT CAPTURE 2 Mode */ +#define TIM_ICAP_CHANNEL_12 0x0600 /* INPUT CAPTURE 1 & 2 Mode */ + +/* TIM OUTPUT COMPARE MODE */ +#define TIM_WAVE 0x0001 +#define TIM_TIMING 0x0002 + +/* TIM CLOCK SOURCE */ +#define TIM_CLK_APB 0xFFFE +#define TIM_CLK_EXTERNAL 0x0001 +#define TIM_CLK_SCU 0x0001 + +/* TIM CLOCK EDGE */ +#define TIM_CLK_EDGE_FALLING 0xFFFD +#define TIM_CLK_EDGE_RISING 0x0002 + +/* TIM OPM INPUT EDGE */ +#define TIM_OPM_EDGE_FALLING 0xFFFB +#define TIM_OPM_EDGE_RISING 0x0004 + +/* TIM ICAPA INPUT EDGE */ +#define TIM_ICAP1_EDGE_FALLING 0xFFFB +#define TIM_ICAP1_EDGE_RISING 0x0004 + +/* TIM ICAPB INPUT EDGE */ +#define TIM_ICAP2_EDGE_FALLING 0xFFF7 +#define TIM_ICAP2_EDGE_RISING 0x0008 + +/* TIM OUTPUT LEVEL */ +#define TIM_HIGH 0x0200 +#define TIM_LOW 0x0300 + +/* TIM OUTPUT EDGE */ +#define TIM_OUTPUT_EDGE_RISING 0x8000 +#define TIM_OUTPUT_EDGE_FALLING 0x0800 + +/* TIM channels */ +#define TIM_PWM_OC1_Channel 0x1 /* PWM/Output Compare 1 Channel */ +#define TIM_OC2_Channel 0x2 /* Output Compare 2 Channel */ + +/* TIM DMA SOURCE */ +#define TIM_DMA_IC1 0x0000 /* Input Capture Channel 1 DMA Source */ +#define TIM_DMA_OC1 0x1000 /* OUTPUT Compare Channel 1 DMA Source */ +#define TIM_DMA_IC2 0x2000 /* Input Capture Channel 2 DMA Source */ +#define TIM_DMA_OC2 0x3000 /* OUTPUT Compare Channel 2 DMA Source */ + +/* TIM DMA ENABLE or DISABLE */ +#define TIM_DMA_ENABLE 0x0400 /* DMA Enable */ +#define TIM_DMA_DISABLE 0xFBFF /* DMA Disable */ + +/* TIM Interruption Sources*/ +#define TIM_IT_IC1 0x8000 /* Input Capture Channel 1 Interrupt Source */ +#define TIM_IT_OC1 0x4000 /* Output Compare Channel 1 Interrupt Source */ +#define TIM_IT_TO 0x2000 /* Timer OverFlow Interrupt Source */ +#define TIM_IT_IC2 0x1000 /* Input Capture Channel 2 Interrupt Source */ +#define TIM_IT_OC2 0x0800 /* Output Compare Channel 2 Interrupt Source */ + +/* TIM Flags */ +#define TIM_FLAG_IC1 0x8000 /* Input Capture Channel 1 Flag */ +#define TIM_FLAG_OC1 0x4000 /* Output Compare Channel 1 Flag */ +#define TIM_FLAG_TO 0x2000 /* Timer OverFlow Flag */ +#define TIM_FLAG_IC2 0x1000 /* Input Capture Channel 2 Flag */ +#define TIM_FLAG_OC2 0x0800 /* Output Compare Channel 2 Flag */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct); +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct); +void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler); +u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx); +u16 TIM_GetCounterValue(TIM_TypeDef *TIMx); +u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx); +u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx); +void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag); +void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag); +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx); +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx); +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate); +void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources); +void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate); + +#endif /* __91x_TIM_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_type.h b/uc_str912/prj_template91x/str91x_lib/include/91x_type.h new file mode 100644 index 0000000..916d81c --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_type.h @@ -0,0 +1,50 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_type.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : It contains common types and constants used in all the +* peripherals' drivers. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +#ifndef __91x_type_H +#define __91x_type_H + + typedef long long u64; + typedef unsigned long u32; + typedef unsigned short u16; + typedef unsigned char u8; + + typedef signed long s32; + typedef signed short s16; + typedef signed char s8; + + typedef volatile unsigned long vu32; + typedef volatile unsigned short vu16; + typedef volatile unsigned char vu8; + + typedef volatile signed long vs32; + typedef volatile signed short vs16; + typedef volatile signed char vs8; + +typedef enum { FALSE = 0, TRUE = !FALSE } bool; + +typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; + +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#endif /* __91x_type_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_uart.h b/uc_str912/prj_template91x/str91x_lib/include/91x_uart.h new file mode 100644 index 0000000..b979438 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_uart.h @@ -0,0 +1,174 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_uart.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* UART software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_UART_H +#define __91x_UART_H + +/* Includes ------------------------------------------------------------------*/ +#include <91x_map.h> + +/* Exported types ------------------------------------------------------------*/ +/* UART FIFO Level enumeration */ +typedef enum +{ + UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */ + UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */ + UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */ + UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */ + UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */ +}UART_FIFOLevel; + +/* UART Init Structure definition */ +typedef struct +{ + u16 UART_WordLength; + u16 UART_StopBits; + u16 UART_Parity; + u32 UART_BaudRate; + u16 UART_HardwareFlowControl; + u16 UART_Mode; + u16 UART_FIFO; + UART_FIFOLevel UART_TxFIFOLevel; + UART_FIFOLevel UART_RxFIFOLevel; +}UART_InitTypeDef; + + +/* UART RTS enumeration */ +typedef enum +{ + LowLevel = 0, + HighLevel +}UART_LevelTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* UART Data Length */ +#define UART_WordLength_5D 0x0000 /* 5 bits Data */ +#define UART_WordLength_6D 0x0020 /* 6 bits Data */ +#define UART_WordLength_7D 0x0040 /* 7 bits Data */ +#define UART_WordLength_8D 0x0060 /* 8 bits Data */ + +/* UART Stop Bits */ +#define UART_StopBits_1 0xFFF7 /* Disable two stop bit is transmitted + at the end of frame */ +#define UART_StopBits_2 0x0008 /* Enable Two stop bits are transmitted + at the end of frame */ +/* UART Parity */ +#define UART_Parity_No 0x0000 /* Parity Disable */ +#define UART_Parity_Even 0x0006 /* Even Parity */ +#define UART_Parity_Odd 0x0002 /* Odd Parity */ +#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */ +#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */ + +/* UART Hardware Flow Control */ +#define UART_HardwareFlowControl_None 0x0000 /* HFC Disable */ +#define UART_HardwareFlowControl_RTS 0x4000 /* RTS Enable */ +#define UART_HardwareFlowControl_CTS 0x8000 /* CTS Enable */ +#define UART_HardwareFlowControl_RTS_CTS 0xC000 /* CTS and RTS Enable */ + +/* UART Mode */ +#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */ +#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */ +#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */ + +/* UART FIFO */ +#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */ +#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */ + +/* UART Interrupt definition */ +#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt mask */ +#define UART_IT_BreakError 0x0200 /* Break Error interrupt mask */ +#define UART_IT_ParityError 0x0100 /* Parity Error interrupt mask */ +#define UART_IT_FrameError 0x0080 /* Frame Error interrupt mask */ +#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt mask */ +#define UART_IT_Transmit 0x0020 /* Transmit interrupt mask */ +#define UART_IT_Receive 0x0010 /* Receive interrupt mask */ +#define UART_IT_DSR 0x0008 /* DSR interrupt mask */ +#define UART_IT_DCD 0x0004 /* DCD interrupt mask */ +#define UART_IT_CTS 0x0002 /* CTS interrupt mask */ +#define UART_IT_RI 0x0001 /* RI interrupt mask */ + +/* UART DMA On Error */ +#define UART_DMAOnError_Enable 0xFFFB /* DMA receive request enabled + when the UART error interrupt + is asserted. */ +#define UART_DMAOnError_Disable 0x0004 /* DMA receive request disabled + when the UART error interrupt + is asserted. */ +/* UART DMA Request */ +#define UART_DMAReq_Tx 0x02 /* Transmit DMA Enable */ +#define UART_DMAReq_Rx 0x01 /* Receive DMA Enable */ + +/* UART FLAG */ +#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */ +#define UART_FLAG_Break 0x22 /* break error flag */ +#define UART_FLAG_ParityError 0x21 /* parity error flag */ +#define UART_FLAG_FrameError 0x20 /* frame error flag */ +#define UART_FLAG_RI 0x48 /* RI flag */ +#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */ +#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */ +#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */ +#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */ +#define UART_FLAG_Busy 0x43 /* UART Busy flag */ +#define UART_FLAG_DCD 0x42 /* DCD flag */ +#define UART_FLAG_DSR 0x41 /* DSR flag */ +#define UART_FLAG_CTS 0x40 /* CTS flag */ +#define UART_RawIT_OverrunError 0x6A /* Overrun Error Raw IT flag */ +#define UART_RawIT_BreakError 0x69 /* Break Error Raw IT flag */ +#define UART_RawIT_ParityError 0x68 /* Parity Error Raw IT flag */ +#define UART_RawIT_FrameError 0x67 /* Frame Error Raw IT flag */ +#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Raw IT flag */ +#define UART_RawIT_Transmit 0x65 /* Transmit Raw IT flag */ +#define UART_RawIT_Receive 0x64 /* Receive Raw IT flag */ +#define UART_RawIT_DSR 0x63 /* DSR Raw IT flag */ +#define UART_RawIT_DCD 0x62 /* DCD Raw IT flag */ +#define UART_RawIT_CTS 0x61 /* CTS Raw IT flag */ +#define UART_RawIT_RI 0x60 /* RI Raw IT flag */ + +/*IrDAx select*/ +#define IrDA0 0x01 /*IrDA0 select*/ +#define IrDA1 0x02 /*IrDA0 select*/ +#define IrDA2 0x03 /*IrDA0 select*/ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void UART_DeInit(UART_TypeDef* UARTx); +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState); +void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError); +void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState); +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT); +void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState); +void UART_IrDACmd(u8 IrDAx, FunctionalState NewState); +void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter); +void UART_SendData(UART_TypeDef* UARTx, u8 Data); +u8 UART_ReceiveData(UART_TypeDef* UARTx); +void UART_SendBreak(UART_TypeDef* UARTx); +void UART_DTRConfig(UART_LevelTypeDef LevelState); +void UART_RTSConfig(UART_LevelTypeDef LevelState); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT); + +#endif /* __91x_UART_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_vic.h b/uc_str912/prj_template91x/str91x_lib/include/91x_vic.h new file mode 100644 index 0000000..127716a --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_vic.h @@ -0,0 +1,94 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_vic.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* VIC software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_VIC_H +#define __91x_VIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" +#include "91x_it.h" + +/* Exported types ------------------------------------------------------------*/ +/* Type of interrupt */ +typedef enum +{ + VIC_IRQ, + VIC_FIQ +} VIC_ITLineMode; + +/* Exported constants --------------------------------------------------------*/ + +/* VIC sources*/ + +#define WDG_ITLine 0 +#define SW_ITLine 1 +#define ARMRX_ITLine 2 +#define ARMTX_ITLine 3 +#define TIM0_ITLine 4 +#define TIM1_ITLine 5 +#define TIM2_ITLine 6 +#define TIM3_ITLine 7 +#define USBHP_ITLine 8 +#define USBLP_ITLine 9 +#define SCU_ITLine 10 +#define ENET_ITLine 11 +#define DMA_ITLine 12 +#define CAN_ITLine 13 +#define MC_ITLine 14 +#define ADC_ITLine 15 +#define UART0_ITLine 16 +#define UART1_ITLine 17 +#define UART2_ITLine 18 +#define I2C0_ITLine 19 +#define I2C1_ITLine 20 +#define SSP0_ITLine 21 +#define SSP1_ITLine 22 +#define LVD_ITLine 23 +#define RTC_ITLine 24 +#define WIU_ITLine 25 +#define EXTIT0_ITLine 26 +#define EXTIT1_ITLine 27 +#define EXTIT2_ITLine 28 +#define EXTIT3_ITLine 29 +#define USBWU_ITLine 30 +#define PFQBC_ITLine 31 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void VIC_DeInit(void); +FlagStatus VIC_GetIRQStatus(u16 VIC_Source); +FlagStatus VIC_GetFIQStatus(u16 VIC_Source); +FlagStatus VIC_GetSourceITStatus(u16 VIC_Source); +void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState); +void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState); +void VIC_ProtectionCmd(FunctionalState VIC_NewState); +u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx); +u32 VIC_GetISRVectAdd(u16 VIC_Source); +void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority); + +#endif /* __91x_VIC_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_wdg.h b/uc_str912/prj_template91x/str91x_lib/include/91x_wdg.h new file mode 100644 index 0000000..fc70547 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_wdg.h @@ -0,0 +1,82 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wdg.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* WDG software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_WDG_H +#define __91x_WDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ +u16 WDG_Mode; +u16 WDG_ClockSource; +u16 WDG_Prescaler; +u16 WDG_Preload; + +} WDG_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/* WDG_Mode */ +#define WDG_Mode_Wdg 0x0001 /*WDG configured to run in watchdog mode.*/ +#define WDG_Mode_Timer 0xFFFE /*WDG configured to be in Free-running Timer mode.*/ + + +/* WDG_ClockSource */ +#define WDG_ClockSource_Rtc 0x0004 /* External clock ( 32 khz RTC clock ) will be used as counting clock.*/ +#define WDG_ClockSource_Apb 0xFFFB /*The APB clock signal will be used as counting clock.*/ + +/* WDG_Prescaler */ +/*This member must be a number between 0x00 and 0xFF. +Specifies the Prescaler value to divide the clock source. +The clock of the Watchdog Timer Counter is divided by " WDG_Prescaler + 1".*/ + + + +/* WDG_Preload */ +/*This member must be a number between 0x0000 and 0xFFFF. +This value is loaded in the WDG Counter when it starts counting.*/ + + +/* WDG Sequence */ +#define WDG_KeyValue1 0xA55A +#define WDG_KeyValue2 0x5AA5 + +/* Exported macro ------------------------------------------------------------*/ + + +/* Exported functions ------------------------------------------------------- */ + +void WDG_DeInit(void); +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct); +void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct); +void WDG_Cmd(FunctionalState NewState); +void WDG_ITConfig(FunctionalState NewState); +u16 WDG_GetCounter(void); +FlagStatus WDG_GetFlagStatus(void); +void WDG_ClearFlag(void); +ITStatus WDG_GetITStatus(void); +void WDG_ClearITPendingBit(void); + +#endif /* __WDG_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/include/91x_wiu.h b/uc_str912/prj_template91x/str91x_lib/include/91x_wiu.h new file mode 100644 index 0000000..8b0349c --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/include/91x_wiu.h @@ -0,0 +1,99 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wiu.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* WIU software library. +********************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_WIU_H +#define __91x_WIU_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* WIU Init structure type define */ +typedef struct +{ + u8 WIU_Mode ; + u8 WIU_TriggerEdge; + u32 WIU_Line ; +}WIU_InitTypeDef ; + +/* Exported constants --------------------------------------------------------*/ +/* Wake-up line triggering edge */ +#define WIU_FallingEdge 0x00 +#define WIU_RisingEdge 0x01 + +/* Wake-up unit modes */ +#define WIU_Mode_WakeUp 0x01 +#define WIU_Mode_Interrupt 0x02 +#define WIU_Mode_WakeUpInterrupt 0x03 +#define WIU_Mode_SWInterrupt 0x04 + +/* Wake-up lines*/ +#define WIU_Line0 0x0001 +#define WIU_Line1 (WIU_Line0<<1) +#define WIU_Line2 (WIU_Line1<<1) +#define WIU_Line3 (WIU_Line2<<1) +#define WIU_Line4 (WIU_Line3<<1) +#define WIU_Line5 (WIU_Line4<<1) +#define WIU_Line6 (WIU_Line5<<1) +#define WIU_Line7 (WIU_Line6<<1) +#define WIU_Line8 (WIU_Line7<<1) +#define WIU_Line9 (WIU_Line8<<1) +#define WIU_Line10 (WIU_Line9<<1) +#define WIU_Line11 (WIU_Line10<<1) +#define WIU_Line12 (WIU_Line11<<1) +#define WIU_Line13 (WIU_Line12<<1) +#define WIU_Line14 (WIU_Line13<<1) +#define WIU_Line15 (WIU_Line14<<1) +#define WIU_Line16 (WIU_Line15<<1) +#define WIU_Line17 (WIU_Line16<<1) +#define WIU_Line18 (WIU_Line17<<1) +#define WIU_Line19 (WIU_Line18<<1) +#define WIU_Line20 (WIU_Line19<<1) +#define WIU_Line21 (WIU_Line20<<1) +#define WIU_Line22 (WIU_Line21<<1) +#define WIU_Line23 (WIU_Line22<<1) +#define WIU_Line24 (WIU_Line23<<1) +#define WIU_Line25 (WIU_Line24<<1) +#define WIU_Line26 (WIU_Line25<<1) +#define WIU_Line27 (WIU_Line26<<1) +#define WIU_Line28 (WIU_Line27<<1) +#define WIU_Line29 (WIU_Line28<<1) +#define WIU_Line30 (WIU_Line29<<1) +#define WIU_Line31 (WIU_Line30<<1) + +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void WIU_DeInit(void); +void WIU_StructInit(WIU_InitTypeDef* WIU_InitStruct); +void WIU_Init(WIU_InitTypeDef* WIU_InitStruct); +void WIU_GenerateSWInterrupt(u32 WIU_Line); +FlagStatus WIU_GetFlagStatus(u32 WIU_Line); +void WIU_ClearFlag(u32 WIU_Line); +ITStatus WIU_GetITStatus(u32 WIU_Line); +void WIU_ClearITPendingBit(u32 WIU_Line); + +#endif /* __91x_WIU_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_adc.c b/uc_str912/prj_template91x/str91x_lib/src/91x_adc.c new file mode 100644 index 0000000..a6a07d3 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_adc.c @@ -0,0 +1,590 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_adc.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the ADC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_adc.h" +#include "91x_scu.h" +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ADC mask */ +#define ADC_FLAG_MASK 0x001F /* ADC Flag Mask */ +#define ADC_RESULT_MASK 0x03FF /* ADC Result Mask */ +#define ADC_SCAN_MODE_MASK 0x0020 /* ADC Sacn Mode Mask */ +#define ADC_STANDBY_MODE_MASK 0x0008 /* ADC Standby Mode Mask */ +#define ADC_CMD_MASK 0x0002 /* ADC Command Mask */ +#define ADC_CHANNEL_MASK 0xFE3F /* ADC Channel Select Mask */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : ADC_DeInit +* Description : Deinitialize the ADC module registers to their default reset +* values +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_DeInit(void) +{ + /* Reset the ADC registers values */ + SCU_APBPeriphReset(__ADC,ENABLE); + SCU_APBPeriphReset(__ADC,DISABLE); +} + +/******************************************************************************* +* Function Name : ADC_Init +* Description : Initializes ADC peripheral according to the specified +* parameters in the ADC_InitTypeDef structure. +* Input : ADC_InitStruct: pointer to a ADC_InitTypeDef structure that +* contains the configuration information for the specified +* ADC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Init(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Set the low threshold of the watchdog */ + ADC->LTR = ADC_InitStruct->ADC_WDG_Low_Threshold; + + /* Set the high threshold of the watchdog */ + ADC->HTR = ADC_InitStruct->ADC_WDG_High_Threshold; + + + /* Channel 0 conversion mode */ + ADC->CCR &= 0xFFFC; + ADC->CCR |= ADC_InitStruct->ADC_Channel_0_Mode; + + /* Channel 1 conversion mode */ + ADC->CCR &= 0xFFF3; + ADC->CCR |= ADC_InitStruct->ADC_Channel_1_Mode << 0x2; + + /* Channel 2 conversion mode */ + ADC->CCR &= 0xFFCF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_2_Mode << 0x4; + + /* Channel 3 conversion mode */ + ADC->CCR &= 0xFF3F; + ADC->CCR |= ADC_InitStruct->ADC_Channel_3_Mode << 0x6; + + /* Channel 4 conversion mode */ + ADC->CCR &= 0xFCFF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_4_Mode << 0x8; + + /* Channel 5 conversion mode */ + ADC->CCR &= 0xF3FF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_5_Mode << 0xA; + + /* Channel 6 conversion mode */ + ADC->CCR &= 0xCFFF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_6_Mode << 0xC; + + /* Channel 7 conversion mode */ + ADC->CCR &= 0x3FFF; + ADC->CCR |= ADC_InitStruct->ADC_Channel_7_Mode << 0xE; + + /* Select the channel to be converted */ + ADC->CR &= ADC_CHANNEL_MASK; + ADC->CR |= ADC_InitStruct->ADC_Select_Channel << 0x6; + + /* Enable/disable the scan mode */ + if (ADC_InitStruct->ADC_Scan_Mode == ENABLE) + { + /* Enable the scan mode */ + ADC->CR |= ADC_SCAN_MODE_MASK; + } + else + { + /* Disable the scan mode */ + ADC->CR &= ~ADC_SCAN_MODE_MASK; + } + + /* Configure the conversion mode */ + if (ADC_InitStruct->ADC_Conversion_Mode == ADC_Continuous_Mode) + { + /* ADC continuous mode */ + ADC->CR |= ADC_Continuous_Mode; + } + else + { + /* ADC single mode */ + ADC->CR &= ADC_Single_Mode; + } +} + +/******************************************************************************* +* Function Name : ADC_StructInit +* Description : Fills each ADC_InitStruct member with its reset value. +* Input : ADC_InitStruct : pointer to a ADC_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + ADC_InitStruct->ADC_WDG_High_Threshold = 0x0000; + ADC_InitStruct->ADC_WDG_Low_Threshold = 0x0000; + ADC_InitStruct->ADC_Channel_0_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_1_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_2_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_3_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_4_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_5_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_6_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Channel_7_Mode = ADC_No_Conversion; + ADC_InitStruct->ADC_Select_Channel = ADC_Channel_0; + ADC_InitStruct->ADC_Scan_Mode = DISABLE; + ADC_InitStruct->ADC_Conversion_Mode = ADC_Single_Mode; +} + +/******************************************************************************* +* Function Name : ADC_PrescalerConfig +* Description : This routine is used to configure the ADC prescaler value. +* Input : ADC_Prescaler: specifies the prescaler value. This parameter +* can be a value from 0x0 to 0xFF. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_PrescalerConfig(u8 ADC_Prescaler) +{ + ADC->PRS &= 0xFF00; + ADC->PRS |= ADC_Prescaler; + +} +/******************************************************************************* +* Function Name : ADC_GetPrescalerValue +* Description : This routine is used to get the ADC prescaler value. +* Input : None +* Output : None +* Return : The prescaler value. +*******************************************************************************/ +u8 ADC_GetPrescalerValue(void) +{ + return ADC->PRS & 0x00FF; +} +/******************************************************************************* +* Function Name : ADC_GetFlagStatus +* Description : Checks whether the specified ADC flag is set or not. +* Input : ADC_Flag: flag to check. +* This parameter can be one of the following values: +* - ADC_FLAG_OV_CH_0: Conversion overflow status for +* channel 0. +* - ADC_FLAG_OV_CH_1: Conversion overflow status for +* channel 1. +* - ADC_FLAG_OV_CH_2: Conversion overflow status for +* channel 2. +* - ADC_FLAG_OV_CH_3: Conversion overflow status for +* channel 3. +* - ADC_FLAG_OV_CH_4: Conversion overflow status for +* channel 4. +* - ADC_FLAG_OV_CH_5: Conversion overflow status for +* channel 5. +* - ADC_FLAG_OV_CH_6: Conversion overflow status for +* channel 6. +* - ADC_FLAG_OV_CH_7: Conversion overflow status for +* channel 7. +* - ADC_FLAG_ECV: End of conversion status. +* - ADC_FLAG_AWD: Analog watchdog status. +* Output : None +* Return : The NewState of the ADC_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetFlagStatus(u16 ADC_Flag) +{ + u8 AdcReg = 0, FlagPos = 0; + + /* Get the ADC register index */ + AdcReg = ADC_Flag >> 5; + + /* Get the flag position */ + FlagPos = ADC_Flag & ADC_FLAG_MASK; + + if(AdcReg == 1) /* The flag to check is in CR register */ + { + if((ADC->CR & (1<DR0 & (1<DR1 & (1<DR2 & (1<DR3 & (1<DR4 & (1<DR5 & (1<DR6 & (1<DR7 & (1<CR |= (1<<(ADC_Flag & ADC_FLAG_MASK)); +} + +/******************************************************************************* +* Function Name : ADC_GetConversionValue +* Description : Read the result of conversion from the appropriate data +* register. +* Input : ADC_Channel: the correspondent channel of the ADC peripheral. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC channel 0. +* - ADC_Channel_1: ADC channel 1. +* - ADC_Channel_2: ADC channel 2. +* - ADC_Channel_3: ADC channel 3. +* - ADC_Channel_4: ADC channel 4. +* - ADC_Channel_5: ADC channel 5. +* - ADC_Channel_6: ADC channel 6. +* - ADC_Channel_7: ADC channel 7. +* Output : None +* Return : The result of the conversion for the specific channel. +*******************************************************************************/ +u16 ADC_GetConversionValue(u16 ADC_Channel) +{ + u16 ADC_Conversion_Value = 0; + + switch (ADC_Channel) + { + case (ADC_Channel_0): + /* Get the conversion value of the channel 0 */ + ADC_Conversion_Value = ADC->DR0 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_1): + /* Get the conversion value of the channel 1 */ + ADC_Conversion_Value = ADC->DR1 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_2): + /* Get the conversion value of the channel 2 */ + ADC_Conversion_Value = ADC->DR2 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_3): + /* Get the conversion value of the channel 3 */ + ADC_Conversion_Value = ADC->DR3 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_4): + /* Get the conversion value of the channel 4 */ + ADC_Conversion_Value = ADC->DR4 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_5): + /* Get the conversion value of the channel 5 */ + ADC_Conversion_Value = ADC->DR5 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_6): + /* Get the conversion value of the channel 6 */ + ADC_Conversion_Value = ADC->DR6 & ADC_RESULT_MASK; + break; + + case (ADC_Channel_7): + /* Get the conversion value of the channel 7 */ + ADC_Conversion_Value = ADC->DR7 & ADC_RESULT_MASK; + break; + + default: + break; + } + + return(ADC_Conversion_Value); +} + +/******************************************************************************* +* Function Name : ADC_GetAnalogWatchdogResult +* Description : Return the result of the comparaison on the selected Analog +* Watchdog. +* Input : ADC_Channel: the correspondent channel of the ADC peripheral. +* This parameter can be one of the following values: +* - ADC_Channel_0: ADC channel 0. +* - ADC_Channel_1: ADC channel 1. +* - ADC_Channel_2: ADC channel 2. +* - ADC_Channel_3: ADC channel 3. +* - ADC_Channel_4: ADC channel 4. +* - ADC_Channel_5: ADC channel 5. +* - ADC_Channel_6: ADC channel 6. +* - ADC_Channel_7: ADC channel 7. +* Output : None +* Return : The state of the comparision (SET or RESET). +*******************************************************************************/ +FlagStatus ADC_GetAnalogWatchdogResult(u16 ADC_Channel) +{ + if (ADC->CRR & (1<CRR = 1<LTR; + break; + + case ADC_HighThreshold: + /* Get the high threshol of the watchdog */ + ADC_Threshold_Value = ADC->HTR; + break; + + default: + break; + } + + return(ADC_Threshold_Value); +} + +/******************************************************************************* +* Function Name : ADC_ITConfig +* Description : Enables or disables the specified ADC interrupts. +* Input : - ADC_IT: specifies the ADC interrupts sources to be enabled +* or disabled. +* This parameter can be one of the following values: +* - ADC_IT_EndOfConversion: End of conversion interrupt. +* - ADC_IT_AnalogWDG: Analog watchdog interrupt. +* - ADC_NewState: new state of the specified ADC interrupts. +* (ADC_Newstate can be ENABLE or DISABLE). +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ITConfig(u16 ADC_IT, FunctionalState ADC_NewState) +{ + if (ADC_NewState == ENABLE) + { + /* Enable the interrupt */ + ADC->CR |= ADC_IT; + } + else + { + /* Disable the interrupt */ + ADC->CR &= ~ADC_IT; + } +} + +/******************************************************************************* +* Function Name : ADC_StandbyModeCmd +* Description : Enable or disable the standby mode. +* Input : ADC_NewState: new state of the ADC standby mode. +* (ADC_Newstate can be ENABLE or DISABLE). +* Output : None +* Return : None +*******************************************************************************/ +void ADC_StandbyModeCmd(FunctionalState ADC_NewState) +{ + if (ADC_NewState == ENABLE) + { + /* Enable the standby mode */ + ADC->CR |= ADC_STANDBY_MODE_MASK; + } + else + { + /* Disable the standby mode */ + ADC->CR &= ~ADC_STANDBY_MODE_MASK; + } +} + +/******************************************************************************* +* Function Name : ADC_Cmd +* Description : Power on or put in reset mode the ADC peripheral. +* Input : ADC_NewState: new state of the ADC peripheral. +* (ADC_Newstate can be ENABLE or DISABLE). +* Output : None +* Return : None +*******************************************************************************/ +void ADC_Cmd(FunctionalState ADC_NewState) +{ + if (ADC_NewState == ENABLE) + { + /* Enable the ADC */ + ADC->CR |= ADC_CMD_MASK; + } + else + { + /* Disable the ADC */ + ADC->CR &= ~ADC_CMD_MASK; + } +} + +/******************************************************************************* +* Function Name : ADC_ConversionCmd +* Description : Start or stop the ADC conversion in the selected mode. +* Input : ADC_Conversion: the conversion command. +* This parameter can be one of the following values: +* - ADC_Conversion_Start: Start the conversion. +* - ADC_Conversion_Stop: Stop the Conversion. +* Output : None +* Return : None +*******************************************************************************/ +void ADC_ConversionCmd(u16 ADC_Conversion) +{ + if (ADC_Conversion == ADC_Conversion_Start) + { + /* Start the ADC conversion */ + ADC->CR |= ADC_Conversion_Start; + } + else + { + /* Stop the ADC conversion */ + ADC->CR &= ADC_Conversion_Stop; + } +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_ahbapb.c b/uc_str912/prj_template91x/str91x_lib/src/91x_ahbapb.c new file mode 100644 index 0000000..41489ac --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_ahbapb.c @@ -0,0 +1,177 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the AHBAPB software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_ahbapb.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#define AHBAPB_SplitCounter_Mask 0xFFE0FFFF +#define AHBAPB_SetTimeOut_Mask 0xFFFFFFE0 +#define AHBAPB_Address_Mask 0xFEFFFFFF +#define AHBAPB_FLAG_RW_Mask 0x01000000 +/******************************************************************************* +* Function Name : AHBAPB_DeInit +* Description : Deinitializes the AHBAPBx peripheral registers to their default +* reset values. +* Input : AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx) +{ + AHBAPBx->BCR = 0x00000000; + AHBAPBx->BSR = 0x00000000; +} +/******************************************************************************* +* Function Name : AHBAPB_Init +* Description : Initializes the AHBAPBx peripheral according to the specified +* parameters in the AHBAPB_InitStruct . +* Input :- AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* - AHBAPB_InitStruct: pointer to a AHBAPB_InitTypeDef structure that +* contains the configuration information for the specified AHBAPB +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + + if(AHBAPB_InitStruct->AHBAPB_Split == AHBAPB_Split_Enable) + { + /* Set SPLITEN bit;*/ + AHBAPBx->BCR |= AHBAPB_Split_Enable; + /*Split_CNT bits[20:16]*/ + AHBAPBx->BCR &= AHBAPB_SplitCounter_Mask; + AHBAPBx->BCR |= (AHBAPB_InitStruct->AHBAPB_SplitCounter)<<16; + } + else + { + /*/ Clear SPLITEN bit;*/ + AHBAPBx->BCR &= AHBAPB_Split_Disable; + } + /*APB Time out*/ + if(AHBAPB_InitStruct->AHBAPB_Error == AHBAPB_Error_Enable) + { + /* Set ERREN bit*/ + AHBAPBx->BCR |= AHBAPB_Error_Enable; + /*Time ouit counter*/ + AHBAPBx->BCR &= AHBAPB_SetTimeOut_Mask; + AHBAPBx->BCR |= AHBAPB_InitStruct->AHBAPB_SetTimeOut; + } + else + { + /* Clear ERREN bit*/ + AHBAPBx->BCR &= AHBAPB_Error_Disable; + } +} + +/******************************************************************************* +* Function Name : AHBAPB_StructInit +* Description : Initialize the AHBAPB Init Structure parameters +* Input : AHBAPB_InitStruct : pointer to a AHBAPB_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + /* Reset AHBAPB init structure parameters values */ + AHBAPB_InitStruct->AHBAPB_Split = AHBAPB_Split_Enable; + AHBAPB_InitStruct->AHBAPB_SplitCounter = 0xFF; + AHBAPB_InitStruct->AHBAPB_Error = AHBAPB_Error_Enable; + AHBAPB_InitStruct->AHBAPB_SetTimeOut = 0xFF; + +} + +/******************************************************************************* +* Function Name : AHBAPB_GetFlagStatus +* Description : Checks whether the specified AHBAPB flag is set or not. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* - AHBAPB_FLAG_RW : Access type flag +* Output : None +* Return : The new state of AHBAPB_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + if(AHBAPB_FLAG == AHBAPB_FLAG_RW) + { + if ((AHBAPBx->PAER & AHBAPB_FLAG_RW_Mask) == RESET) + { + return RESET; + } + else + { + return SET; + } + } + else + { + if ((AHBAPBx->BSR & AHBAPB_FLAG) == RESET) + { + return RESET; + } + else + { + return SET; + } + } +} +/******************************************************************************* +* Function Name : AHBAPB_ClearFlag +* Description : Clears the AHBAPBx flags. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: flags to clear. This parameter one of the +* following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + /* Clear the flag */ + AHBAPBx->BSR &= AHBAPB_FLAG; +} +/******************************************************************************* +* Function Name : AHBAPB_GetPeriphAddrError +* Description : Gets the AHBAPB error address peripherals. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* Output : None +* Return : The Peropheral address error +*******************************************************************************/ +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx) +{ + u32 AHBAPB_Address = 0x00000000; + + /*Return Oeripheral address without RW bit*/ + AHBAPB_Address = (AHBAPBx->PAER)& AHBAPB_Address_Mask; + return (AHBAPB_Address); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_can.c b/uc_str912/prj_template91x/str91x_lib/src/91x_can.c new file mode 100644 index 0000000..e560d03 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_can.c @@ -0,0 +1,768 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_can.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the CAN software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_can.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */ +/* Description : Form the Mask and Arbitration registers value to filter */ +/* a range of identifiers or a fixed identifier, for standard*/ +/* and extended IDs */ +/*----------------------------------------------------------------------------*/ +#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) +#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) + +#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) +#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) + +#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) +#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) + +#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) +#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) + +#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) +#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) +#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) + +#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) +#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) +#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) +#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) + +/* macro to format the timing register value from the timing parameters*/ +#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F)) + +/* Private variables ---------------------------------------------------------*/ +/* array of pre-defined timing parameters for standard bitrates*/ +u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ + CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ + CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ + CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ + CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ + CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ +}; + +/* Private function prototypes -----------------------------------------------*/ +static u32 GetFreeIF(void); +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_DeInit (void) +{ + /* Reset the CAN registers values*/ + + SCU_APBPeriphReset(__CAN,ENABLE); /*CAN peripheral is under Reset */ + SCU_APBPeriphReset(__CAN,DISABLE); /*CAN peripheral Reset off*/ + + +} + +/******************************************************************************* +* Function Name : CAN_Init +* Description : Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +* contains the configuration information for the CAN peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_Init(CAN_InitTypeDef* CAN_InitStruct) +{ + CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters); + CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate); + CAN_LeaveInitMode(); + CAN_LeaveTestMode(); +} + +/******************************************************************************* +* Function Name : CAN_StructInit +* Description : Fills each CAN_InitStruct member with its reset value. +* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ +/* Reset CAN init structure parameters values */ + CAN_InitStruct->CAN_ConfigParameters = 0x0; + CAN_InitStruct->CAN_Bitrate = 0x2301; +} + +/******************************************************************************* +* Function Name : CAN_SetBitrate +* Description : Setups a standard CAN bitrate. +* Input : bitrate: specifies the bit rate. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetBitrate(u32 bitrate) +{ + CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */ + CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */ +} + +/******************************************************************************* +* Function Name : CAN_SetTiming +* Description : Setups the CAN timing with specific parameters +* Input : - tseg1: specifies Time Segment before the sample point. +* This parameter must be a number between 1 and 16. +* - tseg2: Time Segment after the sample point. This parameter +* must be a number between 1 and 8. +* - sjw: Synchronisation Jump Width. This parameter must be +* a number between 1 and 4. +* - brp: Baud Rate Prescaler. This parameter must be a number +* between 1 and 1024. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) +{ + CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); + CAN->BRPR = ((brp-1) >> 6) & 0x0F; +} + +/******************************************************************************* +* Function Name : GetFreeIF +* Description : Searchs the first free message interface, starting from 0. +* Input : None +* Output : None +* Return : A free message interface number (0 or 1) if found, else 2 +*******************************************************************************/ +static u32 GetFreeIF(void) +{ + if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) + return 0; + else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) + return 1; + else + return 2; +} + +/******************************************************************************* +* Function Name : CAN_SetUnusedMsgObj +* Description : Configures the message object as unused +* Input : msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = 0; + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = 0; + + CAN->sMsgObj[msg_if].MCR = 0; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetTxMsgObj +* Description : Configures the message object as TX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].A1R = 0; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; + } + else + { + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SetRxMsgObj +* Description : Configures the message object as RX. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - idType: specifies the identifier type of the frames that +* will be transmitted using this message object. +* This parameter can be one of the following values: +* - CAN_STD_ID (standard ID, 11-bit) +* - CAN_EXT_ID (extended ID, 29-bit) +* - idLow: specifies the low part of the identifier range used +* for acceptance filtering. +* - idHigh: specifies the high part of the identifier range +* used for acceptance filtering. +* - singleOrFifoLast: specifies the end-of-buffer indicator. +* This parameter can be one of the following values: +* - TRUE: for a single receive object or a FIFO receive +* object that is the last one of the FIFO. +* - FALSE: for a FIFO receive object that is not the +* last one. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD + | CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (idType == CAN_STD_ID) + { + CAN->sMsgObj[msg_if].M1R = 0; + CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = 0; + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); + } + else + { + CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); + CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); + + CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); + CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); + } + + CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); + + CAN->sMsgObj[msg_if].DA1R = 0; + CAN->sMsgObj[msg_if].DA2R = 0; + CAN->sMsgObj[msg_if].DB1R = 0; + CAN->sMsgObj[msg_if].DB2R = 0; + + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_InvalidateAllMsgObj +* Description : Configures all the message objects as unused. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_InvalidateAllMsgObj(void) +{ + u32 i=0; + for (i = 0; i < 32; i++) + CAN_SetUnusedMsgObj(i); +} + + +/******************************************************************************* +* Function Name : CAN_ReleaseMessage +* Description : Releases the message object +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Interface to treat the message +* - ERROR: No interface to treat the message +*******************************************************************************/ +ErrorStatus CAN_ReleaseMessage(u32 msgobj) +{ + u32 msg_if=0; + + if ((msg_if = GetFreeIF()) == 2) + { + return ERROR; + } + + CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[msg_if].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_SendMessage +* Description : Start transmission of a message +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* : - pCanMsg: pointer to the message structure containing data +* to transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) +{ + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_TXOK; + + /* read the Arbitration and Message Control*/ + CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + /* update the contents needed for transmission*/ + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + CAN->sMsgObj[0].CRR = 1 + msgobj; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_ReceiveMessage +* Description : Gets the message, if received. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* - release: specifies the message release indicator. +* This parameter can be one of the following values: +* - TRUE: the message object is released when getting +* the data. +* - FALSE: the message object is not released. +* - pCanMsg: pointer to the message structure where received +* data is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) +{ + if (!CAN_IsMessageWaiting(msgobj)) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + /* read the message contents*/ + CAN->sMsgObj[1].CMR = CAN_CMR_MASK + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_CLRINTPND + | (release ? CAN_CMR_TXRQSTNEWDAT : 0) + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + CAN->sMsgObj[1].CRR = 1 + msgobj; + + if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) + { + return ERROR; + } + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_WaitEndOfTx +* Description : Waits until current transmission is finished. +* Input : None +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission ended +* - ERROR: Transmission did not occur yet +*******************************************************************************/ +ErrorStatus CAN_WaitEndOfTx(void) +{ + if ((CAN->SR & CAN_SR_TXOK) == 0) + { + return ERROR; + } + CAN->SR &= ~CAN_SR_TXOK; + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicSendMessage +* Description : Starts transmission of a message in BASIC mode. This mode +* does not use the message RAM. +* Input : pCanMsg: Pointer to the message structure containing data to +* transmit. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Transmission OK +* - ERROR: No transmission +*******************************************************************************/ +ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg) +{ + /* clear NewDat bit in IF2 to detect next reception*/ + CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; + + CAN->SR &= ~CAN_SR_TXOK; + CAN->sMsgObj[0].CMR = CAN_CMR_WRRD + | CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if (pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + CAN->sMsgObj[0].A1R = 0; + CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); + } + else + { + /* extended ID*/ + CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); + CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); + } + + CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; + + CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; + CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; + CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; + CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; + + /* request transmission*/ + if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY ) + { + return ERROR; + } + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_BasicReceiveMessage +* Description : Gets the message in BASIC mode, if received. This mode does +* not use the message RAM. +* Input : pCanMsg: pointer to the message structure where message is copied. +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Reception OK +* - ERROR: No message pending +*******************************************************************************/ +ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg) +{ + if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) + { + return ERROR; + } + + CAN->SR &= ~CAN_SR_RXOK; + + CAN->sMsgObj[1].CMR = CAN_CMR_ARB + | CAN_CMR_CONTROL + | CAN_CMR_DATAA + | CAN_CMR_DATAB; + + if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF); + pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11); + pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); + } + + pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; + + pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; + pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); + pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; + pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); + pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; + pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); + pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; + pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); + + return SUCCESS; +} + +/******************************************************************************* +* Function Name : CAN_EnterInitMode +* Description : Switchs the CAN into initialization mode. This function must +* be used in conjunction with CAN_LeaveInitMode(). +* Input : InitMask: specifies the CAN configuration in normal mode. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterInitMode(u8 InitMask) +{ + CAN->CR = InitMask | CAN_CR_INIT; + CAN->SR = 0; /* reset the status*/ +} + +/******************************************************************************* +* Function Name : CAN_LeaveInitMode +* Description : Leaves the initialization mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterInitMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveInitMode(void) +{ + CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); +} + +/******************************************************************************* +* Function Name : CAN_EnterTestMode +* Description : Switchs the CAN into test mode. This function must be used in +* conjunction with CAN_LeaveTestMode(). +* Input : TestMask: specifies the configuration in test modes. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_EnterTestMode(u8 TestMask) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR |= TestMask; +} + +/******************************************************************************* +* Function Name : CAN_LeaveTestMode +* Description : Leaves the current test mode (switch into normal mode). +* This function must be used in conjunction with CAN_EnterTestMode(). +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_LeaveTestMode(void) +{ + CAN->CR |= CAN_CR_TEST; + CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); + CAN->CR &= ~CAN_CR_TEST; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseTxMessage +* Description : Releases the transmit message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseTxMessage(u32 msgobj) +{ + CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[0].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_ReleaseRxMessage +* Description : Releases the receive message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : None +*******************************************************************************/ +void CAN_ReleaseRxMessage(u32 msgobj) +{ + CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT; + CAN->sMsgObj[1].CRR = 1 + msgobj; +} + +/******************************************************************************* +* Function Name : CAN_IsMessageWaiting +* Description : Tests the waiting status of a received message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object has +* received a message waiting to be copied, else 0. +*******************************************************************************/ +u32 CAN_IsMessageWaiting(u32 msgobj) +{ + return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsTransmitRequested +* Description : Tests the request status of a transmitted message. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message is requested +* to transmit, else 0. +*******************************************************************************/ +u32 CAN_IsTransmitRequested(u32 msgobj) +{ + return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsInterruptPending +* Description : Tests the interrupt status of a message object. +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message has an +* interrupt pending, else 0. +*******************************************************************************/ +u32 CAN_IsInterruptPending(u32 msgobj) +{ + return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); +} + +/******************************************************************************* +* Function Name : CAN_IsObjectValid +* Description : Tests the validity of a message object (ready to use). +* Input : - msgobj: specifies the Message object number, from 0 to 31. +* Output : None +* Return : A non-zero value if the corresponding message object is +* valid, else 0. +*******************************************************************************/ +u32 CAN_IsObjectValid(u32 msgobj) +{ + return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_dma.c b/uc_str912/prj_template91x/str91x_lib/src/91x_dma.c new file mode 100644 index 0000000..db6ad6e --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_dma.c @@ -0,0 +1,1125 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_dma.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the DMA software functions +* needed to access all DMA registers. +******************************************************************************** +* History:v 1.0 +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ + +# include"91x_dma.h" +# include"91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + + +/* DMA Masks "used" only in this module */ + +#define DMA_Width_DES_MASK 0xFF1FFFFF +#define DMA_Width_SRC_MASK 0xFFE3FFFF +#define DMA_Bst_DES_MASK 0xFFFC7FFF +#define DMA_Bst_SRC_MASK 0xFFFF8FFF +#define DMA_FlowCntrl_Mask 0xFFFFC7FF +#define DMA_TrsfSisze_Mask 0xFFFFF000 +#define SRC_Mask 0xFFFFFFE1 +#define DES_Mask 0xFFFFFC3F +#define DMA_TCIE 0x80000000 +#define DMA_ChannelDESInc 0x08000000 +#define DMA_ChannelSRCInc 0x04000000 +#define DMA_BufferChannel 0x20000000 +#define DMA_HaltChannel 0x00040000 +#define DMA_LockChannel 0x00010000 +#define DMA_CacheChannel 0x40000000 +#define DMA_ChannelActive 0x00020000 +#define DMA_Enable 0x00000001 +#define DMA_ChannelEnable 0x00000001 + + + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : DMA_ITMaskConfig +* Description : Enables or disables the specified DMA_Channelx Mask interrupt. +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -DMA_ITMask: specifies the DMA interrupt mask source to be enabled or disabled. +* This parameter can be: +* - DMA_ITMask_IE (Interrupt error mask). +* - DMA_ITMask_ITC (Terminal count interrupt mask). +* - DMA_ITMask_ALL ( All interrupts mask) +* +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask , FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Mask the Interrupt */ + { + DMA_Channelx-> CCNF |= DMA_ITMask ; + } + + else /* Disable the Interrupt Mask*/ + { + DMA_Channelx-> CCNF &= ~ DMA_ITMask ; + } +} + + + + + +/******************************************************************************* +* Function Name : DMA_ITConfig +* Description : Enables or disables the DMA_Channelx Terminal Count interrupt. +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enable the Terminal Count Interrupt */ + { + DMA_Channelx->CC |= DMA_TCIE ; + } + + else /* Disable the Terminal Count Interrupt */ + { + DMA_Channelx-> CC &= ~ DMA_TCIE ; + } +} + + +/******************************************************************************** +* Function Name : DMA_SyncConfig +* Description : Enables or disables synchronization logic for the corresponding DMA Request Signal. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SyncConfig(u16 SRCReq, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enable the synchronization logic for the corresponding DMA Request Signal */ + { + + DMA->SYNR &= ~ SRCReq ; + + } + + else /* Disable the synchronization logic for the corresponding DMA Request Signal. */ + { + DMA->SYNR |= SRCReq ; + + } +} + + +/******************************************************************************** +* Function Name : DMA_SetSReq +* Description : Set the DMA to generate a Single transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SetSReq(u16 SRCReq) + +{ /* Set the DMA to generate a Single transfer request for the corresponding DMA Request Source */ + DMA->SSRR |= SRCReq ; +} + + + + +/******************************************************************************** +* Function Name : DMA_SetLSReq +* Description : Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : None. +*******************************************************************************/ + +void DMA_SetLSReq(u16 SRCReq ) +{ /* Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source */ + DMA->SLSRR |= SRCReq ; +} + + +/******************************************************************************** +* Function Name : DMA_SetBReq +* Description : Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SetBReq(u16 SRCReq) + +{ /* Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source */ + DMA->SBRR |= SRCReq ; +} + + + +/******************************************************************************** +* Function Name : DMA_SetLBReq +* Description : Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source. +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_SetLBReq(u16 SRCReq) + +{ /* Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source */ + DMA->SLBRR |= SRCReq ; +} + + +/******************************************************************************** +* Function Name : DMA_GetSReq +* Description : Check for a specific source if it request a Single transfer . +* Input : +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetSReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Single transfer . */ + if ( (DMA->SSRR & SRCReq )!= RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + + +/******************************************************************************** +* Function Name : DMA_GetLSReq +* Description : Check for a specific source if it request a Last Single transfer . +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetLSReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Last Single transfer . */ + if ( (DMA->SLSRR & SRCReq)!= RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + +/******************************************************************************** +* Function Name : DMA_GetBReq +* Description : Check for a specific source if it request a Burst transfer . +* Input : +* -SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetBReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Burst transfer . */ + if (( DMA->SBRR & SRCReq ) != RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + +/******************************************************************************** +* Function Name : DMA_GetLSReq +* Description : Check for a specific source if it request a Last Burst transfer . +* Input : +* Input : +* - SRCReq:specifies the DMA Request Source. +* This parameter can be: +* -DMA_USB_RX_Mask +* -DMA_USB_TX_Mask +* -DMA_TIM0_Mask +* -DMA_TIM1_Mask +* -DMA_UART0_RX_Mask +* -DMA_UART0_TX_Mask +* -DMA_UART1_RX_Mask +* -DMA_UART1_TX_Mask +* -DMA_External_Req0_Mask +* -DMA_External_Req1_Mask +* -DMA_I2C0_Mask +* -DMA_I2C1_Mask +* -DMA_SSP0_RX_Mask +* -DMA_SSP0_TX_Mask +* -DMA_SSP1_RX_Mask +* -DMA_SSP1_TX_Mask +* Output : None. +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetLBReq(u16 SRCReq) + +{ /* Check for a specific source if it request a Last Burst transfer . */ + if ( ( DMA->SLBRR & SRCReq ) != RESET ) + { + return SET; + } + + else + { + return RESET; + } +} + + + +/******************************************************************************* +* Function Name : DMA_ChannelHalt +* Description : Enables DMA requests or ignore extra source DMA requests for + the specified channel. +* Input : + -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. + -NewState: new state of the specified DMA_Channelx mask interrupt. + This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelHalt(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enables DMA requests */ + + { + DMA_Channelx->CCNF |= DMA_HaltChannel ; + } + + else /* Ignore extra source DMA request */ + { + DMA_Channelx->CCNF &= ~ DMA_HaltChannel ; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelLockTrsf +* Description : Enables or disables the Locked Transfers Feature for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Locked transfers enabled on channel x */ + + { + DMA_Channelx->CCNF |= DMA_LockChannel ; + } + + else /* Locked transfers disabled on channel xt */ + { + DMA_Channelx->CCNF &= ~ DMA_LockChannel; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelCache +* Description : Enables or disables the cacheability Feature for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelCache (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Cacheability Feature enabled on channelx */ + + { + DMA_Channelx->CC |= DMA_CacheChannel ; + } + + else /* Cacheability Feature disabled on channelx */ + { + DMA_Channelx->CC &= ~ DMA_CacheChannel ; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelBuffering +* Description : Enables or disables the Buffering Feature for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Cacheability Feature enabled on channel x */ + + { + DMA_Channelx->CC |= DMA_BufferChannel ; + } + + else /* Cacheability Feature disabled on channel xt */ + { + DMA_Channelx->CC &= ~ DMA_BufferChannel ; + } +} + +/******************************************************************************* +* Function Name : MA_ChannelProt0Mod +* Description : Sets The User or Privileged mode for the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -Prot0Mode: Specifies the Privileged mode Or the User mode. +* This parameter can be: +* - DMA_PrevilegedMode +* - DMA_UserMode +* +* +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelProt0Mode (DMA_Channel_TypeDef * DMA_Channelx, u32 Prot0Mode) + +{ + if (Prot0Mode==DMA_PrevilegedMode) /* Privileged mode */ + { + DMA_Channelx->CC |= DMA_PrevilegedMode ; + } + + else /* User mode */ + { + DMA_Channelx->CC &= DMA_UserMode ; + } +} + + + + + +/******************************************************************************* +* Function Name : DMA_ChannelSRCIncConfig +* Description : Enables or disables the Source address incrementation after each transfer for +* the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* The Source address is incremented after each transfer */ + + { + DMA_Channelx->CC |= DMA_ChannelSRCInc ; + } + + else /* The Source address is not incremented after each Transfer */ + { + DMA_Channelx->CC &= ~ DMA_ChannelSRCInc ; + } +} + + +/******************************************************************************* +* Function Name : DMA_ChannelDESIncConfig +* Description : Enables or disables the Destination address incrementation after each transfer for +* the specified DMA_Channelx +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) + +{ + if (NewState==ENABLE) /* The Destination address is incremented after each transfer */ + + { + DMA_Channelx->CC |= DMA_ChannelDESInc ; + } + + else /* The Destination address is not incremented after each Transfer */ + { + DMA_Channelx->CC &= ~ DMA_ChannelDESInc ; + } +} + + + +/******************************************************************************** +* Function Name : DMA_GetChannelStatus +* Description : Checks the status of DMA channelx ( Enabled or Disabled). +* - ChannelIndx:specifies the DMA Channel to be checked. +* This parameter can be: +* - Channel0 +* - Channel1 +* - Channel2 +* - Channel3 +* - Channel4 +* - Channel5 +* - Channel6 +* - Channel7 +* Output : None. +* +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ) + +{ + + if ( ( DMA->ENCSR & (1 << ChannelIndx )) != RESET ) + { + return SET; /* Channelx Enabled */ + } + + else + + { + + return RESET; /* Channelx Disabled */ + + } + +} + + + +/******************************************************************************** +* Function Name : DMA_GetITStatus +* Description : Checks the status of Terminal Count and Error interrupts request after and before Masking. +* Input : +* - ChannelIndx:specifies the DMA Channel to be checked. +* This parameter can be: +* - Channel0 +* - Channel1 +* - Channel2 +* - Channel3 +* - Channel4 +* - Channel5 +* - Channel6 +* - Channel7 +* +*. - DMA_ITReq: specifies the DMA interrupt request status to be checked. +* This parameter can be: +* +* - DMA_IS +* - DMA_TCS +* - DMA_ES +* - DMA_TCRS +* - DMA_ERS. +* +* Output : None. +* +* Return : SET or RESET. +*******************************************************************************/ + + +ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq) + +{ + u32 DMAReg = 0; + + switch(DMA_ITReq) + + { + + case (DMA_IS): /*The status of the interrupts after masking : logical or of all Interrupts after Masking*/ + DMAReg = DMA->ISR; + break; + + + + case (DMA_TCS): /* The status of the Terminal count request after masking */ + DMAReg = DMA->TCISR; + break; + + + case (DMA_ES): /* The status of the error request after masking */ + DMAReg = DMA->EISR; + break; + + + case (DMA_TCRS): /* Indicates if the DMA channel is requesting a transfer complete (terminal count Interrupt) prior to masking or Not. */ + DMAReg = DMA->TCRISR; + break; + + case (DMA_ERS): /* Indicates if the DMA channel is requesting an Error Interrupt prior to masking or Not. */ + DMAReg = DMA->ERISR; + break; + + + } + + if((DMAReg &(1 << ChannelIndx )) != RESET ) + + { + return SET; + } + + else + + { + + return RESET; + + + } + +} + + +/******************************************************************************** +* Function Name : DMA_ClearIT +* Description : Clears The Interrupt pending bits for termnal count or Error interrupts for a specified DMA Channel. +* - ChannelIndx:specifies the DMA Channel to be checked. +* This parameter can be: +* - Channel0 +* - Channel1 +* - Channel2 +* - Channel3 +* - Channel4 +* - Channel5 +* - Channel6 +* - Channel7 +* - DMA_ITClr : Specifies the DMA interrupt pending to be cleared. +*. This parameter can be: +* - DMA_TCC +* - DMA_EC. +* +* Output : None. + +* Return : SET or RESET. +*******************************************************************************/ + + +void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr) + +{ + + + switch(DMA_ITClr) + + { + + case (DMA_TCC): /* Clear The status of the Terminal count interrupt on the corresponding channel.*/ + DMA->TCICR |=(1 << ChannelIndx ); + break; + + + + case (DMA_EC): /* Clear The status of the error interrupt on the corresponding channel.*/ + DMA->EICR |=(1 << ChannelIndx ); + break; + + + + } + + + +} + + +/******************************************************************************* +* Function Name : DMA_Cmd(FunctionalState NewState) +* Description : Enables or disables the DMA peripheral. +* +* Input : +* -NewState: new state of the DMA. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_Cmd(FunctionalState NewState) + +{ + if (NewState==ENABLE) /* ENABLE the DMA peripheral */ + + { + DMA-> CNFR |= DMA_Enable ; + } + + else /* DISABLE the DMA peripheral */ + { + DMA-> CNFR &= ~ DMA_Enable ; + } +} + + + +/******************************************************************************* +* Function Name : DMA_ChannelCmd +* Description : Enables or disables the specified DMA_Channelx +* +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -NewState: new state of the specified DMA_Channelx mask interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None. +* Return : None. +*******************************************************************************/ + + +void DMA_ChannelCmd (DMA_Channel_TypeDef *DMA_Channelx,FunctionalState NewState) + +{ + if (NewState==ENABLE) /* Enable The Channelx */ + + { + DMA_Channelx->CCNF |= DMA_ChannelEnable ; + } + + else /* Disable The Channelx */ + { + DMA_Channelx-> CCNF &= ~ DMA_ChannelEnable ; + } +} + + + +/******************************************************************************** +* Function Name : DMA_GetChannelActiveStatus +* Description : Checks The DMA_Channelx FIFO if it has data or not. +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* +* +* Output : None. +* +* Return : SET or RESET. +*******************************************************************************/ + + +FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx ) + +{ + + if ( ( DMA_Channelx->CCNF & DMA_ChannelActive) != RESET ) + { + return SET; /* The DMA_Channelx FIFO has data */ + } + + else + + { + + return RESET; /* No data in the DMA_Channelx FIFO */ + + + } + +} + + +/******************************************************************************** +* Function Name : DMA_DeInit +* Description : Initializes the DMA peripheral registers to their default reset values. +* +* +* Input : None +* +* Output : None. +* +* Called Functions: +* +* - SCU_AHBPeriphReset: Function defined in the System clock Unit "scu.c". +* +* +* Return : None +*******************************************************************************/ + + +void DMA_DeInit(void) + +{ + + SCU_AHBPeriphReset(__DMA, ENABLE); /*DMA peripheral is under Reset " Reset on"*/ + SCU_AHBPeriphReset(__DMA, DISABLE); /*DMA peripheral Reset off*/ +} + + + +/******************************************************************************** +* Function Name : DMA_StructInit +* Description : Fills each DMA_InitStruct member with its reset value. +* Input : +* -DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized. +* +* Output : None. +* +* Return : None +*******************************************************************************/ + + +void DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct) + +{ + + /* Initialize The current source address */ + DMA_InitStruct-> DMA_Channel_SrcAdd =0x0000000; + + + /* Initialize The current Destination address */ + DMA_InitStruct->DMA_Channel_DesAdd=0x00000000; + + + + /* Initialize The Linked List Items */ + DMA_InitStruct->DMA_Channel_LLstItm=0x00000000 ; + + + + /* Initialize The Destination width */ + DMA_InitStruct->DMA_Channel_DesWidth= DMA_DesWidth_Byte; + + + + /* Initialize The source width */ + DMA_InitStruct->DMA_Channel_SrcWidth= DMA_SrcWidth_Byte; + + + /* Initialize The Burst Size for the Destination */ + DMA_InitStruct->DMA_Channel_DesBstSize= DMA_DesBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the Destination width */ + + + + /* Initialize The Burst Size for the Source*/ + DMA_InitStruct->DMA_Channel_SrcBstSize= DMA_SrcBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the source width */ + + /* Initialize The Flow control and transfer type for the DMA transfer */ + DMA_InitStruct->DMA_Channel_FlowCntrl=DMA_FlowCntrlt0_DMA; /* memory to memory transfer with DMA as flow controller */ + + + /* Initialize The Transfer Size */ + DMA_InitStruct->DMA_Channel_TrsfSize =0x00; + + + + /* Initialize the DMA source request peripheral :"This field is ignored if the source of the transfer is from memory" */ + DMA_InitStruct->DMA_Channel_Src =0x00; + + + + /* Initialize the DMA Destination request peripheral :"This field is ignored if the destination of the transfer is to memory.*/ + + DMA_InitStruct->DMA_Channel_Des=0x00; + + +} + + + + +/******************************************************************************** +* Function Name : DMA_Init +* Description : Initializes the DMA_Channelx according to the specified parameters +* in the DMA_InitStruct . +* +* Input : +* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. +* -DMA_InitStruct: pointer to a DMA_InitTypeDef structure +* ( Structure Config to be load in DMA Registers). . +* +* Output : None. +* +* Return : None +*******************************************************************************/ + + +void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct) + +{ + + + + /* Select the DMA source peripheral request */ + DMA_Channelx->CCNF &= SRC_Mask; + DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Src; + + + /* Select the flow controller and the transfer type */ + DMA_Channelx->CCNF &= DMA_FlowCntrl_Mask; + DMA_Channelx->CCNF |=DMA_InitStruct->DMA_Channel_FlowCntrl; + + + /* Select the DMA Destination peripheral request*/ + DMA_Channelx->CCNF &= DES_Mask; + DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Des; + + /* Set the source address */ + DMA_Channelx->SRC = DMA_InitStruct-> DMA_Channel_SrcAdd ; + + + /* Set the destination address */ + + DMA_Channelx->DES = DMA_InitStruct->DMA_Channel_DesAdd ; + + + + /* Set the linked list Items address */ + DMA_Channelx->LLI = DMA_InitStruct->DMA_Channel_LLstItm ; + + + /* Set The Destination width */ + DMA_Channelx->CC &= DMA_Width_DES_MASK; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesWidth; + + + /* Set The Source width */ + DMA_Channelx->CC &= DMA_Width_SRC_MASK; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_SrcWidth; + + /* Set The Burst Size for the Destination */ + DMA_Channelx->CC &= DMA_Bst_DES_MASK; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesBstSize; + + /* Set The Burst Size for the Source */ + DMA_Channelx->CC &= DMA_Bst_SRC_MASK; + DMA_Channelx->CC |=DMA_InitStruct->DMA_Channel_SrcBstSize; + + + /* Initialize The Transfer Size for the Source */ + DMA_Channelx->CC &= DMA_TrsfSisze_Mask; + DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_TrsfSize; + + +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_emi.c b/uc_str912/prj_template91x/str91x_lib/src/91x_emi.c new file mode 100644 index 0000000..deadae8 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_emi.c @@ -0,0 +1,167 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_emi.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the EMI software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_emi.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* These constant variables are used as masks to handle the EMI registers. */ + +#define EMI_PageModeRead_TL_Mask 0xFFFFF3FF +#define EMI_PageModeRead_Sel_Mask 0xFFFFFEFF +#define EMI_MemWidth_Mask 0xFFFFFFCF +#define EMI_WriteProtect_Mask 0xFFFFFEF7 + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : EMI_DeInit +* Description : Deinitializes the EMI peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ + +void EMI_DeInit(void) +{ + + SCU_AHBPeriphReset(__EMI, ENABLE); /* EMI peripheral under Reset */ + SCU_AHBPeriphReset(__EMI,DISABLE ); /* EMI not under Reset */ + +} + +/******************************************************************************* +* Function Name : EMI_StructInit +* Description : Fills the EMI_InitTypeDef structure member with its reset +* value. +* Input : EMI_InitStruct : pointer to a EMI_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ + +void EMI_StructInit( EMI_InitTypeDef *EMI_InitStruct) +{ + + /* Number of bus turnaround cycles added between read and write accesses.*/ + /*This member can be 0x01,0x02,0x03, ....0xF (Reset value:0xF "15 cycles"*/ + + EMI_InitStruct->EMI_Bank_IDCY =0xF; + + + /* Number of wait states for read accesses*/ + /*This member can be: 0x01,0x02,0x03, ....0x1F (Reset value:0x1F "31 cycles"*/ + + EMI_InitStruct->EMI_Bank_WSTRD =0x1F; + + + /* Number of wait states for write accesses*/ + /*This member can be: 0x01,0x02,0x03, ....0x1F (Reset value:0x1F "31 cycles"*/ + + EMI_InitStruct->EMI_Bank_WSTWR =0x1F; + + /*Output enable assertion delay from chip select assertion*/ + /*This member can be: 0x01,0x02,0x03, ....0xF (Reset value:0x01 "1 cycle"*/ + + EMI_InitStruct->EMI_Bank_WSTROEN =0x01; + + + /*Write enable assertion delay from chip select assertion*/ + /*This member can be: 0x01,0x02,0x03, ....0xF (Reset value:0x00 "0 cycle"*/ + + EMI_InitStruct->EMI_Bank_WSTWEN =0x00; + + + /*This member Controls the memory width*/ + /*This member can be :"EMI_Width_Byte" = 8 bits width or "EMI_Width_HalfWord" = 16 bits width*/ + + EMI_InitStruct->EMI_Bank_MemWidth = EMI_Width_Byte; + + + /*Write protection feature */ + /*This member can be :"EMI_Bank_NonWriteProtect" = No write protection or "EMI_Bank_WriteProtect" = bank is write protected*/ + + EMI_InitStruct-> EMI_Bank_WriteProtection= EMI_Bank_NonWriteProtect; + + + /* page transfer length for page mode read */ + /*This member can be :"EMI_4Data" = 4 transfers burst or "EMI_8Data" = 8 transfers burst*/ + + EMI_InitStruct->EMI_PageModeRead_TransferLength= EMI_4Data; + + /*Select or deselect the page mode read*/ + /*This member can be :"EMI_NormalMode" =Normal Mode or "EMI_PageModeRead" = Page Mode Read*/ + + EMI_InitStruct->EMI_PageModeRead_Selection = EMI_NormalMode; + + +} + +/******************************************************************************* +* Function Name : EMI_Init +* Description : Initializes EMI peripheral according to the specified +* parameters in the EMI_InitStruct. + +* Input : EMI_Bankx:where x can be 0,1,2 or 3 to select the EMI Bank. + EMI_InitStruct: pointer to a EMI_InitTypeDef structure + ( Structure Config to be loaded in EMI Registers). . + +* Output : None +* Return : None +*******************************************************************************/ + +void EMI_Init( EMI_Bank_TypeDef* EMI_Bankx, EMI_InitTypeDef* EMI_InitStruct) + +{ + + EMI_Bankx->ICR = EMI_InitStruct-> EMI_Bank_IDCY ; + + EMI_Bankx->RCR = EMI_InitStruct->EMI_Bank_WSTRD ; + + EMI_Bankx->WCR = EMI_InitStruct->EMI_Bank_WSTWR ; + + EMI_Bankx->OECR = EMI_InitStruct->EMI_Bank_WSTROEN; + + EMI_Bankx->WECR = EMI_InitStruct->EMI_Bank_WSTWEN ; + + EMI_Bankx->BCR &= EMI_MemWidth_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_Bank_MemWidth; + + EMI_Bankx->BCR &= EMI_WriteProtect_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_Bank_WriteProtection; + + EMI_Bankx->BCR &= EMI_PageModeRead_TL_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_PageModeRead_TransferLength; + + EMI_Bankx->BCR &= EMI_PageModeRead_Sel_Mask; + EMI_Bankx->BCR |= EMI_InitStruct->EMI_PageModeRead_Selection; + + +} + + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_fmi.c b/uc_str912/prj_template91x/str91x_lib/src/91x_fmi.c new file mode 100644 index 0000000..fb558ad --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_fmi.c @@ -0,0 +1,519 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the FMI software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_fmi.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define TIMEOUT 0xFFFFFF /* Timeout value */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/******************************************************************************* +* Function Name : FMI_BankRemapConfig +* Description : Configure the addresses and sizes of bank 0 and bank 1. +* Input1 : FMI_BootBankSize: specifies the boot bank size. +* This parameter can be one of the following values: +* - 0x0: 32KBytes. +* - 0x1: 64KBytes. +* - 0x2: 128KBytes. +* - 0x3: 256KBytes. +* - 0x4: 512KBytes. +* .... +* - 0xB: 64MBytes. +* Input2 : FMI_NonBootBankSize: specifies the non boot bank size. +* This parameter can be one of the following values: +* - 0x0: 8KBytes. +* - 0x1: 16KBytes. +* - 0x2: 32KBytes. +* - 0x3: 64KBytes. +* .... +* - 0xD: 64MBytes. +* Input3 : FMI_BootBankAddress: specifies the address of the boot bank. +* Input4 : FMI_NonBootBankAddress: specifies the address of the non +* boot bank. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress) +{ + FMI->BBSR = FMI_BootBankSize; + FMI->NBBSR = FMI_NonBootBankSize; + FMI->BBADR = (FMI_BootBankAddress >> 2); + FMI->NBBADR = (FMI_NonBootBankAddress >> 2); + FMI->CR |= 0x18; /* Enable bank 1 */ +} + +/******************************************************************************* +* Function Name : FMI_Config +* Description : Configure the FMI. +* Input1 : FMI_ReadWaitState: specifies the needed read wait states. +* This parameter can be one of the following values: +* - FMI_READ_WAIT_STATE_1: One read wait state. +* - FMI_READ_WAIT_STATE_2: Two read wait states. +* - FMI_READ_WAIT_STATE_3: Three read wait states. +* Input2 : FMI_WriteWaitState: specifies the needed write wait states. +* This parameter can be one of the following values: +* - FMI_WRITE_WAIT_STATE_1: One write wait state. +* - FMI_WRITE_WAIT_STATE_2: Two write wait states. +* Input3 : FMI_PWD: specifies the power down mode status. +* This parameter can be one of the following values: +* - FMI_PWD_ENABLE: Enable the PWD. +* - FMI_PWD_DISABLE: Disable the PWD. +* Input4 : FMI_LVDEN: specifies the low voltage detector status. +* This parameter can be one of the following values: +* - FMI_LVD_ENABLE: Enable the LVD. +* - FMI_LVD_DISABLE: Disable the LVD. +* Input5 : FMI_FreqRange: specifies the working frequency range. +* This parameter can be one of the following values: +* - FMI_FREQ_LOW: Low working frequency (up to 66MHz). +* - FMI_FREQ_HIGH: High working frequency (above 66MHz) . +* Output : None +* Return : None +*******************************************************************************/ +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange) +{ + /* Configure the write wait state value */ + if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1) + { + FMI->CR |= FMI_WRITE_WAIT_STATE_1; + } + else + { + FMI->CR &= FMI_WRITE_WAIT_STATE_0; + } + + /* Write a write flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x60; + + /* Configure the flash configuration register */ + *(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03; +} + +/******************************************************************************* +* Function Name : FMI_EraseSector +* Description : Erase the needed sector. +* Input : FMI_Sector: specifies the sector to be erased. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseSector(vu32 FMI_Sector) +{ + /* Write an erase set-up command to the sector */ + *(vu16 *)FMI_Sector = 0x20; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Sector = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_EraseBank +* Description : Erase the needed bank. +* Input : FMI_Bank: specifies the bank to be erased. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseBank(vu32 FMI_Bank) +{ + /* Write a bank erase set-up command to the bank */ + *(vu16 *)FMI_Bank = 0x80; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_WriteHalfWord +* Description : Write a halfword to the needed Flash memory address. +* Input 1 : FMI_Address: specifies the address offset where the data will +* be written. +* Input 2 : FMI_Data: the needed data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data) +{ + /* Write a program command to the sector to be written */ + *(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40; + + /* Write the halfword to the destination address */ + *(vu16 *)FMI_Address = FMI_Data; +} + +/******************************************************************************* +* Function Name : FMI_WriteOTPHalfWord +* Description : Write a halfword to the needed OTP sector address. +* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset +* where the data will be written. +* This parameter can be one of the following values: +* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0. +* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0. +* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1. +* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1. +* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2. +* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2. +* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3. +* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3. +* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4. +* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4. +* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5. +* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5. +* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6. +* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6. +* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7. +* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7. +* Input 2 : FMI_OTPData: The needed OTP data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData) +{ + /* Write a write OTP command to the needed address */ + *(vu16 *)(FMI_BANK_1) = 0xC0; + + /* Write the halfword to the destination address */ + *(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData; +} + +/******************************************************************************* +* Function Name : FMI_ReadWord +* Description : Read the correspondent data. +* Input : FMI_Address: specifies the needed address. +* Output : None +* Return : The data contained in the specified address. +*******************************************************************************/ +u32 FMI_ReadWord(u32 FMI_Address) +{ + return(*(u32*)FMI_Address); +} + +/******************************************************************************* +* Function Name : FMI_ReadOTPData +* Description : Read data from the OTP sector. +* Input : FMI_OTPAddress: specifies the address of the data to be read. +* This parameter can be one of the following values: +* - FMI_OTP_WORD_0: FMI bank 0 sector 0. +* - FMI_OTP_WORD_1: FMI bank 0 sector 1. +* - FMI_OTP_WORD_2: FMI bank 0 sector 2. +* - FMI_OTP_WORD_3: FMI bank 0 sector 3. +* - FMI_OTP_WORD_4: FMI bank 0 sector 4. +* - FMI_OTP_WORD_5: FMI bank 0 sector 5. +* - FMI_OTP_WORD_6: FMI bank 0 sector 6. +* - FMI_OTP_WORD_7: FMI bank 0 sector 7. +* Output : None +* Return : The needed OTP words. +*******************************************************************************/ +u32 FMI_ReadOTPData(u8 FMI_OTPAddress) +{ + u32 OTP_Data = 0x0; + /* write a read OTP sector command */ + *(vu16 *)(FMI_BANK_1) = 0x98; + + /* Read the correspondent data */ + OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress)); + + /* Write a read array command */ + *(vu16 *)(FMI_BANK_1) = 0xFF; + + return OTP_Data; +} + +/******************************************************************************* +* Function Name : FMI_GetFlagStatus +* Description : Check whether the specified FMI flag is set or not. +* Input1 : FMI_Flag: flag to check. +* This parameter can be one of the following values: +* - FMI_FLAG_SPS: Sector Protection Status Flag. +* - FMI_FLAG_PSS: Program Suspend Status Flag. +* - FMI_FLAG_PS: Program Status Flag. +* - FMI_FLAG_ES: Erase Status Flag. +* - FMI_FLAG_ESS: Erase Suspend Status Flag. +* - FMI_FLAG_PECS: FPEC Status Flag. +* Input2 : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank) +{ + u16 FMI_Status_Register = 0; + + /* Write a read status register command */ + *(vu16 *)FMI_Bank = 0x70; + + /* Wait until operation completion */ + while(!((*(vu16 *)FMI_Bank) & 0x80)); + + /* Read the status register */ + FMI_Status_Register = *(vu16 *)FMI_Bank; + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if((FMI_Status_Register & FMI_Flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_GetReadWaitStateValue +* Description : Get the current Read wait state value. +* Input : None +* Output : None +* Return : The current read wait states value. +*******************************************************************************/ +u16 FMI_GetReadWaitStateValue(void) +{ + u16 FMI_Configuration_Register = 0; + /* Write a read flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash configuration register */ + FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3; + + /* Return the wait states value */ + return FMI_Configuration_Register; +} + +/******************************************************************************* +* Function Name : FMI_GetWriteWaitStateValue +* Description : Get the current write wait state value. +* Input : None +* Output : None +* Return : The current write wait states value. +*******************************************************************************/ +u16 FMI_GetWriteWaitStateValue(void) +{ + return ((u16)((FMI->CR & 0x100) >> 8)); +} + +/******************************************************************************* +* Function Name : FMI_SuspendEnable +* Description : Suspend command enable. +* Input : FMI_Bank: specifies the bank to be suspended. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_SuspendEnable(vu32 FMI_Bank) +{ + /* Write a suspend command to the bank */ + *(vu16 *)FMI_Bank = 0xB0; +} + +/******************************************************************************* +* Function Name : FMI_ResumeEnable +* Description : Resume the suspended command. +* Input : FMI_Bank: specifies the suspended bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ResumeEnable(vu32 FMI_Bank) +{ + /* Write a resume command to the bank */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_ClearFlag +* Description : Clear the FMI Flags on the correspondent bank. +* Input : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ClearFlag(vu32 FMI_Bank) +{ + /* Write a clear status register command */ + *(vu16 *)FMI_Bank = 0x50; +} + +/******************************************************************************* +* Function Name : FMI_WriteProtectionCmd +* Description : Enable or disable the write protection for the needed sector. +* Input1 : FMI_Sector: specifies the sector to be protected or +* unprotected. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Input2 : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: Enable the protection. +* - DISABLE: Disable the protection. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState) +{ + if (FMI_NewState == ENABLE) + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0x01; + *(vu16*)FMI_Sector = 0xFF; + } + else /* DISABLE */ + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0xD0; + *(vu16*)FMI_Sector = 0xFF; + } +} + +/******************************************************************************* +* Function Name : FMI_GetWriteProtectionStatus +* Description : Get the write protection status for the needed sector. +* Input : FMI_Sector_Mask: specifies the needed sector mask. +* This parameter can be one of the following values: +* - FMI_B0S0_MASK: FMI bank 0 sector 0. +* - FMI_B0S1_MASK: FMI bank 0 sector 1. +* - FMI_B0S2_MASK: FMI bank 0 sector 2. +* - FMI_B0S3_MASK: FMI bank 0 sector 3. +* - FMI_B0S4_MASK: FMI bank 0 sector 4. +* - FMI_B0S5_MASK: FMI bank 0 sector 5. +* - FMI_B0S6_MASK: FMI bank 0 sector 6. +* - FMI_B0S7_MASK: FMI bank 0 sector 7. +* - FMI_B1S0_MASK: FMI bank 1 sector 0. +* - FMI_B1S1_MASK: FMI bank 1 sector 1. +* - FMI_B1S2_MASK: FMI bank 1 sector 2. +* - FMI_B1S3_MASK: FMI bank 1 sector 3. +* Output : None +* Return : The Protection Status of the needed sector. +* - RESET: The needed sector is not write protected. +* - SET : The needed sector is write protected. +*******************************************************************************/ +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask) +{ + u16 Protection_Level_1_Register = 0; + /* Write a read flash protection level 1 register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash protection level 1 register */ + Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + if (Protection_Level_1_Register &= FMI_Sector_Mask) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_WaitForLastOperation +* Description : Wait until the last operation (Write halfword, Write OTP +* halfword, Erase sector and Erase bank) completion. +* Input : FMI_Bank: specifies the bank where the operation is on going. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : The timeout status. +* This parameter can be one of the following values: +* - FMI_TIME_OUT_ERROR: Timeout error occurred. +* - FMI_NO_TIME_OUT_ERROR: No timeout error. +*******************************************************************************/ +u8 FMI_WaitForLastOperation(vu32 FMI_Bank) +{ + u32 Time_Out = 0; + + /* Write a read status register command */ + *(vu16 *)(FMI_Bank) = 0x70; + + /* Wait until operation compeletion */ + while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT )) + { + Time_Out ++; /* Time Out */ + } + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if (Time_Out == TIMEOUT) + { + return FMI_TIME_OUT_ERROR; + } + else + { + return FMI_NO_TIME_OUT_ERROR; + } +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_gpio.c b/uc_str912/prj_template91x/str91x_lib/src/91x_gpio.c new file mode 100644 index 0000000..f2d0941 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_gpio.c @@ -0,0 +1,407 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the GPIO software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_gpio.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + + /* Reset the GPIO registers values */ + if(GPIOx == GPIO0) + { + SCU_APBPeriphReset(__GPIO0,ENABLE); + SCU_APBPeriphReset(__GPIO0,DISABLE); + SCU->GPIOTYPE[0x00] = 0x0000 ; + SCU->GPIOOUT[0x00] = 0x0000; + SCU->GPIOIN[0x00] = 0x0000; + } + + if(GPIOx == GPIO1) + { + SCU_APBPeriphReset(__GPIO1,ENABLE); + SCU_APBPeriphReset(__GPIO1,DISABLE); + SCU->GPIOTYPE[0x01] = 0x0000 ; + SCU->GPIOOUT[0x01] = 0x0000; + SCU->GPIOIN[0x01] = 0x0000; + } + + if(GPIOx == GPIO2) + { + SCU_APBPeriphReset(__GPIO2,ENABLE); + SCU_APBPeriphReset(__GPIO2,DISABLE); + SCU->GPIOTYPE[0x02] = 0x0000 ; + SCU->GPIOOUT[0x02] = 0x0000; + SCU->GPIOIN[0x02] = 0x0000; + } + + if(GPIOx == GPIO3) + { + SCU_APBPeriphReset(__GPIO3,ENABLE); + SCU_APBPeriphReset(__GPIO3,DISABLE); + SCU->GPIOTYPE[0x03] = 0x0000 ; + SCU->GPIOOUT[0x03] = 0x0000; + SCU->GPIOIN[0x03] = 0x0000; + } + + if(GPIOx == GPIO4) + { + SCU_APBPeriphReset(__GPIO4,ENABLE); + SCU_APBPeriphReset(__GPIO4,DISABLE); + SCU->GPIOTYPE[0x04] = 0x0000 ; + SCU->GPIOOUT[0x04] = 0x0000; + SCU->GPIOIN[0x04] = 0x0000; + SCU->GPIOANA = 0x00; + } + + if(GPIOx == GPIO5) + { + SCU_APBPeriphReset(__GPIO5,ENABLE); + SCU_APBPeriphReset(__GPIO5,DISABLE); + SCU->GPIOTYPE[0x05] = 0x0000 ; + SCU->GPIOOUT[0x05] = 0x0000; + SCU->GPIOIN[0x05] = 0x0000; + } + + if(GPIOx == GPIO6) + { + SCU_APBPeriphReset(__GPIO6,ENABLE); + SCU_APBPeriphReset(__GPIO6,DISABLE); + SCU->GPIOTYPE[0x06] = 0x0000 ; + SCU->GPIOOUT[0x06] = 0x0000; + SCU->GPIOIN[0x06] = 0x0000; + } + + if(GPIOx == GPIO7) + { + SCU_APBPeriphReset(__GPIO7,ENABLE); + SCU_APBPeriphReset(__GPIO7,DISABLE); + SCU->GPIOOUT[0x07] = 0xAAAA; + SCU->GPIOOUT[0x07] = 0x0000; + SCU->GPIOIN[0x07] = 0x0000; + } + + if(GPIOx == GPIO8) + { + SCU_APBPeriphReset(__GPIO8,ENABLE); + SCU_APBPeriphReset(__GPIO8,DISABLE); + SCU->GPIOEMI = 0x00; + } + + if(GPIOx == GPIO9) + { + SCU_APBPeriphReset(__GPIO9,ENABLE); + SCU_APBPeriphReset(__GPIO9,DISABLE); + SCU->GPIOEMI = 0x00; + } +} +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct . +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Select pin direction */ + u8 PinNumber = 0; + u8 Counter = 0; + u8 GPIO_Number = 0; + + GPIO_Number = GPIO_GetGPIONumber(GPIOx); + + + if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput) + { + GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin; + } + else + { + GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin; + } + + for (Counter = 0; Counter < 8;Counter++) + { + /*Search pin number*/ + PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <> Counter) == 1) + { + /*Output ALternate 0*/ + SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2)); + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1) + { + /*Output ALternate 1*/ + SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2) + { + /*Output ALternate 2*/ + SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3) + { + /*Output ALternate 3*/ + SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2); + } + + /*Type configuration: PushPull or Open Collector*/ + SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector) + { + /*Open Drain configuration*/ + SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter; + } + + /*IP Connected disable*/ + SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable) + { + /*IP Connected enable*/ + SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter; + } + } + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Initialize the GPIO Init Structure parameters +* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Direction = GPIO_PinInput; + GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull; + GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable; + GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1; +} + +/******************************************************************************* +* Function Name : GPIO_ReadBit +* Description : Reads the specified port pin +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* Output : None +* Return : The port pin value +*******************************************************************************/ +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin) +{ + if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET ) + { + return Bit_SET; + } + else + { + return Bit_RESET; + } +} + +/******************************************************************************* +* Function Name : GPIO_Read +* Description : Reads the specified GPIO data port +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO data port word value. +*******************************************************************************/ +u8 GPIO_Read(GPIO_TypeDef* GPIOx) +{ + return (GPIOx->DR[0x3FC]); +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* - BitVal: this parameter specifies the value to be written +* to the selected bit. +* BitVal must be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal) +{ + if(BitVal == Bit_SET) + { + GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin; + } + else + { + GPIOx->DR[GPIO_Pin <<2] = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes the passed value in the selected data GPIOx port +* register. +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - PortVal: the value to be written to the data port register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal) +{ + GPIOx->DR[0x3FC] = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_EMIConfig +* Description : Enables or disables GPIO 8 and 9 in EMI mode. +* Input : - NewState: new state of the EMI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EMIConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SCU->GPIOEMI = 0x01; + } + else + { + SCU->GPIOEMI = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_ANAPinConfig +* Description : Enables or disables pins from GPIO 4 in Analogue mode. +* Input :- GPIO_ANAChannel: selects the ADC channel pin. +* This parameter can be one of the following values: +* GPIO_ANAChannel0 +* GPIO_ANAChannel1 +* GPIO_ANAChannel2 +* GPIO_ANAChannel3 +* GPIO_ANAChannel4 +* GPIO_ANAChannel5 +* GPIO_ANAChannel6 +* GPIO_ANAChannel7 +* GPIO_ANAChannelALL +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState) +{ + + if(NewState == ENABLE) + { + if(GPIO_ANAChannel == GPIO_ANAChannelALL) + { + SCU->GPIOOUT[4] = 0x0000; + SCU->GPIOIN[4] = 0x00; + } + else + { + SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1)); + SCU->GPIOIN[4] &= ~GPIO_ANAChannel; + } + SCU->GPIOANA |= GPIO_ANAChannel; + + } + else + { + SCU->GPIOANA &= ~GPIO_ANAChannel; + } +} + +/******************************************************************************* +* Function Name : GPIO_GetGPIONumber +* Description : searche the GPIO number. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO number +*******************************************************************************/ +u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx) +{ + + if(GPIOx == GPIO1) + { + return 1; + } + if(GPIOx == GPIO2) + { + return 2; + } + if(GPIOx == GPIO3) + { + return 3; + } + if(GPIOx == GPIO4) + { + return 4; + } + if(GPIOx == GPIO5) + { + return 5; + } + if(GPIOx == GPIO6) + { + return 6; + } + if(GPIOx == GPIO7) + { + return 7; + } + if(GPIOx == GPIO8) + { + return 8; + } + if(GPIOx == GPIO9) + { + return 9; + } + return 0; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_i2c.c b/uc_str912/prj_template91x/str91x_lib/src/91x_i2c.c new file mode 100644 index 0000000..9f15adb --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_i2c.c @@ -0,0 +1,616 @@ +/******************** (C) COPYRIGHT 2005 STMicroelectronics ******************** +* File Name : 91x_i2c.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the I2C software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_i2c.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* I2C IT enable */ +#define I2C_IT_Enable 0x01 +#define I2C_IT_Disable 0xFE + +/* I2C Peripheral Enable/Disable */ +#define I2C_PE_Set 0x20 +#define I2C_PE_Reset 0xDF + +/* Address direction bit */ +#define I2C_ADD0_Set 0x01 +#define I2C_ADD0_Reset 0xFE + +/* I2C START Enable/Disable */ +#define I2C_Start_Enable 0x08 +#define I2C_Start_Disable 0xF7 + +/* I2C STOP Enable/Disable */ +#define I2C_Stop_Enable 0x02 +#define I2C_Stop_Disable 0xFD + +/* I2C Masks */ +#define I2C_Frequency_Mask 0x1F +#define I2C_AddressHigh_Mask 0xF9 +#define I2C_OwnAddress_Mask 0x0300 +#define I2C_StandardMode_Mask 0x7f +#define I2C_FastMode_Mask 0x80 +#define I2C_Event_Mask 0x3FFF +#define I2C_HeaderSet_Mask 0xF1 +#define I2C_HeaderReset_Mask 0xFE + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : I2C_DeInit +* Description : Deinitializes the I2C peripheral registers to their default +* reset values. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* Output : None +* Return : None +*******************************************************************************/ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + if (I2Cx == I2C0) + { + /* Reset the I2C0 registers values */ + SCU_APBPeriphReset(__I2C0, ENABLE); + SCU_APBPeriphReset(__I2C0, DISABLE); + } + if (I2Cx == I2C1) + { + /* Reset the I2C1 registers values */ + SCU_APBPeriphReset(__I2C1, ENABLE); + SCU_APBPeriphReset(__I2C1, DISABLE); + } +} + +/******************************************************************************* +* Function Name : I2C_Init +* Description : Initializes the I2C peripheral according to the specified +* parameters in the I2C_InitTypeDef structure. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* +* - I2C_InitStruct: pointer to an I2C_InitTypeDef structure that +* contains the configuration information for the specified I2C +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + u16 wResult = 0x0F; + u32 dPCLK = 25000000; + + /* Get PCLK frequency value */ + dPCLK = SCU_GetPCLKFreqValue()*1000; + /* Disable I2C peripheral to set FR[2:0] bits */ + I2C_Cmd (I2Cx, DISABLE); + /* Clear frequency FR[2:0] bits */ + I2Cx->OAR2 &= I2C_Frequency_Mask; + /* Set frequency bits depending on PCLK value */ + if ((dPCLK <1667000) & (dPCLK > 10000000)) + I2Cx->OAR2 |= 0x20; + else if (dPCLK < 26670000) + I2Cx->OAR2 |= 0x40; + else if (dPCLK < 40000000) + I2Cx->OAR2 |= 0x60; + else if (dPCLK < 53330000) + I2Cx->OAR2 |= 0x80; + else if (dPCLK < 66000000) + I2Cx->OAR2 |= 0xA0; + else if (dPCLK < 80000000) + I2Cx->OAR2 |= 0xC0; + else if (dPCLK < 100000000) + I2Cx->OAR2 |= 0xE0; + I2C_Cmd (I2Cx, ENABLE); + + /* Configure general call */ + if (I2C_InitStruct->I2C_GeneralCall == I2C_GeneralCall_Enable) + { + /* Enable general call */ + I2Cx->CR |= I2C_GeneralCall_Enable; + } + else + { + /* Disable general call */ + I2Cx->CR &= I2C_GeneralCall_Disable; + } + /* Configure acknowledgement */ + if (I2C_InitStruct->I2C_Ack == I2C_Ack_Enable) + { + /* Enable acknowledgement */ + I2Cx->CR |= I2C_Ack_Enable; + } + else + { + /* Disable acknowledgement */ + I2Cx->CR &= I2C_Ack_Disable; + } + + /* Configure LSB own address */ + I2Cx->OAR1 = I2C_InitStruct->I2C_OwnAddress; + /* Clear MSB own address ADD[9:8] bits */ + I2Cx->OAR2 &= I2C_AddressHigh_Mask; + /* Set MSB own address value */ + I2Cx->OAR2 |= (I2C_InitStruct->I2C_OwnAddress & I2C_OwnAddress_Mask)>>7; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_CLKSpeed <= 100000) + { + /* Standard mode speed calculate */ + wResult = ((dPCLK/I2C_InitStruct->I2C_CLKSpeed)-7)/2; + /* Set speed value and clear FM/SM bit for standard mode in LSB clock divider */ + I2Cx->CCR = wResult & I2C_StandardMode_Mask; + } + /* Configure speed in fast mode */ + else if (I2C_InitStruct->I2C_CLKSpeed <= 400000) + { + /* Fast mode speed calculate */ + wResult = ((dPCLK/I2C_InitStruct->I2C_CLKSpeed)-9)/3; + /* Set speed value and set FM/SM bit for fast mode in LSB clock divider */ + I2Cx->CCR = wResult | I2C_FastMode_Mask; + } + /* Set speed in MSB clock divider */ + I2Cx->ECCR = wResult >>7; +} + +/******************************************************************************* +* Function Name : I2C_StructInit +* Description : Initialize the I2C Init Structure parameters +* Input : - I2C_InitStruct: pointer to an I2C_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /* Initialize the I2C_CLKSpeed member */ + I2C_InitStruct->I2C_CLKSpeed = 5000; + + /* Initialize the I2C_OwnAddress member */ + I2C_InitStruct->I2C_OwnAddress = 0x0; + + /* Initialize the I2C_GeneralCall member */ + I2C_InitStruct->I2C_GeneralCall = I2C_GeneralCall_Disable; + + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; +} + +/******************************************************************************* +* Function Name : I2C_Cmd +* Description : Enables or disables the specified I2C peripheral. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - NewState: new state of the I2C peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C peripheral by setting twice the PE bit on the CR register */ + I2Cx->CR |= I2C_PE_Set; + I2Cx->CR |= I2C_PE_Set; + } + else + { + /* Disable the I2C peripheral */ + I2Cx->CR &= I2C_PE_Reset; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTART +* Description : Generates I2C communication START condition. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* +* - NewState: new state of the Start condition. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateStart(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a START condition */ + I2Cx->CR |= I2C_Start_Enable; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR &= I2C_Start_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_GenerateSTOP +* Description : Generates I2C communication STOP condition. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* +* - NewState: new state of the Stop condition. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Generate a SIOP condition */ + I2Cx->CR |= I2C_Stop_Enable; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR &= I2C_Stop_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_AcknowledgeConfig +* Description : Enables or disables I2C acknowledge feature. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - NewState: new state of the Acknowledgement. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR |= I2C_Ack_Enable; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR &= I2C_Ack_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_ITConfig +* Description : Enables or disables I2C interrupt feature. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - NewState: new state of the specified I2C interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_ITConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the I2C interrupt */ + I2Cx->CR |= I2C_IT_Enable; + } + else + { + /* Disable the I2C interrupt */ + I2Cx->CR &= I2C_IT_Disable; + } +} + +/******************************************************************************* +* Function Name : I2C_ReadRegister +* Description : Reads any I2C register and returns its value. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_Register: the I2C register to be read. This parameter +* can be one of the following values: +* - I2C_CR: CR register. +* - I2C_SR1: SR1 register. +* - I2C_SR2: SR2 register. +* - I2C_CCR: CCR register. +* - I2C_OAR1: OAR1 register. +* - I2C_OAR2: OAR2 register. +* - I2C_DR: DR register. +* - I2C_ECCR: ECCR register. +* Output : None +* Return : The value of the register passed as parameter +*******************************************************************************/ +u8 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register) +{ + /* Return the selected register value */ + if (I2Cx == I2C0) + { + return (*(u8 *)(I2C0_BASE + I2C_Register)); + } + if (I2Cx == I2C1) + { + return (*(u8 *)(I2C1_BASE + I2C_Register)); + } + return 0; +} + +/******************************************************************************* +* Function Name : I2C_GetFlagStatus +* Description : Checks whether the specified I2C flag is set or not. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_FLAG: flag to check. This parameter can be one of the +* following values: +* - I2C_FLAG_SB: Start bit flag +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Adress matched flag +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* Output : None +* Return : The NewState of the I2C_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u16 I2C_FLAG) +{ + u16 wFlag1=0, wFlag2=0, wTmp=0; + + wFlag1 = I2Cx->SR2; + wFlag1 = wFlag1<<8; + wFlag2 = I2Cx->CR & 0x04; + + /* Get all the I2C flags in a unique register*/ + wTmp = (((I2Cx->SR1 | (wFlag1)) & I2C_Event_Mask) | (wFlag2<<12)); + + /* Check the status of the specified I2C flag */ + if((wTmp & I2C_FLAG) != RESET) + { + /* Return SET if I2C_FLAG is set */ + return SET; + } + else + { + /* Return RESET if I2C_FLAG is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : I2C_ClearFlag +* Description : Clears the I2C Flag passed as a parameter +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_FLAG: flag to check. This parameter can be one of the +* following values: +* - I2C_FLAG_SB: Start bit flag +* - I2C_FLAG_M_SL: Master/Slave flag +* - I2C_FLAG_ADSL: Adress matched flag +* - I2C_FLAG_BTF: Byte transfer finished flag +* - I2C_FLAG_BUSY: Bus busy flag +* - I2C_FLAG_TRA: Transmitter/Receiver flag +* - I2C_FLAG_ADD10: 10-bit addressing in Master mode flag +* - I2C_FLAG_EVF: Event flag +* - I2C_FLAG_GCAL: General call flag +* - I2C_FLAG_BERR: Bus error flag +* - I2C_FLAG_ARLO: Arbitration lost flag +* - I2C_FLAG_STOPF: Stop detection flag +* - I2C_FLAG_AF: Acknowledge failure flag +* - I2C_FLAG_ENDAD: End of address transmission flag +* - I2C_FLAG_ACK: Acknowledge enable flag +* - parameter needed in the case that the flag to be cleared +* need a write in one register +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, u16 I2C_FLAG, ...) +{ + u8 bTmp = (u8)*((u32 *) & I2C_FLAG + sizeof(I2C_FLAG)); + + /* flags that need a read of the SR2 register to be cleared */ + if ((I2C_FLAG==I2C_FLAG_ADD10) || (I2C_FLAG==I2C_FLAG_EVF) || (I2C_FLAG==I2C_FLAG_BERR) || (I2C_FLAG==I2C_FLAG_ARLO) | + (I2C_FLAG==I2C_FLAG_STOPF) ||(I2C_FLAG==I2C_FLAG_AF) || (I2C_FLAG==I2C_FLAG_ENDAD)) + { + /* Read the SR2 register */ + I2Cx->SR2; + + /* Two flags need a second step to be cleared */ + switch (I2C_FLAG) + { + case I2C_FLAG_ADD10: + /* Send the MSB 10bit address passed as second parameter */ + I2Cx->DR = bTmp; + break; + case I2C_FLAG_ENDAD: + /* Write to the I2C_CR register by setting PE bit */ + I2Cx->CR |= I2C_PE_Set; + break; + } + } + + /* flags that need a read of the SR1 register to be cleared */ + else if (I2C_FLAG==I2C_FLAG_SB || I2C_FLAG==I2C_FLAG_ADSL || I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* Read the SR1 register */ + (void)I2Cx->SR1; + + /* three flags need a second step to be cleared */ + if (I2C_FLAG == I2C_FLAG_SB) + { + /* Send the address byte passed as second parameter */ + I2Cx->DR = bTmp; + } + else if (I2C_FLAG==I2C_FLAG_BTF || I2C_FLAG==I2C_FLAG_TRA) + { + /* return the received byte in the variable passed as second parameter */ + bTmp=I2Cx->DR; + } + } + + /* flags that need to disable the I2C interface */ + else if ( I2C_FLAG==I2C_FLAG_M_SL || I2C_FLAG==I2C_FLAG_GCAL) + { + I2C_Cmd(I2Cx, DISABLE); + I2C_Cmd(I2Cx, ENABLE); + } +} + +/******************************************************************************* +* Function Name : I2C_Send7bitAddress +* Description : Transmits the address byte to select the slave device. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - Address: specifies the slave address which will be transmitted +* - Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. This parameter can be one of the +* following values +* - I2C_MODE_TRANSMITTER: Transmitter mode +* - I2C_MODE_RECEIVER: Receiver mode +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 Direction) +{ + /* Test on the direction to define the read/write bit */ + if (Direction == I2C_MODE_RECEIVER) + { + /* Set the address bit0 for read */ + Address |= I2C_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= I2C_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/******************************************************************************* +* Function Name : I2C_SendData +* Description : Send a data byte. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - bData : the byte to be sent +* Output : None +* Return : None. +*******************************************************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, u8 bData) +{ + /* Write in the DR register the byte to be sent */ + I2Cx->DR = bData; +} + +/******************************************************************************* +* Function Name : I2C_ReceiveData +* Description : Read the received byte. +* Input : - I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* Output : None +* Return : The received byte +*******************************************************************************/ +u8 I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Return from the DR register the received byte */ + return I2Cx->DR; +} + +/******************************************************************************* +* Function Name : I2C_GetLastEvent +* Description : Get the Last happened I2C Event. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* Output : None +* Return : The Last happened Event. +*******************************************************************************/ +u16 I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + u16 wFlag1=0, wLastEvent=0; + wFlag1 = I2Cx->SR2; + wFlag1 = wFlag1<<8; + /* Get the last event value from I2C status register */ + wLastEvent = (((I2Cx->SR1 | (wFlag1)) & I2C_Event_Mask)); + /* Return the last event */ + return wLastEvent; +} + +/******************************************************************************* +* Function Name : I2C_CheckEvent +* Description : Checks whether the Last I2C Event is equal to the one passed +* as parameter. +* Input :- I2Cx: I2C peripheral can be: +* - I2C0 +* - I2C1 +* - I2C_EVENT: the event to check. This parameter can be one of +* the following values: +* - I2C_EVENT_SLAVE_ADDRESS_MATCHED +* - I2C_EVENT_SLAVE_BYTE_RECEIVED +* - I2C_EVENT_SLAVE_BYTE_TRANSMITTED +* - I2C_EVENT_MASTER_MODE_SELECT +* - I2C_EVENT_MASTER_MODE_SELECTED +* - I2C_EVENT_MASTER_BYTE_RECEIVED +* - I2C_EVENT_MASTER_BYTE_TRANSMITTED +* - I2C_EVENT_MASTER_MODE_ADDRESS10 +* - I2C_EVENT_SLAVE_STOP_DETECTED +* - I2C_EVENT_SLAVE_ACK_FAILURE +* Output : None +* Return : An ErrorStatus enumuration value: +* - SUCCESS: Last event is equal to the I2C_Event +* - ERROR: Last event is different from the I2C_Event +*******************************************************************************/ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,u16 I2C_EVENT) +{ + u16 wLastEvent = I2C_GetLastEvent(I2Cx); + + /* Check whther the last event is equal to I2C_EVENT */ + if (wLastEvent == I2C_EVENT) + { + /* Return SUCCESS when last event is equal to I2C_EVENT */ + return SUCCESS; + } + else + { + /* Return ERROR when last event is different from I2C_EVENT */ + return ERROR; + } +} + +/******************* (C) COPYRIGHT 2005 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_lib.c b/uc_str912/prj_template91x/str91x_lib/src/91x_lib.c new file mode 100644 index 0000000..3fab413 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_lib.c @@ -0,0 +1,281 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all peripherals pointers + : initialization. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#define EXT + +/* Standard include ----------------------------------------------------------*/ +#include "91x_map.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#ifdef LIBDEBUG + +/******************************************************************************* +* Function Name : debug +* Description : this function initialize peripherals pointers +* Input : no one +* Output : no one +* Return : no one +*******************************************************************************/ +void libdebug(void) +{ + + +/************************* DMA *************************/ + +#ifdef _DMA + DMA = (DMA_TypeDef *)DMA_BASE; +#endif /* _DMA */ + +/************************* DMA *************************/ + + +#ifdef _DMA_Channel0 + DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE; +#endif /* _DMA_Channel0 */ + +#ifdef _DMA_Channel1 + DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE; +#endif /* _DMA_Channel1 */ + +#ifdef _DMA_Channel2 + DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE; +#endif /* _DMA_Channel2 */ + +#ifdef _DMA_Channel3 + DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE; +#endif /* _DMA_Channel3 */ + +#ifdef _DMA_Channel4 + DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE; +#endif /* _DMA_Channel4 */ + +#ifdef _DMA_Channel5 + DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE; +#endif /* _DMA_Channel5*/ + + +#ifdef _DMA_Channel6 + DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE; +#endif /* _DMA_Channel6 */ + +#ifdef _DMA_Channel7 + DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE; +#endif /* _DMA_Channel7 */ + + + + /************************* EMI *************************/ + +#ifdef _EMI_Bank0 + EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE; +#endif /* _EMI_Bank0 */ + +#ifdef _EMI_Bank1 + EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE; +#endif /* _EMI_Bank1 */ + +#ifdef _EMI_Bank2 + EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE; +#endif /* _EMI_Bank2 */ + +#ifdef _EMI_Bank3 + EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE; + #endif /* _EMI_Bank3 */ + + + +/************************* AHBAPB *************************/ + +#ifdef _AHBAPB0 + AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE; +#endif /* _AHBAPB0 */ + +#ifdef _AHBAPB1 + AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE; +#endif /*_AHBAPB1 */ + + + +/************************* FMI *************************/ + +#ifdef _FMI + FMI = (FMI_TypeDef *)FMI_BASE; +#endif /* _FMI */ + +/************************* VIC *************************/ + +#ifdef _VIC0 + VIC0 = (VIC_TypeDef *)VIC0_BASE; +#endif /* _VIC0 */ + +#ifdef _VIC1 + VIC1 = (VIC_TypeDef *)VIC1_BASE; +#endif /* _VIC1 */ + +/************************* WIU *************************/ + +#ifdef _WIU + WIU = (WIU_TypeDef *)WIU_BASE; +#endif /* _WIU */ + +/************************* TIM *************************/ + +#ifdef _TIM0 + TIM0 = (TIM_TypeDef *)TIM0_BASE; +#endif /* _TIM0 */ + +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *)TIM1_BASE; +#endif /* _TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *)TIM2_BASE; +#endif /* _TIM2 */ + +#ifdef _TIM3 + TIM3 = (TIM_TypeDef *)TIM3_BASE; +#endif /* _TIM3 */ + +/************************* GPIO ************************/ + +#ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; +#endif /* _GPIO0 */ + +#ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; +#endif /* _GPIO1 */ + +#ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; +#endif /* _GPIO2 */ + +#ifdef _GPIO3 + GPIO3 = (GPIO_TypeDef *)GPIO3_BASE; +#endif /* _GPIO3 */ + +#ifdef _GPIO4 + GPIO4 = (GPIO_TypeDef *)GPIO4_BASE; +#endif /* _GPIO4 */ + +#ifdef _GPIO5 + GPIO5 = (GPIO_TypeDef *)GPIO5_BASE; +#endif /* _GPIO5 */ + +#ifdef _GPIO6 + GPIO6 = (GPIO_TypeDef *)GPIO6_BASE; +#endif /* _GPIO6 */ + +#ifdef _GPIO7 + GPIO7 = (GPIO_TypeDef *)GPIO7_BASE; +#endif /* _GPIO7 */ + +#ifdef _GPIO8 + GPIO8 = (GPIO_TypeDef *)GPIO8_BASE; +#endif /* _GPIO8 */ + +#ifdef _GPIO9 + GPIO9 = (GPIO_TypeDef *)GPIO9_BASE; +#endif /* _GPIO9 */ + +/************************* RTC *************************/ + +#ifdef _RTC + RTC = (RTC_TypeDef *)RTC_BASE; +#endif /* _RTC */ + +/************************* PRCCU ***********************/ + +#ifdef _SCU + SCU = (SCU_TypeDef *)SCU_BASE; +#endif /* _PRCCU */ + +/************************** MC *************************/ + +#ifdef _MC + MC = (MC_TypeDef *)MC_BASE; +#endif /* _MC */ + +/************************* UART ************************/ + +#ifdef _UART0 + UART0 = (UART_TypeDef *)UART0_BASE; +#endif /* _UART0 */ + +#ifdef _UART1 + UART1 = (UART_TypeDef *)UART1_BASE; +#endif /* _UART1 */ + +#ifdef _UART2 + UART2 = (UART_TypeDef *)UART2_BASE; +#endif /* _UART2 */ + +/************************* SSP *************************/ + +#ifdef _SSP0 + SSP0 = (SSP_TypeDef *)SSP0_BASE; +#endif /* _SSP0 */ + +#ifdef _SSP1 + SSP1 = (SSP_TypeDef *)SSP1_BASE; +#endif /* _SSP1 */ + +/************************* CAN *************************/ + +#ifdef _CAN + CAN = (CAN_TypeDef *)CAN_BASE; +#endif /* _CAN */ + +/************************* ADC *************************/ + +#ifdef _ADC + ADC = (ADC_TypeDef *)ADC_BASE; +#endif /* _ADC */ + +/************************* WDG *************************/ + +#ifdef _WDG + WDG = (WDG_TypeDef *)WDG_BASE; +#endif /* _WDG */ + +/************************* I2C *************************/ + +#ifdef _I2C0 + I2C0 = (I2C_TypeDef *)I2C0_BASE; +#endif /* _I2C0 */ + +#ifdef _I2C1 + I2C1 = (I2C_TypeDef *)I2C1_BASE; +#endif /* _I2C1 */ +/********************** ENET **************************/ +#ifdef _ENET + ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE; + ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE; +#endif /* _ENET */ +} +#endif /* LIBDEBUG */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_mc.c b/uc_str912/prj_template91x/str91x_lib/src/91x_mc.c new file mode 100644 index 0000000..d3ca96a --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_mc.c @@ -0,0 +1,932 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_mc.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the MC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_mc.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +#define MC_ODCS_Set 0x0001 +#define MC_ODCS_Reset 0x00FE + +#define MC_CMS_Set 0x0004 +#define MC_CMS_Reset 0x00FB + +#define MC_CPC_Set 0x0008 +#define MC_CTC_Set 0x0010 + +#define MC_PCE_Set 0x0020 +#define MC_PCE_Reset 0xFFDF + +#define MC_TCE_Set 0x0040 +#define MC_TCE_Reset 0x00BF + +#define MC_DTE_Set 0x0080 +#define MC_DTE_Reset 0x007F + +#define MC_TCB_Set 0x0004 +#define MC_TCB_Reset 0x00FB + +#define MC_STC_Set 0x0008 + +#define MC_TES_Set 0x0010 +#define MC_TES_Reset 0x00EF + +#define MC_CCPT_Set 0x0020 +#define MC_CCPT_Reset 0x005F + +#define MC_DISEST_Set 0x0040 +#define MC_DISEST_Reset 0x003F + +#define MC_DTS_Set 0x0001 +#define MC_DTS_Reset 0x00FE + +#define MC_SDT_Set 0x0002 + +#define MC_C0SE_Set 0x0004 +#define MC_C0SE_Reset 0x00FB + +#define MC_CUSE_Set 0x0008 +#define MC_CUSE_Reset 0x00F7 + +#define MC_CVSE_Set 0x0010 +#define MC_CVSE_Reset 0x00EF + +#define MC_CWSE_Set 0x0020 +#define MC_CWSE_Reset 0x00D0 + +#define MC_RSE_Set 0x0040 +#define MC_RSE_Reset 0x00BF + +#define MC_GPI_Set 0x0080 +#define MC_GPI_Reset 0x007F + +#define MC_PUH_Set 0x0020 +#define MC_PUH_Reset 0x005F +#define MC_PUL_Set 0x0010 +#define MC_PUL_Reset 0x006F + +#define MC_PVH_Set 0x0008 +#define MC_PVH_Reset 0x0077 +#define MC_PVL_Set 0x0004 +#define MC_PVL_Reset 0x007B + +#define MC_PWH_Set 0x0002 +#define MC_PWH_Reset 0x007D +#define MC_PWL_Set 0x0001 +#define MC_PWL_Reset 0x007E + +#define MC_ODS_Set 0x0040 +#define MC_ODS_Reset 0xFF3F + +#define MC_ESC_Clear 0x4321 + +#define MC_PCR1_TIN_MASK 0xFFFC +#define MC_OPR_Mask 0x0040 +#define MC_UDCS_Mask 0x0002 +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/****************************************************************************** +* Function Name : MC_DeInit +* Description : Deinitializes MC peripheral registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_DeInit(void) +{ + /* MC peripheral is under Reset */ + SCU_APBPeriphReset(__MC, ENABLE); + + /* MC peripheral Reset off */ + SCU_APBPeriphReset(__MC, DISABLE); +} + +/******************************************************************************* +* Function Name : MC_Init +* Description : Initializes the MC peripheral according to the specified +* parameters in the MC_InitStruct . +* Input : IMC_InitStruct: pointer to a MC_InitTypeDef structure that +* contains the configuration information for the MC peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void MC_Init(MC_InitTypeDef* MC_InitStruct) +{ + /* Select the operating Mode */ + if(MC_InitStruct->MC_OperatingMode == MC_SoftwareOperating_Mode) + { + /* Select the Data transfer Mode */ + MC->PCR2 |= MC_DTS_Set; + + /* Enable the registers Software Data Transfer */ + MC->PCR2 |= MC_C0SE_Set | MC_CUSE_Set | MC_CVSE_Set | MC_CWSE_Set + |MC_RSE_Set; + + } + else + { + /* Select the Data transfer Mode */ + MC->PCR2 &= MC_DTS_Reset; + + /* Disable the registers Software Data Transfer */ + MC->PCR2 &= MC_C0SE_Reset | MC_CUSE_Reset | MC_CVSE_Reset | MC_CWSE_Reset + |MC_RSE_Reset; + } + + /* Select the MC PWM counter Mode */ + if(MC_InitStruct->MC_PWMMode == MC_PWMZeroCentered_Mode) + { + MC->PCR0 |= MC_CMS_Set; + } + else + { + MC->PCR0 &= MC_CMS_Reset; + } + + /* Set the MC PWM counter Prescaler */ + MC->CPRS = MC_InitStruct->MC_Prescaler; + + /* Set the MC PWM Period */ + MC->CMP0 = MC_InitStruct->MC_Period; + + /* Set the MC PWM Repetition counter */ + MC->REP = MC_InitStruct->MC_RepetitionCounter; + + /* Set the Tacho Compare value */ + MC->TCMP = MC_InitStruct->MC_TachoPeriod; + + /* Set the Tacho Prescaler value */ + MC->TPRS = MC_InitStruct->MC_TachoPrescaler; + + /* Set the MC Tacho Input Polarity */ + MC->PCR1 = (MC->PCR1 & MC_PCR1_TIN_MASK) | MC_InitStruct->MC_TachoPolarity; + + /* Set the MC PWM Forced State */ + MC->OPR |= MC_ODS_Set; + MC->OPR = (MC->OPR & MC_OPR_Mask) | MC_InitStruct->MC_ForcedPWMState; + + /* Select the Tacho Mode */ + if(MC_InitStruct->MC_TachoMode == MC_TachoOneShot_Mode) + { + MC->PCR1 |= MC_TCB_Set; + } + else + { + MC->PCR1 &= MC_TCB_Reset; + } + + /* Select the Tacho Event Mode */ + if(MC_InitStruct->MC_TachoEvent_Mode == MC_TachoEvent_Software_Mode) + { + MC->PCR1 |= MC_TES_Set; + } + else + { + MC->PCR1 &= MC_TES_Reset; + } + + /* Enable or disable the emergency input */ + if(MC_InitStruct->MC_Emergency == MC_Emergency_Enable) + { + MC->PCR1 &= MC_DISEST_Reset; + } + else + { + MC->PCR1 |= MC_DISEST_Set; + } + +/* Select the complementary Mode */ + if(MC_InitStruct->MC_Complementary == MC_Complementary_Enable) + { + MC->DTG = MC_InitStruct->MC_DeadTime; + MC->PCR0 |= MC_ODCS_Set; + } + else + { + MC->PCR0 &= MC_ODCS_Reset; + } + + /* Tacho Mode selection */ + if(MC_InitStruct->MC_TachoMode == MC_TachoOneShot_Mode) + { + MC->PCR1 |= MC_TCB_Set; + } + else + { + MC->PCR1 &= MC_TCB_Reset; + } + + switch(MC_InitStruct->MC_Channel) + { + /* Channel U configuration */ + case MC_Channel_U: + { + MC->CMPU = MC_InitStruct->MC_PulseU; + + if(MC_InitStruct->MC_PolarityUL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUL_Set; + } + else + { + MC->PSR &= MC_PUL_Reset; + } + if(MC_InitStruct->MC_PolarityUH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUH_Set; + } + else + { + MC->PSR &= MC_PUH_Reset; + } + break; + } + + /* Channel V configuration */ + case MC_Channel_V: + { + MC->CMPV = MC_InitStruct->MC_PulseV; + + if(MC_InitStruct->MC_PolarityVL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVL_Set; + } + else + { + MC->PSR &= MC_PVL_Reset; + } + if(MC_InitStruct->MC_PolarityVH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVH_Set; + } + else + { + MC->PSR &= MC_PVH_Reset; + } + break; + } + + /* Channel W configuration */ + case MC_Channel_W: + { + MC->CMPW = MC_InitStruct->MC_PulseW; + + if(MC_InitStruct->MC_PolarityWL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWL_Set; + } + else + { + MC->PSR &= MC_PWL_Reset; + } + if(MC_InitStruct->MC_PolarityWH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWH_Set; + } + else + { + MC->PSR &= MC_PWH_Reset; + } + break; + } + /* All Channel Configuration */ + case MC_Channel_ALL: + { + MC->CMPU = MC_InitStruct->MC_PulseU; + MC->CMPV = MC_InitStruct->MC_PulseV; + MC->CMPW = MC_InitStruct->MC_PulseW; + + if(MC_InitStruct->MC_PolarityUL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUL_Set; + } + else + { + MC->PSR &= MC_PUL_Reset; + } + if(MC_InitStruct->MC_PolarityUH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PUH_Set; + } + else + { + MC->PSR &= MC_PUH_Reset; + } + + if(MC_InitStruct->MC_PolarityVL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVL_Set; + } + else + { + MC->PSR &= MC_PVL_Reset; + } + if(MC_InitStruct->MC_PolarityVH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PVH_Set; + } + else + { + MC->PSR &= MC_PVH_Reset; + } + + if(MC_InitStruct->MC_PolarityWL == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWL_Set; + } + else + { + MC->PSR &= MC_PWL_Reset; + } + if(MC_InitStruct->MC_PolarityWH == MC_Polarity_Inverted) + { + MC->PSR |= MC_PWH_Set; + } + else + { + MC->PSR &= MC_PWH_Reset; + } + } + default: + break; + } +} + +/******************************************************************************* +* Function Name : MC_StructInit +* Description : Fills each MC_InitStruct member with its default value. +* Input : MC_InitStruct : pointer to a MC_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void MC_StructInit(MC_InitTypeDef* MC_InitStruct) +{ + MC_InitStruct->MC_OperatingMode = MC_HardwareOperating_Mode; + MC_InitStruct->MC_TachoMode = MC_TachoContinuous_Mode; + MC_InitStruct->MC_TachoEvent_Mode = MC_TachoEvent_Hardware_Mode; + MC_InitStruct->MC_Prescaler = 0x00; + MC_InitStruct->MC_TachoPrescaler = 0x0000; + MC_InitStruct->MC_PWMMode = MC_PWMClassical_Mode; + MC_InitStruct->MC_Complementary = MC_Complementary_Enable; + MC_InitStruct->MC_Emergency = MC_Emergency_Disable; + MC_InitStruct->MC_ForcedPWMState = 0x003F; + MC_InitStruct->MC_Period = 0x0000; + MC_InitStruct->MC_TachoPeriod = 0x00FF; + MC_InitStruct->MC_Channel = MC_Channel_ALL; + MC_InitStruct->MC_PulseU = 0x0000; + MC_InitStruct->MC_PulseV = 0x0000; + MC_InitStruct->MC_PulseW = 0x0000; + MC_InitStruct->MC_PolarityUL = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityUH = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityVL = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityVH = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityWL = MC_Polarity_NonInverted; + MC_InitStruct->MC_PolarityWH = MC_Polarity_NonInverted; + MC_InitStruct->MC_TachoPolarity = MC_TachoEventEdge_RisingFalling; + MC_InitStruct->MC_DeadTime = 0x003F; + MC_InitStruct->MC_RepetitionCounter = 0x0000; +} + +/******************************************************************************* +* Function Name : MC_Cmd +* Description : Enables or disables the MC peripheral. +* Input : Newstate: new state of the MC peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the PWM counter */ + MC->PCR0 |= MC_PCE_Set; + + /* Enable the Tacho counter */ + MC->PCR0 |= MC_TCE_Set; + + /* Enable the Dead Time counter */ + MC->PCR0 |= MC_DTE_Set; + } + else + { + /* Disable the PWM counter */ + MC->PCR0 &= MC_PCE_Reset; + + /* Disable the Tacho counter */ + MC->PCR0 &= MC_TCE_Reset; + + /* Disable the Dead counter */ + MC->PCR0 &= MC_DTE_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_ClearPWMCounter +* Description : Clears the MC PWM counter. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearPWMCounter(void) +{ +/* Clear the PWM counter */ + MC->PCR0 |= MC_CPC_Set; +} + +/******************************************************************************* +* Function Name : MC_ClearTachoCounter +* Description : Clears the MC Tacho counter. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearTachoCounter(void) +{ +/* Clear the Tacho counter */ + MC->PCR0 |= MC_CTC_Set; +} + +/******************************************************************************* +* Function Name : MC_CtrlPWMOutputs +* Description : Enables or disables MC peripheral Main Outputs. +* Input : Newstate: new state of the MC peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_CtrlPWMOutputs(FunctionalState Newstate) +{ + if(Newstate == ENABLE) + { + /* Enable the dead time generator data */ + MC->OPR &= MC_ODS_Reset; + } + else + { + /* Enable the default state data */ + MC->OPR |= MC_ODS_Set; + } +} + +/******************************************************************************* +* Function Name : MC_ITConfig +* Description : Enables or disables the MC interrupts. +* Input : - MC_IT: specifies the MC interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* - MC_IT_CMPW: Compare W Interrupt. +* - MC_IT_CMPV: Compare V Interrupt. +* - MC_IT_CMPU: Compare U Interrupt. +* - MC_IT_ZPC: Zero of PWM counter Interrupt. +* - MC_IT_ADT: Automatic Data Transfer Interrupt. +* - MC_IT_OTC: Overflow of Tacho counter Interrupt. +* - MC_IT_CPT: Capture of Tacho counter Interrupt. +* - MC_IT_CM0: Compare 0 Interrupt. +* - Newstate: new state of IMC interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ITConfig(u16 MC_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the specific interrupt source */ + MC->IMR |= MC_IT; + + /* Enable the global peripheral interrupt sources */ + MC->PCR2 |= MC_GPI_Set; + } + else + { + /* Disable the specific interrupt source */ + MC->IMR &= ~MC_IT; + + /* Disable the global peripheral interrupt sources */ + MC->PCR2 &= MC_GPI_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_SetPrescaler +* Description : Sets the MC prescaler value. +* Input : MC_Prescaler: MC prescaler new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPrescaler(u8 MC_Prescaler) +{ +/* Set the Prescaler Register value */ + MC->CPRS = MC_Prescaler; +} + +/******************************************************************************* +* Function Name : MC_SetPeriod +* Description : Sets the MC period value. +* Input : MC_Period: MC period new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPeriod(u16 MC_Period) +{ +/* Set the Period Register value */ + MC->CMP0 = MC_Period; +} + +/******************************************************************************* +* Function Name : MC_SetPulseU +* Description : Sets the MC pulse U value. +* Input : MC_PulseU: MC pulse U new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPulseU(u16 MC_PulseU) +{ +/* Set the Pulse U Register value */ + MC->CMPU = MC_PulseU; +} + +/******************************************************************************* +* Function Name : MC_SetPulseV +* Description : Sets the MC pulse V value. +* Input : MC_PulseV: MC pulse V new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPulseV(u16 MC_PulseV) +{ +/* Set the Pulse V Register value */ + MC->CMPV = MC_PulseV; +} + +/******************************************************************************* +* Function Name : MC_SetPulseW +* Description : Sets the MC pulse W value. +* Input : MC_PulseW: MC pulse W new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetPulseW(u16 MC_PulseW) +{ +/* Set the Pulse W Register value */ + MC->CMPW = MC_PulseW; +} + +/******************************************************************************* +* Function Name : MC_PWMModeConfig +* Description : Selects the MC PWM counter Mode. +* Input : MC_PWMMode: MC PWM counter Mode. +* Output : None +* Return : None +*******************************************************************************/ +void MC_PWMModeConfig(u16 MC_PWMMode) +{ + /* Select the MC PWM counter Mode */ + if(MC_PWMMode == MC_PWMZeroCentered_Mode) + { + MC->PCR0 |= MC_CMS_Set; + } + else + { + MC->PCR0 &= MC_CMS_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_SetDeadTime +* Description : Sets the MC dead time value. +* Input : MC_DeadTime: MC dead time new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetDeadTime(u16 MC_DeadTime) +{ +/* Set the dead time Register value */ + MC->DTG = MC_DeadTime; +} + +/******************************************************************************* +* Function Name : MC_SetTachoCompare +* Description : Sets the MC Tacho Compare Register value. +* Input : MC_Compare: MC Tacho compare new value. +* Output : None +* Return : None +*******************************************************************************/ +void MC_SetTachoCompare(u8 MC_Compare) +{ + /* Sets the Tacho Compare Register value */ + MC->TCMP = MC_Compare; +} +/******************************************************************************* +* Function Name : MC_EmergencyCmd +* Description : Enables or disables the MC emergency feauture. +* Input : Newstate: new state of the MC peripheral Emergency. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_EmergencyCmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Reset the DISEST Bit in the PCR1 Register to enable the emergency stop input */ + MC->PCR1 &= MC_DISEST_Reset; + } + else + { + /* Set the DISEST Bit in the PCR1 Register to disable the emergency stop input */ + MC->PCR1 |= MC_DISEST_Reset; + } +} + +/******************************************************************************* +* Function Name : MC_EmergencyClear +* Description : Clears the MC Emergency Register. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_EmergencyClear(void) +{ +/* Force PWM outputs in safe state (All OFF) */ + MC->OPR |= MC_ODS_Set; + +/* Clear EST bit */ + MC->ESC = MC_ESC_Clear; + +/* Re-enable protection */ + MC->ESC = 0; + +/* Enables the Outputs */ + MC->OPR &= MC_ODS_Reset; +} + +/******************************************************************************* +* Function Name : MC_GetPeriod +* Description : Gets the MC period value. +* Input : None +* Output : None +* Return : MC period value. +*******************************************************************************/ +u16 MC_GetPeriod(void) +{ +/* Return the PWM signal period value */ + return MC->CMP0; +} + +/******************************************************************************* +* Function Name : MC_GetPulseU +* Description : Gets the MC pulse U value. +* Input : None +* Output : None +* Return : MC pulse U value. +*******************************************************************************/ +u16 MC_GetPulseU(void) +{ +/* Return the PWM pulse U Register value */ + return MC->CMPU; +} + +/******************************************************************************* +* Function Name : MC_GetPulseV +* Description : Gets the MC pulse V value. +* Input : None +* Output : None +* Return : MC pulse V value. +*******************************************************************************/ +u16 MC_GetPulseV(void) +{ +/* Return the PWM pulse V Register value */ + return MC->CMPV; +} + +/******************************************************************************* +* Function Name : MC_GetPulseW +* Description : Gets the MC pulse W value. +* Input : None +* Output : None +* Return : MC pulse W value. +*******************************************************************************/ +u16 MC_GetPulseW(void) +{ +/* Return the PWM pulse W Register value */ + return MC->CMPW; +} + +/******************************************************************************* +* Function Name : MC_GetTachoCapture +* Description : Gets the MC Tacho period value. +* Input : None +* Output : None +* Return : MC Tacho capture value. +*******************************************************************************/ +u16 MC_GetTachoCapture(void) +{ +/* Return the Tacho Capture Register value */ + return MC->TCPT; +} + +/******************************************************************************* +* Function Name : MC_ClearOnTachoCapture +* Description : Enables or disables the the Clear on capture of tacho counter. +* Input : Newstate: new state of the CCPT bit. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearOnTachoCapture(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the Clear on capture of tacho counter */ + MC->PCR1 |= MC_CCPT_Set; + } + else + { + /* Disable the Clear on capture of tacho counter */ + MC->PCR1 &= MC_CCPT_Reset; + } +} +/******************************************************************************* +* Function Name : MC_ForceDataTransfer +* Description : Sets the MC Outputs default states. +* Input : MC_ForcedData: MC outputs new states. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ForceDataTransfer(u8 MC_ForcedData) +{ + /* Set the MC PWM Forced State */ + MC->OPR |= MC_ODS_Set; + MC->OPR = (MC->OPR & MC_OPR_Mask) | MC_ForcedData; +} + +/******************************************************************************* +* Function Name : MC_PreloadConfig +* Description : Enables the Software Data Transfer. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_SoftwarePreloadConfig(void) +{ + /* Set the SDT: Software Data Transfer bit */ + MC->PCR2 |= MC_SDT_Set; +} + +/******************************************************************************* +* Function Name : MC_SoftwareTachoCapture +* Description : Enables the Software Tacho Capture. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_SoftwareTachoCapture(void) +{ + /* Set the STC: Software Tacho Capture bit */ + MC->PCR1 |= MC_STC_Set; +} + +/******************************************************************************* +* Function Name : MC_GetCountingStatus +* Description : Checks whether the PWM Counter is counting Up or Down. +* Input : None +* Output : None +* Return : The new state of the PWM Counter(DOWN or UP). +*******************************************************************************/ +CountingStatus MC_GetCountingStatus(void) +{ + if((MC->PCR0 & MC_UDCS_Mask) != DOWN) + { + return UP; + } + else + { + return DOWN; + } +} + +/******************************************************************************* +* Function Name : MC_GetFlagStatus +* Description : Checks whether the specified MC flag is set or not. +* Input : MC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - MC_FLAG_CMPW: Compare W Flag. +* - MC_FLAG_CMPV: Compare V Flag. +* - MC_FLAG_CMPU: Compare U Flag. +* - MC_FLAG_ZPC: Zero of PWM counter Flag. +* - MC_FLAG_ADT: Automatic Data Transfer Flag. +* - MC_FLAG_OTC: Overflow of Tacho counter Flag. +* - MC_FLAG_CPT: Capture of Tacho counter Flag. +* - MC_FLAG_CM0: Compare 0 Flag. +* - MC_FLAG_EST: Emergency Stop Flag. +* Output : None +* Return : The new state of the MC_FLAG(SET or RESET). +*******************************************************************************/ +FlagStatus MC_GetFlagStatus(u16 MC_FLAG) +{ + if((MC->IPR & MC_FLAG) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MC_ClearFlag +* Description : Clears the MC’s pending flags. +* Input : MC_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* - MC_FLAG_CMPW: Compare W Flag. +* - MC_FLAG_CMPV: Compare V Flag. +* - MC_FLAG_CMPU: Compare U Flag. +* - MC_FLAG_ZPC: Zero of PWM counter Flag. +* - MC_FLAG_ADT: Automatic Data Transfer Flag. +* - MC_FLAG_OTC: Overflow of Tacho counter Flag. +* - MC_FLAG_CPT: Capture of Tacho counter Flag. +* - MC_FLAG_CM0: Compare 0 Flag. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearFlag(u16 MC_FLAG) +{ +/* Clear the corresponding Flag */ + MC->IPR &= ~MC_FLAG; +} + +/******************************************************************************* +* Function Name : MC_GetITStatus +* Description : Checks whether the MC interrupt has occurred or not. +* Input : MC_IT: specifies the MC interrupt source to check. +* This parameter can be one of the following values: +* - MC_IT_CMPW: Compare W Interrupt. +* - MC_IT_CMPV: Compare V Interrupt. +* - MC_IT_CMPU: Compare U Interrupt. +* - MC_IT_ZPC: Zero of PWM counter Interrupt. +* - MC_IT_ADT: Automatic Data Transfer Interrupt. +* - MC_IT_OTC: Overflow of Tacho counter Interrupt. +* - MC_IT_CPT: Capture of Tacho counter Interrupt. +* - MC_IT_CM0: Compare 0 Interrupt. +* Output : None +* Return : The new state of the MC_IT(SET or RESET). +*******************************************************************************/ +ITStatus MC_GetITStatus(u16 MC_IT) +{ + if((MC->IPR & MC_IT) && (MC->IMR & MC_IT)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : MC_ClearITPendingBit +* Description : Clears the IMC's interrupt pending bits. +* Input : MC_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* - MC_IT_CMPW: Compare W Interrupt. +* - MC_IT_CMPV: Compare V Interrupt. +* - MC_IT_CMPU: Compare U Interrupt. +* - MC_IT_ZPC: Zero of PWM counter Interrupt. +* - MC_IT_ADT: Automatic Data Transfer Interrupt. +* - MC_IT_OTC: Overflow of Tacho counter Interrupt. +* - MC_IT_CPT: Capture of Tacho counter Interrupt. +* - MC_IT_CM0: Compare 0 Interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void MC_ClearITPendingBit(u16 MC_IT) +{ +/* Clear the corresponding interrupt pending bit */ + MC->IPR &= ~MC_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_rtc.c b/uc_str912/prj_template91x/str91x_lib/src/91x_rtc.c new file mode 100644 index 0000000..2d0751b --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_rtc.c @@ -0,0 +1,400 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_rtc.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the RTC library software functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_rtc.h" +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +u8 BYTEToBCD2(u8 value); +u16 WORDToBCD3(u16 value); +u8 BCD2ToBYTE(u8 value); +u16 BCD3ToBYTE(u16 value); +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : BYTEToBCD2 +* Description : Converts a 2 digit decimal to BCD format +* Input : None +* Output : None +* Return : Converted byte +*******************************************************************************/ +u8 BYTEToBCD2(u8 value) +{ + u8 bcdhigh = 0; + while (value >= 10) + { + bcdhigh++; + value -= 10; + } + return (bcdhigh << 4) | value; +} +/******************************************************************************* +* Function Name : WORDToBCD3 +* Description : Converts a 3 digit decimal to BCD format +* Input : None +* Output : None +* Return : Converted word +*******************************************************************************/ +u16 WORDToBCD3(u16 value) +{ + u16 bcdhigh = 0; + while (value >= 100) + { + bcdhigh++; + value -= 100; + } + bcdhigh <<= 4; + while (value >= 10) + { + bcdhigh++; + value -= 10; + } + return (bcdhigh << 4) | value; +} + +/******************************************************************************* +* Function Name : BCD3ToWORD +* Description : convert from 3 digit BCD to Binary +* Input : None +* Output : None +* Return : Converted word +*******************************************************************************/ +u16 BCD3ToWORD(u16 value) +{ + return (u16)((((value&0xF00)>>8)*100) + (((value&0x0F0)>>4)*10) + (value&0x0F)); +} + +/******************************************************************************* +* Function Name : BCD2ToBYTE +* Description : convert from 2 digit BCD to Binary +* Input : None +* Output : None +* Return : Converted word +*******************************************************************************/ +u8 BCD2ToBYTE(u8 value) +{ + u32 tmp; + tmp= ((value&0xF0)>>4)*10; + return (u8)(tmp+ (value&0x0F)); +} + +/******************************************************************************* +* Function Name : RTC_DeInit +* Description : Resets the RTC peripheral registers +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_DeInit(void) +{ + SCU_APBPeriphReset(__RTC,ENABLE); + SCU_APBPeriphReset(__RTC,DISABLE); +} + +/******************************************************************************* +* Function Name : RTC_SetDate +* Description : Sets the Date register +* Input : struct of type RTC_DATE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetDate(RTC_DATE Date) +{ + u32 tmp = 0; + + RTC->CR |=0x80; /*Enable write operation in DTR register*/ + RTC->DTR = 0; + tmp = BYTEToBCD2(Date.century); + RTC->DTR|=tmp<<24; + tmp = BYTEToBCD2(Date.year); + RTC->DTR|=tmp<<16; + tmp = BYTEToBCD2(Date.month); + RTC->DTR|=tmp<<8; + tmp = BYTEToBCD2(Date.weekday); + RTC->DTR|=tmp; + RTC->TR &=0xFFFFFF; + tmp = BYTEToBCD2(Date.day); + RTC->TR|=tmp<<24; + RTC->CR &=~0x80; /*Disable write operation in DTR register*/ +} +/******************************************************************************* +* Function Name : RTC_SetTime +* Description : Sets the Time register +* Input : struct of type RTC_TIME +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SetTime(RTC_TIME Time) +{ + u32 tmp = 0; + + RTC->CR |=0x80; /*Enable write operation in TR register*/ + RTC->TR &= 0xFF000000; + tmp = BYTEToBCD2(Time.hours); + RTC->TR|=tmp<<16; + tmp = BYTEToBCD2(Time.minutes); + RTC->TR|=tmp<<8; + tmp = BYTEToBCD2(Time.seconds); + RTC->TR|=tmp; + RTC->MILR = 0; + RTC->MILR |= WORDToBCD3(Time.milliseconds); + RTC->CR &=~0x80; /*Disable write operation in TR register*/ +} +/******************************************************************************* +* Function Name : RTC_SetAlarm +* Description : Sets the Alarm register +* Input : Struct of type RTC_ALARM +* Output : Date +* Return : None +*******************************************************************************/ +void RTC_SetAlarm(RTC_ALARM Alarm) +{ + u32 tmp = 0; + + RTC->CR |=0x80; /*Enable write operation in ATR register*/ + RTC->ATR = 0; + tmp = BYTEToBCD2(Alarm.day); + RTC->ATR|=tmp<<24; + tmp = BYTEToBCD2(Alarm.hours); + RTC->ATR|=tmp<<16; + tmp = BYTEToBCD2(Alarm.minutes); + RTC->ATR|=tmp<<8; + tmp = BYTEToBCD2(Alarm.seconds); + RTC->ATR|=tmp; + RTC->CR &=~0x80; /*Disable write operation in ATR register*/ +} + +/******************************************************************************* +* Function Name : RTC_GetDate +* Description : Gets RTC date in BCD coded or BINARY code +* Input : -Format: BCD or BINARY +* -Date: pointer to structure of type RTC_DATE to be filled by function +* Output : None +* Return : None +*******************************************************************************/ +void RTC_GetDate(u8 Format, RTC_DATE * Date) +{ + Date->century = (u8)((RTC->DTR&0xFF000000)>>24); + Date->year = (u8)((RTC->DTR&0x00FF0000)>>16); + Date->month = (u8)((RTC->DTR&0x00001F00)>>8); + Date->day = (u8)((RTC->TR&0x3F000000)>>24); + Date->weekday = (u8)(RTC->DTR&0xF); + if (Format == BINARY) + { + Date->century = BCD2ToBYTE(Date->century); + Date->year = BCD2ToBYTE(Date->year); + Date->month = BCD2ToBYTE(Date->month); + Date->day = BCD2ToBYTE(Date->day); + Date->weekday = BCD2ToBYTE(Date->weekday); + } +} + +/******************************************************************************* +* Function Name : RTC_GetTime +* Description : Gets TIME in BCD coded or BINARY code +* Input : -Format: BCD or BINARY +* -Time : pointer to structure of type RTC_TIME to be filled by function +* Output : Time +* Return : None +*******************************************************************************/ +void RTC_GetTime(u8 Format, RTC_TIME * Time) +{ + + Time->hours = (u8)((RTC->TR&0x003F0000)>>16); + Time->minutes = (u8)((RTC->TR&0x00007F00)>>8); + Time->seconds = (u8)(RTC->TR&0x7F); + Time->milliseconds =(u16)(RTC->MILR&0xFFF); + if (Format == BINARY) + { + Time->hours = BCD2ToBYTE(Time->hours); + Time->minutes = BCD2ToBYTE(Time->minutes); + Time->seconds = BCD2ToBYTE(Time->seconds); + Time->milliseconds = BCD3ToWORD(Time->milliseconds); + } +} + + +/******************************************************************************* +* Function Name : RTC_GetAlarm +* Description : Gets the RTC Alarm in BCD or BINARY code +* Input : -Format: BCD or BINARY +* -Alarm : pointer to structure of type RTC_ALARM to be filled by function +* Output : Alarm +* Return : None +*******************************************************************************/ +void RTC_GetAlarm(u8 Format,RTC_ALARM * Alarm) +{ + Alarm->day = (u8)((RTC->ATR&0x3F000000)>>24); + Alarm->hours = (u8)((RTC->ATR&0x003F0000)>>16); + Alarm->minutes = (u8)((RTC->ATR&0x00007F00)>>8); + Alarm->seconds = (u8)((RTC->ATR)&0x7F); + if (Format == BINARY) + { + Alarm->day = BCD2ToBYTE(Alarm->day); + Alarm->hours = BCD2ToBYTE(Alarm->hours); + Alarm->minutes = BCD2ToBYTE(Alarm->minutes); + Alarm->seconds = BCD2ToBYTE(Alarm->seconds); + } +} + +/******************************************************************************* +* Function Name : RTC_TamperConfig +* Description : configures the Tamper mode and tamper polarity +* Input : -TamperMode: RTC_TamperMode_Edge or RTC_TamperMode_Level +* -TamperPol : RTC_TamperPol_Low or RTC_TamperMode_High +* Output : None +* Return : None +*******************************************************************************/ +void RTC_TamperConfig(u32 TamperMode, u32 TamperPol) +{ + RTC->CR&=RTC_TamperMode_Edge; + if (TamperMode!=RTC_TamperMode_Edge) + RTC->CR|=RTC_TamperMode_Level; + + RTC->CR&=RTC_TamperPol_Low; + if (TamperPol!=RTC_TamperPol_Low) + RTC->CR|=RTC_TamperPol_High; +} + +/******************************************************************************* +* Function Name : RTC_TamperCmd +* Description : Enable or Disable Tamper +* Input : NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_TamperCmd(FunctionalState NewState) +{ + RTC->CR&=0xFFFFFFFE; + if (NewState==ENABLE) + RTC->CR|=0x1; +} + +/******************************************************************************* +* Function Name : RTC_AlarmCmd +* Description : Enable or Disable Alarm +* Input : NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_AlarmCmd(FunctionalState NewState) +{ + RTC->CR&=~0x100000; + if (NewState==ENABLE) + RTC->CR|=0x100000; +} + +/******************************************************************************* +* Function Name : RTC_CalibClockCmd +* Description : Enable or Disable RTC Calibration Clock Output +* Input : NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_CalibClockCmd(FunctionalState NewState) +{ + RTC->CR&=~0x40; + if (NewState ==ENABLE) + RTC->CR|=0x40; +} + +/******************************************************************************* +* Function Name : SRAMBattPowerCmd +* Description : Enable or Disable SRAM backup Power by VBATT +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void RTC_SRAMBattPowerCmd(FunctionalState NewState) +{ + RTC->CR&=~0x8; + if (NewState ==ENABLE) + RTC->CR|=0x8; +} + +/******************************************************************************* +* Function Name : RTC_PeridicIntConfig +* Description : Select a Periodic CLock +* Input : PeriodicClock +* Output : None +* Return : None +* Note : When PeriodicClock = RTC_Per_DISABLE the Periodic clock generation +* will be disabled. +*******************************************************************************/ +void RTC_PeriodicIntConfig(u32 PeriodicClock) +{ + RTC->CR &=~0xF0000; + RTC->CR|=PeriodicClock; +} + +/******************************************************************************* +* Function Name : RTC_ITConfig +* Description : Enable or Disable an interrupt +* Input : -RTC_IT : RTC interrupt +* -Newstate: Enable or Disable +* Output : None +* Return : None +*******************************************************************************/ +void RTC_ITConfig(u32 RTC_IT, FunctionalState NewState) +{ + RTC->CR&=~RTC_IT; + if (NewState==ENABLE) + RTC->CR|=RTC_IT; +} + +/******************************************************************************* +* Function Name : RTC_GetFlagStatus +* Description : Gets a RTC flag status +* Input : RTC_FLAG +* Output : None +* Return : FlagStatus :SET or RESET +*******************************************************************************/ +FlagStatus RTC_GetFlagStatus(u32 RTC_FLAG) +{ + if (RTC->SR&RTC_FLAG) return SET; + else return RESET; +} + +/******************************************************************************* +* Function Name : RTC_ClearFlag +* Description : Clears a RTC flag +* Input : RTC_FLAG +* Output : None +* Return : None +* Note : Before clearing the RTC Periodic Flag you need to disable the +* Periodic interrupt generation, to do this use function +* RTC_PeriodicIntConfig(RTC_Per_DISABLE) +*******************************************************************************/ +void RTC_ClearFlag(u32 RTC_FLAG) +{ + vu32 tmp=0; + if (RTC_FLAG == RTC_FLAG_Per) tmp=RTC->SR; + else if (RTC_FLAG == RTC_FLAG_Alarm) RTC->CR&=~0x100000; + else if (RTC_FLAG == RTC_FLAG_Tamper) RTC->CR&=~0x1; +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_scu.c b/uc_str912/prj_template91x/str91x_lib/src/91x_scu.c new file mode 100644 index 0000000..21116b2 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_scu.c @@ -0,0 +1,661 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SCU_PLLEN 0x80000 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SCU_MCLKSourceConfig +* Description : Configures the MCLK source clock +* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : this function returns ERROR if trying to select the PLL as +* clock source while the PLL is disabled or not locked. +*******************************************************************************/ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source) +{ + u32 CLKCNTR_Value; + + CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/ + CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/ + if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/ + { + /*check if PLL enabled & locked*/ + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + return ERROR; + } + else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/ + SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/ + return SUCCESS; +} + +/******************************************************************************* +* Function Name : SCU_PLLFactorsConfig +* Description : Sets the PLL factors +* Input : PLLN, PLLM and PLLP +* Output : None +* Return : ErrorStatus: ERROR or SUCCESS +* Notes : -The PLL factors must respect the PLL specification requirements +* -The function returns ERROR if trying to change PLL +* factors while PLL is selected as Main Clock source (MCLK) +* -This function disables the PLL, to enable the PLL use +* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors +******************************************************************************/ +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP) +{ + if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/ + { + SCU->PLLCONF =0; /*clear PLLCONF register*/ + SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/ + SCU->PLLCONF |=PLLM; /*update PLLM field*/ + SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/ + return SUCCESS; + } + return ERROR; +} + +/******************************************************************************* +* Function Name : SCU_PLLCmd +* Description : Enable or Disable the PLL +* Input : NewState = ENABLE or DISABLE +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : -The function returns ERROR if: +* *trying to disable the PLL while it is selected as the MCLK +* *trying to enable the PLL while it is already enabled and +* locked +*******************************************************************************/ +ErrorStatus SCU_PLLCmd(FunctionalState NewState) +{ + vu32 i; + if (NewState==ENABLE) + { + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + { + SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/ + SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/ + while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/ + return SUCCESS; + } + else return ERROR; + } + else /*NewState = DISABLE*/ + { + if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/ + { + for(i=10;i>0;i--); /*delay before PLL disabling*/ + SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/ + return SUCCESS; + } + else return ERROR; + } +} + +/******************************************************************************* +* Function Name : SCU_RCLKDivisorConfig +* Description : Sets the RCLK divisor value +* Input : RCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/ + if (RCLK_Divisor!=SCU_RCLK_Div1) + SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_HCLKDivisorConfig +* Description : Sets the HCLK divisor value +* Input : HCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/ + if (HCLK_Divisor!=SCU_HCLK_Div1) + SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_PCLKDivisorConfig +* Description : Sets the PCLK divisor value +* Input : PCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/ + if (PCLK_Divisor!=SCU_PCLK_Div1) + SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphClockConfig +* Description : Enable the clock for an APB peripheral +* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for APB peripheral*/ + SCU->PCGR1 |=APBPeriph; + else + SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphClockConfig +* Description : Enable the clock for an AHB peripheral +* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for AHB peripheral*/ + SCU->PCGRO |=AHBPeriph; + else + SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphReset +* Description : Assert or deassert Reset on APB peripheral +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) /*APB peripheral not held in Reset*/ + SCU->PRR1 |=APBPeriph; + else + SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphReset +* Description : Assert or deassert Reset on AHB peripheral +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) + SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/ + else + SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/ + else + SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/ + else + SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/ +} +/******************************************************************************* +* Function Name : SCU_BRCLKDivisorConfig +* Description : Sets the BRCLK divisor value +* Input : BRCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/ + if (BRCLK_Divisor!=SCU_BRCLK_Div1) + SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/ +} + +/******************************************************************************* +* Function Name : SCU_TIMCLKSourceConfig +* Description : Sets the TIMx clock source +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source) +{ + if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/ + { + SCU->CLKCNTR &=0xFFFFDFFF; + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x2000; + } + else + { + SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/ + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x4000; + } +} + +/******************************************************************************* +* Function Name : SCU_TIMPresConfig +* Description : Sets the TIMx Prescaler Value +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - Prescaler (16 bit value) +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler) +{ + if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/ + SCU->SCR1 = Prescaler&0xFFFF; + else + SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/ +} + +/******************************************************************************* +* Function Name : SCU_USBCLKConfig +* Description : Configures the clock source for the 48MHz USBCLK +* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_USBCLKConfig(u32 USBCLK_Source) +{ + SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/ + if (USBCLK_Source!=SCU_USBCLK_MCLK) + SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/ +} + +/******************************************************************************* +* Function Name : SCU_PHYCLKConfig +* Description : Enable or Disable PHY clock output +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PHYCLKConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/ + else + SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/ +} + +/******************************************************************************* +* Function Name : SCU_FMICLKDivisorConfig +* Description : Set the FMI clock divisor +* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor) +{ + SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/ + if (FMICLK_Divisor!=SCU_FMICLK_Div1) + SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIBCLKDivisorConfig +* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2 +* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK) +{ + SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */ + if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1) + SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIModeConfig +* Description : Configure the EMI as Multiplexed or Demultiplexed +* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIModeConfig(u32 SCU_EMIMODE) +{ + SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/ + if (SCU_EMIMODE!=SCU_EMI_MUX) + SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/ +} + +/******************************************************************************* +* Function Name : SCU_EMIALEConfig +* Description : Configure the ALE signal (length & polarity) +* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2 +* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL) +{ + /*Configure EMI ALE Length*/ + SCU->SCR0 &=SCU_EMIALE_LEN1; + if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1) + SCU->SCR0 |= SCU_EMIALE_LEN2; + + /*Configure EMI ALE POL*/ + SCU->SCR0 &=SCU_EMIALE_POLLow; + if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow) + SCU->SCR0 |= SCU_EMIALE_POLHigh; +} + +/******************************************************************************* +* Function Name : SCU_ITConfig +* Description : ENBALE or DISABLE an SCU interrupt +* Input : -SCU_IT: interrupt mask +* -NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->ITCMSK&=~SCU_IT; /*IT enable */ + else + SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/ +} + +/******************************************************************************* +* Function Name : SCU_GetFlagStatus +* Description : Returns flag status +* Input : SCU_Flag +* Output : NONE +* Return : SET or RESET +*******************************************************************************/ +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag) +{ + if (SCU->SYSSTATUS&SCU_Flag) + return SET; + else return RESET; +} + +/******************************************************************************* +* Function Name : SCU_ClearFlag +* Description : Clears a SYSTATUS Flag +* Input : SCU_Flag +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ClearFlag(u32 SCU_Flag) +{ + SCU->SYSSTATUS = SCU_Flag; +} +/******************************************************************************* +* Function Name : SCU_GetPLLfreqValue +* Description : Gets the current PLL frequency +* Input : None +* Output : None +* Return : PLL frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPLLFreqValue(void) +{ + u8 PLL_M; + u8 PLL_N; + u8 PLL_P; + + PLL_M = SCU->PLLCONF&0xFF; + PLL_N = (SCU->PLLCONF&0xFF00)>>8; + PLL_P = (SCU->PLLCONF&0x70000)>>16; + + if ((PLL_M>0)&&(PLL_N>0)) + return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal); + if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32); + else return (SCU_GetPLLFreqValue()); +} + +/******************************************************************************* +* Function Name : SCU_GetRCLKFreqValue +* Description : Gets the current RCLK frequency +* Input : None +* Output : None +* Return : RCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetRCLKFreqValue(void) +{ + u8 RCLK_Div; + RCLK_Div = (SCU->CLKCNTR&0x1C)>>2; + if (RCLK_Div==0x5) RCLK_Div=10; + return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetHCLKFreqValue +* Description : Gets the current PCLK frequency +* Input : None +* Output : None +* Return : HCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetHCLKFreqValue(void) +{ + u8 HCLK_Div; + HCLK_Div = (SCU->CLKCNTR&0x60)>>5; + return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetPCLKFreqValue +* Description : Gets the current HCLK frequency +* Input : None +* Output : None +* Return : PCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPCLKFreqValue(void) +{ + u8 PCLK_Div; + PCLK_Div = (SCU->CLKCNTR&0x180)>>7; + return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_WakeUpLineConfig +* Description : Configures an External interrupt as WakeUp line +* Input : EXTint : 0 -> 31 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_WakeUpLineConfig(u8 EXTint) +{ + if (EXTint < 8) + { + SCU->WKUPSEL&=~0x7; + SCU->WKUPSEL|=EXTint; + } + else if (EXTint<16) + { + SCU->WKUPSEL&=~0x38; + SCU->WKUPSEL|=(EXTint-8)<<3; + } + else if (EXTint<24) + { + SCU->WKUPSEL&=~0x1C0; + SCU->WKUPSEL|=(EXTint-16)<<6; + } + else + { + SCU->WKUPSEL&=~0xE00; + SCU->WKUPSEL|=(EXTint-24)<<9; + } +} + +/******************************************************************************* +* Function Name : SCU_SpecIntRunModeConfig +* Description : Enables or Disables the Special Run mode +* Input : newstate = ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_SpecIntRunModeConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + SCU->PWRMNG |=0x8; + else + SCU->PWRMNG &=~0x8; +} +/******************************************************************************* +* Function Name : SCU_EnterIdleMode +* Description : Enters in Idle mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterIdleMode(void) +{ + SCU->PWRMNG |=0x1; +} +/******************************************************************************* +* Function Name : SCU_EnterSleepMode +* Description : Enters in Sleep mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterSleepMode(void) +{ + SCU->PWRMNG |=0x2; +} + +/******************************************************************************* +* Function Name : SCU_UARTIrDAConfig +* Description : Enable or Disable the Irda mode for UARTx +* Input : - UARTx :x=0,1 or 2 +* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART +* Output : None +* Return : None +*******************************************************************************/ +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode) +{ + if (UART_IrDA_Mode == SCU_UARTMode_IrDA) + { + if (UARTx== UART0) SCU->SCR0 |=0x400; + else if (UARTx==UART1) SCU->SCR0 |=0x800; + else SCU->SCR0 |=0x1000; + } + else + { + if (UARTx== UART0) SCU->SCR0 &=~0x400; + else if (UARTx==UART1) SCU->SCR0 &=~0x800; + else SCU->SCR0 &=~0x1000; + } +} +/******************************************************************************* +* Function Name : SCU_PFQBCCmd +* Description : Enable or Disable PFQBC +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PFQBCCmd(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->SCR0 |=0x1; + else SCU->SCR0 &=~0x1; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_ssp.c b/uc_str912/prj_template91x/str91x_lib/src/91x_ssp.c new file mode 100644 index 0000000..06bf30c --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_ssp.c @@ -0,0 +1,469 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ssp.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the SSP software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_ssp.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* SSP peripheral Enable */ +#define SSP_Enable 0x0002 +#define SSP_Disable 0xFFFD + +/* SSP Loop Back Mode Enable */ +#define SSP_LoopBackMode_Enable 0x0001 +#define SSP_LoopBackMode_Disable 0xFFFE + +/* SSP Flag Mask */ +#define SSP_Flag_Mask 0x001F + +/* SSP DMA transmit/ receive enable/disable Masks */ +#define SSP_DMA_TransmitEnable 0x0002 +#define SSP_DMA_TransmitDisable 0xFFFD +#define SSP_DMA_ReceiveEnable 0x0001 +#define SSP_DMA_ReceiveDisable 0xFFFE + +/* SSP Masks */ +#define SSP_FrameFormat_Mask 0xFFCF +#define SSP_DataSize_Mask 0xFFF0 +#define SSP_ClockRate_Mask 0x00FF +#define SSP_ClockPrescaler_Mask 0xFF00 + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SSP_DeInit +* Description : Deinitializes the SSPx peripheral registers to their default +* reset values. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DeInit(SSP_TypeDef* SSPx) +{ + if(SSPx == SSP0) + { + /* Reset the SSP0 registers values*/ + SCU_APBPeriphReset(__SSP0,ENABLE); + SCU_APBPeriphReset(__SSP0,DISABLE); + } + else if (SSPx == SSP1) + { + /* Reset the SSP1 registers values*/ + SCU_APBPeriphReset(__SSP1,ENABLE); + SCU_APBPeriphReset(__SSP1,DISABLE); + } +} + +/******************************************************************************* +* Function Name : SSP_Init +* Description : Initializes the SSPx peripheral according to the specified +* parameters in the SSP_InitTypeDef structure. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_InitStruct: pointer to a SSP_InitTypeDef structure that +* contains the configuration information for the specified SSP +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct) +{ + if(SSP_InitStruct->SSP_FrameFormat == SSP_FrameFormat_Motorola) + { + /* Set the Motorola frame format */ + SSPx->CR0 &= SSP_FrameFormat_Motorola; + /* Configure the Clock polarity */ + if(SSP_InitStruct->SSP_CPOL == SSP_CPOL_High) + { + /* SCK is held high when no data is being transfered */ + SSPx->CR0 |= SSP_CPOL_High; + } + else + { + /* SCK is held low when no data is being transfered */ + SSPx->CR0 &= SSP_CPOL_Low; + } + /* Configure the Clock Phase */ + if(SSP_InitStruct->SSP_CPHA == SSP_CPHA_2Edge) + { + /* Data captured on second clock edge */ + SSPx->CR0 |= SSP_CPHA_2Edge; + } + else + { + /* Data captured on first clock edge */ + SSPx->CR0 &= SSP_CPHA_1Edge; + } + } + /* Configure the Frame format */ + else + { + /* Clear the FRF[1:0] bits */ + SSPx->CR0 &= SSP_FrameFormat_Mask; + /* Set the TI frame format */ + SSPx->CR0 |= SSP_InitStruct->SSP_FrameFormat; + } + /* Configure the Mode */ + if(SSP_InitStruct->SSP_Mode == SSP_Mode_Slave) + { + /* Set the slave mode */ + SSPx->CR1 |= SSP_Mode_Slave; + /* Configure the Slave output */ + if(SSP_InitStruct->SSP_SlaveOutput == SSP_SlaveOutput_Disable) + { + /* Slave output disabled */ + SSPx->CR1 |= SSP_SlaveOutput_Disable; + } + else + { + /* Slave output enabled */ + SSPx->CR1 &= SSP_SlaveOutput_Enable; + } + } + else + { + /* Set the master mode */ + SSPx->CR1 &= SSP_Mode_Master; + /* Clear clock rate SCR[7:0] bits */ + SSPx->CR0 &= SSP_ClockRate_Mask; + /* Set the serial clock rate */ + SSPx->CR0 |= (SSP_InitStruct->SSP_ClockRate<<8); + /* Clear clock prescaler CPSDVSR[7:0] bits */ + SSPx->PR &= SSP_ClockPrescaler_Mask; + /* Set the serial clock prescaler */ + SSPx->PR |= SSP_InitStruct->SSP_ClockPrescaler; + } + + /* Clear data size DSS[3:0] bits */ + SSPx->CR0 &= SSP_DataSize_Mask; + /* Set the data size */ + SSPx->CR0 |= SSP_InitStruct->SSP_DataSize; +} +/******************************************************************************* +* Function Name : SSP_StructInit +* Description : Fills in a SSP_InitTypeDef structure with the reset value of +* each parameter. +* Input : SSP_InitStruct : pointer to a SSP_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct) +{ + /* Initialize the SSP_FrameFormat member */ + SSP_InitStruct->SSP_FrameFormat = SSP_FrameFormat_Motorola; + + /* Initialize the SSP_Mode member */ + SSP_InitStruct->SSP_Mode = SSP_Mode_Master; + + /* Initialize the SSP_CPOL member */ + SSP_InitStruct->SSP_CPOL = SSP_CPOL_Low; + + /* Initialize the SSP_CPHA member */ + SSP_InitStruct->SSP_CPHA = SSP_CPHA_1Edge; + + /* Initialize the SSP_DataSize member */ + SSP_InitStruct->SSP_DataSize = SSP_DataSize_8b; + + /* Initialize the SSP_SlaveOutput member */ + SSP_InitStruct->SSP_SlaveOutput = SSP_SlaveOutput_Enable; + + /* Initialize the SSP_ClockRate member */ + SSP_InitStruct->SSP_ClockRate = 0; + + /* Initialize the SSP_ClockPrescaler member */ + SSP_InitStruct->SSP_ClockPrescaler = 0; +} + +/******************************************************************************* +* Function Name : SSP_Cmd +* Description : Enables or disables the specified SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the SSPx peripheral. This parameter +* can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the SSP peripheral */ + SSPx->CR1 |= SSP_Enable; + } + else + { + /* Disable the SSP peripheral */ + SSPx->CR1 &= SSP_Disable; + } +} + +/******************************************************************************* +* Function Name : SSP_ITConfig +* Description : Enables or disables the specified SSP interrupts. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: specifies the SSP interrupts sources to be enabled +* or disabled. This parameter can be any combination of the +* following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* - NewState: new state of the specified SSP interrupts. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the selected SSP interrupts */ + SSPx->IMSCR |= SSP_IT; + } + else + { + /* Disable the selected SSP interrupts */ + SSPx->IMSCR &= ~SSP_IT; + } +} + +/******************************************************************************* +* Function Name : SSP_DMACmd +* Description : Configures the SSP0 DMA interface. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_DMATransfert : specifies the DMA transfert to be +* enabled or disabled. This parameter can be one of the +* following values: +* - SSP_DMA_Transmit: transmit Fifo DMA transfert +* - SSP_DMA_Receive : receive Fifo DMA transfert +* - NewState: new state of the DMA transfert. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_DMACmd(SSP_TypeDef* SSPx, u16 SSP_DMATransfert, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + if(SSP_DMATransfert == SSP_DMA_Transmit) + { + /* Enable DMA for the transmit FIFO */ + SSPx->DMACR |= SSP_DMA_TransmitEnable; + } + else + { + /* Enable DMA for the receive FIFO */ + SSPx->DMACR |= SSP_DMA_ReceiveEnable; + } + } + else + { + if(SSP_DMATransfert == SSP_DMA_Transmit) + { + /* Disable DMA for the transmit FIFO */ + SSPx->DMACR &= SSP_DMA_TransmitDisable; + } + else + { + /* Disable DMA for the receive FIFO */ + SSPx->DMACR &= SSP_DMA_ReceiveDisable; + } + } +} + +/******************************************************************************* +* Function Name : SSP_SendData. +* Description : Transmits a Data through the SSP peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - Data : Data to be transmitted. +* Output : None +* Return : None +*******************************************************************************/ +void SSP_SendData(SSP_TypeDef* SSPx, u16 Data) +{ + /* Write in the DR register the data to be sent */ + SSPx->DR = Data; +} + +/******************************************************************************* +* Function Name : SSP_ReceiveData. +* Description : Returns the most recent received data by the SSP peripheral. +* Input : SSPx: where x can be 0 or 1 to select the SSP peripheral. +* Output : None +* Return : The value of the received data. +*******************************************************************************/ +u16 SSP_ReceiveData(SSP_TypeDef* SSPx) +{ + /* Return the data in the DR register */ + return SSPx->DR; +} + +/******************************************************************************* +* Function Name : SSP_LoopBackMode +* Description : Enable or disable the Loop back mode for the selected SSPx peripheral. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - NewState: new state of the Loop Back mode. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None. +*******************************************************************************/ +void SSP_LoopBackMode(SSP_TypeDef* SSPx, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable loop back mode */ + SSPx->CR1 |= SSP_LoopBackMode_Enable; + } + else + { + /* Disable loop back mode */ + SSPx->CR1 &= SSP_LoopBackMode_Disable; + } +} + + + +/******************************************************************************* +* Function Name : SSP_GetFlagStatus +* Description : Checks whether the specified SSP flag is set or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: flag to check. This parameter can be one of the +* following values: +* - SSP_FLAG_Busy: busy flag +* - SSP_FLAG_RxFifoFull: Receive FIFO full flag +* - SSP_FLAG_RxFifoNotEmpty: Receive FIFO not empty flag +* - SSP_FLAG_TxFifoNotFull: Transmit FIFO not full flag +* - SSP_FLAG_TxFifoEmpty: Transmit FIFO empty flag +* - SSP_FLAG_TxFifo: Transmit FIFO half empty or less flag +* - SSP_FLAG_RxFifo: Receive FIFO half full or less flag +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : The new state of SSP_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u32 SSPReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the SSP register index */ + SSPReg = SSP_FLAG >> 5; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Find the register of the flag to check */ + if(SSPReg == 1) + { + /* The flag to check is in SR register */ + StatusReg = SSPx->SR; + } + else if (SSPReg == 2) + { + /* The flag to check is in RISR register */ + StatusReg = SSPx->RISR; + } + + /* Check the status of the specified SSP flag */ + if((StatusReg & (1 << FlagPos)) != RESET) + { + /* Return SET if the SSP flag is set */ + return SET; + } + else + { + /* Return RESET if the SSP flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearFlag +* Description : Clears the SSPx flags. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_FLAG: flags to clear. This parameter one of the +* following values: +* - SSP_FLAG_RxTimeOut: Receive timeout flag +* - SSP_FLAG_RxOverrun: Receive overrun flag +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG) +{ + u8 FlagPos = 0; + + /* Get the flag position */ + FlagPos = SSP_FLAG & SSP_Flag_Mask; + + /* Clear the selected SSP flag */ + SSPx->ICR = (1 << FlagPos); +} + +/******************************************************************************* +* Function Name : SSP_GetITStatus +* Description : Checks whether the specified SSP interrupt flag is set or not. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: interrupt flag to check. This parameter can be one +* of the following values: +* - SSP_IT_TxFifo: Transmit FIFO half empty or less interrupt +* - SSP_IT_RxFifo: Receive FIFO half full or less interrupt +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : The new state of SSP_IT flag (SET or RESET). +*******************************************************************************/ +ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Check the status of the specified interrupt flag */ + if((SSPx->MISR & SSP_IT) != RESET) + { + /* Return SET if the SSP interrupt flag is set */ + return SET; + } + else + { + /* Return RESET if SSP interrupt flag is reset */ + return RESET; + } +} + +/******************************************************************************* +* Function Name : SSP_ClearITPendingBit +* Description : Clears the pending interrupt flags. +* Input : - SSPx: where x can be 0 or 1 to select the SSP peripheral. +* - SSP_IT: interrupts pending bits to clear. This parameter +* can be any combination of the following values: +* - SSP_IT_RxTimeOut: Receive timeout interrupt +* - SSP_IT_RxOverrun: Receive overrun interrupt +* Output : None +* Return : None +*******************************************************************************/ +void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT) +{ + /* Clear the selected SSP interrupts pending bits */ + SSPx->ICR = SSP_IT; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_tim.c b/uc_str912/prj_template91x/str91x_lib/src/91x_tim.c new file mode 100644 index 0000000..7957168 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_tim.c @@ -0,0 +1,694 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_tim.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the TIM software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_tim.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* TIM Bits Masks */ + +#define TIM_PWM_MASK 0x0010 +#define TIM_OPM_MASK 0x0020 +#define TIM_OC1_ENABLE_MASK 0x0040 +#define TIM_OC1_DISABLE_MASK 0xFFBF +#define TIM_OC2_ENABLE_MASK 0x0080 +#define TIM_OC2_DISABLE_MASK 0xFF7F + +#define TIM_OLVL1_SET_MASK 0x0100 +#define TIM_OLVL1_RESET_MASK 0xFEFF + +#define TIM_OLVL2_SET_MASK 0x0200 +#define TIM_OLVL2_RESET_MASK 0xFDFF + +#define TIM_ENABLE_MASK 0x8000 +#define TIM_DISABLE_MASK 0x7FFF + +#define TIM_DMA_CLEAR_MASK 0xCFFF + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/******************************************************************************* +* Function Name : TIM_DeInit +* Description : Initializes TIM peripheral control and registers to their +* : default reset values. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if((TIMx == TIM0)||(TIMx == TIM1)) + { + SCU_APBPeriphReset(__TIM01, DISABLE); /* TIM0 & TIM1 Reset's off */ + } + else + { + SCU_APBPeriphReset(__TIM23, DISABLE); /* TIM2 & TIM3 Reset's off */ + } + + /* Set all the TIMx registers to thier default values */ + TIMx->OC1R = 0x8000; + TIMx->OC2R = 0x8000; + TIMx->CR1 = 0x0; + TIMx->CR2 = 0x1; + TIMx->CNTR = 0x1234; + TIMx->SR = 0x0; +} + +/******************************************************************************* +* Function Name : TIM_StructInit +* Description : Fills in a TIM_InitTypeDef structure with the reset value of +* each parameter. +* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure + which will be initialized. +* Output : None +* Return : None. +*******************************************************************************/ +void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct) +{ + TIM_InitStruct->TIM_Mode = 0x0000; + TIM_InitStruct->TIM_OC1_Modes = 0x0000; + TIM_InitStruct->TIM_OC2_Modes = 0x0000; + TIM_InitStruct->TIM_Clock_Source = 0x0000; + TIM_InitStruct->TIM_Clock_Edge = 0x0000; + TIM_InitStruct->TIM_OPM_INPUT_Edge = 0x0000; + TIM_InitStruct->TIM_ICAP1_Edge = 0x0000; + TIM_InitStruct->TIM_ICAP2_Edge = 0x0000; + TIM_InitStruct->TIM_Prescaler = 0x0000; + TIM_InitStruct->TIM_Pulse_Level_1 = 0x0000; + TIM_InitStruct->TIM_Pulse_Level_2 = 0x0000; + TIM_InitStruct->TIM_Period_Level = 0x0000; + TIM_InitStruct->TIM_Pulse_Length_1 = 0x0000; + TIM_InitStruct->TIM_Pulse_Length_2 = 0x0000; + TIM_InitStruct->TIM_Full_Period = 0x0000; +} + +/******************************************************************************* +* Function Name : TIM_Init +* Description : Initializes TIM peripheral according to the specified +* parameters in the TIM_InitTypeDef structure. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_InitStruct: pointer to a TIM_InitTypeDef structure that +* contains the configuration information for the specified +* TIM peripheral. +* Output : None +* Return : None +*******************************************************************************/ + +void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct) +{ +/***************************** Clock configuration ****************************/ + + if (TIM_InitStruct->TIM_Clock_Source == TIM_CLK_APB) + { + /* APB clock */ + TIMx->CR1 &= TIM_CLK_APB; + } + else + { + /* External/SCU clock */ + TIMx->CR1 |= TIM_CLK_EXTERNAL; + if (TIM_InitStruct->TIM_Clock_Edge == TIM_CLK_EDGE_RISING) + { + /* Clock rising edge */ + TIMx->CR1 |= TIM_CLK_EDGE_RISING; + } + else + { + /* Clock falling edge */ + TIMx->CR1 &= TIM_CLK_EDGE_FALLING; + } + } + +/************************** Prescaler configuration ***************************/ + + TIMx->CR2 =( TIMx->CR2 & 0xFF00 )|TIM_InitStruct->TIM_Prescaler ; + +/********************************** TIM Modes *********************************/ + + switch ( TIM_InitStruct->TIM_Mode) + { +/******************************* PWM Input mode *******************************/ + + case TIM_PWMI: + + /* Set the PWMI Bit */ + TIMx->CR1 |= TIM_PWMI; + + /* Set the first edge Level */ + if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + /* Set the Second edge Level ( Opposite of the first level ) */ + if ( TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + else + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + + break; + +/************************** Output compare channel 1 **************************/ + + case TIM_OCM_CHANNEL_1: + + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC1_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + } + + break; + +/************************** Output compare channel 2 **************************/ + + case TIM_OCM_CHANNEL_2: + + if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2; + + if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC2_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC2_ENABLE_MASK; + } + + break; + +/************************ Output compare channel 1 & 2 ************************/ + + case TIM_OCM_CHANNEL_12: + + TIMx->OC2R = TIM_InitStruct->TIM_Pulse_Length_2; + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + if (TIM_InitStruct->TIM_OC2_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC2_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC2_ENABLE_MASK; + } + + if (TIM_InitStruct->TIM_OC1_Modes == TIM_TIMING) + { + TIMx->CR1 &= TIM_OC1_DISABLE_MASK; + } + else + { + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + } + + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + if (TIM_InitStruct->TIM_Pulse_Level_2 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + break; + +/********************************** PWM mode **********************************/ + + case TIM_PWM: + + /* Set the Level During the pulse */ + if ( TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL2_RESET_MASK; + } + + /* Set the Level after the pulse */ + if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + else + { + TIMx->CR1 &= TIM_OLVL1_RESET_MASK; + } + + /* Set the OCAE */ + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + + /* Set the PWM Bit */ + TIMx->CR1 |= TIM_PWM_MASK; + + /* Set the Duty Cycle value */ + if ( TIM_InitStruct->TIM_Pulse_Length_1 < 5 ) + { + TIM_InitStruct->TIM_Pulse_Length_1 = 4; + } + + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1 - 4; + + /* Set the Full Period */ + TIMx->OC2R = TIM_InitStruct->TIM_Full_Period - 4; + + break; + +/******************************* One pulse mode *******************************/ + + case TIM_OPM: + + /* Set the Level During the pulse */ + if (TIM_InitStruct->TIM_Pulse_Level_1 == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL2_SET_MASK; + } + + /* Set the Level after the pulse */ + if (TIM_InitStruct->TIM_Period_Level == TIM_HIGH) + { + TIMx->CR1 |= TIM_OLVL1_SET_MASK; + } + + /* Set the Activation Edge on the ICAP 1 */ + if (TIM_InitStruct->TIM_OPM_INPUT_Edge == TIM_OPM_EDGE_RISING) + { + TIMx->CR1 |= TIM_OPM_EDGE_RISING; + } + + /* Set the Output Compare Function */ + TIMx->CR1 |= TIM_OC1_ENABLE_MASK; + + /* Set the One pulse mode */ + TIMx->CR1 |= TIM_OPM_MASK; + + /* Set the Pulse length */ + TIMx->OC1R = TIM_InitStruct->TIM_Pulse_Length_1; + + break; + +/*************************** Input capture channel 1 **************************/ + + case TIM_ICAP_CHANNEL_1: + + if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + break; + +/*************************** Input capture channel 2 **************************/ + + case TIM_ICAP_CHANNEL_2: + + if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + + break; + +/************************* Input capture channel 1 & 2 ************************/ + + case TIM_ICAP_CHANNEL_12: + if (TIM_InitStruct->TIM_ICAP2_Edge == TIM_ICAP2_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP2_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP2_EDGE_FALLING; + } + + if (TIM_InitStruct->TIM_ICAP1_Edge == TIM_ICAP1_EDGE_RISING) + { + TIMx->CR1 |= TIM_ICAP1_EDGE_RISING; + } + else + { + TIMx->CR1 &= TIM_ICAP1_EDGE_FALLING; + } + + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_CounterCmd +* Description : Enables or disables TIMx Counter peripheral. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_operation: specifies the new state of the TIMx Counter. +* This parameter can be one of the following values: +* - TIM_START: Start the timer counter. +* - TIM_STOP : Stop the timer counter. +* - TIM_CLEAR: Clear the timer counter. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation) +{ + switch (TIM_operation) + { + case TIM_START: + TIMx->CR1 |= TIM_ENABLE_MASK; + break; + + case TIM_STOP: + TIMx->CR1 &= TIM_DISABLE_MASK; + break; + + case TIM_CLEAR: + TIMx->CNTR = 0x1234; + break; + + default: + break; + } +} + +/******************************************************************************* +* Function Name : TIM_PrescalerConfig +* Description : This routine is used to configure the TIMx prescaler value +* (when using the APB clock). +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Prescaler: specifies the prescaler value. This parameter +* can be a value from 0x0 to 0xFF. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler) +{ + TIMx->CR2 &= 0xFF00; + TIMx->CR2 |= TIM_Prescaler; + +} +/******************************************************************************* +* Function Name : TIM_GetPrescalerValue +* Description : This routine is used to get the TIMx prescaler value +* (when using the APB clock). +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The prescaler value. +*******************************************************************************/ +u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx) +{ + return TIMx->CR2 & 0x00FF; +} + +/******************************************************************************* +* Function Name : TIM_GetCounterValue +* Description : This routine is used to get the TIMx counter value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The counter value. +*******************************************************************************/ +u16 TIM_GetCounterValue(TIM_TypeDef *TIMx) +{ + return TIMx->CNTR; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP1Value +* Description : This routine is used to get the Input Capture 1 value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The Input Capture 1 value. +*******************************************************************************/ +u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx) +{ + return TIMx->IC1R; +} + +/******************************************************************************* +* Function Name : TIM_GetICAP2Value +* Description : This routine is used to get the Input Capture 2 value. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The Input Capture 2 value. +*******************************************************************************/ +u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx) +{ + return TIMx->IC2R; +} + +/******************************************************************************* +* Function Name : TIM_SetPulse +* Description : This routine is used to set the pulse value. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Channel: specifies the needed channel. +* This parameter can be one of the following values: +* - TIM_PWM_OC1_Channel: PWM/Output Compare 1 Channel +* - TIM_OC2_Channel : Output Compare 2 Channel +* Input3 : TIM_Pulse: specifies the new pulse value. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse) +{ + if (TIM_Channel == TIM_PWM_OC1_Channel) + { + TIMx->OC1R = TIM_Pulse; + } + else + { + TIMx->OC2R = TIM_Pulse; + } +} +/******************************************************************************* +* Function Name : TIM_GetFlagStatus +* Description : Checks whether the specified TIMx flag is set or not. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Flag: specifies the flag to check. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture Channel 1 Flag +* - TIM_FLAG_IC2: Input Capture Channel 2 Flag +* - TIM_FLAG_TO : Timer Overflow Flag +* - TIM_FLAG_OC1: Output Compare Channel 1 Flag +* - TIM_FLAG_OC2: Output Compare Channel 2 Flag +* Output : None +* Return : The NewState of the TIM_Flag (SET or RESET). +*******************************************************************************/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag) +{ + if((TIMx->SR & TIM_Flag) == RESET) + { + return RESET; + } + else + { + return SET; + } +} + +/******************************************************************************* +* Function Name : TIM_ClearFlag +* Description : Clears the TIM Flag passed as a parameter. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Flag: specifies the flag to clear. +* This parameter can be one of the following values: +* - TIM_FLAG_IC1: Input Capture Channel 1 Flag +* - TIM_FLAG_IC2: Input Capture Channel 2 Flag +* - TIM_FLAG_TO : Timer Overflow Flag +* - TIM_FLAG_OC1: Output Compare Channel 1 Flag +* - TIM_FLAG_OC2: Output Compare Channel 2 Flag +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag) +{ + /* Clear TIM_Flag */ + TIMx->SR &= ~TIM_Flag; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPulse +* Description : This routine is used to get the Pulse value in PWMI Mode. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The pulse value. +*******************************************************************************/ +u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx) +{ + return TIMx->IC2R; +} + +/******************************************************************************* +* Function Name : TIM_GetPWMIPeriod +* Description : This routine is used to get the Period value in PWMI Mode. +* Input : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Output : None +* Return : The period value. +*******************************************************************************/ +u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx) +{ + return TIMx->IC1R; +} + +/******************************************************************************* +* Function Name : TIM_ITConfig +* Description : Configures the Timer interrupt source. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_IT: specifies the TIM interrupt source to be enabled. +* This parameter can be one of the following values: +* - TIM_IT_IC1: Input Capture 1 Interrupt source. +* - TIM_IT_OC1: Output Compare 1 Interrupt source. +* - TIM_IT_TO : Timer Overflow Interrupt source. +* - TIM_IT_IC2: Input Capture 2 Interrupt source. +* - TIM_IT_OC2: Output Compare 2 Interrupt source. +* Input3 : TIM_Newstate: specifies the new state of the TIMx IT. +* This parameter can be one of the following values: +* - ENABLE : Enable the needed interrupt. +* - DISABLE: Disable the needed interrupt. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate) +{ + if(TIM_Newstate == ENABLE) + { + TIMx->CR2 = (TIMx->CR2 & 0x00FF) | TIM_IT; + } + else + { + TIMx->CR2 &= ~TIM_IT; + } +} + +/******************************************************************************* +* Function Name : TIM_DMAConfig +* Description : Configures the Timer DMA source. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_DMA_Souces: specifies the TIM DMA source to be selected. +* This parameter can be one of the following values: +* - TIM_DMA_IC1: Input Capture 1 DMA source. +* - TIM_DMA_OCA1 Output Compare 1 DMA source. +* - TIM_DMA_TO: Timer Overflow DMA source. +* - TIM_DMA_IC2: Input Capture 2 DMA source. +* - TIM_DMA_OC2: Output Compare 2 DMA source. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources) +{ + /* Reset the DMAS[1:0] bits */ + TIMx->CR1 &= TIM_DMA_CLEAR_MASK; + /* Set the DMAS[1:0] bits according to TIM_DMA_Sources parameter */ + TIMx->CR1 |= TIM_DMA_Sources; +} + +/******************************************************************************* +* Function Name : TIM_DMACmd +* Description : Enables or disables TIMx DMA peripheral. +* Input1 : TIMx: where x can be from 0 to 3 to select the TIM +* peripheral. +* Input2 : TIM_Newstate: new state of the TIMx DMA peripheral +* This parameter can be one of the following values: +* - ENABLE : Enable the TIMx DMA. +* - DISABLE: Disable the TIMx DMA. +* Output : None +* Return : None +*******************************************************************************/ +void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate) +{ + if (TIM_Newstate == ENABLE) + { + TIMx->CR2 |= TIM_DMA_ENABLE; + } + else + { + TIMx->CR2 &= TIM_DMA_DISABLE; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_uart.c b/uc_str912/prj_template91x/str91x_lib/src/91x_uart.c new file mode 100644 index 0000000..3c87216 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_uart.c @@ -0,0 +1,658 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_uart.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the UART software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_uart.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* UART IrDA Mask */ +#define UART_IrDA_Disable_Mask 0xFFFD /* IrDA Disable Mask */ +#define UART_IrDA_Enable_Mask 0x0002 /* IrDA Enable Mask */ +#define IrDA_LowPower_Enable_Mask 0x0004 /*IrDA lower power mode enable*/ +#define IrDA_LowPower_Disable_Mask 0xFFFB /*IrDA lower power mode enable*/ + +/* UART Mask */ +#define UART_Enable_Mask 0x0001 /* UART Enable Mask */ +#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */ + +/* UART LoopBack */ +#define UART_LoopBack_Disable_Mask 0xFF7F /* LoopBack Disable Mask */ +#define UART_LoopBack_Enable_Mask 0x0080 /* LoopBack Enable Mask */ + +#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */ +#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */ +#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */ +#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */ +#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask*/ +#define UART_FLAG_Mask 0x1F /* UART Flag Mask */ +#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */ +#define UART_RTS_LowLevel_Mask 0x0800 /* RTS signal is low */ +#define UART_RTS_HighLevel_Mask 0xF7FF /* RTS signal is High */ +#define UART_DTR_LowLevel_Mask 0x0400 /* DTR signal is low */ +#define UART_DTR_HighLevel_Mask 0xFBFF /* DTR signal is High */ +#define UART_ClearFlag_Mask 0xAA /* Clear Flag Mask */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + /******************************************************************************* +* Function Name : UART_DeInit +* Description : Deinitializes the UARTx peripheral registers +* to their default reset values. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DeInit(UART_TypeDef* UARTx) +{ + /* Reset the UARTx registers values */ + if(UARTx == UART0) + { + SCU_APBPeriphReset(__UART0,ENABLE); + SCU_APBPeriphReset(__UART0,DISABLE); + } + else if(UARTx == UART1) + { + SCU_APBPeriphReset(__UART1,ENABLE); + SCU_APBPeriphReset(__UART1,DISABLE); + } + else if(UARTx == UART2) + { + SCU_APBPeriphReset(__UART2,ENABLE); + SCU_APBPeriphReset(__UART2,DISABLE); + } +} + +/******************************************************************************* +* Function Name : UART_Init +* Description : Initializes the UARTx peripheral according to the specified +* parameters in the UART_InitStruct . +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_InitStruct: pointer to a UART_InitTypeDef structure +* that contains the configuration information for the +* specified UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + + u64 UART_MainClock = 0; + u32 IntegerDivider = 0; + u32 FractionalDivider = 0; + + /* Clear the LCR[6:5] bits */ + UARTx->LCR &= UART_WordLength_Mask; + /* Set the LCR[6:5] bits according to UART_WordLength value */ + UARTx->LCR |= UART_InitStruct->UART_WordLength; + + /* Choose Stop Bits */ + if(UART_InitStruct->UART_StopBits == UART_StopBits_2) + { + /* 2 Stop Bit */ + UARTx->LCR |= UART_StopBits_2; + } + else + { + /* One Stop Bits */ + UARTx->LCR &= UART_StopBits_1; + } + + /* Configure the Parity */ + /* Clear the LCR[7]and LCR[2:1] bits */ + UARTx->LCR &= UART_Parity_Mask; + /* Set the LCR[7]and LCR[2:1] bits according to UART_Parity value */ + UARTx->LCR |= UART_InitStruct->UART_Parity; + + /* Configure the BaudRate */ + UART_MainClock = (SCU_GetMCLKFreqValue())*1000; + if((SCU->CLKCNTR & 0x200) != 0x200) + { + UART_MainClock = UART_MainClock/2; + } + /* Determine the integer part */ + IntegerDivider = ((100) * (UART_MainClock) / (16 * (UART_InitStruct->UART_BaudRate))); + UARTx->IBRD = IntegerDivider / 100; + + /* Determine the fractional part */ + FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD)); + UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100)); + + /* Choose the Hardware Flow Control */ + /* Clear the CR[15:14] bits */ + UARTx->CR &= UART_HardwareFlowControl_Mask; + /* Set the CR[15:14] bits according to UART_HardwareFlowControl value */ + UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl; + + /* Configure the UART mode */ + /* Clear the CR[9:8] bits */ + UARTx->CR &= UART_Mode_Mask; + /* Set the CR[9:8] bits according to UART_Mode value */ + UARTx->CR |= UART_InitStruct->UART_Mode; + + /* Enable or disable the FIFOs */ + /* Set the FIFOs Levels */ + if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable) + { + /* Enable the FIFOs */ + UARTx->LCR |= UART_FIFO_Enable; + + /* Clear TXIFLSEL and RXIFLSEL bits */ + UARTx->IFLS &= UART_TxRxFIFOLevel_Mask; + + /* Set RXIFLSEL bits according to UART_RxFIFOLevel value */ + UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3); + + /* Set TXIFLSEL bits according to UART_TxFIFOLevel value */ + UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel; + } + else + { + /* Disable the FIFOs */ + UARTx->LCR &= UART_FIFO_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_StructInit +* Description : Fills each UART_InitStruct member with its reset value. +* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which +* will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* Reset the UART_InitStruct members */ + UART_InitStruct->UART_WordLength = UART_WordLength_8D; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_Odd ; + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx; + UART_InitStruct->UART_FIFO = UART_FIFO_Enable; + UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2; + UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2; +} + +/******************************************************************************* +* Function Name : UART_Cmd +* Description : Enables or disables the specified UART peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the selected UART by setting the UARTEN bit in the CR register */ + UARTx->CR |= UART_Enable_Mask; + } + else + { + /* Disable the selected UART by clearing the UARTEN bit in the CR register */ + UARTx->CR &= UART_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_ITConfig +* Description : Enables or disables the specified UART interrupts. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_IT: specifies the UART interrupts sources to be +* enabled or disabled. This parameter can be any combination +* of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enables the selected interrupts */ + UARTx->IMSC |= UART_IT; + } + else + { + /* Disables the selected interrupts */ + UARTx->IMSC &= ~UART_IT; + } +} + +/******************************************************************************* +* Function Name : UART_DMAConfig +* Description : Configures the UARTx’s DMA interface. +* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral +* - UART_DMAOnError: specifies the DMA on error request. +* This parameter can be: +* - UART_DMAOnError_Enable: DMA receive request enabled +* when the UART error interrupt is asserted. +* - UART_DMAOnError_Disable: DMA receive request disabled +* when the UART error interrupt is asserted. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError) +{ + if(UART_DMAOnError == UART_DMAOnError_Enable) + { + UARTx->DMACR &= UART_DMAOnError_Enable; + } + else + { + UARTx->DMACR |= UART_DMAOnError_Disable; + } +} + +/******************************************************************************* +* Function Name : UART_DMACmd +* Description : Enables or disables the UARTx’s DMA interface. +* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral +* - UART_DMAReq: enables or disables the request of DMA from UART. +* This parameter can be: +* - UART_DMAReq_Tx: Transmit DMA Enable +* - UART_DMAReq_Rx: Receive DMA Enable +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState) +{ + if(UART_DMAReq == UART_DMAReq_Tx) + { + if(NewState == ENABLE) + { + UARTx->DMACR |= UART_DMAReq_Tx; + } + else + { + UARTx->DMACR &= ~UART_DMAReq_Tx; + } + } + + if(UART_DMAReq == UART_DMAReq_Rx) + { + if(NewState == ENABLE) + { + UARTx->DMACR |= UART_DMAReq_Rx; + } + else + { + UARTx->DMACR &= ~UART_DMAReq_Rx; + } + } +} + +/******************************************************************************* +* Function Name : UART_LoopBackConfig +* Description : Enables or disables the LoopBack mode. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState) +{ + if (NewState == ENABLE) + { + /* Enable the LoopBack mode of the specified UART */ + UARTx->CR |= UART_LoopBack_Enable_Mask; + } + else + { + /* Disable the LoopBack mode of the specified UART */ + UARTx->CR &= UART_LoopBack_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_GetFlagStatus +* Description : Checks whether the specified UART flag is set or not. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral +* - UART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - UART_FLAG_OverrunError: Overrun error flag +* - UART_FLAG_Break: break error flag +* - UART_FLAG_ParityError: parity error flag +* - UART_FLAG_FrameError: frame error flag +* - UART_FLAG_RI: RI flag +* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag +* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag +* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag +* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag +* - UART_FLAG_Busy: UART Busy flag +* - UART_FLAG_CTS: CTS flag +* - UART_FLAG_DCD: DCD flag +* - UART_FLAG_DSR: DSR flag +* - UART_RawIT_OverrunError: Overrun Error interrupt flag +* - UART_RawIT_BreakError: Break Error interrupt flag +* - UART_RawIT_ParityError: Parity Error interrupt flag +* - UART_RawIT_FrameError: Frame Error interrupt flag +* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag +* - UART_RawIT_Transmit: Transmit interrupt flag +* - UART_RawIT_Receive: Receive interrupt flag +* - UART_RawIT_DSR: DSR interrupt flag +* - UART_RawIT_DCD: DCD interrupt flag +* - UART_RawIT_CTS: CTS interrupt flag +* - UART_RawIT_RI: RI interrupt flag +* Output : None +* Return : The new state of UART_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG) +{ + + u32 UARTReg = 0, FlagPos = 0; + u32 StatusReg = 0; + + /* Get the UART register index */ + UARTReg = UART_FLAG >> 5; + + /* Get the flag position */ + FlagPos = UART_FLAG & UART_FLAG_Mask; + + if(UARTReg == 1) /* The flag to check is in RSR register */ + { + StatusReg = UARTx->RSECR; + } + else if (UARTReg == 2) /* The flag to check is in FR register */ + { + StatusReg = UARTx->FR; + } + else if(UARTReg == 3) /* The flag to check is in RIS register */ + { + StatusReg = UARTx->RIS; + } + + if((StatusReg & (1 << FlagPos))!= RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearFlag +* Description : Clears the UARTx’s flags(Frame, Parity, Break, Overrun error). +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearFlag(UART_TypeDef* UARTx) +{ + /* Clear the flag */ + UARTx->RSECR = UART_ClearFlag_Mask; +} + +/******************************************************************************* +* Function Name : UART_GetITStatus +* Description : Checks whether the specified UART interrupt has occured or not. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to be checked. +* This parameter can be one of the following values: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* Output : None +* Return : The new state of UART_IT (SET or RESET). +*******************************************************************************/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT) +{ + if((UARTx->MIS & UART_IT) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : UART_ClearITPendingBit +* Description : Clears the UARTx’s interrupt pending bits. +* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral. +* - UART_IT: specifies the interrupt pending bit to clear. +* More than one interrupt can be cleared using the “|” operator. +* This parameter can be: +* - UART_IT_OverrunError: Overrun Error interrupt +* - UART_IT_BreakError: Break Error interrupt +* - UART_IT_ParityError: Parity Error interrupt +* - UART_IT_FrameError: Frame Error interrupt +* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt +* - UART_IT_Transmit: Transmit interrupt +* - UART_IT_Receive: Receive interrupt +* - UART_IT_DSR: DSR interrupt +* - UART_IT_DCD: DCD interrupt +* - UART_IT_CTS: CTS interrupt +* - UART_IT_RI: RI interrupt +* Output : None +* Return : None +*******************************************************************************/ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT) +{ + /* Clear the specified interrupt */ + UARTx->ICR = UART_IT; +} + +/******************************************************************************* +* Function Name : UART_IrDALowPowerConfig +* Description : Sets the IrDA low power mode +* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. +* - NewState: new state of the UARTIrDA peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState) +{ + UART_TypeDef* UARTx; + + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + + if (NewState == ENABLE) + { + UARTx->CR |= IrDA_LowPower_Enable_Mask; + } + else + { + UARTx->CR &= IrDA_LowPower_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_IrDASetCounter +* Description : Sets the IrDA counter divisor value. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART/IrDA peripheral. +* - IrDA_Counter: IrDA counter divisor new value n low power mode(Hz). +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter) +{ + UART_TypeDef* UARTx; + u32 APBClock; + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + /* Get the APB frequency */ + APBClock = (SCU_GetPCLKFreqValue())*1000; + /* Determine the Counter Divisor part */ + UARTx->ILPR = (((APBClock*10) / ( IrDA_Counter)) + 5 )/10; + } + +/******************************************************************************* +* Function Name : UART_IrDACmd +* Description : Enables or disables the UARTx’s IrDA interface. +* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral +* - NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void UART_IrDACmd(u8 IrDAx, FunctionalState NewState) +{ + UART_TypeDef* UARTx; + + switch(IrDAx) + { + case IrDA0: UARTx = UART0; + break; + case IrDA1: UARTx = UART1; + break; + case IrDA2: UARTx = UART2; + break; + } + if(NewState == ENABLE) + { + /* Enable the IrDA mode of the specified UART */ + UARTx->CR |= UART_IrDA_Enable_Mask; + } + else + { + /* Disable the IrDA mode of the specified UART */ + UARTx->CR &= UART_IrDA_Disable_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_SendData +* Description : Transmits signle Byte of data through the UARTx peripheral. +* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* - Data: the byte to transmit +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendData(UART_TypeDef* UARTx, u8 Data) +{ + /* Transmit one byte */ + UARTx->DR = Data; +} + +/******************************************************************************* +* Function Name : UART_ReceiveData +* Description : Returns the most recent received Byte by the UARTx peripheral. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : The received data +*******************************************************************************/ +u8 UART_ReceiveData(UART_TypeDef* UARTx) +{ + /* Receive one byte */ + return ((u8)UARTx->DR); +} + +/******************************************************************************* +* Function Name : UART_SendBreak +* Description : Transmits break characters. +* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void UART_SendBreak(UART_TypeDef* UARTx) +{ + /* Send break characters */ + UARTx->LCR |= UART_BreakChar_Mask; +} + +/******************************************************************************* +* Function Name : UART_RTSConfig +* Description : Sets or Resets the RTS signal +* Input : - LevelState: new state of the RTS signal for UART0 only. +* This parameter can be: LowLevel or HighLevel +* Output : None +* Return : None +*******************************************************************************/ +void UART_RTSConfig(UART_LevelTypeDef LevelState) +{ + if(LevelState == LowLevel) + { + UART0->CR |= UART_RTS_LowLevel_Mask; + } + else + { + UART0->CR &= UART_RTS_HighLevel_Mask; + } +} + +/******************************************************************************* +* Function Name : UART_DTRConfig +* Description : Sets or Resets the DTR signal for UART0 only +* Input : - LevelState: new state of the DTR signal. +* This parameter can be: LowLevel or HighLevel +* Output : None +* Return : None +*******************************************************************************/ +void UART_DTRConfig(UART_LevelTypeDef LevelState) +{ + if(LevelState == LowLevel) + { + UART0->CR |= UART_DTR_LowLevel_Mask; + } + else + { + UART0->CR &= UART_DTR_HighLevel_Mask; + } +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_vic.c b/uc_str912/prj_template91x/str91x_lib/src/91x_vic.c new file mode 100644 index 0000000..fecb890 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_vic.c @@ -0,0 +1,830 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_vic.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the VIC software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_vic.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define VIC_REGISTER_NUMBER 16 +#define VIC_PROTECTION_ENABLE_MASK 0x1 +#define VIC_PROTECTION_DISABLE_MASK 0xFFFFFFFE +#define VIC_VECTOR_ENABLE_MASK 0x20 +#define VIC_IT_SOURCE_MASK 0xFFFFFFE0 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode); +static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ + void (*VIC_VectAddress)(void)); +static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority); +static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority); + +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : VIC_DeInit +* Description : Deinitialize the VIC module registers to their default reset +* values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void VIC_DeInit(void) +{ + SCU_AHBPeriphReset(__VIC, ENABLE); /* VIC peripheral is under Reset */ + SCU_AHBPeriphReset(__VIC, DISABLE); /* VIC peripheral Reset off */ +} + +/******************************************************************************* +* Function Name : VIC_GetIRQStatus +* Description : Get the status of interrupts after IRQ masking. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the IRQ interrupt after masking (SET or RESET). +*******************************************************************************/ +FlagStatus VIC_GetIRQStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->ISR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->ISR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_GetFIQStatus +* Description : Get the status of interrupts after FIQ masking +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the FIQ interrupt after masking (SET or RESET) +*******************************************************************************/ +FlagStatus VIC_GetFIQStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->RINTSR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->RINTSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_GetSourceITStatus +* Description : Get the status of the source interrupts before masking. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The status of the source interrupt before masking +*******************************************************************************/ +FlagStatus VIC_GetSourceITStatus(u16 VIC_Source) +{ + u32 VIC_Mask = 1; + if (VIC_Source < VIC_REGISTER_NUMBER) + { + if ((VIC0->FSR | VIC_Mask << VIC_Source) != RESET) + return SET; + else + return RESET; + } + else + { + if ((VIC1->FSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET) + return SET; + else + return RESET; + } +} + +/******************************************************************************* +* Function Name : VIC_ITModeConfig +* Description : Select the type of interrupt (IRQ or FIQ) +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_LineMode :specifies the type of interrupt of the source +* line. This parameter can be one of the following values: +* - VIC_IRQ: the correspondent line is configured as IRQ. +* - VIC_FIQ: the correspondent line is configured as FIQ. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode) +{ + u32 VIC_Mask = 1; + + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + { + if (VIC_LineMode == VIC_IRQ) + VIC0->INTSR &= ~(VIC_Mask << VIC_Source); + else /* VIC_LineMode == VIC_FIQ */ + VIC0->INTSR |= (VIC_Mask << VIC_Source); + } + else /* VIC1 */ + { + if (VIC_LineMode == VIC_IRQ) + VIC1->INTSR &= ~(VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + else /* VIC_LineMode == VIC_FIQ */ + VIC1->INTSR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_ITCmd +* Description : Enable or disable the interrupt request lines. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : FMI_NewState: specifies the line status. +* This parameter can be one of the following values: +* - ENABLE: The line is enabled. +* - DISABLE: The line is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState) +{ + u32 VIC_Mask = 1; + + if (VIC_NewState == ENABLE) + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->INTER |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->INTER |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } + else /* VIC_NewState == DISABLE */ + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->INTECR |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->INTECR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_SWITCmd +* Description : Generate a software interrupt for the specific source +* interrupt. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : FMI_NewState: specifies the software interrupt status. +* This parameter can be one of the following values: +* - ENABLE: The software interrupt is enabled. +* - DISABLE: The software interrupt is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState) +{ + u32 VIC_Mask = 1; + + if (VIC_NewState == ENABLE) + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->SWINTR |= (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->SWINTR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } + else /* VIC_NewState == DISABLE */ + { + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->SWINTCR = (VIC_Mask << VIC_Source); + else /* VIC1 */ + VIC1->SWINTCR = (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)); + } +} + +/******************************************************************************* +* Function Name : VIC_ProtectionCmd +* Description : Enable or Disable the register access protection. +* Input : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: The protection is enabled. +* - DISABLE: The protection is disabled. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_ProtectionCmd(FunctionalState VIC_NewState) +{ + if (VIC_NewState == ENABLE) + { + VIC0->PER |= VIC_PROTECTION_ENABLE_MASK; + VIC1->PER |= VIC_PROTECTION_ENABLE_MASK; + } + else + { + VIC0->PER &= VIC_PROTECTION_DISABLE_MASK; + VIC1->PER &= VIC_PROTECTION_DISABLE_MASK; + } +} + +/******************************************************************************* +* Function Name : VIC_GetCurrentISRAdd +* Description : Get the address of the current active ISR. +* Input : VICx: specifies the VIC peripheral +* This parameter can be one of the following values: +* - VIC0: To select VIC0. +* - VIC1: To select VIC1. +* Output : None +* Return : The Address of the active ISR. +*******************************************************************************/ +u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx) +{ + return VICx->VAR; +} + +/******************************************************************************* +* Function Name : VIC_ISRVectAddConfig +* Description : Configuration of the ISR vector address. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Input3 : void (*VIC_VectAddress)(void): specifies the ISR vector +* address pointer. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \ + void (*VIC_VectAddress)(void)) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->VAiR[VIC_Priority] = (u32)VIC_VectAddress; + else /* VIC1 */ + VIC1->VAiR[VIC_Priority] = (u32)VIC_VectAddress; +} + +/******************************************************************************* +* Function Name : VIC_GetISRVectAdd +* Description : Get the ISR vector address of the correspondent line. +* Input : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Output : None +* Return : The correspondent ISR vector address. +*******************************************************************************/ +u32 VIC_GetISRVectAdd(u16 VIC_Source) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + return VIC0->VAiR[VIC_Source]; + else /* VIC1 */ + return VIC1->VAiR[VIC_Source - VIC_REGISTER_NUMBER]; +} + +/******************************************************************************* +* Function Name : VIC_VectEnableConfig +* Description : Enable the vector interrupt. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + VIC0->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; + else /* VIC1 */ + VIC1->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK; +} + +/******************************************************************************* +* Function Name : VIC_ITSourceConfig +* Description : Select the interrupt source. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority) +{ + if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */ + { + VIC0->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; + VIC0->VCiR[VIC_Priority] |= VIC_Source; + } + else /* VIC1 */ + { + VIC1->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK; + VIC1->VCiR[VIC_Priority] |= VIC_Source - VIC_REGISTER_NUMBER; + } +} + +/******************************************************************************* +* Function Name : VIC_Config +* Description : Configure the ISR, the line, the mode and the priority for +* each interrupt source line. +* Input1 : VIC_Source: specifies the number of the source line. +* This parameter can be one of the following values: +* - WDG_ITLine : VIC source 0 +* - SW_ITLine : VIC source 1 +* - ARMRX_ITLine : VIC source 2 +* - ARMTX_ITLine : VIC source 3 +* - TIM0_ITLine : VIC source 4 +* - TIM1_ITLine : VIC source 5 +* - TIM2_ITLine : VIC source 6 +* - TIM3_ITLine : VIC source 7 +* - USBHP_ITLine : VIC source 8 +* - USBLP_ITLine : VIC source 9 +* - SCU_ITLine : VIC source 10 +* - ENET_ITLine : VIC source 11 +* - DMA_ITLine : VIC source 12 +* - CAN_ITLine : VIC source 13 +* - MC_ITLine : VIC source 14 +* - ADC_ITLine : VIC source 15 +* - UART0_ITLine : VIC source 16 +* - UART1_ITLine : VIC source 17 +* - UART2_ITLine : VIC source 18 +* - I2C0_ITLine : VIC source 19 +* - I2C1_ITLine : VIC source 20 +* - SSP0_ITLine : VIC source 21 +* - SSP1_ITLine : VIC source 22 +* - LVD_ITLine : VIC source 23 +* - RTC_ITLine : VIC source 24 +* - WIU_ITLine : VIC source 25 +* - EXTIT0_ITLine: VIC source 26 +* - EXTIT1_ITLine: VIC source 27 +* - EXTIT2_ITLine: VIC source 28 +* - EXTIT3_ITLine: VIC source 29 +* - USBWU_ITLine : VIC source 30 +* - PFQBC_ITLine : VIC source 31 +* Input2 : VIC_LineMode :specifies the type of interrupt of the source +* line. This parameter can be one of the following values: +* - VIC_IRQ: the correspondent line is configured as IRQ. +* - VIC_FIQ: the correspondent line is configured as FIQ. +* Input3 : VIC_Priority: specifies the priority of the interrupt. +* It can be a value from 0 to 15. 0 is the highest priority. +* Output : None +* Return : None +*******************************************************************************/ +void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority) +{ + switch (VIC_Source) + { + case 0: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WDG_IRQHandler); + break; + + case 1: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SW_IRQHandler); + break; + + case 2: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMRX_IRQHandler); + break; + + case 3: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMTX_IRQHandler); + break; + + case 4: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM0_IRQHandler); + break; + + case 5: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM1_IRQHandler); + break; + + case 6: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM2_IRQHandler); + break; + + case 7: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM3_IRQHandler); + break; + + case 8: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBHP_IRQHandler); + break; + + case 9: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBLP_IRQHandler); + break; + + case 10: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SCU_IRQHandler); + break; + + case 11: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ENET_IRQHandler); + break; + + case 12: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, DMA_IRQHandler); + break; + + case 13: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, CAN_IRQHandler); + break; + + case 14: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, MC_IRQHandler); + break; + + case 15: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ADC_IRQHandler); + break; + + case 16: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART0_IRQHandler); + break; + + case 17: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART1_IRQHandler); + break; + + case 18: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART2_IRQHandler); + break; + + case 19: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C0_IRQHandler); + break; + + case 20: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C1_IRQHandler); + break; + + case 21: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP0_IRQHandler); + break; + + case 22: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP1_IRQHandler); + break; + + case 23: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, LVD_IRQHandler); + break; + + case 24: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, RTC_IRQHandler); + break; + + case 25: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WIU_IRQHandler); + break; + + case 26: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT0_IRQHandler); + break; + + case 27: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT1_IRQHandler); + break; + + case 28: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT2_IRQHandler); + break; + + case 29: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT3_IRQHandler); + break; + + case 30: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBWU_IRQHandler); + break; + + case 31: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, PFQBC_IRQHandler); + break; + + default: break; + } + VIC_ITModeConfig(VIC_Source, VIC_LineMode); + VIC_VectEnableConfig(VIC_Source, VIC_Priority); + VIC_ITSourceConfig(VIC_Source, VIC_Priority); +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_wdg.c b/uc_str912/prj_template91x/str91x_lib/src/91x_wdg.c new file mode 100644 index 0000000..f933635 --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_wdg.c @@ -0,0 +1,277 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wdg.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the WDG software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_wdg.h" +#include "91x_scu.h" +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + + +/* WDG End of Count interrupt Flag */ +#define WDG_FLAG_EC 0x0001 + + +/* WDG End of Count interrupt request */ +#define WDG_IT_EC 0x0001 + + + +/* WDG Start/Stop counter */ +#define WDG_Counter_Start 0x0002 +#define WDG_Counter_Stop 0xFFFD + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Registers reset value */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/****************************************************************************** +* Function Name : WDG_DeInit +* Description : Deinitializes the WDG peripheral registers to their default +* reset values. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_DeInit(void) +{ + + SCU_APBPeriphReset(__WDG, ENABLE); /*WDG peripheral under Reset */ + SCU_APBPeriphReset(__WDG, DISABLE); /*WDG peripheral Reset off*/ + +} + +/******************************************************************************* +* Function Name : WDG_StructInit +* Description : Fills the WDG_InitTypeDef structure member with its reset +* value. +* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct) +{ + /* Select the Watchdog running mode*/ + WDG_InitStruct->WDG_Mode = WDG_Mode_Timer; + + /* Select the source clock */ + WDG_InitStruct-> WDG_ClockSource = WDG_ClockSource_Apb; + + /* Initialize Prescaler */ + WDG_InitStruct->WDG_Prescaler =0xFF; + + /* Initialize Preload */ + WDG_InitStruct->WDG_Preload =0xFFFF; + + +} + +/******************************************************************************* +* Function Name : WDG_Init +* Description : Initializes WDG peripheral according to the specified +* parameters in the WDG_InitStruct. +* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that +* contains the configuration information for the WDG peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Init(WDG_InitTypeDef* WDG_InitStruct) +{ + + + if(WDG_InitStruct->WDG_ClockSource == WDG_ClockSource_Apb) + { + /* Select The APB clock as clock source */ + WDG->CR &= WDG_ClockSource_Apb; + } + + else + { + /* Select the RTC clock as source */ + WDG->CR |= WDG_ClockSource_Rtc ; + } + + + /* Configure WDG Prescaler register value */ + WDG->PR = WDG_InitStruct->WDG_Prescaler; + + /* Configure WDG Pre-load register value */ + WDG->VR = WDG_InitStruct->WDG_Preload ; + + + if(WDG_InitStruct->WDG_Mode == WDG_Mode_Timer) + { + /* Select Timer mode */ + WDG->CR &= WDG_Mode_Timer; + } + else + { + /* Select WDG mode */ + WDG->CR |= WDG_Mode_Wdg ; + } + + +} + +/******************************************************************************* +* Function Name : WDG_Cmd +* Description : Enables or disables the WDG peripheral. +* Input : NewState: new state of the WDG peripheral (Newstate can be +* ENABLE or DISABLE) +* Output : None +* Return : None +*******************************************************************************/ +void WDG_Cmd(FunctionalState NewState ) +{ + if((WDG->CR & WDG_Mode_Wdg) == 0) + { + /* Timer mode */ + if(NewState == ENABLE) + { + /* Start timer by setting SC bit in Control register */ + WDG->CR |= WDG_Counter_Start; + } + else + { + /* Stop timer by clearning SC bit in Control register */ + WDG->CR &= WDG_Counter_Stop; + } + } + else + { + /* Watchdog mode */ + if(NewState == ENABLE) + { + WDG->KR = WDG_KeyValue1; + WDG->KR = WDG_KeyValue2; + } + } +} + +/******************************************************************************* +* Function Name : WDG_ITConfig +* Description : Enables or disables the WDG End of Count(EC) interrupt. +* Input : Newstate: new state of the End of Count(EC) WDG interrupt. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ITConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + /* Enable the End of Count interrupt */ + WDG->MR |= WDG_IT_EC; + } + else + { + /* Disable the End of Count interrupt */ + WDG->MR &= ~WDG_IT_EC; + } +} + +/******************************************************************************* +* Function Name : WDG_GetCounter +* Description : Gets the WDG’s current counter value. +* Input : None +* Output : None +* Return : The WDG current counter value +*******************************************************************************/ +u16 WDG_GetCounter(void) +{ + return WDG->CNT; +} + + + + +/******************************************************************************* +* Function Name : WDG_GetITStatus +* Description : Checks whether the WDG End of Count(EC) interrupt is occured or not. +* Input : None +* Output : None +* Return : The new state of WDG_IT (SET or RESET). +*******************************************************************************/ +ITStatus WDG_GetITStatus(void) +{ + if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET )) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WDG_ClearITPendingBit +* Description : Clears the WDG's End of Count(EC) interrupt pending bit. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearITPendingBit(void) +{ + /* Clear the EC pending bit */ + WDG->SR &= ~WDG_IT_EC; + +} + +/******************************************************************************* +* Function Name : WDG_ClearFlag +* Description : Clears the WDG's End of Count(EC) Flag. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_ClearFlag(void) +{ + /* Clear the EC Flag */ + + WDG->SR &= ~WDG_FLAG_EC; + +} + + +/******************************************************************************* +* Function Name : WDG_GetFlagStatus +* Description : Checks whether the WDG End of Count(EC) flag is set or not. +* Input : None +* Output : None +* Return : The new state of the WDG_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus WDG_GetFlagStatus(void) +{ + if((WDG->SR & WDG_FLAG_EC) != RESET ) + { + return SET; + } + else + { + return RESET; + } +} + + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_template91x/str91x_lib/src/91x_wiu.c b/uc_str912/prj_template91x/str91x_lib/src/91x_wiu.c new file mode 100644 index 0000000..3154a3c --- /dev/null +++ b/uc_str912/prj_template91x/str91x_lib/src/91x_wiu.c @@ -0,0 +1,190 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_wiu.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the WIU software functions. +********************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +/* Standard include ----------------------------------------------------------*/ +#include "91x_wiu.h" +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/****************************************************************************** +* Function Name : WIU_Init +* Description : Initializes the WIU unit according to the specified parameters +* in the WIU_InitTypeDef structure. +* Input : WIU_InitStruct: pointer to a WIU_InitTypeDef structure that +* contains the configuration information for the WIU peripheral. +* Output : None +* Return : None +******************************************************************************/ +void WIU_Init(WIU_InitTypeDef* WIU_InitStruct) +{ + /* select the Wake-up line to be used */ + WIU->MR |= WIU_InitStruct->WIU_Line; + + /* configure the triggering edge */ + if(WIU_InitStruct->WIU_TriggerEdge == WIU_RisingEdge) + { + /* trigger on rising edge */ + WIU->TR |= WIU_InitStruct->WIU_Line; + } + else + { + /* trigger on falling edge */ + WIU->TR &= ~WIU_InitStruct->WIU_Line; + } + + if(WIU_InitStruct->WIU_Mode == WIU_Mode_SWInterrupt) + { + /* enable interrupt mode */ + WIU->CTRL |= WIU_Mode_Interrupt; + + /* set the corresponding WUINT bit*/ + WIU->INTR |= WIU_InitStruct->WIU_Line; + } + else + { + /* configure the WIU mode */ + WIU->CTRL |= WIU_InitStruct->WIU_Mode; + } +} + +/****************************************************************************** +* Function Name : WIU_DeInit +* Description : Deinitializes the WIU registers to their default reset values. +* Input : None +* Output : None +* Return : None +******************************************************************************/ +void WIU_DeInit(void) +{ + /* initialize the WIU registers to their reset value */ + SCU_APBPeriphReset(__WIU, ENABLE); + SCU_APBPeriphReset(__WIU, DISABLE); +} + +/****************************************************************************** +* Function Name : WIU_StructInit +* Description : Fills in a WIU_InitTypeDef structure with the reset value of +* each parameter. +* Input : WIU_InitStruct : pointer to a WIU_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +******************************************************************************/ +void WIU_StructInit(WIU_InitTypeDef* WIU_InitStruct) +{ + /* initialize the WIU_InitStruct fields to their reset values */ + WIU_InitStruct->WIU_Mode = 0x0 ; + WIU_InitStruct->WIU_Line = 0x0 ; + WIU_InitStruct->WIU_TriggerEdge = WIU_FallingEdge ; +} + + +/******************************************************************************* +* Function Name : WIU_GenerateSWInterrupt +* Description : Generates a Software interrupt. +* Input : - WIU_Line: specifies the WIU lines to be enabled or +* disabled. This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : None +*******************************************************************************/ +void WIU_GenerateSWInterrupt(u32 WIU_Line) +{ + WIU->INTR |= WIU_Line; +} + +/******************************************************************************* +* Function Name : WIU_GetFlagStatus +* Description : Checks whether the specified WIU line flag is set or not. +* Input : - WIU_Line: specifies the WIU lines flag to check. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : The new state of WIU_Line (SET or RESET). +*******************************************************************************/ +FlagStatus WIU_GetFlagStatus(u32 WIU_Line) +{ + if((WIU->PR & WIU_Line) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WIU_ClearFlag +* Description : Clears the WIU’s line pending flags. +* Input : - WIU_Line: specifies the WIU lines flags to clear. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : None +*******************************************************************************/ +void WIU_ClearFlag(u32 WIU_Line) +{ + WIU->PR = WIU_Line; +} + +/******************************************************************************* +* Function Name : WIU_GetITStatus +* Description : Checks whether the specified WIU line is asserted or not. +* Input : - WIU_Line: specifies the WIU lines to check. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : The new state of WIU_Line (SET or RESET). +*******************************************************************************/ +ITStatus WIU_GetITStatus(u32 WIU_Line) +{ + if(((WIU->PR & WIU_Line) != RESET)&& ((WIU->MR & WIU_Line) != RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : WIU_ClearITPendingBit +* Description : Clears the WIU’s line pending bits. +* Input : - WIU_Line: specifies the WIU lines to clear. +* This parameter can be: +* - WIU_Linex: External interrupt line x where x(0..31) +* Output : None +* Return : None +*******************************************************************************/ +void WIU_ClearITPendingBit(u32 WIU_Line) +{ + WIU->PR = WIU_Line; +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/Makefile b/uc_str912/prj_test_lcd/Makefile new file mode 100644 index 0000000..9bfbf4e --- /dev/null +++ b/uc_str912/prj_test_lcd/Makefile @@ -0,0 +1,496 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# WinARM template makefile +# by Giacomo Fazio and Antonio Nasca, Catania, Italy +# +# +# +# based on the WinARM template makefile written by Martin Thomas +# Released to the Public Domain +# Please read the make user manual! +# +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make program = Download the hex file to the device +# +# (TODO: make filename.s = Just compile filename.c into the assembler code only) +# +# To rebuild project do "make clean" then "make all". +# Toolchain prefix (i.e arm-elf -> arm-elf-gcc.exe) +#TCHAIN = arm-elf +TCHAIN = arm-none-eabi + +USE_THUMB_MODE = YES +#USE_THUMB_MODE = NO + +# MCU name and submodel +MCU = arm966e-s +SUBMDL = STR91x + +## Create ROM-Image +RUN_MODE=ROM_RUN +## Create RAM-Image +#RUN_MODE=RAM_RUN + +## not supported in this example: +## Exception-Vector placement only supported for "ROM_RUN" +## (placement settings ignored when using "RAM_RUN") +## - Exception vectors in ROM: +#VECTOR_LOCATION=VECTORS_IN_ROM +## - Exception vectors in RAM: +#VECTOR_LOCATION=VECTORS_IN_RAM + + +# Target file name (without extension). +TARGET = lcd + +# List C source files here. (C dependencies are automatically generated.) +# use file-extension c for "c-only"-files +SRC = src/$(TARGET).c str91x_lib/91x_scu.c str91x_lib/91x_gpio.c src/lcd_lib_91x.c + +# List C source files here which must be compiled in ARM-Mode. +# use file-extension c for "c-only"-files +SRCARM = src/vectors.c +# thumb is possible too for vectors.c - keep ARM, TODO: profile + +# List C++ source files here. +# use file-extension cpp for C++-files (use extension .cpp) +CPPSRC = + +# List C++ source files here which must be compiled in ARM-Mode. +# use file-extension cpp for C++-files (use extension .cpp) +#CPPSRCARM = $(TARGET).cpp +CPPSRCARM = + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +# List Assembler source files here which must be assembled in ARM-Mode.. +ASRCARM = src/vector.S src/startup.S + +# Path to Linker-Scripts +LINKERSCRIPTPATH = . + +## Output format. (can be ihex or binary or both) +## (binary i.e. for openocd and SAM-BA, hex i.e. for lpc21isp and uVision) +#FORMAT = ihex +#FORMAT = binary +FORMAT = both + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +#OPT = s +OPT = 0 + +## Using the Atmel AT91_lib produces warning with +## the default warning-levels. +## yes - disable these warnings; no - keep default settings +#AT91LIBNOWARN = yes +AT91LIBNOWARN = no + +# Debugging format. +# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2. +# AVR (extended) COFF requires stabs, plus an avr-objcopy run. +#DEBUG = stabs +DEBUG = dwarf-2 + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +EXTRAINCDIRS = ./include ./str91x_lib/include + +# List any extra directories to look for library files here. +# Each directory must be seperated by a space. +#EXTRA_LIBDIRS = ../arm7_efsl_0_2_4 +EXTRA_LIBDIRS = ./str91x_lib + + +# Compiler flag to set the C Standard level. +# c89 - "ANSI" C +# gnu89 - c89 plus GCC extensions +# c99 - ISO C99 standard (not yet fully implemented) +# gnu99 - c99 plus GCC extensions +CSTANDARD = -std=gnu99 + +# Place -D or -U options for C here +CDEFS = -D$(RUN_MODE) + +# Place -I options here +CINCS = + +# Place -D or -U options for ASM here +ADEFS = -D$(RUN_MODE) + +ifdef VECTOR_LOCATION +CDEFS += -D$(VECTOR_LOCATION) +ADEFS += -D$(VECTOR_LOCATION) +endif + +CDEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__ +ADEFS += -D__WinARM__ -D__WINARMSUBMDL_$(SUBMDL)__ + +# Compiler flags. + +ifeq ($(USE_THUMB_MODE),YES) +THUMB = -mthumb +THUMB_IW = -mthumb-interwork +else +THUMB = +THUMB_IW = +endif + +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +# +# Flags for C and C++ (arm-elf-gcc/arm-elf-g++) +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) $(CINCS) +CFLAGS += -O$(OPT) +CFLAGS += -Wall -Wcast-align -Wimplicit +CFLAGS += -Wpointer-arith -Wswitch +CFLAGS += -ffunction-sections -fdata-sections +CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused +CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +# flags only for C +CONLYFLAGS += -Wnested-externs +CONLYFLAGS += $(CSTANDARD) + +ifneq ($(AT91LIBNOWARN),yes) +#AT91-lib warnings with: +CFLAGS += -Wcast-qual +CONLYFLAGS += -Wmissing-prototypes +CONLYFLAGS += -Wstrict-prototypes +CONLYFLAGS += -Wmissing-declarations +endif + +# flags only for C++ (arm-elf-g++) +# CPPFLAGS = -fno-rtti -fno-exceptions +CPPFLAGS = + +# Assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlns: create listing +# -g$(DEBUG): have the assembler create line number information +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG) + + +#Additional libraries. + +# Extra libraries +# Each library-name must be seperated by a space. +# To add libxyz.a, libabc.a and libefsl.a: +# EXTRA_LIBS = xyz abc efsl +#EXTRA_LIBS = efsl +EXTRA_LIBS = +#STR91x_lib + +#Support for newlibc-lpc (file: libnewlibc-lpc.a) +#NEWLIBLPC = -lnewlib-lpc + +MATH_LIB = -lm + +# CPLUSPLUS_LIB = -lstdc++ + + +# Linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref,--gc-sections,--no-warn-mismatch +LDFLAGS += -lc +LDFLAGS += $(NEWLIBLPC) $(MATH_LIB) +LDFLAGS += -lc -lgcc +LDFLAGS += $(CPLUSPLUS_LIB) +LDFLAGS += $(patsubst %,-L%,$(EXTRA_LIBDIRS)) +LDFLAGS += $(patsubst %,-l%,$(EXTRA_LIBS)) + +# Set Linker-Script Depending On Selected Memory and Controller +ifeq ($(RUN_MODE),RAM_RUN) +LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-RAM.ld +else +LDFLAGS +=-T$(LINKERSCRIPTPATH)/$(SUBMDL)-ROM.ld +endif + + +# Define directories, if needed. +## DIRARM = c:/WinARM/ +## DIRARMBIN = $(DIRAVR)/bin/ +## DIRAVRUTILS = $(DIRAVR)/utils/bin/ + +# Define programs and commands. +SHELL = sh +CC = $(TCHAIN)-gcc +CPP = $(TCHAIN)-g++ +AR = $(TCHAIN)-ar +OBJCOPY = $(TCHAIN)-objcopy +OBJDUMP = $(TCHAIN)-objdump +SIZE = $(TCHAIN)-size +NM = $(TCHAIN)-nm +REMOVE = rm -f +REMOVEDIR = rm -f -r +COPY = cp + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = "-------- begin (mode: $(RUN_MODE)) --------" +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_FLASH = Creating load file for Flash: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_ARM = "Compiling C (ARM-only):" +MSG_COMPILINGCPP = Compiling C++: +MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):" +MSG_ASSEMBLING = Assembling: +MSG_ASSEMBLING_ARM = "Assembling (ARM-only):" +MSG_CLEANING = Cleaning project: +MSG_FORMATERROR = Can not handle output-format +MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now. + +# Define all object files. +COBJ = $(SRC:.c=.o) +AOBJ = $(ASRC:.S=.o) +COBJARM = $(SRCARM:.c=.o) +AOBJARM = $(ASRCARM:.S=.o) +CPPOBJ = $(CPPSRC:.cpp=.o) +CPPOBJARM = $(CPPSRCARM:.cpp=.o) + +# Define all listing files. +LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst) +LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst) + +# Compiler flags to generate dependency files. +### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d +GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS) + + +# Default target. +all: begin gccversion sizebefore build sizeafter finished end + +ifeq ($(FORMAT),ihex) +build: elf hex lss sym +hex: $(TARGET).hex +IMGEXT=hex +else +ifeq ($(FORMAT),binary) +build: elf bin lss sym +bin: $(TARGET).bin +IMGEXT=bin +else +ifeq ($(FORMAT),both) +build: elf hex bin lss sym +hex: $(TARGET).hex +bin: $(TARGET).bin +else +$(error "$(MSG_FORMATERROR) $(FORMAT)") +endif +endif +endif + +elf: $(TARGET).elf +lss: $(TARGET).lss +sym: $(TARGET).sym + +# Eye candy. +begin: + @echo + @echo $(MSG_BEGIN) + +finished: + @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf +sizebefore: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + + +# Display compiler version information. +gccversion : + @$(CC) --version + +# FLASH Programming with OPENOCD + +# specify the directory where openocd executable resides (openocd-ftd2xx.exe or openocd-pp.exe) +# Note: you may have to adjust this if a newer version of YAGARTO has been downloaded +OPENOCD_DIR = 'c:\Programmi\openocd\bin\' + +# specify OpenOCD executable (pp is for the wiggler, ftd2xx is for the USB debugger) +OPENOCD = $(OPENOCD_DIR)openocd-pp.exe +#OPENOCD = $(OPENOCD_DIR)openocd-ftd2xx.exe + +# specify OpenOCD configuration file (pick the one for your device) +#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_signalyzer-flash-program.cfg +#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_jtagkey-flash-program.cfg +#OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_armusbocd-flash-program.cfg +OPENOCD_CFG = C:\openocd-configs\str91x-configs\str91x_pp-flash-program.cfg + +program: + @echo + @echo "Flash Programming with OpenOCD..." + $(OPENOCD) -f $(OPENOCD_CFG) + @echo + @echo + @echo "Flash Programming Finished." + + +# Create final output file (.hex) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O ihex $< $@ + +# Create final output file (.bin) from ELF output file. +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary $< $@ + + +# Create extended listing file from ELF output file. +# testing: option -C +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S -C $< > $@ + + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) +%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) +# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) + +# Compile: create object files from C source files. ARM/Thumb +$(COBJ) : %.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C source files. ARM-only +$(COBJARM) : %.o : %.c + @echo + @echo $(MSG_COMPILING_ARM) $< + $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM/Thumb +$(CPPOBJ) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP) $< + $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM-only +$(CPPOBJARM) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP_ARM) $< + $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. ARM/Thumb +## does not work - TODO - hints welcome +##$(COBJ) : %.s : %.c +## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM/Thumb +$(AOBJ) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM-only +$(AOBJARM) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING_ARM) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list finished end + + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).a90 + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lnk + $(REMOVE) $(TARGET).lss + $(REMOVE) $(COBJ) + $(REMOVE) $(CPPOBJ) + $(REMOVE) $(AOBJ) + $(REMOVE) $(COBJARM) + $(REMOVE) $(CPPOBJARM) + $(REMOVE) $(AOBJARM) + $(REMOVE) $(LST) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRCARM:.c=.s) + $(REMOVE) $(SRCARM:.c=.d) + $(REMOVE) $(CPPSRC:.cpp=.s) + $(REMOVE) $(CPPSRC:.cpp=.d) + $(REMOVE) $(CPPSRCARM:.cpp=.s) + $(REMOVE) $(CPPSRCARM:.cpp=.d) + $(REMOVEDIR) .dep | exit 0 + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin lss sym clean clean_list program + diff --git a/uc_str912/prj_test_lcd/STR91x-ROM.ld b/uc_str912/prj_test_lcd/STR91x-ROM.ld new file mode 100644 index 0000000..ed2979b --- /dev/null +++ b/uc_str912/prj_test_lcd/STR91x-ROM.ld @@ -0,0 +1,221 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 256; + _STACKSIZE_SVC = 0; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t .glue_7) + KEEP(*(.fini)) + *(.gcc_except_table) + } >CODE =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >CODE + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >CODE + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >CODE + . = ALIGN(4); + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + __data_start = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + . = ALIGN(4); + *(.fastrun .fastrun.*) + } >DATA + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/prj_test_lcd/include/91x_ahbapb.h b/uc_str912/prj_test_lcd/include/91x_ahbapb.h new file mode 100644 index 0000000..1828d48 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_ahbapb.h @@ -0,0 +1,60 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* AHBAPB software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef _91x_AHBAPB_H +#define _91x_AHBAPB_H + +#include "91x_map.h" + +#define AHBAPB_Split_Enable 0x01000000 +#define AHBAPB_Split_Disable 0xFEFFFFFF +#define AHBAPB_Error_Enable 0x0000100 +#define AHBAPB_Error_Disable 0xFFFFEFF + +/*FLAG*/ +#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/ +#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */ +#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */ +#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/ + +/* Includes ------------------------------------------------------------------*/ + + +/* AHBAPB Init structure definition */ +typedef struct +{ + u32 AHBAPB_SetTimeOut; + u32 AHBAPB_Error; + u32 AHBAPB_Split; + u8 AHBAPB_SplitCounter; +}AHBAPB_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx); +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct); +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct); +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG); +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx); + + +#endif /* _91x_AHBAPB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/include/91x_conf.h b/uc_str912/prj_test_lcd/include/91x_conf.h new file mode 100644 index 0000000..578335d --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_conf.h @@ -0,0 +1,115 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_conf.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Library configuration. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +#ifndef __91x_CONF_H +#define __91x_CONF_H + +/* To work in buffered mode just decomment the following line */ + +//#define Buffered + +/* Comment the line below to put the library in release mode */ +//#define DEBUG + +/************************* AHBAPB *************************/ +//#define _AHBAPB +//#define _AHBAPB0 +//#define _AHBAPB1 +/************************* VIC *************************/ +//#define _VIC +//#define _VIC0 +//#define _VIC1 +/************************* DMA *************************/ +//#define _DMA +//#define _DMA_Channel0 +//#define _DMA_Channel1 +//#define _DMA_Channel2 +//#define _DMA_Channel3 +//#define _DMA_Channel4 +//#define _DMA_Channel5 +//#define _DMA_Channel6 +//#define _DMA_Channel7 + +/************************* EMI *************************/ +//#define _EMI +//#define _EMI_Bank0 +//#define _EMI_Bank1 +//#define _EMI_Bank2 +//#define _EMI_Bank3 +/************************* FMI *************************/ +//#define _FMI +/************************* WIU *************************/ +//#define _WIU +/************************* TIM *************************/ +//#define _TIM +//#define _TIM0 +//#define _TIM1 +//#define _TIM2 +//#define _TIM3 +/************************* GPIO ************************/ +#define _GPIO +#define _GPIO0 +#define _GPIO1 +#define _GPIO2 +#define _GPIO3 +#define _GPIO4 +#define _GPIO5 +#define _GPIO6 +#define _GPIO7 +#define _GPIO8 +#define _GPIO9 +/************************* RTC *************************/ +//#define _RTC +/************************* SCU *************************/ +#define _SCU +/************************* MC **************************/ +//#define _MC +/************************* UART ************************/ +//#define _UART +//#define _UART0 +//#define _UART1 +//#define _UART2 +/************************* SSP *************************/ +//#define _SSP +//#define _SSP0 +//#define _SSP1 +/************************* CAN *************************/ +//#define _CAN +/************************* ADC *************************/ +//#define _ADC +/************************* WDG *************************/ +//#define _WDG +/************************* I2C *************************/ +//#define _I2C +//#define _I2C0 +//#define _I2C1 +/************************ ENET *************************/ +//#define _ENET + +/*---------------------------- _Main_Crystal frequency value (KHz)------------*/ + +#ifndef _Main_Crystal +#define _Main_Crystal 25000 +#endif +/*------------------------------------------------------------------------------*/ + + +#endif /* __91x_CONF_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/include/91x_fmi.h b/uc_str912/prj_test_lcd/include/91x_fmi.h new file mode 100644 index 0000000..06e8115 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_fmi.h @@ -0,0 +1,184 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* FMI software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef __91x_FMI_H +#define __91x_FMI_H + +/* ========================================================================== */ +/* When bank 1 is remapped at address 0x0, decomment the following line */ +/* ========================================================================== */ + +//#define Remap_Bank_1 + + +/* Includes ------------------------------------------------------------------*/ + +#include "91x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* FMI banks */ + +#ifdef Remap_Bank_1 + +#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */ + +#else /* Remap Bank 0 */ + +#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */ +#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */ + +#endif + +/* FMI sectors */ + +#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */ +#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */ +#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */ +#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */ +#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */ +#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */ +#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */ +#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */ + +#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */ +#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */ +#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */ +#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */ + +/* FMI Flags */ + +#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */ +#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */ +#define FMI_FLAG_PS 0x10 /* Program Status Flag */ +#define FMI_FLAG_ES 0x20 /* Erase Status Flag */ +#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */ +#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */ + +/* FMI read wait states */ + +#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */ +#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */ +#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */ + +/* FMI write wait states */ + +#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */ +#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */ + +/* FMI power down configuration */ + +#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */ +#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */ + +/* FMI low voltage detector */ + +#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */ +#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */ + +/* FMI frequency range */ + +#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */ +#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */ + /* Above 66 MHz*/ +/* FMI OTP word addresses */ + +#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */ +#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */ +#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */ +#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */ +#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */ +#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */ +#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */ +#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */ + +/* FMI OTP halfword addresses */ + +#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */ +#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */ +#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */ +#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */ +#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */ +#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */ +#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */ +#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */ +#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */ +#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */ +#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */ +#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */ +#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */ +#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */ +#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */ +#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */ + +/* FMI sectors Masks */ + +#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */ +#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */ +#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */ +#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */ +#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */ +#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */ +#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */ +#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */ + +#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */ +#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */ +#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */ +#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */ + +/* Timeout error */ + +#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */ +#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */ + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress); +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange); +void FMI_EraseSector(vu32 FMI_Sector); +void FMI_EraseBank(vu32 FMI_Bank); +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data); +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData); +u32 FMI_ReadWord(u32 FMI_Address); +u32 FMI_ReadOTPData(u8 FMI_OTPAddress); +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank); +u16 FMI_GetReadWaitStateValue(void); +u16 FMI_GetWriteWaitStateValue(void); +void FMI_SuspendEnable(vu32 FMI_Bank); +void FMI_ResumeEnable(vu32 FMI_Bank); +void FMI_ClearFlag(vu32 FMI_Bank); +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState); +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection); +u8 FMI_WaitForLastOperation(vu32 FMI_Bank); + +#endif /* __91x_FMI_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_test_lcd/include/91x_gpio.h b/uc_str912/prj_test_lcd/include/91x_gpio.h new file mode 100644 index 0000000..4beab75 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_gpio.h @@ -0,0 +1,93 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file contains all the functions prototypes for the +* GPIO software library. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ + +#ifndef _91x_GPIO_H +#define _91x_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* GPIO Init structure definition */ +typedef struct +{ + u8 GPIO_Pin; + u8 GPIO_Direction; + u8 GPIO_Type; + u8 GPIO_IPConnected; + u16 GPIO_Alternate; +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + + +/* Exported constants --------------------------------------------------------*/ +#define GPIO_Pin_None 0x00 +#define GPIO_Pin_0 0x01 +#define GPIO_Pin_1 0x02 +#define GPIO_Pin_2 0x04 +#define GPIO_Pin_3 0x08 +#define GPIO_Pin_4 0x10 +#define GPIO_Pin_5 0x20 +#define GPIO_Pin_6 0x40 +#define GPIO_Pin_7 0x80 +#define GPIO_Pin_All 0xFF + +#define GPIO_PinInput 0x00 +#define GPIO_PinOutput 0x01 + +#define GPIO_Type_PushPull 0x00 +#define GPIO_Type_OpenCollector 0x01 + +#define GPIO_IPConnected_Disable 0x00 +#define GPIO_IPConnected_Enable 0x01 + +#define GPIO_InputAlt1 0x00 +#define GPIO_OutputAlt1 0x01 +#define GPIO_OutputAlt2 0x02 +#define GPIO_OutputAlt3 0x03 + +#define GPIO_ANAChannel0 0x01 +#define GPIO_ANAChannel1 0x02 +#define GPIO_ANAChannel2 0x04 +#define GPIO_ANAChannel3 0x08 +#define GPIO_ANAChannel4 0x10 +#define GPIO_ANAChannel5 0x20 +#define GPIO_ANAChannel6 0x40 +#define GPIO_ANAChannel7 0x80 +#define GPIO_ANAChannelALL 0xFF + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin); +u8 GPIO_Read(GPIO_TypeDef* GPIOx); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal); +void GPIO_EMIConfig(FunctionalState NewState); +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState); + +#endif /* _91x_GPIO_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/include/91x_lib.h b/uc_str912/prj_test_lcd/include/91x_lib.h new file mode 100644 index 0000000..823b250 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_lib.h @@ -0,0 +1,114 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Used to include the peripherals header file in the +* user application. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __91x_LIB_H +#define __91x_LIB_H + +#include "91x_map.h" +#include "91x_conf.h" + +#ifdef _AHBAPB + #include "91x_ahbapb.h" +#endif /* _AHBAPB */ + +#ifdef _EMI + #include "91x_emi.h" +#endif /* _EMI */ + +#ifdef _DMA + #include "91x_dma.h" +#endif /* _DMA */ + +#ifdef _FMI + #include "91x_fmi.h" +#endif /* _FMI */ + +#ifdef _VIC + #include "91x_vic.h" +#endif /* _VIC */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif /* _WIU */ + +#ifdef _TIM + #include "91x_tim.h" +#endif /* _TIM */ + +#ifdef _GPIO + #include "91x_gpio.h" +#endif /* _GPIO */ + +#ifdef _RTC + #include "91x_rtc.h" +#endif /* _RTC */ + +#ifdef _SCU + #include "91x_scu.h" +#endif /* _SCU */ + +#ifdef _UART + #include "91x_uart.h" +#endif /* _UART */ + +#ifdef _SSP + #include "91x_ssp.h" +#endif /* _SSP */ + +#ifdef _CAN + #include "91x_can.h" +#endif /* _CAN */ + +#ifdef _ADC + #include "91x_adc.h" +#endif /* _ADC */ + +#ifdef _WDG + #include "91x_wdg.h" +#endif /* _WDG */ + +#ifdef _I2C + #include "91x_i2c.h" +#endif /* _I2C */ + +#ifdef _WIU + #include "91x_wiu.h" +#endif + +#ifdef _MC + #include "91x_mc.h" +#endif + +#ifdef _ENET + #include "91x_enet.h" +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + void debug( void ); + + +#endif /* __91x_LIB_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/include/91x_map.h b/uc_str912/prj_test_lcd/include/91x_map.h new file mode 100644 index 0000000..2e94a91 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_map.h @@ -0,0 +1,878 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_map.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : Peripherals registers definition and memory mapping. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef __91x_MAP_H +#define __91x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_conf.h" +#include "91x_type.h" + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ + +/*------------------------------------ FMI -----------------------------------*/ + +typedef struct +{ + vu32 BBSR; /* Boot Bank Size Register */ + vu32 NBBSR; /* Non-Boot Bank Size Register */ + vu32 EMPTY1; + vu32 BBADR; /* Boot Bank Base Address Register */ + vu32 NBBADR; /* Non-Boot Bank Base Address Register */ + vu32 EMPTY2; + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */ +} FMI_TypeDef; + +/*---------------------- Analog to Digital Convertor ------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 CCR; /* Channel Configuration Register */ + vu16 EMPTY2; + vu16 HTR; /* Higher Threshold Register */ + vu16 EMPTY3; + vu16 LTR; /* Lower Threshold Register */ + vu16 EMPTY4; + vu16 CRR; /* Compare Result Register */ + vu16 EMPTY5; + vu16 DR0; /* Data Register for Channel 0 */ + vu16 EMPTY6; + vu16 DR1; /* Data Register for Channel 1 */ + vu16 EMPTY7; + vu16 DR2; /* Data Register for Channel 2 */ + vu16 EMPTY8; + vu16 DR3; /* Data Register for Channel 3 */ + vu16 EMPTY9; + vu16 DR4; /* Data Register for Channel 4 */ + vu16 EMPTY10; + vu16 DR5; /* Data Register for Channel 5 */ + vu16 EMPTY11; + vu16 DR6; /* Data Register for Channel 6 */ + vu16 EMPTY12; + vu16 DR7; /* Data Register for Channel 7 */ + vu16 EMPTY13; + vu16 PRS; /* Prescaler Value Register */ + vu16 EMPTY14; +} ADC_TypeDef; + +/*--------------------- AHB APB BRIDGE registers strcture --------------------*/ + +typedef struct +{ + vu32 BSR; /* Bridge Status Register */ + vu32 BCR; /* Bridge Configuration Register */ + vu32 PAER; /* Peripheral Address Error register */ +} AHBAPB_TypeDef; + +/*--------------- Controller Area Network Interface Register -----------------*/ + +typedef struct +{ + vu16 CRR; /* IFn Command request Register */ + vu16 EMPTY1; + vu16 CMR; /* IFn Command Mask Register */ + vu16 EMPTY2; + vu16 M1R; /* IFn Message Mask 1 Register */ + vu16 EMPTY3; + vu16 M2R; /* IFn Message Mask 2 Register */ + vu16 EMPTY4; + vu16 A1R; /* IFn Message Arbitration 1 Register */ + vu16 EMPTY5; + vu16 A2R; /* IFn Message Arbitration 2 Register */ + vu16 EMPTY6; + vu16 MCR; /* IFn Message Control Register */ + vu16 EMPTY7; + vu16 DA1R; /* IFn DATA A 1 Register */ + vu16 EMPTY8; + vu16 DA2R; /* IFn DATA A 2 Register */ + vu16 EMPTY9; + vu16 DB1R; /* IFn DATA B 1 Register */ + vu16 EMPTY10; + vu16 DB2R; /* IFn DATA B 2 Register */ + vu16 EMPTY11[27]; +} CAN_MsgObj_TypeDef; + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 SR; /* Status Register */ + vu16 EMPTY2; + vu16 ERR; /* Error counter Register */ + vu16 EMPTY3; + vu16 BTR; /* Bit Timing Register */ + vu16 EMPTY4; + vu16 IDR; /* Interrupt Identifier Register */ + vu16 EMPTY5; + vu16 TESTR; /* Test Register */ + vu16 EMPTY6; + vu16 BRPR; /* BRP Extension Register */ + vu16 EMPTY7[3]; + CAN_MsgObj_TypeDef sMsgObj[2]; + vu16 EMPTY8[16]; + vu16 TXR1R; /* Transmission request 1 Register */ + vu16 EMPTY9; + vu16 TXR2R; /* Transmission Request 2 Register */ + vu16 EMPTY10[13]; + vu16 ND1R; /* New Data 1 Register */ + vu16 EMPTY11; + vu16 ND2R; /* New Data 2 Register */ + vu16 EMPTY12[13]; + vu16 IP1R; /* Interrupt Pending 1 Register */ + vu16 EMPTY13; + vu16 IP2R; /* Interrupt Pending 2 Register */ + vu16 EMPTY14[13]; + vu16 MV1R; /* Message Valid 1 Register */ + vu16 EMPTY15; + vu16 MV2R; /* Message VAlid 2 Register */ + vu16 EMPTY16; +} CAN_TypeDef; + +/*----------------------- System Control Unit---------------------------------*/ + +typedef struct +{ + vu32 CLKCNTR; /* Clock Control Register */ + vu32 PLLCONF; /* PLL Configuration Register */ + vu32 SYSSTATUS; /* System Status Register */ + vu32 PWRMNG; /* Power Management Register */ + vu32 ITCMSK; /* Interrupt Mask Register */ + vu32 PCGRO; /* Peripheral Clock Gating Register 0 */ + vu32 PCGR1; /* Peripheral Clock Gating Register 1 */ + vu32 PRR0; /* Peripheral Reset Register 0 */ + vu32 PRR1; /* Peripheral Reset Register 1 */ + vu32 MGR0; /* Idle Mode Mask Gating Register 0 */ + vu32 MGR1; /* Idle Mode Mask Gating Register 1 */ + vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */ + vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */ + vu32 SCR0; /* System Configuration Register 0 */ + vu32 SCR1; /* System Configuration Register 1 */ + vu32 SCR2; /* System Configuration Register 2 */ + u32 EMPTY1; + vu32 GPIOOUT[8]; /* GPIO Output Registers */ + vu32 GPIOIN[8]; /* GPIO Input Registers */ + vu32 GPIOTYPE[10];/* GPIO Type Registers */ + vu32 GPIOEMI; /* GPIO EMI Selector Register */ + vu32 WKUPSEL; /* Wake-Up Selection Register */ + u32 EMPTY2[2]; + vu32 GPIOANA; /* GPIO Analag mode Register */ +} SCU_TypeDef; + +/*------------------------- DMA Channelx Registers ---------------------------*/ + +typedef struct +{ + vu32 SRC; /* Channelx Source Address Register */ + vu32 DES; /* Channelx Destination Address Register */ + vu32 LLI; /* Channelx Lincked List Item Register */ + vu32 CC; /* Channelx Contol Register */ + vu32 CCNF; /* Channelx Configuration Register */ +} DMA_Channel_TypeDef; + +/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */ + +/*----------------------------- DMA Controller -------------------------------*/ + +typedef struct +{ + vu32 ISR; /* Interrupt Status Register */ + vu32 TCISR; /* Terminal Count Interrupt Status Register */ + vu32 TCICR; /* Terminal CountInterrupt Clear Register */ + vu32 EISR; /* Error Interrupt Status Register */ + vu32 EICR; /* Error Interrupt Clear Register */ + vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */ + vu32 ERISR; /* Raw Error Interrupt Status Register */ + vu32 ENCSR; /* Enabled Channel Status Register */ + vu32 SBRR; /* Software Burst Request Register */ + vu32 SSRR; /* Software Single Request Register */ + vu32 SLBRR; /* Software Last Burst Request Register */ + vu32 SLSRR; /* Software Last Single Request Register */ + vu32 CNFR; /* Configuration Register */ + vu32 SYNR; /* Syncronization Register */ + } DMA_TypeDef; + +/*--------------------------------- TIM Timer --------------------------------*/ + +typedef struct +{ + vu16 IC1R; /* Input Capture 1 Register */ + vu16 EMPTY1; + vu16 IC2R; /* Input Capture 2 Register */ + vu16 EMPTY2; + vu16 OC1R; /* Output Compare 1 Register */ + vu16 EMPTY3; + vu16 OC2R; /* Output Compare 2 Register */ + vu16 EMPTY4; + vu16 CNTR; /* Counter Register */ + vu16 EMPTY5; + vu16 CR1; /* Control Register 1 */ + vu16 EMPTY6; + vu16 CR2; /* Control Register 2 */ + vu16 EMPTY7; + vu16 SR; /* Status Register */ + vu16 EMPTY8; +} TIM_TypeDef; + +/*---------------------------- EMI Bankx Registers ---------------------------*/ + +typedef struct +{ + vu32 ICR; /* Bankx Idle Cycle Control Register */ + vu32 RCR; /* Bankx Read Wait State Control Register */ + vu32 WCR; /* Bankx Write Wait State Control Register */ + vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */ + vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */ + vu32 BCR; /* Bankx Control Register */ + } EMI_Bank_TypeDef; + +/*---------------------------- Ethernet Controller ---------------------------*/ + +/* MAC Registers */ +typedef struct +{ + vu32 MCR; /* ENET Control Register */ + vu32 MAH; /* ENET Address High Register */ + vu32 MAL; /* ENET Address Low Register */ + vu32 MCHA; /* Multicast Address High Register */ + vu32 MCLA; /* Multicast Address Low Register */ + vu32 MIIA; /* MII Address Register */ + vu32 MIID; /* MII Data Register */ + vu32 MCF; /* ENET Control Frame Register */ + vu32 VL1; /* VLAN1 Register */ + vu32 VL2; /* VLAN2 register */ + vu32 MTS; /* ENET Transmission Status Register */ + vu32 MRS; /* ENET Reception Status Register */ +} ENET_MAC_TypeDef; + +/* DMA Registers */ +typedef struct +{ + vu32 SCR; /* DMA Status and Control Register */ + vu32 IER; /* DMA Interrupt Sources Enable Register */ + vu32 ISR; /* DMA Interrupt Status Register */ + vu32 CCR; /* Clock Control Relation : HCLK, PCLK and + ENET_CLK phase relations */ + vu32 RXSTR; /* Rx DMA start Register */ + vu32 RXCR; /* Rx DMA Control Register */ + vu32 RXSAR; /* Rx DMA Base Address Register */ + vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */ + vu32 RXCAR; /* Rx DMA Current Address Register */ + vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */ + vu32 RXTOR; /* Rx DMA FIFO Time Out Register */ + vu32 RXSR; /* Rx DMA FIFO Status Register */ + vu32 TXSTR; /* Tx DMA start Register */ + vu32 TXCR; /* Tx DMA Control Register */ + vu32 TXSAR; /* Tx DMA Base Address Register */ + vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */ + vu32 TXCAR; /* Tx DMA Current Address Register */ + vu32 TXTCR; /* Tx DMA Current Transfer Count Register */ + vu32 TXTOR; /* Tx DMA FIFO Time Out Register */ + vu32 TXSR; /* Tx DMA FIFO Status Register */ +} ENET_DMA_TypeDef; + +/*------------------------------------- GPIO ---------------------------------*/ + +typedef struct +{ + vu8 DR[1021]; /* Data Register */ + vu32 DDR; /* Data Direction Register */ +} GPIO_TypeDef; + +/*-------------------------------- I2C interface -----------------------------*/ + +typedef struct +{ + vu8 CR; /* Control Register */ + vu8 EMPTY1[3]; + vu8 SR1; /* Status Register 1 */ + vu8 EMPTY2[3]; + vu8 SR2; /* Status Register 2 */ + vu8 EMPTY3[3]; + vu8 CCR; /* Clock Control Register */ + vu8 EMPTY4[3]; + vu8 OAR1; /* Own Address Register 1 */ + vu8 EMPTY5[3]; + vu8 OAR2; /* Own Address Register 2 */ + vu8 EMPTY6[3]; + vu8 DR; /* Data Register */ + vu8 EMPTY7[3]; + vu8 ECCR; /* Extended Clock Control Register */ + vu8 EMPTY8[3]; +} I2C_TypeDef; + +/*------------------------------------- VIC ----------------------------------*/ + +typedef struct +{ + vu32 ISR; /* IRQ Status Register */ + vu32 FSR; /* FIQ Status Register */ + vu32 RINTSR; /* Raw Interrupt Status Register */ + vu32 INTSR; /* Interrupt Select Register */ + vu32 INTER; /* Interrupt Enable Register */ + vu32 INTECR; /* Interrupt Enable Clear Register */ + vu32 SWINTR; /* Software Interrupt Register */ + vu32 SWINTCR; /* Software Interrupt clear Register */ + vu32 PER; /* Protection Enable Register */ + vu32 EMPTY1[3]; + vu32 VAR; /* Vector Address Register */ + vu32 DVAR; /* Default Vector Address Register */ + vu32 EMPTY2[50]; + vu32 VAiR[16]; /* Vector Address 0-15 Register */ + vu32 EMPTY3[48]; + vu32 VCiR[16]; /* Vector Control 0-15 Register */ +} VIC_TypeDef; + +/*-------------------------------- Motor Control -----------------------------*/ + +typedef struct +{ + vu16 TCPT; /* Tacho Capture Register */ + vu16 EMPTY1; + vu16 TCMP; /* Tacho Compare Register */ + vu16 EMPTY2; + vu16 IPR; /* Input Pending Register */ + vu16 EMPTY3; + vu16 TPRS; /* Tacho Prescaler Register */ + vu16 EMPTY4; + vu16 CPRS; /* PWM Counter Prescaler Register */ + vu16 EMPTY5; + vu16 REP; /* Repetition Counter Register */ + vu16 EMPTY6; + vu16 CMPW; /* Compare Phase W Preload Register */ + vu16 EMPTY7; + vu16 CMPV; /* Compare Phase V Preload Register */ + vu16 EMPTY8; + vu16 CMPU; /* Compare Phase U Preload Register */ + vu16 EMPTY9; + vu16 CMP0; /* Compare 0 Preload Register */ + vu16 EMPTY10; + vu16 PCR0; /* Peripheral Control Register 0 */ + vu16 EMPTY11; + vu16 PCR1; /* Peripheral Control Register 1 */ + vu16 EMPTY12; + vu16 PCR2; /* Peripheral Control Register 2 */ + vu16 EMPTY13; + vu16 PSR; /* Polarity Selection Register */ + vu16 EMPTY14; + vu16 OPR; /* Output Peripheral Register */ + vu16 EMPTY15; + vu16 IMR; /* Interrupt Mask Register */ + vu16 EMPTY16; + vu16 DTG; /* Dead Time Generator Register */ + vu16 EMPTY17; + vu16 ESC; /* Emergency Stop Clear Register */ + vu16 EMPTY18; +}MC_TypeDef; + +/*------------------------------------- RTC ----------------------------------*/ + +typedef struct +{ + vu32 TR; /* Time Register */ + vu32 DTR; /* Date Register */ + vu32 ATR; /* Alarm time Register */ + vu32 CR; /* Control Register */ + vu32 SR; /* Status Register */ + vu32 MILR; /* Millisec Register */ +}RTC_TypeDef; + +/*------------------------------------- SSP ----------------------------------*/ + +typedef struct +{ + vu16 CR0; /* Control Register 1 */ + vu16 EMPTY1; + vu16 CR1; /* Control Register 2 */ + vu16 EMPTY2; + vu16 DR; /* Data Register */ + vu16 EMPTY3; + vu16 SR; /* Status Register */ + vu16 EMPTY4; + vu16 PR; /* Clock Prescale Register */ + vu16 EMPTY5; + vu16 IMSCR; /* Interrupt Mask Set or Clear Register */ + vu16 EMPTY6; + vu16 RISR; /* Raw Interrupt Status Register */ + vu16 EMPTY7; + vu16 MISR; /* Masked Interrupt Status Register */ + vu16 EMPTY8; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY9; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY10; +}SSP_TypeDef; + +/*------------------------------------ UART ----------------------------------*/ + +typedef struct +{ + vu16 DR; /* Data Register */ + vu16 EMPTY1; + vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */ + vu16 EMPTY2[9]; + vu16 FR; /* Flag Register */ + vu16 EMPTY3[3]; + vu16 ILPR; /* IrDA Low-Power counter Register */ + vu16 EMPTY4; + vu16 IBRD; /* Integer Baud Rate Divisor Register */ + vu16 EMPTY5; + vu16 FBRD; /* Fractional Baud Rate Divisor Register */ + vu16 EMPTY6; + vu16 LCR; /* Line Control Register, High byte */ + vu16 EMPTY7; + vu16 CR; /* Control Register */ + vu16 EMPTY8; + vu16 IFLS; /* Interrupt FIFO Level Select Register */ + vu16 EMPTY9; + vu16 IMSC; /* Interrupt Mask Set/Clear Register */ + vu16 EMPTY10; + vu16 RIS; /* Raw Interrupt Status Register */ + vu16 EMPTY11; + vu16 MIS; /* Masked Interrupt Status Register */ + vu16 EMPTY12; + vu16 ICR; /* Interrupt Clear Register */ + vu16 EMPTY13; + vu16 DMACR; /* DMA Control Register */ + vu16 EMPTY14; +}UART_TypeDef; + +/*------------------------------- Wake-up System -----------------------------*/ + +typedef struct +{ + vu32 CTRL; /* Control Register */ + vu32 MR; /* Mask Register */ + vu32 TR; /* Trigger Register */ + vu32 PR; /* Pending Register */ + vu32 INTR; /* Software Interrupt Register */ +} WIU_TypeDef; + +/*------------------------------- WatchDog Timer -----------------------------*/ + +typedef struct +{ + vu16 CR; /* Control Register */ + vu16 EMPTY1; + vu16 PR; /* Presclar Register */ + vu16 EMPTY2; + vu16 VR; /* Pre-load Value Register */ + vu16 EMPTY3; + vu16 CNT; /* Counter Register */ + vu16 EMPTY4; + vu16 SR; /* Status Register */ + vu16 EMPTY5; + vu16 MR; /* Mask Register */ + vu16 EMPTY6; + vu16 KR; /* Key Register */ + vu16 EMPTY7; +} WDG_TypeDef; + +/******************************************************************************* +* Memory Mapping of STR91x * +*******************************************************************************/ + +#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */ +#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */ + +#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */ +#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */ + +#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */ +#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */ + +#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */ +#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */ + +#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */ +#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */ + +#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */ +#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */ + +#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */ +#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */ + +#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */ +#define AHB_FMI_B (0x44000000) /* FMI buffered Space */ + +/******************************************************************************* +* Addresses related to the VICs' peripherals * +*******************************************************************************/ + +#define VIC0_BASE (AHB_VIC0_U) +#define VIC1_BASE (AHB_VIC1_U) + +/******************************************************************************* +* Addresses related to the EMI banks * +*******************************************************************************/ + +#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */ +#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */ +#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */ +#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */ + +/******************************************************************************* +* Addresses related to the DMA peripheral * +*******************************************************************************/ + +#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */ +#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */ +#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */ +#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */ +#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */ +#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */ +#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */ +#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */ + +/******************************************************************************* +* Addresses related to the APB0 sub-system * +*******************************************************************************/ + +#define APB_WIU_OFST (0x00001000) /* Offset of WIU */ +#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */ +#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */ +#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */ +#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */ +#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */ +#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */ +#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */ +#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */ +#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */ +#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */ +#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */ +#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */ +#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */ +#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */ + +/******************************************************************************* +* Addresses related to the APB1 sub-system * +*******************************************************************************/ + +#define APB_RTC_OFST (0x00001000) /* Offset of RTC */ +#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */ +#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */ +#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */ +#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */ +#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */ +#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */ +#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */ +#define APB_CAN_OFST (0x00009000) /* Offset of CAN */ +#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */ +#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */ +#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */ +#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */ + +/*----------------------------------------------------------------------------*/ +/*----------------------------- Unbuffered Mode ------------------------------*/ +/*----------------------------------------------------------------------------*/ + +#ifndef Buffered + +/******************************************************************************* +* AHBAPB peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_U) +#define AHBAPB1_BASE (AHB_APB_BRDG1_U) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_U) +#define ENET_DMA_BASE (AHB_ENET_DMA_U) + +/******************************************************************************* +* DMA peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_U) + +/******************************************************************************* +* EMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_U) + +/******************************************************************************* +* FMI peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_U) + + +#else /* Buffered */ + +/*----------------------------------------------------------------------------*/ +/*------------------------------ Buffered Mode -------------------------------*/ +/*----------------------------------------------------------------------------*/ + +/******************************************************************************* +* AHBAPB peripheral Buffered Base Address * +*******************************************************************************/ + +#define AHBAPB0_BASE (AHB_APB_BRDG0_B) +#define AHBAPB1_BASE (AHB_APB_BRDG1_B) + +/******************************************************************************* +* ENET peripheral Unbuffered Base Address * +*******************************************************************************/ + +#define ENET_MAC_BASE (AHB_ENET_MAC_B) +#define ENET_DMA_BASE (AHB_ENET_DMA_B) + +/******************************************************************************* +* DMA peripheral Buffered Base Address * +*******************************************************************************/ + +#define DMA_BASE (AHB_DMA_B) + +/******************************************************************************* +* EMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define EMI_BASE (AHB_EMI_B) + +/******************************************************************************* +* FMI peripheral Buffered Base Address * +*******************************************************************************/ + +#define FMI_BASE (AHB_FMI_B) + +#endif /* Buffered */ + +/******************************************************************************* +* DMA channels Base Address * +*******************************************************************************/ +#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST) +#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST) +#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST) +#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST) +#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST) +#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST) +#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST) +#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST) + +/******************************************************************************* +* EMI Banks peripheral Base Address * +*******************************************************************************/ + +#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST) +#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST) +#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST) +#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST) + +/******************************************************************************* +* APB0 Peripherals' Base addresses * +*******************************************************************************/ + +#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST) +#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST) +#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST) +#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST) +#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST) +#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST) +#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST) +#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST) +#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST) +#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST) +#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST) +#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST) +#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST) +#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST) +#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST) + +/******************************************************************************* +* APB1 Peripherals' Base addresses * +*******************************************************************************/ + +#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST) +#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST) +#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST) +#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST) +#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST) +#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST) +#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST) +#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST) +#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST) +#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST) +#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST) +#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST) +#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST) + +/******************************************************************************* +* IPs' declaration * +*******************************************************************************/ + +/*------------------------------ Non Debug Mode ------------------------------*/ +#undef DEBUG +#ifndef DEBUG + +/*********************************** AHBAPB ***********************************/ + +#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE) +#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE) + +/************************************* EMI ************************************/ + +#define EMI ((EMI_TypeDef *)EMI_BASE) + +/************************************* DMA ************************************/ + +#define DMA ((DMA_TypeDef *)DMA_BASE) +#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) +#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) +#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) +#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) +#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) +#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE) +#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE) +#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE) + +/************************************* EMI ************************************/ + +#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE) +#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE) +#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE) +#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE) + +/************************************* ENET_MAC ************************************/ + +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) + +/************************************* ENET_DMA ************************************/ + +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +/************************************* FMI ************************************/ + +#define FMI ((FMI_TypeDef *)FMI_BASE) + +/************************************* VIC ************************************/ + +#define VIC0 ((VIC_TypeDef *)VIC0_BASE) +#define VIC1 ((VIC_TypeDef *)VIC1_BASE) + +/******************************************************************************* +* APB0 Peripherals' * +*******************************************************************************/ +#define WIU ((WIU_TypeDef *)WIU_BASE) +#define TIM0 ((TIM_TypeDef *)TIM0_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) +#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) +#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) +#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE) +#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE) +#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE) +#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE) +#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE) +#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE) +#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE) +/******************************************************************************* +* APB1 Peripherals' * +*******************************************************************************/ +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define SCU ((SCU_TypeDef *)SCU_BASE) +#define MC ((MC_TypeDef *)MC_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define SSP0 ((SSP_TypeDef *)SSP0_BASE) +#define SSP1 ((SSP_TypeDef *)SSP1_BASE) +#define CAN ((CAN_TypeDef *)CAN_BASE) +#define ADC ((ADC_TypeDef *)ADC_BASE) +#define WDG ((WDG_TypeDef *)WDG_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE) +#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE) + +#else /* DEBUG */ + +/*-------------------------------- Debug Mode --------------------------------*/ + +EXT AHBAPB_TypeDef *AHBAPB0; +EXT AHBAPB_TypeDef *AHBAPB1; +EXT DMA_TypeDef *DMA; +EXT DMA_Channel_TypeDef *DMA_Channel0; +EXT DMA_Channel_TypeDef *DMA_Channel1; +EXT DMA_Channel_TypeDef *DMA_Channel2; +EXT DMA_Channel_TypeDef *DMA_Channel3; +EXT DMA_Channel_TypeDef *DMA_Channel4; +EXT DMA_Channel_TypeDef *DMA_Channel5; +EXT DMA_Channel_TypeDef *DMA_Channel6; +EXT DMA_Channel_TypeDef *DMA_Channel7; +EXT EMI_Bank_TypeDef *EMI_Bank0; +EXT EMI_Bank_TypeDef *EMI_Bank1; +EXT EMI_Bank_TypeDef *EMI_Bank2; +EXT EMI_Bank_TypeDef *EMI_Bank3; +EXT FMI_TypeDef *FMI; +EXT VIC_TypeDef *VIC0; +EXT VIC_TypeDef *VIC1; +EXT WIU_TypeDef *WIU; +EXT TIM_TypeDef *TIM0; +EXT TIM_TypeDef *TIM1; +EXT TIM_TypeDef *TIM2; +EXT TIM_TypeDef *TIM3; +EXT GPIO_TypeDef *GPIO0; +EXT GPIO_TypeDef *GPIO1; +EXT GPIO_TypeDef *GPIO2; +EXT GPIO_TypeDef *GPIO3; +EXT GPIO_TypeDef *GPIO4; +EXT GPIO_TypeDef *GPIO5; +EXT GPIO_TypeDef *GPIO6; +EXT GPIO_TypeDef *GPIO7; +EXT GPIO_TypeDef *GPIO8; +EXT GPIO_TypeDef *GPIO9; +EXT RTC_TypeDef *RTC; +EXT SCU_TypeDef *SCU; +EXT MC_TypeDef *MC; +EXT UART_TypeDef *UART0; +EXT UART_TypeDef *UART1; +EXT UART_TypeDef *UART2; +EXT SSP_TypeDef *SSP0; +EXT SSP_TypeDef *SSP1; +EXT CAN_TypeDef *CAN; +EXT ADC_TypeDef *ADC; +EXT WDG_TypeDef *WDG; +EXT I2C_TypeDef *I2C0; +EXT I2C_TypeDef *I2C1; +EXT ENET_MAC_TypeDef *ENET_MAC; +EXT ENET_DMA_TypeDef *ENET_DMA; + + +#endif /* DEBUG */ + +#endif /* __91x_MAP_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ + diff --git a/uc_str912/prj_test_lcd/include/91x_scu.h b/uc_str912/prj_test_lcd/include/91x_scu.h new file mode 100644 index 0000000..b9d04f5 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_scu.h @@ -0,0 +1,196 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +* prototypes & definitions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __91x_SCU_H +#define __91x_SCU_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_map.h" + +/* Exported constants --------------------------------------------------------*/ + +/*MCLK_Source*/ +#define SCU_MCLK_PLL 0x0 +#define SCU_MCLK_RTC 0x1 +#define SCU_MCLK_OSC 0x2 + +/*RCLK_Divisor*/ +#define SCU_RCLK_Div1 0xFFFFFFE3 +#define SCU_RCLK_Div2 0x4 +#define SCU_RCLK_Div4 0x8 +#define SCU_RCLK_Div8 0xC +#define SCU_RCLK_Div16 0x10 +#define SCU_RCLK_Div1024 0x14 + +/*HCLK_Divisor*/ +#define SCU_HCLK_Div1 0xFFFFFF9F +#define SCU_HCLK_Div2 0x20 +#define SCU_HCLK_Div4 0x40 + +/*PCLK_Divisor*/ +#define SCU_PCLK_Div1 0xFFFFFE7F +#define SCU_PCLK_Div2 0x80 +#define SCU_PCLK_Div4 0x100 +#define SCU_PCLK_Div8 0x180 + +/*FMICLK_Divisor*/ +#define SCU_FMICLK_Div1 0xFFFEFFFF +#define SCU_FMICLK_Div2 0x10000 + +/*BRCLK_Divisor*/ +#define SCU_BRCLK_Div1 0xFFFFFDFF +#define SCU_BRCLK_Div2 0x200 + +/*TIMCLK_Source*/ +#define SCU_TIMCLK_EXT 0x1 +#define SCU_TIMCLK_INT 0x0 + +/*TIMx*/ +#define SCU_TIM01 0x0 +#define SCU_TIM23 0x1 + + +/*USBCLK_Source*/ +#define SCU_USBCLK_MCLK 0xFFFFF3FF +#define SCU_USBCLK_MCLK2 0x400 +#define SCU_USBCLK_EXT 0x800 + +/*SCU_EMIBCLK*/ +#define SCU_EMIBCLK_Div1 0xFFF9FFFF +#define SCU_EMIBCLK_Div2 0x20000 + +/*SCU_EMIMODE*/ +#define SCU_EMI_MUX 0xFFFFFFBF +#define SCU_EMI_DEMUX 0x40 + +/*SCU_EMIALE_LEN*/ +#define SCU_EMIALE_LEN1 0xFFFFFEFF +#define SCU_EMIALE_LEN2 0x100 + +/*SCU_EMIALE_POL*/ +#define SCU_EMIALE_POLLow 0xFFFFFF7F +#define SCU_EMIALE_POLHigh 0x80 + +/*UART_IrDA_Mode*/ +#define SCU_UARTMode_IrDA 0x1 +#define SCU_UARTMode_UART 0x0 + +/*APBPeriph*/ +#define __TIM01 0x1 +#define __TIM23 0x2 +#define __MC 0x4 +#define __UART0 0x8 +#define __UART1 0x10 +#define __UART2 0x20 +#define __I2C0 0x40 +#define __I2C1 0x80 +#define __SSP0 0x100 +#define __SSP1 0x200 +#define __CAN 0x400 +#define __ADC 0x800 +#define __WDG 0x1000 +#define __WIU 0x2000 +#define __GPIO0 0x4000 +#define __GPIO1 0x8000 +#define __GPIO2 0x10000 +#define __GPIO3 0x20000 +#define __GPIO4 0x40000 +#define __GPIO5 0x80000 +#define __GPIO6 0x100000 +#define __GPIO7 0x200000 +#define __GPIO8 0x400000 +#define __GPIO9 0x800000 +#define __RTC 0x1000000 + +/*AHBPeriph*/ +#define __FMI 0x1 +#define __FPQBC 0x2 +#define __SRAM 0x8 +#define __SRAM_ARBITER 0x10 +#define __VIC 0x20 +#define __EMI 0x40 +#define __EMI_MEM_CLK 0x80 +#define __DMA 0x100 +#define __USB 0x200 +#define __USB48M 0x400 +#define __ENET 0x800 +#define __PFQBC_AHB 0x1000 + +/*SCU_IT*/ +#define SCU_IT_LVD_RST 0x10 +#define SCU_IT_SRAM_ERROR 0x8 +#define SCU_IT_ACK_PFQBC 0x4 +#define SCU_IT_LOCK_LOST 0x2 +#define SCU_IT_LOCK 0x1 + +/*SCU_FLAG*/ +#define SCU_FLAG_SRAM_ERROR 0x20 +#define SCU_FLAG_ACK_PFQBC 0x10 +#define SCU_FLAG_LVD_RESET 0x8 +#define SCU_FLAG_WDG_RST 0x4 +#define SCU_FLAG_LOCK_LOST 0x2 +#define SCU_FLAG_LOCK 0x1 + + +/* Module private variables --------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source); +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP); +ErrorStatus SCU_PLLCmd(FunctionalState NewState); +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor); +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor); +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor); +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState); +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState); +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor); +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source); +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler); +void SCU_USBCLKConfig(u32 USBCLK_Source); +void SCU_PHYCLKConfig(FunctionalState NewState); +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor); +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK); +void SCU_EMIModeConfig(u32 SCU_EMIMODE); +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL); +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState); +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag); +void SCU_ClearFlag(u32 SCU_Flag); +u32 SCU_GetPLLFreqValue(void); +u32 SCU_GetMCLKFreqValue(void); +u32 SCU_GetRCLKFreqValue(void); +u32 SCU_GetHCLKFreqValue(void); +u32 SCU_GetPCLKFreqValue(void); +void SCU_WakeUpLineConfig(u8 EXTint); +void SCU_SpecIntRunModeConfig(FunctionalState NewState); +void SCU_EnterIdleMode(void); +void SCU_EnterSleepMode(void); +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode); +void SCU_PFQBCCmd(FunctionalState NewState); + +#endif /*__91x_SCU_H*/ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/include/91x_type.h b/uc_str912/prj_test_lcd/include/91x_type.h new file mode 100644 index 0000000..916d81c --- /dev/null +++ b/uc_str912/prj_test_lcd/include/91x_type.h @@ -0,0 +1,50 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_type.h +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : It contains common types and constants used in all the +* peripherals' drivers. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +********************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*********************************************************************************/ + +#ifndef __91x_type_H +#define __91x_type_H + + typedef long long u64; + typedef unsigned long u32; + typedef unsigned short u16; + typedef unsigned char u8; + + typedef signed long s32; + typedef signed short s16; + typedef signed char s8; + + typedef volatile unsigned long vu32; + typedef volatile unsigned short vu16; + typedef volatile unsigned char vu8; + + typedef volatile signed long vs32; + typedef volatile signed short vs16; + typedef volatile signed char vs8; + +typedef enum { FALSE = 0, TRUE = !FALSE } bool; + +typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus; + +typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#endif /* __91x_type_H */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/include/char_code.h b/uc_str912/prj_test_lcd/include/char_code.h new file mode 100644 index 0000000..51775e3 --- /dev/null +++ b/uc_str912/prj_test_lcd/include/char_code.h @@ -0,0 +1,79 @@ +#ifndef char_code +#define char_code + +#define A 65 +#define B 66 +#define C 67 +#define D 68 +#define E 69 +#define F 70 +#define G 71 +#define H 72 +#define I 73 +#define J 74 +#define K 75 +#define L 76 +#define M 77 +#define N 78 +#define O 79 +#define P 80 +#define Q 81 +#define R 82 +#define S 83 +#define T 84 +#define U 85 +#define V 86 +#define W 87 +#define X 88 +#define Y 89 +#define Z 90 + +#define a 97 +#define b 98 +#define c 99 +#define d 100 +#define e 101 +#define f 102 +#define g 103 +#define h 104 +#define i 105 +#define j 106 +#define k 107 +#define l 108 +#define m 109 +#define n 110 +#define o 111 +#define p 112 +#define q 113 +#define r 114 +#define s 115 +#define t 116 +#define u 117 +#define v 118 +#define w 119 +#define x 120 +#define y 121 +#define z 122 + +/* +#define . 46 +#define , 44 +#define - 45 +#define ( 40 +#define ) 41 +#define [ 91 +#define ] 93 +#define { 123 +#define } 125 +#define : 58 +#define ; 59 +#define ! 33 +#define % 37 +#define * 42 +#define + 43 +#define = 61 +*/ + +#define space 32 + +#endif diff --git a/uc_str912/prj_test_lcd/include/lcd_lib_91x.h b/uc_str912/prj_test_lcd/include/lcd_lib_91x.h new file mode 100644 index 0000000..bdc4fdb --- /dev/null +++ b/uc_str912/prj_test_lcd/include/lcd_lib_91x.h @@ -0,0 +1,63 @@ +/******************** (C) COPYRIGHT 2007 PROPOX ******************************** +* File Name : lcd_lib_91x.h +* Author : PROPOX Team +* Date First Issued : 09/24/2007 : Version 1.0 +* Description : This file provides all the 2x16 LCD functions. +******************************************************************************** +* History: +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, PROPOX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR +* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion ------------------------------------ */ +#ifndef _lcd_lib_91x_H +#define _lcd_lib_91x_H + +/* Includes ------------------------------------------------------------------*/ +#include "91x_lib.h" +#include "91x_gpio.h" + +/* Private Definision */ +#define D7_set GPIO_WriteBit(GPIO8, GPIO_Pin_3, Bit_SET) +#define D6_set GPIO_WriteBit(GPIO8, GPIO_Pin_2, Bit_SET) +#define D5_set GPIO_WriteBit(GPIO8, GPIO_Pin_1, Bit_SET) +#define D4_set GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_SET) + +#define D7_reset GPIO_WriteBit(GPIO8, GPIO_Pin_3, Bit_RESET) +#define D6_reset GPIO_WriteBit(GPIO8, GPIO_Pin_2, Bit_RESET) +#define D5_reset GPIO_WriteBit(GPIO8, GPIO_Pin_1, Bit_RESET) +#define D4_reset GPIO_WriteBit(GPIO8, GPIO_Pin_0, Bit_RESET) + +#define RS_set GPIO_WriteBit(GPIO8, GPIO_Pin_4, Bit_SET) +#define E_set GPIO_WriteBit(GPIO8, GPIO_Pin_5, Bit_SET) + +#define RS_reset GPIO_WriteBit(GPIO8, GPIO_Pin_4, Bit_RESET) +#define E_reset GPIO_WriteBit(GPIO8, GPIO_Pin_5, Bit_RESET) + +void delay(int time); +void LCDinit(void); +void LCDsendChar(u8 ch); +void LCDsendCommand(u8 cmd); +void LCDclr(void); +void LCDhome(void); +void LCDstring(u8* data, u8 nBytes); +void LCDGotoXY(u8 row, u8 column); +void LCDshiftLeft(u8 right); +void LCDshiftRight(u8 left); +void LCDcursorOn(void); +void LCDcursorOnBlink(void); +void LCDcursorOFF(void); +void LCDblank(void); +void LCDvisible(void); +void LCDcursorLeft(u8 left); +void LCDcursorRight(u8 right); + +#endif /* _lcd_lib_91x_H */ + + +/******************* (C) COPYRIGHT 2007 PROPOX *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/include/vectors.h b/uc_str912/prj_test_lcd/include/vectors.h new file mode 100644 index 0000000..d48e61f --- /dev/null +++ b/uc_str912/prj_test_lcd/include/vectors.h @@ -0,0 +1,67 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +#ifndef _VECTOR_H +#define _VECTOR_H + +#ifdef __cplusplus +extern "C" { +#endif + +void Undefined_Handler(void); +void FIQ_Handler(void); +void SWI_Handler(void); +void Prefetch_Handler(void); +void Abort_Handler(void); +void WDG_IRQHandler(void); +void SW_IRQHandler(void); +void ARMRX_IRQHandler(void); +void ARMTX_IRQHandler(void); +void TIM0_IRQHandler(void); +void TIM1_IRQHandler(void); +void TIM2_IRQHandler(void); +void TIM3_IRQHandler(void); +void USBHP_IRQHandler(void); +void USBLP_IRQHandler(void); +void SCU_IRQHandler(void); +void ENET_IRQHandler(void); +void DMA_IRQHandler(void); +void CAN_IRQHandler(void); +void MC_IRQHandler(void); +void ADC_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void UART2_IRQHandler(void); +void I2C0_IRQHandler(void); +void I2C1_IRQHandler(void); +void SSP0_IRQHandler(void); +void SSP1_IRQHandler(void); +void LVD_IRQHandler(void); +void RTC_IRQHandler(void); +void WIU_IRQHandler(void); +void EXTIT0_IRQHandler(void); +void EXTIT1_IRQHandler(void); +void EXTIT2_IRQHandler(void); +void EXTIT3_IRQHandler(void); +void USBWU_IRQHandler(void); +void PFQBC_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif //_VECTOR_H diff --git a/uc_str912/prj_test_lcd/load_amontec.gdb b/uc_str912/prj_test_lcd/load_amontec.gdb new file mode 100644 index 0000000..8767ed9 --- /dev/null +++ b/uc_str912/prj_test_lcd/load_amontec.gdb @@ -0,0 +1,15 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +set remote hardware-breakpoint-limit 2 +set remote hardware-watchpoint-limit 2 + +target remote localhost:3333 + +monitor reset init +monitor halt + +load lcd.elf +file lcd.elf diff --git a/uc_str912/prj_test_lcd/load_segger.gdb b/uc_str912/prj_test_lcd/load_segger.gdb new file mode 100644 index 0000000..cd9fd7e --- /dev/null +++ b/uc_str912/prj_test_lcd/load_segger.gdb @@ -0,0 +1,20 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:2331 + +monitor speed adaptive +monitor endian little + +monitor reset +monitor flash device = STR912FAW44 +monitor flash breakpoints = 1 +monitor flash download = 1 +monitor halt + + +pwd +load lcd.elf +file lcd.elf diff --git a/uc_str912/prj_test_lcd/src/lcd.c b/uc_str912/prj_test_lcd/src/lcd.c new file mode 100644 index 0000000..9eae1c1 --- /dev/null +++ b/uc_str912/prj_test_lcd/src/lcd.c @@ -0,0 +1,93 @@ +/****************************************************************************** + * www.propox.com + * MMstr912 - Minimodu³ Ethernetowy z procesorem ARM9 STR912. + * Ethernet minimodule with ARM9 STR912 microcontroller. + * + * LCD Test - wyswietla tekst 'www.propox.com' na LCD + * put text 'www.propox.com' on LCD + * + * P8.0, P8.1, P8.2, P8.3 - D4, D5, D6, D7 + * P8.4, P8.5 - RS, E + + * Includes ------------------------------------------------------------------*/ +/* Pliki nag³ówkowe ----------------------------------------------------------*/ +/* Library includes. */ +#include "91x_lib.h" +#include "91x_gpio.h" +#include "91x_map.h" +#include "91x_scu.h" +#include "char_code.h" +#include "lcd_lib_91x.h" + +//#include rem BLa + +/* Hardware Configuration */ +/* Konfiguracja sprzetu */ +void HardwareConf(void) +{ + //Main clock as exesternal oscillator 25MHz + //G³ówny zegar to kwarc 25MHz + SCU_MCLKSourceConfig(SCU_MCLK_OSC); + //Disable reset for GPIO8 + //wylaczenie resetu na GPIO8 + SCU_APBPeriphReset(__GPIO8, DISABLE); + //Enable clock for GPIO8 + //W³¹czenie zegara na GPIO8 + SCU_APBPeriphClockConfig(__GPIO8, ENABLE); +} + + +/* Ports Configuration */ +/* Konfiguracja protow */ +void LCD_DataLinesConfig() +{ + /* Private typedef */ + /* Deklaracja struktury */ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Configure D7~D4 data lines in Output Push-Pull mode */ + /* Konfiguracja lini portu 8 jako wyjsc D7-D4 w trybie push-pull */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5; + GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt1; + GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput; + GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull; + GPIO_Init(GPIO8, &GPIO_InitStructure); + +} + + +int main() +{ +u8 web[] = "www.propox.com"; +u8 title[] = "MMstr912"; + +//Hardware Configuration +//Konfiguracja sprzetu +HardwareConf(); +//Ports Configuration +//Konfiguracja portow +LCD_DataLinesConfig(); + +LCDinit(); +LCDcursorOFF(); +LCDGotoXY(0,0); +LCDstring(web,14); +delay(250000); +LCDGotoXY(3,1); +LCDstring(title,8); + +while(1) +{ + delay(500000); + LCDshiftLeft(1); + delay(100000); + LCDshiftLeft(1); + + delay(500000); + LCDshiftRight(1); + delay(100000); + LCDshiftRight(1); +} + +return 0; +} diff --git a/uc_str912/prj_test_lcd/src/lcd_lib_91x.c b/uc_str912/prj_test_lcd/src/lcd_lib_91x.c new file mode 100644 index 0000000..7c01f53 --- /dev/null +++ b/uc_str912/prj_test_lcd/src/lcd_lib_91x.c @@ -0,0 +1,455 @@ +/******************** (C) COPYRIGHT 2007 PROPOX ******************************** +* File Name : lcd_lib_91x.c +* Author : PROPOX Team +* Date First Issued : 09/24/2007 : Version 1.0 +* Description : This file provides all the 2x16 LCD functions. +******************************************************************************** +* History: +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, PROPOX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR +* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_lib.h" +#include "91x_gpio.h" +#include "91x_map.h" +#include "91x_scu.h" +#include "lcd_lib_91x.h" + + +/******************************************************************************* +* Function Name : delay +* Description : Delay (opoznienie) +* +* Input : time - number of cycles +* Output : None +* Return : None +*******************************************************************************/ +void delay(int time) +{ + while(time--) + asm volatile ("nop"); +} + +/******************************************************************************* +* Function Name : LCDinit +* Description : Inicialize LCD (Inicjalizacja LCD) +* (4 bit data, 2 lines, characters 5x7, blinking cursor on) +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCDinit(void) +{ + GPIO_Write(GPIO8, 0x00); + delay(375000); //15ms + //--------- Write 0x03 ----------- + D7_reset; + D6_reset; + D5_set; + D4_set; + E_set; + delay(25000); //1ms + E_reset; + delay(125000); //5ms + //--------- Write 0x03 ----------- + D7_reset; + D6_reset; + D5_set; + D4_set; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //--------- Write 0x03 ----------- + D7_reset; + D6_reset; + D5_set; + D4_set; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //--------- Enable Four Bit Mode ---------- + D7_reset; + D6_reset; + D5_set; + D4_reset; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //---------- Set Interface Length ---------- + //Write 0x2 - 4 bits + D7_reset; + D6_reset; + D5_set; + D4_reset; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //Write 0x8 - 2 lines, 5x7 + D7_set; + D6_reset; + D5_reset; + D4_reset; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //---------- Turn off the Display ---------- + //Write 0x0 + D7_reset; + D6_reset; + D5_reset; + D4_reset; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //Write 0x8 + D7_set; + D6_reset; + D5_reset; + D4_reset; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //------------ Clear the Display ----------- + //Write 0x0 + D7_reset; + D6_reset; + D5_reset; + D4_reset; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //Write 0x1 + D7_reset; + D6_reset; + D5_reset; + D4_set; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //-------- Set Cursor Move Direction -------- + //Write 0x0 + D7_reset; + D6_reset; + D5_reset; + D4_reset; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //Write 0x6 - Increment the Cursor + D7_reset; + D6_set; + D5_set; + D4_reset; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //---------- Enable Display/Cursor ---------- + //Write 0x0 + D7_reset; + D6_reset; + D5_reset; + D4_reset; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms + //Write 0xF - Display on, cursor on, blink on + D7_set; + D6_set; + D5_set; + D4_set; + E_set; + delay(25000); //1ms + E_reset; + delay(25000); //1ms +} + +/******************************************************************************* +* Function Name : LCDsendChar +* Description : Send Char to LCD (Wyslanie znaku na LCD) +* +* Input : ch - is a ascii code of character or char from char_code.h +* Output : None +* Return : None +*******************************************************************************/ +void LCDsendChar(u8 ch) +{ + //4 MSB bits + //4 starsze bity + GPIO_Write(GPIO8, (ch>>4) & 0x0f); + RS_set; + E_set; + delay(25000); + E_reset; + delay(25000); + //4 LSB bits + //4 mlodsze bity + GPIO_Write(GPIO8, ch & 0x0f); + RS_set; + E_set; + delay(25000); + E_reset; + delay(25000); +} + +/******************************************************************************* +* Function Name : LCDsendCommand +* Description : Send Command to LCD (Wyslanie rozkazu do LCD) +* +* Input : cmd - is a ascii code of command +* Output : None +* Return : None +*******************************************************************************/ +void LCDsendCommand(u8 cmd) +{ + //4 MSB bits + //4 starsze bity + GPIO_Write(GPIO8, (cmd>>4) & 0x0f); + RS_reset; + E_set; + delay(25000); + E_reset; + delay(25000); + //4 LSB bits + //4 mlodsze bity + GPIO_Write(GPIO8, cmd & 0x0f); + RS_reset; + E_set; + delay(25000); + E_reset; + delay(25000); +} + +/******************************************************************************* +* Function Name : LCDclr +* Description : Clear LCD (Czyszczenie LCD) +* +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCDclr(void) +{ + LCDsendCommand(0x01); +} + +/******************************************************************************* +* Function Name : LCDhome +* Description : LCD cursor home (Przesuniecie kursora na pozycje poczatkowa) +* +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCDhome(void) +{ + LCDsendCommand(0x02); +} + +/******************************************************************************* +* Function Name : LCDstring +* Description : Outputs string to LCD (Wyswietl ciag znakow na LCD) +* +* Input : data - pointer to start of table, nBytes - nuber of bytes to send +* Output : None +* Return : None +*******************************************************************************/ +void LCDstring(u8* data, u8 nBytes) +{ + u8 count; + //check to make sure we have a good pointer + //sprawdzenie zgodnosci wskaznika + if (!data) return; + + //print data + //wyswietl znaki + for(count=0; count> 2) /* Boot Bank Base Address */ + STR r1, [r0, #BBADR_off_addr] + + LDR r1, =(0x00080000 >> 2) /* Non Boot Bank Base Address */ + STR r1, [r0, #NBBADR_off_addr] + + LDR r1, =0x18 /* Flash Banks 0 1 enabled */ + STR r1, [r0, #CR_off_addr] + +/* Enable 96K RAM */ + + LDR r0, =SCRO_AHB_UMB +# LDR r1, =0x0196 /* prefetch disabled, default enabled */ + LDR r1, =0x0187|SRAM96 + STR r1, [r0] + +/* Set bits 17-18 (Instruction/Data TCM order) of the */ +/* Core Configuration Control Register */ + + MOV r0, #0x60000 + MCR p15, 0x1, r0, c15, c1, 0 + +/* Setup Stack for each mode */ + +/* Enter Abort Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_ABT|I_Bit|F_Bit + LDR sp, =__stack_abt_end__ + +/* Enter Undefined Instruction Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_UND|I_Bit|F_Bit + LDR sp, =__stack_und_end__ + +/* Enter Supervisor Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SVC|I_Bit|F_Bit + LDR sp, =__stack_svc_end__ + +/* Enter FIQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_FIQ|I_Bit|F_Bit + LDR sp, =__stack_fiq_end__ + +/* Enter IRQ Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit + LDR sp, =__stack_irq_end__ + +/* Enter System/User Mode and set its Stack Pointer */ + + MSR cpsr_c, #Mode_SYS + LDR sp, =__stack_end__ + +/* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */ + + LDR sl, =__bss_end__ + +/* Relocate .data section (Copy from ROM to RAM) */ + + LDR r1, =_etext + LDR r2, =__data_start + LDR r3, =_edata +LoopRel: + CMP r2, r3 + LDRLO r0, [r1], #4 + STRLO r0, [r2], #4 + BLO LoopRel + +/* Clear .bss section (Zero init) */ + + MOV r0, #0 + LDR r1, =__bss_start__ + LDR r2, =__bss_end__ +LoopZI: + CMP r1, r2 + STRLO r0, [r1], #4 + BLO LoopZI + +/* Call C++ constructors */ + + LDR r0, =__ctors_start__ + LDR r1, =__ctors_end__ +ctor_loop: + CMP r0, r1 + BEQ ctor_end + LDR r2, [r0], #4 + STMFD sp!, {r0-r1} + BLX r2 + LDMFD sp!, {r0-r1} + B ctor_loop +ctor_end: + +/* Need to set up standard file handles */ +/* Only used under simulator, normally overide syscall.c */ + +# BL initialise_monitor_handles + +/* if we use debug version of str9lib this will call the init function */ + + BL libdebug +libdebug: + +/* Enter the C code, use B instruction so as to never return */ +/* use BL main if you want to use c++ destructors below */ + + B main + +/* Call destructors */ + +# LDR r0, =__dtors_start__ +# LDR r1, =__dtors_end__ +#dtor_loop: +# CMP r0, r1 +# BEQ dtor_end +# LDR r2, [r0], #4 +# STMFD sp!, {r0-r1} +# BLX r2 +# LDMFD sp!, {r0-r1} +# B dtor_loop +#dtor_end: + +/* Return from main, loop forever. */ + +#exit_loop: +# B exit_loop + +/* Fosc values, used by libstr9 */ + +_Main_Crystal: .long FOSC + + .weak libdebug + + .end diff --git a/uc_str912/prj_test_lcd/src/vector.s b/uc_str912/prj_test_lcd/src/vector.s new file mode 100644 index 0000000..7708f54 --- /dev/null +++ b/uc_str912/prj_test_lcd/src/vector.s @@ -0,0 +1,202 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + + .equ VectorAddress, 0xFFFFF030 /* VIC Vector address register address. */ + .equ VectorAddressDaisy, 0xFC000030 /* Daisy VIC Vector address register */ + + .equ Mode_USR, 0x10 + .equ Mode_FIQ, 0x11 + .equ Mode_IRQ, 0x12 + .equ Mode_SVC, 0x13 + .equ Mode_ABT, 0x17 + .equ Mode_UND, 0x1B + .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */ + + .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ + .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ + + .text + .arm + .section .vectors, "ax" + + .global Reset_Vec + +/* Note: LDR PC instructions are used here, though branch (B) instructions */ +/* could also be used, unless the ROM is at an address >32MB. */ + +/******************************************************************************* + Exception vectors +*******************************************************************************/ + +Reset_Vec: LDR pc, Reset_Addr /* Reset Handler */ +Undef_Vec: LDR pc, Undefined_Addr +SWI_Vec: LDR pc, SWI_Addr +PAbt_Vec: LDR pc, Prefetch_Addr +DAbt_Vec: LDR pc, Abort_Addr + NOP /* Reserved vector */ +IRQ_Vec: LDR pc, IRQ_Addr +FIQ_Vec: LDR pc, FIQ_Addr + +/******************************************************************************* + Exception handlers address table +*******************************************************************************/ + +Reset_Addr: .word _start +Undefined_Addr: .word UndefinedHandler +SWI_Addr: .word SWIHandler +Prefetch_Addr: .word PrefetchHandler +Abort_Addr: .word AbortHandler + .word 0 /* reserved */ +IRQ_Addr: .word IRQHandler +FIQ_Addr: .word FIQHandler + +/******************************************************************************* + Exception Handlers +*******************************************************************************/ + +/******************************************************************************* +* Macro Name : SaveContext +* Description : This macro used to save the context before entering + an exception handler. +* Input : The range of registers to store. +* Output : none +*******************************************************************************/ + +.macro SaveContext reg1 reg2 + STMFD sp!,{\reg1-\reg2,lr} /* Save The workspace plus the current return */ + /* address lr_ mode into the stack */ + MRS r1, spsr /* Save the spsr_mode into r1 */ + STMFD sp!, {r1} /* Save spsr */ +.endm + +/******************************************************************************* +* Macro Name : RestoreContext +* Description : This macro used to restore the context to return from + an exception handler and continue the program execution. +* Input : The range of registers to restore. +* Output : none +*******************************************************************************/ + +.macro RestoreContext reg1 reg2 + LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */ + MSR spsr_cxsf, r1 /* Restore spsr_mode */ + LDMFD sp!, {\reg1-\reg2,pc}^ /* Return to the instruction following */ + /* the exception interrupt */ +.endm + +/******************************************************************************* +* Function Name : IRQHandler +* Description : This function called when IRQ exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +IRQHandler: + SUB lr, lr, #4 /* Update the link register */ + SaveContext r0, r12 /* Save the workspace plus the current */ + /* return address lr_irq and spsr_irq */ + LDR r0, =VectorAddress + LDR r0, [r0] /* Read the routine address */ + LDR r1, =VectorAddressDaisy + LDR r1, [r1] + /* Padding between the acknowledge and re-enable of interrupts */ + /* For more details, please refer to the following URL */ + /* http://www.arm.com/support/faqip/3682.html */ + NOP + NOP + MSR cpsr_c, #Mode_SYS /* Switch to SYS mode and enable IRQ */ + STMFD sp!, {lr} /* Save the link register. */ + LDR lr, =ReturnAddress /* Read the return address. */ + MOV pc, r0 /* Branch to the IRQ handler. */ +ReturnAddress: + LDMFD sp!, {lr} /* Restore the link register. */ + MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit /* Switch to IRQ mode and disable IRQ */ + LDR r0, =VectorAddress /* Write to the VectorAddress to clear the */ + STR r0, [r0] /* respective interrupt in the internal interrupt */ + LDR r1, =VectorAddressDaisy /* Write to the VectorAddressDaisy to clear the */ + STR r1, [r1] /* respective interrupt in the internal interrupt */ + RestoreContext r0, r12 /* Restore the context and return to the program execution. */ + +/******************************************************************************* +* Function Name : SWIHandler +* Description : This function called when SWI instruction executed. +* Input : none +* Output : none +*******************************************************************************/ + +SWIHandler: + SaveContext r0, r12 /* r0 holds swi number */ + MOV r1, sp /* load regs */ + BL SWI_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : UndefinedHandler +* Description : This function called when undefined instruction + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +UndefinedHandler: + SaveContext r0, r12 + BL Undefined_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : PrefetchAbortHandler +* Description : This function called when Prefetch Abort + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +PrefetchHandler: + SUB lr, lr, #4 /* Update the link register. */ + SaveContext r0, r12 + BL Prefetch_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : DataAbortHandler +* Description : This function is called when Data Abort + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +AbortHandler: + SUB lr, lr, #8 /* Update the link register. */ + SaveContext r0, r12 + BL Abort_Handler + RestoreContext r0, r12 + +/******************************************************************************* +* Function Name : FIQHandler +* Description : This function is called when FIQ + exception is entered. +* Input : none +* Output : none +*******************************************************************************/ + +FIQHandler: + SUB lr, lr, #4 /* Update the link register. */ + SaveContext r0, r7 + BL FIQ_Handler + RestoreContext r0, r7 + + .end diff --git a/uc_str912/prj_test_lcd/src/vectors.c b/uc_str912/prj_test_lcd/src/vectors.c new file mode 100644 index 0000000..4022391 --- /dev/null +++ b/uc_str912/prj_test_lcd/src/vectors.c @@ -0,0 +1,462 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +#include "vectors.h" + +/******************************************************************************* +* Function Name : Undefined_Handler +* Description : This function Undefined instruction exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Undefined_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SWI_Handler +* Description : This function handles SW exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SWI_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles preftetch abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Prefetch_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : Abort_Handler +* Description : This function handles data abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Abort_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : FIQ_Handler +* Description : This function handles FIQ exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FIQ_Handler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : WDG_IRQHandler +* Description : This function handles the WDG interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WDG_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SW_IRQHandler +* Description : This function handles the SW interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SW_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ARMRX_IRQHandler +* Description : This function handles the ARMRX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMRX_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ARMTX_IRQHandler +* Description : This function handles the ARMTX interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ARMTX_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM0_IRQHandler +* Description : This function handles the TIM0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM1_IRQHandler +* Description : This function handles the TIM1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM2_IRQHandler +* Description : This function handles the TIM2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : TIM3_IRQHandler +* Description : This function handles the TIM3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void TIM3_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBHP_IRQHandler +* Description : This function handles the USBHP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBHP_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBLP_IRQHandler +* Description : This function handles the USBLP interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBLP_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SCU_IRQHandler +* Description : This function handles the SCU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ENET_IRQHandler +* Description : This function handles the ENET interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ENET_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : DMA_IRQHandler +* Description : This function handles the DMA interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void DMA_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : CAN_IRQHandler +* Description : This function handles the CAN interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void CAN_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : MC_IRQHandler +* Description : This function handles the MC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void MC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : ADC_IRQHandler +* Description : This function handles the ADC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void ADC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART0_IRQHandler +* Description : This function handles the UART0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART1_IRQHandler +* Description : This function handles the UART1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : UART2_IRQHandler +* Description : This function handles the UART2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void UART2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : I2C0_IRQHandler +* Description : This function handles the I2C0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : I2C1_IRQHandler +* Description : This function handles the I2C1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void I2C1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SSP0_IRQHandler +* Description : This function handles the SSP0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : SSP1_IRQHandler +* Description : This function handles the SSP1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SSP1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : LVD_IRQHandler +* Description : This function handles the LVD interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LVD_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : RTC_IRQHandler +* Description : This function handles the RTC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void RTC_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : WIU_IRQHandler +* Description : This function handles the WIU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void WIU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT0_IRQHandler +* Description : This function handles the EXTIT0 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT0_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT1_IRQHandler +* Description : This function handles the EXTIT1 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT1_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT2_IRQHandler +* Description : This function handles the EXTIT2 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT2_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : EXTIT3_IRQHandler +* Description : This function handles the EXTIT3 interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void EXTIT3_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : USBWU_IRQHandler +* Description : This function handles the USBWU interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void USBWU_IRQHandler(void) +{ + while(1); +} + +/******************************************************************************* +* Function Name : PFQBC_IRQHandler +* Description : This function handles the PFQBC interrupt request +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void PFQBC_IRQHandler(void) +{ + while(1); +} diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_ahbapb.c b/uc_str912/prj_test_lcd/str91x_lib/91x_ahbapb.c new file mode 100644 index 0000000..41489ac --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_ahbapb.c @@ -0,0 +1,177 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_ahbapb.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the AHBAPB software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_ahbapb.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#define AHBAPB_SplitCounter_Mask 0xFFE0FFFF +#define AHBAPB_SetTimeOut_Mask 0xFFFFFFE0 +#define AHBAPB_Address_Mask 0xFEFFFFFF +#define AHBAPB_FLAG_RW_Mask 0x01000000 +/******************************************************************************* +* Function Name : AHBAPB_DeInit +* Description : Deinitializes the AHBAPBx peripheral registers to their default +* reset values. +* Input : AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx) +{ + AHBAPBx->BCR = 0x00000000; + AHBAPBx->BSR = 0x00000000; +} +/******************************************************************************* +* Function Name : AHBAPB_Init +* Description : Initializes the AHBAPBx peripheral according to the specified +* parameters in the AHBAPB_InitStruct . +* Input :- AHBAPBx: where x can be 0 or 1 to select the AHBAPB peripheral. +* - AHBAPB_InitStruct: pointer to a AHBAPB_InitTypeDef structure that +* contains the configuration information for the specified AHBAPB +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + + if(AHBAPB_InitStruct->AHBAPB_Split == AHBAPB_Split_Enable) + { + /* Set SPLITEN bit;*/ + AHBAPBx->BCR |= AHBAPB_Split_Enable; + /*Split_CNT bits[20:16]*/ + AHBAPBx->BCR &= AHBAPB_SplitCounter_Mask; + AHBAPBx->BCR |= (AHBAPB_InitStruct->AHBAPB_SplitCounter)<<16; + } + else + { + /*/ Clear SPLITEN bit;*/ + AHBAPBx->BCR &= AHBAPB_Split_Disable; + } + /*APB Time out*/ + if(AHBAPB_InitStruct->AHBAPB_Error == AHBAPB_Error_Enable) + { + /* Set ERREN bit*/ + AHBAPBx->BCR |= AHBAPB_Error_Enable; + /*Time ouit counter*/ + AHBAPBx->BCR &= AHBAPB_SetTimeOut_Mask; + AHBAPBx->BCR |= AHBAPB_InitStruct->AHBAPB_SetTimeOut; + } + else + { + /* Clear ERREN bit*/ + AHBAPBx->BCR &= AHBAPB_Error_Disable; + } +} + +/******************************************************************************* +* Function Name : AHBAPB_StructInit +* Description : Initialize the AHBAPB Init Structure parameters +* Input : AHBAPB_InitStruct : pointer to a AHBAPB_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct) +{ + /* Reset AHBAPB init structure parameters values */ + AHBAPB_InitStruct->AHBAPB_Split = AHBAPB_Split_Enable; + AHBAPB_InitStruct->AHBAPB_SplitCounter = 0xFF; + AHBAPB_InitStruct->AHBAPB_Error = AHBAPB_Error_Enable; + AHBAPB_InitStruct->AHBAPB_SetTimeOut = 0xFF; + +} + +/******************************************************************************* +* Function Name : AHBAPB_GetFlagStatus +* Description : Checks whether the specified AHBAPB flag is set or not. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* - AHBAPB_FLAG_RW : Access type flag +* Output : None +* Return : The new state of AHBAPB_FLAG (SET or RESET). +*******************************************************************************/ +FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + if(AHBAPB_FLAG == AHBAPB_FLAG_RW) + { + if ((AHBAPBx->PAER & AHBAPB_FLAG_RW_Mask) == RESET) + { + return RESET; + } + else + { + return SET; + } + } + else + { + if ((AHBAPBx->BSR & AHBAPB_FLAG) == RESET) + { + return RESET; + } + else + { + return SET; + } + } +} +/******************************************************************************* +* Function Name : AHBAPB_ClearFlag +* Description : Clears the AHBAPBx flags. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* - AHBAPB_FLAG: flags to clear. This parameter one of the +* following values: +* - AHBAPB_FLAG_ERROR: error flag +* - AHBAPB_FLAG_OUTM : Out of Memory flag +* - AHBAPB_FLAG_APBT : APB Time-out flag +* Output : None +* Return : None +*******************************************************************************/ +void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG) +{ + /* Clear the flag */ + AHBAPBx->BSR &= AHBAPB_FLAG; +} +/******************************************************************************* +* Function Name : AHBAPB_GetPeriphAddrError +* Description : Gets the AHBAPB error address peripherals. +* Input : - AHBAPB: where x can be 0 or 1 to select the AHBAPB peripheral +* Output : None +* Return : The Peropheral address error +*******************************************************************************/ +u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx) +{ + u32 AHBAPB_Address = 0x00000000; + + /*Return Oeripheral address without RW bit*/ + AHBAPB_Address = (AHBAPBx->PAER)& AHBAPB_Address_Mask; + return (AHBAPB_Address); +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_fmi.c b/uc_str912/prj_test_lcd/str91x_lib/91x_fmi.c new file mode 100644 index 0000000..fb558ad --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_fmi.c @@ -0,0 +1,519 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_fmi.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the FMI software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + + +/* Standard include ----------------------------------------------------------*/ +#include "91x_fmi.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define TIMEOUT 0xFFFFFF /* Timeout value */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/******************************************************************************* +* Function Name : FMI_BankRemapConfig +* Description : Configure the addresses and sizes of bank 0 and bank 1. +* Input1 : FMI_BootBankSize: specifies the boot bank size. +* This parameter can be one of the following values: +* - 0x0: 32KBytes. +* - 0x1: 64KBytes. +* - 0x2: 128KBytes. +* - 0x3: 256KBytes. +* - 0x4: 512KBytes. +* .... +* - 0xB: 64MBytes. +* Input2 : FMI_NonBootBankSize: specifies the non boot bank size. +* This parameter can be one of the following values: +* - 0x0: 8KBytes. +* - 0x1: 16KBytes. +* - 0x2: 32KBytes. +* - 0x3: 64KBytes. +* .... +* - 0xD: 64MBytes. +* Input3 : FMI_BootBankAddress: specifies the address of the boot bank. +* Input4 : FMI_NonBootBankAddress: specifies the address of the non +* boot bank. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \ + u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress) +{ + FMI->BBSR = FMI_BootBankSize; + FMI->NBBSR = FMI_NonBootBankSize; + FMI->BBADR = (FMI_BootBankAddress >> 2); + FMI->NBBADR = (FMI_NonBootBankAddress >> 2); + FMI->CR |= 0x18; /* Enable bank 1 */ +} + +/******************************************************************************* +* Function Name : FMI_Config +* Description : Configure the FMI. +* Input1 : FMI_ReadWaitState: specifies the needed read wait states. +* This parameter can be one of the following values: +* - FMI_READ_WAIT_STATE_1: One read wait state. +* - FMI_READ_WAIT_STATE_2: Two read wait states. +* - FMI_READ_WAIT_STATE_3: Three read wait states. +* Input2 : FMI_WriteWaitState: specifies the needed write wait states. +* This parameter can be one of the following values: +* - FMI_WRITE_WAIT_STATE_1: One write wait state. +* - FMI_WRITE_WAIT_STATE_2: Two write wait states. +* Input3 : FMI_PWD: specifies the power down mode status. +* This parameter can be one of the following values: +* - FMI_PWD_ENABLE: Enable the PWD. +* - FMI_PWD_DISABLE: Disable the PWD. +* Input4 : FMI_LVDEN: specifies the low voltage detector status. +* This parameter can be one of the following values: +* - FMI_LVD_ENABLE: Enable the LVD. +* - FMI_LVD_DISABLE: Disable the LVD. +* Input5 : FMI_FreqRange: specifies the working frequency range. +* This parameter can be one of the following values: +* - FMI_FREQ_LOW: Low working frequency (up to 66MHz). +* - FMI_FREQ_HIGH: High working frequency (above 66MHz) . +* Output : None +* Return : None +*******************************************************************************/ +void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\ + u16 FMI_LVDEN, u16 FMI_FreqRange) +{ + /* Configure the write wait state value */ + if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1) + { + FMI->CR |= FMI_WRITE_WAIT_STATE_1; + } + else + { + FMI->CR &= FMI_WRITE_WAIT_STATE_0; + } + + /* Write a write flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x60; + + /* Configure the flash configuration register */ + *(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03; +} + +/******************************************************************************* +* Function Name : FMI_EraseSector +* Description : Erase the needed sector. +* Input : FMI_Sector: specifies the sector to be erased. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseSector(vu32 FMI_Sector) +{ + /* Write an erase set-up command to the sector */ + *(vu16 *)FMI_Sector = 0x20; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Sector = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_EraseBank +* Description : Erase the needed bank. +* Input : FMI_Bank: specifies the bank to be erased. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_EraseBank(vu32 FMI_Bank) +{ + /* Write a bank erase set-up command to the bank */ + *(vu16 *)FMI_Bank = 0x80; + + /* Write an erase confirm command to the sector */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_WriteHalfWord +* Description : Write a halfword to the needed Flash memory address. +* Input 1 : FMI_Address: specifies the address offset where the data will +* be written. +* Input 2 : FMI_Data: the needed data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data) +{ + /* Write a program command to the sector to be written */ + *(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40; + + /* Write the halfword to the destination address */ + *(vu16 *)FMI_Address = FMI_Data; +} + +/******************************************************************************* +* Function Name : FMI_WriteOTPHalfWord +* Description : Write a halfword to the needed OTP sector address. +* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset +* where the data will be written. +* This parameter can be one of the following values: +* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0. +* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0. +* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1. +* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1. +* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2. +* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2. +* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3. +* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3. +* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4. +* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4. +* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5. +* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5. +* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6. +* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6. +* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7. +* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7. +* Input 2 : FMI_OTPData: The needed OTP data. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData) +{ + /* Write a write OTP command to the needed address */ + *(vu16 *)(FMI_BANK_1) = 0xC0; + + /* Write the halfword to the destination address */ + *(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData; +} + +/******************************************************************************* +* Function Name : FMI_ReadWord +* Description : Read the correspondent data. +* Input : FMI_Address: specifies the needed address. +* Output : None +* Return : The data contained in the specified address. +*******************************************************************************/ +u32 FMI_ReadWord(u32 FMI_Address) +{ + return(*(u32*)FMI_Address); +} + +/******************************************************************************* +* Function Name : FMI_ReadOTPData +* Description : Read data from the OTP sector. +* Input : FMI_OTPAddress: specifies the address of the data to be read. +* This parameter can be one of the following values: +* - FMI_OTP_WORD_0: FMI bank 0 sector 0. +* - FMI_OTP_WORD_1: FMI bank 0 sector 1. +* - FMI_OTP_WORD_2: FMI bank 0 sector 2. +* - FMI_OTP_WORD_3: FMI bank 0 sector 3. +* - FMI_OTP_WORD_4: FMI bank 0 sector 4. +* - FMI_OTP_WORD_5: FMI bank 0 sector 5. +* - FMI_OTP_WORD_6: FMI bank 0 sector 6. +* - FMI_OTP_WORD_7: FMI bank 0 sector 7. +* Output : None +* Return : The needed OTP words. +*******************************************************************************/ +u32 FMI_ReadOTPData(u8 FMI_OTPAddress) +{ + u32 OTP_Data = 0x0; + /* write a read OTP sector command */ + *(vu16 *)(FMI_BANK_1) = 0x98; + + /* Read the correspondent data */ + OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress)); + + /* Write a read array command */ + *(vu16 *)(FMI_BANK_1) = 0xFF; + + return OTP_Data; +} + +/******************************************************************************* +* Function Name : FMI_GetFlagStatus +* Description : Check whether the specified FMI flag is set or not. +* Input1 : FMI_Flag: flag to check. +* This parameter can be one of the following values: +* - FMI_FLAG_SPS: Sector Protection Status Flag. +* - FMI_FLAG_PSS: Program Suspend Status Flag. +* - FMI_FLAG_PS: Program Status Flag. +* - FMI_FLAG_ES: Erase Status Flag. +* - FMI_FLAG_ESS: Erase Suspend Status Flag. +* - FMI_FLAG_PECS: FPEC Status Flag. +* Input2 : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank) +{ + u16 FMI_Status_Register = 0; + + /* Write a read status register command */ + *(vu16 *)FMI_Bank = 0x70; + + /* Wait until operation completion */ + while(!((*(vu16 *)FMI_Bank) & 0x80)); + + /* Read the status register */ + FMI_Status_Register = *(vu16 *)FMI_Bank; + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if((FMI_Status_Register & FMI_Flag) != RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_GetReadWaitStateValue +* Description : Get the current Read wait state value. +* Input : None +* Output : None +* Return : The current read wait states value. +*******************************************************************************/ +u16 FMI_GetReadWaitStateValue(void) +{ + u16 FMI_Configuration_Register = 0; + /* Write a read flash configuration register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash configuration register */ + FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3; + + /* Return the wait states value */ + return FMI_Configuration_Register; +} + +/******************************************************************************* +* Function Name : FMI_GetWriteWaitStateValue +* Description : Get the current write wait state value. +* Input : None +* Output : None +* Return : The current write wait states value. +*******************************************************************************/ +u16 FMI_GetWriteWaitStateValue(void) +{ + return ((u16)((FMI->CR & 0x100) >> 8)); +} + +/******************************************************************************* +* Function Name : FMI_SuspendEnable +* Description : Suspend command enable. +* Input : FMI_Bank: specifies the bank to be suspended. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_SuspendEnable(vu32 FMI_Bank) +{ + /* Write a suspend command to the bank */ + *(vu16 *)FMI_Bank = 0xB0; +} + +/******************************************************************************* +* Function Name : FMI_ResumeEnable +* Description : Resume the suspended command. +* Input : FMI_Bank: specifies the suspended bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ResumeEnable(vu32 FMI_Bank) +{ + /* Write a resume command to the bank */ + *(vu16 *)FMI_Bank = 0xD0; +} + +/******************************************************************************* +* Function Name : FMI_ClearFlag +* Description : Clear the FMI Flags on the correspondent bank. +* Input : FMI_Bank: specifies the needed bank. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_ClearFlag(vu32 FMI_Bank) +{ + /* Write a clear status register command */ + *(vu16 *)FMI_Bank = 0x50; +} + +/******************************************************************************* +* Function Name : FMI_WriteProtectionCmd +* Description : Enable or disable the write protection for the needed sector. +* Input1 : FMI_Sector: specifies the sector to be protected or +* unprotected. +* This parameter can be one of the following values: +* - FMI_B0S0: FMI bank 0 sector 0. +* - FMI_B0S1: FMI bank 0 sector 1. +* - FMI_B0S2: FMI bank 0 sector 2. +* - FMI_B0S3: FMI bank 0 sector 3. +* - FMI_B0S4: FMI bank 0 sector 4. +* - FMI_B0S5: FMI bank 0 sector 5. +* - FMI_B0S6: FMI bank 0 sector 6. +* - FMI_B0S7: FMI bank 0 sector 7. +* - FMI_B1S0: FMI bank 1 sector 0. +* - FMI_B1S1: FMI bank 1 sector 1. +* - FMI_B1S2: FMI bank 1 sector 2. +* - FMI_B1S3: FMI bank 1 sector 3. +* Input2 : FMI_NewState: specifies the protection status. +* This parameter can be one of the following values: +* - ENABLE: Enable the protection. +* - DISABLE: Disable the protection. +* Output : None +* Return : None +*******************************************************************************/ +void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState) +{ + if (FMI_NewState == ENABLE) + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0x01; + *(vu16*)FMI_Sector = 0xFF; + } + else /* DISABLE */ + { + *(vu16*)FMI_Sector = 0x60; + *(vu16*)FMI_Sector = 0xD0; + *(vu16*)FMI_Sector = 0xFF; + } +} + +/******************************************************************************* +* Function Name : FMI_GetWriteProtectionStatus +* Description : Get the write protection status for the needed sector. +* Input : FMI_Sector_Mask: specifies the needed sector mask. +* This parameter can be one of the following values: +* - FMI_B0S0_MASK: FMI bank 0 sector 0. +* - FMI_B0S1_MASK: FMI bank 0 sector 1. +* - FMI_B0S2_MASK: FMI bank 0 sector 2. +* - FMI_B0S3_MASK: FMI bank 0 sector 3. +* - FMI_B0S4_MASK: FMI bank 0 sector 4. +* - FMI_B0S5_MASK: FMI bank 0 sector 5. +* - FMI_B0S6_MASK: FMI bank 0 sector 6. +* - FMI_B0S7_MASK: FMI bank 0 sector 7. +* - FMI_B1S0_MASK: FMI bank 1 sector 0. +* - FMI_B1S1_MASK: FMI bank 1 sector 1. +* - FMI_B1S2_MASK: FMI bank 1 sector 2. +* - FMI_B1S3_MASK: FMI bank 1 sector 3. +* Output : None +* Return : The Protection Status of the needed sector. +* - RESET: The needed sector is not write protected. +* - SET : The needed sector is write protected. +*******************************************************************************/ +FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask) +{ + u16 Protection_Level_1_Register = 0; + /* Write a read flash protection level 1 register command */ + *(vu16 *)FMI_BANK_1 = 0x90; + + /* Read the flash protection level 1 register */ + Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10); + + /* Write a read array command */ + *(vu16 *)FMI_BANK_1 = 0xFF; + + if (Protection_Level_1_Register &= FMI_Sector_Mask) + { + return SET; + } + else + { + return RESET; + } +} + +/******************************************************************************* +* Function Name : FMI_WaitForLastOperation +* Description : Wait until the last operation (Write halfword, Write OTP +* halfword, Erase sector and Erase bank) completion. +* Input : FMI_Bank: specifies the bank where the operation is on going. +* This parameter can be one of the following values: +* - FMI_BANK_0: FMI bank 0. +* - FMI_BANK_1: FMI bank 1. +* Output : None +* Return : The timeout status. +* This parameter can be one of the following values: +* - FMI_TIME_OUT_ERROR: Timeout error occurred. +* - FMI_NO_TIME_OUT_ERROR: No timeout error. +*******************************************************************************/ +u8 FMI_WaitForLastOperation(vu32 FMI_Bank) +{ + u32 Time_Out = 0; + + /* Write a read status register command */ + *(vu16 *)(FMI_Bank) = 0x70; + + /* Wait until operation compeletion */ + while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT )) + { + Time_Out ++; /* Time Out */ + } + + /* Write a read array command */ + *(vu16 *)FMI_Bank = 0xFF; + + if (Time_Out == TIMEOUT) + { + return FMI_TIME_OUT_ERROR; + } + else + { + return FMI_NO_TIME_OUT_ERROR; + } +} + + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_gpio.c b/uc_str912/prj_test_lcd/str91x_lib/91x_gpio.c new file mode 100644 index 0000000..f2d0941 --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_gpio.c @@ -0,0 +1,407 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_gpio.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all the GPIO software functions. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_gpio.h" +#include "91x_scu.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx); + +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : GPIO_DeInit +* Description : Deinitializes the GPIOx peripheral registers to their default +* reset values. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + + /* Reset the GPIO registers values */ + if(GPIOx == GPIO0) + { + SCU_APBPeriphReset(__GPIO0,ENABLE); + SCU_APBPeriphReset(__GPIO0,DISABLE); + SCU->GPIOTYPE[0x00] = 0x0000 ; + SCU->GPIOOUT[0x00] = 0x0000; + SCU->GPIOIN[0x00] = 0x0000; + } + + if(GPIOx == GPIO1) + { + SCU_APBPeriphReset(__GPIO1,ENABLE); + SCU_APBPeriphReset(__GPIO1,DISABLE); + SCU->GPIOTYPE[0x01] = 0x0000 ; + SCU->GPIOOUT[0x01] = 0x0000; + SCU->GPIOIN[0x01] = 0x0000; + } + + if(GPIOx == GPIO2) + { + SCU_APBPeriphReset(__GPIO2,ENABLE); + SCU_APBPeriphReset(__GPIO2,DISABLE); + SCU->GPIOTYPE[0x02] = 0x0000 ; + SCU->GPIOOUT[0x02] = 0x0000; + SCU->GPIOIN[0x02] = 0x0000; + } + + if(GPIOx == GPIO3) + { + SCU_APBPeriphReset(__GPIO3,ENABLE); + SCU_APBPeriphReset(__GPIO3,DISABLE); + SCU->GPIOTYPE[0x03] = 0x0000 ; + SCU->GPIOOUT[0x03] = 0x0000; + SCU->GPIOIN[0x03] = 0x0000; + } + + if(GPIOx == GPIO4) + { + SCU_APBPeriphReset(__GPIO4,ENABLE); + SCU_APBPeriphReset(__GPIO4,DISABLE); + SCU->GPIOTYPE[0x04] = 0x0000 ; + SCU->GPIOOUT[0x04] = 0x0000; + SCU->GPIOIN[0x04] = 0x0000; + SCU->GPIOANA = 0x00; + } + + if(GPIOx == GPIO5) + { + SCU_APBPeriphReset(__GPIO5,ENABLE); + SCU_APBPeriphReset(__GPIO5,DISABLE); + SCU->GPIOTYPE[0x05] = 0x0000 ; + SCU->GPIOOUT[0x05] = 0x0000; + SCU->GPIOIN[0x05] = 0x0000; + } + + if(GPIOx == GPIO6) + { + SCU_APBPeriphReset(__GPIO6,ENABLE); + SCU_APBPeriphReset(__GPIO6,DISABLE); + SCU->GPIOTYPE[0x06] = 0x0000 ; + SCU->GPIOOUT[0x06] = 0x0000; + SCU->GPIOIN[0x06] = 0x0000; + } + + if(GPIOx == GPIO7) + { + SCU_APBPeriphReset(__GPIO7,ENABLE); + SCU_APBPeriphReset(__GPIO7,DISABLE); + SCU->GPIOOUT[0x07] = 0xAAAA; + SCU->GPIOOUT[0x07] = 0x0000; + SCU->GPIOIN[0x07] = 0x0000; + } + + if(GPIOx == GPIO8) + { + SCU_APBPeriphReset(__GPIO8,ENABLE); + SCU_APBPeriphReset(__GPIO8,DISABLE); + SCU->GPIOEMI = 0x00; + } + + if(GPIOx == GPIO9) + { + SCU_APBPeriphReset(__GPIO9,ENABLE); + SCU_APBPeriphReset(__GPIO9,DISABLE); + SCU->GPIOEMI = 0x00; + } +} +/******************************************************************************* +* Function Name : GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct . +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Select pin direction */ + u8 PinNumber = 0; + u8 Counter = 0; + u8 GPIO_Number = 0; + + GPIO_Number = GPIO_GetGPIONumber(GPIOx); + + + if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput) + { + GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin; + } + else + { + GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin; + } + + for (Counter = 0; Counter < 8;Counter++) + { + /*Search pin number*/ + PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <> Counter) == 1) + { + /*Output ALternate 0*/ + SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2)); + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1) + { + /*Output ALternate 1*/ + SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2) + { + /*Output ALternate 2*/ + SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2); + } + if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3) + { + /*Output ALternate 3*/ + SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2); + } + + /*Type configuration: PushPull or Open Collector*/ + SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector) + { + /*Open Drain configuration*/ + SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter; + } + + /*IP Connected disable*/ + SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ; + if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable) + { + /*IP Connected enable*/ + SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter; + } + } + } +} + +/******************************************************************************* +* Function Name : GPIO_StructInit +* Description : Initialize the GPIO Init Structure parameters +* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Direction = GPIO_PinInput; + GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull; + GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable; + GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1; +} + +/******************************************************************************* +* Function Name : GPIO_ReadBit +* Description : Reads the specified port pin +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* Output : None +* Return : The port pin value +*******************************************************************************/ +u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin) +{ + if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET ) + { + return Bit_SET; + } + else + { + return Bit_RESET; + } +} + +/******************************************************************************* +* Function Name : GPIO_Read +* Description : Reads the specified GPIO data port +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO data port word value. +*******************************************************************************/ +u8 GPIO_Read(GPIO_TypeDef* GPIOx) +{ + return (GPIOx->DR[0x3FC]); +} + +/******************************************************************************* +* Function Name : GPIO_WriteBit +* Description : Sets or clears the selected data port bit. +* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x +* where x can be (0..7). +* - BitVal: this parameter specifies the value to be written +* to the selected bit. +* BitVal must be one of the BitAction enum values: +* - Bit_RESET: to clear the port pin +* - Bit_SET: to set the port pin +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal) +{ + if(BitVal == Bit_SET) + { + GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin; + } + else + { + GPIOx->DR[GPIO_Pin <<2] = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_Write +* Description : Writes the passed value in the selected data GPIOx port +* register. +* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral. +* - PortVal: the value to be written to the data port register. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal) +{ + GPIOx->DR[0x3FC] = PortVal; +} + +/******************************************************************************* +* Function Name : GPIO_EMIConfig +* Description : Enables or disables GPIO 8 and 9 in EMI mode. +* Input : - NewState: new state of the EMI. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_EMIConfig(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + SCU->GPIOEMI = 0x01; + } + else + { + SCU->GPIOEMI = 0x00; + } +} + +/******************************************************************************* +* Function Name : GPIO_ANAPinConfig +* Description : Enables or disables pins from GPIO 4 in Analogue mode. +* Input :- GPIO_ANAChannel: selects the ADC channel pin. +* This parameter can be one of the following values: +* GPIO_ANAChannel0 +* GPIO_ANAChannel1 +* GPIO_ANAChannel2 +* GPIO_ANAChannel3 +* GPIO_ANAChannel4 +* GPIO_ANAChannel5 +* GPIO_ANAChannel6 +* GPIO_ANAChannel7 +* GPIO_ANAChannelALL +* - NewState: new state of the port pin. +* This parameter can be: ENABLE or DISABLE. +* Output : None +* Return : None +*******************************************************************************/ +void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState) +{ + + if(NewState == ENABLE) + { + if(GPIO_ANAChannel == GPIO_ANAChannelALL) + { + SCU->GPIOOUT[4] = 0x0000; + SCU->GPIOIN[4] = 0x00; + } + else + { + SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1)); + SCU->GPIOIN[4] &= ~GPIO_ANAChannel; + } + SCU->GPIOANA |= GPIO_ANAChannel; + + } + else + { + SCU->GPIOANA &= ~GPIO_ANAChannel; + } +} + +/******************************************************************************* +* Function Name : GPIO_GetGPIONumber +* Description : searche the GPIO number. +* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral. +* Output : None +* Return : GPIO number +*******************************************************************************/ +u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx) +{ + + if(GPIOx == GPIO1) + { + return 1; + } + if(GPIOx == GPIO2) + { + return 2; + } + if(GPIOx == GPIO3) + { + return 3; + } + if(GPIOx == GPIO4) + { + return 4; + } + if(GPIOx == GPIO5) + { + return 5; + } + if(GPIOx == GPIO6) + { + return 6; + } + if(GPIOx == GPIO7) + { + return 7; + } + if(GPIOx == GPIO8) + { + return 8; + } + if(GPIOx == GPIO9) + { + return 9; + } + return 0; +} +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_lib.c b/uc_str912/prj_test_lcd/str91x_lib/91x_lib.c new file mode 100644 index 0000000..c0eadbb --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_lib.c @@ -0,0 +1,281 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_lib.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides all peripherals pointers + : initialization. +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#define EXT + +/* Standard include ----------------------------------------------------------*/ +#include "91x_map.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#ifdef DEBUG + +/******************************************************************************* +* Function Name : debug +* Description : this function initialize peripherals pointers +* Input : no one +* Output : no one +* Return : no one +*******************************************************************************/ +void debug(void) +{ + + +/************************* DMA *************************/ + +#ifdef _DMA + DMA = (DMA_TypeDef *)DMA_BASE; +#endif /* _DMA */ + +/************************* DMA *************************/ + + +#ifdef _DMA_Channel0 + DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE; +#endif /* _DMA_Channel0 */ + +#ifdef _DMA_Channel1 + DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE; +#endif /* _DMA_Channel1 */ + +#ifdef _DMA_Channel2 + DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE; +#endif /* _DMA_Channel2 */ + +#ifdef _DMA_Channel3 + DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE; +#endif /* _DMA_Channel3 */ + +#ifdef _DMA_Channel4 + DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE; +#endif /* _DMA_Channel4 */ + +#ifdef _DMA_Channel5 + DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE; +#endif /* _DMA_Channel5*/ + + +#ifdef _DMA_Channel6 + DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE; +#endif /* _DMA_Channel6 */ + +#ifdef _DMA_Channel7 + DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE; +#endif /* _DMA_Channel7 */ + + + + /************************* EMI *************************/ + +#ifdef _EMI_Bank0 + EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE; +#endif /* _EMI_Bank0 */ + +#ifdef _EMI_Bank1 + EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE; +#endif /* _EMI_Bank1 */ + +#ifdef _EMI_Bank2 + EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE; +#endif /* _EMI_Bank2 */ + +#ifdef _EMI_Bank3 + EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE; + #endif /* _EMI_Bank3 */ + + + +/************************* AHBAPB *************************/ + +#ifdef _AHBAPB0 + AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE; +#endif /* _AHBAPB0 */ + +#ifdef _AHBAPB1 + AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE; +#endif /*_AHBAPB1 */ + + + +/************************* FMI *************************/ + +#ifdef _FMI + FMI = (FMI_TypeDef *)FMI_BASE; +#endif /* _FMI */ + +/************************* VIC *************************/ + +#ifdef _VIC0 + VIC0 = (VIC_TypeDef *)VIC0_BASE; +#endif /* _VIC0 */ + +#ifdef _VIC1 + VIC1 = (VIC_TypeDef *)VIC1_BASE; +#endif /* _VIC1 */ + +/************************* WIU *************************/ + +#ifdef _WIU + WIU = (WIU_TypeDef *)WIU_BASE; +#endif /* _WIU */ + +/************************* TIM *************************/ + +#ifdef _TIM0 + TIM0 = (TIM_TypeDef *)TIM0_BASE; +#endif /* _TIM0 */ + +#ifdef _TIM1 + TIM1 = (TIM_TypeDef *)TIM1_BASE; +#endif /* _TIM1 */ + +#ifdef _TIM2 + TIM2 = (TIM_TypeDef *)TIM2_BASE; +#endif /* _TIM2 */ + +#ifdef _TIM3 + TIM3 = (TIM_TypeDef *)TIM3_BASE; +#endif /* _TIM3 */ + +/************************* GPIO ************************/ + +#ifdef _GPIO0 + GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; +#endif /* _GPIO0 */ + +#ifdef _GPIO1 + GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; +#endif /* _GPIO1 */ + +#ifdef _GPIO2 + GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; +#endif /* _GPIO2 */ + +#ifdef _GPIO3 + GPIO3 = (GPIO_TypeDef *)GPIO3_BASE; +#endif /* _GPIO3 */ + +#ifdef _GPIO4 + GPIO4 = (GPIO_TypeDef *)GPIO4_BASE; +#endif /* _GPIO4 */ + +#ifdef _GPIO5 + GPIO5 = (GPIO_TypeDef *)GPIO5_BASE; +#endif /* _GPIO5 */ + +#ifdef _GPIO6 + GPIO6 = (GPIO_TypeDef *)GPIO6_BASE; +#endif /* _GPIO6 */ + +#ifdef _GPIO7 + GPIO7 = (GPIO_TypeDef *)GPIO7_BASE; +#endif /* _GPIO7 */ + +#ifdef _GPIO8 + GPIO8 = (GPIO_TypeDef *)GPIO8_BASE; +#endif /* _GPIO8 */ + +#ifdef _GPIO9 + GPIO9 = (GPIO_TypeDef *)GPIO9_BASE; +#endif /* _GPIO9 */ + +/************************* RTC *************************/ + +#ifdef _RTC + RTC = (RTC_TypeDef *)RTC_BASE; +#endif /* _RTC */ + +/************************* PRCCU ***********************/ + +#ifdef _SCU + SCU = (SCU_TypeDef *)SCU_BASE; +#endif /* _PRCCU */ + +/************************** MC *************************/ + +#ifdef _MC + MC = (MC_TypeDef *)MC_BASE; +#endif /* _MC */ + +/************************* UART ************************/ + +#ifdef _UART0 + UART0 = (UART_TypeDef *)UART0_BASE; +#endif /* _UART0 */ + +#ifdef _UART1 + UART1 = (UART_TypeDef *)UART1_BASE; +#endif /* _UART1 */ + +#ifdef _UART2 + UART2 = (UART_TypeDef *)UART2_BASE; +#endif /* _UART2 */ + +/************************* SSP *************************/ + +#ifdef _SSP0 + SSP0 = (SSP_TypeDef *)SSP0_BASE; +#endif /* _SSP0 */ + +#ifdef _SSP1 + SSP1 = (SSP_TypeDef *)SSP1_BASE; +#endif /* _SSP1 */ + +/************************* CAN *************************/ + +#ifdef _CAN + CAN = (CAN_TypeDef *)CAN_BASE; +#endif /* _CAN */ + +/************************* ADC *************************/ + +#ifdef _ADC + ADC = (ADC_TypeDef *)ADC_BASE; +#endif /* _ADC */ + +/************************* WDG *************************/ + +#ifdef _WDG + WDG = (WDG_TypeDef *)WDG_BASE; +#endif /* _WDG */ + +/************************* I2C *************************/ + +#ifdef _I2C0 + I2C0 = (I2C_TypeDef *)I2C0_BASE; +#endif /* _I2C0 */ + +#ifdef _I2C1 + I2C1 = (I2C_TypeDef *)I2C1_BASE; +#endif /* _I2C1 */ +/********************** ENET **************************/ +#ifdef _ENET + ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE; + ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE; +#endif /* _ENET */ +} +#endif /* DEBUG */ + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/prj_test_lcd/str91x_lib/91x_scu.c b/uc_str912/prj_test_lcd/str91x_lib/91x_scu.c new file mode 100644 index 0000000..21116b2 --- /dev/null +++ b/uc_str912/prj_test_lcd/str91x_lib/91x_scu.c @@ -0,0 +1,661 @@ +/******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +* File Name : 91x_scu.c +* Author : MCD Application Team +* Date First Issued : 05/18/2006 : Version 1.0 +* Description : This file provides the SCU library software functions +******************************************************************************** +* History: +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "91x_scu.h" + +/* Include of other module interface headers ---------------------------------*/ +/* Local includes ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define SCU_PLLEN 0x80000 +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Interface functions -------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************* +* Function Name : SCU_MCLKSourceConfig +* Description : Configures the MCLK source clock +* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : this function returns ERROR if trying to select the PLL as +* clock source while the PLL is disabled or not locked. +*******************************************************************************/ +ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source) +{ + u32 CLKCNTR_Value; + + CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/ + CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/ + if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/ + { + /*check if PLL enabled & locked*/ + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + return ERROR; + } + else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/ + SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/ + return SUCCESS; +} + +/******************************************************************************* +* Function Name : SCU_PLLFactorsConfig +* Description : Sets the PLL factors +* Input : PLLN, PLLM and PLLP +* Output : None +* Return : ErrorStatus: ERROR or SUCCESS +* Notes : -The PLL factors must respect the PLL specification requirements +* -The function returns ERROR if trying to change PLL +* factors while PLL is selected as Main Clock source (MCLK) +* -This function disables the PLL, to enable the PLL use +* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors +******************************************************************************/ +ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP) +{ + if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/ + { + SCU->PLLCONF =0; /*clear PLLCONF register*/ + SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/ + SCU->PLLCONF |=PLLM; /*update PLLM field*/ + SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/ + return SUCCESS; + } + return ERROR; +} + +/******************************************************************************* +* Function Name : SCU_PLLCmd +* Description : Enable or Disable the PLL +* Input : NewState = ENABLE or DISABLE +* Output : None +* Return : ErrorStatus: SUCCESS or ERROR +* Note : -The function returns ERROR if: +* *trying to disable the PLL while it is selected as the MCLK +* *trying to enable the PLL while it is already enabled and +* locked +*******************************************************************************/ +ErrorStatus SCU_PLLCmd(FunctionalState NewState) +{ + vu32 i; + if (NewState==ENABLE) + { + if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK))) + { + SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/ + SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/ + while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/ + return SUCCESS; + } + else return ERROR; + } + else /*NewState = DISABLE*/ + { + if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/ + { + for(i=10;i>0;i--); /*delay before PLL disabling*/ + SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/ + return SUCCESS; + } + else return ERROR; + } +} + +/******************************************************************************* +* Function Name : SCU_RCLKDivisorConfig +* Description : Sets the RCLK divisor value +* Input : RCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_RCLKDivisorConfig(u32 RCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/ + if (RCLK_Divisor!=SCU_RCLK_Div1) + SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_HCLKDivisorConfig +* Description : Sets the HCLK divisor value +* Input : HCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_HCLKDivisorConfig(u32 HCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/ + if (HCLK_Divisor!=SCU_HCLK_Div1) + SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_PCLKDivisorConfig +* Description : Sets the PCLK divisor value +* Input : PCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PCLKDivisorConfig(u32 PCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/ + if (PCLK_Divisor!=SCU_PCLK_Div1) + SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphClockConfig +* Description : Enable the clock for an APB peripheral +* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for APB peripheral*/ + SCU->PCGR1 |=APBPeriph; + else + SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphClockConfig +* Description : Enable the clock for an AHB peripheral +* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...) +* -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) /*Enable clock for AHB peripheral*/ + SCU->PCGRO |=AHBPeriph; + else + SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphReset +* Description : Assert or deassert Reset on APB peripheral +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) /*APB peripheral not held in Reset*/ + SCU->PRR1 |=APBPeriph; + else + SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphReset +* Description : Assert or deassert Reset on AHB peripheral +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==DISABLE) + SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/ + else + SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/ + else + SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphIdleConfig +* Description : Enable or Disable Periph Clock during Idle mode +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/ + else + SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/ +} + +/******************************************************************************* +* Function Name : SCU_APBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/ +} + +/******************************************************************************* +* Function Name : SCU_AHBPeriphDebugConfig +* Description : Enable or Disable Periph Clock during ARM debug state +* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...) + -NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/ + else + SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/ +} +/******************************************************************************* +* Function Name : SCU_BRCLKDivisorConfig +* Description : Sets the BRCLK divisor value +* Input : BRCLK_Divisor +* Output : None +* Return : None +*******************************************************************************/ +void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor) +{ + SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/ + if (BRCLK_Divisor!=SCU_BRCLK_Div1) + SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/ +} + +/******************************************************************************* +* Function Name : SCU_TIMCLKSourceConfig +* Description : Sets the TIMx clock source +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source) +{ + if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/ + { + SCU->CLKCNTR &=0xFFFFDFFF; + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x2000; + } + else + { + SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/ + if (TIMCLK_Source == SCU_TIMCLK_EXT) + SCU->CLKCNTR |=0x4000; + } +} + +/******************************************************************************* +* Function Name : SCU_TIMPresConfig +* Description : Sets the TIMx Prescaler Value +* Input : - TIMx : SCU_TIM01 or SCU_TIM23 +* - Prescaler (16 bit value) +* Output : None +* Return : None +*******************************************************************************/ +void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler) +{ + if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/ + SCU->SCR1 = Prescaler&0xFFFF; + else + SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/ +} + +/******************************************************************************* +* Function Name : SCU_USBCLKConfig +* Description : Configures the clock source for the 48MHz USBCLK +* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT +* Output : None +* Return : None +*******************************************************************************/ +void SCU_USBCLKConfig(u32 USBCLK_Source) +{ + SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/ + if (USBCLK_Source!=SCU_USBCLK_MCLK) + SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/ +} + +/******************************************************************************* +* Function Name : SCU_PHYCLKConfig +* Description : Enable or Disable PHY clock output +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PHYCLKConfig(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/ + else + SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/ +} + +/******************************************************************************* +* Function Name : SCU_FMICLKDivisorConfig +* Description : Set the FMI clock divisor +* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor) +{ + SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/ + if (FMICLK_Divisor!=SCU_FMICLK_Div1) + SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIBCLKDivisorConfig +* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2 +* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK) +{ + SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */ + if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1) + SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */ +} + +/******************************************************************************* +* Function Name : SCU_EMIModeConfig +* Description : Configure the EMI as Multiplexed or Demultiplexed +* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIModeConfig(u32 SCU_EMIMODE) +{ + SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/ + if (SCU_EMIMODE!=SCU_EMI_MUX) + SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/ +} + +/******************************************************************************* +* Function Name : SCU_EMIALEConfig +* Description : Configure the ALE signal (length & polarity) +* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2 +* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL) +{ + /*Configure EMI ALE Length*/ + SCU->SCR0 &=SCU_EMIALE_LEN1; + if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1) + SCU->SCR0 |= SCU_EMIALE_LEN2; + + /*Configure EMI ALE POL*/ + SCU->SCR0 &=SCU_EMIALE_POLLow; + if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow) + SCU->SCR0 |= SCU_EMIALE_POLHigh; +} + +/******************************************************************************* +* Function Name : SCU_ITConfig +* Description : ENBALE or DISABLE an SCU interrupt +* Input : -SCU_IT: interrupt mask +* -NewState: ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->ITCMSK&=~SCU_IT; /*IT enable */ + else + SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/ +} + +/******************************************************************************* +* Function Name : SCU_GetFlagStatus +* Description : Returns flag status +* Input : SCU_Flag +* Output : NONE +* Return : SET or RESET +*******************************************************************************/ +FlagStatus SCU_GetFlagStatus(u32 SCU_Flag) +{ + if (SCU->SYSSTATUS&SCU_Flag) + return SET; + else return RESET; +} + +/******************************************************************************* +* Function Name : SCU_ClearFlag +* Description : Clears a SYSTATUS Flag +* Input : SCU_Flag +* Output : None +* Return : None +*******************************************************************************/ +void SCU_ClearFlag(u32 SCU_Flag) +{ + SCU->SYSSTATUS = SCU_Flag; +} +/******************************************************************************* +* Function Name : SCU_GetPLLfreqValue +* Description : Gets the current PLL frequency +* Input : None +* Output : None +* Return : PLL frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPLLFreqValue(void) +{ + u8 PLL_M; + u8 PLL_N; + u8 PLL_P; + + PLL_M = SCU->PLLCONF&0xFF; + PLL_N = (SCU->PLLCONF&0xFF00)>>8; + PLL_P = (SCU->PLLCONF&0x70000)>>16; + + if ((PLL_M>0)&&(PLL_N>0)) + return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal); + if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32); + else return (SCU_GetPLLFreqValue()); +} + +/******************************************************************************* +* Function Name : SCU_GetRCLKFreqValue +* Description : Gets the current RCLK frequency +* Input : None +* Output : None +* Return : RCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetRCLKFreqValue(void) +{ + u8 RCLK_Div; + RCLK_Div = (SCU->CLKCNTR&0x1C)>>2; + if (RCLK_Div==0x5) RCLK_Div=10; + return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetHCLKFreqValue +* Description : Gets the current PCLK frequency +* Input : None +* Output : None +* Return : HCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetHCLKFreqValue(void) +{ + u8 HCLK_Div; + HCLK_Div = (SCU->CLKCNTR&0x60)>>5; + return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_GetPCLKFreqValue +* Description : Gets the current HCLK frequency +* Input : None +* Output : None +* Return : PCLK frequency (KHz) +*******************************************************************************/ +u32 SCU_GetPCLKFreqValue(void) +{ + u8 PCLK_Div; + PCLK_Div = (SCU->CLKCNTR&0x180)>>7; + return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div); +} + +/******************************************************************************* +* Function Name : SCU_WakeUpLineConfig +* Description : Configures an External interrupt as WakeUp line +* Input : EXTint : 0 -> 31 +* Output : None +* Return : None +*******************************************************************************/ +void SCU_WakeUpLineConfig(u8 EXTint) +{ + if (EXTint < 8) + { + SCU->WKUPSEL&=~0x7; + SCU->WKUPSEL|=EXTint; + } + else if (EXTint<16) + { + SCU->WKUPSEL&=~0x38; + SCU->WKUPSEL|=(EXTint-8)<<3; + } + else if (EXTint<24) + { + SCU->WKUPSEL&=~0x1C0; + SCU->WKUPSEL|=(EXTint-16)<<6; + } + else + { + SCU->WKUPSEL&=~0xE00; + SCU->WKUPSEL|=(EXTint-24)<<9; + } +} + +/******************************************************************************* +* Function Name : SCU_SpecIntRunModeConfig +* Description : Enables or Disables the Special Run mode +* Input : newstate = ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_SpecIntRunModeConfig(FunctionalState NewState) +{ + if (NewState == ENABLE) + SCU->PWRMNG |=0x8; + else + SCU->PWRMNG &=~0x8; +} +/******************************************************************************* +* Function Name : SCU_EnterIdleMode +* Description : Enters in Idle mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterIdleMode(void) +{ + SCU->PWRMNG |=0x1; +} +/******************************************************************************* +* Function Name : SCU_EnterSleepMode +* Description : Enters in Sleep mode +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void SCU_EnterSleepMode(void) +{ + SCU->PWRMNG |=0x2; +} + +/******************************************************************************* +* Function Name : SCU_UARTIrDAConfig +* Description : Enable or Disable the Irda mode for UARTx +* Input : - UARTx :x=0,1 or 2 +* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART +* Output : None +* Return : None +*******************************************************************************/ +void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode) +{ + if (UART_IrDA_Mode == SCU_UARTMode_IrDA) + { + if (UARTx== UART0) SCU->SCR0 |=0x400; + else if (UARTx==UART1) SCU->SCR0 |=0x800; + else SCU->SCR0 |=0x1000; + } + else + { + if (UARTx== UART0) SCU->SCR0 &=~0x400; + else if (UARTx==UART1) SCU->SCR0 &=~0x800; + else SCU->SCR0 &=~0x1000; + } +} +/******************************************************************************* +* Function Name : SCU_PFQBCCmd +* Description : Enable or Disable PFQBC +* Input : NewState : ENABLE or DISABLE +* Output : None +* Return : None +*******************************************************************************/ +void SCU_PFQBCCmd(FunctionalState NewState) +{ + if (NewState==ENABLE) + SCU->SCR0 |=0x1; + else SCU->SCR0 &=~0x1; +} + +/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ diff --git a/uc_str912/scripts/flash_str9.ld b/uc_str912/scripts/flash_str9.ld new file mode 100644 index 0000000..7bd5a06 --- /dev/null +++ b/uc_str912/scripts/flash_str9.ld @@ -0,0 +1,137 @@ +/*** Linker Script File ***/ +/*** Hitex/We/2006-04-24 ***/ + +/* Memory Definitions */ +/* for STR912-Eval */ + + + +MEMORY +{ + IntCodeFlash (rx) : ORIGIN = 0x00000000, LENGTH = 512k + IntDataRAM (rw) : ORIGIN = 0x04000000, LENGTH = 96k + IntDataEth (!rx) : ORIGIN = 0x07C00000, LENGTH = 0x42F /* AHB nonbuffered Ethernet RAM */ +} + +/* this address is used in startup for initilizing stack */ +/* stack is at the end of data range */ + +PROVIDE(_top_stack_ = 0x4018000 -4); + +SECTIONS +{ + + /* first section is .text which is used for code */ + .start : { *(.startup)} >IntCodeFlash = 0 + .text : + { + /* here is the path to change and Processor-specific ISR_XXX-file */ + ./startup912.o (.text) /* Startup code */ + ./*(.text) /* remaining code */ + *(.glue_7t) + *(.glue_7) + } >IntCodeFlash =0 + + __end_of_text__ = .; + + __exidx_start = .; + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } + __exidx_end = .; + + + + . = ALIGN(4); + + /* .rodata section which is used for read-only data (constants) */ + + .rodata . : + { + *(.rodata) + } >IntCodeFlash + + . = ALIGN(4); + + _etext = . ; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + _data = . ; + __data_beg_src__ = __end_of_text__; + __data_start__ = . ; + PROVIDE (__data_start__ = .) ; + *(.data) + SORT(CONSTRUCTORS) + *(.ramfunc) + } >IntDataRAM + . = ALIGN(4); + + _edata = . ; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = . ; + __bss_start__ = . ; + *(.bss) + *(COMMON) + } >IntDataRAM + . = ALIGN(4); + __bss_end__ = . ; + __bss_end = . ; + + _end = .; + PROVIDE (end = .); + +.bss2 : + { + /* used for uninitialized data */ + + __bss2_start = . ; + __bss2_start__ = . ; + *(COMMON) + . = ALIGN(4); + __bss2_end__ = . ; + + } >IntDataRAM + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + + diff --git a/uc_str912/scripts/load.gdb b/uc_str912/scripts/load.gdb new file mode 100644 index 0000000..90cab56 --- /dev/null +++ b/uc_str912/scripts/load.gdb @@ -0,0 +1,24 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) +target remote localhost:3333 +monitor reset init +monitor halt +# 16 = 450 bytes/sec +# 32 = 870 bytes/sec +# 64 = 1 kbyte/sec c bleibt nicht stehen +# 127 = 2 kbyte/sec c bleibt nicht stehen +# 250 = 4 kbyte/sec +# 500 = 5 kbyte/sec +# 1000 = 7 kbyte/sec +# 2000 = 8 kbyte/sec +# 3000 = 8 kbyte/sec +monitor jtag_rclk 3000 +monitor str9x flash_config 0 4 2 0x00000 0x80000 +monitor flash protect 0 0 7 off +monitor flash protect_check 0 +pwd +load main.elf +file main.elf +#monitor jtag_rclk 3000 diff --git a/uc_str912/scripts/load_amontec.gdb b/uc_str912/scripts/load_amontec.gdb new file mode 100644 index 0000000..a846f82 --- /dev/null +++ b/uc_str912/scripts/load_amontec.gdb @@ -0,0 +1,20 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:3333 + + +monitor reset init +monitor halt +monitor jtag_rclk 1000 +monitor str9x flash_config 0 4 2 0x00000 0x80000 +monitor flash protect 0 0 7 off +monitor flash erase_sector 0 0 7 + + + +pwd +load main.elf +#load test_led.elf diff --git a/uc_str912/scripts/load_segger.gdb b/uc_str912/scripts/load_segger.gdb new file mode 100644 index 0000000..569b5dc --- /dev/null +++ b/uc_str912/scripts/load_segger.gdb @@ -0,0 +1,18 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:2331 + +monitor speed adaptive +monitor endian little + +monitor reset +monitor flash device = STR912 +monitor flash download = 1 +monitor halt + +pwd +load main.elf +file main.elf diff --git a/uc_str912/scripts/str912_rom.ld b/uc_str912/scripts/str912_rom.ld new file mode 100644 index 0000000..8cbb7f7 --- /dev/null +++ b/uc_str912/scripts/str912_rom.ld @@ -0,0 +1,249 @@ +/*********************************************************************************** +* Copyright 2005 Anglia Design +* This demo code and associated components are provided as is and has no warranty, +* implied or otherwise. You are free to use/modify any of the provided +* code at your own risk in your applications with the expressed limitation +* of liability (see below) +* +* LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY +* LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER +* THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* +* Author : Spencer Oliver +* Web : www.anglia-designs.com +* +***********************************************************************************/ + +/* Stack Sizes */ + + _STACKSIZE = 1024; + _STACKSIZE_IRQ = 256; + _STACKSIZE_FIQ = 0; + _STACKSIZE_SVC = 1024; + _STACKSIZE_ABT = 0; + _STACKSIZE_UND = 0; + _HEAPSIZE = 1024; + +/* Memory Definitions */ + +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + DATA (rw) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + + .text : + { + CREATE_OBJECT_SYMBOLS + KEEP(*(.vectors)) + KEEP(*(.init)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + KEEP(*(.fini)) + *(.gcc_except_table) + } >CODE =0 + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >CODE + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >CODE + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >CODE + . = ALIGN(4); + + .init_array : + { + *(.init) + *(.fini) + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >CODE + + . = ALIGN(4); + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >CODE + __exidx_end = .; + + _etext = .; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + __data_start = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + . = ALIGN(4); + *(.fastrun .fastrun.*) + } >DATA + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = .; + __bss_start__ = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >DATA + . = ALIGN(4); + __bss_end__ = .; + + _end = .; + PROVIDE(end = .); + + /* .heap section which is used for memory allocation */ + + .heap (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = MAX(__heap_start__ + _HEAPSIZE , .); + } >DATA + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + /* .stack section - user mode stack */ + + .stack (__heap_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = MAX(__stack_start__ + _STACKSIZE , .); + } >DATA + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + /* .stack_irq section */ + + .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); + } >DATA + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + /* .stack_fiq section */ + + .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); + } >DATA + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + /* .stack_svc section */ + + .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); + } >DATA + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + /* .stack_abt section */ + + .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); + } >DATA + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + /* .stack_und section */ + + .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); + } >DATA + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/uc_str912/scripts/str912fw44.ld b/uc_str912/scripts/str912fw44.ld new file mode 100644 index 0000000..feabaa4 --- /dev/null +++ b/uc_str912/scripts/str912fw44.ld @@ -0,0 +1,61 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +MEMORY +{ + flash (RX) : ORIGIN = 0x00000000, LENGTH = 512k + sram (W!RX) : ORIGIN = 0x04000000, LENGTH = 96k +} + +SECTIONS +{ + .fixed : + { + . = ALIGN(4); + _sfixed = .; + *(.text .text.*) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + } >flash + +/* .ARM.extab : { *(.ARM.extab*) } */ + + . = ALIGN(4); + + __exidx_start = .; + .ARM.exidx : { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >flash + __exidx_end = .; + + . = ALIGN(4); + + _efixed = .; + PROVIDE(etext = .); + + .relocate : AT (_efixed) + { + . = ALIGN(4); + _srelocate = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(4); + _erelocate = .; + } >sram + + .bss (NOLOAD) : { + _szero = .; + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ezero = .; + } >sram + . = ALIGN(4); + + end = .; +} diff --git a/uc_str912/scripts/str91x-configs/str91x_flash.gdb b/uc_str912/scripts/str91x-configs/str91x_flash.gdb new file mode 100644 index 0000000..2c194e2 --- /dev/null +++ b/uc_str912/scripts/str91x-configs/str91x_flash.gdb @@ -0,0 +1,6 @@ +target remote localhost:3333 +monitor reset +monitor sleep 500 +monitor poll +monitor soft_reset_halt +monitor arm7_9 force_hw_bkpts enable diff --git a/uc_str912/scripts/str91x-configs/str91x_flasherase.ocd b/uc_str912/scripts/str91x-configs/str91x_flasherase.ocd new file mode 100644 index 0000000..7b998ea --- /dev/null +++ b/uc_str912/scripts/str91x-configs/str91x_flasherase.ocd @@ -0,0 +1,6 @@ +wait_halt +str9x flash_config 4 2 0 0x80000 +flash protect 0 0 10 off +flash erase 0 0 10 +reset +shutdown diff --git a/uc_str912/scripts/str91x-configs/str91x_flashprobe.gdb b/uc_str912/scripts/str91x-configs/str91x_flashprobe.gdb new file mode 100644 index 0000000..aa528d3 --- /dev/null +++ b/uc_str912/scripts/str91x-configs/str91x_flashprobe.gdb @@ -0,0 +1,10 @@ +target remote localhost:3333 +monitor reset +monitor sleep 500 +monitor poll +monitor soft_reset_halt +monitor flash protect 0 0 10 off +monitor flash probe 0 +monitor flash info 0 +monitor reset run +monitor sleep 500 diff --git a/uc_str912/scripts/str91x-configs/str91x_flashprogram.ocd b/uc_str912/scripts/str91x-configs/str91x_flashprogram.ocd new file mode 100644 index 0000000..ad854e1 --- /dev/null +++ b/uc_str912/scripts/str91x-configs/str91x_flashprogram.ocd @@ -0,0 +1,7 @@ +wait_halt +str9x flash_config 4 2 0 0x80000 +flash protect 0 0 10 off +flash erase 0 0 10 +flash write 0 main.bin 0 +reset +shutdown diff --git a/uc_str912/scripts/str91x-configs/str91x_jtagkey-flash-erase.cfg b/uc_str912/scripts/str91x-configs/str91x_jtagkey-flash-erase.cfg new file mode 100644 index 0000000..16567d3 --- /dev/null +++ b/uc_str912/scripts/str91x-configs/str91x_jtagkey-flash-erase.cfg @@ -0,0 +1,43 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + + +#interface +interface ft2232 +ft2232_device_desc "Amontec JTAGkey A" +ft2232_layout jtagkey +#jtag_speed 1 +jtag_nsrst_delay 200 +jtag_ntrst_delay 200 + + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 8 0x1 0x1 0xfe +jtag_device 4 0x1 0xf 0xe +jtag_device 5 0x1 0x1 0x1e + + +#target configuration +daemon_startup reset + + +#target +#target arm966e +target arm966e little reset_init 1 arm966e +run_and_halt_time 0 30 + + +working_area 0 0x50000000 16384 nobackup + + +#flash bank +flash bank str9x 0x00000000 0x00080000 0 0 0 + +#Script used for FLASH erasing +target_script 0 reset C:\openocd-configs\str91x-configs\str91x_flasherase.ocd diff --git a/uc_str912/scripts/str91x-configs/str91x_jtagkey-flash-program.cfg b/uc_str912/scripts/str91x-configs/str91x_jtagkey-flash-program.cfg new file mode 100644 index 0000000..c264096 --- /dev/null +++ b/uc_str912/scripts/str91x-configs/str91x_jtagkey-flash-program.cfg @@ -0,0 +1,43 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + + +#interface +interface ft2232 +ft2232_device_desc "Amontec JTAGkey A" +ft2232_layout jtagkey +#jtag_speed 1 +jtag_nsrst_delay 200 +jtag_ntrst_delay 200 + + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 8 0x1 0x1 0xfe +jtag_device 4 0x1 0xf 0xe +jtag_device 5 0x1 0x1 0x1e + + +#target configuration +daemon_startup reset + + +#target +#target arm966e +target arm966e little reset_init 1 arm966e +run_and_halt_time 0 30 + + +working_area 0 0x50000000 16384 nobackup + + +#flash bank +flash bank str9x 0x00000000 0x00080000 0 0 0 + +#Script used for FLASH programming +target_script 0 reset C:\openocd-configs\str91x-configs\str91x_flashprogram.ocd diff --git a/uc_str912/scripts/str91x-configs/str91x_jtagkey.cfg b/uc_str912/scripts/str91x-configs/str91x_jtagkey.cfg new file mode 100644 index 0000000..6394ddc --- /dev/null +++ b/uc_str912/scripts/str91x-configs/str91x_jtagkey.cfg @@ -0,0 +1,42 @@ +#daemon configuration +telnet_port 4444 +gdb_port 3333 + + +#interface +interface ft2232 +ft2232_device_desc "Amontec JTAGkey A" +ft2232_layout jtagkey +#jtag_speed 1 + + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 8 0x1 0x1 0xfe +jtag_device 4 0x1 0xf 0xe +jtag_device 5 0x1 0x1 0x1e + + +#target configuration +daemon_startup reset + + +#target +#target arm966e +target arm966e little reset_halt 1 arm966e +run_and_halt_time 0 30 + + +working_area 0 0x50000000 16384 nobackup + + +#flash bank +flash bank str9x 0x00000000 0x00080000 0 0 0 + + +# For more information about the configuration files, take a look at: +# http://openfacts.berlios.de/index-en.phtml?title=Open On-Chip Debugger diff --git a/uc_str912/scripts/str91x-configs/str91x_ram.gdb b/uc_str912/scripts/str91x-configs/str91x_ram.gdb new file mode 100644 index 0000000..de9e060 --- /dev/null +++ b/uc_str912/scripts/str91x-configs/str91x_ram.gdb @@ -0,0 +1,6 @@ +target remote localhost:3333 +monitor reset +monitor sleep 500 +monitor poll +monitor soft_reset_halt +monitor arm7_9 sw_bkpts enable diff --git a/uc_str912/scripts/test.gdb b/uc_str912/scripts/test.gdb new file mode 100644 index 0000000..adca3a3 --- /dev/null +++ b/uc_str912/scripts/test.gdb @@ -0,0 +1,42 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) +target remote localhost:3333 +monitor reset +monitor jtag_rclk 1000 +#monitor arm7_9 dcc_downloads enable +#monitor arm7_9 fast_memory_access enable +monitor poll +monitor halt +#bbsr = FMI_BBSR +#nbsr = FMI_NBBSR +# info lt. RM0006 +# BBSIZE +# 0000 = 32 kB +# 0001 = 64 kB +# 1011 = 64 MByte +# NBBSIZE +# 0000 = 8 kB +# 0001 = 16 kB +# 1011 = 64 MByte +monitor str9x flash_config 0 4 2 0x00000 0x80000 +monitor flash protect 0 0 7 off +monitor flash protect_check 0 +monitor flash info 0 + +set remotetimeout 10000 + +pwd + +#monitor flash write_image erase ../main.elf 0 elf +#monitor flash write_image erase ../main.hex 0 ihex +#monitor flash write_image erase ../main.bin 0 bin +#monitor flash write_image erase ../test_led.elf 0 elf +#load test_led.elf +load main.elf + +#monitor sleep 200 +#monitor reset +kill +quit diff --git a/uc_str912/segger.gdb b/uc_str912/segger.gdb new file mode 100644 index 0000000..31f9031 --- /dev/null +++ b/uc_str912/segger.gdb @@ -0,0 +1,17 @@ +set complaints 1 +set output-radix 16 +set input-radix 16 +set prompt (arm-gdb) + +target remote localhost:2331 + +monitor speed adaptive +monitor endian little + +monitor reset +monitor flash device = STR912FAW44 +monitor flash breakpoints = 1 +monitor flash download = 1 +monitor halt + +pwd -- cgit v1.1